VMM.cpp@ 3068

Last change on this file since 3068 was 2981, checked in by vboxsync, 18 years ago
InnoTek -> innotek: all the headers and comments.
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1	/* $Id: VMM.cpp 2981 2007-06-01 16:01:28Z vboxsync $ */
2	/** @file
3	* VMM - The Virtual Machine Monitor Core.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 innotek GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22	//#define NO_SUPCALLR0VMM
23
24	/** @page pg_vmm VMM - The Virtual Machine Monitor
25	*
26	* !Revise this! It's already incorrect!
27	*
28	* The Virtual Machine Monitor (VMM) is the core of the virtual machine. It
29	* manages the alternate reality; controlling the virtualization, managing
30	* resources, tracking CPU state, it's resources and so on...
31	*
32	* We will split the VMM into smaller entities:
33	*
34	* - Virtual Machine Core Monitor (VMCM), which purpose it is to
35	* provide ring and world switching, that including routing
36	* interrupts to the host OS and traps to the appropriate trap
37	* handlers. It will implement an external interface for
38	* managing trap handlers.
39	*
40	* - CPU Monitor (CM), tracking the state of the CPU (in the alternate
41	* reality) and implementing external interfaces to read and change
42	* the state.
43	*
44	* - Memory Monitor (MM), which purpose it is to virtualize physical
45	* pages, segment descriptor tables, interrupt descriptor tables, task
46	* segments, and keep track of all memory providing external interfaces
47	* to access content and map pages. (Internally splitt into smaller entities!)
48	*
49	* - IO Monitor (IOM), which virtualizes in and out I/O operations. It
50	* interacts with the MM to implement memory mapped I/O. External
51	* interfaces for adding and removing I/O ranges are implemented.
52	*
53	* - External Interrupt Monitor (EIM), which purpose it is to manage
54	* interrupts generated by virtual devices. This monitor provides
55	* an interfaces for raising interrupts which is accessible at any
56	* time and from all thread.
57	* <p>
58	* A subentity of the EIM is the vitual Programmable Interrupt
59	* Controller Device (VPICD), and perhaps a virtual I/O Advanced
60	* Programmable Interrupt Controller Device (VAPICD).
61	*
62	* - Direct Memory Access Monitor (DMAM), which purpose it is to support
63	* virtual device using the DMA controller. Interfaces must be as the
64	* EIM interfaces independent and threadable.
65	* <p>
66	* A subentity of the DMAM is a virtual DMA Controller Device (VDMACD).
67	*
68	*
69	* Entities working on a higher level:
70	*
71	* - Device Manager (DM), which is a support facility for virtualized
72	* hardware. This provides generic facilities for efficient device
73	* virtualization. It will manage device attaching and detaching
74	* conversing with EIM and IOM.
75	*
76	* - Debugger Facility (DBGF) provides the basic features for
77	* debugging the alternate reality execution.
78	*
79	*
80	*
81	* @section pg_vmm_s_use_cases Use Cases
82	*
83	* @subsection pg_vmm_s_use_case_boot Bootstrap
84	*
85	* - Basic Init:
86	* - Init SUPDRV.
87	*
88	* - Init Virtual Machine Instance:
89	* - Load settings.
90	* - Check resource requirements (memory, com, stuff).
91	*
92	* - Init Host Ring 3 part:
93	* - Init Core code.
94	* - Load Pluggable Components.
95	* - Init Pluggable Components.
96	*
97	* - Init Host Ring 0 part:
98	* - Load Core (core = core components like VMM, RMI, CA, and so on) code.
99	* - Init Core code.
100	* - Load Pluggable Component code.
101	* - Init Pluggable Component code.
102	*
103	* - Allocate first chunk of memory and pin it down. This block of memory
104	* will fit the following pieces:
105	* - Virtual Machine Instance data. (Config, CPU state, VMM state, ++)
106	* (This is available from everywhere (at different addresses though)).
107	* - VMM Guest Context code.
108	* - Pluggable devices Guest Context code.
109	* - Page tables (directory and everything) for the VMM Guest
110	*
111	* - Setup Guest (Ring 0) part:
112	* - Setup initial page tables (i.e. directory all the stuff).
113	* - Load Core Guest Context code.
114	* - Load Pluggable Devices Guest Context code.
115	*
116	*
117	*/
118
119
120	/*******************************************************************************
121	* Header Files *
122	*******************************************************************************/
123	#define LOG_GROUP LOG_GROUP_VMM
124	#include <VBox/vmm.h>
125	#include <VBox/vmapi.h>
126	#include <VBox/pgm.h>
127	#include <VBox/cfgm.h>
128	#include <VBox/pdm.h>
129	#include <VBox/cpum.h>
130	#include <VBox/mm.h>
131	#include <VBox/iom.h>
132	#include <VBox/trpm.h>
133	#include <VBox/selm.h>
134	#include <VBox/em.h>
135	#include <VBox/sup.h>
136	#include <VBox/dbgf.h>
137	#include <VBox/csam.h>
138	#include <VBox/patm.h>
139	#include <VBox/rem.h>
140	#include <VBox/ssm.h>
141	#include <VBox/tm.h>
142	#include "VMMInternal.h"
143	#include "VMMSwitcher/VMMSwitcher.h"
144	#include <VBox/vm.h>
145	#include <VBox/err.h>
146	#include <VBox/param.h>
147	#include <VBox/version.h>
148	#include <VBox/x86.h>
149	#include <VBox/hwaccm.h>
150	#include <iprt/assert.h>
151	#include <iprt/alloc.h>
152	#include <iprt/asm.h>
153	#include <iprt/time.h>
154	#include <iprt/stream.h>
155	#include <iprt/string.h>
156	#include <iprt/stdarg.h>
157	#include <iprt/ctype.h>
158
159
160
161	/** The saved state version. */
162	#define VMM_SAVED_STATE_VERSION 3
163
164
165	/*******************************************************************************
166	* Internal Functions *
167	*******************************************************************************/
168	static DECLCALLBACK(int) vmmR3Save(PVM pVM, PSSMHANDLE pSSM);
169	static DECLCALLBACK(int) vmmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
170	static DECLCALLBACK(void) vmmR3YieldEMT(PVM pVM, PTMTIMER pTimer, void *pvUser);
171	static int vmmR3ServiceCallHostRequest(PVM pVM);
172
173
174	/*******************************************************************************
175	* Global Variables *
176	*******************************************************************************/
177	/** Array of switcher defininitions.
178	* The type and index shall match!
179	*/
180	static PVMMSWITCHERDEF s_apSwitchers[VMMSWITCHER_MAX] =
181	{
182	NULL, /* invalid entry */
183	#ifndef __AMD64__
184	&vmmR3Switcher32BitTo32Bit_Def,
185	&vmmR3Switcher32BitToPAE_Def,
186	NULL, //&vmmR3Switcher32BitToAMD64_Def,
187	&vmmR3SwitcherPAETo32Bit_Def,
188	&vmmR3SwitcherPAEToPAE_Def,
189	NULL, //&vmmR3SwitcherPAEToAMD64_Def,
190	# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
191	&vmmR3SwitcherAMD64ToPAE_Def,
192	# else
193	NULL, //&vmmR3SwitcherAMD64ToPAE_Def,
194	# endif
195	NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
196	#else
197	NULL, //&vmmR3Switcher32BitTo32Bit_Def,
198	NULL, //&vmmR3Switcher32BitToPAE_Def,
199	NULL, //&vmmR3Switcher32BitToAMD64_Def,
200	NULL, //&vmmR3SwitcherPAETo32Bit_Def,
201	NULL, //&vmmR3SwitcherPAEToPAE_Def,
202	NULL, //&vmmR3SwitcherPAEToAMD64_Def,
203	&vmmR3SwitcherAMD64ToPAE_Def,
204	NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
205	#endif
206	};
207
208
209
210	/**
211	* Initiates the core code.
212	*
213	* This is core per VM code which might need fixups and/or for ease of use
214	* are put on linear contiguous backing.
215	*
216	* @returns VBox status code.
217	* @param pVM Pointer to VM structure.
218	*/
219	static int vmmR3InitCoreCode(PVM pVM)
220	{
221	/*
222	* Calc the size.
223	*/
224	unsigned cbCoreCode = 0;
225	for (unsigned iSwitcher = 0; iSwitcher < ELEMENTS(s_apSwitchers); iSwitcher++)
226	{
227	pVM->vmm.s.aoffSwitchers[iSwitcher] = cbCoreCode;
228	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
229	if (pSwitcher)
230	{
231	AssertRelease((unsigned)pSwitcher->enmType == iSwitcher);
232	cbCoreCode += RT_ALIGN_32(pSwitcher->cbCode + 1, 32);
233	}
234	}
235
236	/*
237	* Allocate continguous pages for switchers and deal with
238	* conflicts in the intermediate mapping of the code.
239	*/
240	pVM->vmm.s.cbCoreCode = RT_ALIGN_32(cbCoreCode, PAGE_SIZE);
241	pVM->vmm.s.pvHCCoreCodeR3 = SUPContAlloc2(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvHCCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
242	int rc = VERR_NO_MEMORY;
243	if (pVM->vmm.s.pvHCCoreCodeR3)
244	{
245	rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvHCCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
246	if (rc == VERR_PGM_MAPPINGS_FIX_CONFLICT)
247	{
248	/* try more allocations. */
249	struct
250	{
251	RTR0PTR pvR0;
252	void *pvR3;
253	RTHCPHYS HCPhys;
254	RTUINT cb;
255	} aBadTries[16];
256	unsigned i = 0;
257	do
258	{
259	aBadTries[i].pvR3 = pVM->vmm.s.pvHCCoreCodeR3;
260	aBadTries[i].pvR0 = pVM->vmm.s.pvHCCoreCodeR0;
261	aBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
262	i++;
263	pVM->vmm.s.pvHCCoreCodeR0 = NIL_RTR0PTR;
264	pVM->vmm.s.HCPhysCoreCode = NIL_RTHCPHYS;
265	pVM->vmm.s.pvHCCoreCodeR3 = SUPContAlloc2(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvHCCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
266	if (!pVM->vmm.s.pvHCCoreCodeR3)
267	break;
268	rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvHCCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
269	} while ( rc == VERR_PGM_MAPPINGS_FIX_CONFLICT
270	&& i < ELEMENTS(aBadTries) - 1);
271
272	/* cleanup */
273	if (VBOX_FAILURE(rc))
274	{
275	aBadTries[i].pvR3 = pVM->vmm.s.pvHCCoreCodeR3;
276	aBadTries[i].pvR0 = pVM->vmm.s.pvHCCoreCodeR0;
277	aBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
278	aBadTries[i].cb = pVM->vmm.s.cbCoreCode;
279	i++;
280	LogRel(("Failed to allocated and map core code: rc=%Vrc\n", rc));
281	}
282	while (i-- > 0)
283	{
284	LogRel(("Core code alloc attempt #%d: pvR3=%p pvR0=%p HCPhys=%VHp\n",
285	i, aBadTries[i].pvR3, aBadTries[i].pvR0, aBadTries[i].HCPhys));
286	SUPContFree(aBadTries[i].pvR3, aBadTries[i].cb >> PAGE_SHIFT);
287	}
288	}
289	}
290	if (VBOX_SUCCESS(rc))
291	{
292	/*
293	* copy the code.
294	*/
295	for (unsigned iSwitcher = 0; iSwitcher < ELEMENTS(s_apSwitchers); iSwitcher++)
296	{
297	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
298	if (pSwitcher)
299	memcpy((uint8_t *)pVM->vmm.s.pvHCCoreCodeR3 + pVM->vmm.s.aoffSwitchers[iSwitcher],
300	pSwitcher->pvCode, pSwitcher->cbCode);
301	}
302
303	/*
304	* Map the code into the GC address space.
305	*/
306	rc = MMR3HyperMapHCPhys(pVM, pVM->vmm.s.pvHCCoreCodeR3, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, "Core Code", &pVM->vmm.s.pvGCCoreCode);
307	if (VBOX_SUCCESS(rc))
308	{
309	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
310	LogRel(("CoreCode: R3=%VHv R0=%VHv GC=%VGv Phys=%VHp cb=%#x\n",
311	pVM->vmm.s.pvHCCoreCodeR3, pVM->vmm.s.pvHCCoreCodeR0, pVM->vmm.s.pvGCCoreCode, pVM->vmm.s.HCPhysCoreCode, pVM->vmm.s.cbCoreCode));
312
313	/*
314	* Finally, PGM probably have selected a switcher already but we need
315	* to do get the addresses so we'll reselect it.
316	* This may legally fail so, we're ignoring the rc.
317	*/
318	VMMR3SelectSwitcher(pVM, pVM->vmm.s.enmSwitcher);
319	return rc;
320	}
321
322	/* shit */
323	AssertMsgFailed(("PGMR3Map(,%VGv, %VGp, %#x, 0) failed with rc=%Vrc\n", pVM->vmm.s.pvGCCoreCode, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, rc));
324	SUPContFree(pVM->vmm.s.pvHCCoreCodeR3, pVM->vmm.s.cbCoreCode >> PAGE_SHIFT);
325	}
326	else
327	VMSetError(pVM, rc, RT_SRC_POS,
328	N_("Failed to allocate %d bytes of contiguous memory for the world switcher code."),
329	cbCoreCode);
330
331	pVM->vmm.s.pvHCCoreCodeR3 = NULL;
332	pVM->vmm.s.pvHCCoreCodeR0 = NIL_RTR0PTR;
333	pVM->vmm.s.pvGCCoreCode = 0;
334	return rc;
335	}
336
337
338	/**
339	* Initializes the VMM.
340	*
341	* @returns VBox status code.
342	* @param pVM The VM to operate on.
343	*/
344	VMMR3DECL(int) VMMR3Init(PVM pVM)
345	{
346	LogFlow(("VMMR3Init\n"));
347
348	/*
349	* Assert alignment, sizes and order.
350	*/
351	AssertMsg(pVM->vmm.s.offVM == 0, ("Already initialized!\n"));
352	AssertMsg(sizeof(pVM->vmm.padding) >= sizeof(pVM->vmm.s),
353	("pVM->vmm.padding is too small! vmm.padding %d while vmm.s is %d\n",
354	sizeof(pVM->vmm.padding), sizeof(pVM->vmm.s)));
355
356	/*
357	* Init basic VM VMM members.
358	*/
359	pVM->vmm.s.offVM = RT_OFFSETOF(VM, vmm);
360	int rc = CFGMR3QueryU32(CFGMR3GetRoot(pVM), "YieldEMTInterval", &pVM->vmm.s.cYieldEveryMillies);
361	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
362	pVM->vmm.s.cYieldEveryMillies = 23; /* Value arrived at after experimenting with the grub boot prompt. */
363	//pVM->vmm.s.cYieldEveryMillies = 8; //debugging
364	else
365	AssertMsgRCReturn(rc, ("Configuration error. Failed to query \"YieldEMTInterval\", rc=%Vrc\n", rc), rc);
366
367	/* GC switchers are enabled by default. Turned off by HWACCM. */
368	pVM->vmm.s.fSwitcherDisabled = false;
369
370	/*
371	* Register the saved state data unit.
372	*/
373	rc = SSMR3RegisterInternal(pVM, "vmm", 1, VMM_SAVED_STATE_VERSION, VMM_STACK_SIZE + sizeof(RTGCPTR),
374	NULL, vmmR3Save, NULL,
375	NULL, vmmR3Load, NULL);
376	if (VBOX_FAILURE(rc))
377	return rc;
378
379	#ifdef VBOX_WITHOUT_IDT_PATCHING
380	/*
381	* Register the Ring-0 VM handle with the session for fast ioctl calls.
382	*/
383	rc = SUPSetVMForFastIOCtl(pVM->pVMR0);
384	if (VBOX_FAILURE(rc))
385	return rc;
386	#endif
387
388	/*
389	* Init core code.
390	*/
391	rc = vmmR3InitCoreCode(pVM);
392	if (VBOX_SUCCESS(rc))
393	{
394	/*
395	* Allocate & init VMM GC stack.
396	* The stack pages are also used by the VMM R0 when VMMR0CallHost is invoked.
397	* (The page protection is modifed during R3 init completion.)
398	*/
399	#ifdef VBOX_STRICT_VMM_STACK
400	rc = MMHyperAlloc(pVM, VMM_STACK_SIZE + PAGE_SIZE + PAGE_SIZE, PAGE_SIZE, MM_TAG_VMM, (void **)&pVM->vmm.s.pbHCStack);
401	#else
402	rc = MMHyperAlloc(pVM, VMM_STACK_SIZE, PAGE_SIZE, MM_TAG_VMM, (void **)&pVM->vmm.s.pbHCStack);
403	#endif
404	if (VBOX_SUCCESS(rc))
405	{
406	/* Set HC and GC stack pointers to top of stack. */
407	pVM->vmm.s.CallHostR0JmpBuf.pvSavedStack = (RTR0PTR)pVM->vmm.s.pbHCStack;
408	pVM->vmm.s.pbGCStack = MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack);
409	pVM->vmm.s.pbGCStackBottom = pVM->vmm.s.pbGCStack + VMM_STACK_SIZE;
410	AssertRelease(pVM->vmm.s.pbGCStack);
411
412	/* Set hypervisor eip. */
413	CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStack);
414
415	/*
416	* Allocate GC & R0 Logger instances (they are finalized in the relocator).
417	*/
418	#ifdef LOG_ENABLED
419	PRTLOGGER pLogger = RTLogDefaultInstance();
420	if (pLogger)
421	{
422	pVM->vmm.s.cbLoggerGC = RT_OFFSETOF(RTLOGGERGC, afGroups[pLogger->cGroups]);
423	rc = MMHyperAlloc(pVM, pVM->vmm.s.cbLoggerGC, 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pLoggerHC);
424	if (VBOX_SUCCESS(rc))
425	{
426	pVM->vmm.s.pLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pLoggerHC);
427
428	/*
429	* Ring-0 logging isn't 100% safe yet (thread id reuse / process exit cleanup), so
430	* you have to sign up here by adding your defined(DEBUG_<userid>) to the #if.
431	*
432	* If you want to log in non-debug modes, you'll have to remember to change SUPDRvShared.c
433	* to not stub all the log functions.
434	*/
435	# ifdef DEBUG_sandervl
436	rc = MMHyperAlloc(pVM, RT_OFFSETOF(VMMR0LOGGER, Logger.afGroups[pLogger->cGroups]),
437	0, MM_TAG_VMM, (void **)&pVM->vmm.s.pR0Logger);
438	if (VBOX_SUCCESS(rc))
439	{
440	pVM->vmm.s.pR0Logger->pVM = pVM;
441	//pVM->vmm.s.pR0Logger->fCreated = false;
442	pVM->vmm.s.pR0Logger->cbLogger = RT_OFFSETOF(RTLOGGER, afGroups[pLogger->cGroups]);
443	}
444	# endif
445	}
446	}
447	#endif /* LOG_ENABLED */
448
449	#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
450	/*
451	* Allocate GC Release Logger instances (finalized in the relocator).
452	*/
453	if (VBOX_SUCCESS(rc))
454	{
455	PRTLOGGER pRelLogger = RTLogRelDefaultInstance();
456	if (pRelLogger)
457	{
458	pVM->vmm.s.cbRelLoggerGC = RT_OFFSETOF(RTLOGGERGC, afGroups[pRelLogger->cGroups]);
459	rc = MMHyperAlloc(pVM, pVM->vmm.s.cbRelLoggerGC, 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pRelLoggerHC);
460	if (VBOX_SUCCESS(rc))
461	pVM->vmm.s.pRelLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pRelLoggerHC);
462	}
463	}
464	#endif /* VBOX_WITH_GC_AND_R0_RELEASE_LOG */
465
466	#ifdef VBOX_WITH_NMI
467	/*
468	* Allocate mapping for the host APIC.
469	*/
470	if (VBOX_SUCCESS(rc))
471	{
472	rc = MMR3HyperReserve(pVM, PAGE_SIZE, "Host APIC", &pVM->vmm.s.GCPtrApicBase);
473	AssertRC(rc);
474	}
475	#endif
476	if (VBOX_SUCCESS(rc))
477	{
478	rc = RTCritSectInit(&pVM->vmm.s.CritSectVMLock);
479	if (VBOX_SUCCESS(rc))
480	{
481	/*
482	* Statistics.
483	*/
484	STAM_REG(pVM, &pVM->vmm.s.StatRunGC, STAMTYPE_COUNTER, "/VMM/RunGC", STAMUNIT_OCCURENCES, "Number of context switches.");
485	STAM_REG(pVM, &pVM->vmm.s.StatGCRetNormal, STAMTYPE_COUNTER, "/VMM/GCRet/Normal", STAMUNIT_OCCURENCES, "Number of VINF_SUCCESS returns.");
486	STAM_REG(pVM, &pVM->vmm.s.StatGCRetInterrupt, STAMTYPE_COUNTER, "/VMM/GCRet/Interrupt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT returns.");
487	STAM_REG(pVM, &pVM->vmm.s.StatGCRetInterruptHyper, STAMTYPE_COUNTER, "/VMM/GCRet/InterruptHyper", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT_HYPER returns.");
488	STAM_REG(pVM, &pVM->vmm.s.StatGCRetGuestTrap, STAMTYPE_COUNTER, "/VMM/GCRet/GuestTrap", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_GUEST_TRAP returns.");
489	STAM_REG(pVM, &pVM->vmm.s.StatGCRetRingSwitch, STAMTYPE_COUNTER, "/VMM/GCRet/RingSwitch", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_RING_SWITCH returns.");
490	STAM_REG(pVM, &pVM->vmm.s.StatGCRetRingSwitchInt, STAMTYPE_COUNTER, "/VMM/GCRet/RingSwitchInt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_RING_SWITCH_INT returns.");
491	STAM_REG(pVM, &pVM->vmm.s.StatGCRetExceptionPrivilege, STAMTYPE_COUNTER, "/VMM/GCRet/ExceptionPrivilege", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_EXCEPTION_PRIVILEGED returns.");
492	STAM_REG(pVM, &pVM->vmm.s.StatGCRetStaleSelector, STAMTYPE_COUNTER, "/VMM/GCRet/StaleSelector", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_STALE_SELECTOR returns.");
493	STAM_REG(pVM, &pVM->vmm.s.StatGCRetIRETTrap, STAMTYPE_COUNTER, "/VMM/GCRet/IRETTrap", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_IRET_TRAP returns.");
494	STAM_REG(pVM, &pVM->vmm.s.StatGCRetEmulate, STAMTYPE_COUNTER, "/VMM/GCRet/Emulate", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION returns.");
495	STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchEmulate, STAMTYPE_COUNTER, "/VMM/GCRet/PatchEmulate", STAMUNIT_OCCURENCES, "Number of VINF_PATCH_EMULATE_INSTR returns.");
496	STAM_REG(pVM, &pVM->vmm.s.StatGCRetIORead, STAMTYPE_COUNTER, "/VMM/GCRet/IORead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_IOPORT_READ returns.");
497	STAM_REG(pVM, &pVM->vmm.s.StatGCRetIOWrite, STAMTYPE_COUNTER, "/VMM/GCRet/IOWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_IOPORT_WRITE returns.");
498	STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIORead, STAMTYPE_COUNTER, "/VMM/GCRet/MMIORead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_READ returns.");
499	STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOWrite, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_WRITE returns.");
500	STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOReadWrite, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOReadWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_READ_WRITE returns.");
501	STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOPatchRead, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOPatchRead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_PATCH_READ returns.");
502	STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOPatchWrite, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOPatchWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_PATCH_WRITE returns.");
503	STAM_REG(pVM, &pVM->vmm.s.StatGCRetLDTFault, STAMTYPE_COUNTER, "/VMM/GCRet/LDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_GDT_FAULT returns.");
504	STAM_REG(pVM, &pVM->vmm.s.StatGCRetGDTFault, STAMTYPE_COUNTER, "/VMM/GCRet/GDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_LDT_FAULT returns.");
505	STAM_REG(pVM, &pVM->vmm.s.StatGCRetIDTFault, STAMTYPE_COUNTER, "/VMM/GCRet/IDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_IDT_FAULT returns.");
506	STAM_REG(pVM, &pVM->vmm.s.StatGCRetTSSFault, STAMTYPE_COUNTER, "/VMM/GCRet/TSSFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_TSS_FAULT returns.");
507	STAM_REG(pVM, &pVM->vmm.s.StatGCRetPDFault, STAMTYPE_COUNTER, "/VMM/GCRet/PDFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_PD_FAULT returns.");
508	STAM_REG(pVM, &pVM->vmm.s.StatGCRetCSAMTask, STAMTYPE_COUNTER, "/VMM/GCRet/CSAMTask", STAMUNIT_OCCURENCES, "Number of VINF_CSAM_PENDING_ACTION returns.");
509	STAM_REG(pVM, &pVM->vmm.s.StatGCRetSyncCR3, STAMTYPE_COUNTER, "/VMM/GCRet/SyncCR", STAMUNIT_OCCURENCES, "Number of VINF_PGM_SYNC_CR3 returns.");
510	STAM_REG(pVM, &pVM->vmm.s.StatGCRetMisc, STAMTYPE_COUNTER, "/VMM/GCRet/Misc", STAMUNIT_OCCURENCES, "Number of misc returns.");
511	STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchInt3, STAMTYPE_COUNTER, "/VMM/GCRet/PatchInt3", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_INT3 returns.");
512	STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchPF, STAMTYPE_COUNTER, "/VMM/GCRet/PatchPF", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_TRAP_PF returns.");
513	STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchGP, STAMTYPE_COUNTER, "/VMM/GCRet/PatchGP", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_TRAP_GP returns.");
514	STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchIretIRQ, STAMTYPE_COUNTER, "/VMM/GCRet/PatchIret", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PENDING_IRQ_AFTER_IRET returns.");
515	STAM_REG(pVM, &pVM->vmm.s.StatGCRetPageOverflow, STAMTYPE_COUNTER, "/VMM/GCRet/InvlpgOverflow", STAMUNIT_OCCURENCES, "Number of VERR_REM_FLUSHED_PAGES_OVERFLOW returns.");
516	STAM_REG(pVM, &pVM->vmm.s.StatGCRetRescheduleREM, STAMTYPE_COUNTER, "/VMM/GCRet/ScheduleREM", STAMUNIT_OCCURENCES, "Number of VINF_EM_RESCHEDULE_REM returns.");
517	STAM_REG(pVM, &pVM->vmm.s.StatGCRetToR3, STAMTYPE_COUNTER, "/VMM/GCRet/ToR3", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TO_R3 returns.");
518	STAM_REG(pVM, &pVM->vmm.s.StatGCRetTimerPending, STAMTYPE_COUNTER, "/VMM/GCRet/TimerPending", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TIMER_PENDING returns.");
519	STAM_REG(pVM, &pVM->vmm.s.StatGCRetInterruptPending, STAMTYPE_COUNTER, "/VMM/GCRet/InterruptPending", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT_PENDING returns.");
520	STAM_REG(pVM, &pVM->vmm.s.StatGCRetCallHost, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/Misc", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
521	STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMGrowRAM, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/GrowRAM", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
522	STAM_REG(pVM, &pVM->vmm.s.StatGCRetPDMLock, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/PDMLock", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
523	STAM_REG(pVM, &pVM->vmm.s.StatGCRetLogFlush, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/LogFlush", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
524	STAM_REG(pVM, &pVM->vmm.s.StatGCRetPDMQueueFlush, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/QueueFlush", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
525	STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMPoolGrow, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/PGMPoolGrow",STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
526	STAM_REG(pVM, &pVM->vmm.s.StatGCRetRemReplay, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/REMReplay", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
527	STAM_REG(pVM, &pVM->vmm.s.StatGCRetVMSetError, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/VMSetError", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
528	STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMLock, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/PGMLock", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
529	STAM_REG(pVM, &pVM->vmm.s.StatGCRetPATMDuplicateFn, STAMTYPE_COUNTER, "/VMM/GCRet/PATMDuplicateFn", STAMUNIT_OCCURENCES, "Number of VINF_PATM_DUPLICATE_FUNCTION returns.");
530	STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMChangeMode, STAMTYPE_COUNTER, "/VMM/GCRet/PGMChangeMode", STAMUNIT_OCCURENCES, "Number of VINF_PGM_CHANGE_MODE returns.");
531	STAM_REG(pVM, &pVM->vmm.s.StatGCRetEmulHlt, STAMTYPE_COUNTER, "/VMM/GCRet/EmulHlt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_EMULATE_INSTR_HLT returns.");
532	STAM_REG(pVM, &pVM->vmm.s.StatGCRetPendingRequest, STAMTYPE_COUNTER, "/VMM/GCRet/PendingRequest", STAMUNIT_OCCURENCES, "Number of VINF_EM_PENDING_REQUEST returns.");
533
534	return VINF_SUCCESS;
535	}
536	AssertRC(rc);
537	}
538	}
539	/** @todo: Need failure cleanup. */
540
541	//more todo in here?
542	//if (VBOX_SUCCESS(rc))
543	//{
544	//}
545	//int rc2 = vmmR3TermCoreCode(pVM);
546	//AssertRC(rc2));
547	}
548
549	return rc;
550	}
551
552
553	/**
554	* Ring-3 init finalizing.
555	*
556	* @returns VBox status code.
557	* @param pVM The VM handle.
558	*/
559	VMMR3DECL(int) VMMR3InitFinalize(PVM pVM)
560	{
561	#ifdef VBOX_STRICT_VMM_STACK
562	/*
563	* Two inaccessible pages at each sides of the stack to catch over/under-flows.
564	*/
565	memset(pVM->vmm.s.pbHCStack - PAGE_SIZE, 0xcc, PAGE_SIZE);
566	PGMMapSetPage(pVM, MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack - PAGE_SIZE), PAGE_SIZE, 0);
567	RTMemProtect(pVM->vmm.s.pbHCStack - PAGE_SIZE, PAGE_SIZE, RTMEM_PROT_NONE);
568
569	memset(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE, 0xcc, PAGE_SIZE);
570	PGMMapSetPage(pVM, MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack + VMM_STACK_SIZE), PAGE_SIZE, 0);
571	RTMemProtect(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE, PAGE_SIZE, RTMEM_PROT_NONE);
572	#endif
573
574	/*
575	* Set page attributes to r/w for stack pages.
576	*/
577	int rc = PGMMapSetPage(pVM, pVM->vmm.s.pbGCStack, VMM_STACK_SIZE, X86_PTE_P \| X86_PTE_A \| X86_PTE_D \| X86_PTE_RW);
578	AssertRC(rc);
579	if (VBOX_SUCCESS(rc))
580	{
581	/*
582	* Create the EMT yield timer.
583	*/
584	rc = TMR3TimerCreateInternal(pVM, TMCLOCK_REAL, vmmR3YieldEMT, NULL, "EMT Yielder", &pVM->vmm.s.pYieldTimer);
585	if (VBOX_SUCCESS(rc))
586	rc = TMTimerSetMillies(pVM->vmm.s.pYieldTimer, pVM->vmm.s.cYieldEveryMillies);
587	}
588	#ifdef VBOX_WITH_NMI
589	/*
590	* Map the host APIC into GC - This may be host os specific!
591	*/
592	if (VBOX_SUCCESS(rc))
593	rc = PGMMap(pVM, pVM->vmm.s.GCPtrApicBase, 0xfee00000, PAGE_SIZE,
594	X86_PTE_P \| X86_PTE_RW \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_A \| X86_PTE_D);
595	#endif
596	return rc;
597	}
598
599
600	/**
601	* Initializes the R0 VMM.
602	*
603	* @returns VBox status code.
604	* @param pVM The VM to operate on.
605	*/
606	VMMR3DECL(int) VMMR3InitR0(PVM pVM)
607	{
608	int rc;
609
610	/*
611	* Initialize the ring-0 logger if we haven't done so yet.
612	*/
613	if ( pVM->vmm.s.pR0Logger
614	&& !pVM->vmm.s.pR0Logger->fCreated)
615	{
616	rc = VMMR3UpdateLoggers(pVM);
617	if (VBOX_FAILURE(rc))
618	return rc;
619	}
620
621	/*
622	* Call Ring-0 entry with init code.
623	*/
624	for (;;)
625	{
626	#ifdef NO_SUPCALLR0VMM
627	//rc = VERR_GENERAL_FAILURE;
628	rc = VINF_SUCCESS;
629	#else
630	rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_VMMR0_INIT, (void *)VBOX_VERSION);
631	#endif
632	if ( pVM->vmm.s.pR0Logger
633	&& pVM->vmm.s.pR0Logger->Logger.offScratch > 0)
634	RTLogFlushToLogger(&pVM->vmm.s.pR0Logger->Logger, NULL);
635	if (rc != VINF_VMM_CALL_HOST)
636	break;
637	rc = vmmR3ServiceCallHostRequest(pVM);
638	if (VBOX_FAILURE(rc) \|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
639	break;
640	break; // remove this when we do setjmp for all ring-0 stuff.
641	}
642
643	if (VBOX_FAILURE(rc) \|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
644	{
645	LogRel(("R0 init failed, rc=%Vra\n", rc));
646	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
647	rc = VERR_INTERNAL_ERROR;
648	}
649	return rc;
650	}
651
652
653	/**
654	* Initializes the GC VMM.
655	*
656	* @returns VBox status code.
657	* @param pVM The VM to operate on.
658	*/
659	VMMR3DECL(int) VMMR3InitGC(PVM pVM)
660	{
661	/* In VMX mode, there's no need to init GC. */
662	if (pVM->vmm.s.fSwitcherDisabled)
663	return VINF_SUCCESS;
664
665	/*
666	* Call VMMGCInit():
667	* -# resolve the address.
668	* -# setup stackframe and EIP to use the trampoline.
669	* -# do a generic hypervisor call.
670	*/
671	RTGCPTR GCPtrEP;
672	int rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &GCPtrEP);
673	if (VBOX_SUCCESS(rc))
674	{
675	CPUMHyperSetCtxCore(pVM, NULL);
676	CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom); /* Clear the stack. */
677	CPUMPushHyper(pVM, VBOX_VERSION); /* Param 2: Version argument. */
678	CPUMPushHyper(pVM, VMMGC_DO_VMMGC_INIT); /* Param 1: Operation. */
679	CPUMPushHyper(pVM, pVM->pVMGC); /* Param 0: pVM */
680	CPUMPushHyper(pVM, 3 * sizeof(RTGCPTR)); /* trampoline param: stacksize. */
681	CPUMPushHyper(pVM, GCPtrEP); /* Call EIP. */
682	CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnGCCallTrampoline);
683
684	for (;;)
685	{
686	#ifdef NO_SUPCALLR0VMM
687	//rc = VERR_GENERAL_FAILURE;
688	rc = VINF_SUCCESS;
689	#else
690	rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_CALL_HYPERVISOR, NULL);
691	#endif
692	#ifdef LOG_ENABLED
693	PRTLOGGERGC pLogger = pVM->vmm.s.pLoggerHC;
694	if ( pLogger
695	&& pLogger->offScratch > 0)
696	RTLogFlushGC(NULL, pLogger);
697	#endif
698	#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
699	PRTLOGGERGC pRelLogger = pVM->vmm.s.pRelLoggerHC;
700	if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
701	RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
702	#endif
703	if (rc != VINF_VMM_CALL_HOST)
704	break;
705	rc = vmmR3ServiceCallHostRequest(pVM);
706	if (VBOX_FAILURE(rc) \|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
707	break;
708	}
709
710	if (VBOX_FAILURE(rc) \|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
711	{
712	VMMR3FatalDump(pVM, rc);
713	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
714	rc = VERR_INTERNAL_ERROR;
715	}
716	AssertRC(rc);
717	}
718	return rc;
719	}
720
721
722	/**
723	* Terminate the VMM bits.
724	*
725	* @returns VINF_SUCCESS.
726	* @param pVM The VM handle.
727	*/
728	VMMR3DECL(int) VMMR3Term(PVM pVM)
729	{
730	/** @todo must call ring-0 so the logger thread instance can be properly removed. */
731
732	#ifdef VBOX_STRICT_VMM_STACK
733	/*
734	* Make the two stack guard pages present again.
735	*/
736	RTMemProtect(pVM->vmm.s.pbHCStack - PAGE_SIZE, PAGE_SIZE, RTMEM_PROT_READ \| RTMEM_PROT_WRITE);
737	RTMemProtect(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE, PAGE_SIZE, RTMEM_PROT_READ \| RTMEM_PROT_WRITE);
738	#endif
739	return VINF_SUCCESS;
740	}
741
742
743	/**
744	* Applies relocations to data and code managed by this
745	* component. This function will be called at init and
746	* whenever the VMM need to relocate it self inside the GC.
747	*
748	* The VMM will need to apply relocations to the core code.
749	*
750	* @param pVM The VM handle.
751	* @param offDelta The relocation delta.
752	*/
753	VMMR3DECL(void) VMMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
754	{
755	LogFlow(("VMMR3Relocate: offDelta=%VGv\n", offDelta));
756
757	/*
758	* Recalc the GC address.
759	*/
760	pVM->vmm.s.pvGCCoreCode = MMHyperHC2GC(pVM, pVM->vmm.s.pvHCCoreCodeR3);
761
762	/*
763	* The stack.
764	*/
765	CPUMSetHyperESP(pVM, CPUMGetHyperESP(pVM) + offDelta);
766	pVM->vmm.s.pbGCStack = MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack);
767	pVM->vmm.s.pbGCStackBottom = pVM->vmm.s.pbGCStack + VMM_STACK_SIZE;
768
769	/*
770	* All the switchers.
771	*/
772	for (unsigned iSwitcher = 0; iSwitcher < ELEMENTS(s_apSwitchers); iSwitcher++)
773	{
774	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
775	if (pSwitcher && pSwitcher->pfnRelocate)
776	{
777	unsigned off = pVM->vmm.s.aoffSwitchers[iSwitcher];
778	pSwitcher->pfnRelocate(pVM,
779	pSwitcher,
780	(uint8_t *)pVM->vmm.s.pvHCCoreCodeR0 + off,
781	(uint8_t *)pVM->vmm.s.pvHCCoreCodeR3 + off,
782	pVM->vmm.s.pvGCCoreCode + off,
783	pVM->vmm.s.HCPhysCoreCode + off);
784	}
785	}
786
787	/*
788	* Recalc the GC address for the current switcher.
789	*/
790	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[pVM->vmm.s.enmSwitcher];
791	RTGCPTR GCPtr = pVM->vmm.s.pvGCCoreCode + pVM->vmm.s.aoffSwitchers[pVM->vmm.s.enmSwitcher];
792	pVM->vmm.s.pfnGCGuestToHost = GCPtr + pSwitcher->offGCGuestToHost;
793	pVM->vmm.s.pfnGCCallTrampoline = GCPtr + pSwitcher->offGCCallTrampoline;
794	pVM->pfnVMMGCGuestToHostAsm = GCPtr + pSwitcher->offGCGuestToHostAsm;
795	pVM->pfnVMMGCGuestToHostAsmHyperCtx = GCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
796	pVM->pfnVMMGCGuestToHostAsmGuestCtx = GCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
797
798	/*
799	* Get other GC entry points.
800	*/
801	int rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "CPUMGCResumeGuest", &pVM->vmm.s.pfnCPUMGCResumeGuest);
802	AssertReleaseMsgRC(rc, ("CPUMGCResumeGuest not found! rc=%Vra\n", rc));
803
804	rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "CPUMGCResumeGuestV86", &pVM->vmm.s.pfnCPUMGCResumeGuestV86);
805	AssertReleaseMsgRC(rc, ("CPUMGCResumeGuestV86 not found! rc=%Vra\n", rc));
806
807	/*
808	* Update the logger.
809	*/
810	VMMR3UpdateLoggers(pVM);
811	}
812
813
814	/**
815	* Updates the settings for the GC and R0 loggers.
816	*
817	* @returns VBox status code.
818	* @param pVM The VM handle.
819	*/
820	VMMR3DECL(int) VMMR3UpdateLoggers(PVM pVM)
821	{
822	/*
823	* Simply clone the logger instance (for GC).
824	*/
825	int rc = VINF_SUCCESS;
826	RTGCPTR GCPtrLoggerFlush = 0;
827
828	if (pVM->vmm.s.pLoggerHC
829	#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
830	\|\| pVM->vmm.s.pRelLoggerHC
831	#endif
832	)
833	{
834	rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCLoggerFlush", &GCPtrLoggerFlush);
835	AssertReleaseMsgRC(rc, ("vmmGCLoggerFlush not found! rc=%Vra\n", rc));
836	}
837
838	if (pVM->vmm.s.pLoggerHC)
839	{
840	RTGCPTR GCPtrLoggerWrapper = 0;
841	rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCLoggerWrapper", &GCPtrLoggerWrapper);
842	AssertReleaseMsgRC(rc, ("vmmGCLoggerWrapper not found! rc=%Vra\n", rc));
843	pVM->vmm.s.pLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pLoggerHC);
844	rc = RTLogCloneGC(NULL /* default */, pVM->vmm.s.pLoggerHC, pVM->vmm.s.cbLoggerGC,
845	GCPtrLoggerWrapper, GCPtrLoggerFlush, RTLOGFLAGS_BUFFERED);
846	AssertReleaseMsgRC(rc, ("RTLogCloneGC failed! rc=%Vra\n", rc));
847	}
848
849	#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
850	if (pVM->vmm.s.pRelLoggerHC)
851	{
852	RTGCPTR GCPtrLoggerWrapper = 0;
853	rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCRelLoggerWrapper", &GCPtrLoggerWrapper);
854	AssertReleaseMsgRC(rc, ("vmmGCRelLoggerWrapper not found! rc=%Vra\n", rc));
855	pVM->vmm.s.pRelLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pRelLoggerHC);
856	rc = RTLogCloneGC(RTLogRelDefaultInstance(), pVM->vmm.s.pRelLoggerHC, pVM->vmm.s.cbRelLoggerGC,
857	GCPtrLoggerWrapper, GCPtrLoggerFlush, RTLOGFLAGS_BUFFERED);
858	AssertReleaseMsgRC(rc, ("RTLogCloneGC failed! rc=%Vra\n", rc));
859	}
860	#endif /* VBOX_WITH_GC_AND_R0_RELEASE_LOG */
861
862	/*
863	* For the ring-0 EMT logger, we use a per-thread logger
864	* instance in ring-0. Only initialize it once.
865	*/
866	PVMMR0LOGGER pR0Logger = pVM->vmm.s.pR0Logger;
867	if (pR0Logger)
868	{
869	if (!pR0Logger->fCreated)
870	{
871	RTR0PTR pfnLoggerWrapper = NIL_RTR0PTR;
872	rc = PDMR3GetSymbolR0(pVM, VMMR0_MAIN_MODULE_NAME, "vmmR0LoggerWrapper", &pfnLoggerWrapper);
873	AssertReleaseMsgRCReturn(rc, ("VMMLoggerWrapper not found! rc=%Vra\n", rc), rc);
874
875	RTR0PTR pfnLoggerFlush = NIL_RTR0PTR;
876	rc = PDMR3GetSymbolR0(pVM, VMMR0_MAIN_MODULE_NAME, "vmmR0LoggerFlush", &pfnLoggerFlush);
877	AssertReleaseMsgRCReturn(rc, ("VMMLoggerFlush not found! rc=%Vra\n", rc), rc);
878
879	rc = RTLogCreateForR0(&pR0Logger->Logger, pR0Logger->cbLogger,
880	(PFNRTLOGGER )&pfnLoggerWrapper, (PFNRTLOGFLUSH )&pfnLoggerFlush,
881	RTLOGFLAGS_BUFFERED, RTLOGDEST_DUMMY);
882	AssertReleaseMsgRCReturn(rc, ("RTLogCloneGC failed! rc=%Vra\n", rc), rc);
883	pR0Logger->fCreated = true;
884	}
885
886	rc = RTLogCopyGroupsAndFlags(&pR0Logger->Logger, NULL /* default */, RTLOGFLAGS_BUFFERED, 0);
887	AssertRC(rc);
888	}
889
890	return rc;
891	}
892
893
894	/**
895	* Generic switch code relocator.
896	*
897	* @param pVM The VM handle.
898	* @param pSwitcher The switcher definition.
899	* @param pu8CodeR3 Pointer to the core code block for the switcher, ring-3 mapping.
900	* @param pu8CodeR0 Pointer to the core code block for the switcher, ring-0 mapping.
901	* @param GCPtrCode The guest context address corresponding to pu8Code.
902	* @param u32IDCode The identity mapped (ID) address corresponding to pu8Code.
903	* @param SelCS The hypervisor CS selector.
904	* @param SelDS The hypervisor DS selector.
905	* @param SelTSS The hypervisor TSS selector.
906	* @param GCPtrGDT The GC address of the hypervisor GDT.
907	* @param SelCS64 The 64-bit mode hypervisor CS selector.
908	*/
909	static void vmmR3SwitcherGenericRelocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t pu8CodeR0, uint8_t pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode,
910	RTSEL SelCS, RTSEL SelDS, RTSEL SelTSS, RTGCPTR GCPtrGDT, RTSEL SelCS64)
911	{
912	union
913	{
914	const uint8_t *pu8;
915	const uint16_t *pu16;
916	const uint32_t *pu32;
917	const uint64_t *pu64;
918	const void *pv;
919	uintptr_t u;
920	} u;
921	u.pv = pSwitcher->pvFixups;
922
923	/*
924	* Process fixups.
925	*/
926	uint8_t u8;
927	while ((u8 = *u.pu8++) != FIX_THE_END)
928	{
929	/*
930	* Get the source (where to write the fixup).
931	*/
932	uint32_t offSrc = *u.pu32++;
933	Assert(offSrc < pSwitcher->cbCode);
934	union
935	{
936	uint8_t *pu8;
937	uint16_t *pu16;
938	uint32_t *pu32;
939	uint64_t *pu64;
940	uintptr_t u;
941	} uSrc;
942	uSrc.pu8 = pu8CodeR3 + offSrc;
943
944	/* The fixup target and method depends on the type. */
945	switch (u8)
946	{
947	/*
948	* 32-bit relative, source in HC and target in GC.
949	*/
950	case FIX_HC_2_GC_NEAR_REL:
951	{
952	Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
953	uint32_t offTrg = *u.pu32++;
954	Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
955	*uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (uSrc.u + 4));
956	break;
957	}
958
959	/*
960	* 32-bit relative, source in HC and target in ID.
961	*/
962	case FIX_HC_2_ID_NEAR_REL:
963	{
964	Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
965	uint32_t offTrg = *u.pu32++;
966	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
967	*uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (uSrc.u + 4));
968	break;
969	}
970
971	/*
972	* 32-bit relative, source in GC and target in HC.
973	*/
974	case FIX_GC_2_HC_NEAR_REL:
975	{
976	Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
977	uint32_t offTrg = *u.pu32++;
978	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
979	*uSrc.pu32 = (uint32_t)(((uintptr_t)pu8CodeR0 + offTrg) - (GCPtrCode + offSrc + 4));
980	break;
981	}
982
983	/*
984	* 32-bit relative, source in GC and target in ID.
985	*/
986	case FIX_GC_2_ID_NEAR_REL:
987	{
988	Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
989	uint32_t offTrg = *u.pu32++;
990	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
991	*uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (GCPtrCode + offSrc + 4));
992	break;
993	}
994
995	/*
996	* 32-bit relative, source in ID and target in HC.
997	*/
998	case FIX_ID_2_HC_NEAR_REL:
999	{
1000	Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1001	uint32_t offTrg = *u.pu32++;
1002	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1003	*uSrc.pu32 = (uint32_t)(((uintptr_t)pu8CodeR0 + offTrg) - (u32IDCode + offSrc + 4));
1004	break;
1005	}
1006
1007	/*
1008	* 32-bit relative, source in ID and target in HC.
1009	*/
1010	case FIX_ID_2_GC_NEAR_REL:
1011	{
1012	Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1013	uint32_t offTrg = *u.pu32++;
1014	Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1015	*uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (u32IDCode + offSrc + 4));
1016	break;
1017	}
1018
1019	/*
1020	* 16:32 far jump, target in GC.
1021	*/
1022	case FIX_GC_FAR32:
1023	{
1024	uint32_t offTrg = *u.pu32++;
1025	Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1026	*uSrc.pu32++ = (uint32_t)(GCPtrCode + offTrg);
1027	*uSrc.pu16++ = SelCS;
1028	break;
1029	}
1030
1031	/*
1032	* Make 32-bit GC pointer given CPUM offset.
1033	*/
1034	case FIX_GC_CPUM_OFF:
1035	{
1036	uint32_t offCPUM = *u.pu32++;
1037	Assert(offCPUM < sizeof(pVM->cpum));
1038	*uSrc.pu32 = (uint32_t)(VM_GUEST_ADDR(pVM, &pVM->cpum) + offCPUM);
1039	break;
1040	}
1041
1042	/*
1043	* Make 32-bit GC pointer given VM offset.
1044	*/
1045	case FIX_GC_VM_OFF:
1046	{
1047	uint32_t offVM = *u.pu32++;
1048	Assert(offVM < sizeof(VM));
1049	*uSrc.pu32 = (uint32_t)(VM_GUEST_ADDR(pVM, pVM) + offVM);
1050	break;
1051	}
1052
1053	/*
1054	* Make 32-bit HC pointer given CPUM offset.
1055	*/
1056	case FIX_HC_CPUM_OFF:
1057	{
1058	uint32_t offCPUM = *u.pu32++;
1059	Assert(offCPUM < sizeof(pVM->cpum));
1060	*uSrc.pu32 = (uint32_t)pVM->pVMR0 + RT_OFFSETOF(VM, cpum) + offCPUM;
1061	break;
1062	}
1063
1064	/*
1065	* Make 32-bit R0 pointer given VM offset.
1066	*/
1067	case FIX_HC_VM_OFF:
1068	{
1069	uint32_t offVM = *u.pu32++;
1070	Assert(offVM < sizeof(VM));
1071	*uSrc.pu32 = (uint32_t)pVM->pVMR0 + offVM;
1072	break;
1073	}
1074
1075	/*
1076	* Store the 32-Bit CR3 (32-bit) for the intermediate memory context.
1077	*/
1078	case FIX_INTER_32BIT_CR3:
1079	{
1080
1081	*uSrc.pu32 = PGMGetInter32BitCR3(pVM);
1082	break;
1083	}
1084
1085	/*
1086	* Store the PAE CR3 (32-bit) for the intermediate memory context.
1087	*/
1088	case FIX_INTER_PAE_CR3:
1089	{
1090
1091	*uSrc.pu32 = PGMGetInterPaeCR3(pVM);
1092	break;
1093	}
1094
1095	/*
1096	* Store the AMD64 CR3 (32-bit) for the intermediate memory context.
1097	*/
1098	case FIX_INTER_AMD64_CR3:
1099	{
1100
1101	*uSrc.pu32 = PGMGetInterAmd64CR3(pVM);
1102	break;
1103	}
1104
1105	/*
1106	* Store the 32-Bit CR3 (32-bit) for the hypervisor (shadow) memory context.
1107	*/
1108	case FIX_HYPER_32BIT_CR3:
1109	{
1110
1111	*uSrc.pu32 = PGMGetHyper32BitCR3(pVM);
1112	break;
1113	}
1114
1115	/*
1116	* Store the PAE CR3 (32-bit) for the hypervisor (shadow) memory context.
1117	*/
1118	case FIX_HYPER_PAE_CR3:
1119	{
1120
1121	*uSrc.pu32 = PGMGetHyperPaeCR3(pVM);
1122	break;
1123	}
1124
1125	/*
1126	* Store the AMD64 CR3 (32-bit) for the hypervisor (shadow) memory context.
1127	*/
1128	case FIX_HYPER_AMD64_CR3:
1129	{
1130
1131	*uSrc.pu32 = PGMGetHyperAmd64CR3(pVM);
1132	break;
1133	}
1134
1135	/*
1136	* Store Hypervisor CS (16-bit).
1137	*/
1138	case FIX_HYPER_CS:
1139	{
1140	*uSrc.pu16 = SelCS;
1141	break;
1142	}
1143
1144	/*
1145	* Store Hypervisor DS (16-bit).
1146	*/
1147	case FIX_HYPER_DS:
1148	{
1149	*uSrc.pu16 = SelDS;
1150	break;
1151	}
1152
1153	/*
1154	* Store Hypervisor TSS (16-bit).
1155	*/
1156	case FIX_HYPER_TSS:
1157	{
1158	*uSrc.pu16 = SelTSS;
1159	break;
1160	}
1161
1162	/*
1163	* Store the 32-bit GC address of the 2nd dword of the TSS descriptor (in the GDT).
1164	*/
1165	case FIX_GC_TSS_GDTE_DW2:
1166	{
1167	RTGCPTR GCPtr = GCPtrGDT + (SelTSS & ~7) + 4;
1168	*uSrc.pu32 = (uint32_t)GCPtr;
1169	break;
1170	}
1171
1172
1173	///@todo case FIX_CR4_MASK:
1174	///@todo case FIX_CR4_OSFSXR:
1175
1176	/*
1177	* Insert relative jump to specified target it FXSAVE/FXRSTOR isn't supported by the cpu.
1178	*/
1179	case FIX_NO_FXSAVE_JMP:
1180	{
1181	uint32_t offTrg = *u.pu32++;
1182	Assert(offTrg < pSwitcher->cbCode);
1183	if (!CPUMSupportsFXSR(pVM))
1184	{
1185	uSrc.pu8++ = 0xe9; / jmp rel32 */
1186	*uSrc.pu32++ = offTrg - (offSrc + 5);
1187	}
1188	else
1189	{
1190	uSrc.pu8++ = ((uint8_t *)pSwitcher->pvCode + offSrc);
1191	uSrc.pu32++ = (uint32_t )((uint8_t )pSwitcher->pvCode + offSrc + 1);
1192	}
1193	break;
1194	}
1195
1196	/*
1197	* Insert relative jump to specified target it SYSENTER isn't used by the host.
1198	*/
1199	case FIX_NO_SYSENTER_JMP:
1200	{
1201	uint32_t offTrg = *u.pu32++;
1202	Assert(offTrg < pSwitcher->cbCode);
1203	if (!CPUMIsHostUsingSysEnter(pVM))
1204	{
1205	uSrc.pu8++ = 0xe9; / jmp rel32 */
1206	*uSrc.pu32++ = offTrg - (offSrc + 5);
1207	}
1208	else
1209	{
1210	uSrc.pu8++ = ((uint8_t *)pSwitcher->pvCode + offSrc);
1211	uSrc.pu32++ = (uint32_t )((uint8_t )pSwitcher->pvCode + offSrc + 1);
1212	}
1213	break;
1214	}
1215
1216	/*
1217	* Insert relative jump to specified target it SYSENTER isn't used by the host.
1218	*/
1219	case FIX_NO_SYSCALL_JMP:
1220	{
1221	uint32_t offTrg = *u.pu32++;
1222	Assert(offTrg < pSwitcher->cbCode);
1223	if (!CPUMIsHostUsingSysEnter(pVM))
1224	{
1225	uSrc.pu8++ = 0xe9; / jmp rel32 */
1226	*uSrc.pu32++ = offTrg - (offSrc + 5);
1227	}
1228	else
1229	{
1230	uSrc.pu8++ = ((uint8_t *)pSwitcher->pvCode + offSrc);
1231	uSrc.pu32++ = (uint32_t )((uint8_t )pSwitcher->pvCode + offSrc + 1);
1232	}
1233	break;
1234	}
1235
1236	/*
1237	* 32-bit HC pointer fixup to (HC) target within the code (32-bit offset).
1238	*/
1239	case FIX_HC_32BIT:
1240	{
1241	uint32_t offTrg = *u.pu32++;
1242	Assert(offSrc < pSwitcher->cbCode);
1243	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1244	*uSrc.pu32 = (uintptr_t)pu8CodeR0 + offTrg;
1245	break;
1246	}
1247
1248	#if defined(__AMD64__) \|\| defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
1249	/*
1250	* 64-bit HC pointer fixup to (HC) target within the code (32-bit offset).
1251	*/
1252	case FIX_HC_64BIT:
1253	{
1254	uint32_t offTrg = *u.pu32++;
1255	Assert(offSrc < pSwitcher->cbCode);
1256	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1257	*uSrc.pu64 = (uintptr_t)pu8CodeR0 + offTrg;
1258	break;
1259	}
1260
1261	/*
1262	* 64-bit HC Code Selector (no argument).
1263	*/
1264	case FIX_HC_64BIT_CS:
1265	{
1266	Assert(offSrc < pSwitcher->cbCode);
1267	#if defined(__DARWIN__) && defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
1268	uSrc.pu16 = 0x80; / KERNEL64_CS from i386/seg.h */
1269	#else
1270	AssertFatalMsgFailed(("FIX_HC_64BIT_CS not implemented for this host\n"));
1271	#endif
1272	break;
1273	}
1274
1275	/*
1276	* 64-bit HC pointer to the CPUM instance data (no argument).
1277	*/
1278	case FIX_HC_64BIT_CPUM:
1279	{
1280	Assert(offSrc < pSwitcher->cbCode);
1281	*uSrc.pu64 = pVM->pVMR0 + RT_OFFSETOF(VM, cpum);
1282	break;
1283	}
1284	#endif
1285
1286	/*
1287	* 32-bit ID pointer to (ID) target within the code (32-bit offset).
1288	*/
1289	case FIX_ID_32BIT:
1290	{
1291	uint32_t offTrg = *u.pu32++;
1292	Assert(offSrc < pSwitcher->cbCode);
1293	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1294	*uSrc.pu32 = u32IDCode + offTrg;
1295	break;
1296	}
1297
1298	/*
1299	* 64-bit ID pointer to (ID) target within the code (32-bit offset).
1300	*/
1301	case FIX_ID_64BIT:
1302	{
1303	uint32_t offTrg = *u.pu32++;
1304	Assert(offSrc < pSwitcher->cbCode);
1305	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1306	*uSrc.pu64 = u32IDCode + offTrg;
1307	break;
1308	}
1309
1310	/*
1311	* Far 16:32 ID pointer to 64-bit mode (ID) target within the code (32-bit offset).
1312	*/
1313	case FIX_ID_FAR32_TO_64BIT_MODE:
1314	{
1315	uint32_t offTrg = *u.pu32++;
1316	Assert(offSrc < pSwitcher->cbCode);
1317	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1318	*uSrc.pu32++ = u32IDCode + offTrg;
1319	*uSrc.pu16 = SelCS64;
1320	AssertRelease(SelCS64);
1321	break;
1322	}
1323
1324	#ifdef VBOX_WITH_NMI
1325	/*
1326	* 32-bit address to the APIC base.
1327	*/
1328	case FIX_GC_APIC_BASE_32BIT:
1329	{
1330	*uSrc.pu32 = pVM->vmm.s.GCPtrApicBase;
1331	break;
1332	}
1333	#endif
1334
1335	default:
1336	AssertReleaseMsgFailed(("Unknown fixup %d in switcher %s\n", u8, pSwitcher->pszDesc));
1337	break;
1338	}
1339	}
1340
1341	#ifdef LOG_ENABLED
1342	/*
1343	* If Log2 is enabled disassemble the switcher code.
1344	*
1345	* The switcher code have 1-2 HC parts, 1 GC part and 0-2 ID parts.
1346	*/
1347	if (LogIs2Enabled())
1348	{
1349	RTLogPrintf("* Disassembly of switcher %d '%s' %#x bytes *\n"
1350	" pu8CodeR0 = %p\n"
1351	" pu8CodeR3 = %p\n"
1352	" GCPtrCode = %VGv\n"
1353	" u32IDCode = %08x\n"
1354	" pVMGC = %VGv\n"
1355	" pCPUMGC = %VGv\n"
1356	" pVMHC = %p\n"
1357	" pCPUMHC = %p\n"
1358	" GCPtrGDT = %VGv\n"
1359	" InterCR3s = %08x, %08x, %08x (32-Bit, PAE, AMD64)\n"
1360	" HyperCR3s = %08x, %08x, %08x (32-Bit, PAE, AMD64)\n"
1361	" SelCS = %04x\n"
1362	" SelDS = %04x\n"
1363	" SelCS64 = %04x\n"
1364	" SelTSS = %04x\n",
1365	pSwitcher->enmType, pSwitcher->pszDesc, pSwitcher->cbCode,
1366	pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode, VM_GUEST_ADDR(pVM, pVM),
1367	VM_GUEST_ADDR(pVM, &pVM->cpum), pVM, &pVM->cpum,
1368	GCPtrGDT,
1369	PGMGetHyper32BitCR3(pVM), PGMGetHyperPaeCR3(pVM), PGMGetHyperAmd64CR3(pVM),
1370	PGMGetInter32BitCR3(pVM), PGMGetInterPaeCR3(pVM), PGMGetInterAmd64CR3(pVM),
1371	SelCS, SelDS, SelCS64, SelTSS);
1372
1373	uint32_t offCode = 0;
1374	while (offCode < pSwitcher->cbCode)
1375	{
1376	/*
1377	* Figure out where this is.
1378	*/
1379	const char *pszDesc = NULL;
1380	RTUINTPTR uBase;
1381	uint32_t cbCode;
1382	if (offCode - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0)
1383	{
1384	pszDesc = "HCCode0";
1385	uBase = (RTUINTPTR)pu8CodeR0;
1386	offCode = pSwitcher->offHCCode0;
1387	cbCode = pSwitcher->cbHCCode0;
1388	}
1389	else if (offCode - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1)
1390	{
1391	pszDesc = "HCCode1";
1392	uBase = (RTUINTPTR)pu8CodeR0;
1393	offCode = pSwitcher->offHCCode1;
1394	cbCode = pSwitcher->cbHCCode1;
1395	}
1396	else if (offCode - pSwitcher->offGCCode < pSwitcher->cbGCCode)
1397	{
1398	pszDesc = "GCCode";
1399	uBase = GCPtrCode;
1400	offCode = pSwitcher->offGCCode;
1401	cbCode = pSwitcher->cbGCCode;
1402	}
1403	else if (offCode - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0)
1404	{
1405	pszDesc = "IDCode0";
1406	uBase = u32IDCode;
1407	offCode = pSwitcher->offIDCode0;
1408	cbCode = pSwitcher->cbIDCode0;
1409	}
1410	else if (offCode - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1)
1411	{
1412	pszDesc = "IDCode1";
1413	uBase = u32IDCode;
1414	offCode = pSwitcher->offIDCode1;
1415	cbCode = pSwitcher->cbIDCode1;
1416	}
1417	else
1418	{
1419	RTLogPrintf(" %04x: %02x '%c' (nowhere)\n",
1420	offCode, pu8CodeR3[offCode], isprint(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
1421	offCode++;
1422	continue;
1423	}
1424
1425	/*
1426	* Disassemble it.
1427	*/
1428	RTLogPrintf(" %s: offCode=%#x cbCode=%#x\n", pszDesc, offCode, cbCode);
1429	DISCPUSTATE Cpu = {0};
1430	Cpu.mode = CPUMODE_32BIT;
1431	while (cbCode > 0)
1432	{
1433	/* try label it */
1434	if (pSwitcher->offR0HostToGuest == offCode)
1435	RTLogPrintf(" *R0HostToGuest:\n");
1436	if (pSwitcher->offGCGuestToHost == offCode)
1437	RTLogPrintf(" *GCGuestToHost:\n");
1438	if (pSwitcher->offGCCallTrampoline == offCode)
1439	RTLogPrintf(" *GCCallTrampoline:\n");
1440	if (pSwitcher->offGCGuestToHostAsm == offCode)
1441	RTLogPrintf(" *GCGuestToHostAsm:\n");
1442	if (pSwitcher->offGCGuestToHostAsmHyperCtx == offCode)
1443	RTLogPrintf(" *GCGuestToHostAsmHyperCtx:\n");
1444	if (pSwitcher->offGCGuestToHostAsmGuestCtx == offCode)
1445	RTLogPrintf(" *GCGuestToHostAsmGuestCtx:\n");
1446
1447	/* disas */
1448	uint32_t cbInstr = 0;
1449	char szDisas[256];
1450	if (DISInstr(&Cpu, (RTUINTPTR)pu8CodeR3 + offCode, uBase - (RTUINTPTR)pu8CodeR3, &cbInstr, szDisas))
1451	RTLogPrintf(" %04x: %s", offCode, szDisas); //for whatever reason szDisas includes '\n'.
1452	else
1453	{
1454	RTLogPrintf(" %04x: %02x '%c'\n",
1455	offCode, pu8CodeR3[offCode], isprint(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
1456	cbInstr = 1;
1457	}
1458	offCode += cbInstr;
1459	cbCode -= RT_MIN(cbInstr, cbCode);
1460	}
1461	}
1462	}
1463	#endif
1464	}
1465
1466
1467	/**
1468	* Relocator for the 32-Bit to 32-Bit world switcher.
1469	*/
1470	DECLCALLBACK(void) vmmR3Switcher32BitTo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t pu8CodeR0, uint8_t pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1471	{
1472	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1473	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1474	}
1475
1476
1477	/**
1478	* Relocator for the 32-Bit to PAE world switcher.
1479	*/
1480	DECLCALLBACK(void) vmmR3Switcher32BitToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t pu8CodeR0, uint8_t pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1481	{
1482	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1483	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1484	}
1485
1486
1487	/**
1488	* Relocator for the PAE to 32-Bit world switcher.
1489	*/
1490	DECLCALLBACK(void) vmmR3SwitcherPAETo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t pu8CodeR0, uint8_t pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1491	{
1492	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1493	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1494	}
1495
1496
1497	/**
1498	* Relocator for the PAE to PAE world switcher.
1499	*/
1500	DECLCALLBACK(void) vmmR3SwitcherPAEToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t pu8CodeR0, uint8_t pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1501	{
1502	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1503	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1504	}
1505
1506
1507	/**
1508	* Relocator for the AMD64 to PAE world switcher.
1509	*/
1510	DECLCALLBACK(void) vmmR3SwitcherAMD64ToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t pu8CodeR0, uint8_t pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1511	{
1512	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1513	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
1514	}
1515
1516
1517	/**
1518	* Gets the pointer to g_szRTAssertMsg1 in GC.
1519	* @returns Pointer to VMMGC::g_szRTAssertMsg1.
1520	* Returns NULL if not present.
1521	* @param pVM The VM handle.
1522	*/
1523	VMMR3DECL(const char *) VMMR3GetGCAssertMsg1(PVM pVM)
1524	{
1525	RTGCPTR GCPtr;
1526	int rc = PDMR3GetSymbolGC(pVM, NULL, "g_szRTAssertMsg1", &GCPtr);
1527	if (VBOX_SUCCESS(rc))
1528	return (const char *)MMHyperGC2HC(pVM, GCPtr);
1529	return NULL;
1530	}
1531
1532
1533	/**
1534	* Gets the pointer to g_szRTAssertMsg2 in GC.
1535	* @returns Pointer to VMMGC::g_szRTAssertMsg2.
1536	* Returns NULL if not present.
1537	* @param pVM The VM handle.
1538	*/
1539	VMMR3DECL(const char *) VMMR3GetGCAssertMsg2(PVM pVM)
1540	{
1541	RTGCPTR GCPtr;
1542	int rc = PDMR3GetSymbolGC(pVM, NULL, "g_szRTAssertMsg2", &GCPtr);
1543	if (VBOX_SUCCESS(rc))
1544	return (const char *)MMHyperGC2HC(pVM, GCPtr);
1545	return NULL;
1546	}
1547
1548
1549	/**
1550	* Execute state save operation.
1551	*
1552	* @returns VBox status code.
1553	* @param pVM VM Handle.
1554	* @param pSSM SSM operation handle.
1555	*/
1556	static DECLCALLBACK(int) vmmR3Save(PVM pVM, PSSMHANDLE pSSM)
1557	{
1558	LogFlow(("vmmR3Save:\n"));
1559
1560	/*
1561	* The hypervisor stack.
1562	*/
1563	SSMR3PutGCPtr(pSSM, pVM->vmm.s.pbGCStackBottom);
1564	RTGCPTR GCPtrESP = CPUMGetHyperESP(pVM);
1565	Assert(pVM->vmm.s.pbGCStackBottom - GCPtrESP <= VMM_STACK_SIZE);
1566	SSMR3PutGCPtr(pSSM, GCPtrESP);
1567	SSMR3PutMem(pSSM, pVM->vmm.s.pbHCStack, VMM_STACK_SIZE);
1568	return SSMR3PutU32(pSSM, ~0); /* terminator */
1569	}
1570
1571
1572	/**
1573	* Execute state load operation.
1574	*
1575	* @returns VBox status code.
1576	* @param pVM VM Handle.
1577	* @param pSSM SSM operation handle.
1578	* @param u32Version Data layout version.
1579	*/
1580	static DECLCALLBACK(int) vmmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
1581	{
1582	LogFlow(("vmmR3Load:\n"));
1583
1584	/*
1585	* Validate version.
1586	*/
1587	if (u32Version != VMM_SAVED_STATE_VERSION)
1588	{
1589	Log(("vmmR3Load: Invalid version u32Version=%d!\n", u32Version));
1590	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1591	}
1592
1593	/*
1594	* Check that the stack is in the same place, or that it's fearly empty.
1595	*/
1596	RTGCPTR GCPtrStackBottom;
1597	SSMR3GetGCPtr(pSSM, &GCPtrStackBottom);
1598	RTGCPTR GCPtrESP;
1599	int rc = SSMR3GetGCPtr(pSSM, &GCPtrESP);
1600	if (VBOX_FAILURE(rc))
1601	return rc;
1602	if ( GCPtrStackBottom == pVM->vmm.s.pbGCStackBottom
1603	\|\| (GCPtrStackBottom - GCPtrESP < 32)) /** @todo This will break if we start preemting the hypervisor. */
1604	{
1605	/*
1606	* We must set the ESP because the CPUM load + PGM load relocations will render
1607	* the ESP in CPUM fatally invalid.
1608	*/
1609	CPUMSetHyperESP(pVM, GCPtrESP);
1610
1611	/* restore the stack. */
1612	SSMR3GetMem(pSSM, pVM->vmm.s.pbHCStack, VMM_STACK_SIZE);
1613
1614	/* terminator */
1615	uint32_t u32;
1616	rc = SSMR3GetU32(pSSM, &u32);
1617	if (VBOX_FAILURE(rc))
1618	return rc;
1619	if (u32 != ~0U)
1620	{
1621	AssertMsgFailed(("u32=%#x\n", u32));
1622	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1623	}
1624	return VINF_SUCCESS;
1625	}
1626
1627	LogRel(("The stack is not in the same place and it's not empty! GCPtrStackBottom=%VGv pbGCStackBottom=%VGv ESP=%VGv\n",
1628	GCPtrStackBottom, pVM->vmm.s.pbGCStackBottom, GCPtrESP));
1629	AssertFailed();
1630	return VERR_SSM_LOAD_CONFIG_MISMATCH;
1631	}
1632
1633
1634	/**
1635	* Selects the switcher to be used for switching to GC.
1636	*
1637	* @returns VBox status code.
1638	* @param pVM VM handle.
1639	* @param enmSwitcher The new switcher.
1640	* @remark This function may be called before the VMM is initialized.
1641	*/
1642	VMMR3DECL(int) VMMR3SelectSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
1643	{
1644	/*
1645	* Validate input.
1646	*/
1647	if ( enmSwitcher < VMMSWITCHER_INVALID
1648	\|\| enmSwitcher >= VMMSWITCHER_MAX)
1649	{
1650	AssertMsgFailed(("Invalid input enmSwitcher=%d\n", enmSwitcher));
1651	return VERR_INVALID_PARAMETER;
1652	}
1653
1654	/*
1655	* Select the new switcher.
1656	*/
1657	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[enmSwitcher];
1658	if (pSwitcher)
1659	{
1660	Log(("VMMR3SelectSwitcher: enmSwitcher %d -> %d %s\n", pVM->vmm.s.enmSwitcher, enmSwitcher, pSwitcher->pszDesc));
1661	pVM->vmm.s.enmSwitcher = enmSwitcher;
1662
1663	RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvHCCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher]; /** @todo fix the pvHCCoreCodeR0 type */
1664	pVM->vmm.s.pfnR0HostToGuest = pbCodeR0 + pSwitcher->offR0HostToGuest;
1665
1666	RTGCPTR GCPtr = pVM->vmm.s.pvGCCoreCode + pVM->vmm.s.aoffSwitchers[enmSwitcher];
1667	pVM->vmm.s.pfnGCGuestToHost = GCPtr + pSwitcher->offGCGuestToHost;
1668	pVM->vmm.s.pfnGCCallTrampoline = GCPtr + pSwitcher->offGCCallTrampoline;
1669	pVM->pfnVMMGCGuestToHostAsm = GCPtr + pSwitcher->offGCGuestToHostAsm;
1670	pVM->pfnVMMGCGuestToHostAsmHyperCtx = GCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
1671	pVM->pfnVMMGCGuestToHostAsmGuestCtx = GCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
1672	return VINF_SUCCESS;
1673	}
1674	return VERR_NOT_IMPLEMENTED;
1675	}
1676
1677	/**
1678	* Disable the switcher logic permanently.
1679	*
1680	* @returns VBox status code.
1681	* @param pVM VM handle.
1682	*/
1683	VMMR3DECL(int) VMMR3DisableSwitcher(PVM pVM)
1684	{
1685	/** @todo r=bird: I would suggest that we create a dummy switcher which just does something like:
1686	* @code
1687	* mov eax, VERR_INTERNAL_ERROR
1688	* ret
1689	* @endcode
1690	* And then check for fSwitcherDisabled in VMMR3SelectSwitcher() in order to prevent it from being removed.
1691	*/
1692	pVM->vmm.s.fSwitcherDisabled = true;
1693	return VINF_SUCCESS;
1694	}
1695
1696
1697	/**
1698	* Resolve a builtin GC symbol.
1699	* Called by PDM when loading or relocating GC modules.
1700	*
1701	* @returns VBox status
1702	* @param pVM VM Handle.
1703	* @param pszSymbol Symbol to resolv
1704	* @param pGCPtrValue Where to store the symbol value.
1705	* @remark This has to work before VMMR3Relocate() is called.
1706	*/
1707	VMMR3DECL(int) VMMR3GetImportGC(PVM pVM, const char *pszSymbol, PRTGCPTR pGCPtrValue)
1708	{
1709	if (!strcmp(pszSymbol, "g_Logger"))
1710	{
1711	if (pVM->vmm.s.pLoggerHC)
1712	pVM->vmm.s.pLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pLoggerHC);
1713	*pGCPtrValue = pVM->vmm.s.pLoggerGC;
1714	}
1715	else if (!strcmp(pszSymbol, "g_RelLogger"))
1716	{
1717	#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
1718	if (pVM->vmm.s.pRelLoggerHC)
1719	pVM->vmm.s.pRelLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pRelLoggerHC);
1720	*pGCPtrValue = pVM->vmm.s.pRelLoggerGC;
1721	#else
1722	*pGCPtrValue = NIL_RTGCPTR;
1723	#endif
1724	}
1725	else
1726	return VERR_SYMBOL_NOT_FOUND;
1727	return VINF_SUCCESS;
1728	}
1729
1730
1731	/**
1732	* Suspends the the CPU yielder.
1733	*
1734	* @param pVM The VM handle.
1735	*/
1736	VMMR3DECL(void) VMMR3YieldSuspend(PVM pVM)
1737	{
1738	if (!pVM->vmm.s.cYieldResumeMillies)
1739	{
1740	uint64_t u64Now = TMTimerGet(pVM->vmm.s.pYieldTimer);
1741	uint64_t u64Expire = TMTimerGetExpire(pVM->vmm.s.pYieldTimer);
1742	if (u64Now >= u64Expire \|\| u64Expire == ~(uint64_t)0)
1743	pVM->vmm.s.cYieldResumeMillies = pVM->vmm.s.cYieldEveryMillies;
1744	else
1745	pVM->vmm.s.cYieldResumeMillies = TMTimerToMilli(pVM->vmm.s.pYieldTimer, u64Expire - u64Now);
1746	TMTimerStop(pVM->vmm.s.pYieldTimer);
1747	}
1748	pVM->vmm.s.u64LastYield = RTTimeNanoTS();
1749	}
1750
1751
1752	/**
1753	* Stops the the CPU yielder.
1754	*
1755	* @param pVM The VM handle.
1756	*/
1757	VMMR3DECL(void) VMMR3YieldStop(PVM pVM)
1758	{
1759	if (!pVM->vmm.s.cYieldResumeMillies)
1760	TMTimerStop(pVM->vmm.s.pYieldTimer);
1761	pVM->vmm.s.cYieldResumeMillies = pVM->vmm.s.cYieldEveryMillies;
1762	pVM->vmm.s.u64LastYield = RTTimeNanoTS();
1763	}
1764
1765
1766	/**
1767	* Resumes the CPU yielder when it has been a suspended or stopped.
1768	*
1769	* @param pVM The VM handle.
1770	*/
1771	VMMR3DECL(void) VMMR3YieldResume(PVM pVM)
1772	{
1773	if (pVM->vmm.s.cYieldResumeMillies)
1774	{
1775	TMTimerSetMillies(pVM->vmm.s.pYieldTimer, pVM->vmm.s.cYieldResumeMillies);
1776	pVM->vmm.s.cYieldResumeMillies = 0;
1777	}
1778	}
1779
1780
1781	/**
1782	* Internal timer callback function.
1783	*
1784	* @param pVM The VM.
1785	* @param pTimer The timer handle.
1786	* @param pvUser User argument specified upon timer creation.
1787	*/
1788	static DECLCALLBACK(void) vmmR3YieldEMT(PVM pVM, PTMTIMER pTimer, void *pvUser)
1789	{
1790	/*
1791	* This really needs some careful tuning. While we shouldn't be too gready since
1792	* that'll cause the rest of the system to stop up, we shouldn't be too nice either
1793	* because that'll cause us to stop up.
1794	*
1795	* The current logic is to use the default interval when there is no lag worth
1796	* mentioning, but when we start accumulating lag we don't bother yielding at all.
1797	*
1798	* (This depends on the TMCLOCK_VIRTUAL_SYNC to be scheduled before TMCLOCK_REAL
1799	* so the lag is up to date.)
1800	*/
1801	const uint64_t u64Lag = TMVirtualSyncGetLag(pVM);
1802	if ( u64Lag < 50000000 /* 50ms */
1803	\|\| ( u64Lag < 1000000000 /* 1s */
1804	&& RTTimeNanoTS() - pVM->vmm.s.u64LastYield < 500000000 /* 500 ms */)
1805	)
1806	{
1807	uint64_t u64Elapsed = RTTimeNanoTS();
1808	pVM->vmm.s.u64LastYield = u64Elapsed;
1809
1810	RTThreadYield();
1811
1812	#ifdef LOG_ENABLED
1813	u64Elapsed = RTTimeNanoTS() - u64Elapsed;
1814	Log(("vmmR3YieldEMT: %RI64 ns\n", u64Elapsed));
1815	#endif
1816	}
1817	TMTimerSetMillies(pTimer, pVM->vmm.s.cYieldEveryMillies);
1818	}
1819
1820
1821	/**
1822	* Acquire global VM lock.
1823	*
1824	* @returns VBox status code
1825	* @param pVM The VM to operate on.
1826	*/
1827	VMMR3DECL(int) VMMR3Lock(PVM pVM)
1828	{
1829	return RTCritSectEnter(&pVM->vmm.s.CritSectVMLock);
1830	}
1831
1832
1833	/**
1834	* Release global VM lock.
1835	*
1836	* @returns VBox status code
1837	* @param pVM The VM to operate on.
1838	*/
1839	VMMR3DECL(int) VMMR3Unlock(PVM pVM)
1840	{
1841	return RTCritSectLeave(&pVM->vmm.s.CritSectVMLock);
1842	}
1843
1844
1845	/**
1846	* Return global VM lock owner.
1847	*
1848	* @returns Thread id of owner.
1849	* @returns NIL_RTTHREAD if no owner.
1850	* @param pVM The VM to operate on.
1851	*/
1852	VMMR3DECL(RTNATIVETHREAD) VMMR3LockGetOwner(PVM pVM)
1853	{
1854	return RTCritSectGetOwner(&pVM->vmm.s.CritSectVMLock);
1855	}
1856
1857
1858	/**
1859	* Checks if the current thread is the owner of the global VM lock.
1860	*
1861	* @returns true if owner.
1862	* @returns false if not owner.
1863	* @param pVM The VM to operate on.
1864	*/
1865	VMMR3DECL(bool) VMMR3LockIsOwner(PVM pVM)
1866	{
1867	return RTCritSectIsOwner(&pVM->vmm.s.CritSectVMLock);
1868	}
1869
1870
1871	/**
1872	* Executes guest code.
1873	*
1874	* @param pVM VM handle.
1875	*/
1876	VMMR3DECL(int) VMMR3RawRunGC(PVM pVM)
1877	{
1878	Log2(("VMMR3RawRunGC: (cs:eip=%04x:%08x)\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1879
1880	/*
1881	* Set the EIP and ESP.
1882	*/
1883	CPUMSetHyperEIP(pVM, CPUMGetGuestEFlags(pVM) & X86_EFL_VM
1884	? pVM->vmm.s.pfnCPUMGCResumeGuestV86
1885	: pVM->vmm.s.pfnCPUMGCResumeGuest);
1886	CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom);
1887
1888	/*
1889	* We hide log flushes (outer) and hypervisor interrupts (inner).
1890	*/
1891	for (;;)
1892	{
1893	int rc;
1894	do
1895	{
1896	#ifdef NO_SUPCALLR0VMM
1897	rc = VERR_GENERAL_FAILURE;
1898	#else
1899	rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_RAW_RUN, NULL);
1900	#endif
1901	} while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
1902
1903	/*
1904	* Flush the logs.
1905	*/
1906	#ifdef LOG_ENABLED
1907	PRTLOGGERGC pLogger = pVM->vmm.s.pLoggerHC;
1908	if ( pLogger
1909	&& pLogger->offScratch > 0)
1910	RTLogFlushGC(NULL, pLogger);
1911	#endif
1912	#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
1913	PRTLOGGERGC pRelLogger = pVM->vmm.s.pRelLoggerHC;
1914	if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
1915	RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
1916	#endif
1917	if (rc != VINF_VMM_CALL_HOST)
1918	{
1919	Log2(("VMMR3RawRunGC: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1920	return rc;
1921	}
1922	rc = vmmR3ServiceCallHostRequest(pVM);
1923	if (VBOX_FAILURE(rc))
1924	return rc;
1925	/* Resume GC */
1926	}
1927	}
1928
1929
1930	/**
1931	* Executes guest code (Intel VMX and AMD SVM).
1932	*
1933	* @param pVM VM handle.
1934	*/
1935	VMMR3DECL(int) VMMR3HwAccRunGC(PVM pVM)
1936	{
1937	Log2(("VMMR3HwAccRunGC: (cs:eip=%04x:%08x)\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1938
1939	for (;;)
1940	{
1941	int rc;
1942	do
1943	{
1944	#ifdef NO_SUPCALLR0VMM
1945	rc = VERR_GENERAL_FAILURE;
1946	#else
1947	rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_HWACC_RUN, NULL);
1948	#endif
1949	} while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
1950
1951	#ifdef LOG_ENABLED
1952	/*
1953	* Flush the log
1954	*/
1955	PVMMR0LOGGER pR0Logger = pVM->vmm.s.pR0Logger;
1956	if ( pR0Logger
1957	&& pR0Logger->Logger.offScratch > 0)
1958	RTLogFlushToLogger(&pR0Logger->Logger, NULL);
1959	#endif /* !LOG_ENABLED */
1960	if (rc != VINF_VMM_CALL_HOST)
1961	{
1962	Log2(("VMMR3HwAccRunGC: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1963	return rc;
1964	}
1965	rc = vmmR3ServiceCallHostRequest(pVM);
1966	if (VBOX_FAILURE(rc))
1967	return rc;
1968	/* Resume R0 */
1969	}
1970	}
1971
1972	/**
1973	* Calls GC a function.
1974	*
1975	* @param pVM The VM handle.
1976	* @param GCPtrEntry The GC function address.
1977	* @param cArgs The number of arguments in the ....
1978	* @param ... Arguments to the function.
1979	*/
1980	VMMR3DECL(int) VMMR3CallGC(PVM pVM, RTGCPTR GCPtrEntry, unsigned cArgs, ...)
1981	{
1982	va_list args;
1983	va_start(args, cArgs);
1984	int rc = VMMR3CallGCV(pVM, GCPtrEntry, cArgs, args);
1985	va_end(args);
1986	return rc;
1987	}
1988
1989
1990	/**
1991	* Calls GC a function.
1992	*
1993	* @param pVM The VM handle.
1994	* @param GCPtrEntry The GC function address.
1995	* @param cArgs The number of arguments in the ....
1996	* @param args Arguments to the function.
1997	*/
1998	VMMR3DECL(int) VMMR3CallGCV(PVM pVM, RTGCPTR GCPtrEntry, unsigned cArgs, va_list args)
1999	{
2000	Log2(("VMMR3CallGCV: GCPtrEntry=%VGv cArgs=%d\n", GCPtrEntry, cArgs));
2001
2002	/*
2003	* Setup the call frame using the trampoline.
2004	*/
2005	CPUMHyperSetCtxCore(pVM, NULL);
2006	memset(pVM->vmm.s.pbHCStack, 0xaa, VMM_STACK_SIZE); /* Clear the stack. */
2007	CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom - cArgs * sizeof(RTGCUINTPTR));
2008	PRTGCUINTPTR pFrame = (PRTGCUINTPTR)(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE) - cArgs;
2009	int i = cArgs;
2010	while (i-- > 0)
2011	*pFrame++ = va_arg(args, RTGCUINTPTR);
2012
2013	CPUMPushHyper(pVM, cArgs * sizeof(RTGCUINTPTR)); /* stack frame size */
2014	CPUMPushHyper(pVM, GCPtrEntry); /* what to call */
2015	CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnGCCallTrampoline);
2016
2017	/*
2018	* We hide log flushes (outer) and hypervisor interrupts (inner).
2019	*/
2020	for (;;)
2021	{
2022	int rc;
2023	do
2024	{
2025	#ifdef NO_SUPCALLR0VMM
2026	rc = VERR_GENERAL_FAILURE;
2027	#else
2028	rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_RAW_RUN, NULL);
2029	#endif
2030	} while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
2031
2032	/*
2033	* Flush the logs.
2034	*/
2035	#ifdef LOG_ENABLED
2036	PRTLOGGERGC pLogger = pVM->vmm.s.pLoggerHC;
2037	if ( pLogger
2038	&& pLogger->offScratch > 0)
2039	RTLogFlushGC(NULL, pLogger);
2040	#endif
2041	#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
2042	PRTLOGGERGC pRelLogger = pVM->vmm.s.pRelLoggerHC;
2043	if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
2044	RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
2045	#endif
2046	if (rc == VERR_TRPM_PANIC \|\| rc == VERR_TRPM_DONT_PANIC)
2047	VMMR3FatalDump(pVM, rc);
2048	if (rc != VINF_VMM_CALL_HOST)
2049	{
2050	Log2(("VMMR3CallGCV: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
2051	return rc;
2052	}
2053	rc = vmmR3ServiceCallHostRequest(pVM);
2054	if (VBOX_FAILURE(rc))
2055	return rc;
2056	}
2057	}
2058
2059
2060	/**
2061	* Resumes executing hypervisor code when interrupted
2062	* by a queue flush or a debug event.
2063	*
2064	* @returns VBox status code.
2065	* @param pVM VM handle.
2066	*/
2067	VMMR3DECL(int) VMMR3ResumeHyper(PVM pVM)
2068	{
2069	Log(("VMMR3ResumeHyper: eip=%VGv esp=%VGv\n", CPUMGetHyperEIP(pVM), CPUMGetHyperESP(pVM)));
2070
2071	/*
2072	* We hide log flushes (outer) and hypervisor interrupts (inner).
2073	*/
2074	for (;;)
2075	{
2076	int rc;
2077	do
2078	{
2079	#ifdef NO_SUPCALLR0VMM
2080	rc = VERR_GENERAL_FAILURE;
2081	#else
2082	rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_RAW_RUN, NULL);
2083	#endif
2084	} while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
2085
2086	/*
2087	* Flush the loggers,
2088	*/
2089	#ifdef LOG_ENABLED
2090	PRTLOGGERGC pLogger = pVM->vmm.s.pLoggerHC;
2091	if ( pLogger
2092	&& pLogger->offScratch > 0)
2093	RTLogFlushGC(NULL, pLogger);
2094	#endif
2095	#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
2096	PRTLOGGERGC pRelLogger = pVM->vmm.s.pRelLoggerHC;
2097	if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
2098	RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
2099	#endif
2100	if (rc == VERR_TRPM_PANIC \|\| rc == VERR_TRPM_DONT_PANIC)
2101	VMMR3FatalDump(pVM, rc);
2102	if (rc != VINF_VMM_CALL_HOST)
2103	{
2104	Log(("VMMR3ResumeHyper: returns %Vrc\n", rc));
2105	return rc;
2106	}
2107	rc = vmmR3ServiceCallHostRequest(pVM);
2108	if (VBOX_FAILURE(rc))
2109	return rc;
2110	}
2111	}
2112
2113
2114	/**
2115	* Service a call to the ring-3 host code.
2116	*
2117	* @returns VBox status code.
2118	* @param pVM VM handle.
2119	* @remark Careful with critsects.
2120	*/
2121	static int vmmR3ServiceCallHostRequest(PVM pVM)
2122	{
2123	switch (pVM->vmm.s.enmCallHostOperation)
2124	{
2125	/*
2126	* Acquire the PDM lock.
2127	*/
2128	case VMMCALLHOST_PDM_LOCK:
2129	{
2130	pVM->vmm.s.rcCallHost = PDMR3LockCall(pVM);
2131	break;
2132	}
2133
2134	/*
2135	* Flush a PDM queue.
2136	*/
2137	case VMMCALLHOST_PDM_QUEUE_FLUSH:
2138	{
2139	PDMR3QueueFlushWorker(pVM, NULL);
2140	pVM->vmm.s.rcCallHost = VINF_SUCCESS;
2141	break;
2142	}
2143
2144	/*
2145	* Grow the PGM pool.
2146	*/
2147	case VMMCALLHOST_PGM_POOL_GROW:
2148	{
2149	pVM->vmm.s.rcCallHost = PGMR3PoolGrow(pVM);
2150	break;
2151	}
2152
2153	/*
2154	* Acquire the PGM lock.
2155	*/
2156	case VMMCALLHOST_PGM_LOCK:
2157	{
2158	pVM->vmm.s.rcCallHost = PGMR3LockCall(pVM);
2159	break;
2160	}
2161
2162	/*
2163	* Flush REM handler notifications.
2164	*/
2165	case VMMCALLHOST_REM_REPLAY_HANDLER_NOTIFICATIONS:
2166	{
2167	REMR3ReplayHandlerNotifications(pVM);
2168	break;
2169	}
2170
2171	case VMMCALLHOST_PGM_RAM_GROW_RANGE:
2172	{
2173	pVM->vmm.s.rcCallHost = PGM3PhysGrowRange(pVM, pVM->vmm.s.u64CallHostArg);
2174	break;
2175	}
2176
2177	/*
2178	* This is a noop. We just take this route to avoid unnecessary
2179	* tests in the loops.
2180	*/
2181	case VMMCALLHOST_VMM_LOGGER_FLUSH:
2182	break;
2183
2184	/*
2185	* Set the VM error message.
2186	*/
2187	case VMMCALLHOST_VM_SET_ERROR:
2188	VMR3SetErrorWorker(pVM);
2189	break;
2190
2191	/*
2192	* Set the VM runtime error message.
2193	*/
2194	case VMMCALLHOST_VM_SET_RUNTIME_ERROR:
2195	VMR3SetRuntimeErrorWorker(pVM);
2196	break;
2197
2198	default:
2199	AssertMsgFailed(("enmCallHostOperation=%d\n", pVM->vmm.s.enmCallHostOperation));
2200	return VERR_INTERNAL_ERROR;
2201	}
2202
2203	pVM->vmm.s.enmCallHostOperation = VMMCALLHOST_INVALID;
2204	return VINF_SUCCESS;
2205	}
2206
2207
2208
2209	/**
2210	* Structure to pass to DBGFR3Info() and for doing all other
2211	* output during fatal dump.
2212	*/
2213	typedef struct VMMR3FATALDUMPINFOHLP
2214	{
2215	/** The helper core. */
2216	DBGFINFOHLP Core;
2217	/** The release logger instance. */
2218	PRTLOGGER pRelLogger;
2219	/** The saved release logger flags. */
2220	RTUINT fRelLoggerFlags;
2221	/** The logger instance. */
2222	PRTLOGGER pLogger;
2223	/** The saved logger flags. */
2224	RTUINT fLoggerFlags;
2225	/** The saved logger destination flags. */
2226	RTUINT fLoggerDestFlags;
2227	/** Whether to output to stderr or not. */
2228	bool fStdErr;
2229	} VMMR3FATALDUMPINFOHLP, *PVMMR3FATALDUMPINFOHLP;
2230	typedef const VMMR3FATALDUMPINFOHLP *PCVMMR3FATALDUMPINFOHLP;
2231
2232
2233	/**
2234	* Print formatted string.
2235	*
2236	* @param pHlp Pointer to this structure.
2237	* @param pszFormat The format string.
2238	* @param ... Arguments.
2239	*/
2240	static DECLCALLBACK(void) vmmR3FatalDumpInfoHlp_pfnPrintf(PCDBGFINFOHLP pHlp, const char *pszFormat, ...)
2241	{
2242	va_list args;
2243	va_start(args, pszFormat);
2244	pHlp->pfnPrintfV(pHlp, pszFormat, args);
2245	va_end(args);
2246	}
2247
2248
2249	/**
2250	* Print formatted string.
2251	*
2252	* @param pHlp Pointer to this structure.
2253	* @param pszFormat The format string.
2254	* @param args Argument list.
2255	*/
2256	static DECLCALLBACK(void) vmmR3FatalDumpInfoHlp_pfnPrintfV(PCDBGFINFOHLP pHlp, const char *pszFormat, va_list args)
2257	{
2258	PCVMMR3FATALDUMPINFOHLP pMyHlp = (PCVMMR3FATALDUMPINFOHLP)pHlp;
2259
2260	if (pMyHlp->pRelLogger)
2261	{
2262	va_list args2;
2263	va_copy(args2, args);
2264	RTLogLoggerV(pMyHlp->pRelLogger, pszFormat, args2);
2265	va_end(args2);
2266	}
2267	if (pMyHlp->pLogger)
2268	{
2269	va_list args2;
2270	va_copy(args2, args);
2271	RTLogLoggerV(pMyHlp->pLogger, pszFormat, args);
2272	va_end(args2);
2273	}
2274	if (pMyHlp->fStdErr)
2275	{
2276	va_list args2;
2277	va_copy(args2, args);
2278	RTStrmPrintfV(g_pStdErr, pszFormat, args);
2279	va_end(args2);
2280	}
2281	}
2282
2283
2284	/**
2285	* Initializes the fatal dump output helper.
2286	*
2287	* @param pHlp The structure to initialize.
2288	*/
2289	static void vmmR3FatalDumpInfoHlpInit(PVMMR3FATALDUMPINFOHLP pHlp)
2290	{
2291	memset(pHlp, 0, sizeof(*pHlp));
2292
2293	pHlp->Core.pfnPrintf = vmmR3FatalDumpInfoHlp_pfnPrintf;
2294	pHlp->Core.pfnPrintfV = vmmR3FatalDumpInfoHlp_pfnPrintfV;
2295
2296	/*
2297	* The loggers.
2298	*/
2299	pHlp->pRelLogger = RTLogRelDefaultInstance();
2300	#ifndef LOG_ENABLED
2301	if (!pHlp->pRelLogger)
2302	#endif
2303	pHlp->pLogger = RTLogDefaultInstance();
2304
2305	if (pHlp->pRelLogger)
2306	{
2307	pHlp->fRelLoggerFlags = pHlp->pRelLogger->fFlags;
2308	pHlp->pRelLogger->fFlags &= ~(RTLOGFLAGS_BUFFERED \| RTLOGFLAGS_DISABLED);
2309	}
2310
2311	if (pHlp->pLogger)
2312	{
2313	pHlp->fLoggerFlags = pHlp->pLogger->fFlags;
2314	pHlp->fLoggerDestFlags = pHlp->pLogger->fDestFlags;
2315	pHlp->pLogger->fFlags &= ~(RTLOGFLAGS_BUFFERED \| RTLOGFLAGS_DISABLED);
2316	#ifndef DEBUG_sandervl
2317	pHlp->pLogger->fDestFlags \|= RTLOGDEST_DEBUGGER;
2318	#endif
2319	}
2320
2321	/*
2322	* Check if we need write to stderr.
2323	*/
2324	pHlp->fStdErr = (!pHlp->pRelLogger \|\| !(pHlp->pRelLogger->fDestFlags & (RTLOGDEST_STDOUT \| RTLOGDEST_STDERR)))
2325	&& (!pHlp->pLogger \|\| !(pHlp->pLogger->fDestFlags & (RTLOGDEST_STDOUT \| RTLOGDEST_STDERR)));
2326	}
2327
2328
2329	/**
2330	* Deletes the fatal dump output helper.
2331	*
2332	* @param pHlp The structure to delete.
2333	*/
2334	static void vmmR3FatalDumpInfoHlpDelete(PVMMR3FATALDUMPINFOHLP pHlp)
2335	{
2336	if (pHlp->pRelLogger)
2337	{
2338	RTLogFlush(pHlp->pRelLogger);
2339	pHlp->pRelLogger->fFlags = pHlp->fRelLoggerFlags;
2340	}
2341
2342	if (pHlp->pLogger)
2343	{
2344	RTLogFlush(pHlp->pLogger);
2345	pHlp->pLogger->fFlags = pHlp->fLoggerFlags;
2346	pHlp->pLogger->fDestFlags = pHlp->fLoggerDestFlags;
2347	}
2348	}
2349
2350
2351	/**
2352	* Dumps the VM state on a fatal error.
2353	*
2354	* @param pVM VM Handle.
2355	* @param rcErr VBox status code.
2356	*/
2357	VMMR3DECL(void) VMMR3FatalDump(PVM pVM, int rcErr)
2358	{
2359	/*
2360	* Create our output helper and sync it with the log settings.
2361	* This helper will be used for all the output.
2362	*/
2363	VMMR3FATALDUMPINFOHLP Hlp;
2364	PCDBGFINFOHLP pHlp = &Hlp.Core;
2365	vmmR3FatalDumpInfoHlpInit(&Hlp);
2366
2367	/*
2368	* Header.
2369	*/
2370	pHlp->pfnPrintf(pHlp,
2371	"!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n"
2372	"!!\n"
2373	"!! Guru Meditation %d (%Vrc)\n"
2374	"!!\n",
2375	rcErr, rcErr);
2376
2377	/*
2378	* Continue according to context.
2379	*/
2380	bool fDoneHyper = false;
2381	switch (rcErr)
2382	{
2383	/*
2384	* Hyper visor errors.
2385	*/
2386	case VINF_EM_DBG_HYPER_ASSERTION:
2387	pHlp->pfnPrintf(pHlp, "%s%s!!\n", VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
2388	/* fall thru */
2389	case VERR_TRPM_DONT_PANIC:
2390	case VERR_TRPM_PANIC:
2391	case VINF_EM_RAW_STALE_SELECTOR:
2392	case VINF_EM_RAW_IRET_TRAP:
2393	case VINF_EM_DBG_HYPER_BREAKPOINT:
2394	case VINF_EM_DBG_HYPER_STEPPED:
2395	{
2396	/* Trap? */
2397	uint32_t uEIP = CPUMGetHyperEIP(pVM);
2398	TRPMEVENT enmType;
2399	uint8_t u8TrapNo = 0xce;
2400	RTGCUINT uErrorCode = 0xdeadface;
2401	RTGCUINTPTR uCR2 = 0xdeadface;
2402	int rc2 = TRPMQueryTrapAll(pVM, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
2403	if (VBOX_SUCCESS(rc2))
2404	pHlp->pfnPrintf(pHlp,
2405	"!! TRAP=%02x ERRCD=%VGv CR2=%VGv EIP=%VGv Type=%d\n",
2406	u8TrapNo, uErrorCode, uCR2, uEIP, enmType);
2407	else
2408	pHlp->pfnPrintf(pHlp,
2409	"!! EIP=%VGv NOTRAP\n",
2410	uEIP);
2411
2412	/*
2413	* Try figure out where eip is.
2414	*/
2415	/** @todo make query call for core code or move this function to VMM. */
2416	/* core code? */
2417	//if (uEIP - (RTGCUINTPTR)pVM->vmm.s.pvGCCoreCode < pVM->vmm.s.cbCoreCode)
2418	// pHlp->pfnPrintf(pHlp,
2419	// "!! EIP is in CoreCode, offset %#x\n",
2420	// uEIP - (RTGCUINTPTR)pVM->vmm.s.pvGCCoreCode);
2421	//else
2422	{ /* ask PDM */
2423	/** @todo ask DBGFR3Sym later. */
2424	char szModName[64];
2425	RTGCPTR GCPtrMod;
2426	char szNearSym1[260];
2427	RTGCPTR GCPtrNearSym1;
2428	char szNearSym2[260];
2429	RTGCPTR GCPtrNearSym2;
2430	int rc = PDMR3QueryModFromEIP(pVM, uEIP,
2431	&szModName[0], sizeof(szModName), &GCPtrMod,
2432	&szNearSym1[0], sizeof(szNearSym1), &GCPtrNearSym1,
2433	&szNearSym2[0], sizeof(szNearSym2), &GCPtrNearSym2);
2434	if (VBOX_SUCCESS(rc))
2435	{
2436	pHlp->pfnPrintf(pHlp,
2437	"!! EIP in %s (%p) at rva %x near symbols:\n"
2438	"!! %VGv rva %VGv off %08x %s\n"
2439	"!! %VGv rva %VGv off -%08x %s\n",
2440	szModName, GCPtrMod, (unsigned)(uEIP - GCPtrMod),
2441	GCPtrNearSym1, GCPtrNearSym1 - GCPtrMod, (unsigned)(uEIP - GCPtrNearSym1), szNearSym1,
2442	GCPtrNearSym2, GCPtrNearSym2 - GCPtrMod, (unsigned)(GCPtrNearSym2 - uEIP), szNearSym2);
2443	}
2444	else
2445	pHlp->pfnPrintf(pHlp,
2446	"!! EIP is not in any code known to VMM!\n");
2447	}
2448
2449	/* Disassemble the instruction. */
2450	char szInstr[256];
2451	rc2 = DBGFR3DisasInstrEx(pVM, 0, 0, DBGF_DISAS_FLAGS_CURRENT_HYPER, &szInstr[0], sizeof(szInstr), NULL);
2452	if (VBOX_SUCCESS(rc2))
2453	pHlp->pfnPrintf(pHlp,
2454	"!! %s\n", szInstr);
2455
2456	/* Dump the hypervisor cpu state. */
2457	pHlp->pfnPrintf(pHlp,
2458	"!!\n"
2459	"!!\n"
2460	"!!\n");
2461	rc2 = DBGFR3Info(pVM, "cpumhyper", "verbose", pHlp);
2462	fDoneHyper = true;
2463
2464	/* Callstack. */
2465	DBGFSTACKFRAME Frame = {0};
2466	rc2 = DBGFR3StackWalkBeginHyper(pVM, &Frame);
2467	if (VBOX_SUCCESS(rc2))
2468	{
2469	pHlp->pfnPrintf(pHlp,
2470	"!!\n"
2471	"!! Call Stack:\n"
2472	"!!\n"
2473	"EBP Ret EBP Ret CS:EIP Arg0 Arg1 Arg2 Arg3 CS:EIP Symbol [line]\n");
2474	do
2475	{
2476	pHlp->pfnPrintf(pHlp,
2477	"%08RX32 %08RX32 %04RX32:%08RX32 %08RX32 %08RX32 %08RX32 %08RX32",
2478	(uint32_t)Frame.AddrFrame.off,
2479	(uint32_t)Frame.AddrReturnFrame.off,
2480	(uint32_t)Frame.AddrReturnPC.Sel,
2481	(uint32_t)Frame.AddrReturnPC.off,
2482	Frame.Args.au32[0],
2483	Frame.Args.au32[1],
2484	Frame.Args.au32[2],
2485	Frame.Args.au32[3]);
2486	pHlp->pfnPrintf(pHlp, " %RTsel:%08RGv", Frame.AddrPC.Sel, Frame.AddrPC.off);
2487	if (Frame.pSymPC)
2488	{
2489	RTGCINTPTR offDisp = Frame.AddrPC.FlatPtr - Frame.pSymPC->Value;
2490	if (offDisp > 0)
2491	pHlp->pfnPrintf(pHlp, " %s+%llx", Frame.pSymPC->szName, (int64_t)offDisp);
2492	else if (offDisp < 0)
2493	pHlp->pfnPrintf(pHlp, " %s-%llx", Frame.pSymPC->szName, -(int64_t)offDisp);
2494	else
2495	pHlp->pfnPrintf(pHlp, " %s", Frame.pSymPC->szName);
2496	}
2497	if (Frame.pLinePC)
2498	pHlp->pfnPrintf(pHlp, " [%s @ 0i%d]", Frame.pLinePC->szFilename, Frame.pLinePC->uLineNo);
2499	pHlp->pfnPrintf(pHlp, "\n");
2500
2501	/* next */
2502	rc2 = DBGFR3StackWalkNext(pVM, &Frame);
2503	} while (VBOX_SUCCESS(rc2));
2504	DBGFR3StackWalkEnd(pVM, &Frame);
2505	}
2506
2507	/* raw stack */
2508	pHlp->pfnPrintf(pHlp,
2509	"!!\n"
2510	"!! Raw stack (mind the direction).\n"
2511	"!!\n"
2512	"%.*Vhxd\n",
2513	VMM_STACK_SIZE, (char *)pVM->vmm.s.pbHCStack);
2514	break;
2515	}
2516
2517	default:
2518	{
2519	break;
2520	}
2521
2522	} /* switch (rcErr) */
2523
2524
2525	/*
2526	* Dump useful state information.
2527	*/
2528	/** @todo convert these dumpers to DBGFR3Info() handlers!!! */
2529	pHlp->pfnPrintf(pHlp,
2530	"!!\n"
2531	"!! PGM Access Handlers & Stuff:\n"
2532	"!!\n");
2533	PGMR3DumpMappings(pVM);
2534
2535
2536	/*
2537	* Generic info dumper loop.
2538	*/
2539	static struct
2540	{
2541	const char *pszInfo;
2542	const char *pszArgs;
2543	} const aInfo[] =
2544	{
2545	{ "hma", NULL },
2546	{ "cpumguest", "verbose" },
2547	{ "cpumhyper", "verbose" },
2548	{ "cpumhost", "verbose" },
2549	{ "mode", "all" },
2550	{ "cpuid", "verbose" },
2551	{ "gdt", NULL },
2552	{ "ldt", NULL },
2553	//{ "tss", NULL },
2554	{ "ioport", NULL },
2555	{ "mmio", NULL },
2556	{ "phys", NULL },
2557	//{ "pgmpd", NULL }, - doesn't always work at init time...
2558	{ "timers", NULL },
2559	{ "activetimers", NULL },
2560	{ "handlers", "phys virt stats" },
2561	{ "cfgm", NULL },
2562	};
2563	for (unsigned i = 0; i < ELEMENTS(aInfo); i++)
2564	{
2565	if (fDoneHyper && !strcmp(aInfo[i].pszInfo, "cpumhyper"))
2566	continue;
2567	pHlp->pfnPrintf(pHlp,
2568	"!!\n"
2569	"!! {%s, %s}\n"
2570	"!!\n",
2571	aInfo[i].pszInfo, aInfo[i].pszArgs);
2572	DBGFR3Info(pVM, aInfo[i].pszInfo, aInfo[i].pszArgs, pHlp);
2573	}
2574
2575	/* done */
2576	pHlp->pfnPrintf(pHlp,
2577	"!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n");
2578
2579
2580	/*
2581	* Delete the output instance (flushing and restoring of flags).
2582	*/
2583	vmmR3FatalDumpInfoHlpDelete(&Hlp);
2584	}
2585

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source: vbox/trunk/src/VBox/VMM/VMM.cpp@ 3068

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