VirtualBox

source: vbox/trunk/src/VBox/VMM/VMM.cpp@ 439

Last change on this file since 439 was 421, checked in by vboxsync, 18 years ago

Stop GCC4 from being 'clever'.
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1/* $Id: VMM.cpp 421 2007-01-29 18:40:07Z vboxsync $ */
2/** @file
3 * VMM - The Virtual Machine Monitor Core.
4 */
5
6/*
7 * Copyright (C) 2006 InnoTek Systemberatung GmbH
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License as published by the Free Software Foundation,
13 * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14 * distribution. VirtualBox OSE is distributed in the hope that it will
15 * be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * If you received this file as part of a commercial VirtualBox
18 * distribution, then only the terms of your commercial VirtualBox
19 * license agreement apply instead of the previous paragraph.
20 */
21
22#if 0 //defined(__AMD64__) && !defined(__WIN__)
23# define NO_SUPCALLR0VMM
24#endif
25
26/** @page pg_vmm VMM - The Virtual Machine Monitor
27 *
28 * !Revise this! It's already incorrect!
29 *
30 * The Virtual Machine Monitor (VMM) is the core of the virtual machine. It
31 * manages the alternate reality; controlling the virtualization, managing
32 * resources, tracking CPU state, it's resources and so on...
33 *
34 * We will split the VMM into smaller entities:
35 *
36 * - Virtual Machine Core Monitor (VMCM), which purpose it is to
37 * provide ring and world switching, that including routing
38 * interrupts to the host OS and traps to the appropriate trap
39 * handlers. It will implement an external interface for
40 * managing trap handlers.
41 *
42 * - CPU Monitor (CM), tracking the state of the CPU (in the alternate
43 * reality) and implementing external interfaces to read and change
44 * the state.
45 *
46 * - Memory Monitor (MM), which purpose it is to virtualize physical
47 * pages, segment descriptor tables, interrupt descriptor tables, task
48 * segments, and keep track of all memory providing external interfaces
49 * to access content and map pages. (Internally splitt into smaller entities!)
50 *
51 * - IO Monitor (IOM), which virtualizes in and out I/O operations. It
52 * interacts with the MM to implement memory mapped I/O. External
53 * interfaces for adding and removing I/O ranges are implemented.
54 *
55 * - External Interrupt Monitor (EIM), which purpose it is to manage
56 * interrupts generated by virtual devices. This monitor provides
57 * an interfaces for raising interrupts which is accessible at any
58 * time and from all thread.
59 * <p>
60 * A subentity of the EIM is the vitual Programmable Interrupt
61 * Controller Device (VPICD), and perhaps a virtual I/O Advanced
62 * Programmable Interrupt Controller Device (VAPICD).
63 *
64 * - Direct Memory Access Monitor (DMAM), which purpose it is to support
65 * virtual device using the DMA controller. Interfaces must be as the
66 * EIM interfaces independent and threadable.
67 * <p>
68 * A subentity of the DMAM is a virtual DMA Controller Device (VDMACD).
69 *
70 *
71 * Entities working on a higher level:
72 *
73 * - Device Manager (DM), which is a support facility for virtualized
74 * hardware. This provides generic facilities for efficient device
75 * virtualization. It will manage device attaching and detaching
76 * conversing with EIM and IOM.
77 *
78 * - Debugger Facility (DBGF) provides the basic features for
79 * debugging the alternate reality execution.
80 *
81 *
82 *
83 * @section pg_vmm_s_use_cases Use Cases
84 *
85 * @subsection pg_vmm_s_use_case_boot Bootstrap
86 *
87 * - Basic Init:
88 * - Init SUPDRV.
89 *
90 * - Init Virtual Machine Instance:
91 * - Load settings.
92 * - Check resource requirements (memory, com, stuff).
93 *
94 * - Init Host Ring 3 part:
95 * - Init Core code.
96 * - Load Pluggable Components.
97 * - Init Pluggable Components.
98 *
99 * - Init Host Ring 0 part:
100 * - Load Core (core = core components like VMM, RMI, CA, and so on) code.
101 * - Init Core code.
102 * - Load Pluggable Component code.
103 * - Init Pluggable Component code.
104 *
105 * - Allocate first chunk of memory and pin it down. This block of memory
106 * will fit the following pieces:
107 * - Virtual Machine Instance data. (Config, CPU state, VMM state, ++)
108 * (This is available from everywhere (at different addresses though)).
109 * - VMM Guest Context code.
110 * - Pluggable devices Guest Context code.
111 * - Page tables (directory and everything) for the VMM Guest
112 *
113 * - Setup Guest (Ring 0) part:
114 * - Setup initial page tables (i.e. directory all the stuff).
115 * - Load Core Guest Context code.
116 * - Load Pluggable Devices Guest Context code.
117 *
118 *
119 */
120
121
122/*******************************************************************************
123* Header Files *
124*******************************************************************************/
125#define LOG_GROUP LOG_GROUP_VMM
126#include <VBox/vmm.h>
127#include <VBox/vmapi.h>
128#include <VBox/pgm.h>
129#include <VBox/cfgm.h>
130#include <VBox/pdm.h>
131#include <VBox/cpum.h>
132#include <VBox/mm.h>
133#include <VBox/iom.h>
134#include <VBox/trpm.h>
135#include <VBox/selm.h>
136#include <VBox/em.h>
137#include <VBox/sup.h>
138#include <VBox/dbgf.h>
139#include <VBox/csam.h>
140#include <VBox/patm.h>
141#include <VBox/rem.h>
142#include <VBox/ssm.h>
143#include <VBox/tm.h>
144#include "VMMInternal.h"
145#include "VMMSwitcher/VMMSwitcher.h"
146#include <VBox/vm.h>
147#include <VBox/err.h>
148#include <VBox/param.h>
149#include <VBox/version.h>
150#include <VBox/x86.h>
151#include <iprt/assert.h>
152#include <iprt/alloc.h>
153#include <iprt/asm.h>
154#include <iprt/time.h>
155#include <iprt/stream.h>
156#include <iprt/string.h>
157#include <iprt/stdarg.h>
158#include <iprt/ctype.h>
159
160
161
162/** The saved state version. */
163#define VMM_SAVED_STATE_VERSION 3
164
165
166/*******************************************************************************
167* Internal Functions *
168*******************************************************************************/
169static DECLCALLBACK(int) vmmR3Save(PVM pVM, PSSMHANDLE pSSM);
170static DECLCALLBACK(int) vmmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
171static DECLCALLBACK(void) vmmR3YieldEMT(PVM pVM, PTMTIMER pTimer, void *pvUser);
172static int vmmR3ServiceCallHostRequest(PVM pVM);
173
174
175/*******************************************************************************
176* Global Variables *
177*******************************************************************************/
178/** Array of switcher defininitions.
179 * The type and index shall match!
180 */
181static PVMMSWITCHERDEF s_apSwitchers[VMMSWITCHER_MAX] =
182{
183 NULL, /* invalid entry */
184#ifndef __AMD64__
185 &vmmR3Switcher32BitTo32Bit_Def,
186 &vmmR3Switcher32BitToPAE_Def,
187 NULL, //&vmmR3Switcher32BitToAMD64_Def,
188 &vmmR3SwitcherPAETo32Bit_Def,
189 &vmmR3SwitcherPAEToPAE_Def,
190 NULL, //&vmmR3SwitcherPAEToAMD64_Def,
191 NULL, //&vmmR3SwitcherAMD64ToPAE_Def,
192 NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
193#else
194 NULL, //&vmmR3Switcher32BitTo32Bit_Def,
195 NULL, //&vmmR3Switcher32BitToPAE_Def,
196 NULL, //&vmmR3Switcher32BitToAMD64_Def,
197 NULL, //&vmmR3SwitcherPAETo32Bit_Def,
198 NULL, //&vmmR3SwitcherPAEToPAE_Def,
199 NULL, //&vmmR3SwitcherPAEToAMD64_Def,
200 &vmmR3SwitcherAMD64ToPAE_Def,
201 NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
202#endif
203};
204
205
206
207/**
208 * Initiates the core code.
209 *
210 * This is core per VM code which might need fixups and/or for ease of use
211 * are put on linear contiguous backing.
212 *
213 * @returns VBox status code.
214 * @param pVM Pointer to VM structure.
215 */
216static int vmmR3InitCoreCode(PVM pVM)
217{
218 /*
219 * Calc the size.
220 */
221 unsigned cbCoreCode = 0;
222 for (unsigned iSwitcher = 0; iSwitcher < ELEMENTS(s_apSwitchers); iSwitcher++)
223 {
224 pVM->vmm.s.aoffSwitchers[iSwitcher] = cbCoreCode;
225 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
226 if (pSwitcher)
227 {
228 AssertRelease((unsigned)pSwitcher->enmType == iSwitcher);
229 cbCoreCode += RT_ALIGN_32(pSwitcher->cbCode + 1, 32);
230 }
231 }
232
233 /*
234 * Allocate continguous pages for switchers and deal with
235 * conflicts in the intermediate mapping of the code.
236 */
237 pVM->vmm.s.cbCoreCode = RT_ALIGN_32(cbCoreCode, PAGE_SIZE);
238 pVM->vmm.s.pvHCCoreCodeR3 = SUPContAlloc2(pVM->vmm.s.cbCoreCode, &pVM->vmm.s.pvHCCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
239 int rc = VERR_NO_MEMORY;
240 if (pVM->vmm.s.pvHCCoreCodeR3)
241 {
242 rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvHCCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
243 if (rc == VERR_PGM_MAPPINGS_FIX_CONFLICT)
244 {
245 /* try more allocations. */
246 struct
247 {
248 void *pvR0;
249 void *pvR3;
250 RTHCPHYS HCPhys;
251 } aBadTries[16];
252 unsigned i = 0;
253 do
254 {
255 aBadTries[i].pvR3 = pVM->vmm.s.pvHCCoreCodeR3;
256 aBadTries[i].pvR0 = pVM->vmm.s.pvHCCoreCodeR0;
257 aBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
258 i++;
259 pVM->vmm.s.pvHCCoreCodeR0 = NIL_RTR0PTR;
260 pVM->vmm.s.HCPhysCoreCode = NIL_RTHCPHYS;
261 pVM->vmm.s.pvHCCoreCodeR3 = SUPContAlloc2(pVM->vmm.s.cbCoreCode, &pVM->vmm.s.pvHCCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
262 if (!pVM->vmm.s.pvHCCoreCodeR3)
263 break;
264 rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvHCCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
265 } while ( rc == VERR_PGM_MAPPINGS_FIX_CONFLICT
266 && i < ELEMENTS(aBadTries) - 1);
267
268 /* cleanup */
269 if (VBOX_FAILURE(rc))
270 {
271 aBadTries[i].pvR3 = pVM->vmm.s.pvHCCoreCodeR3;
272 aBadTries[i].pvR0 = pVM->vmm.s.pvHCCoreCodeR0;
273 aBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
274 i++;
275 LogRel(("Failed to allocated and map core code: rc=%Vrc\n", rc));
276 }
277 while (i-- > 0)
278 {
279 LogRel(("Core code alloc attempt #%d: pvR3=%p pvR0=%p HCPhys=%VHp\n",
280 i, aBadTries[i].pvR3, aBadTries[i].pvR0, aBadTries[i].HCPhys));
281 SUPContFree(aBadTries[i].pvR3);
282 }
283 }
284 }
285 if (VBOX_SUCCESS(rc))
286 {
287 /*
288 * copy the code.
289 */
290 for (unsigned iSwitcher = 0; iSwitcher < ELEMENTS(s_apSwitchers); iSwitcher++)
291 {
292 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
293 if (pSwitcher)
294 memcpy((uint8_t *)pVM->vmm.s.pvHCCoreCodeR3 + pVM->vmm.s.aoffSwitchers[iSwitcher],
295 pSwitcher->pvCode, pSwitcher->cbCode);
296 }
297
298 /*
299 * Map the code into the GC address space.
300 */
301 rc = MMR3HyperMapHCPhys(pVM, pVM->vmm.s.pvHCCoreCodeR3, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, "Core Code", &pVM->vmm.s.pvGCCoreCode);
302 if (VBOX_SUCCESS(rc))
303 {
304 MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
305 /*
306 * Finally, PGM probably have selected a switcher already but we need
307 * to do get the addresses so we'll reselect it.
308 * This may legally fail so, we're ignoring the rc.
309 */
310 VMMR3SelectSwitcher(pVM, pVM->vmm.s.enmSwitcher);
311 return rc;
312 }
313
314 /* shit */
315 AssertMsgFailed(("PGMR3Map(,%VGv, %VGp, %#x, 0) failed with rc=%Vrc\n", pVM->vmm.s.pvGCCoreCode, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, rc));
316 SUPContFree(pVM->vmm.s.pvHCCoreCodeR3);
317 }
318 else
319 VMSetError(pVM, rc, RT_SRC_POS,
320 N_("Failed to allocate %d bytes of contiguous memory for the world switcher code."),
321 cbCoreCode);
322
323 pVM->vmm.s.pvHCCoreCodeR3 = NULL;
324 pVM->vmm.s.pvHCCoreCodeR0 = NIL_RTR0PTR;
325 pVM->vmm.s.pvGCCoreCode = 0;
326 return rc;
327}
328
329
330/**
331 * Initializes the VMM.
332 *
333 * @returns VBox status code.
334 * @param pVM The VM to operate on.
335 */
336VMMR3DECL(int) VMMR3Init(PVM pVM)
337{
338 LogFlow(("VMMR3Init\n"));
339
340 /*
341 * Assert alignment, sizes and order.
342 */
343 AssertMsg(pVM->vmm.s.offVM == 0, ("Already initialized!\n"));
344 AssertMsg(sizeof(pVM->vmm.padding) >= sizeof(pVM->vmm.s),
345 ("pVM->vmm.padding is too small! vmm.padding %d while vmm.s is %d\n",
346 sizeof(pVM->vmm.padding), sizeof(pVM->vmm.s)));
347
348 /*
349 * Init basic VM VMM members.
350 */
351 pVM->vmm.s.offVM = RT_OFFSETOF(VM, vmm);
352 int rc = CFGMR3QueryU32(CFGMR3GetRoot(pVM), "YieldEMTInterval", &pVM->vmm.s.cYieldEveryMillies);
353 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
354 pVM->vmm.s.cYieldEveryMillies = 23; /* Value arrived at after experimenting with the grub boot prompt. */
355 //pVM->vmm.s.cYieldEveryMillies = 8; //debugging
356 else
357 AssertMsgRCReturn(rc, ("Configuration error. Failed to query \"YieldEMTInterval\", rc=%Vrc\n", rc), rc);
358
359 /*
360 * Register the saved state data unit.
361 */
362 rc = SSMR3RegisterInternal(pVM, "vmm", 1, VMM_SAVED_STATE_VERSION, VMM_STACK_SIZE + sizeof(RTGCPTR),
363 NULL, vmmR3Save, NULL,
364 NULL, vmmR3Load, NULL);
365 if (VBOX_FAILURE(rc))
366 return rc;
367
368 /* GC switchers are enabled by default. Turned off by HWACCM. */
369 pVM->vmm.s.fSwitcherDisabled = false;
370
371 /*
372 * Init core code.
373 */
374 rc = vmmR3InitCoreCode(pVM);
375 if (VBOX_SUCCESS(rc))
376 {
377 /*
378 * Allocate & init VMM GC stack.
379 * The stack pages are also used by the VMM R0 when VMMR0CallHost is invoked.
380 * (The page protection is modifed during R3 init completion.)
381 */
382#ifdef VBOX_STRICT_VMM_STACK
383 rc = MMHyperAlloc(pVM, VMM_STACK_SIZE + PAGE_SIZE + PAGE_SIZE, PAGE_SIZE, MM_TAG_VMM, (void **)&pVM->vmm.s.pbHCStack);
384#else
385 rc = MMHyperAlloc(pVM, VMM_STACK_SIZE, PAGE_SIZE, MM_TAG_VMM, (void **)&pVM->vmm.s.pbHCStack);
386#endif
387 if (VBOX_SUCCESS(rc))
388 {
389 /* Set HC and GC stack pointers to top of stack. */
390 pVM->vmm.s.CallHostR0JmpBuf.pvSavedStack = (RTR0PTR)pVM->vmm.s.pbHCStack;
391 pVM->vmm.s.pbGCStack = MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack);
392 pVM->vmm.s.pbGCStackBottom = pVM->vmm.s.pbGCStack + VMM_STACK_SIZE;
393 AssertRelease(pVM->vmm.s.pbGCStack);
394
395 /* Set hypervisor eip. */
396 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStack);
397
398 /*
399 * Allocate GC & R0 Logger instances (they are finalized in the relocator).
400 */
401#ifdef LOG_ENABLED
402 PRTLOGGER pLogger = RTLogDefaultInstance();
403 if (pLogger)
404 {
405 pVM->vmm.s.cbLoggerGC = RT_OFFSETOF(RTLOGGERGC, afGroups[pLogger->cGroups]);
406 rc = MMHyperAlloc(pVM, pVM->vmm.s.cbLoggerGC, 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pLoggerHC);
407 if (VBOX_SUCCESS(rc))
408 {
409 pVM->vmm.s.pLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pLoggerHC);
410
411/*
412 * Ring-0 logging isn't 100% safe yet (thread id reuse / process exit cleanup), so
413 * you have to sign up here by adding your defined(DEBUG_<userid>) to the #if.
414 *
415 * If you want to log in non-debug modes, you'll have to remember to change SUPDRvShared.c
416 * to not stub all the log functions.
417 */
418# ifdef DEBUG_sandervl
419 rc = MMHyperAlloc(pVM, RT_OFFSETOF(VMMR0LOGGER, Logger.afGroups[pLogger->cGroups]),
420 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pR0Logger);
421 if (VBOX_SUCCESS(rc))
422 {
423 pVM->vmm.s.pR0Logger->pVM = pVM;
424 //pVM->vmm.s.pR0Logger->fCreated = false;
425 pVM->vmm.s.pR0Logger->cbLogger = RT_OFFSETOF(RTLOGGER, afGroups[pLogger->cGroups]);
426 }
427# endif
428 }
429 }
430#endif /* LOG_ENABLED */
431
432#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
433 /*
434 * Allocate GC Release Logger instances (finalized in the relocator).
435 */
436 if (VBOX_SUCCESS(rc))
437 {
438 PRTLOGGER pRelLogger = RTLogRelDefaultInstance();
439 if (pRelLogger)
440 {
441 pVM->vmm.s.cbRelLoggerGC = RT_OFFSETOF(RTLOGGERGC, afGroups[pRelLogger->cGroups]);
442 rc = MMHyperAlloc(pVM, pVM->vmm.s.cbRelLoggerGC, 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pRelLoggerHC);
443 if (VBOX_SUCCESS(rc))
444 pVM->vmm.s.pRelLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pRelLoggerHC);
445 }
446 }
447#endif /* VBOX_WITH_GC_AND_R0_RELEASE_LOG */
448
449#ifdef VBOX_WITH_NMI
450 /*
451 * Allocate mapping for the host APIC.
452 */
453 if (VBOX_SUCCESS(rc))
454 {
455 rc = MMR3HyperReserve(pVM, PAGE_SIZE, "Host APIC", &pVM->vmm.s.GCPtrApicBase);
456 AssertRC(rc);
457 }
458#endif
459 if (VBOX_SUCCESS(rc))
460 {
461 rc = RTCritSectInit(&pVM->vmm.s.CritSectVMLock);
462 if (VBOX_SUCCESS(rc))
463 {
464 /*
465 * Statistics.
466 */
467 STAM_REG(pVM, &pVM->vmm.s.StatRunGC, STAMTYPE_COUNTER, "/VMM/RunGC", STAMUNIT_OCCURENCES, "Number of context switches.");
468 STAM_REG(pVM, &pVM->vmm.s.StatGCRetNormal, STAMTYPE_COUNTER, "/VMM/GCRet/Normal", STAMUNIT_OCCURENCES, "Number of VINF_SUCCESS returns.");
469 STAM_REG(pVM, &pVM->vmm.s.StatGCRetInterrupt, STAMTYPE_COUNTER, "/VMM/GCRet/Interrupt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT returns.");
470 STAM_REG(pVM, &pVM->vmm.s.StatGCRetInterruptHyper, STAMTYPE_COUNTER, "/VMM/GCRet/InterruptHyper", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT_HYPER returns.");
471 STAM_REG(pVM, &pVM->vmm.s.StatGCRetGuestTrap, STAMTYPE_COUNTER, "/VMM/GCRet/GuestTrap", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_GUEST_TRAP returns.");
472 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRingSwitch, STAMTYPE_COUNTER, "/VMM/GCRet/RingSwitch", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_RING_SWITCH returns.");
473 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRingSwitchInt, STAMTYPE_COUNTER, "/VMM/GCRet/RingSwitchInt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_RING_SWITCH_INT returns.");
474 STAM_REG(pVM, &pVM->vmm.s.StatGCRetExceptionPrivilege, STAMTYPE_COUNTER, "/VMM/GCRet/ExceptionPrivilege", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_EXCEPTION_PRIVILEGED returns.");
475 STAM_REG(pVM, &pVM->vmm.s.StatGCRetStaleSelector, STAMTYPE_COUNTER, "/VMM/GCRet/StaleSelector", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_STALE_SELECTOR returns.");
476 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIRETTrap, STAMTYPE_COUNTER, "/VMM/GCRet/IRETTrap", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_IRET_TRAP returns.");
477 STAM_REG(pVM, &pVM->vmm.s.StatGCRetEmulate, STAMTYPE_COUNTER, "/VMM/GCRet/Emulate", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION returns.");
478 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchEmulate, STAMTYPE_COUNTER, "/VMM/GCRet/PatchEmulate", STAMUNIT_OCCURENCES, "Number of VINF_PATCH_EMULATE_INSTR returns.");
479 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIORead, STAMTYPE_COUNTER, "/VMM/GCRet/IORead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_IOPORT_READ returns.");
480 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIOWrite, STAMTYPE_COUNTER, "/VMM/GCRet/IOWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_IOPORT_WRITE returns.");
481 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIOReadWrite, STAMTYPE_COUNTER, "/VMM/GCRet/IOReadWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_IOPORT_READWRITE returns.");
482 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIORead, STAMTYPE_COUNTER, "/VMM/GCRet/MMIORead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_READ returns.");
483 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOWrite, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_WRITE returns.");
484 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOReadWrite, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOReadWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_READ_WRITE returns.");
485 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOPatchRead, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOPatchRead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_PATCH_READ returns.");
486 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOPatchWrite, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOPatchWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_PATCH_WRITE returns.");
487 STAM_REG(pVM, &pVM->vmm.s.StatGCRetLDTFault, STAMTYPE_COUNTER, "/VMM/GCRet/LDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_GDT_FAULT returns.");
488 STAM_REG(pVM, &pVM->vmm.s.StatGCRetGDTFault, STAMTYPE_COUNTER, "/VMM/GCRet/GDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_LDT_FAULT returns.");
489 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIDTFault, STAMTYPE_COUNTER, "/VMM/GCRet/IDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_IDT_FAULT returns.");
490 STAM_REG(pVM, &pVM->vmm.s.StatGCRetTSSFault, STAMTYPE_COUNTER, "/VMM/GCRet/TSSFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_TSS_FAULT returns.");
491 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPDFault, STAMTYPE_COUNTER, "/VMM/GCRet/PDFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_PD_FAULT returns.");
492 STAM_REG(pVM, &pVM->vmm.s.StatGCRetCSAMTask, STAMTYPE_COUNTER, "/VMM/GCRet/CSAMTask", STAMUNIT_OCCURENCES, "Number of VINF_CSAM_PENDING_ACTION returns.");
493 STAM_REG(pVM, &pVM->vmm.s.StatGCRetSyncCR3, STAMTYPE_COUNTER, "/VMM/GCRet/SyncCR", STAMUNIT_OCCURENCES, "Number of VINF_PGM_SYNC_CR3 returns.");
494 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMisc, STAMTYPE_COUNTER, "/VMM/GCRet/Misc", STAMUNIT_OCCURENCES, "Number of misc returns.");
495 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchInt3, STAMTYPE_COUNTER, "/VMM/GCRet/PatchInt3", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_INT3 returns.");
496 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchPF, STAMTYPE_COUNTER, "/VMM/GCRet/PatchPF", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_TRAP_PF returns.");
497 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchGP, STAMTYPE_COUNTER, "/VMM/GCRet/PatchGP", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_TRAP_GP returns.");
498 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchIretIRQ, STAMTYPE_COUNTER, "/VMM/GCRet/PatchIret", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PENDING_IRQ_AFTER_IRET returns.");
499 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPageOverflow, STAMTYPE_COUNTER, "/VMM/GCRet/InvlpgOverflow", STAMUNIT_OCCURENCES, "Number of VERR_REM_FLUSHED_PAGES_OVERFLOW returns.");
500 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRescheduleREM, STAMTYPE_COUNTER, "/VMM/GCRet/ScheduleREM", STAMUNIT_OCCURENCES, "Number of VINF_EM_RESCHEDULE_REM returns.");
501 STAM_REG(pVM, &pVM->vmm.s.StatGCRetToR3, STAMTYPE_COUNTER, "/VMM/GCRet/ToR3", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TO_R3 returns.");
502 STAM_REG(pVM, &pVM->vmm.s.StatGCRetTimerPending, STAMTYPE_COUNTER, "/VMM/GCRet/TimerPending", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TIMER_PENDING returns.");
503 STAM_REG(pVM, &pVM->vmm.s.StatGCRetInterruptPending, STAMTYPE_COUNTER, "/VMM/GCRet/InterruptPending", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT_PENDING returns.");
504 STAM_REG(pVM, &pVM->vmm.s.StatGCRetCallHost, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/Misc", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
505 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMGrowRAM, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/GrowRAM", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
506 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPDMLock, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/PDMLock", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
507 STAM_REG(pVM, &pVM->vmm.s.StatGCRetLogFlush, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/LogFlush", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
508 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPDMQueueFlush, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/QueueFlush", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
509 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMPoolGrow, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/PGMPoolGrow",STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
510 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRemReplay, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/REMReplay", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
511 STAM_REG(pVM, &pVM->vmm.s.StatGCRetVMSetError, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/VMSetError", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
512 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMLock, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/PGMLock", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
513 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPATMDuplicateFn, STAMTYPE_COUNTER, "/VMM/GCRet/PATMDuplicateFn", STAMUNIT_OCCURENCES, "Number of VINF_PATM_DUPLICATE_FUNCTION returns.");
514 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMChangeMode, STAMTYPE_COUNTER, "/VMM/GCRet/PGMChangeMode", STAMUNIT_OCCURENCES, "Number of VINF_PGM_CHANGE_MODE returns.");
515 STAM_REG(pVM, &pVM->vmm.s.StatGCRetEmulHlt, STAMTYPE_COUNTER, "/VMM/GCRet/EmulHlt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_EMULATE_INSTR_HLT returns.");
516 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPendingRequest, STAMTYPE_COUNTER, "/VMM/GCRet/PendingRequest", STAMUNIT_OCCURENCES, "Number of VINF_EM_PENDING_REQUEST returns.");
517
518 return VINF_SUCCESS;
519 }
520 AssertRC(rc);
521 }
522 }
523 /** @todo: Need failure cleanup. */
524
525 //more todo in here?
526 //if (VBOX_SUCCESS(rc))
527 //{
528 //}
529 //int rc2 = vmmR3TermCoreCode(pVM);
530 //AssertRC(rc2));
531 }
532
533 return rc;
534}
535
536
537/**
538 * Ring-3 init finalizing.
539 *
540 * @returns VBox status code.
541 * @param pVM The VM handle.
542 */
543VMMR3DECL(int) VMMR3InitFinalize(PVM pVM)
544{
545#ifdef VBOX_STRICT_VMM_STACK
546 /*
547 * Two inaccessible pages at each sides of the stack to catch over/under-flows.
548 */
549 memset(pVM->vmm.s.pbHCStack - PAGE_SIZE, 0xcc, PAGE_SIZE);
550 PGMMapSetPage(pVM, MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack - PAGE_SIZE), PAGE_SIZE, 0);
551 RTMemProtect(pVM->vmm.s.pbHCStack - PAGE_SIZE, PAGE_SIZE, RTMEM_PROT_NONE);
552
553 memset(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE, 0xcc, PAGE_SIZE);
554 PGMMapSetPage(pVM, MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack + VMM_STACK_SIZE), PAGE_SIZE, 0);
555 RTMemProtect(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE, PAGE_SIZE, RTMEM_PROT_NONE);
556#endif
557
558 /*
559 * Set page attributes to r/w for stack pages.
560 */
561 int rc = PGMMapSetPage(pVM, pVM->vmm.s.pbGCStack, VMM_STACK_SIZE, X86_PTE_P | X86_PTE_A | X86_PTE_D | X86_PTE_RW);
562 AssertRC(rc);
563 if (VBOX_SUCCESS(rc))
564 {
565 /*
566 * Create the EMT yield timer.
567 */
568 rc = TMR3TimerCreateInternal(pVM, TMCLOCK_REAL, vmmR3YieldEMT, NULL, "EMT Yielder", &pVM->vmm.s.pYieldTimer);
569 if (VBOX_SUCCESS(rc))
570 rc = TMTimerSetMillies(pVM->vmm.s.pYieldTimer, pVM->vmm.s.cYieldEveryMillies);
571 }
572#ifdef VBOX_WITH_NMI
573 /*
574 * Map the host APIC into GC - This may be host os specific!
575 */
576 if (VBOX_SUCCESS(rc))
577 rc = PGMMap(pVM, pVM->vmm.s.GCPtrApicBase, 0xfee00000, PAGE_SIZE,
578 X86_PTE_P | X86_PTE_RW | X86_PTE_PWT | X86_PTE_PCD | X86_PTE_A | X86_PTE_D);
579#endif
580 return rc;
581}
582
583
584/**
585 * Initializes the R0 VMM.
586 *
587 * @returns VBox status code.
588 * @param pVM The VM to operate on.
589 */
590VMMR3DECL(int) VMMR3InitR0(PVM pVM)
591{
592 int rc;
593
594 /*
595 * Initialize the ring-0 logger if we haven't done so yet.
596 */
597 if ( pVM->vmm.s.pR0Logger
598 && !pVM->vmm.s.pR0Logger->fCreated)
599 {
600 rc = VMMR3UpdateLoggers(pVM);
601 if (VBOX_FAILURE(rc))
602 return rc;
603 }
604
605 /*
606 * Call Ring-0 entry with init code.
607 */
608 for (;;)
609 {
610#ifdef NO_SUPCALLR0VMM
611 //rc = VERR_GENERAL_FAILURE;
612 rc = VINF_SUCCESS;
613#else
614 rc = SUPCallVMMR0(pVM, VMMR0_DO_VMMR0_INIT, (void *)VBOX_VERSION);
615#endif
616 if ( pVM->vmm.s.pR0Logger
617 && pVM->vmm.s.pR0Logger->Logger.offScratch > 0)
618 RTLogFlushToLogger(&pVM->vmm.s.pR0Logger->Logger, NULL);
619 if (rc != VINF_VMM_CALL_HOST)
620 break;
621 rc = vmmR3ServiceCallHostRequest(pVM);
622 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
623 break;
624 break; // remove this when we do setjmp for all ring-0 stuff.
625 }
626
627 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
628 {
629 LogRel(("R0 init failed, rc=%Vra\n", rc));
630 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
631 rc = VERR_INTERNAL_ERROR;
632 }
633 return rc;
634}
635
636
637/**
638 * Initializes the GC VMM.
639 *
640 * @returns VBox status code.
641 * @param pVM The VM to operate on.
642 */
643VMMR3DECL(int) VMMR3InitGC(PVM pVM)
644{
645 /* In VMX mode, there's no need to init GC. */
646 if (pVM->vmm.s.fSwitcherDisabled)
647 return VINF_SUCCESS;
648
649 /*
650 * Call VMMGCInit():
651 * -# resolve the address.
652 * -# setup stackframe and EIP to use the trampoline.
653 * -# do a generic hypervisor call.
654 */
655 RTGCPTR GCPtrEP;
656 int rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &GCPtrEP);
657 if (VBOX_SUCCESS(rc))
658 {
659 CPUMHyperSetCtxCore(pVM, NULL);
660 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom); /* Clear the stack. */
661 CPUMPushHyper(pVM, VBOX_VERSION); /* Param 2: Version argument. */
662 CPUMPushHyper(pVM, VMMGC_DO_VMMGC_INIT); /* Param 1: Operation. */
663 CPUMPushHyper(pVM, pVM->pVMGC); /* Param 0: pVM */
664 CPUMPushHyper(pVM, 3 * sizeof(RTGCPTR)); /* trampoline param: stacksize. */
665 CPUMPushHyper(pVM, GCPtrEP); /* Call EIP. */
666 CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnGCCallTrampoline);
667
668 for (;;)
669 {
670#ifdef NO_SUPCALLR0VMM
671 //rc = VERR_GENERAL_FAILURE;
672 rc = VINF_SUCCESS;
673#else
674 rc = SUPCallVMMR0(pVM, VMMR0_DO_CALL_HYPERVISOR, NULL);
675#endif
676#ifdef LOG_ENABLED
677 PRTLOGGERGC pLogger = pVM->vmm.s.pLoggerHC;
678 if ( pLogger
679 && pLogger->offScratch > 0)
680 RTLogFlushGC(NULL, pLogger);
681#endif
682#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
683 PRTLOGGERGC pRelLogger = pVM->vmm.s.pRelLoggerHC;
684 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
685 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
686#endif
687 if (rc != VINF_VMM_CALL_HOST)
688 break;
689 rc = vmmR3ServiceCallHostRequest(pVM);
690 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
691 break;
692 }
693
694 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
695 {
696 VMMR3FatalDump(pVM, rc);
697 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
698 rc = VERR_INTERNAL_ERROR;
699 }
700 AssertRC(rc);
701 }
702 return rc;
703}
704
705
706/**
707 * Terminate the VMM bits.
708 *
709 * @returns VINF_SUCCESS.
710 * @param pVM The VM handle.
711 */
712VMMR3DECL(int) VMMR3Term(PVM pVM)
713{
714 /** @todo must call ring-0 so the logger thread instance can be properly removed. */
715
716#ifdef VBOX_STRICT_VMM_STACK
717 /*
718 * Make the two stack guard pages present again.
719 */
720 RTMemProtect(pVM->vmm.s.pbHCStack - PAGE_SIZE, PAGE_SIZE, RTMEM_PROT_READ | RTMEM_PROT_WRITE);
721 RTMemProtect(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE, PAGE_SIZE, RTMEM_PROT_READ | RTMEM_PROT_WRITE);
722#endif
723 return VINF_SUCCESS;
724}
725
726
727/**
728 * Applies relocations to data and code managed by this
729 * component. This function will be called at init and
730 * whenever the VMM need to relocate it self inside the GC.
731 *
732 * The VMM will need to apply relocations to the core code.
733 *
734 * @param pVM The VM handle.
735 * @param offDelta The relocation delta.
736 */
737VMMR3DECL(void) VMMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
738{
739 LogFlow(("VMMR3Relocate: offDelta=%VGv\n", offDelta));
740
741 /*
742 * Recalc the GC address.
743 */
744 pVM->vmm.s.pvGCCoreCode = MMHyperHC2GC(pVM, pVM->vmm.s.pvHCCoreCodeR3);
745
746 /*
747 * The stack.
748 */
749 CPUMSetHyperESP(pVM, CPUMGetHyperESP(pVM) + offDelta);
750 pVM->vmm.s.pbGCStack = MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack);
751 pVM->vmm.s.pbGCStackBottom = pVM->vmm.s.pbGCStack + VMM_STACK_SIZE;
752
753 /*
754 * All the switchers.
755 */
756 for (unsigned iSwitcher = 0; iSwitcher < ELEMENTS(s_apSwitchers); iSwitcher++)
757 {
758 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
759 if (pSwitcher && pSwitcher->pfnRelocate)
760 {
761 unsigned off = pVM->vmm.s.aoffSwitchers[iSwitcher];
762 pSwitcher->pfnRelocate(pVM,
763 pSwitcher,
764 (uint8_t *)pVM->vmm.s.pvHCCoreCodeR0 + off,
765 (uint8_t *)pVM->vmm.s.pvHCCoreCodeR3 + off,
766 pVM->vmm.s.pvGCCoreCode + off,
767 pVM->vmm.s.HCPhysCoreCode + off);
768 }
769 }
770
771 /*
772 * Recalc the GC address for the current switcher.
773 */
774 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[pVM->vmm.s.enmSwitcher];
775 RTGCPTR GCPtr = pVM->vmm.s.pvGCCoreCode + pVM->vmm.s.aoffSwitchers[pVM->vmm.s.enmSwitcher];
776 pVM->vmm.s.pfnGCGuestToHost = GCPtr + pSwitcher->offGCGuestToHost;
777 pVM->vmm.s.pfnGCCallTrampoline = GCPtr + pSwitcher->offGCCallTrampoline;
778 pVM->pfnVMMGCGuestToHostAsm = GCPtr + pSwitcher->offGCGuestToHostAsm;
779 pVM->pfnVMMGCGuestToHostAsmHyperCtx = GCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
780 pVM->pfnVMMGCGuestToHostAsmGuestCtx = GCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
781
782 /*
783 * Get other GC entry points.
784 */
785 int rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "CPUMGCResumeGuest", &pVM->vmm.s.pfnCPUMGCResumeGuest);
786 AssertReleaseMsgRC(rc, ("CPUMGCResumeGuest not found! rc=%Vra\n", rc));
787
788 rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "CPUMGCResumeGuestV86", &pVM->vmm.s.pfnCPUMGCResumeGuestV86);
789 AssertReleaseMsgRC(rc, ("CPUMGCResumeGuestV86 not found! rc=%Vra\n", rc));
790
791 /*
792 * Update the logger.
793 */
794 VMMR3UpdateLoggers(pVM);
795}
796
797
798/**
799 * Updates the settings for the GC and R0 loggers.
800 *
801 * @returns VBox status code.
802 * @param pVM The VM handle.
803 */
804VMMR3DECL(int) VMMR3UpdateLoggers(PVM pVM)
805{
806 /*
807 * Simply clone the logger instance (for GC).
808 */
809 int rc = VINF_SUCCESS;
810 RTGCPTR GCPtrLoggerFlush = 0;
811
812 if (pVM->vmm.s.pLoggerHC
813#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
814 || pVM->vmm.s.pRelLoggerHC
815#endif
816 )
817 {
818 rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCLoggerFlush", &GCPtrLoggerFlush);
819 AssertReleaseMsgRC(rc, ("vmmGCLoggerFlush not found! rc=%Vra\n", rc));
820 }
821
822 if (pVM->vmm.s.pLoggerHC)
823 {
824 RTGCPTR GCPtrLoggerWrapper = 0;
825 rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCLoggerWrapper", &GCPtrLoggerWrapper);
826 AssertReleaseMsgRC(rc, ("vmmGCLoggerWrapper not found! rc=%Vra\n", rc));
827 pVM->vmm.s.pLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pLoggerHC);
828 rc = RTLogCloneGC(NULL /* default */, pVM->vmm.s.pLoggerHC, pVM->vmm.s.cbLoggerGC,
829 GCPtrLoggerWrapper, GCPtrLoggerFlush, RTLOGFLAGS_BUFFERED);
830 AssertReleaseMsgRC(rc, ("RTLogCloneGC failed! rc=%Vra\n", rc));
831 }
832
833#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
834 if (pVM->vmm.s.pRelLoggerHC)
835 {
836 RTGCPTR GCPtrLoggerWrapper = 0;
837 rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCRelLoggerWrapper", &GCPtrLoggerWrapper);
838 AssertReleaseMsgRC(rc, ("vmmGCRelLoggerWrapper not found! rc=%Vra\n", rc));
839 pVM->vmm.s.pRelLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pRelLoggerHC);
840 rc = RTLogCloneGC(RTLogRelDefaultInstance(), pVM->vmm.s.pRelLoggerHC, pVM->vmm.s.cbRelLoggerGC,
841 GCPtrLoggerWrapper, GCPtrLoggerFlush, RTLOGFLAGS_BUFFERED);
842 AssertReleaseMsgRC(rc, ("RTLogCloneGC failed! rc=%Vra\n", rc));
843 }
844#endif /* VBOX_WITH_GC_AND_R0_RELEASE_LOG */
845
846 /*
847 * For the ring-0 EMT logger, we use a per-thread logger
848 * instance in ring-0. Only initialize it once.
849 */
850 PVMMR0LOGGER pR0Logger = pVM->vmm.s.pR0Logger;
851 if (pR0Logger)
852 {
853 if (!pR0Logger->fCreated)
854 {
855 RTHCPTR pfnLoggerWrapper = NULL;
856 rc = PDMR3GetSymbolR0(pVM, VMMR0_MAIN_MODULE_NAME, "vmmR0LoggerWrapper", &pfnLoggerWrapper);
857 AssertReleaseMsgRCReturn(rc, ("VMMLoggerWrapper not found! rc=%Vra\n", rc), rc);
858
859 RTHCPTR pfnLoggerFlush = NULL;
860 rc = PDMR3GetSymbolR0(pVM, VMMR0_MAIN_MODULE_NAME, "vmmR0LoggerFlush", &pfnLoggerFlush);
861 AssertReleaseMsgRCReturn(rc, ("VMMLoggerFlush not found! rc=%Vra\n", rc), rc);
862
863 rc = RTLogCreateForR0(&pR0Logger->Logger, pR0Logger->cbLogger,
864 *(PFNRTLOGGER *)&pfnLoggerWrapper, *(PFNRTLOGFLUSH *)&pfnLoggerFlush,
865 RTLOGFLAGS_BUFFERED, RTLOGDEST_DUMMY);
866 AssertReleaseMsgRCReturn(rc, ("RTLogCloneGC failed! rc=%Vra\n", rc), rc);
867 pR0Logger->fCreated = true;
868 }
869
870 rc = RTLogCopyGroupsAndFlags(&pR0Logger->Logger, NULL /* default */, RTLOGFLAGS_BUFFERED, 0);
871 AssertRC(rc);
872 }
873
874 return rc;
875}
876
877
878/**
879 * Generic switch code relocator.
880 *
881 * @param pVM The VM handle.
882 * @param pSwitcher The switcher definition.
883 * @param pu8CodeR3 Pointer to the core code block for the switcher, ring-3 mapping.
884 * @param pu8CodeR0 Pointer to the core code block for the switcher, ring-0 mapping.
885 * @param GCPtrCode The guest context address corresponding to pu8Code.
886 * @param u32IDCode The identity mapped (ID) address corresponding to pu8Code.
887 * @param SelCS The hypervisor CS selector.
888 * @param SelDS The hypervisor DS selector.
889 * @param SelTSS The hypervisor TSS selector.
890 * @param GCPtrGDT The GC address of the hypervisor GDT.
891 * @param SelCS64 The 64-bit mode hypervisor CS selector.
892 */
893static void vmmR3SwitcherGenericRelocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode,
894 RTSEL SelCS, RTSEL SelDS, RTSEL SelTSS, RTGCPTR GCPtrGDT, RTSEL SelCS64)
895{
896 union
897 {
898 const uint8_t *pu8;
899 const uint16_t *pu16;
900 const uint32_t *pu32;
901 const uint64_t *pu64;
902 const void *pv;
903 uintptr_t u;
904 } u;
905 u.pv = pSwitcher->pvFixups;
906
907 /*
908 * Process fixups.
909 */
910 uint8_t u8;
911 while ((u8 = *u.pu8++) != FIX_THE_END)
912 {
913 /*
914 * Get the source (where to write the fixup).
915 */
916 uint32_t offSrc = *u.pu32++;
917 Assert(offSrc < pSwitcher->cbCode);
918 union
919 {
920 uint8_t *pu8;
921 uint16_t *pu16;
922 uint32_t *pu32;
923 uint64_t *pu64;
924 uintptr_t u;
925 } uSrc;
926 uSrc.pu8 = pu8CodeR3 + offSrc;
927
928 /* The fixup target and method depends on the type. */
929 switch (u8)
930 {
931 /*
932 * 32-bit relative, source in HC and target in GC.
933 */
934 case FIX_HC_2_GC_NEAR_REL:
935 {
936 Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
937 uint32_t offTrg = *u.pu32++;
938 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
939 *uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (uSrc.u + 4));
940 break;
941 }
942
943 /*
944 * 32-bit relative, source in HC and target in ID.
945 */
946 case FIX_HC_2_ID_NEAR_REL:
947 {
948 Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
949 uint32_t offTrg = *u.pu32++;
950 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
951 *uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (uSrc.u + 4));
952 break;
953 }
954
955 /*
956 * 32-bit relative, source in GC and target in HC.
957 */
958 case FIX_GC_2_HC_NEAR_REL:
959 {
960 Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
961 uint32_t offTrg = *u.pu32++;
962 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
963 *uSrc.pu32 = (uint32_t)(((uintptr_t)pu8CodeR0 + offTrg) - (GCPtrCode + offSrc + 4));
964 break;
965 }
966
967 /*
968 * 32-bit relative, source in GC and target in ID.
969 */
970 case FIX_GC_2_ID_NEAR_REL:
971 {
972 Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
973 uint32_t offTrg = *u.pu32++;
974 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
975 *uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (GCPtrCode + offSrc + 4));
976 break;
977 }
978
979 /*
980 * 32-bit relative, source in ID and target in HC.
981 */
982 case FIX_ID_2_HC_NEAR_REL:
983 {
984 Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
985 uint32_t offTrg = *u.pu32++;
986 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
987 *uSrc.pu32 = (uint32_t)(((uintptr_t)pu8CodeR0 + offTrg) - (u32IDCode + offSrc + 4));
988 break;
989 }
990
991 /*
992 * 32-bit relative, source in ID and target in HC.
993 */
994 case FIX_ID_2_GC_NEAR_REL:
995 {
996 Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
997 uint32_t offTrg = *u.pu32++;
998 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
999 *uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (u32IDCode + offSrc + 4));
1000 break;
1001 }
1002
1003 /*
1004 * 16:32 far jump, target in GC.
1005 */
1006 case FIX_GC_FAR32:
1007 {
1008 uint32_t offTrg = *u.pu32++;
1009 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1010 *uSrc.pu32++ = (uint32_t)(GCPtrCode + offTrg);
1011 *uSrc.pu16++ = SelCS;
1012 break;
1013 }
1014
1015 /*
1016 * Make 32-bit GC pointer given CPUM offset.
1017 */
1018 case FIX_GC_CPUM_OFF:
1019 {
1020 uint32_t offCPUM = *u.pu32++;
1021 Assert(offCPUM < sizeof(pVM->cpum));
1022 *uSrc.pu32 = (uint32_t)(VM_GUEST_ADDR(pVM, &pVM->cpum) + offCPUM);
1023 break;
1024 }
1025
1026 /*
1027 * Make 32-bit GC pointer given VM offset.
1028 */
1029 case FIX_GC_VM_OFF:
1030 {
1031 uint32_t offVM = *u.pu32++;
1032 Assert(offVM < sizeof(VM));
1033 *uSrc.pu32 = (uint32_t)(VM_GUEST_ADDR(pVM, pVM) + offVM);
1034 break;
1035 }
1036
1037 /*
1038 * Make 32-bit HC pointer given CPUM offset.
1039 */
1040 case FIX_HC_CPUM_OFF:
1041 {
1042 uint32_t offCPUM = *u.pu32++;
1043 Assert(offCPUM < sizeof(pVM->cpum));
1044 *uSrc.pu32 = (uint32_t)((uintptr_t)&pVM->cpum + offCPUM);
1045 break;
1046 }
1047
1048 /*
1049 * Make 32-bit HC pointer given VM offset.
1050 */
1051 case FIX_HC_VM_OFF:
1052 {
1053 uint32_t offVM = *u.pu32++;
1054 Assert(offVM < sizeof(VM));
1055 *uSrc.pu32 = (uint32_t)(uintptr_t)pVM + offVM;
1056 break;
1057 }
1058
1059 /*
1060 * Store the 32-Bit CR3 (32-bit) for the intermediate memory context.
1061 */
1062 case FIX_INTER_32BIT_CR3:
1063 {
1064
1065 *uSrc.pu32 = PGMGetInter32BitCR3(pVM);
1066 break;
1067 }
1068
1069 /*
1070 * Store the PAE CR3 (32-bit) for the intermediate memory context.
1071 */
1072 case FIX_INTER_PAE_CR3:
1073 {
1074
1075 *uSrc.pu32 = PGMGetInterPaeCR3(pVM);
1076 break;
1077 }
1078
1079 /*
1080 * Store the AMD64 CR3 (32-bit) for the intermediate memory context.
1081 */
1082 case FIX_INTER_AMD64_CR3:
1083 {
1084
1085 *uSrc.pu32 = PGMGetInterAmd64CR3(pVM);
1086 break;
1087 }
1088
1089 /*
1090 * Store the 32-Bit CR3 (32-bit) for the hypervisor (shadow) memory context.
1091 */
1092 case FIX_HYPER_32BIT_CR3:
1093 {
1094
1095 *uSrc.pu32 = PGMGetHyper32BitCR3(pVM);
1096 break;
1097 }
1098
1099 /*
1100 * Store the PAE CR3 (32-bit) for the hypervisor (shadow) memory context.
1101 */
1102 case FIX_HYPER_PAE_CR3:
1103 {
1104
1105 *uSrc.pu32 = PGMGetHyperPaeCR3(pVM);
1106 break;
1107 }
1108
1109 /*
1110 * Store the AMD64 CR3 (32-bit) for the hypervisor (shadow) memory context.
1111 */
1112 case FIX_HYPER_AMD64_CR3:
1113 {
1114
1115 *uSrc.pu32 = PGMGetHyperAmd64CR3(pVM);
1116 break;
1117 }
1118
1119 /*
1120 * Store Hypervisor CS (16-bit).
1121 */
1122 case FIX_HYPER_CS:
1123 {
1124 *uSrc.pu16 = SelCS;
1125 break;
1126 }
1127
1128 /*
1129 * Store Hypervisor DS (16-bit).
1130 */
1131 case FIX_HYPER_DS:
1132 {
1133 *uSrc.pu16 = SelDS;
1134 break;
1135 }
1136
1137 /*
1138 * Store Hypervisor TSS (16-bit).
1139 */
1140 case FIX_HYPER_TSS:
1141 {
1142 *uSrc.pu16 = SelTSS;
1143 break;
1144 }
1145
1146 /*
1147 * Store the 32-bit GC address of the 2nd dword of the TSS descriptor (in the GDT).
1148 */
1149 case FIX_GC_TSS_GDTE_DW2:
1150 {
1151 RTGCPTR GCPtr = GCPtrGDT + (SelTSS & ~7) + 4;
1152 *uSrc.pu32 = (uint32_t)GCPtr;
1153 break;
1154 }
1155
1156
1157 ///@todo case FIX_CR4_MASK:
1158 ///@todo case FIX_CR4_OSFSXR:
1159
1160 /*
1161 * Insert relative jump to specified target it FXSAVE/FXRSTOR isn't supported by the cpu.
1162 */
1163 case FIX_NO_FXSAVE_JMP:
1164 {
1165 uint32_t offTrg = *u.pu32++;
1166 Assert(offTrg < pSwitcher->cbCode);
1167 if (!CPUMSupportsFXSR(pVM))
1168 {
1169 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
1170 *uSrc.pu32++ = offTrg - (offSrc + 5);
1171 }
1172 else
1173 {
1174 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
1175 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
1176 }
1177 break;
1178 }
1179
1180 /*
1181 * Insert relative jump to specified target it SYSENTER isn't used by the host.
1182 */
1183 case FIX_NO_SYSENTER_JMP:
1184 {
1185 uint32_t offTrg = *u.pu32++;
1186 Assert(offTrg < pSwitcher->cbCode);
1187 if (!CPUMIsHostUsingSysEnter(pVM))
1188 {
1189 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
1190 *uSrc.pu32++ = offTrg - (offSrc + 5);
1191 }
1192 else
1193 {
1194 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
1195 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
1196 }
1197 break;
1198 }
1199
1200 /*
1201 * Insert relative jump to specified target it SYSENTER isn't used by the host.
1202 */
1203 case FIX_NO_SYSCALL_JMP:
1204 {
1205 uint32_t offTrg = *u.pu32++;
1206 Assert(offTrg < pSwitcher->cbCode);
1207 if (!CPUMIsHostUsingSysEnter(pVM))
1208 {
1209 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
1210 *uSrc.pu32++ = offTrg - (offSrc + 5);
1211 }
1212 else
1213 {
1214 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
1215 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
1216 }
1217 break;
1218 }
1219
1220#ifdef __AMD64__
1221 /*
1222 * 64-bit HC pointer fixup to (HC) target within the code (32-bit offset).
1223 */
1224 case FIX_HC_64BIT:
1225 {
1226 uint32_t offTrg = *u.pu32++;
1227 Assert(offSrc < pSwitcher->cbCode);
1228 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1229 *uSrc.pu64 = (uintptr_t)pu8CodeR0 + offTrg;
1230 break;
1231 }
1232
1233 /*
1234 * 64-bit HC pointer to the CPUM instance data (no argument).
1235 */
1236 case FIX_HC_64BIT_CPUM:
1237 {
1238 Assert(offSrc < pSwitcher->cbCode);
1239 *uSrc.pu64 = (uintptr_t)&pVM->cpum;
1240 break;
1241 }
1242#endif
1243
1244 /*
1245 * 32-bit ID pointer to (ID) target within the code (32-bit offset).
1246 */
1247 case FIX_ID_32BIT:
1248 {
1249 uint32_t offTrg = *u.pu32++;
1250 Assert(offSrc < pSwitcher->cbCode);
1251 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1252 *uSrc.pu32 = u32IDCode + offTrg;
1253 break;
1254 }
1255
1256 /*
1257 * 64-bit ID pointer to (ID) target within the code (32-bit offset).
1258 */
1259 case FIX_ID_64BIT:
1260 {
1261 uint32_t offTrg = *u.pu32++;
1262 Assert(offSrc < pSwitcher->cbCode);
1263 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1264 *uSrc.pu64 = u32IDCode + offTrg;
1265 break;
1266 }
1267
1268 /*
1269 * Far 16:32 ID pointer to 64-bit mode (ID) target within the code (32-bit offset).
1270 */
1271 case FIX_ID_FAR32_TO_64BIT_MODE:
1272 {
1273 uint32_t offTrg = *u.pu32++;
1274 Assert(offSrc < pSwitcher->cbCode);
1275 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1276 *uSrc.pu32++ = u32IDCode + offTrg;
1277 *uSrc.pu16 = SelCS64;
1278 AssertRelease(SelCS64);
1279 break;
1280 }
1281
1282#ifdef VBOX_WITH_NMI
1283 /*
1284 * 32-bit address to the APIC base.
1285 */
1286 case FIX_GC_APIC_BASE_32BIT:
1287 {
1288 *uSrc.pu32 = pVM->vmm.s.GCPtrApicBase;
1289 break;
1290 }
1291#endif
1292
1293 default:
1294 AssertReleaseMsgFailed(("Unknown fixup %d in switcher %s\n", u8, pSwitcher->pszDesc));
1295 break;
1296 }
1297 }
1298
1299#ifdef LOG_ENABLED
1300 /*
1301 * If Log2 is enabled disassemble the switcher code.
1302 *
1303 * The switcher code have 1-2 HC parts, 1 GC part and 0-2 ID parts.
1304 */
1305 if (LogIs2Enabled())
1306 {
1307 RTLogPrintf("*** Disassembly of switcher %d '%s' %#x bytes ***\n"
1308 " pu8CodeR0 = %p\n"
1309 " pu8CodeR3 = %p\n"
1310 " GCPtrCode = %VGv\n"
1311 " u32IDCode = %08x\n"
1312 " pVMGC = %VGv\n"
1313 " pCPUMGC = %VGv\n"
1314 " pVMHC = %p\n"
1315 " pCPUMHC = %p\n"
1316 " GCPtrGDT = %VGv\n"
1317 " InterCR3s = %08x, %08x, %08x (32-Bit, PAE, AMD64)\n"
1318 " HyperCR3s = %08x, %08x, %08x (32-Bit, PAE, AMD64)\n"
1319 " SelCS = %04x\n"
1320 " SelDS = %04x\n"
1321 " SelCS64 = %04x\n"
1322 " SelTSS = %04x\n",
1323 pSwitcher->enmType, pSwitcher->pszDesc, pSwitcher->cbCode,
1324 pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode, VM_GUEST_ADDR(pVM, pVM),
1325 VM_GUEST_ADDR(pVM, &pVM->cpum), pVM, &pVM->cpum,
1326 GCPtrGDT,
1327 PGMGetHyper32BitCR3(pVM), PGMGetHyperPaeCR3(pVM), PGMGetHyperAmd64CR3(pVM),
1328 PGMGetInter32BitCR3(pVM), PGMGetInterPaeCR3(pVM), PGMGetInterAmd64CR3(pVM),
1329 SelCS, SelDS, SelCS64, SelTSS);
1330
1331 uint32_t offCode = 0;
1332 while (offCode < pSwitcher->cbCode)
1333 {
1334 /*
1335 * Figure out where this is.
1336 */
1337 const char *pszDesc = NULL;
1338 RTUINTPTR uBase;
1339 uint32_t cbCode;
1340 if (offCode - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0)
1341 {
1342 pszDesc = "HCCode0";
1343 uBase = (RTUINTPTR)pu8CodeR0;
1344 offCode = pSwitcher->offHCCode0;
1345 cbCode = pSwitcher->cbHCCode0;
1346 }
1347 else if (offCode - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1)
1348 {
1349 pszDesc = "HCCode1";
1350 uBase = (RTUINTPTR)pu8CodeR0;
1351 offCode = pSwitcher->offHCCode1;
1352 cbCode = pSwitcher->cbHCCode1;
1353 }
1354 else if (offCode - pSwitcher->offGCCode < pSwitcher->cbGCCode)
1355 {
1356 pszDesc = "GCCode";
1357 uBase = GCPtrCode;
1358 offCode = pSwitcher->offGCCode;
1359 cbCode = pSwitcher->cbGCCode;
1360 }
1361 else if (offCode - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0)
1362 {
1363 pszDesc = "IDCode0";
1364 uBase = u32IDCode;
1365 offCode = pSwitcher->offIDCode0;
1366 cbCode = pSwitcher->cbIDCode0;
1367 }
1368 else if (offCode - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1)
1369 {
1370 pszDesc = "IDCode1";
1371 uBase = u32IDCode;
1372 offCode = pSwitcher->offIDCode1;
1373 cbCode = pSwitcher->cbIDCode1;
1374 }
1375 else
1376 {
1377 RTLogPrintf(" %04x: %02x '%c' (nowhere)\n",
1378 offCode, pu8CodeR3[offCode], isprint(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
1379 offCode++;
1380 continue;
1381 }
1382
1383 /*
1384 * Disassemble it.
1385 */
1386 RTLogPrintf(" %s: offCode=%#x cbCode=%#x\n", pszDesc, offCode, cbCode);
1387 DISCPUSTATE Cpu = {0};
1388 Cpu.mode = CPUMODE_32BIT;
1389 while (cbCode > 0)
1390 {
1391 /* try label it */
1392 if (pSwitcher->offR0HostToGuest == offCode)
1393 RTLogPrintf(" *R0HostToGuest:\n");
1394 if (pSwitcher->offGCGuestToHost == offCode)
1395 RTLogPrintf(" *GCGuestToHost:\n");
1396 if (pSwitcher->offGCCallTrampoline == offCode)
1397 RTLogPrintf(" *GCCallTrampoline:\n");
1398 if (pSwitcher->offGCGuestToHostAsm == offCode)
1399 RTLogPrintf(" *GCGuestToHostAsm:\n");
1400 if (pSwitcher->offGCGuestToHostAsmHyperCtx == offCode)
1401 RTLogPrintf(" *GCGuestToHostAsmHyperCtx:\n");
1402 if (pSwitcher->offGCGuestToHostAsmGuestCtx == offCode)
1403 RTLogPrintf(" *GCGuestToHostAsmGuestCtx:\n");
1404
1405 /* disas */
1406 uint32_t cbInstr = 0;
1407 char szDisas[256];
1408 if (DISInstr(&Cpu, (RTUINTPTR)pu8CodeR3 + offCode, uBase - (RTUINTPTR)pu8CodeR3, &cbInstr, szDisas))
1409 RTLogPrintf(" %04x: %s", offCode, szDisas); //for whatever reason szDisas includes '\n'.
1410 else
1411 {
1412 RTLogPrintf(" %04x: %02x '%c'\n",
1413 offCode, pu8CodeR3[offCode], isprint(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
1414 cbInstr = 1;
1415 }
1416 offCode += cbInstr;
1417 cbCode -= RT_MIN(cbInstr, cbCode);
1418 }
1419 }
1420 }
1421#endif
1422}
1423
1424
1425/**
1426 * Relocator for the 32-Bit to 32-Bit world switcher.
1427 */
1428DECLCALLBACK(void) vmmR3Switcher32BitTo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1429{
1430 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1431 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1432}
1433
1434
1435/**
1436 * Relocator for the 32-Bit to PAE world switcher.
1437 */
1438DECLCALLBACK(void) vmmR3Switcher32BitToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1439{
1440 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1441 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1442}
1443
1444
1445/**
1446 * Relocator for the PAE to 32-Bit world switcher.
1447 */
1448DECLCALLBACK(void) vmmR3SwitcherPAETo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1449{
1450 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1451 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1452}
1453
1454
1455/**
1456 * Relocator for the PAE to PAE world switcher.
1457 */
1458DECLCALLBACK(void) vmmR3SwitcherPAEToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1459{
1460 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1461 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1462}
1463
1464
1465/**
1466 * Relocator for the AMD64 to PAE world switcher.
1467 */
1468DECLCALLBACK(void) vmmR3SwitcherAMD64ToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1469{
1470 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1471 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
1472}
1473
1474
1475/**
1476 * Gets the pointer to g_szRTAssertMsg1 in GC.
1477 * @returns Pointer to VMMGC::g_szRTAssertMsg1.
1478 * Returns NULL if not present.
1479 * @param pVM The VM handle.
1480 */
1481VMMR3DECL(const char *) VMMR3GetGCAssertMsg1(PVM pVM)
1482{
1483 RTGCPTR GCPtr;
1484 int rc = PDMR3GetSymbolGC(pVM, NULL, "g_szRTAssertMsg1", &GCPtr);
1485 if (VBOX_SUCCESS(rc))
1486 return (const char *)MMHyperGC2HC(pVM, GCPtr);
1487 return NULL;
1488}
1489
1490
1491/**
1492 * Gets the pointer to g_szRTAssertMsg2 in GC.
1493 * @returns Pointer to VMMGC::g_szRTAssertMsg2.
1494 * Returns NULL if not present.
1495 * @param pVM The VM handle.
1496 */
1497VMMR3DECL(const char *) VMMR3GetGCAssertMsg2(PVM pVM)
1498{
1499 RTGCPTR GCPtr;
1500 int rc = PDMR3GetSymbolGC(pVM, NULL, "g_szRTAssertMsg2", &GCPtr);
1501 if (VBOX_SUCCESS(rc))
1502 return (const char *)MMHyperGC2HC(pVM, GCPtr);
1503 return NULL;
1504}
1505
1506
1507/**
1508 * Execute state save operation.
1509 *
1510 * @returns VBox status code.
1511 * @param pVM VM Handle.
1512 * @param pSSM SSM operation handle.
1513 */
1514static DECLCALLBACK(int) vmmR3Save(PVM pVM, PSSMHANDLE pSSM)
1515{
1516 LogFlow(("vmmR3Save:\n"));
1517
1518 /*
1519 * The hypervisor stack.
1520 */
1521 SSMR3PutGCPtr(pSSM, pVM->vmm.s.pbGCStackBottom);
1522 RTGCPTR GCPtrESP = CPUMGetHyperESP(pVM);
1523 Assert(pVM->vmm.s.pbGCStackBottom - GCPtrESP <= VMM_STACK_SIZE);
1524 SSMR3PutGCPtr(pSSM, GCPtrESP);
1525 SSMR3PutMem(pSSM, pVM->vmm.s.pbHCStack, VMM_STACK_SIZE);
1526 return SSMR3PutU32(pSSM, ~0); /* terminator */
1527}
1528
1529
1530/**
1531 * Execute state load operation.
1532 *
1533 * @returns VBox status code.
1534 * @param pVM VM Handle.
1535 * @param pSSM SSM operation handle.
1536 * @param u32Version Data layout version.
1537 */
1538static DECLCALLBACK(int) vmmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
1539{
1540 LogFlow(("vmmR3Load:\n"));
1541
1542 /*
1543 * Validate version.
1544 */
1545 if (u32Version != VMM_SAVED_STATE_VERSION)
1546 {
1547 Log(("vmmR3Load: Invalid version u32Version=%d!\n", u32Version));
1548 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1549 }
1550
1551 /*
1552 * Check that the stack is in the same place, or that it's fearly empty.
1553 */
1554 RTGCPTR GCPtrStackBottom;
1555 SSMR3GetGCPtr(pSSM, &GCPtrStackBottom);
1556 RTGCPTR GCPtrESP;
1557 int rc = SSMR3GetGCPtr(pSSM, &GCPtrESP);
1558 if (VBOX_FAILURE(rc))
1559 return rc;
1560 if ( GCPtrStackBottom == pVM->vmm.s.pbGCStackBottom
1561 || (GCPtrStackBottom - GCPtrESP < 32)) /** @todo This will break if we start preemting the hypervisor. */
1562 {
1563 /*
1564 * We *must* set the ESP because the CPUM load + PGM load relocations will render
1565 * the ESP in CPUM fatally invalid.
1566 */
1567 CPUMSetHyperESP(pVM, GCPtrESP);
1568
1569 /* restore the stack. */
1570 SSMR3GetMem(pSSM, pVM->vmm.s.pbHCStack, VMM_STACK_SIZE);
1571
1572 /* terminator */
1573 uint32_t u32;
1574 rc = SSMR3GetU32(pSSM, &u32);
1575 if (VBOX_FAILURE(rc))
1576 return rc;
1577 if (u32 != ~0U)
1578 {
1579 AssertMsgFailed(("u32=%#x\n", u32));
1580 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1581 }
1582 return VINF_SUCCESS;
1583 }
1584
1585 AssertMsgFailed(("The stack is not in the same place and it's not empty! GCPtrStackBottom=%VGv pbGCStackBottom=%VGv ESP=%VGv\n",
1586 GCPtrStackBottom, pVM->vmm.s.pbGCStackBottom, GCPtrESP));
1587 return VERR_SSM_LOAD_CONFIG_MISMATCH;
1588}
1589
1590
1591/**
1592 * Selects the switcher to be used for switching to GC.
1593 *
1594 * @returns VBox status code.
1595 * @param pVM VM handle.
1596 * @param enmSwitcher The new switcher.
1597 * @remark This function may be called before the VMM is initialized.
1598 */
1599VMMR3DECL(int) VMMR3SelectSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
1600{
1601 /*
1602 * Validate input.
1603 */
1604 if ( enmSwitcher < VMMSWITCHER_INVALID
1605 || enmSwitcher >= VMMSWITCHER_MAX)
1606 {
1607 AssertMsgFailed(("Invalid input enmSwitcher=%d\n", enmSwitcher));
1608 return VERR_INVALID_PARAMETER;
1609 }
1610
1611 /*
1612 * Select the new switcher.
1613 */
1614 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[enmSwitcher];
1615 if (pSwitcher)
1616 {
1617 Log(("VMMR3SelectSwitcher: enmSwitcher %d -> %d %s\n", pVM->vmm.s.enmSwitcher, enmSwitcher, pSwitcher->pszDesc));
1618 pVM->vmm.s.enmSwitcher = enmSwitcher;
1619
1620 RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvHCCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher]; /** @todo fix the pvHCCoreCodeR0 type */
1621 pVM->vmm.s.pfnR0HostToGuest = pbCodeR0 + pSwitcher->offR0HostToGuest;
1622
1623 RTGCPTR GCPtr = pVM->vmm.s.pvGCCoreCode + pVM->vmm.s.aoffSwitchers[enmSwitcher];
1624 pVM->vmm.s.pfnGCGuestToHost = GCPtr + pSwitcher->offGCGuestToHost;
1625 pVM->vmm.s.pfnGCCallTrampoline = GCPtr + pSwitcher->offGCCallTrampoline;
1626 pVM->pfnVMMGCGuestToHostAsm = GCPtr + pSwitcher->offGCGuestToHostAsm;
1627 pVM->pfnVMMGCGuestToHostAsmHyperCtx = GCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
1628 pVM->pfnVMMGCGuestToHostAsmGuestCtx = GCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
1629 return VINF_SUCCESS;
1630 }
1631 return VERR_NOT_IMPLEMENTED;
1632}
1633
1634/**
1635 * Disable the switcher logic permanently.
1636 *
1637 * @returns VBox status code.
1638 * @param pVM VM handle.
1639 */
1640VMMR3DECL(int) VMMR3DisableSwitcher(PVM pVM)
1641{
1642/** @todo r=bird: I would suggest that we create a dummy switcher which just does something like:
1643 * @code
1644 * mov eax, VERR_INTERNAL_ERROR
1645 * ret
1646 * @endcode
1647 * And then check for fSwitcherDisabled in VMMR3SelectSwitcher() in order to prevent it from being removed.
1648 */
1649 pVM->vmm.s.fSwitcherDisabled = true;
1650 return VINF_SUCCESS;
1651}
1652
1653
1654/**
1655 * Resolve a builtin GC symbol.
1656 * Called by PDM when loading or relocating GC modules.
1657 *
1658 * @returns VBox status
1659 * @param pVM VM Handle.
1660 * @param pszSymbol Symbol to resolv
1661 * @param pGCPtrValue Where to store the symbol value.
1662 * @remark This has to work before VMMR3Relocate() is called.
1663 */
1664VMMR3DECL(int) VMMR3GetImportGC(PVM pVM, const char *pszSymbol, PRTGCPTR pGCPtrValue)
1665{
1666 if (!strcmp(pszSymbol, "g_Logger"))
1667 {
1668 if (pVM->vmm.s.pLoggerHC)
1669 pVM->vmm.s.pLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pLoggerHC);
1670 *pGCPtrValue = pVM->vmm.s.pLoggerGC;
1671 }
1672 else if (!strcmp(pszSymbol, "g_RelLogger"))
1673 {
1674#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
1675 if (pVM->vmm.s.pRelLoggerHC)
1676 pVM->vmm.s.pRelLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pRelLoggerHC);
1677 *pGCPtrValue = pVM->vmm.s.pRelLoggerGC;
1678#else
1679 *pGCPtrValue = NIL_RTGCPTR;
1680#endif
1681 }
1682 else
1683 return VERR_SYMBOL_NOT_FOUND;
1684 return VINF_SUCCESS;
1685}
1686
1687
1688/**
1689 * Suspends the the CPU yielder.
1690 *
1691 * @param pVM The VM handle.
1692 */
1693VMMR3DECL(void) VMMR3YieldSuspend(PVM pVM)
1694{
1695 if (!pVM->vmm.s.cYieldResumeMillies)
1696 {
1697 uint64_t u64Now = TMTimerGet(pVM->vmm.s.pYieldTimer);
1698 uint64_t u64Expire = TMTimerGetExpire(pVM->vmm.s.pYieldTimer);
1699 if (u64Now >= u64Expire || u64Expire == ~(uint64_t)0)
1700 pVM->vmm.s.cYieldResumeMillies = pVM->vmm.s.cYieldEveryMillies;
1701 else
1702 pVM->vmm.s.cYieldResumeMillies = TMTimerToMilli(pVM->vmm.s.pYieldTimer, u64Expire - u64Now);
1703 TMTimerStop(pVM->vmm.s.pYieldTimer);
1704 }
1705}
1706
1707
1708/**
1709 * Stops the the CPU yielder.
1710 *
1711 * @param pVM The VM handle.
1712 */
1713VMMR3DECL(void) VMMR3YieldStop(PVM pVM)
1714{
1715 if (!pVM->vmm.s.cYieldResumeMillies)
1716 TMTimerStop(pVM->vmm.s.pYieldTimer);
1717 pVM->vmm.s.cYieldResumeMillies = pVM->vmm.s.cYieldEveryMillies;
1718}
1719
1720
1721/**
1722 * Resumes the CPU yielder when it has been a suspended or stopped.
1723 *
1724 * @param pVM The VM handle.
1725 */
1726VMMR3DECL(void) VMMR3YieldResume(PVM pVM)
1727{
1728 if (pVM->vmm.s.cYieldResumeMillies)
1729 {
1730 TMTimerSetMillies(pVM->vmm.s.pYieldTimer, pVM->vmm.s.cYieldResumeMillies);
1731 pVM->vmm.s.cYieldResumeMillies = 0;
1732 }
1733}
1734
1735
1736/**
1737 * Internal timer callback function.
1738 *
1739 * @param pVM The VM.
1740 * @param pTimer The timer handle.
1741 * @param pvUser User argument specified upon timer creation.
1742 */
1743static DECLCALLBACK(void) vmmR3YieldEMT(PVM pVM, PTMTIMER pTimer, void *pvUser)
1744{
1745#ifdef LOG_ENABLED
1746 uint64_t u64Elapsed = RTTimeNanoTS();
1747#endif
1748 RTThreadYield();
1749 TMTimerSetMillies(pTimer, pVM->vmm.s.cYieldEveryMillies);
1750 Log(("vmmR3YieldEMT: %RI64 ns\n", RTTimeNanoTS() - u64Elapsed));
1751}
1752
1753
1754/**
1755 * Acquire global VM lock.
1756 *
1757 * @returns VBox status code
1758 * @param pVM The VM to operate on.
1759 */
1760VMMR3DECL(int) VMMR3Lock(PVM pVM)
1761{
1762 return RTCritSectEnter(&pVM->vmm.s.CritSectVMLock);
1763}
1764
1765
1766/**
1767 * Release global VM lock.
1768 *
1769 * @returns VBox status code
1770 * @param pVM The VM to operate on.
1771 */
1772VMMR3DECL(int) VMMR3Unlock(PVM pVM)
1773{
1774 return RTCritSectLeave(&pVM->vmm.s.CritSectVMLock);
1775}
1776
1777
1778/**
1779 * Return global VM lock owner.
1780 *
1781 * @returns Thread id of owner.
1782 * @returns NIL_RTTHREAD if no owner.
1783 * @param pVM The VM to operate on.
1784 */
1785VMMR3DECL(RTNATIVETHREAD) VMMR3LockGetOwner(PVM pVM)
1786{
1787 return RTCritSectGetOwner(&pVM->vmm.s.CritSectVMLock);
1788}
1789
1790
1791/**
1792 * Checks if the current thread is the owner of the global VM lock.
1793 *
1794 * @returns true if owner.
1795 * @returns false if not owner.
1796 * @param pVM The VM to operate on.
1797 */
1798VMMR3DECL(bool) VMMR3LockIsOwner(PVM pVM)
1799{
1800 return RTCritSectIsOwner(&pVM->vmm.s.CritSectVMLock);
1801}
1802
1803
1804/**
1805 * Executes guest code.
1806 *
1807 * @param pVM VM handle.
1808 */
1809VMMR3DECL(int) VMMR3RawRunGC(PVM pVM)
1810{
1811 Log2(("VMMR3RawRunGC: (cs:eip=%04x:%08x)\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1812
1813 /*
1814 * Set the EIP and ESP.
1815 */
1816 CPUMSetHyperEIP(pVM, CPUMGetGuestEFlags(pVM) & X86_EFL_VM
1817 ? pVM->vmm.s.pfnCPUMGCResumeGuestV86
1818 : pVM->vmm.s.pfnCPUMGCResumeGuest);
1819 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom);
1820
1821 /*
1822 * We hide log flushes (outer) and hypervisor interrupts (inner).
1823 */
1824 for (;;)
1825 {
1826 int rc;
1827 do
1828 {
1829#ifdef NO_SUPCALLR0VMM
1830 rc = VERR_GENERAL_FAILURE;
1831#else
1832 rc = SUPCallVMMR0(pVM, VMMR0_DO_RAW_RUN, NULL);
1833#endif
1834 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
1835
1836 /*
1837 * Flush the logs.
1838 */
1839#ifdef LOG_ENABLED
1840 PRTLOGGERGC pLogger = pVM->vmm.s.pLoggerHC;
1841 if ( pLogger
1842 && pLogger->offScratch > 0)
1843 RTLogFlushGC(NULL, pLogger);
1844#endif
1845#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
1846 PRTLOGGERGC pRelLogger = pVM->vmm.s.pRelLoggerHC;
1847 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
1848 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
1849#endif
1850 if (rc != VINF_VMM_CALL_HOST)
1851 {
1852 Log2(("VMMR3RawRunGC: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1853 return rc;
1854 }
1855 rc = vmmR3ServiceCallHostRequest(pVM);
1856 if (VBOX_FAILURE(rc))
1857 return rc;
1858 /* Resume GC */
1859 }
1860}
1861
1862
1863/**
1864 * Executes guest code (Intel VMX and AMD SVM).
1865 *
1866 * @param pVM VM handle.
1867 */
1868VMMR3DECL(int) VMMR3HwAccRunGC(PVM pVM)
1869{
1870 Log2(("VMMR3HwAccRunGC: (cs:eip=%04x:%08x)\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1871
1872 for (;;)
1873 {
1874 int rc;
1875 do
1876 {
1877#ifdef NO_SUPCALLR0VMM
1878 rc = VERR_GENERAL_FAILURE;
1879#else
1880 rc = SUPCallVMMR0(pVM, VMMR0_DO_HWACC_RUN, NULL);
1881#endif
1882 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
1883
1884#ifdef LOG_ENABLED
1885 /*
1886 * Flush the log
1887 */
1888 PVMMR0LOGGER pR0Logger = pVM->vmm.s.pR0Logger;
1889 if ( pR0Logger
1890 && pR0Logger->Logger.offScratch > 0)
1891 RTLogFlushToLogger(&pR0Logger->Logger, NULL);
1892#endif /* !LOG_ENABLED */
1893 if (rc != VINF_VMM_CALL_HOST)
1894 {
1895 Log2(("VMMR3HwAccRunGC: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1896 return rc;
1897 }
1898 rc = vmmR3ServiceCallHostRequest(pVM);
1899 if (VBOX_FAILURE(rc))
1900 return rc;
1901 /* Resume R0 */
1902 }
1903}
1904
1905/**
1906 * Calls GC a function.
1907 *
1908 * @param pVM The VM handle.
1909 * @param GCPtrEntry The GC function address.
1910 * @param cArgs The number of arguments in the ....
1911 * @param ... Arguments to the function.
1912 */
1913VMMR3DECL(int) VMMR3CallGC(PVM pVM, RTGCPTR GCPtrEntry, unsigned cArgs, ...)
1914{
1915 va_list args;
1916 va_start(args, cArgs);
1917 int rc = VMMR3CallGCV(pVM, GCPtrEntry, cArgs, args);
1918 va_end(args);
1919 return rc;
1920}
1921
1922
1923/**
1924 * Calls GC a function.
1925 *
1926 * @param pVM The VM handle.
1927 * @param GCPtrEntry The GC function address.
1928 * @param cArgs The number of arguments in the ....
1929 * @param args Arguments to the function.
1930 */
1931VMMR3DECL(int) VMMR3CallGCV(PVM pVM, RTGCPTR GCPtrEntry, unsigned cArgs, va_list args)
1932{
1933 Log2(("VMMR3CallGCV: GCPtrEntry=%VGv cArgs=%d\n", GCPtrEntry, cArgs));
1934
1935 /*
1936 * Setup the call frame using the trampoline.
1937 */
1938 CPUMHyperSetCtxCore(pVM, NULL);
1939 memset(pVM->vmm.s.pbHCStack, 0xaa, VMM_STACK_SIZE); /* Clear the stack. */
1940 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom - cArgs * sizeof(RTGCUINTPTR));
1941 PRTGCUINTPTR pFrame = (PRTGCUINTPTR)(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE) - cArgs;
1942 int i = cArgs;
1943 while (i-- > 0)
1944 *pFrame++ = va_arg(args, RTGCUINTPTR);
1945
1946 CPUMPushHyper(pVM, cArgs * sizeof(RTGCUINTPTR)); /* stack frame size */
1947 CPUMPushHyper(pVM, GCPtrEntry); /* what to call */
1948 CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnGCCallTrampoline);
1949
1950 /*
1951 * We hide log flushes (outer) and hypervisor interrupts (inner).
1952 */
1953 for (;;)
1954 {
1955 int rc;
1956 do
1957 {
1958#ifdef NO_SUPCALLR0VMM
1959 rc = VERR_GENERAL_FAILURE;
1960#else
1961 rc = SUPCallVMMR0(pVM, VMMR0_DO_RAW_RUN, NULL);
1962#endif
1963 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
1964
1965 /*
1966 * Flush the logs.
1967 */
1968#ifdef LOG_ENABLED
1969 PRTLOGGERGC pLogger = pVM->vmm.s.pLoggerHC;
1970 if ( pLogger
1971 && pLogger->offScratch > 0)
1972 RTLogFlushGC(NULL, pLogger);
1973#endif
1974#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
1975 PRTLOGGERGC pRelLogger = pVM->vmm.s.pRelLoggerHC;
1976 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
1977 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
1978#endif
1979 if (rc == VERR_TRPM_PANIC || rc == VERR_TRPM_DONT_PANIC)
1980 VMMR3FatalDump(pVM, rc);
1981 if (rc != VINF_VMM_CALL_HOST)
1982 {
1983 Log2(("VMMR3CallGCV: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1984 return rc;
1985 }
1986 rc = vmmR3ServiceCallHostRequest(pVM);
1987 if (VBOX_FAILURE(rc))
1988 return rc;
1989 }
1990}
1991
1992
1993/**
1994 * Resumes executing hypervisor code when interrupted
1995 * by a queue flush or a debug event.
1996 *
1997 * @returns VBox status code.
1998 * @param pVM VM handle.
1999 */
2000VMMR3DECL(int) VMMR3ResumeHyper(PVM pVM)
2001{
2002 Log(("VMMR3ResumeHyper: eip=%VGv esp=%VGv\n", CPUMGetHyperEIP(pVM), CPUMGetHyperESP(pVM)));
2003
2004 /*
2005 * We hide log flushes (outer) and hypervisor interrupts (inner).
2006 */
2007 for (;;)
2008 {
2009 int rc;
2010 do
2011 {
2012#ifdef NO_SUPCALLR0VMM
2013 rc = VERR_GENERAL_FAILURE;
2014#else
2015 rc = SUPCallVMMR0(pVM, VMMR0_DO_RAW_RUN, NULL);
2016#endif
2017 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
2018
2019 /*
2020 * Flush the loggers,
2021 */
2022#ifdef LOG_ENABLED
2023 PRTLOGGERGC pLogger = pVM->vmm.s.pLoggerHC;
2024 if ( pLogger
2025 && pLogger->offScratch > 0)
2026 RTLogFlushGC(NULL, pLogger);
2027#endif
2028#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
2029 PRTLOGGERGC pRelLogger = pVM->vmm.s.pRelLoggerHC;
2030 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
2031 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
2032#endif
2033 if (rc == VERR_TRPM_PANIC || rc == VERR_TRPM_DONT_PANIC)
2034 VMMR3FatalDump(pVM, rc);
2035 if (rc != VINF_VMM_CALL_HOST)
2036 {
2037 Log(("VMMR3ResumeHyper: returns %Vrc\n", rc));
2038 return rc;
2039 }
2040 rc = vmmR3ServiceCallHostRequest(pVM);
2041 if (VBOX_FAILURE(rc))
2042 return rc;
2043 }
2044}
2045
2046
2047/**
2048 * Service a call to the ring-3 host code.
2049 *
2050 * @returns VBox status code.
2051 * @param pVM VM handle.
2052 * @remark Careful with critsects.
2053 */
2054static int vmmR3ServiceCallHostRequest(PVM pVM)
2055{
2056 switch (pVM->vmm.s.enmCallHostOperation)
2057 {
2058 /*
2059 * Acquire the PDM lock.
2060 */
2061 case VMMCALLHOST_PDM_LOCK:
2062 {
2063 pVM->vmm.s.rcCallHost = PDMR3LockCall(pVM);
2064 break;
2065 }
2066
2067 /*
2068 * Flush a PDM queue.
2069 */
2070 case VMMCALLHOST_PDM_QUEUE_FLUSH:
2071 {
2072 PDMR3QueueFlushWorker(pVM, NULL);
2073 pVM->vmm.s.rcCallHost = VINF_SUCCESS;
2074 break;
2075 }
2076
2077 /*
2078 * Grow the PGM pool.
2079 */
2080 case VMMCALLHOST_PGM_POOL_GROW:
2081 {
2082 pVM->vmm.s.rcCallHost = PGMR3PoolGrow(pVM);
2083 break;
2084 }
2085
2086 /*
2087 * Acquire the PGM lock.
2088 */
2089 case VMMCALLHOST_PGM_LOCK:
2090 {
2091 pVM->vmm.s.rcCallHost = PGMR3LockCall(pVM);
2092 break;
2093 }
2094
2095 /*
2096 * Flush REM handler notifications.
2097 */
2098 case VMMCALLHOST_REM_REPLAY_HANDLER_NOTIFICATIONS:
2099 {
2100 REMR3ReplayHandlerNotifications(pVM);
2101 break;
2102 }
2103
2104 case VMMCALLHOST_PGM_RAM_GROW_RANGE:
2105 {
2106 pVM->vmm.s.rcCallHost = PGM3PhysGrowRange(pVM, pVM->vmm.s.u64CallHostArg);
2107 break;
2108 }
2109
2110 /*
2111 * This is a noop. We just take this route to avoid unnecessary
2112 * tests in the loops.
2113 */
2114 case VMMCALLHOST_VMM_LOGGER_FLUSH:
2115 break;
2116
2117 /*
2118 * Set the VM error message.
2119 */
2120 case VMMCALLHOST_VM_SET_ERROR:
2121 VMR3SetErrorWorker(pVM);
2122 break;
2123
2124 /*
2125 * Set the VM runtime error message.
2126 */
2127 case VMMCALLHOST_VM_SET_RUNTIME_ERROR:
2128 VMR3SetRuntimeErrorWorker(pVM);
2129 break;
2130
2131 default:
2132 AssertMsgFailed(("enmCallHostOperation=%d\n", pVM->vmm.s.enmCallHostOperation));
2133 return VERR_INTERNAL_ERROR;
2134 }
2135
2136 pVM->vmm.s.enmCallHostOperation = VMMCALLHOST_INVALID;
2137 return VINF_SUCCESS;
2138}
2139
2140
2141
2142/**
2143 * Structure to pass to DBGFR3Info() and for doing all other
2144 * output during fatal dump.
2145 */
2146typedef struct VMMR3FATALDUMPINFOHLP
2147{
2148 /** The helper core. */
2149 DBGFINFOHLP Core;
2150 /** The release logger instance. */
2151 PRTLOGGER pRelLogger;
2152 /** The saved release logger flags. */
2153 RTUINT fRelLoggerFlags;
2154 /** The logger instance. */
2155 PRTLOGGER pLogger;
2156 /** The saved logger flags. */
2157 RTUINT fLoggerFlags;
2158 /** The saved logger destination flags. */
2159 RTUINT fLoggerDestFlags;
2160 /** Whether to output to stderr or not. */
2161 bool fStdErr;
2162} VMMR3FATALDUMPINFOHLP, *PVMMR3FATALDUMPINFOHLP;
2163typedef const VMMR3FATALDUMPINFOHLP *PCVMMR3FATALDUMPINFOHLP;
2164
2165
2166/**
2167 * Print formatted string.
2168 *
2169 * @param pHlp Pointer to this structure.
2170 * @param pszFormat The format string.
2171 * @param ... Arguments.
2172 */
2173static DECLCALLBACK(void) vmmR3FatalDumpInfoHlp_pfnPrintf(PCDBGFINFOHLP pHlp, const char *pszFormat, ...)
2174{
2175 va_list args;
2176 va_start(args, pszFormat);
2177 pHlp->pfnPrintfV(pHlp, pszFormat, args);
2178 va_end(args);
2179}
2180
2181
2182/**
2183 * Print formatted string.
2184 *
2185 * @param pHlp Pointer to this structure.
2186 * @param pszFormat The format string.
2187 * @param args Argument list.
2188 */
2189static DECLCALLBACK(void) vmmR3FatalDumpInfoHlp_pfnPrintfV(PCDBGFINFOHLP pHlp, const char *pszFormat, va_list args)
2190{
2191 PCVMMR3FATALDUMPINFOHLP pMyHlp = (PCVMMR3FATALDUMPINFOHLP)pHlp;
2192
2193 if (pMyHlp->pRelLogger)
2194 {
2195 va_list args2;
2196 va_copy(args2, args);
2197 RTLogLoggerV(pMyHlp->pRelLogger, pszFormat, args2);
2198 va_end(args2);
2199 }
2200 if (pMyHlp->pLogger)
2201 {
2202 va_list args2;
2203 va_copy(args2, args);
2204 RTLogLoggerV(pMyHlp->pLogger, pszFormat, args);
2205 va_end(args2);
2206 }
2207 if (pMyHlp->fStdErr)
2208 {
2209 va_list args2;
2210 va_copy(args2, args);
2211 RTStrmPrintfV(g_pStdErr, pszFormat, args);
2212 va_end(args2);
2213 }
2214}
2215
2216
2217/**
2218 * Initializes the fatal dump output helper.
2219 *
2220 * @param pHlp The structure to initialize.
2221 */
2222static void vmmR3FatalDumpInfoHlpInit(PVMMR3FATALDUMPINFOHLP pHlp)
2223{
2224 memset(pHlp, 0, sizeof(*pHlp));
2225
2226 pHlp->Core.pfnPrintf = vmmR3FatalDumpInfoHlp_pfnPrintf;
2227 pHlp->Core.pfnPrintfV = vmmR3FatalDumpInfoHlp_pfnPrintfV;
2228
2229 /*
2230 * The loggers.
2231 */
2232 pHlp->pRelLogger = RTLogRelDefaultInstance();
2233#ifndef LOG_ENABLED
2234 if (!pHlp->pRelLogger)
2235#endif
2236 pHlp->pLogger = RTLogDefaultInstance();
2237
2238 if (pHlp->pRelLogger)
2239 {
2240 pHlp->fRelLoggerFlags = pHlp->pRelLogger->fFlags;
2241 pHlp->pRelLogger->fFlags &= ~(RTLOGFLAGS_BUFFERED | RTLOGFLAGS_DISABLED);
2242 }
2243
2244 if (pHlp->pLogger)
2245 {
2246 pHlp->fLoggerFlags = pHlp->pLogger->fFlags;
2247 pHlp->fLoggerDestFlags = pHlp->pLogger->fDestFlags;
2248 pHlp->pLogger->fFlags &= ~(RTLOGFLAGS_BUFFERED | RTLOGFLAGS_DISABLED);
2249 pHlp->pLogger->fDestFlags |= RTLOGDEST_DEBUGGER;
2250 }
2251
2252 /*
2253 * Check if we need write to stderr.
2254 */
2255 pHlp->fStdErr = (!pHlp->pRelLogger || !(pHlp->pRelLogger->fDestFlags & (RTLOGDEST_STDOUT | RTLOGDEST_STDERR)))
2256 && (!pHlp->pLogger || !(pHlp->pLogger->fDestFlags & (RTLOGDEST_STDOUT | RTLOGDEST_STDERR)));
2257}
2258
2259
2260/**
2261 * Deletes the fatal dump output helper.
2262 *
2263 * @param pHlp The structure to delete.
2264 */
2265static void vmmR3FatalDumpInfoHlpDelete(PVMMR3FATALDUMPINFOHLP pHlp)
2266{
2267 if (pHlp->pRelLogger)
2268 {
2269 RTLogFlush(pHlp->pRelLogger);
2270 pHlp->pRelLogger->fFlags = pHlp->fRelLoggerFlags;
2271 }
2272
2273 if (pHlp->pLogger)
2274 {
2275 RTLogFlush(pHlp->pLogger);
2276 pHlp->pLogger->fFlags = pHlp->fLoggerFlags;
2277 pHlp->pLogger->fDestFlags = pHlp->fLoggerDestFlags;
2278 }
2279}
2280
2281
2282/**
2283 * Dumps the VM state on a fatal error.
2284 *
2285 * @param pVM VM Handle.
2286 * @param rcErr VBox status code.
2287 */
2288VMMR3DECL(void) VMMR3FatalDump(PVM pVM, int rcErr)
2289{
2290 /*
2291 * Create our output helper and sync it with the log settings.
2292 * This helper will be used for all the output.
2293 */
2294 VMMR3FATALDUMPINFOHLP Hlp;
2295 PCDBGFINFOHLP pHlp = &Hlp.Core;
2296 vmmR3FatalDumpInfoHlpInit(&Hlp);
2297
2298 /*
2299 * Header.
2300 */
2301 pHlp->pfnPrintf(pHlp,
2302 "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n"
2303 "!!\n"
2304 "!! Guru Meditation %d (%Vrc)\n"
2305 "!!\n",
2306 rcErr, rcErr);
2307
2308 /*
2309 * Continue according to context.
2310 */
2311 bool fDoneHyper = false;
2312 switch (rcErr)
2313 {
2314 /*
2315 * Hyper visor errors.
2316 */
2317 case VINF_EM_DBG_HYPER_ASSERTION:
2318 pHlp->pfnPrintf(pHlp, "%s%s!!\n", VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
2319 /* fall thru */
2320 case VERR_TRPM_DONT_PANIC:
2321 case VERR_TRPM_PANIC:
2322 case VINF_EM_RAW_STALE_SELECTOR:
2323 case VINF_EM_RAW_IRET_TRAP:
2324 case VINF_EM_DBG_HYPER_BREAKPOINT:
2325 case VINF_EM_DBG_HYPER_STEPPED:
2326 {
2327 /* Trap? */
2328 uint32_t uEIP = CPUMGetHyperEIP(pVM);
2329 bool fSoftwareInterrupt = false;
2330 uint8_t u8TrapNo = 0xce;
2331 RTGCUINT uErrorCode = 0xdeadface;
2332 RTGCUINTPTR uCR2 = 0xdeadface;
2333 int rc2 = TRPMQueryTrapAll(pVM, &u8TrapNo, &fSoftwareInterrupt, &uErrorCode, &uCR2);
2334 if (VBOX_SUCCESS(rc2))
2335 pHlp->pfnPrintf(pHlp,
2336 "!! TRAP=%02x ERRCD=%VGv CR2=%VGv EIP=%VGv fSoft=%d\n",
2337 u8TrapNo, uErrorCode, uCR2, uEIP, fSoftwareInterrupt);
2338 else
2339 pHlp->pfnPrintf(pHlp,
2340 "!! EIP=%VGv NOTRAP\n",
2341 uEIP);
2342
2343 /*
2344 * Try figure out where eip is.
2345 */
2346 /** @todo make query call for core code or move this function to VMM. */
2347 /* core code? */
2348 //if (uEIP - (RTGCUINTPTR)pVM->vmm.s.pvGCCoreCode < pVM->vmm.s.cbCoreCode)
2349 // pHlp->pfnPrintf(pHlp,
2350 // "!! EIP is in CoreCode, offset %#x\n",
2351 // uEIP - (RTGCUINTPTR)pVM->vmm.s.pvGCCoreCode);
2352 //else
2353 { /* ask PDM */
2354 /** @todo ask DBGFR3Sym later. */
2355 char szModName[64];
2356 RTGCPTR GCPtrMod;
2357 char szNearSym1[260];
2358 RTGCPTR GCPtrNearSym1;
2359 char szNearSym2[260];
2360 RTGCPTR GCPtrNearSym2;
2361 int rc = PDMR3QueryModFromEIP(pVM, uEIP,
2362 &szModName[0], sizeof(szModName), &GCPtrMod,
2363 &szNearSym1[0], sizeof(szNearSym1), &GCPtrNearSym1,
2364 &szNearSym2[0], sizeof(szNearSym2), &GCPtrNearSym2);
2365 if (VBOX_SUCCESS(rc))
2366 {
2367 pHlp->pfnPrintf(pHlp,
2368 "!! EIP in %s (%p) at rva %x near symbols:\n"
2369 "!! %VGv rva %VGv off %08x %s\n"
2370 "!! %VGv rva %VGv off -%08x %s\n",
2371 szModName, GCPtrMod, (unsigned)(uEIP - GCPtrMod),
2372 GCPtrNearSym1, GCPtrNearSym1 - GCPtrMod, (unsigned)(uEIP - GCPtrNearSym1), szNearSym1,
2373 GCPtrNearSym2, GCPtrNearSym2 - GCPtrMod, (unsigned)(GCPtrNearSym2 - uEIP), szNearSym2);
2374 }
2375 else
2376 pHlp->pfnPrintf(pHlp,
2377 "!! EIP is not in any code known to VMM!\n");
2378 }
2379
2380 /* Disassemble the instruction. */
2381 char szInstr[256];
2382 rc2 = DBGFR3DisasInstrEx(pVM, 0, 0, DBGF_DISAS_FLAGS_CURRENT_HYPER, &szInstr[0], sizeof(szInstr), NULL);
2383 if (VBOX_SUCCESS(rc2))
2384 pHlp->pfnPrintf(pHlp,
2385 "!! %s\n", szInstr);
2386
2387 /* Dump the hypervisor cpu state. */
2388 pHlp->pfnPrintf(pHlp,
2389 "!!\n"
2390 "!!\n"
2391 "!!\n");
2392 rc2 = DBGFR3Info(pVM, "cpumhyper", "verbose", pHlp);
2393 fDoneHyper = true;
2394
2395 /* Callstack. */
2396 DBGFSTACKFRAME Frame = {0};
2397 rc2 = DBGFR3StackWalkBeginHyper(pVM, &Frame);
2398 if (VBOX_SUCCESS(rc2))
2399 {
2400 pHlp->pfnPrintf(pHlp,
2401 "!!\n"
2402 "!! Call Stack:\n"
2403 "!!\n"
2404 "EBP Ret EBP Ret CS:EIP Arg0 Arg1 Arg2 Arg3 CS:EIP Symbol [line]\n");
2405 do
2406 {
2407 pHlp->pfnPrintf(pHlp,
2408 "%08RX32 %08RX32 %04RX32:%08RX32 %08RX32 %08RX32 %08RX32 %08RX32",
2409 (uint32_t)Frame.AddrFrame.off,
2410 (uint32_t)Frame.AddrReturnFrame.off,
2411 (uint32_t)Frame.AddrReturnPC.Sel,
2412 (uint32_t)Frame.AddrReturnPC.off,
2413 Frame.Args.au32[0],
2414 Frame.Args.au32[1],
2415 Frame.Args.au32[2],
2416 Frame.Args.au32[3]);
2417 pHlp->pfnPrintf(pHlp, " %RTsel:%08RGv", Frame.AddrPC.Sel, Frame.AddrPC.off);
2418 if (Frame.pSymPC)
2419 {
2420 RTGCINTPTR offDisp = Frame.AddrPC.FlatPtr - Frame.pSymPC->Value;
2421 if (offDisp > 0)
2422 pHlp->pfnPrintf(pHlp, " %s+%llx", Frame.pSymPC->szName, (int64_t)offDisp);
2423 else if (offDisp < 0)
2424 pHlp->pfnPrintf(pHlp, " %s-%llx", Frame.pSymPC->szName, -(int64_t)offDisp);
2425 else
2426 pHlp->pfnPrintf(pHlp, " %s", Frame.pSymPC->szName);
2427 }
2428 if (Frame.pLinePC)
2429 pHlp->pfnPrintf(pHlp, " [%s @ 0i%d]", Frame.pLinePC->szFilename, Frame.pLinePC->uLineNo);
2430 pHlp->pfnPrintf(pHlp, "\n");
2431
2432 /* next */
2433 rc2 = DBGFR3StackWalkNext(pVM, &Frame);
2434 } while (VBOX_SUCCESS(rc2));
2435 DBGFR3StackWalkEnd(pVM, &Frame);
2436 }
2437
2438 /* raw stack */
2439 pHlp->pfnPrintf(pHlp,
2440 "!!\n"
2441 "!! Raw stack (mind the direction).\n"
2442 "!!\n"
2443 "%.*Vhxd\n",
2444 VMM_STACK_SIZE, (char *)pVM->vmm.s.pbHCStack);
2445 break;
2446 }
2447
2448 default:
2449 {
2450 break;
2451 }
2452
2453 } /* switch (rcErr) */
2454
2455
2456 /*
2457 * Dump useful state information.
2458 */
2459 /** @todo convert these dumpers to DBGFR3Info() handlers!!! */
2460 pHlp->pfnPrintf(pHlp,
2461 "!!\n"
2462 "!! PGM Access Handlers & Stuff:\n"
2463 "!!\n");
2464 PGMR3DumpMappings(pVM);
2465
2466
2467 /*
2468 * Generic info dumper loop.
2469 */
2470 static struct
2471 {
2472 const char *pszInfo;
2473 const char *pszArgs;
2474 } const aInfo[] =
2475 {
2476 { "hma", NULL },
2477 { "cpumguest", "verbose" },
2478 { "cpumhyper", "verbose" },
2479 { "cpumhost", "verbose" },
2480 { "mode", "all" },
2481 { "cpuid", "verbose" },
2482 { "gdt", NULL },
2483 { "ldt", NULL },
2484 //{ "tss", NULL },
2485 { "ioport", NULL },
2486 { "mmio", NULL },
2487 { "phys", NULL },
2488 //{ "pgmpd", NULL }, - doesn't always work at init time...
2489 { "timers", NULL },
2490 { "activetimers", NULL },
2491 { "handlers", "phys virt stats" },
2492 { "cfgm", NULL },
2493 };
2494 for (unsigned i = 0; i < ELEMENTS(aInfo); i++)
2495 {
2496 if (fDoneHyper && !strcmp(aInfo[i].pszInfo, "cpumhyper"))
2497 continue;
2498 pHlp->pfnPrintf(pHlp,
2499 "!!\n"
2500 "!! {%s, %s}\n"
2501 "!!\n",
2502 aInfo[i].pszInfo, aInfo[i].pszArgs);
2503 DBGFR3Info(pVM, aInfo[i].pszInfo, aInfo[i].pszArgs, pHlp);
2504 }
2505
2506 /* done */
2507 pHlp->pfnPrintf(pHlp,
2508 "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n");
2509
2510
2511 /*
2512 * Delete the output instance (flushing and restoring of flags).
2513 */
2514 vmmR3FatalDumpInfoHlpDelete(&Hlp);
2515}
2516
2517
2518/**
2519 * Performs a testcase.
2520 *
2521 * @returns return value from the test.
2522 * @param pVM The VM handle.
2523 * @param enmTestcase The testcase operation to perform.
2524 * @param uVariation The testcase variation id.
2525 */
2526static int vmmR3DoGCTest(PVM pVM, VMMGCOPERATION enmTestcase, unsigned uVariation)
2527{
2528 RTGCPTR GCPtrEP;
2529 int rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &GCPtrEP);
2530 if (VBOX_FAILURE(rc))
2531 return rc;
2532
2533 CPUMHyperSetCtxCore(pVM, NULL);
2534 memset(pVM->vmm.s.pbHCStack, 0xaa, VMM_STACK_SIZE);
2535 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom); /* Clear the stack. */
2536 CPUMPushHyper(pVM, uVariation);
2537 CPUMPushHyper(pVM, enmTestcase);
2538 CPUMPushHyper(pVM, pVM->pVMGC);
2539 CPUMPushHyper(pVM, 3 * sizeof(RTGCPTR)); /* stack frame size */
2540 CPUMPushHyper(pVM, GCPtrEP); /* what to call */
2541 CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnGCCallTrampoline);
2542 return SUPCallVMMR0(pVM, VMMR0_DO_RAW_RUN, NULL);
2543}
2544
2545
2546/**
2547 * Performs a trap test.
2548 *
2549 * @returns Return value from the trap test.
2550 * @param pVM The VM handle.
2551 * @param u8Trap The trap number to test.
2552 * @param uVariation The testcase variation.
2553 * @param rcExpect The expected result.
2554 * @param u32Eax The expected eax value.
2555 * @param pszFaultEIP The fault address. Pass NULL if this isn't available or doesn't apply.
2556 * @param pszDesc The test description.
2557 */
2558static int vmmR3DoTrapTest(PVM pVM, uint8_t u8Trap, unsigned uVariation, int rcExpect, uint32_t u32Eax, const char *pszFaultEIP, const char *pszDesc)
2559{
2560 RTPrintf("VMM: testing 0%x / %d - %s\n", u8Trap, uVariation, pszDesc);
2561
2562 RTGCPTR GCPtrEP;
2563 int rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &GCPtrEP);
2564 if (VBOX_FAILURE(rc))
2565 return rc;
2566
2567 CPUMHyperSetCtxCore(pVM, NULL);
2568 memset(pVM->vmm.s.pbHCStack, 0xaa, VMM_STACK_SIZE);
2569 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom); /* Clear the stack. */
2570 CPUMPushHyper(pVM, uVariation);
2571 CPUMPushHyper(pVM, u8Trap + VMMGC_DO_TESTCASE_TRAP_FIRST);
2572 CPUMPushHyper(pVM, pVM->pVMGC);
2573 CPUMPushHyper(pVM, 3 * sizeof(RTGCPTR)); /* stack frame size */
2574 CPUMPushHyper(pVM, GCPtrEP); /* what to call */
2575 CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnGCCallTrampoline);
2576 rc = SUPCallVMMR0(pVM, VMMR0_DO_RAW_RUN, NULL);
2577 bool fDump = false;
2578 if (rc != rcExpect)
2579 {
2580 RTPrintf("VMM: FAILURE - rc=%Vrc expected %Vrc\n", rc, rcExpect);
2581 if (rc != VERR_NOT_IMPLEMENTED)
2582 fDump = true;
2583 }
2584 else if ( u8Trap != 8 /* double fault doesn't dare setting TrapNo. */
2585 && u8Trap != 3 /* guest only, we're not in guest. */
2586 && u8Trap != 1 /* guest only, we're not in guest. */
2587 && u8Trap != TRPMGetTrapNo(pVM))
2588 {
2589 RTPrintf("VMM: FAILURE - Trap %#x expected %#x\n", TRPMGetTrapNo(pVM), u8Trap);
2590 fDump = true;
2591 }
2592 else if (pszFaultEIP)
2593 {
2594 RTGCPTR GCPtrFault;
2595 int rc2 = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, pszFaultEIP, &GCPtrFault);
2596 if (VBOX_FAILURE(rc2))
2597 RTPrintf("VMM: FAILURE - Failed to resolve symbol '%s', %Vrc!\n", pszFaultEIP, rc);
2598 else if (GCPtrFault != CPUMGetHyperEIP(pVM))
2599 {
2600 RTPrintf("VMM: FAILURE - EIP=%VGv expected %VGv (%s)\n", CPUMGetHyperEIP(pVM), GCPtrFault, pszFaultEIP);
2601 fDump = true;
2602 }
2603 }
2604 else
2605 {
2606 if (CPUMGetHyperSS(pVM) == SELMGetHyperDS(pVM))
2607 RTPrintf("VMM: FAILURE - ss=%x expected %x\n", CPUMGetHyperSS(pVM), SELMGetHyperDS(pVM));
2608 if (CPUMGetHyperES(pVM) == SELMGetHyperDS(pVM))
2609 RTPrintf("VMM: FAILURE - es=%x expected %x\n", CPUMGetHyperES(pVM), SELMGetHyperDS(pVM));
2610 if (CPUMGetHyperDS(pVM) == SELMGetHyperDS(pVM))
2611 RTPrintf("VMM: FAILURE - ds=%x expected %x\n", CPUMGetHyperDS(pVM), SELMGetHyperDS(pVM));
2612 if (CPUMGetHyperFS(pVM) == SELMGetHyperDS(pVM))
2613 RTPrintf("VMM: FAILURE - fs=%x expected %x\n", CPUMGetHyperFS(pVM), SELMGetHyperDS(pVM));
2614 if (CPUMGetHyperGS(pVM) == SELMGetHyperDS(pVM))
2615 RTPrintf("VMM: FAILURE - gs=%x expected %x\n", CPUMGetHyperGS(pVM), SELMGetHyperDS(pVM));
2616 if (CPUMGetHyperEDI(pVM) == 0x01234567)
2617 RTPrintf("VMM: FAILURE - edi=%x expected %x\n", CPUMGetHyperEDI(pVM), 0x01234567);
2618 if (CPUMGetHyperESI(pVM) == 0x42000042)
2619 RTPrintf("VMM: FAILURE - esi=%x expected %x\n", CPUMGetHyperESI(pVM), 0x42000042);
2620 if (CPUMGetHyperEBP(pVM) == 0xffeeddcc)
2621 RTPrintf("VMM: FAILURE - ebp=%x expected %x\n", CPUMGetHyperEBP(pVM), 0xffeeddcc);
2622 if (CPUMGetHyperEBX(pVM) == 0x89abcdef)
2623 RTPrintf("VMM: FAILURE - ebx=%x expected %x\n", CPUMGetHyperEBX(pVM), 0x89abcdef);
2624 if (CPUMGetHyperECX(pVM) == 0xffffaaaa)
2625 RTPrintf("VMM: FAILURE - ecx=%x expected %x\n", CPUMGetHyperECX(pVM), 0xffffaaaa);
2626 if (CPUMGetHyperEDX(pVM) == 0x77778888)
2627 RTPrintf("VMM: FAILURE - edx=%x expected %x\n", CPUMGetHyperEDX(pVM), 0x77778888);
2628 if (CPUMGetHyperEAX(pVM) == u32Eax)
2629 RTPrintf("VMM: FAILURE - eax=%x expected %x\n", CPUMGetHyperEAX(pVM), u32Eax);
2630 }
2631 if (fDump)
2632 VMMR3FatalDump(pVM, rc);
2633 return rc;
2634}
2635
2636
2637/* execute the switch. */
2638VMMR3DECL(int) VMMDoTest(PVM pVM)
2639{
2640#if 1
2641#ifdef NO_SUPCALLR0VMM
2642 RTPrintf("NO_SUPCALLR0VMM\n");
2643 return VINF_SUCCESS;
2644#endif
2645
2646 /*
2647 * Setup stack for calling VMMGCEntry().
2648 */
2649 RTGCPTR GCPtrEP;
2650 int rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &GCPtrEP);
2651 if (VBOX_SUCCESS(rc))
2652 {
2653 RTPrintf("VMM: VMMGCEntry=%VGv\n", GCPtrEP);
2654
2655 /*
2656 * Test various crashes which we must be able to recover from.
2657 */
2658 vmmR3DoTrapTest(pVM, 0x3, 0, VINF_EM_DBG_HYPER_ASSERTION, 0xf0f0f0f0, "vmmGCTestTrap3_FaultEIP", "int3");
2659 vmmR3DoTrapTest(pVM, 0x3, 1, VINF_EM_DBG_HYPER_ASSERTION, 0xf0f0f0f0, "vmmGCTestTrap3_FaultEIP", "int3 WP");
2660
2661#if defined(DEBUG_bird) /* guess most people would like to skip these since they write to com1. */
2662 vmmR3DoTrapTest(pVM, 0x8, 0, VERR_TRPM_PANIC, 0x00000000, "vmmGCTestTrap8_FaultEIP", "#DF [#PG]");
2663 SELMR3Relocate(pVM); /* this resets the busy flag of the Trap 08 TSS */
2664 bool f;
2665 rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "DoubleFault", &f);
2666#if !defined(DEBUG_bird)
2667 if (VBOX_SUCCESS(rc) && f)
2668#endif
2669 {
2670 /* see tripple fault warnings in SELM and VMMGC.cpp. */
2671 vmmR3DoTrapTest(pVM, 0x8, 1, VERR_TRPM_PANIC, 0x00000000, "vmmGCTestTrap8_FaultEIP", "#DF [#PG] WP");
2672 SELMR3Relocate(pVM); /* this resets the busy flag of the Trap 08 TSS */
2673 }
2674#endif
2675
2676 vmmR3DoTrapTest(pVM, 0xd, 0, VERR_TRPM_DONT_PANIC, 0xf0f0f0f0, "vmmGCTestTrap0d_FaultEIP", "ltr #GP");
2677 ///@todo find a better \#GP case, on intel ltr will \#PF (busy update?) and not \#GP.
2678 //vmmR3DoTrapTest(pVM, 0xd, 1, VERR_TRPM_DONT_PANIC, 0xf0f0f0f0, "vmmGCTestTrap0d_FaultEIP", "ltr #GP WP");
2679
2680 vmmR3DoTrapTest(pVM, 0xe, 0, VERR_TRPM_DONT_PANIC, 0x00000000, "vmmGCTestTrap0e_FaultEIP", "#PF (NULL)");
2681 vmmR3DoTrapTest(pVM, 0xe, 1, VERR_TRPM_DONT_PANIC, 0x00000000, "vmmGCTestTrap0e_FaultEIP", "#PF (NULL) WP");
2682
2683 /*
2684 * Set a debug register and perform a context switch.
2685 */
2686 rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_NOP, 0);
2687 if (rc != VINF_SUCCESS)
2688 {
2689 RTPrintf("VMM: Nop test failed, rc=%Vrc not VINF_SUCCESS\n", rc);
2690 return rc;
2691 }
2692
2693 /* a harmless breakpoint */
2694 RTPrintf("VMM: testing hardware bp at 0x10000 (not hit)\n");
2695 DBGFADDRESS Addr;
2696 DBGFR3AddrFromFlat(pVM, &Addr, 0x10000);
2697 RTUINT iBp0;
2698 rc = DBGFR3BpSetReg(pVM, &Addr, 0, ~(uint64_t)0, X86_DR7_RW_EO, 1, &iBp0);
2699 AssertReleaseRC(rc);
2700 rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_NOP, 0);
2701 if (rc != VINF_SUCCESS)
2702 {
2703 RTPrintf("VMM: DR0=0x10000 test failed with rc=%Vrc!\n", rc);
2704 return rc;
2705 }
2706
2707 /* a bad one at VMMGCEntry */
2708 RTPrintf("VMM: testing hardware bp at VMMGCEntry (hit)\n");
2709 DBGFR3AddrFromFlat(pVM, &Addr, GCPtrEP);
2710 RTUINT iBp1;
2711 rc = DBGFR3BpSetReg(pVM, &Addr, 0, ~(uint64_t)0, X86_DR7_RW_EO, 1, &iBp1);
2712 AssertReleaseRC(rc);
2713 rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_NOP, 0);
2714 if (rc != VINF_EM_DBG_HYPER_BREAKPOINT)
2715 {
2716 RTPrintf("VMM: DR1=VMMGCEntry test failed with rc=%Vrc! expected VINF_EM_RAW_BREAKPOINT_HYPER\n", rc);
2717 return rc;
2718 }
2719
2720 /* resume the breakpoint */
2721 RTPrintf("VMM: resuming hyper after breakpoint\n");
2722 CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) | X86_EFL_RF);
2723 rc = VMMR3ResumeHyper(pVM);
2724 if (rc != VINF_SUCCESS)
2725 {
2726 RTPrintf("VMM: failed to resume on hyper breakpoint, rc=%Vrc\n", rc);
2727 return rc;
2728 }
2729
2730 /* engage the breakpoint again and try single stepping. */
2731 RTPrintf("VMM: testing hardware bp at VMMGCEntry + stepping\n");
2732 rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_NOP, 0);
2733 if (rc != VINF_EM_DBG_HYPER_BREAKPOINT)
2734 {
2735 RTPrintf("VMM: DR1=VMMGCEntry test failed with rc=%Vrc! expected VINF_EM_RAW_BREAKPOINT_HYPER\n", rc);
2736 return rc;
2737 }
2738
2739 RTGCUINTREG OldPc = CPUMGetHyperEIP(pVM);
2740 RTPrintf("%RGr=>", OldPc);
2741 unsigned i;
2742 for (i = 0; i < 8; i++)
2743 {
2744 CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) | X86_EFL_TF | X86_EFL_RF);
2745 rc = VMMR3ResumeHyper(pVM);
2746 if (rc != VINF_EM_DBG_HYPER_STEPPED)
2747 {
2748 RTPrintf("\nVMM: failed to step on hyper breakpoint, rc=%Vrc\n", rc);
2749 return rc;
2750 }
2751 RTGCUINTREG Pc = CPUMGetHyperEIP(pVM);
2752 RTPrintf("%RGr=>", Pc);
2753 if (Pc == OldPc)
2754 {
2755 RTPrintf("\nVMM: step failed, PC: %RGr -> %RGr\n", OldPc, Pc);
2756 return VERR_GENERAL_FAILURE;
2757 }
2758 OldPc = Pc;
2759 }
2760 RTPrintf("ok\n");
2761
2762 /* done, clear it */
2763 if ( VBOX_FAILURE(DBGFR3BpClear(pVM, iBp0))
2764 || VBOX_FAILURE(DBGFR3BpClear(pVM, iBp1)))
2765 {
2766 RTPrintf("VMM: Failed to clear breakpoints!\n");
2767 return VERR_GENERAL_FAILURE;
2768 }
2769 rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_NOP, 0);
2770 if (rc != VINF_SUCCESS)
2771 {
2772 RTPrintf("VMM: NOP failed, rc=%Vrc\n", rc);
2773 return rc;
2774 }
2775
2776 /*
2777 * Interrupt forwarding.
2778 */
2779 CPUMHyperSetCtxCore(pVM, NULL);
2780 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom); /* Clear the stack. */
2781 CPUMPushHyper(pVM, 0);
2782 CPUMPushHyper(pVM, VMMGC_DO_TESTCASE_HYPER_INTERRUPT);
2783 CPUMPushHyper(pVM, pVM->pVMGC);
2784 CPUMPushHyper(pVM, 3 * sizeof(RTGCPTR)); /* stack frame size */
2785 CPUMPushHyper(pVM, GCPtrEP); /* what to call */
2786 CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnGCCallTrampoline);
2787 Log(("trampoline=%x\n", pVM->vmm.s.pfnGCCallTrampoline));
2788
2789 /*
2790 * Switch and do da thing.
2791 */
2792 RTPrintf("VMM: interrupt forwarding...\n"); RTStrmFlush(g_pStdOut); RTThreadSleep(250);
2793 i = 0;
2794 uint64_t tsBegin = RTTimeNanoTS();
2795 uint64_t TickStart = ASMReadTSC();
2796 do
2797 {
2798 rc = SUPCallVMMR0(pVM, VMMR0_DO_RAW_RUN, NULL);
2799 if (VBOX_FAILURE(rc))
2800 {
2801 Log(("VMM: GC returned fatal %Vra in iteration %d\n", rc, i));
2802 VMMR3FatalDump(pVM, rc);
2803 return rc;
2804 }
2805 i++;
2806 if (!(i % 32))
2807 Log(("VMM: iteration %d, esi=%08x edi=%08x ebx=%08x\n",
2808 i, CPUMGetHyperESI(pVM), CPUMGetHyperEDI(pVM), CPUMGetHyperEBX(pVM)));
2809 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
2810 uint64_t TickEnd = ASMReadTSC();
2811 uint64_t tsEnd = RTTimeNanoTS();
2812
2813 uint64_t Elapsed = tsEnd - tsBegin;
2814 uint64_t PerIteration = Elapsed / (uint64_t)i;
2815 uint64_t cTicksElapsed = TickEnd - TickStart;
2816 uint64_t cTicksPerIteration = cTicksElapsed / (uint64_t)i;
2817
2818 RTPrintf("VMM: %8d interrupts in %11llu ns (%11llu ticks), %10llu ns/iteration (%11llu ticks)\n",
2819 i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration);
2820 Log(("VMM: %8d interrupts in %11llu ns (%11llu ticks), %10llu ns/iteration (%11llu ticks)\n",
2821 i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration));
2822
2823 /*
2824 * These forced actions are not necessary for the test and trigger breakpoints too.
2825 */
2826 VM_FF_CLEAR(pVM, VM_FF_TRPM_SYNC_IDT);
2827 VM_FF_CLEAR(pVM, VM_FF_SELM_SYNC_TSS);
2828
2829 /*
2830 * Profile switching.
2831 */
2832 RTPrintf("VMM: profiling switcher...\n");
2833 Log(("VMM: profiling switcher...\n"));
2834 uint64_t TickMin = ~0;
2835 tsBegin = RTTimeNanoTS();
2836 TickStart = ASMReadTSC();
2837 for (i = 0; i < 1000000; i++)
2838 {
2839 CPUMHyperSetCtxCore(pVM, NULL);
2840 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom); /* Clear the stack. */
2841 CPUMPushHyper(pVM, 0);
2842 CPUMPushHyper(pVM, VMMGC_DO_TESTCASE_NOP);
2843 CPUMPushHyper(pVM, pVM->pVMGC);
2844 CPUMPushHyper(pVM, 3 * sizeof(RTGCPTR)); /* stack frame size */
2845 CPUMPushHyper(pVM, GCPtrEP); /* what to call */
2846 CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnGCCallTrampoline);
2847
2848 uint64_t TickThisStart = ASMReadTSC();
2849 rc = SUPCallVMMR0(pVM, VMMR0_DO_RAW_RUN, NULL);
2850 uint64_t TickThisElapsed = ASMReadTSC() - TickThisStart;
2851 if (VBOX_FAILURE(rc))
2852 {
2853 Log(("VMM: GC returned fatal %Vra in iteration %d\n", rc, i));
2854 VMMR3FatalDump(pVM, rc);
2855 return rc;
2856 }
2857 if (TickThisElapsed < TickMin)
2858 TickMin = TickThisElapsed;
2859 }
2860 TickEnd = ASMReadTSC();
2861 tsEnd = RTTimeNanoTS();
2862
2863 Elapsed = tsEnd - tsBegin;
2864 PerIteration = Elapsed / (uint64_t)i;
2865 cTicksElapsed = TickEnd - TickStart;
2866 cTicksPerIteration = cTicksElapsed / (uint64_t)i;
2867
2868 RTPrintf("VMM: %8d cycles in %11llu ns (%11lld ticks), %10llu ns/iteration (%11lld ticks) Min %11lld ticks\n",
2869 i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration, TickMin);
2870 Log(("VMM: %8d cycles in %11llu ns (%11lld ticks), %10llu ns/iteration (%11lld ticks) Min %11lld ticks\n",
2871 i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration, TickMin));
2872
2873 rc = VINF_SUCCESS;
2874 }
2875 else
2876 AssertMsgFailed(("Failed to resolved VMMGC.gc::VMMGCEntry(), rc=%Vrc\n", rc));
2877#endif
2878 return rc;
2879}
2880
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