VirtualBox

source: vbox/trunk/src/VBox/VMM/VMM.cpp@ 6300

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1/* $Id: VMM.cpp 6300 2008-01-09 16:41:22Z vboxsync $ */
2/** @file
3 * VMM - The Virtual Machine Monitor Core.
4 */
5
6/*
7 * Copyright (C) 2006-2007 innotek GmbH
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18//#define NO_SUPCALLR0VMM
19
20/** @page pg_vmm VMM - The Virtual Machine Monitor
21 *
22 * !Revise this! It's already incorrect!
23 *
24 * The Virtual Machine Monitor (VMM) is the core of the virtual machine. It
25 * manages the alternate reality; controlling the virtualization, managing
26 * resources, tracking CPU state, it's resources and so on...
27 *
28 * We will split the VMM into smaller entities:
29 *
30 * - Virtual Machine Core Monitor (VMCM), which purpose it is to
31 * provide ring and world switching, that including routing
32 * interrupts to the host OS and traps to the appropriate trap
33 * handlers. It will implement an external interface for
34 * managing trap handlers.
35 *
36 * - CPU Monitor (CM), tracking the state of the CPU (in the alternate
37 * reality) and implementing external interfaces to read and change
38 * the state.
39 *
40 * - Memory Monitor (MM), which purpose it is to virtualize physical
41 * pages, segment descriptor tables, interrupt descriptor tables, task
42 * segments, and keep track of all memory providing external interfaces
43 * to access content and map pages. (Internally splitt into smaller entities!)
44 *
45 * - IO Monitor (IOM), which virtualizes in and out I/O operations. It
46 * interacts with the MM to implement memory mapped I/O. External
47 * interfaces for adding and removing I/O ranges are implemented.
48 *
49 * - External Interrupt Monitor (EIM), which purpose it is to manage
50 * interrupts generated by virtual devices. This monitor provides
51 * an interfaces for raising interrupts which is accessible at any
52 * time and from all thread.
53 * <p>
54 * A subentity of the EIM is the vitual Programmable Interrupt
55 * Controller Device (VPICD), and perhaps a virtual I/O Advanced
56 * Programmable Interrupt Controller Device (VAPICD).
57 *
58 * - Direct Memory Access Monitor (DMAM), which purpose it is to support
59 * virtual device using the DMA controller. Interfaces must be as the
60 * EIM interfaces independent and threadable.
61 * <p>
62 * A subentity of the DMAM is a virtual DMA Controller Device (VDMACD).
63 *
64 *
65 * Entities working on a higher level:
66 *
67 * - Device Manager (DM), which is a support facility for virtualized
68 * hardware. This provides generic facilities for efficient device
69 * virtualization. It will manage device attaching and detaching
70 * conversing with EIM and IOM.
71 *
72 * - Debugger Facility (DBGF) provides the basic features for
73 * debugging the alternate reality execution.
74 *
75 *
76 *
77 * @section pg_vmm_s_use_cases Use Cases
78 *
79 * @subsection pg_vmm_s_use_case_boot Bootstrap
80 *
81 * - Basic Init:
82 * - Init SUPDRV.
83 *
84 * - Init Virtual Machine Instance:
85 * - Load settings.
86 * - Check resource requirements (memory, com, stuff).
87 *
88 * - Init Host Ring 3 part:
89 * - Init Core code.
90 * - Load Pluggable Components.
91 * - Init Pluggable Components.
92 *
93 * - Init Host Ring 0 part:
94 * - Load Core (core = core components like VMM, RMI, CA, and so on) code.
95 * - Init Core code.
96 * - Load Pluggable Component code.
97 * - Init Pluggable Component code.
98 *
99 * - Allocate first chunk of memory and pin it down. This block of memory
100 * will fit the following pieces:
101 * - Virtual Machine Instance data. (Config, CPU state, VMM state, ++)
102 * (This is available from everywhere (at different addresses though)).
103 * - VMM Guest Context code.
104 * - Pluggable devices Guest Context code.
105 * - Page tables (directory and everything) for the VMM Guest
106 *
107 * - Setup Guest (Ring 0) part:
108 * - Setup initial page tables (i.e. directory all the stuff).
109 * - Load Core Guest Context code.
110 * - Load Pluggable Devices Guest Context code.
111 *
112 *
113 */
114
115
116/*******************************************************************************
117* Header Files *
118*******************************************************************************/
119#define LOG_GROUP LOG_GROUP_VMM
120#include <VBox/vmm.h>
121#include <VBox/vmapi.h>
122#include <VBox/pgm.h>
123#include <VBox/cfgm.h>
124#include <VBox/pdmqueue.h>
125#include <VBox/pdmapi.h>
126#include <VBox/cpum.h>
127#include <VBox/mm.h>
128#include <VBox/iom.h>
129#include <VBox/trpm.h>
130#include <VBox/selm.h>
131#include <VBox/em.h>
132#include <VBox/sup.h>
133#include <VBox/dbgf.h>
134#include <VBox/csam.h>
135#include <VBox/patm.h>
136#include <VBox/rem.h>
137#include <VBox/ssm.h>
138#include <VBox/tm.h>
139#include "VMMInternal.h"
140#include "VMMSwitcher/VMMSwitcher.h"
141#include <VBox/vm.h>
142#include <VBox/err.h>
143#include <VBox/param.h>
144#include <VBox/version.h>
145#include <VBox/x86.h>
146#include <VBox/hwaccm.h>
147#include <iprt/assert.h>
148#include <iprt/alloc.h>
149#include <iprt/asm.h>
150#include <iprt/time.h>
151#include <iprt/stream.h>
152#include <iprt/string.h>
153#include <iprt/stdarg.h>
154#include <iprt/ctype.h>
155
156
157
158/** The saved state version. */
159#define VMM_SAVED_STATE_VERSION 3
160
161
162/*******************************************************************************
163* Internal Functions *
164*******************************************************************************/
165static DECLCALLBACK(int) vmmR3Save(PVM pVM, PSSMHANDLE pSSM);
166static DECLCALLBACK(int) vmmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
167static DECLCALLBACK(void) vmmR3YieldEMT(PVM pVM, PTMTIMER pTimer, void *pvUser);
168static int vmmR3ServiceCallHostRequest(PVM pVM);
169static DECLCALLBACK(void) vmmR3InfoFF(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
170
171
172/*******************************************************************************
173* Global Variables *
174*******************************************************************************/
175/** Array of switcher defininitions.
176 * The type and index shall match!
177 */
178static PVMMSWITCHERDEF s_apSwitchers[VMMSWITCHER_MAX] =
179{
180 NULL, /* invalid entry */
181#ifndef RT_ARCH_AMD64
182 &vmmR3Switcher32BitTo32Bit_Def,
183 &vmmR3Switcher32BitToPAE_Def,
184 NULL, //&vmmR3Switcher32BitToAMD64_Def,
185 &vmmR3SwitcherPAETo32Bit_Def,
186 &vmmR3SwitcherPAEToPAE_Def,
187 NULL, //&vmmR3SwitcherPAEToAMD64_Def,
188# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
189 &vmmR3SwitcherAMD64ToPAE_Def,
190# else
191 NULL, //&vmmR3SwitcherAMD64ToPAE_Def,
192# endif
193 NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
194#else
195 NULL, //&vmmR3Switcher32BitTo32Bit_Def,
196 NULL, //&vmmR3Switcher32BitToPAE_Def,
197 NULL, //&vmmR3Switcher32BitToAMD64_Def,
198 NULL, //&vmmR3SwitcherPAETo32Bit_Def,
199 NULL, //&vmmR3SwitcherPAEToPAE_Def,
200 NULL, //&vmmR3SwitcherPAEToAMD64_Def,
201 &vmmR3SwitcherAMD64ToPAE_Def,
202 NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
203#endif
204};
205
206
207
208/**
209 * Initiates the core code.
210 *
211 * This is core per VM code which might need fixups and/or for ease of use
212 * are put on linear contiguous backing.
213 *
214 * @returns VBox status code.
215 * @param pVM Pointer to VM structure.
216 */
217static int vmmR3InitCoreCode(PVM pVM)
218{
219 /*
220 * Calc the size.
221 */
222 unsigned cbCoreCode = 0;
223 for (unsigned iSwitcher = 0; iSwitcher < ELEMENTS(s_apSwitchers); iSwitcher++)
224 {
225 pVM->vmm.s.aoffSwitchers[iSwitcher] = cbCoreCode;
226 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
227 if (pSwitcher)
228 {
229 AssertRelease((unsigned)pSwitcher->enmType == iSwitcher);
230 cbCoreCode += RT_ALIGN_32(pSwitcher->cbCode + 1, 32);
231 }
232 }
233
234 /*
235 * Allocate continguous pages for switchers and deal with
236 * conflicts in the intermediate mapping of the code.
237 */
238 pVM->vmm.s.cbCoreCode = RT_ALIGN_32(cbCoreCode, PAGE_SIZE);
239 pVM->vmm.s.pvHCCoreCodeR3 = SUPContAlloc2(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvHCCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
240 int rc = VERR_NO_MEMORY;
241 if (pVM->vmm.s.pvHCCoreCodeR3)
242 {
243 rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvHCCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
244 if (rc == VERR_PGM_MAPPINGS_FIX_CONFLICT)
245 {
246 /* try more allocations. */
247 struct
248 {
249 RTR0PTR pvR0;
250 void *pvR3;
251 RTHCPHYS HCPhys;
252 RTUINT cb;
253 } aBadTries[16];
254 unsigned i = 0;
255 do
256 {
257 aBadTries[i].pvR3 = pVM->vmm.s.pvHCCoreCodeR3;
258 aBadTries[i].pvR0 = pVM->vmm.s.pvHCCoreCodeR0;
259 aBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
260 i++;
261 pVM->vmm.s.pvHCCoreCodeR0 = NIL_RTR0PTR;
262 pVM->vmm.s.HCPhysCoreCode = NIL_RTHCPHYS;
263 pVM->vmm.s.pvHCCoreCodeR3 = SUPContAlloc2(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvHCCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
264 if (!pVM->vmm.s.pvHCCoreCodeR3)
265 break;
266 rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvHCCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
267 } while ( rc == VERR_PGM_MAPPINGS_FIX_CONFLICT
268 && i < ELEMENTS(aBadTries) - 1);
269
270 /* cleanup */
271 if (VBOX_FAILURE(rc))
272 {
273 aBadTries[i].pvR3 = pVM->vmm.s.pvHCCoreCodeR3;
274 aBadTries[i].pvR0 = pVM->vmm.s.pvHCCoreCodeR0;
275 aBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
276 aBadTries[i].cb = pVM->vmm.s.cbCoreCode;
277 i++;
278 LogRel(("Failed to allocated and map core code: rc=%Vrc\n", rc));
279 }
280 while (i-- > 0)
281 {
282 LogRel(("Core code alloc attempt #%d: pvR3=%p pvR0=%p HCPhys=%VHp\n",
283 i, aBadTries[i].pvR3, aBadTries[i].pvR0, aBadTries[i].HCPhys));
284 SUPContFree(aBadTries[i].pvR3, aBadTries[i].cb >> PAGE_SHIFT);
285 }
286 }
287 }
288 if (VBOX_SUCCESS(rc))
289 {
290 /*
291 * copy the code.
292 */
293 for (unsigned iSwitcher = 0; iSwitcher < ELEMENTS(s_apSwitchers); iSwitcher++)
294 {
295 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
296 if (pSwitcher)
297 memcpy((uint8_t *)pVM->vmm.s.pvHCCoreCodeR3 + pVM->vmm.s.aoffSwitchers[iSwitcher],
298 pSwitcher->pvCode, pSwitcher->cbCode);
299 }
300
301 /*
302 * Map the code into the GC address space.
303 */
304 rc = MMR3HyperMapHCPhys(pVM, pVM->vmm.s.pvHCCoreCodeR3, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, "Core Code", &pVM->vmm.s.pvGCCoreCode);
305 if (VBOX_SUCCESS(rc))
306 {
307 MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
308 LogRel(("CoreCode: R3=%VHv R0=%VHv GC=%VGv Phys=%VHp cb=%#x\n",
309 pVM->vmm.s.pvHCCoreCodeR3, pVM->vmm.s.pvHCCoreCodeR0, pVM->vmm.s.pvGCCoreCode, pVM->vmm.s.HCPhysCoreCode, pVM->vmm.s.cbCoreCode));
310
311 /*
312 * Finally, PGM probably have selected a switcher already but we need
313 * to do get the addresses so we'll reselect it.
314 * This may legally fail so, we're ignoring the rc.
315 */
316 VMMR3SelectSwitcher(pVM, pVM->vmm.s.enmSwitcher);
317 return rc;
318 }
319
320 /* shit */
321 AssertMsgFailed(("PGMR3Map(,%VGv, %VGp, %#x, 0) failed with rc=%Vrc\n", pVM->vmm.s.pvGCCoreCode, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, rc));
322 SUPContFree(pVM->vmm.s.pvHCCoreCodeR3, pVM->vmm.s.cbCoreCode >> PAGE_SHIFT);
323 }
324 else
325 VMSetError(pVM, rc, RT_SRC_POS,
326 N_("Failed to allocate %d bytes of contiguous memory for the world switcher code"),
327 cbCoreCode);
328
329 pVM->vmm.s.pvHCCoreCodeR3 = NULL;
330 pVM->vmm.s.pvHCCoreCodeR0 = NIL_RTR0PTR;
331 pVM->vmm.s.pvGCCoreCode = 0;
332 return rc;
333}
334
335
336/**
337 * Initializes the VMM.
338 *
339 * @returns VBox status code.
340 * @param pVM The VM to operate on.
341 */
342VMMR3DECL(int) VMMR3Init(PVM pVM)
343{
344 LogFlow(("VMMR3Init\n"));
345
346 /*
347 * Assert alignment, sizes and order.
348 */
349 AssertMsg(pVM->vmm.s.offVM == 0, ("Already initialized!\n"));
350 AssertMsg(sizeof(pVM->vmm.padding) >= sizeof(pVM->vmm.s),
351 ("pVM->vmm.padding is too small! vmm.padding %d while vmm.s is %d\n",
352 sizeof(pVM->vmm.padding), sizeof(pVM->vmm.s)));
353
354 /*
355 * Init basic VM VMM members.
356 */
357 pVM->vmm.s.offVM = RT_OFFSETOF(VM, vmm);
358 int rc = CFGMR3QueryU32(CFGMR3GetRoot(pVM), "YieldEMTInterval", &pVM->vmm.s.cYieldEveryMillies);
359 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
360 pVM->vmm.s.cYieldEveryMillies = 23; /* Value arrived at after experimenting with the grub boot prompt. */
361 //pVM->vmm.s.cYieldEveryMillies = 8; //debugging
362 else
363 AssertMsgRCReturn(rc, ("Configuration error. Failed to query \"YieldEMTInterval\", rc=%Vrc\n", rc), rc);
364
365 /* GC switchers are enabled by default. Turned off by HWACCM. */
366 pVM->vmm.s.fSwitcherDisabled = false;
367
368 /*
369 * Register the saved state data unit.
370 */
371 rc = SSMR3RegisterInternal(pVM, "vmm", 1, VMM_SAVED_STATE_VERSION, VMM_STACK_SIZE + sizeof(RTGCPTR),
372 NULL, vmmR3Save, NULL,
373 NULL, vmmR3Load, NULL);
374 if (VBOX_FAILURE(rc))
375 return rc;
376
377 /*
378 * Register the Ring-0 VM handle with the session for fast ioctl calls.
379 */
380 rc = SUPSetVMForFastIOCtl(pVM->pVMR0);
381 if (VBOX_FAILURE(rc))
382 return rc;
383
384 /*
385 * Init core code.
386 */
387 rc = vmmR3InitCoreCode(pVM);
388 if (VBOX_SUCCESS(rc))
389 {
390 /*
391 * Allocate & init VMM GC stack.
392 * The stack pages are also used by the VMM R0 when VMMR0CallHost is invoked.
393 * (The page protection is modifed during R3 init completion.)
394 */
395#ifdef VBOX_STRICT_VMM_STACK
396 rc = MMHyperAlloc(pVM, VMM_STACK_SIZE + PAGE_SIZE + PAGE_SIZE, PAGE_SIZE, MM_TAG_VMM, (void **)&pVM->vmm.s.pbHCStack);
397#else
398 rc = MMHyperAlloc(pVM, VMM_STACK_SIZE, PAGE_SIZE, MM_TAG_VMM, (void **)&pVM->vmm.s.pbHCStack);
399#endif
400 if (VBOX_SUCCESS(rc))
401 {
402 /* Set HC and GC stack pointers to top of stack. */
403 pVM->vmm.s.CallHostR0JmpBuf.pvSavedStack = (RTR0PTR)pVM->vmm.s.pbHCStack;
404 pVM->vmm.s.pbGCStack = MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack);
405 pVM->vmm.s.pbGCStackBottom = pVM->vmm.s.pbGCStack + VMM_STACK_SIZE;
406 AssertRelease(pVM->vmm.s.pbGCStack);
407
408 /* Set hypervisor eip. */
409 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStack);
410
411 /*
412 * Allocate GC & R0 Logger instances (they are finalized in the relocator).
413 */
414#ifdef LOG_ENABLED
415 PRTLOGGER pLogger = RTLogDefaultInstance();
416 if (pLogger)
417 {
418 pVM->vmm.s.cbLoggerGC = RT_OFFSETOF(RTLOGGERGC, afGroups[pLogger->cGroups]);
419 rc = MMHyperAlloc(pVM, pVM->vmm.s.cbLoggerGC, 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pLoggerHC);
420 if (VBOX_SUCCESS(rc))
421 {
422 pVM->vmm.s.pLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pLoggerHC);
423
424/*
425 * Ring-0 logging isn't 100% safe yet (thread id reuse / process exit cleanup), so
426 * you have to sign up here by adding your defined(DEBUG_<userid>) to the #if.
427 *
428 * If you want to log in non-debug modes, you'll have to remember to change SUPDRvShared.c
429 * to not stub all the log functions.
430 *
431 * You might also wish to enable the AssertMsg1/2 overrides in VMMR0.cpp when enabling this.
432 */
433# if defined(DEBUG_sandervl) || defined(DEBUG_frank)
434 rc = MMHyperAlloc(pVM, RT_OFFSETOF(VMMR0LOGGER, Logger.afGroups[pLogger->cGroups]),
435 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pR0Logger);
436 if (VBOX_SUCCESS(rc))
437 {
438 pVM->vmm.s.pR0Logger->pVM = pVM;
439 //pVM->vmm.s.pR0Logger->fCreated = false;
440 pVM->vmm.s.pR0Logger->cbLogger = RT_OFFSETOF(RTLOGGER, afGroups[pLogger->cGroups]);
441 }
442# endif
443 }
444 }
445#endif /* LOG_ENABLED */
446
447#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
448 /*
449 * Allocate GC Release Logger instances (finalized in the relocator).
450 */
451 if (VBOX_SUCCESS(rc))
452 {
453 PRTLOGGER pRelLogger = RTLogRelDefaultInstance();
454 if (pRelLogger)
455 {
456 pVM->vmm.s.cbRelLoggerGC = RT_OFFSETOF(RTLOGGERGC, afGroups[pRelLogger->cGroups]);
457 rc = MMHyperAlloc(pVM, pVM->vmm.s.cbRelLoggerGC, 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pRelLoggerHC);
458 if (VBOX_SUCCESS(rc))
459 pVM->vmm.s.pRelLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pRelLoggerHC);
460 }
461 }
462#endif /* VBOX_WITH_GC_AND_R0_RELEASE_LOG */
463
464#ifdef VBOX_WITH_NMI
465 /*
466 * Allocate mapping for the host APIC.
467 */
468 if (VBOX_SUCCESS(rc))
469 {
470 rc = MMR3HyperReserve(pVM, PAGE_SIZE, "Host APIC", &pVM->vmm.s.GCPtrApicBase);
471 AssertRC(rc);
472 }
473#endif
474 if (VBOX_SUCCESS(rc))
475 {
476 rc = RTCritSectInit(&pVM->vmm.s.CritSectVMLock);
477 if (VBOX_SUCCESS(rc))
478 {
479 /*
480 * Debug info.
481 */
482 DBGFR3InfoRegisterInternal(pVM, "ff", "Displays the current Forced actions Flags.", vmmR3InfoFF);
483
484 /*
485 * Statistics.
486 */
487 STAM_REG(pVM, &pVM->vmm.s.StatRunGC, STAMTYPE_COUNTER, "/VMM/RunGC", STAMUNIT_OCCURENCES, "Number of context switches.");
488 STAM_REG(pVM, &pVM->vmm.s.StatGCRetNormal, STAMTYPE_COUNTER, "/VMM/GCRet/Normal", STAMUNIT_OCCURENCES, "Number of VINF_SUCCESS returns.");
489 STAM_REG(pVM, &pVM->vmm.s.StatGCRetInterrupt, STAMTYPE_COUNTER, "/VMM/GCRet/Interrupt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT returns.");
490 STAM_REG(pVM, &pVM->vmm.s.StatGCRetInterruptHyper, STAMTYPE_COUNTER, "/VMM/GCRet/InterruptHyper", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT_HYPER returns.");
491 STAM_REG(pVM, &pVM->vmm.s.StatGCRetGuestTrap, STAMTYPE_COUNTER, "/VMM/GCRet/GuestTrap", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_GUEST_TRAP returns.");
492 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRingSwitch, STAMTYPE_COUNTER, "/VMM/GCRet/RingSwitch", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_RING_SWITCH returns.");
493 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRingSwitchInt, STAMTYPE_COUNTER, "/VMM/GCRet/RingSwitchInt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_RING_SWITCH_INT returns.");
494 STAM_REG(pVM, &pVM->vmm.s.StatGCRetExceptionPrivilege, STAMTYPE_COUNTER, "/VMM/GCRet/ExceptionPrivilege", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_EXCEPTION_PRIVILEGED returns.");
495 STAM_REG(pVM, &pVM->vmm.s.StatGCRetStaleSelector, STAMTYPE_COUNTER, "/VMM/GCRet/StaleSelector", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_STALE_SELECTOR returns.");
496 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIRETTrap, STAMTYPE_COUNTER, "/VMM/GCRet/IRETTrap", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_IRET_TRAP returns.");
497 STAM_REG(pVM, &pVM->vmm.s.StatGCRetEmulate, STAMTYPE_COUNTER, "/VMM/GCRet/Emulate", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION returns.");
498 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchEmulate, STAMTYPE_COUNTER, "/VMM/GCRet/PatchEmulate", STAMUNIT_OCCURENCES, "Number of VINF_PATCH_EMULATE_INSTR returns.");
499 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIORead, STAMTYPE_COUNTER, "/VMM/GCRet/IORead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_IOPORT_READ returns.");
500 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIOWrite, STAMTYPE_COUNTER, "/VMM/GCRet/IOWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_IOPORT_WRITE returns.");
501 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIORead, STAMTYPE_COUNTER, "/VMM/GCRet/MMIORead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_READ returns.");
502 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOWrite, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_WRITE returns.");
503 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOReadWrite, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOReadWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_READ_WRITE returns.");
504 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOPatchRead, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOPatchRead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_PATCH_READ returns.");
505 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOPatchWrite, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOPatchWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_PATCH_WRITE returns.");
506 STAM_REG(pVM, &pVM->vmm.s.StatGCRetLDTFault, STAMTYPE_COUNTER, "/VMM/GCRet/LDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_GDT_FAULT returns.");
507 STAM_REG(pVM, &pVM->vmm.s.StatGCRetGDTFault, STAMTYPE_COUNTER, "/VMM/GCRet/GDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_LDT_FAULT returns.");
508 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIDTFault, STAMTYPE_COUNTER, "/VMM/GCRet/IDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_IDT_FAULT returns.");
509 STAM_REG(pVM, &pVM->vmm.s.StatGCRetTSSFault, STAMTYPE_COUNTER, "/VMM/GCRet/TSSFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_TSS_FAULT returns.");
510 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPDFault, STAMTYPE_COUNTER, "/VMM/GCRet/PDFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_PD_FAULT returns.");
511 STAM_REG(pVM, &pVM->vmm.s.StatGCRetCSAMTask, STAMTYPE_COUNTER, "/VMM/GCRet/CSAMTask", STAMUNIT_OCCURENCES, "Number of VINF_CSAM_PENDING_ACTION returns.");
512 STAM_REG(pVM, &pVM->vmm.s.StatGCRetSyncCR3, STAMTYPE_COUNTER, "/VMM/GCRet/SyncCR", STAMUNIT_OCCURENCES, "Number of VINF_PGM_SYNC_CR3 returns.");
513 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMisc, STAMTYPE_COUNTER, "/VMM/GCRet/Misc", STAMUNIT_OCCURENCES, "Number of misc returns.");
514 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchInt3, STAMTYPE_COUNTER, "/VMM/GCRet/PatchInt3", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_INT3 returns.");
515 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchPF, STAMTYPE_COUNTER, "/VMM/GCRet/PatchPF", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_TRAP_PF returns.");
516 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchGP, STAMTYPE_COUNTER, "/VMM/GCRet/PatchGP", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_TRAP_GP returns.");
517 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchIretIRQ, STAMTYPE_COUNTER, "/VMM/GCRet/PatchIret", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PENDING_IRQ_AFTER_IRET returns.");
518 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPageOverflow, STAMTYPE_COUNTER, "/VMM/GCRet/InvlpgOverflow", STAMUNIT_OCCURENCES, "Number of VERR_REM_FLUSHED_PAGES_OVERFLOW returns.");
519 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRescheduleREM, STAMTYPE_COUNTER, "/VMM/GCRet/ScheduleREM", STAMUNIT_OCCURENCES, "Number of VINF_EM_RESCHEDULE_REM returns.");
520 STAM_REG(pVM, &pVM->vmm.s.StatGCRetToR3, STAMTYPE_COUNTER, "/VMM/GCRet/ToR3", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TO_R3 returns.");
521 STAM_REG(pVM, &pVM->vmm.s.StatGCRetTimerPending, STAMTYPE_COUNTER, "/VMM/GCRet/TimerPending", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TIMER_PENDING returns.");
522 STAM_REG(pVM, &pVM->vmm.s.StatGCRetInterruptPending, STAMTYPE_COUNTER, "/VMM/GCRet/InterruptPending", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT_PENDING returns.");
523 STAM_REG(pVM, &pVM->vmm.s.StatGCRetCallHost, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/Misc", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
524 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMGrowRAM, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/GrowRAM", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
525 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPDMLock, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/PDMLock", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
526 STAM_REG(pVM, &pVM->vmm.s.StatGCRetLogFlush, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/LogFlush", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
527 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPDMQueueFlush, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/QueueFlush", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
528 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMPoolGrow, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/PGMPoolGrow",STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
529 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRemReplay, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/REMReplay", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
530 STAM_REG(pVM, &pVM->vmm.s.StatGCRetVMSetError, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/VMSetError", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
531 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMLock, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/PGMLock", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
532 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPATMDuplicateFn, STAMTYPE_COUNTER, "/VMM/GCRet/PATMDuplicateFn", STAMUNIT_OCCURENCES, "Number of VINF_PATM_DUPLICATE_FUNCTION returns.");
533 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMChangeMode, STAMTYPE_COUNTER, "/VMM/GCRet/PGMChangeMode", STAMUNIT_OCCURENCES, "Number of VINF_PGM_CHANGE_MODE returns.");
534 STAM_REG(pVM, &pVM->vmm.s.StatGCRetEmulHlt, STAMTYPE_COUNTER, "/VMM/GCRet/EmulHlt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_EMULATE_INSTR_HLT returns.");
535 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPendingRequest, STAMTYPE_COUNTER, "/VMM/GCRet/PendingRequest", STAMUNIT_OCCURENCES, "Number of VINF_EM_PENDING_REQUEST returns.");
536
537 return VINF_SUCCESS;
538 }
539 AssertRC(rc);
540 }
541 }
542 /** @todo: Need failure cleanup. */
543
544 //more todo in here?
545 //if (VBOX_SUCCESS(rc))
546 //{
547 //}
548 //int rc2 = vmmR3TermCoreCode(pVM);
549 //AssertRC(rc2));
550 }
551
552 return rc;
553}
554
555
556/**
557 * Ring-3 init finalizing.
558 *
559 * @returns VBox status code.
560 * @param pVM The VM handle.
561 */
562VMMR3DECL(int) VMMR3InitFinalize(PVM pVM)
563{
564#ifdef VBOX_STRICT_VMM_STACK
565 /*
566 * Two inaccessible pages at each sides of the stack to catch over/under-flows.
567 */
568 memset(pVM->vmm.s.pbHCStack - PAGE_SIZE, 0xcc, PAGE_SIZE);
569 PGMMapSetPage(pVM, MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack - PAGE_SIZE), PAGE_SIZE, 0);
570 RTMemProtect(pVM->vmm.s.pbHCStack - PAGE_SIZE, PAGE_SIZE, RTMEM_PROT_NONE);
571
572 memset(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE, 0xcc, PAGE_SIZE);
573 PGMMapSetPage(pVM, MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack + VMM_STACK_SIZE), PAGE_SIZE, 0);
574 RTMemProtect(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE, PAGE_SIZE, RTMEM_PROT_NONE);
575#endif
576
577 /*
578 * Set page attributes to r/w for stack pages.
579 */
580 int rc = PGMMapSetPage(pVM, pVM->vmm.s.pbGCStack, VMM_STACK_SIZE, X86_PTE_P | X86_PTE_A | X86_PTE_D | X86_PTE_RW);
581 AssertRC(rc);
582 if (VBOX_SUCCESS(rc))
583 {
584 /*
585 * Create the EMT yield timer.
586 */
587 rc = TMR3TimerCreateInternal(pVM, TMCLOCK_REAL, vmmR3YieldEMT, NULL, "EMT Yielder", &pVM->vmm.s.pYieldTimer);
588 if (VBOX_SUCCESS(rc))
589 rc = TMTimerSetMillies(pVM->vmm.s.pYieldTimer, pVM->vmm.s.cYieldEveryMillies);
590 }
591#ifdef VBOX_WITH_NMI
592 /*
593 * Map the host APIC into GC - This may be host os specific!
594 */
595 if (VBOX_SUCCESS(rc))
596 rc = PGMMap(pVM, pVM->vmm.s.GCPtrApicBase, 0xfee00000, PAGE_SIZE,
597 X86_PTE_P | X86_PTE_RW | X86_PTE_PWT | X86_PTE_PCD | X86_PTE_A | X86_PTE_D);
598#endif
599 return rc;
600}
601
602
603/**
604 * Initializes the R0 VMM.
605 *
606 * @returns VBox status code.
607 * @param pVM The VM to operate on.
608 */
609VMMR3DECL(int) VMMR3InitR0(PVM pVM)
610{
611 int rc;
612
613 /*
614 * Initialize the ring-0 logger if we haven't done so yet.
615 */
616 if ( pVM->vmm.s.pR0Logger
617 && !pVM->vmm.s.pR0Logger->fCreated)
618 {
619 rc = VMMR3UpdateLoggers(pVM);
620 if (VBOX_FAILURE(rc))
621 return rc;
622 }
623
624 /*
625 * Call Ring-0 entry with init code.
626 */
627 for (;;)
628 {
629#ifdef NO_SUPCALLR0VMM
630 //rc = VERR_GENERAL_FAILURE;
631 rc = VINF_SUCCESS;
632#else
633 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_VMMR0_INIT, VBOX_VERSION, NULL);
634#endif
635 if ( pVM->vmm.s.pR0Logger
636 && pVM->vmm.s.pR0Logger->Logger.offScratch > 0)
637 RTLogFlushToLogger(&pVM->vmm.s.pR0Logger->Logger, NULL);
638 if (rc != VINF_VMM_CALL_HOST)
639 break;
640 rc = vmmR3ServiceCallHostRequest(pVM);
641 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
642 break;
643 /* Resume R0 */
644 }
645
646 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
647 {
648 LogRel(("R0 init failed, rc=%Vra\n", rc));
649 if (VBOX_SUCCESS(rc))
650 rc = VERR_INTERNAL_ERROR;
651 }
652 return rc;
653}
654
655
656/**
657 * Initializes the GC VMM.
658 *
659 * @returns VBox status code.
660 * @param pVM The VM to operate on.
661 */
662VMMR3DECL(int) VMMR3InitGC(PVM pVM)
663{
664 /* In VMX mode, there's no need to init GC. */
665 if (pVM->vmm.s.fSwitcherDisabled)
666 return VINF_SUCCESS;
667
668 /*
669 * Call VMMGCInit():
670 * -# resolve the address.
671 * -# setup stackframe and EIP to use the trampoline.
672 * -# do a generic hypervisor call.
673 */
674 RTGCPTR GCPtrEP;
675 int rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &GCPtrEP);
676 if (VBOX_SUCCESS(rc))
677 {
678 CPUMHyperSetCtxCore(pVM, NULL);
679 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom); /* Clear the stack. */
680 uint64_t u64TS = RTTimeProgramStartNanoTS();
681#if GC_ARCH_BITS == 32
682 CPUMPushHyper(pVM, (uint32_t)(u64TS >> 32)); /* Param 3: The program startup TS - Hi. */
683 CPUMPushHyper(pVM, (uint32_t)u64TS); /* Param 3: The program startup TS - Lo. */
684#else /* 64-bit GC */
685 CPUMPushHyper(pVM, u64TS); /* Param 3: The program startup TS. */
686#endif
687 CPUMPushHyper(pVM, VBOX_VERSION); /* Param 2: Version argument. */
688 CPUMPushHyper(pVM, VMMGC_DO_VMMGC_INIT); /* Param 1: Operation. */
689 CPUMPushHyper(pVM, pVM->pVMGC); /* Param 0: pVM */
690 CPUMPushHyper(pVM, 3 * sizeof(RTGCPTR)); /* trampoline param: stacksize. */
691 CPUMPushHyper(pVM, GCPtrEP); /* Call EIP. */
692 CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnGCCallTrampoline);
693
694 for (;;)
695 {
696#ifdef NO_SUPCALLR0VMM
697 //rc = VERR_GENERAL_FAILURE;
698 rc = VINF_SUCCESS;
699#else
700 rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_CALL_HYPERVISOR, NULL);
701#endif
702#ifdef LOG_ENABLED
703 PRTLOGGERGC pLogger = pVM->vmm.s.pLoggerHC;
704 if ( pLogger
705 && pLogger->offScratch > 0)
706 RTLogFlushGC(NULL, pLogger);
707#endif
708#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
709 PRTLOGGERGC pRelLogger = pVM->vmm.s.pRelLoggerHC;
710 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
711 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
712#endif
713 if (rc != VINF_VMM_CALL_HOST)
714 break;
715 rc = vmmR3ServiceCallHostRequest(pVM);
716 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
717 break;
718 }
719
720 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
721 {
722 VMMR3FatalDump(pVM, rc);
723 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
724 rc = VERR_INTERNAL_ERROR;
725 }
726 AssertRC(rc);
727 }
728 return rc;
729}
730
731
732/**
733 * Terminate the VMM bits.
734 *
735 * @returns VINF_SUCCESS.
736 * @param pVM The VM handle.
737 */
738VMMR3DECL(int) VMMR3Term(PVM pVM)
739{
740 /*
741 * Call Ring-0 entry with termination code.
742 */
743 int rc;
744 for (;;)
745 {
746#ifdef NO_SUPCALLR0VMM
747 //rc = VERR_GENERAL_FAILURE;
748 rc = VINF_SUCCESS;
749#else
750 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_VMMR0_TERM, VBOX_VERSION, NULL);
751#endif
752 if ( pVM->vmm.s.pR0Logger
753 && pVM->vmm.s.pR0Logger->Logger.offScratch > 0)
754 RTLogFlushToLogger(&pVM->vmm.s.pR0Logger->Logger, NULL);
755 if (rc != VINF_VMM_CALL_HOST)
756 break;
757 rc = vmmR3ServiceCallHostRequest(pVM);
758 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
759 break;
760 /* Resume R0 */
761 }
762 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
763 {
764 LogRel(("VMMR3Term: R0 term failed, rc=%Vra. (warning)\n", rc));
765 if (VBOX_SUCCESS(rc))
766 rc = VERR_INTERNAL_ERROR;
767 }
768
769#ifdef VBOX_STRICT_VMM_STACK
770 /*
771 * Make the two stack guard pages present again.
772 */
773 RTMemProtect(pVM->vmm.s.pbHCStack - PAGE_SIZE, PAGE_SIZE, RTMEM_PROT_READ | RTMEM_PROT_WRITE);
774 RTMemProtect(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE, PAGE_SIZE, RTMEM_PROT_READ | RTMEM_PROT_WRITE);
775#endif
776 return rc;
777}
778
779
780/**
781 * Applies relocations to data and code managed by this
782 * component. This function will be called at init and
783 * whenever the VMM need to relocate it self inside the GC.
784 *
785 * The VMM will need to apply relocations to the core code.
786 *
787 * @param pVM The VM handle.
788 * @param offDelta The relocation delta.
789 */
790VMMR3DECL(void) VMMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
791{
792 LogFlow(("VMMR3Relocate: offDelta=%VGv\n", offDelta));
793
794 /*
795 * Recalc the GC address.
796 */
797 pVM->vmm.s.pvGCCoreCode = MMHyperHC2GC(pVM, pVM->vmm.s.pvHCCoreCodeR3);
798
799 /*
800 * The stack.
801 */
802 CPUMSetHyperESP(pVM, CPUMGetHyperESP(pVM) + offDelta);
803 pVM->vmm.s.pbGCStack = MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack);
804 pVM->vmm.s.pbGCStackBottom = pVM->vmm.s.pbGCStack + VMM_STACK_SIZE;
805
806 /*
807 * All the switchers.
808 */
809 for (unsigned iSwitcher = 0; iSwitcher < ELEMENTS(s_apSwitchers); iSwitcher++)
810 {
811 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
812 if (pSwitcher && pSwitcher->pfnRelocate)
813 {
814 unsigned off = pVM->vmm.s.aoffSwitchers[iSwitcher];
815 pSwitcher->pfnRelocate(pVM,
816 pSwitcher,
817 (uint8_t *)pVM->vmm.s.pvHCCoreCodeR0 + off,
818 (uint8_t *)pVM->vmm.s.pvHCCoreCodeR3 + off,
819 pVM->vmm.s.pvGCCoreCode + off,
820 pVM->vmm.s.HCPhysCoreCode + off);
821 }
822 }
823
824 /*
825 * Recalc the GC address for the current switcher.
826 */
827 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[pVM->vmm.s.enmSwitcher];
828 RTGCPTR GCPtr = pVM->vmm.s.pvGCCoreCode + pVM->vmm.s.aoffSwitchers[pVM->vmm.s.enmSwitcher];
829 pVM->vmm.s.pfnGCGuestToHost = GCPtr + pSwitcher->offGCGuestToHost;
830 pVM->vmm.s.pfnGCCallTrampoline = GCPtr + pSwitcher->offGCCallTrampoline;
831 pVM->pfnVMMGCGuestToHostAsm = GCPtr + pSwitcher->offGCGuestToHostAsm;
832 pVM->pfnVMMGCGuestToHostAsmHyperCtx = GCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
833 pVM->pfnVMMGCGuestToHostAsmGuestCtx = GCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
834
835 /*
836 * Get other GC entry points.
837 */
838 int rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "CPUMGCResumeGuest", &pVM->vmm.s.pfnCPUMGCResumeGuest);
839 AssertReleaseMsgRC(rc, ("CPUMGCResumeGuest not found! rc=%Vra\n", rc));
840
841 rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "CPUMGCResumeGuestV86", &pVM->vmm.s.pfnCPUMGCResumeGuestV86);
842 AssertReleaseMsgRC(rc, ("CPUMGCResumeGuestV86 not found! rc=%Vra\n", rc));
843
844 /*
845 * Update the logger.
846 */
847 VMMR3UpdateLoggers(pVM);
848}
849
850
851/**
852 * Updates the settings for the GC and R0 loggers.
853 *
854 * @returns VBox status code.
855 * @param pVM The VM handle.
856 */
857VMMR3DECL(int) VMMR3UpdateLoggers(PVM pVM)
858{
859 /*
860 * Simply clone the logger instance (for GC).
861 */
862 int rc = VINF_SUCCESS;
863 RTGCPTR GCPtrLoggerFlush = 0;
864
865 if (pVM->vmm.s.pLoggerHC
866#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
867 || pVM->vmm.s.pRelLoggerHC
868#endif
869 )
870 {
871 rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCLoggerFlush", &GCPtrLoggerFlush);
872 AssertReleaseMsgRC(rc, ("vmmGCLoggerFlush not found! rc=%Vra\n", rc));
873 }
874
875 if (pVM->vmm.s.pLoggerHC)
876 {
877 RTGCPTR GCPtrLoggerWrapper = 0;
878 rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCLoggerWrapper", &GCPtrLoggerWrapper);
879 AssertReleaseMsgRC(rc, ("vmmGCLoggerWrapper not found! rc=%Vra\n", rc));
880 pVM->vmm.s.pLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pLoggerHC);
881 rc = RTLogCloneGC(NULL /* default */, pVM->vmm.s.pLoggerHC, pVM->vmm.s.cbLoggerGC,
882 GCPtrLoggerWrapper, GCPtrLoggerFlush, RTLOGFLAGS_BUFFERED);
883 AssertReleaseMsgRC(rc, ("RTLogCloneGC failed! rc=%Vra\n", rc));
884 }
885
886#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
887 if (pVM->vmm.s.pRelLoggerHC)
888 {
889 RTGCPTR GCPtrLoggerWrapper = 0;
890 rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCRelLoggerWrapper", &GCPtrLoggerWrapper);
891 AssertReleaseMsgRC(rc, ("vmmGCRelLoggerWrapper not found! rc=%Vra\n", rc));
892 pVM->vmm.s.pRelLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pRelLoggerHC);
893 rc = RTLogCloneGC(RTLogRelDefaultInstance(), pVM->vmm.s.pRelLoggerHC, pVM->vmm.s.cbRelLoggerGC,
894 GCPtrLoggerWrapper, GCPtrLoggerFlush, RTLOGFLAGS_BUFFERED);
895 AssertReleaseMsgRC(rc, ("RTLogCloneGC failed! rc=%Vra\n", rc));
896 }
897#endif /* VBOX_WITH_GC_AND_R0_RELEASE_LOG */
898
899 /*
900 * For the ring-0 EMT logger, we use a per-thread logger
901 * instance in ring-0. Only initialize it once.
902 */
903 PVMMR0LOGGER pR0Logger = pVM->vmm.s.pR0Logger;
904 if (pR0Logger)
905 {
906 if (!pR0Logger->fCreated)
907 {
908 RTR0PTR pfnLoggerWrapper = NIL_RTR0PTR;
909 rc = PDMR3GetSymbolR0(pVM, VMMR0_MAIN_MODULE_NAME, "vmmR0LoggerWrapper", &pfnLoggerWrapper);
910 AssertReleaseMsgRCReturn(rc, ("VMMLoggerWrapper not found! rc=%Vra\n", rc), rc);
911
912 RTR0PTR pfnLoggerFlush = NIL_RTR0PTR;
913 rc = PDMR3GetSymbolR0(pVM, VMMR0_MAIN_MODULE_NAME, "vmmR0LoggerFlush", &pfnLoggerFlush);
914 AssertReleaseMsgRCReturn(rc, ("VMMLoggerFlush not found! rc=%Vra\n", rc), rc);
915
916 rc = RTLogCreateForR0(&pR0Logger->Logger, pR0Logger->cbLogger,
917 *(PFNRTLOGGER *)&pfnLoggerWrapper, *(PFNRTLOGFLUSH *)&pfnLoggerFlush,
918 RTLOGFLAGS_BUFFERED, RTLOGDEST_DUMMY);
919 AssertReleaseMsgRCReturn(rc, ("RTLogCloneGC failed! rc=%Vra\n", rc), rc);
920 pR0Logger->fCreated = true;
921 }
922
923 rc = RTLogCopyGroupsAndFlags(&pR0Logger->Logger, NULL /* default */, RTLOGFLAGS_BUFFERED, 0);
924 AssertRC(rc);
925 }
926
927 return rc;
928}
929
930
931/**
932 * Generic switch code relocator.
933 *
934 * @param pVM The VM handle.
935 * @param pSwitcher The switcher definition.
936 * @param pu8CodeR3 Pointer to the core code block for the switcher, ring-3 mapping.
937 * @param pu8CodeR0 Pointer to the core code block for the switcher, ring-0 mapping.
938 * @param GCPtrCode The guest context address corresponding to pu8Code.
939 * @param u32IDCode The identity mapped (ID) address corresponding to pu8Code.
940 * @param SelCS The hypervisor CS selector.
941 * @param SelDS The hypervisor DS selector.
942 * @param SelTSS The hypervisor TSS selector.
943 * @param GCPtrGDT The GC address of the hypervisor GDT.
944 * @param SelCS64 The 64-bit mode hypervisor CS selector.
945 */
946static void vmmR3SwitcherGenericRelocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode,
947 RTSEL SelCS, RTSEL SelDS, RTSEL SelTSS, RTGCPTR GCPtrGDT, RTSEL SelCS64)
948{
949 union
950 {
951 const uint8_t *pu8;
952 const uint16_t *pu16;
953 const uint32_t *pu32;
954 const uint64_t *pu64;
955 const void *pv;
956 uintptr_t u;
957 } u;
958 u.pv = pSwitcher->pvFixups;
959
960 /*
961 * Process fixups.
962 */
963 uint8_t u8;
964 while ((u8 = *u.pu8++) != FIX_THE_END)
965 {
966 /*
967 * Get the source (where to write the fixup).
968 */
969 uint32_t offSrc = *u.pu32++;
970 Assert(offSrc < pSwitcher->cbCode);
971 union
972 {
973 uint8_t *pu8;
974 uint16_t *pu16;
975 uint32_t *pu32;
976 uint64_t *pu64;
977 uintptr_t u;
978 } uSrc;
979 uSrc.pu8 = pu8CodeR3 + offSrc;
980
981 /* The fixup target and method depends on the type. */
982 switch (u8)
983 {
984 /*
985 * 32-bit relative, source in HC and target in GC.
986 */
987 case FIX_HC_2_GC_NEAR_REL:
988 {
989 Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
990 uint32_t offTrg = *u.pu32++;
991 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
992 *uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (uSrc.u + 4));
993 break;
994 }
995
996 /*
997 * 32-bit relative, source in HC and target in ID.
998 */
999 case FIX_HC_2_ID_NEAR_REL:
1000 {
1001 Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1002 uint32_t offTrg = *u.pu32++;
1003 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1004 *uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (uSrc.u + 4));
1005 break;
1006 }
1007
1008 /*
1009 * 32-bit relative, source in GC and target in HC.
1010 */
1011 case FIX_GC_2_HC_NEAR_REL:
1012 {
1013 Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1014 uint32_t offTrg = *u.pu32++;
1015 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1016 *uSrc.pu32 = (uint32_t)(((uintptr_t)pu8CodeR0 + offTrg) - (GCPtrCode + offSrc + 4));
1017 break;
1018 }
1019
1020 /*
1021 * 32-bit relative, source in GC and target in ID.
1022 */
1023 case FIX_GC_2_ID_NEAR_REL:
1024 {
1025 Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1026 uint32_t offTrg = *u.pu32++;
1027 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1028 *uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (GCPtrCode + offSrc + 4));
1029 break;
1030 }
1031
1032 /*
1033 * 32-bit relative, source in ID and target in HC.
1034 */
1035 case FIX_ID_2_HC_NEAR_REL:
1036 {
1037 Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1038 uint32_t offTrg = *u.pu32++;
1039 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1040 *uSrc.pu32 = (uint32_t)(((uintptr_t)pu8CodeR0 + offTrg) - (u32IDCode + offSrc + 4));
1041 break;
1042 }
1043
1044 /*
1045 * 32-bit relative, source in ID and target in HC.
1046 */
1047 case FIX_ID_2_GC_NEAR_REL:
1048 {
1049 Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1050 uint32_t offTrg = *u.pu32++;
1051 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1052 *uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (u32IDCode + offSrc + 4));
1053 break;
1054 }
1055
1056 /*
1057 * 16:32 far jump, target in GC.
1058 */
1059 case FIX_GC_FAR32:
1060 {
1061 uint32_t offTrg = *u.pu32++;
1062 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1063 *uSrc.pu32++ = (uint32_t)(GCPtrCode + offTrg);
1064 *uSrc.pu16++ = SelCS;
1065 break;
1066 }
1067
1068 /*
1069 * Make 32-bit GC pointer given CPUM offset.
1070 */
1071 case FIX_GC_CPUM_OFF:
1072 {
1073 uint32_t offCPUM = *u.pu32++;
1074 Assert(offCPUM < sizeof(pVM->cpum));
1075 *uSrc.pu32 = (uint32_t)(VM_GUEST_ADDR(pVM, &pVM->cpum) + offCPUM);
1076 break;
1077 }
1078
1079 /*
1080 * Make 32-bit GC pointer given VM offset.
1081 */
1082 case FIX_GC_VM_OFF:
1083 {
1084 uint32_t offVM = *u.pu32++;
1085 Assert(offVM < sizeof(VM));
1086 *uSrc.pu32 = (uint32_t)(VM_GUEST_ADDR(pVM, pVM) + offVM);
1087 break;
1088 }
1089
1090 /*
1091 * Make 32-bit HC pointer given CPUM offset.
1092 */
1093 case FIX_HC_CPUM_OFF:
1094 {
1095 uint32_t offCPUM = *u.pu32++;
1096 Assert(offCPUM < sizeof(pVM->cpum));
1097 *uSrc.pu32 = (uint32_t)pVM->pVMR0 + RT_OFFSETOF(VM, cpum) + offCPUM;
1098 break;
1099 }
1100
1101 /*
1102 * Make 32-bit R0 pointer given VM offset.
1103 */
1104 case FIX_HC_VM_OFF:
1105 {
1106 uint32_t offVM = *u.pu32++;
1107 Assert(offVM < sizeof(VM));
1108 *uSrc.pu32 = (uint32_t)pVM->pVMR0 + offVM;
1109 break;
1110 }
1111
1112 /*
1113 * Store the 32-Bit CR3 (32-bit) for the intermediate memory context.
1114 */
1115 case FIX_INTER_32BIT_CR3:
1116 {
1117
1118 *uSrc.pu32 = PGMGetInter32BitCR3(pVM);
1119 break;
1120 }
1121
1122 /*
1123 * Store the PAE CR3 (32-bit) for the intermediate memory context.
1124 */
1125 case FIX_INTER_PAE_CR3:
1126 {
1127
1128 *uSrc.pu32 = PGMGetInterPaeCR3(pVM);
1129 break;
1130 }
1131
1132 /*
1133 * Store the AMD64 CR3 (32-bit) for the intermediate memory context.
1134 */
1135 case FIX_INTER_AMD64_CR3:
1136 {
1137
1138 *uSrc.pu32 = PGMGetInterAmd64CR3(pVM);
1139 break;
1140 }
1141
1142 /*
1143 * Store the 32-Bit CR3 (32-bit) for the hypervisor (shadow) memory context.
1144 */
1145 case FIX_HYPER_32BIT_CR3:
1146 {
1147
1148 *uSrc.pu32 = PGMGetHyper32BitCR3(pVM);
1149 break;
1150 }
1151
1152 /*
1153 * Store the PAE CR3 (32-bit) for the hypervisor (shadow) memory context.
1154 */
1155 case FIX_HYPER_PAE_CR3:
1156 {
1157
1158 *uSrc.pu32 = PGMGetHyperPaeCR3(pVM);
1159 break;
1160 }
1161
1162 /*
1163 * Store the AMD64 CR3 (32-bit) for the hypervisor (shadow) memory context.
1164 */
1165 case FIX_HYPER_AMD64_CR3:
1166 {
1167
1168 *uSrc.pu32 = PGMGetHyperAmd64CR3(pVM);
1169 break;
1170 }
1171
1172 /*
1173 * Store Hypervisor CS (16-bit).
1174 */
1175 case FIX_HYPER_CS:
1176 {
1177 *uSrc.pu16 = SelCS;
1178 break;
1179 }
1180
1181 /*
1182 * Store Hypervisor DS (16-bit).
1183 */
1184 case FIX_HYPER_DS:
1185 {
1186 *uSrc.pu16 = SelDS;
1187 break;
1188 }
1189
1190 /*
1191 * Store Hypervisor TSS (16-bit).
1192 */
1193 case FIX_HYPER_TSS:
1194 {
1195 *uSrc.pu16 = SelTSS;
1196 break;
1197 }
1198
1199 /*
1200 * Store the 32-bit GC address of the 2nd dword of the TSS descriptor (in the GDT).
1201 */
1202 case FIX_GC_TSS_GDTE_DW2:
1203 {
1204 RTGCPTR GCPtr = GCPtrGDT + (SelTSS & ~7) + 4;
1205 *uSrc.pu32 = (uint32_t)GCPtr;
1206 break;
1207 }
1208
1209
1210 ///@todo case FIX_CR4_MASK:
1211 ///@todo case FIX_CR4_OSFSXR:
1212
1213 /*
1214 * Insert relative jump to specified target it FXSAVE/FXRSTOR isn't supported by the cpu.
1215 */
1216 case FIX_NO_FXSAVE_JMP:
1217 {
1218 uint32_t offTrg = *u.pu32++;
1219 Assert(offTrg < pSwitcher->cbCode);
1220 if (!CPUMSupportsFXSR(pVM))
1221 {
1222 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
1223 *uSrc.pu32++ = offTrg - (offSrc + 5);
1224 }
1225 else
1226 {
1227 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
1228 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
1229 }
1230 break;
1231 }
1232
1233 /*
1234 * Insert relative jump to specified target it SYSENTER isn't used by the host.
1235 */
1236 case FIX_NO_SYSENTER_JMP:
1237 {
1238 uint32_t offTrg = *u.pu32++;
1239 Assert(offTrg < pSwitcher->cbCode);
1240 if (!CPUMIsHostUsingSysEnter(pVM))
1241 {
1242 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
1243 *uSrc.pu32++ = offTrg - (offSrc + 5);
1244 }
1245 else
1246 {
1247 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
1248 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
1249 }
1250 break;
1251 }
1252
1253 /*
1254 * Insert relative jump to specified target it SYSENTER isn't used by the host.
1255 */
1256 case FIX_NO_SYSCALL_JMP:
1257 {
1258 uint32_t offTrg = *u.pu32++;
1259 Assert(offTrg < pSwitcher->cbCode);
1260 if (!CPUMIsHostUsingSysEnter(pVM))
1261 {
1262 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
1263 *uSrc.pu32++ = offTrg - (offSrc + 5);
1264 }
1265 else
1266 {
1267 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
1268 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
1269 }
1270 break;
1271 }
1272
1273 /*
1274 * 32-bit HC pointer fixup to (HC) target within the code (32-bit offset).
1275 */
1276 case FIX_HC_32BIT:
1277 {
1278 uint32_t offTrg = *u.pu32++;
1279 Assert(offSrc < pSwitcher->cbCode);
1280 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1281 *uSrc.pu32 = (uintptr_t)pu8CodeR0 + offTrg;
1282 break;
1283 }
1284
1285#if defined(RT_ARCH_AMD64) || defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
1286 /*
1287 * 64-bit HC pointer fixup to (HC) target within the code (32-bit offset).
1288 */
1289 case FIX_HC_64BIT:
1290 {
1291 uint32_t offTrg = *u.pu32++;
1292 Assert(offSrc < pSwitcher->cbCode);
1293 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1294 *uSrc.pu64 = (uintptr_t)pu8CodeR0 + offTrg;
1295 break;
1296 }
1297
1298 /*
1299 * 64-bit HC Code Selector (no argument).
1300 */
1301 case FIX_HC_64BIT_CS:
1302 {
1303 Assert(offSrc < pSwitcher->cbCode);
1304#if defined(RT_OS_DARWIN) && defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
1305 *uSrc.pu16 = 0x80; /* KERNEL64_CS from i386/seg.h */
1306#else
1307 AssertFatalMsgFailed(("FIX_HC_64BIT_CS not implemented for this host\n"));
1308#endif
1309 break;
1310 }
1311
1312 /*
1313 * 64-bit HC pointer to the CPUM instance data (no argument).
1314 */
1315 case FIX_HC_64BIT_CPUM:
1316 {
1317 Assert(offSrc < pSwitcher->cbCode);
1318 *uSrc.pu64 = pVM->pVMR0 + RT_OFFSETOF(VM, cpum);
1319 break;
1320 }
1321#endif
1322
1323 /*
1324 * 32-bit ID pointer to (ID) target within the code (32-bit offset).
1325 */
1326 case FIX_ID_32BIT:
1327 {
1328 uint32_t offTrg = *u.pu32++;
1329 Assert(offSrc < pSwitcher->cbCode);
1330 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1331 *uSrc.pu32 = u32IDCode + offTrg;
1332 break;
1333 }
1334
1335 /*
1336 * 64-bit ID pointer to (ID) target within the code (32-bit offset).
1337 */
1338 case FIX_ID_64BIT:
1339 {
1340 uint32_t offTrg = *u.pu32++;
1341 Assert(offSrc < pSwitcher->cbCode);
1342 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1343 *uSrc.pu64 = u32IDCode + offTrg;
1344 break;
1345 }
1346
1347 /*
1348 * Far 16:32 ID pointer to 64-bit mode (ID) target within the code (32-bit offset).
1349 */
1350 case FIX_ID_FAR32_TO_64BIT_MODE:
1351 {
1352 uint32_t offTrg = *u.pu32++;
1353 Assert(offSrc < pSwitcher->cbCode);
1354 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1355 *uSrc.pu32++ = u32IDCode + offTrg;
1356 *uSrc.pu16 = SelCS64;
1357 AssertRelease(SelCS64);
1358 break;
1359 }
1360
1361#ifdef VBOX_WITH_NMI
1362 /*
1363 * 32-bit address to the APIC base.
1364 */
1365 case FIX_GC_APIC_BASE_32BIT:
1366 {
1367 *uSrc.pu32 = pVM->vmm.s.GCPtrApicBase;
1368 break;
1369 }
1370#endif
1371
1372 default:
1373 AssertReleaseMsgFailed(("Unknown fixup %d in switcher %s\n", u8, pSwitcher->pszDesc));
1374 break;
1375 }
1376 }
1377
1378#ifdef LOG_ENABLED
1379 /*
1380 * If Log2 is enabled disassemble the switcher code.
1381 *
1382 * The switcher code have 1-2 HC parts, 1 GC part and 0-2 ID parts.
1383 */
1384 if (LogIs2Enabled())
1385 {
1386 RTLogPrintf("*** Disassembly of switcher %d '%s' %#x bytes ***\n"
1387 " pu8CodeR0 = %p\n"
1388 " pu8CodeR3 = %p\n"
1389 " GCPtrCode = %VGv\n"
1390 " u32IDCode = %08x\n"
1391 " pVMGC = %VGv\n"
1392 " pCPUMGC = %VGv\n"
1393 " pVMHC = %p\n"
1394 " pCPUMHC = %p\n"
1395 " GCPtrGDT = %VGv\n"
1396 " InterCR3s = %08x, %08x, %08x (32-Bit, PAE, AMD64)\n"
1397 " HyperCR3s = %08x, %08x, %08x (32-Bit, PAE, AMD64)\n"
1398 " SelCS = %04x\n"
1399 " SelDS = %04x\n"
1400 " SelCS64 = %04x\n"
1401 " SelTSS = %04x\n",
1402 pSwitcher->enmType, pSwitcher->pszDesc, pSwitcher->cbCode,
1403 pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode, VM_GUEST_ADDR(pVM, pVM),
1404 VM_GUEST_ADDR(pVM, &pVM->cpum), pVM, &pVM->cpum,
1405 GCPtrGDT,
1406 PGMGetHyper32BitCR3(pVM), PGMGetHyperPaeCR3(pVM), PGMGetHyperAmd64CR3(pVM),
1407 PGMGetInter32BitCR3(pVM), PGMGetInterPaeCR3(pVM), PGMGetInterAmd64CR3(pVM),
1408 SelCS, SelDS, SelCS64, SelTSS);
1409
1410 uint32_t offCode = 0;
1411 while (offCode < pSwitcher->cbCode)
1412 {
1413 /*
1414 * Figure out where this is.
1415 */
1416 const char *pszDesc = NULL;
1417 RTUINTPTR uBase;
1418 uint32_t cbCode;
1419 if (offCode - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0)
1420 {
1421 pszDesc = "HCCode0";
1422 uBase = (RTUINTPTR)pu8CodeR0;
1423 offCode = pSwitcher->offHCCode0;
1424 cbCode = pSwitcher->cbHCCode0;
1425 }
1426 else if (offCode - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1)
1427 {
1428 pszDesc = "HCCode1";
1429 uBase = (RTUINTPTR)pu8CodeR0;
1430 offCode = pSwitcher->offHCCode1;
1431 cbCode = pSwitcher->cbHCCode1;
1432 }
1433 else if (offCode - pSwitcher->offGCCode < pSwitcher->cbGCCode)
1434 {
1435 pszDesc = "GCCode";
1436 uBase = GCPtrCode;
1437 offCode = pSwitcher->offGCCode;
1438 cbCode = pSwitcher->cbGCCode;
1439 }
1440 else if (offCode - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0)
1441 {
1442 pszDesc = "IDCode0";
1443 uBase = u32IDCode;
1444 offCode = pSwitcher->offIDCode0;
1445 cbCode = pSwitcher->cbIDCode0;
1446 }
1447 else if (offCode - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1)
1448 {
1449 pszDesc = "IDCode1";
1450 uBase = u32IDCode;
1451 offCode = pSwitcher->offIDCode1;
1452 cbCode = pSwitcher->cbIDCode1;
1453 }
1454 else
1455 {
1456 RTLogPrintf(" %04x: %02x '%c' (nowhere)\n",
1457 offCode, pu8CodeR3[offCode], isprint(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
1458 offCode++;
1459 continue;
1460 }
1461
1462 /*
1463 * Disassemble it.
1464 */
1465 RTLogPrintf(" %s: offCode=%#x cbCode=%#x\n", pszDesc, offCode, cbCode);
1466 DISCPUSTATE Cpu = {0};
1467 Cpu.mode = CPUMODE_32BIT;
1468 while (cbCode > 0)
1469 {
1470 /* try label it */
1471 if (pSwitcher->offR0HostToGuest == offCode)
1472 RTLogPrintf(" *R0HostToGuest:\n");
1473 if (pSwitcher->offGCGuestToHost == offCode)
1474 RTLogPrintf(" *GCGuestToHost:\n");
1475 if (pSwitcher->offGCCallTrampoline == offCode)
1476 RTLogPrintf(" *GCCallTrampoline:\n");
1477 if (pSwitcher->offGCGuestToHostAsm == offCode)
1478 RTLogPrintf(" *GCGuestToHostAsm:\n");
1479 if (pSwitcher->offGCGuestToHostAsmHyperCtx == offCode)
1480 RTLogPrintf(" *GCGuestToHostAsmHyperCtx:\n");
1481 if (pSwitcher->offGCGuestToHostAsmGuestCtx == offCode)
1482 RTLogPrintf(" *GCGuestToHostAsmGuestCtx:\n");
1483
1484 /* disas */
1485 uint32_t cbInstr = 0;
1486 char szDisas[256];
1487 if (RT_SUCCESS(DISInstr(&Cpu, (RTUINTPTR)pu8CodeR3 + offCode, uBase - (RTUINTPTR)pu8CodeR3, &cbInstr, szDisas)))
1488 RTLogPrintf(" %04x: %s", offCode, szDisas); //for whatever reason szDisas includes '\n'.
1489 else
1490 {
1491 RTLogPrintf(" %04x: %02x '%c'\n",
1492 offCode, pu8CodeR3[offCode], isprint(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
1493 cbInstr = 1;
1494 }
1495 offCode += cbInstr;
1496 cbCode -= RT_MIN(cbInstr, cbCode);
1497 }
1498 }
1499 }
1500#endif
1501}
1502
1503
1504/**
1505 * Relocator for the 32-Bit to 32-Bit world switcher.
1506 */
1507DECLCALLBACK(void) vmmR3Switcher32BitTo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1508{
1509 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1510 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1511}
1512
1513
1514/**
1515 * Relocator for the 32-Bit to PAE world switcher.
1516 */
1517DECLCALLBACK(void) vmmR3Switcher32BitToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1518{
1519 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1520 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1521}
1522
1523
1524/**
1525 * Relocator for the PAE to 32-Bit world switcher.
1526 */
1527DECLCALLBACK(void) vmmR3SwitcherPAETo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1528{
1529 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1530 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1531}
1532
1533
1534/**
1535 * Relocator for the PAE to PAE world switcher.
1536 */
1537DECLCALLBACK(void) vmmR3SwitcherPAEToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1538{
1539 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1540 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1541}
1542
1543
1544/**
1545 * Relocator for the AMD64 to PAE world switcher.
1546 */
1547DECLCALLBACK(void) vmmR3SwitcherAMD64ToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1548{
1549 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1550 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
1551}
1552
1553
1554/**
1555 * Gets the pointer to g_szRTAssertMsg1 in GC.
1556 * @returns Pointer to VMMGC::g_szRTAssertMsg1.
1557 * Returns NULL if not present.
1558 * @param pVM The VM handle.
1559 */
1560VMMR3DECL(const char *) VMMR3GetGCAssertMsg1(PVM pVM)
1561{
1562 RTGCPTR GCPtr;
1563 int rc = PDMR3GetSymbolGC(pVM, NULL, "g_szRTAssertMsg1", &GCPtr);
1564 if (VBOX_SUCCESS(rc))
1565 return (const char *)MMHyperGC2HC(pVM, GCPtr);
1566 return NULL;
1567}
1568
1569
1570/**
1571 * Gets the pointer to g_szRTAssertMsg2 in GC.
1572 * @returns Pointer to VMMGC::g_szRTAssertMsg2.
1573 * Returns NULL if not present.
1574 * @param pVM The VM handle.
1575 */
1576VMMR3DECL(const char *) VMMR3GetGCAssertMsg2(PVM pVM)
1577{
1578 RTGCPTR GCPtr;
1579 int rc = PDMR3GetSymbolGC(pVM, NULL, "g_szRTAssertMsg2", &GCPtr);
1580 if (VBOX_SUCCESS(rc))
1581 return (const char *)MMHyperGC2HC(pVM, GCPtr);
1582 return NULL;
1583}
1584
1585
1586/**
1587 * Execute state save operation.
1588 *
1589 * @returns VBox status code.
1590 * @param pVM VM Handle.
1591 * @param pSSM SSM operation handle.
1592 */
1593static DECLCALLBACK(int) vmmR3Save(PVM pVM, PSSMHANDLE pSSM)
1594{
1595 LogFlow(("vmmR3Save:\n"));
1596
1597 /*
1598 * The hypervisor stack.
1599 */
1600 SSMR3PutGCPtr(pSSM, pVM->vmm.s.pbGCStackBottom);
1601 RTGCPTR GCPtrESP = CPUMGetHyperESP(pVM);
1602 Assert(pVM->vmm.s.pbGCStackBottom - GCPtrESP <= VMM_STACK_SIZE);
1603 SSMR3PutGCPtr(pSSM, GCPtrESP);
1604 SSMR3PutMem(pSSM, pVM->vmm.s.pbHCStack, VMM_STACK_SIZE);
1605 return SSMR3PutU32(pSSM, ~0); /* terminator */
1606}
1607
1608
1609/**
1610 * Execute state load operation.
1611 *
1612 * @returns VBox status code.
1613 * @param pVM VM Handle.
1614 * @param pSSM SSM operation handle.
1615 * @param u32Version Data layout version.
1616 */
1617static DECLCALLBACK(int) vmmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
1618{
1619 LogFlow(("vmmR3Load:\n"));
1620
1621 /*
1622 * Validate version.
1623 */
1624 if (u32Version != VMM_SAVED_STATE_VERSION)
1625 {
1626 Log(("vmmR3Load: Invalid version u32Version=%d!\n", u32Version));
1627 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1628 }
1629
1630 /*
1631 * Check that the stack is in the same place, or that it's fearly empty.
1632 */
1633 RTGCPTR GCPtrStackBottom;
1634 SSMR3GetGCPtr(pSSM, &GCPtrStackBottom);
1635 RTGCPTR GCPtrESP;
1636 int rc = SSMR3GetGCPtr(pSSM, &GCPtrESP);
1637 if (VBOX_FAILURE(rc))
1638 return rc;
1639 if ( GCPtrStackBottom == pVM->vmm.s.pbGCStackBottom
1640 || (GCPtrStackBottom - GCPtrESP < 32)) /** @todo This will break if we start preemting the hypervisor. */
1641 {
1642 /*
1643 * We *must* set the ESP because the CPUM load + PGM load relocations will render
1644 * the ESP in CPUM fatally invalid.
1645 */
1646 CPUMSetHyperESP(pVM, GCPtrESP);
1647
1648 /* restore the stack. */
1649 SSMR3GetMem(pSSM, pVM->vmm.s.pbHCStack, VMM_STACK_SIZE);
1650
1651 /* terminator */
1652 uint32_t u32;
1653 rc = SSMR3GetU32(pSSM, &u32);
1654 if (VBOX_FAILURE(rc))
1655 return rc;
1656 if (u32 != ~0U)
1657 {
1658 AssertMsgFailed(("u32=%#x\n", u32));
1659 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1660 }
1661 return VINF_SUCCESS;
1662 }
1663
1664 LogRel(("The stack is not in the same place and it's not empty! GCPtrStackBottom=%VGv pbGCStackBottom=%VGv ESP=%VGv\n",
1665 GCPtrStackBottom, pVM->vmm.s.pbGCStackBottom, GCPtrESP));
1666 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
1667 return VINF_SUCCESS; /* ignore this */
1668 AssertFailed();
1669 return VERR_SSM_LOAD_CONFIG_MISMATCH;
1670}
1671
1672
1673/**
1674 * Selects the switcher to be used for switching to GC.
1675 *
1676 * @returns VBox status code.
1677 * @param pVM VM handle.
1678 * @param enmSwitcher The new switcher.
1679 * @remark This function may be called before the VMM is initialized.
1680 */
1681VMMR3DECL(int) VMMR3SelectSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
1682{
1683 /*
1684 * Validate input.
1685 */
1686 if ( enmSwitcher < VMMSWITCHER_INVALID
1687 || enmSwitcher >= VMMSWITCHER_MAX)
1688 {
1689 AssertMsgFailed(("Invalid input enmSwitcher=%d\n", enmSwitcher));
1690 return VERR_INVALID_PARAMETER;
1691 }
1692
1693 /*
1694 * Select the new switcher.
1695 */
1696 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[enmSwitcher];
1697 if (pSwitcher)
1698 {
1699 Log(("VMMR3SelectSwitcher: enmSwitcher %d -> %d %s\n", pVM->vmm.s.enmSwitcher, enmSwitcher, pSwitcher->pszDesc));
1700 pVM->vmm.s.enmSwitcher = enmSwitcher;
1701
1702 RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvHCCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher]; /** @todo fix the pvHCCoreCodeR0 type */
1703 pVM->vmm.s.pfnR0HostToGuest = pbCodeR0 + pSwitcher->offR0HostToGuest;
1704
1705 RTGCPTR GCPtr = pVM->vmm.s.pvGCCoreCode + pVM->vmm.s.aoffSwitchers[enmSwitcher];
1706 pVM->vmm.s.pfnGCGuestToHost = GCPtr + pSwitcher->offGCGuestToHost;
1707 pVM->vmm.s.pfnGCCallTrampoline = GCPtr + pSwitcher->offGCCallTrampoline;
1708 pVM->pfnVMMGCGuestToHostAsm = GCPtr + pSwitcher->offGCGuestToHostAsm;
1709 pVM->pfnVMMGCGuestToHostAsmHyperCtx = GCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
1710 pVM->pfnVMMGCGuestToHostAsmGuestCtx = GCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
1711 return VINF_SUCCESS;
1712 }
1713 return VERR_NOT_IMPLEMENTED;
1714}
1715
1716/**
1717 * Disable the switcher logic permanently.
1718 *
1719 * @returns VBox status code.
1720 * @param pVM VM handle.
1721 */
1722VMMR3DECL(int) VMMR3DisableSwitcher(PVM pVM)
1723{
1724/** @todo r=bird: I would suggest that we create a dummy switcher which just does something like:
1725 * @code
1726 * mov eax, VERR_INTERNAL_ERROR
1727 * ret
1728 * @endcode
1729 * And then check for fSwitcherDisabled in VMMR3SelectSwitcher() in order to prevent it from being removed.
1730 */
1731 pVM->vmm.s.fSwitcherDisabled = true;
1732 return VINF_SUCCESS;
1733}
1734
1735
1736/**
1737 * Resolve a builtin GC symbol.
1738 * Called by PDM when loading or relocating GC modules.
1739 *
1740 * @returns VBox status
1741 * @param pVM VM Handle.
1742 * @param pszSymbol Symbol to resolv
1743 * @param pGCPtrValue Where to store the symbol value.
1744 * @remark This has to work before VMMR3Relocate() is called.
1745 */
1746VMMR3DECL(int) VMMR3GetImportGC(PVM pVM, const char *pszSymbol, PRTGCPTR pGCPtrValue)
1747{
1748 if (!strcmp(pszSymbol, "g_Logger"))
1749 {
1750 if (pVM->vmm.s.pLoggerHC)
1751 pVM->vmm.s.pLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pLoggerHC);
1752 *pGCPtrValue = pVM->vmm.s.pLoggerGC;
1753 }
1754 else if (!strcmp(pszSymbol, "g_RelLogger"))
1755 {
1756#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
1757 if (pVM->vmm.s.pRelLoggerHC)
1758 pVM->vmm.s.pRelLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pRelLoggerHC);
1759 *pGCPtrValue = pVM->vmm.s.pRelLoggerGC;
1760#else
1761 *pGCPtrValue = NIL_RTGCPTR;
1762#endif
1763 }
1764 else
1765 return VERR_SYMBOL_NOT_FOUND;
1766 return VINF_SUCCESS;
1767}
1768
1769
1770/**
1771 * Suspends the the CPU yielder.
1772 *
1773 * @param pVM The VM handle.
1774 */
1775VMMR3DECL(void) VMMR3YieldSuspend(PVM pVM)
1776{
1777 if (!pVM->vmm.s.cYieldResumeMillies)
1778 {
1779 uint64_t u64Now = TMTimerGet(pVM->vmm.s.pYieldTimer);
1780 uint64_t u64Expire = TMTimerGetExpire(pVM->vmm.s.pYieldTimer);
1781 if (u64Now >= u64Expire || u64Expire == ~(uint64_t)0)
1782 pVM->vmm.s.cYieldResumeMillies = pVM->vmm.s.cYieldEveryMillies;
1783 else
1784 pVM->vmm.s.cYieldResumeMillies = TMTimerToMilli(pVM->vmm.s.pYieldTimer, u64Expire - u64Now);
1785 TMTimerStop(pVM->vmm.s.pYieldTimer);
1786 }
1787 pVM->vmm.s.u64LastYield = RTTimeNanoTS();
1788}
1789
1790
1791/**
1792 * Stops the the CPU yielder.
1793 *
1794 * @param pVM The VM handle.
1795 */
1796VMMR3DECL(void) VMMR3YieldStop(PVM pVM)
1797{
1798 if (!pVM->vmm.s.cYieldResumeMillies)
1799 TMTimerStop(pVM->vmm.s.pYieldTimer);
1800 pVM->vmm.s.cYieldResumeMillies = pVM->vmm.s.cYieldEveryMillies;
1801 pVM->vmm.s.u64LastYield = RTTimeNanoTS();
1802}
1803
1804
1805/**
1806 * Resumes the CPU yielder when it has been a suspended or stopped.
1807 *
1808 * @param pVM The VM handle.
1809 */
1810VMMR3DECL(void) VMMR3YieldResume(PVM pVM)
1811{
1812 if (pVM->vmm.s.cYieldResumeMillies)
1813 {
1814 TMTimerSetMillies(pVM->vmm.s.pYieldTimer, pVM->vmm.s.cYieldResumeMillies);
1815 pVM->vmm.s.cYieldResumeMillies = 0;
1816 }
1817}
1818
1819
1820/**
1821 * Internal timer callback function.
1822 *
1823 * @param pVM The VM.
1824 * @param pTimer The timer handle.
1825 * @param pvUser User argument specified upon timer creation.
1826 */
1827static DECLCALLBACK(void) vmmR3YieldEMT(PVM pVM, PTMTIMER pTimer, void *pvUser)
1828{
1829 /*
1830 * This really needs some careful tuning. While we shouldn't be too gready since
1831 * that'll cause the rest of the system to stop up, we shouldn't be too nice either
1832 * because that'll cause us to stop up.
1833 *
1834 * The current logic is to use the default interval when there is no lag worth
1835 * mentioning, but when we start accumulating lag we don't bother yielding at all.
1836 *
1837 * (This depends on the TMCLOCK_VIRTUAL_SYNC to be scheduled before TMCLOCK_REAL
1838 * so the lag is up to date.)
1839 */
1840 const uint64_t u64Lag = TMVirtualSyncGetLag(pVM);
1841 if ( u64Lag < 50000000 /* 50ms */
1842 || ( u64Lag < 1000000000 /* 1s */
1843 && RTTimeNanoTS() - pVM->vmm.s.u64LastYield < 500000000 /* 500 ms */)
1844 )
1845 {
1846 uint64_t u64Elapsed = RTTimeNanoTS();
1847 pVM->vmm.s.u64LastYield = u64Elapsed;
1848
1849 RTThreadYield();
1850
1851#ifdef LOG_ENABLED
1852 u64Elapsed = RTTimeNanoTS() - u64Elapsed;
1853 Log(("vmmR3YieldEMT: %RI64 ns\n", u64Elapsed));
1854#endif
1855 }
1856 TMTimerSetMillies(pTimer, pVM->vmm.s.cYieldEveryMillies);
1857}
1858
1859
1860/**
1861 * Acquire global VM lock.
1862 *
1863 * @returns VBox status code
1864 * @param pVM The VM to operate on.
1865 */
1866VMMR3DECL(int) VMMR3Lock(PVM pVM)
1867{
1868 return RTCritSectEnter(&pVM->vmm.s.CritSectVMLock);
1869}
1870
1871
1872/**
1873 * Release global VM lock.
1874 *
1875 * @returns VBox status code
1876 * @param pVM The VM to operate on.
1877 */
1878VMMR3DECL(int) VMMR3Unlock(PVM pVM)
1879{
1880 return RTCritSectLeave(&pVM->vmm.s.CritSectVMLock);
1881}
1882
1883
1884/**
1885 * Return global VM lock owner.
1886 *
1887 * @returns Thread id of owner.
1888 * @returns NIL_RTTHREAD if no owner.
1889 * @param pVM The VM to operate on.
1890 */
1891VMMR3DECL(RTNATIVETHREAD) VMMR3LockGetOwner(PVM pVM)
1892{
1893 return RTCritSectGetOwner(&pVM->vmm.s.CritSectVMLock);
1894}
1895
1896
1897/**
1898 * Checks if the current thread is the owner of the global VM lock.
1899 *
1900 * @returns true if owner.
1901 * @returns false if not owner.
1902 * @param pVM The VM to operate on.
1903 */
1904VMMR3DECL(bool) VMMR3LockIsOwner(PVM pVM)
1905{
1906 return RTCritSectIsOwner(&pVM->vmm.s.CritSectVMLock);
1907}
1908
1909
1910/**
1911 * Executes guest code.
1912 *
1913 * @param pVM VM handle.
1914 */
1915VMMR3DECL(int) VMMR3RawRunGC(PVM pVM)
1916{
1917 Log2(("VMMR3RawRunGC: (cs:eip=%04x:%08x)\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1918
1919 /*
1920 * Set the EIP and ESP.
1921 */
1922 CPUMSetHyperEIP(pVM, CPUMGetGuestEFlags(pVM) & X86_EFL_VM
1923 ? pVM->vmm.s.pfnCPUMGCResumeGuestV86
1924 : pVM->vmm.s.pfnCPUMGCResumeGuest);
1925 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom);
1926
1927 /*
1928 * We hide log flushes (outer) and hypervisor interrupts (inner).
1929 */
1930 for (;;)
1931 {
1932 int rc;
1933 do
1934 {
1935#ifdef NO_SUPCALLR0VMM
1936 rc = VERR_GENERAL_FAILURE;
1937#else
1938 rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_RAW_RUN, NULL);
1939#endif
1940 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
1941
1942 /*
1943 * Flush the logs.
1944 */
1945#ifdef LOG_ENABLED
1946 PRTLOGGERGC pLogger = pVM->vmm.s.pLoggerHC;
1947 if ( pLogger
1948 && pLogger->offScratch > 0)
1949 RTLogFlushGC(NULL, pLogger);
1950#endif
1951#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
1952 PRTLOGGERGC pRelLogger = pVM->vmm.s.pRelLoggerHC;
1953 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
1954 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
1955#endif
1956 if (rc != VINF_VMM_CALL_HOST)
1957 {
1958 Log2(("VMMR3RawRunGC: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1959 return rc;
1960 }
1961 rc = vmmR3ServiceCallHostRequest(pVM);
1962 if (VBOX_FAILURE(rc))
1963 return rc;
1964 /* Resume GC */
1965 }
1966}
1967
1968
1969/**
1970 * Executes guest code (Intel VMX and AMD SVM).
1971 *
1972 * @param pVM VM handle.
1973 */
1974VMMR3DECL(int) VMMR3HwAccRunGC(PVM pVM)
1975{
1976 Log2(("VMMR3HwAccRunGC: (cs:eip=%04x:%08x)\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1977
1978 for (;;)
1979 {
1980 int rc;
1981 do
1982 {
1983#ifdef NO_SUPCALLR0VMM
1984 rc = VERR_GENERAL_FAILURE;
1985#else
1986 rc = SUPCallVMMR0Fast(pVM->pVMR0, VMMR0_DO_HWACC_RUN);
1987#endif
1988 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
1989
1990#ifdef LOG_ENABLED
1991 /*
1992 * Flush the log
1993 */
1994 PVMMR0LOGGER pR0Logger = pVM->vmm.s.pR0Logger;
1995 if ( pR0Logger
1996 && pR0Logger->Logger.offScratch > 0)
1997 RTLogFlushToLogger(&pR0Logger->Logger, NULL);
1998#endif /* !LOG_ENABLED */
1999 if (rc != VINF_VMM_CALL_HOST)
2000 {
2001 Log2(("VMMR3HwAccRunGC: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
2002 return rc;
2003 }
2004 rc = vmmR3ServiceCallHostRequest(pVM);
2005 if (VBOX_FAILURE(rc))
2006 return rc;
2007 /* Resume R0 */
2008 }
2009}
2010
2011/**
2012 * Calls GC a function.
2013 *
2014 * @param pVM The VM handle.
2015 * @param GCPtrEntry The GC function address.
2016 * @param cArgs The number of arguments in the ....
2017 * @param ... Arguments to the function.
2018 */
2019VMMR3DECL(int) VMMR3CallGC(PVM pVM, RTGCPTR GCPtrEntry, unsigned cArgs, ...)
2020{
2021 va_list args;
2022 va_start(args, cArgs);
2023 int rc = VMMR3CallGCV(pVM, GCPtrEntry, cArgs, args);
2024 va_end(args);
2025 return rc;
2026}
2027
2028
2029/**
2030 * Calls GC a function.
2031 *
2032 * @param pVM The VM handle.
2033 * @param GCPtrEntry The GC function address.
2034 * @param cArgs The number of arguments in the ....
2035 * @param args Arguments to the function.
2036 */
2037VMMR3DECL(int) VMMR3CallGCV(PVM pVM, RTGCPTR GCPtrEntry, unsigned cArgs, va_list args)
2038{
2039 Log2(("VMMR3CallGCV: GCPtrEntry=%VGv cArgs=%d\n", GCPtrEntry, cArgs));
2040
2041 /*
2042 * Setup the call frame using the trampoline.
2043 */
2044 CPUMHyperSetCtxCore(pVM, NULL);
2045 memset(pVM->vmm.s.pbHCStack, 0xaa, VMM_STACK_SIZE); /* Clear the stack. */
2046 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom - cArgs * sizeof(RTGCUINTPTR));
2047 PRTGCUINTPTR pFrame = (PRTGCUINTPTR)(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE) - cArgs;
2048 int i = cArgs;
2049 while (i-- > 0)
2050 *pFrame++ = va_arg(args, RTGCUINTPTR);
2051
2052 CPUMPushHyper(pVM, cArgs * sizeof(RTGCUINTPTR)); /* stack frame size */
2053 CPUMPushHyper(pVM, GCPtrEntry); /* what to call */
2054 CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnGCCallTrampoline);
2055
2056 /*
2057 * We hide log flushes (outer) and hypervisor interrupts (inner).
2058 */
2059 for (;;)
2060 {
2061 int rc;
2062 do
2063 {
2064#ifdef NO_SUPCALLR0VMM
2065 rc = VERR_GENERAL_FAILURE;
2066#else
2067 rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_RAW_RUN, NULL);
2068#endif
2069 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
2070
2071 /*
2072 * Flush the logs.
2073 */
2074#ifdef LOG_ENABLED
2075 PRTLOGGERGC pLogger = pVM->vmm.s.pLoggerHC;
2076 if ( pLogger
2077 && pLogger->offScratch > 0)
2078 RTLogFlushGC(NULL, pLogger);
2079#endif
2080#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
2081 PRTLOGGERGC pRelLogger = pVM->vmm.s.pRelLoggerHC;
2082 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
2083 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
2084#endif
2085 if (rc == VERR_TRPM_PANIC || rc == VERR_TRPM_DONT_PANIC)
2086 VMMR3FatalDump(pVM, rc);
2087 if (rc != VINF_VMM_CALL_HOST)
2088 {
2089 Log2(("VMMR3CallGCV: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
2090 return rc;
2091 }
2092 rc = vmmR3ServiceCallHostRequest(pVM);
2093 if (VBOX_FAILURE(rc))
2094 return rc;
2095 }
2096}
2097
2098
2099/**
2100 * Resumes executing hypervisor code when interrupted
2101 * by a queue flush or a debug event.
2102 *
2103 * @returns VBox status code.
2104 * @param pVM VM handle.
2105 */
2106VMMR3DECL(int) VMMR3ResumeHyper(PVM pVM)
2107{
2108 Log(("VMMR3ResumeHyper: eip=%VGv esp=%VGv\n", CPUMGetHyperEIP(pVM), CPUMGetHyperESP(pVM)));
2109
2110 /*
2111 * We hide log flushes (outer) and hypervisor interrupts (inner).
2112 */
2113 for (;;)
2114 {
2115 int rc;
2116 do
2117 {
2118#ifdef NO_SUPCALLR0VMM
2119 rc = VERR_GENERAL_FAILURE;
2120#else
2121 rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_RAW_RUN, NULL);
2122#endif
2123 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
2124
2125 /*
2126 * Flush the loggers,
2127 */
2128#ifdef LOG_ENABLED
2129 PRTLOGGERGC pLogger = pVM->vmm.s.pLoggerHC;
2130 if ( pLogger
2131 && pLogger->offScratch > 0)
2132 RTLogFlushGC(NULL, pLogger);
2133#endif
2134#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
2135 PRTLOGGERGC pRelLogger = pVM->vmm.s.pRelLoggerHC;
2136 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
2137 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
2138#endif
2139 if (rc == VERR_TRPM_PANIC || rc == VERR_TRPM_DONT_PANIC)
2140 VMMR3FatalDump(pVM, rc);
2141 if (rc != VINF_VMM_CALL_HOST)
2142 {
2143 Log(("VMMR3ResumeHyper: returns %Vrc\n", rc));
2144 return rc;
2145 }
2146 rc = vmmR3ServiceCallHostRequest(pVM);
2147 if (VBOX_FAILURE(rc))
2148 return rc;
2149 }
2150}
2151
2152
2153/**
2154 * Service a call to the ring-3 host code.
2155 *
2156 * @returns VBox status code.
2157 * @param pVM VM handle.
2158 * @remark Careful with critsects.
2159 */
2160static int vmmR3ServiceCallHostRequest(PVM pVM)
2161{
2162 switch (pVM->vmm.s.enmCallHostOperation)
2163 {
2164 /*
2165 * Acquire the PDM lock.
2166 */
2167 case VMMCALLHOST_PDM_LOCK:
2168 {
2169 pVM->vmm.s.rcCallHost = PDMR3LockCall(pVM);
2170 break;
2171 }
2172
2173 /*
2174 * Flush a PDM queue.
2175 */
2176 case VMMCALLHOST_PDM_QUEUE_FLUSH:
2177 {
2178 PDMR3QueueFlushWorker(pVM, NULL);
2179 pVM->vmm.s.rcCallHost = VINF_SUCCESS;
2180 break;
2181 }
2182
2183 /*
2184 * Grow the PGM pool.
2185 */
2186 case VMMCALLHOST_PGM_POOL_GROW:
2187 {
2188 pVM->vmm.s.rcCallHost = PGMR3PoolGrow(pVM);
2189 break;
2190 }
2191
2192 /*
2193 * Maps an page allocation chunk into ring-3 so ring-0 can use it.
2194 */
2195 case VMMCALLHOST_PGM_MAP_CHUNK:
2196 {
2197 pVM->vmm.s.rcCallHost = PGMR3PhysChunkMap(pVM, pVM->vmm.s.u64CallHostArg);
2198 break;
2199 }
2200
2201 /*
2202 * Allocates more handy pages.
2203 */
2204 case VMMCALLHOST_PGM_ALLOCATE_HANDY_PAGES:
2205 {
2206 pVM->vmm.s.rcCallHost = PGMR3PhysAllocateHandyPages(pVM);
2207 break;
2208 }
2209#ifndef NEW_PHYS_CODE
2210
2211 case VMMCALLHOST_PGM_RAM_GROW_RANGE:
2212 {
2213 pVM->vmm.s.rcCallHost = PGM3PhysGrowRange(pVM, pVM->vmm.s.u64CallHostArg);
2214 break;
2215 }
2216#endif
2217
2218 /*
2219 * Acquire the PGM lock.
2220 */
2221 case VMMCALLHOST_PGM_LOCK:
2222 {
2223 pVM->vmm.s.rcCallHost = PGMR3LockCall(pVM);
2224 break;
2225 }
2226
2227 /*
2228 * Flush REM handler notifications.
2229 */
2230 case VMMCALLHOST_REM_REPLAY_HANDLER_NOTIFICATIONS:
2231 {
2232 REMR3ReplayHandlerNotifications(pVM);
2233 break;
2234 }
2235
2236 /*
2237 * This is a noop. We just take this route to avoid unnecessary
2238 * tests in the loops.
2239 */
2240 case VMMCALLHOST_VMM_LOGGER_FLUSH:
2241 break;
2242
2243 /*
2244 * Set the VM error message.
2245 */
2246 case VMMCALLHOST_VM_SET_ERROR:
2247 VMR3SetErrorWorker(pVM);
2248 break;
2249
2250 /*
2251 * Set the VM runtime error message.
2252 */
2253 case VMMCALLHOST_VM_SET_RUNTIME_ERROR:
2254 VMR3SetRuntimeErrorWorker(pVM);
2255 break;
2256
2257 /*
2258 * Signal a ring 0 hypervisor assertion.
2259 * Cancel the longjmp operation that's in progress.
2260 */
2261 case VMMCALLHOST_VM_R0_HYPER_ASSERTION:
2262 pVM->vmm.s.CallHostR0JmpBuf.fInRing3Call = false;
2263#ifdef RT_ARCH_X86
2264 pVM->vmm.s.CallHostR0JmpBuf.eip = 0;
2265#else
2266 pVM->vmm.s.CallHostR0JmpBuf.rip = 0;
2267#endif
2268 return VINF_EM_DBG_HYPER_ASSERTION;
2269
2270 default:
2271 AssertMsgFailed(("enmCallHostOperation=%d\n", pVM->vmm.s.enmCallHostOperation));
2272 return VERR_INTERNAL_ERROR;
2273 }
2274
2275 pVM->vmm.s.enmCallHostOperation = VMMCALLHOST_INVALID;
2276 return VINF_SUCCESS;
2277}
2278
2279
2280
2281/**
2282 * Structure to pass to DBGFR3Info() and for doing all other
2283 * output during fatal dump.
2284 */
2285typedef struct VMMR3FATALDUMPINFOHLP
2286{
2287 /** The helper core. */
2288 DBGFINFOHLP Core;
2289 /** The release logger instance. */
2290 PRTLOGGER pRelLogger;
2291 /** The saved release logger flags. */
2292 RTUINT fRelLoggerFlags;
2293 /** The logger instance. */
2294 PRTLOGGER pLogger;
2295 /** The saved logger flags. */
2296 RTUINT fLoggerFlags;
2297 /** The saved logger destination flags. */
2298 RTUINT fLoggerDestFlags;
2299 /** Whether to output to stderr or not. */
2300 bool fStdErr;
2301} VMMR3FATALDUMPINFOHLP, *PVMMR3FATALDUMPINFOHLP;
2302typedef const VMMR3FATALDUMPINFOHLP *PCVMMR3FATALDUMPINFOHLP;
2303
2304
2305/**
2306 * Print formatted string.
2307 *
2308 * @param pHlp Pointer to this structure.
2309 * @param pszFormat The format string.
2310 * @param ... Arguments.
2311 */
2312static DECLCALLBACK(void) vmmR3FatalDumpInfoHlp_pfnPrintf(PCDBGFINFOHLP pHlp, const char *pszFormat, ...)
2313{
2314 va_list args;
2315 va_start(args, pszFormat);
2316 pHlp->pfnPrintfV(pHlp, pszFormat, args);
2317 va_end(args);
2318}
2319
2320
2321/**
2322 * Print formatted string.
2323 *
2324 * @param pHlp Pointer to this structure.
2325 * @param pszFormat The format string.
2326 * @param args Argument list.
2327 */
2328static DECLCALLBACK(void) vmmR3FatalDumpInfoHlp_pfnPrintfV(PCDBGFINFOHLP pHlp, const char *pszFormat, va_list args)
2329{
2330 PCVMMR3FATALDUMPINFOHLP pMyHlp = (PCVMMR3FATALDUMPINFOHLP)pHlp;
2331
2332 if (pMyHlp->pRelLogger)
2333 {
2334 va_list args2;
2335 va_copy(args2, args);
2336 RTLogLoggerV(pMyHlp->pRelLogger, pszFormat, args2);
2337 va_end(args2);
2338 }
2339 if (pMyHlp->pLogger)
2340 {
2341 va_list args2;
2342 va_copy(args2, args);
2343 RTLogLoggerV(pMyHlp->pLogger, pszFormat, args);
2344 va_end(args2);
2345 }
2346 if (pMyHlp->fStdErr)
2347 {
2348 va_list args2;
2349 va_copy(args2, args);
2350 RTStrmPrintfV(g_pStdErr, pszFormat, args);
2351 va_end(args2);
2352 }
2353}
2354
2355
2356/**
2357 * Initializes the fatal dump output helper.
2358 *
2359 * @param pHlp The structure to initialize.
2360 */
2361static void vmmR3FatalDumpInfoHlpInit(PVMMR3FATALDUMPINFOHLP pHlp)
2362{
2363 memset(pHlp, 0, sizeof(*pHlp));
2364
2365 pHlp->Core.pfnPrintf = vmmR3FatalDumpInfoHlp_pfnPrintf;
2366 pHlp->Core.pfnPrintfV = vmmR3FatalDumpInfoHlp_pfnPrintfV;
2367
2368 /*
2369 * The loggers.
2370 */
2371 pHlp->pRelLogger = RTLogRelDefaultInstance();
2372#ifndef LOG_ENABLED
2373 if (!pHlp->pRelLogger)
2374#endif
2375 pHlp->pLogger = RTLogDefaultInstance();
2376
2377 if (pHlp->pRelLogger)
2378 {
2379 pHlp->fRelLoggerFlags = pHlp->pRelLogger->fFlags;
2380 pHlp->pRelLogger->fFlags &= ~(RTLOGFLAGS_BUFFERED | RTLOGFLAGS_DISABLED);
2381 }
2382
2383 if (pHlp->pLogger)
2384 {
2385 pHlp->fLoggerFlags = pHlp->pLogger->fFlags;
2386 pHlp->fLoggerDestFlags = pHlp->pLogger->fDestFlags;
2387 pHlp->pLogger->fFlags &= ~(RTLOGFLAGS_BUFFERED | RTLOGFLAGS_DISABLED);
2388#ifndef DEBUG_sandervl
2389 pHlp->pLogger->fDestFlags |= RTLOGDEST_DEBUGGER;
2390#endif
2391 }
2392
2393 /*
2394 * Check if we need write to stderr.
2395 */
2396 pHlp->fStdErr = (!pHlp->pRelLogger || !(pHlp->pRelLogger->fDestFlags & (RTLOGDEST_STDOUT | RTLOGDEST_STDERR)))
2397 && (!pHlp->pLogger || !(pHlp->pLogger->fDestFlags & (RTLOGDEST_STDOUT | RTLOGDEST_STDERR)));
2398}
2399
2400
2401/**
2402 * Deletes the fatal dump output helper.
2403 *
2404 * @param pHlp The structure to delete.
2405 */
2406static void vmmR3FatalDumpInfoHlpDelete(PVMMR3FATALDUMPINFOHLP pHlp)
2407{
2408 if (pHlp->pRelLogger)
2409 {
2410 RTLogFlush(pHlp->pRelLogger);
2411 pHlp->pRelLogger->fFlags = pHlp->fRelLoggerFlags;
2412 }
2413
2414 if (pHlp->pLogger)
2415 {
2416 RTLogFlush(pHlp->pLogger);
2417 pHlp->pLogger->fFlags = pHlp->fLoggerFlags;
2418 pHlp->pLogger->fDestFlags = pHlp->fLoggerDestFlags;
2419 }
2420}
2421
2422
2423/**
2424 * Dumps the VM state on a fatal error.
2425 *
2426 * @param pVM VM Handle.
2427 * @param rcErr VBox status code.
2428 */
2429VMMR3DECL(void) VMMR3FatalDump(PVM pVM, int rcErr)
2430{
2431 /*
2432 * Create our output helper and sync it with the log settings.
2433 * This helper will be used for all the output.
2434 */
2435 VMMR3FATALDUMPINFOHLP Hlp;
2436 PCDBGFINFOHLP pHlp = &Hlp.Core;
2437 vmmR3FatalDumpInfoHlpInit(&Hlp);
2438
2439 /*
2440 * Header.
2441 */
2442 pHlp->pfnPrintf(pHlp,
2443 "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n"
2444 "!!\n"
2445 "!! Guru Meditation %d (%Vrc)\n"
2446 "!!\n",
2447 rcErr, rcErr);
2448
2449 /*
2450 * Continue according to context.
2451 */
2452 bool fDoneHyper = false;
2453 switch (rcErr)
2454 {
2455 /*
2456 * Hyper visor errors.
2457 */
2458 case VINF_EM_DBG_HYPER_ASSERTION:
2459 pHlp->pfnPrintf(pHlp, "%s%s!!\n", VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
2460 /* fall thru */
2461 case VERR_TRPM_DONT_PANIC:
2462 case VERR_TRPM_PANIC:
2463 case VINF_EM_RAW_STALE_SELECTOR:
2464 case VINF_EM_RAW_IRET_TRAP:
2465 case VINF_EM_DBG_HYPER_BREAKPOINT:
2466 case VINF_EM_DBG_HYPER_STEPPED:
2467 {
2468 /* Trap? */
2469 uint32_t uEIP = CPUMGetHyperEIP(pVM);
2470 TRPMEVENT enmType;
2471 uint8_t u8TrapNo = 0xce;
2472 RTGCUINT uErrorCode = 0xdeadface;
2473 RTGCUINTPTR uCR2 = 0xdeadface;
2474 int rc2 = TRPMQueryTrapAll(pVM, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
2475 if (VBOX_SUCCESS(rc2))
2476 pHlp->pfnPrintf(pHlp,
2477 "!! TRAP=%02x ERRCD=%VGv CR2=%VGv EIP=%VGv Type=%d\n",
2478 u8TrapNo, uErrorCode, uCR2, uEIP, enmType);
2479 else
2480 pHlp->pfnPrintf(pHlp,
2481 "!! EIP=%VGv NOTRAP\n",
2482 uEIP);
2483
2484 /*
2485 * Try figure out where eip is.
2486 */
2487 /** @todo make query call for core code or move this function to VMM. */
2488 /* core code? */
2489 //if (uEIP - (RTGCUINTPTR)pVM->vmm.s.pvGCCoreCode < pVM->vmm.s.cbCoreCode)
2490 // pHlp->pfnPrintf(pHlp,
2491 // "!! EIP is in CoreCode, offset %#x\n",
2492 // uEIP - (RTGCUINTPTR)pVM->vmm.s.pvGCCoreCode);
2493 //else
2494 { /* ask PDM */
2495 /** @todo ask DBGFR3Sym later. */
2496 char szModName[64];
2497 RTGCPTR GCPtrMod;
2498 char szNearSym1[260];
2499 RTGCPTR GCPtrNearSym1;
2500 char szNearSym2[260];
2501 RTGCPTR GCPtrNearSym2;
2502 int rc = PDMR3QueryModFromEIP(pVM, uEIP,
2503 &szModName[0], sizeof(szModName), &GCPtrMod,
2504 &szNearSym1[0], sizeof(szNearSym1), &GCPtrNearSym1,
2505 &szNearSym2[0], sizeof(szNearSym2), &GCPtrNearSym2);
2506 if (VBOX_SUCCESS(rc))
2507 {
2508 pHlp->pfnPrintf(pHlp,
2509 "!! EIP in %s (%p) at rva %x near symbols:\n"
2510 "!! %VGv rva %VGv off %08x %s\n"
2511 "!! %VGv rva %VGv off -%08x %s\n",
2512 szModName, GCPtrMod, (unsigned)(uEIP - GCPtrMod),
2513 GCPtrNearSym1, GCPtrNearSym1 - GCPtrMod, (unsigned)(uEIP - GCPtrNearSym1), szNearSym1,
2514 GCPtrNearSym2, GCPtrNearSym2 - GCPtrMod, (unsigned)(GCPtrNearSym2 - uEIP), szNearSym2);
2515 }
2516 else
2517 pHlp->pfnPrintf(pHlp,
2518 "!! EIP is not in any code known to VMM!\n");
2519 }
2520
2521 /* Disassemble the instruction. */
2522 char szInstr[256];
2523 rc2 = DBGFR3DisasInstrEx(pVM, 0, 0, DBGF_DISAS_FLAGS_CURRENT_HYPER, &szInstr[0], sizeof(szInstr), NULL);
2524 if (VBOX_SUCCESS(rc2))
2525 pHlp->pfnPrintf(pHlp,
2526 "!! %s\n", szInstr);
2527
2528 /* Dump the hypervisor cpu state. */
2529 pHlp->pfnPrintf(pHlp,
2530 "!!\n"
2531 "!!\n"
2532 "!!\n");
2533 rc2 = DBGFR3Info(pVM, "cpumhyper", "verbose", pHlp);
2534 fDoneHyper = true;
2535
2536 /* Callstack. */
2537 DBGFSTACKFRAME Frame = {0};
2538 rc2 = DBGFR3StackWalkBeginHyper(pVM, &Frame);
2539 if (VBOX_SUCCESS(rc2))
2540 {
2541 pHlp->pfnPrintf(pHlp,
2542 "!!\n"
2543 "!! Call Stack:\n"
2544 "!!\n"
2545 "EBP Ret EBP Ret CS:EIP Arg0 Arg1 Arg2 Arg3 CS:EIP Symbol [line]\n");
2546 do
2547 {
2548 pHlp->pfnPrintf(pHlp,
2549 "%08RX32 %08RX32 %04RX32:%08RX32 %08RX32 %08RX32 %08RX32 %08RX32",
2550 (uint32_t)Frame.AddrFrame.off,
2551 (uint32_t)Frame.AddrReturnFrame.off,
2552 (uint32_t)Frame.AddrReturnPC.Sel,
2553 (uint32_t)Frame.AddrReturnPC.off,
2554 Frame.Args.au32[0],
2555 Frame.Args.au32[1],
2556 Frame.Args.au32[2],
2557 Frame.Args.au32[3]);
2558 pHlp->pfnPrintf(pHlp, " %RTsel:%08RGv", Frame.AddrPC.Sel, Frame.AddrPC.off);
2559 if (Frame.pSymPC)
2560 {
2561 RTGCINTPTR offDisp = Frame.AddrPC.FlatPtr - Frame.pSymPC->Value;
2562 if (offDisp > 0)
2563 pHlp->pfnPrintf(pHlp, " %s+%llx", Frame.pSymPC->szName, (int64_t)offDisp);
2564 else if (offDisp < 0)
2565 pHlp->pfnPrintf(pHlp, " %s-%llx", Frame.pSymPC->szName, -(int64_t)offDisp);
2566 else
2567 pHlp->pfnPrintf(pHlp, " %s", Frame.pSymPC->szName);
2568 }
2569 if (Frame.pLinePC)
2570 pHlp->pfnPrintf(pHlp, " [%s @ 0i%d]", Frame.pLinePC->szFilename, Frame.pLinePC->uLineNo);
2571 pHlp->pfnPrintf(pHlp, "\n");
2572
2573 /* next */
2574 rc2 = DBGFR3StackWalkNext(pVM, &Frame);
2575 } while (VBOX_SUCCESS(rc2));
2576 DBGFR3StackWalkEnd(pVM, &Frame);
2577 }
2578
2579 /* raw stack */
2580 pHlp->pfnPrintf(pHlp,
2581 "!!\n"
2582 "!! Raw stack (mind the direction).\n"
2583 "!!\n"
2584 "%.*Vhxd\n",
2585 VMM_STACK_SIZE, (char *)pVM->vmm.s.pbHCStack);
2586 break;
2587 }
2588
2589 default:
2590 {
2591 break;
2592 }
2593
2594 } /* switch (rcErr) */
2595
2596
2597 /*
2598 * Dump useful state information.
2599 */
2600 /** @todo convert these dumpers to DBGFR3Info() handlers!!! */
2601 pHlp->pfnPrintf(pHlp,
2602 "!!\n"
2603 "!! PGM Access Handlers & Stuff:\n"
2604 "!!\n");
2605 PGMR3DumpMappings(pVM);
2606
2607
2608 /*
2609 * Generic info dumper loop.
2610 */
2611 static struct
2612 {
2613 const char *pszInfo;
2614 const char *pszArgs;
2615 } const aInfo[] =
2616 {
2617 { "hma", NULL },
2618 { "cpumguest", "verbose" },
2619 { "cpumhyper", "verbose" },
2620 { "cpumhost", "verbose" },
2621 { "mode", "all" },
2622 { "cpuid", "verbose" },
2623 { "gdt", NULL },
2624 { "ldt", NULL },
2625 //{ "tss", NULL },
2626 { "ioport", NULL },
2627 { "mmio", NULL },
2628 { "phys", NULL },
2629 //{ "pgmpd", NULL }, - doesn't always work at init time...
2630 { "timers", NULL },
2631 { "activetimers", NULL },
2632 { "handlers", "phys virt stats" },
2633 { "cfgm", NULL },
2634 };
2635 for (unsigned i = 0; i < ELEMENTS(aInfo); i++)
2636 {
2637 if (fDoneHyper && !strcmp(aInfo[i].pszInfo, "cpumhyper"))
2638 continue;
2639 pHlp->pfnPrintf(pHlp,
2640 "!!\n"
2641 "!! {%s, %s}\n"
2642 "!!\n",
2643 aInfo[i].pszInfo, aInfo[i].pszArgs);
2644 DBGFR3Info(pVM, aInfo[i].pszInfo, aInfo[i].pszArgs, pHlp);
2645 }
2646
2647 /* done */
2648 pHlp->pfnPrintf(pHlp,
2649 "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n");
2650
2651
2652 /*
2653 * Delete the output instance (flushing and restoring of flags).
2654 */
2655 vmmR3FatalDumpInfoHlpDelete(&Hlp);
2656}
2657
2658
2659
2660/**
2661 * Displays the Force action Flags.
2662 *
2663 * @param pVM The VM handle.
2664 * @param pHlp The output helpers.
2665 * @param pszArgs The additional arguments (ignored).
2666 */
2667static DECLCALLBACK(void) vmmR3InfoFF(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2668{
2669 const uint32_t fForcedActions = pVM->fForcedActions;
2670
2671 pHlp->pfnPrintf(pHlp, "Forced action Flags: %#RX32", fForcedActions);
2672
2673 /* show the flag mnemonics */
2674 int c = 0;
2675 uint32_t f = fForcedActions;
2676#define PRINT_FLAG(flag) do { \
2677 if (f & (flag)) \
2678 { \
2679 static const char *s_psz = #flag; \
2680 if (!(c % 6)) \
2681 pHlp->pfnPrintf(pHlp, "%s\n %s", c ? "," : "", s_psz + 6); \
2682 else \
2683 pHlp->pfnPrintf(pHlp, ", %s", s_psz + 6); \
2684 c++; \
2685 f &= ~(flag); \
2686 } \
2687 } while (0)
2688 PRINT_FLAG(VM_FF_INTERRUPT_APIC);
2689 PRINT_FLAG(VM_FF_INTERRUPT_PIC);
2690 PRINT_FLAG(VM_FF_TIMER);
2691 PRINT_FLAG(VM_FF_PDM_QUEUES);
2692 PRINT_FLAG(VM_FF_PDM_DMA);
2693 PRINT_FLAG(VM_FF_PDM_CRITSECT);
2694 PRINT_FLAG(VM_FF_DBGF);
2695 PRINT_FLAG(VM_FF_REQUEST);
2696 PRINT_FLAG(VM_FF_TERMINATE);
2697 PRINT_FLAG(VM_FF_RESET);
2698 PRINT_FLAG(VM_FF_PGM_SYNC_CR3);
2699 PRINT_FLAG(VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2700 PRINT_FLAG(VM_FF_TRPM_SYNC_IDT);
2701 PRINT_FLAG(VM_FF_SELM_SYNC_TSS);
2702 PRINT_FLAG(VM_FF_SELM_SYNC_GDT);
2703 PRINT_FLAG(VM_FF_SELM_SYNC_LDT);
2704 PRINT_FLAG(VM_FF_INHIBIT_INTERRUPTS);
2705 PRINT_FLAG(VM_FF_CSAM_SCAN_PAGE);
2706 PRINT_FLAG(VM_FF_CSAM_PENDING_ACTION);
2707 PRINT_FLAG(VM_FF_TO_R3);
2708 PRINT_FLAG(VM_FF_DEBUG_SUSPEND);
2709 if (f)
2710 pHlp->pfnPrintf(pHlp, "%s\n Unknown bits: %#RX32\n", c ? "," : "", f);
2711 else
2712 pHlp->pfnPrintf(pHlp, "\n");
2713#undef PRINT_FLAG
2714
2715 /* the groups */
2716 c = 0;
2717#define PRINT_GROUP(grp) do { \
2718 if (fForcedActions & (grp)) \
2719 { \
2720 static const char *s_psz = #grp; \
2721 if (!(c % 5)) \
2722 pHlp->pfnPrintf(pHlp, "%s %s", c ? ",\n" : "Groups:\n", s_psz + 6); \
2723 else \
2724 pHlp->pfnPrintf(pHlp, ", %s", s_psz + 6); \
2725 c++; \
2726 } \
2727 } while (0)
2728 PRINT_GROUP(VM_FF_EXTERNAL_SUSPENDED_MASK);
2729 PRINT_GROUP(VM_FF_EXTERNAL_HALTED_MASK);
2730 PRINT_GROUP(VM_FF_HIGH_PRIORITY_PRE_MASK);
2731 PRINT_GROUP(VM_FF_HIGH_PRIORITY_PRE_RAW_MASK);
2732 PRINT_GROUP(VM_FF_HIGH_PRIORITY_POST_MASK);
2733 PRINT_GROUP(VM_FF_NORMAL_PRIORITY_POST_MASK);
2734 PRINT_GROUP(VM_FF_NORMAL_PRIORITY_MASK);
2735 PRINT_GROUP(VM_FF_RESUME_GUEST_MASK);
2736 PRINT_GROUP(VM_FF_ALL_BUT_RAW_MASK);
2737 if (c)
2738 pHlp->pfnPrintf(pHlp, "\n");
2739#undef PRINT_GROUP
2740}
2741
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