VirtualBox

source: vbox/trunk/src/VBox/VMM/VMM.cpp@ 880

Last change on this file since 880 was 873, checked in by vboxsync, 18 years ago

Some release logging, mainly for debugging the 64-bit restore issue.
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1/* $Id: VMM.cpp 873 2007-02-13 14:09:53Z vboxsync $ */
2/** @file
3 * VMM - The Virtual Machine Monitor Core.
4 */
5
6/*
7 * Copyright (C) 2006 InnoTek Systemberatung GmbH
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License as published by the Free Software Foundation,
13 * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14 * distribution. VirtualBox OSE is distributed in the hope that it will
15 * be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * If you received this file as part of a commercial VirtualBox
18 * distribution, then only the terms of your commercial VirtualBox
19 * license agreement apply instead of the previous paragraph.
20 */
21
22#if 0 //defined(__AMD64__) && !defined(__WIN__)
23# define NO_SUPCALLR0VMM
24#endif
25
26/** @page pg_vmm VMM - The Virtual Machine Monitor
27 *
28 * !Revise this! It's already incorrect!
29 *
30 * The Virtual Machine Monitor (VMM) is the core of the virtual machine. It
31 * manages the alternate reality; controlling the virtualization, managing
32 * resources, tracking CPU state, it's resources and so on...
33 *
34 * We will split the VMM into smaller entities:
35 *
36 * - Virtual Machine Core Monitor (VMCM), which purpose it is to
37 * provide ring and world switching, that including routing
38 * interrupts to the host OS and traps to the appropriate trap
39 * handlers. It will implement an external interface for
40 * managing trap handlers.
41 *
42 * - CPU Monitor (CM), tracking the state of the CPU (in the alternate
43 * reality) and implementing external interfaces to read and change
44 * the state.
45 *
46 * - Memory Monitor (MM), which purpose it is to virtualize physical
47 * pages, segment descriptor tables, interrupt descriptor tables, task
48 * segments, and keep track of all memory providing external interfaces
49 * to access content and map pages. (Internally splitt into smaller entities!)
50 *
51 * - IO Monitor (IOM), which virtualizes in and out I/O operations. It
52 * interacts with the MM to implement memory mapped I/O. External
53 * interfaces for adding and removing I/O ranges are implemented.
54 *
55 * - External Interrupt Monitor (EIM), which purpose it is to manage
56 * interrupts generated by virtual devices. This monitor provides
57 * an interfaces for raising interrupts which is accessible at any
58 * time and from all thread.
59 * <p>
60 * A subentity of the EIM is the vitual Programmable Interrupt
61 * Controller Device (VPICD), and perhaps a virtual I/O Advanced
62 * Programmable Interrupt Controller Device (VAPICD).
63 *
64 * - Direct Memory Access Monitor (DMAM), which purpose it is to support
65 * virtual device using the DMA controller. Interfaces must be as the
66 * EIM interfaces independent and threadable.
67 * <p>
68 * A subentity of the DMAM is a virtual DMA Controller Device (VDMACD).
69 *
70 *
71 * Entities working on a higher level:
72 *
73 * - Device Manager (DM), which is a support facility for virtualized
74 * hardware. This provides generic facilities for efficient device
75 * virtualization. It will manage device attaching and detaching
76 * conversing with EIM and IOM.
77 *
78 * - Debugger Facility (DBGF) provides the basic features for
79 * debugging the alternate reality execution.
80 *
81 *
82 *
83 * @section pg_vmm_s_use_cases Use Cases
84 *
85 * @subsection pg_vmm_s_use_case_boot Bootstrap
86 *
87 * - Basic Init:
88 * - Init SUPDRV.
89 *
90 * - Init Virtual Machine Instance:
91 * - Load settings.
92 * - Check resource requirements (memory, com, stuff).
93 *
94 * - Init Host Ring 3 part:
95 * - Init Core code.
96 * - Load Pluggable Components.
97 * - Init Pluggable Components.
98 *
99 * - Init Host Ring 0 part:
100 * - Load Core (core = core components like VMM, RMI, CA, and so on) code.
101 * - Init Core code.
102 * - Load Pluggable Component code.
103 * - Init Pluggable Component code.
104 *
105 * - Allocate first chunk of memory and pin it down. This block of memory
106 * will fit the following pieces:
107 * - Virtual Machine Instance data. (Config, CPU state, VMM state, ++)
108 * (This is available from everywhere (at different addresses though)).
109 * - VMM Guest Context code.
110 * - Pluggable devices Guest Context code.
111 * - Page tables (directory and everything) for the VMM Guest
112 *
113 * - Setup Guest (Ring 0) part:
114 * - Setup initial page tables (i.e. directory all the stuff).
115 * - Load Core Guest Context code.
116 * - Load Pluggable Devices Guest Context code.
117 *
118 *
119 */
120
121
122/*******************************************************************************
123* Header Files *
124*******************************************************************************/
125#define LOG_GROUP LOG_GROUP_VMM
126#include <VBox/vmm.h>
127#include <VBox/vmapi.h>
128#include <VBox/pgm.h>
129#include <VBox/cfgm.h>
130#include <VBox/pdm.h>
131#include <VBox/cpum.h>
132#include <VBox/mm.h>
133#include <VBox/iom.h>
134#include <VBox/trpm.h>
135#include <VBox/selm.h>
136#include <VBox/em.h>
137#include <VBox/sup.h>
138#include <VBox/dbgf.h>
139#include <VBox/csam.h>
140#include <VBox/patm.h>
141#include <VBox/rem.h>
142#include <VBox/ssm.h>
143#include <VBox/tm.h>
144#include "VMMInternal.h"
145#include "VMMSwitcher/VMMSwitcher.h"
146#include <VBox/vm.h>
147#include <VBox/err.h>
148#include <VBox/param.h>
149#include <VBox/version.h>
150#include <VBox/x86.h>
151#include <iprt/assert.h>
152#include <iprt/alloc.h>
153#include <iprt/asm.h>
154#include <iprt/time.h>
155#include <iprt/stream.h>
156#include <iprt/string.h>
157#include <iprt/stdarg.h>
158#include <iprt/ctype.h>
159
160
161
162/** The saved state version. */
163#define VMM_SAVED_STATE_VERSION 3
164
165
166/*******************************************************************************
167* Internal Functions *
168*******************************************************************************/
169static DECLCALLBACK(int) vmmR3Save(PVM pVM, PSSMHANDLE pSSM);
170static DECLCALLBACK(int) vmmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
171static DECLCALLBACK(void) vmmR3YieldEMT(PVM pVM, PTMTIMER pTimer, void *pvUser);
172static int vmmR3ServiceCallHostRequest(PVM pVM);
173
174
175/*******************************************************************************
176* Global Variables *
177*******************************************************************************/
178/** Array of switcher defininitions.
179 * The type and index shall match!
180 */
181static PVMMSWITCHERDEF s_apSwitchers[VMMSWITCHER_MAX] =
182{
183 NULL, /* invalid entry */
184#ifndef __AMD64__
185 &vmmR3Switcher32BitTo32Bit_Def,
186 &vmmR3Switcher32BitToPAE_Def,
187 NULL, //&vmmR3Switcher32BitToAMD64_Def,
188 &vmmR3SwitcherPAETo32Bit_Def,
189 &vmmR3SwitcherPAEToPAE_Def,
190 NULL, //&vmmR3SwitcherPAEToAMD64_Def,
191 NULL, //&vmmR3SwitcherAMD64ToPAE_Def,
192 NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
193#else
194 NULL, //&vmmR3Switcher32BitTo32Bit_Def,
195 NULL, //&vmmR3Switcher32BitToPAE_Def,
196 NULL, //&vmmR3Switcher32BitToAMD64_Def,
197 NULL, //&vmmR3SwitcherPAETo32Bit_Def,
198 NULL, //&vmmR3SwitcherPAEToPAE_Def,
199 NULL, //&vmmR3SwitcherPAEToAMD64_Def,
200 &vmmR3SwitcherAMD64ToPAE_Def,
201 NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
202#endif
203};
204
205
206
207/**
208 * Initiates the core code.
209 *
210 * This is core per VM code which might need fixups and/or for ease of use
211 * are put on linear contiguous backing.
212 *
213 * @returns VBox status code.
214 * @param pVM Pointer to VM structure.
215 */
216static int vmmR3InitCoreCode(PVM pVM)
217{
218 /*
219 * Calc the size.
220 */
221 unsigned cbCoreCode = 0;
222 for (unsigned iSwitcher = 0; iSwitcher < ELEMENTS(s_apSwitchers); iSwitcher++)
223 {
224 pVM->vmm.s.aoffSwitchers[iSwitcher] = cbCoreCode;
225 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
226 if (pSwitcher)
227 {
228 AssertRelease((unsigned)pSwitcher->enmType == iSwitcher);
229 cbCoreCode += RT_ALIGN_32(pSwitcher->cbCode + 1, 32);
230 }
231 }
232
233 /*
234 * Allocate continguous pages for switchers and deal with
235 * conflicts in the intermediate mapping of the code.
236 */
237 pVM->vmm.s.cbCoreCode = RT_ALIGN_32(cbCoreCode, PAGE_SIZE);
238 pVM->vmm.s.pvHCCoreCodeR3 = SUPContAlloc2(pVM->vmm.s.cbCoreCode, &pVM->vmm.s.pvHCCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
239 int rc = VERR_NO_MEMORY;
240 if (pVM->vmm.s.pvHCCoreCodeR3)
241 {
242 rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvHCCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
243 if (rc == VERR_PGM_MAPPINGS_FIX_CONFLICT)
244 {
245 /* try more allocations. */
246 struct
247 {
248 void *pvR0;
249 void *pvR3;
250 RTHCPHYS HCPhys;
251 } aBadTries[16];
252 unsigned i = 0;
253 do
254 {
255 aBadTries[i].pvR3 = pVM->vmm.s.pvHCCoreCodeR3;
256 aBadTries[i].pvR0 = pVM->vmm.s.pvHCCoreCodeR0;
257 aBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
258 i++;
259 pVM->vmm.s.pvHCCoreCodeR0 = NIL_RTR0PTR;
260 pVM->vmm.s.HCPhysCoreCode = NIL_RTHCPHYS;
261 pVM->vmm.s.pvHCCoreCodeR3 = SUPContAlloc2(pVM->vmm.s.cbCoreCode, &pVM->vmm.s.pvHCCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
262 if (!pVM->vmm.s.pvHCCoreCodeR3)
263 break;
264 rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvHCCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
265 } while ( rc == VERR_PGM_MAPPINGS_FIX_CONFLICT
266 && i < ELEMENTS(aBadTries) - 1);
267
268 /* cleanup */
269 if (VBOX_FAILURE(rc))
270 {
271 aBadTries[i].pvR3 = pVM->vmm.s.pvHCCoreCodeR3;
272 aBadTries[i].pvR0 = pVM->vmm.s.pvHCCoreCodeR0;
273 aBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
274 i++;
275 LogRel(("Failed to allocated and map core code: rc=%Vrc\n", rc));
276 }
277 while (i-- > 0)
278 {
279 LogRel(("Core code alloc attempt #%d: pvR3=%p pvR0=%p HCPhys=%VHp\n",
280 i, aBadTries[i].pvR3, aBadTries[i].pvR0, aBadTries[i].HCPhys));
281 SUPContFree(aBadTries[i].pvR3);
282 }
283 }
284 }
285 if (VBOX_SUCCESS(rc))
286 {
287 /*
288 * copy the code.
289 */
290 for (unsigned iSwitcher = 0; iSwitcher < ELEMENTS(s_apSwitchers); iSwitcher++)
291 {
292 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
293 if (pSwitcher)
294 memcpy((uint8_t *)pVM->vmm.s.pvHCCoreCodeR3 + pVM->vmm.s.aoffSwitchers[iSwitcher],
295 pSwitcher->pvCode, pSwitcher->cbCode);
296 }
297
298 /*
299 * Map the code into the GC address space.
300 */
301 rc = MMR3HyperMapHCPhys(pVM, pVM->vmm.s.pvHCCoreCodeR3, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, "Core Code", &pVM->vmm.s.pvGCCoreCode);
302 if (VBOX_SUCCESS(rc))
303 {
304 MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
305 LogRel(("CoreCode: R3=%VHv R0=%VHv GC=%VGv Phys=%VHp cb=%#x\n",
306 pVM->vmm.s.pvHCCoreCodeR3, pVM->vmm.s.pvHCCoreCodeR0, pVM->vmm.s.pvGCCoreCode, pVM->vmm.s.HCPhysCoreCode, pVM->vmm.s.cbCoreCode));
307
308 /*
309 * Finally, PGM probably have selected a switcher already but we need
310 * to do get the addresses so we'll reselect it.
311 * This may legally fail so, we're ignoring the rc.
312 */
313 VMMR3SelectSwitcher(pVM, pVM->vmm.s.enmSwitcher);
314 return rc;
315 }
316
317 /* shit */
318 AssertMsgFailed(("PGMR3Map(,%VGv, %VGp, %#x, 0) failed with rc=%Vrc\n", pVM->vmm.s.pvGCCoreCode, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, rc));
319 SUPContFree(pVM->vmm.s.pvHCCoreCodeR3);
320 }
321 else
322 VMSetError(pVM, rc, RT_SRC_POS,
323 N_("Failed to allocate %d bytes of contiguous memory for the world switcher code."),
324 cbCoreCode);
325
326 pVM->vmm.s.pvHCCoreCodeR3 = NULL;
327 pVM->vmm.s.pvHCCoreCodeR0 = NIL_RTR0PTR;
328 pVM->vmm.s.pvGCCoreCode = 0;
329 return rc;
330}
331
332
333/**
334 * Initializes the VMM.
335 *
336 * @returns VBox status code.
337 * @param pVM The VM to operate on.
338 */
339VMMR3DECL(int) VMMR3Init(PVM pVM)
340{
341 LogFlow(("VMMR3Init\n"));
342
343 /*
344 * Assert alignment, sizes and order.
345 */
346 AssertMsg(pVM->vmm.s.offVM == 0, ("Already initialized!\n"));
347 AssertMsg(sizeof(pVM->vmm.padding) >= sizeof(pVM->vmm.s),
348 ("pVM->vmm.padding is too small! vmm.padding %d while vmm.s is %d\n",
349 sizeof(pVM->vmm.padding), sizeof(pVM->vmm.s)));
350
351 /*
352 * Init basic VM VMM members.
353 */
354 pVM->vmm.s.offVM = RT_OFFSETOF(VM, vmm);
355 int rc = CFGMR3QueryU32(CFGMR3GetRoot(pVM), "YieldEMTInterval", &pVM->vmm.s.cYieldEveryMillies);
356 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
357 pVM->vmm.s.cYieldEveryMillies = 23; /* Value arrived at after experimenting with the grub boot prompt. */
358 //pVM->vmm.s.cYieldEveryMillies = 8; //debugging
359 else
360 AssertMsgRCReturn(rc, ("Configuration error. Failed to query \"YieldEMTInterval\", rc=%Vrc\n", rc), rc);
361
362 /*
363 * Register the saved state data unit.
364 */
365 rc = SSMR3RegisterInternal(pVM, "vmm", 1, VMM_SAVED_STATE_VERSION, VMM_STACK_SIZE + sizeof(RTGCPTR),
366 NULL, vmmR3Save, NULL,
367 NULL, vmmR3Load, NULL);
368 if (VBOX_FAILURE(rc))
369 return rc;
370
371 /* GC switchers are enabled by default. Turned off by HWACCM. */
372 pVM->vmm.s.fSwitcherDisabled = false;
373
374 /*
375 * Init core code.
376 */
377 rc = vmmR3InitCoreCode(pVM);
378 if (VBOX_SUCCESS(rc))
379 {
380 /*
381 * Allocate & init VMM GC stack.
382 * The stack pages are also used by the VMM R0 when VMMR0CallHost is invoked.
383 * (The page protection is modifed during R3 init completion.)
384 */
385#ifdef VBOX_STRICT_VMM_STACK
386 rc = MMHyperAlloc(pVM, VMM_STACK_SIZE + PAGE_SIZE + PAGE_SIZE, PAGE_SIZE, MM_TAG_VMM, (void **)&pVM->vmm.s.pbHCStack);
387#else
388 rc = MMHyperAlloc(pVM, VMM_STACK_SIZE, PAGE_SIZE, MM_TAG_VMM, (void **)&pVM->vmm.s.pbHCStack);
389#endif
390 if (VBOX_SUCCESS(rc))
391 {
392 /* Set HC and GC stack pointers to top of stack. */
393 pVM->vmm.s.CallHostR0JmpBuf.pvSavedStack = (RTR0PTR)pVM->vmm.s.pbHCStack;
394 pVM->vmm.s.pbGCStack = MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack);
395 pVM->vmm.s.pbGCStackBottom = pVM->vmm.s.pbGCStack + VMM_STACK_SIZE;
396 AssertRelease(pVM->vmm.s.pbGCStack);
397
398 /* Set hypervisor eip. */
399 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStack);
400
401 /*
402 * Allocate GC & R0 Logger instances (they are finalized in the relocator).
403 */
404#ifdef LOG_ENABLED
405 PRTLOGGER pLogger = RTLogDefaultInstance();
406 if (pLogger)
407 {
408 pVM->vmm.s.cbLoggerGC = RT_OFFSETOF(RTLOGGERGC, afGroups[pLogger->cGroups]);
409 rc = MMHyperAlloc(pVM, pVM->vmm.s.cbLoggerGC, 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pLoggerHC);
410 if (VBOX_SUCCESS(rc))
411 {
412 pVM->vmm.s.pLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pLoggerHC);
413
414/*
415 * Ring-0 logging isn't 100% safe yet (thread id reuse / process exit cleanup), so
416 * you have to sign up here by adding your defined(DEBUG_<userid>) to the #if.
417 *
418 * If you want to log in non-debug modes, you'll have to remember to change SUPDRvShared.c
419 * to not stub all the log functions.
420 */
421# ifdef DEBUG_sandervl
422 rc = MMHyperAlloc(pVM, RT_OFFSETOF(VMMR0LOGGER, Logger.afGroups[pLogger->cGroups]),
423 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pR0Logger);
424 if (VBOX_SUCCESS(rc))
425 {
426 pVM->vmm.s.pR0Logger->pVM = pVM;
427 //pVM->vmm.s.pR0Logger->fCreated = false;
428 pVM->vmm.s.pR0Logger->cbLogger = RT_OFFSETOF(RTLOGGER, afGroups[pLogger->cGroups]);
429 }
430# endif
431 }
432 }
433#endif /* LOG_ENABLED */
434
435#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
436 /*
437 * Allocate GC Release Logger instances (finalized in the relocator).
438 */
439 if (VBOX_SUCCESS(rc))
440 {
441 PRTLOGGER pRelLogger = RTLogRelDefaultInstance();
442 if (pRelLogger)
443 {
444 pVM->vmm.s.cbRelLoggerGC = RT_OFFSETOF(RTLOGGERGC, afGroups[pRelLogger->cGroups]);
445 rc = MMHyperAlloc(pVM, pVM->vmm.s.cbRelLoggerGC, 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pRelLoggerHC);
446 if (VBOX_SUCCESS(rc))
447 pVM->vmm.s.pRelLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pRelLoggerHC);
448 }
449 }
450#endif /* VBOX_WITH_GC_AND_R0_RELEASE_LOG */
451
452#ifdef VBOX_WITH_NMI
453 /*
454 * Allocate mapping for the host APIC.
455 */
456 if (VBOX_SUCCESS(rc))
457 {
458 rc = MMR3HyperReserve(pVM, PAGE_SIZE, "Host APIC", &pVM->vmm.s.GCPtrApicBase);
459 AssertRC(rc);
460 }
461#endif
462 if (VBOX_SUCCESS(rc))
463 {
464 rc = RTCritSectInit(&pVM->vmm.s.CritSectVMLock);
465 if (VBOX_SUCCESS(rc))
466 {
467 /*
468 * Statistics.
469 */
470 STAM_REG(pVM, &pVM->vmm.s.StatRunGC, STAMTYPE_COUNTER, "/VMM/RunGC", STAMUNIT_OCCURENCES, "Number of context switches.");
471 STAM_REG(pVM, &pVM->vmm.s.StatGCRetNormal, STAMTYPE_COUNTER, "/VMM/GCRet/Normal", STAMUNIT_OCCURENCES, "Number of VINF_SUCCESS returns.");
472 STAM_REG(pVM, &pVM->vmm.s.StatGCRetInterrupt, STAMTYPE_COUNTER, "/VMM/GCRet/Interrupt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT returns.");
473 STAM_REG(pVM, &pVM->vmm.s.StatGCRetInterruptHyper, STAMTYPE_COUNTER, "/VMM/GCRet/InterruptHyper", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT_HYPER returns.");
474 STAM_REG(pVM, &pVM->vmm.s.StatGCRetGuestTrap, STAMTYPE_COUNTER, "/VMM/GCRet/GuestTrap", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_GUEST_TRAP returns.");
475 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRingSwitch, STAMTYPE_COUNTER, "/VMM/GCRet/RingSwitch", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_RING_SWITCH returns.");
476 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRingSwitchInt, STAMTYPE_COUNTER, "/VMM/GCRet/RingSwitchInt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_RING_SWITCH_INT returns.");
477 STAM_REG(pVM, &pVM->vmm.s.StatGCRetExceptionPrivilege, STAMTYPE_COUNTER, "/VMM/GCRet/ExceptionPrivilege", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_EXCEPTION_PRIVILEGED returns.");
478 STAM_REG(pVM, &pVM->vmm.s.StatGCRetStaleSelector, STAMTYPE_COUNTER, "/VMM/GCRet/StaleSelector", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_STALE_SELECTOR returns.");
479 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIRETTrap, STAMTYPE_COUNTER, "/VMM/GCRet/IRETTrap", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_IRET_TRAP returns.");
480 STAM_REG(pVM, &pVM->vmm.s.StatGCRetEmulate, STAMTYPE_COUNTER, "/VMM/GCRet/Emulate", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION returns.");
481 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchEmulate, STAMTYPE_COUNTER, "/VMM/GCRet/PatchEmulate", STAMUNIT_OCCURENCES, "Number of VINF_PATCH_EMULATE_INSTR returns.");
482 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIORead, STAMTYPE_COUNTER, "/VMM/GCRet/IORead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_IOPORT_READ returns.");
483 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIOWrite, STAMTYPE_COUNTER, "/VMM/GCRet/IOWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_IOPORT_WRITE returns.");
484 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIOReadWrite, STAMTYPE_COUNTER, "/VMM/GCRet/IOReadWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_IOPORT_READWRITE returns.");
485 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIORead, STAMTYPE_COUNTER, "/VMM/GCRet/MMIORead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_READ returns.");
486 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOWrite, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_WRITE returns.");
487 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOReadWrite, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOReadWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_READ_WRITE returns.");
488 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOPatchRead, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOPatchRead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_PATCH_READ returns.");
489 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOPatchWrite, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOPatchWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_PATCH_WRITE returns.");
490 STAM_REG(pVM, &pVM->vmm.s.StatGCRetLDTFault, STAMTYPE_COUNTER, "/VMM/GCRet/LDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_GDT_FAULT returns.");
491 STAM_REG(pVM, &pVM->vmm.s.StatGCRetGDTFault, STAMTYPE_COUNTER, "/VMM/GCRet/GDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_LDT_FAULT returns.");
492 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIDTFault, STAMTYPE_COUNTER, "/VMM/GCRet/IDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_IDT_FAULT returns.");
493 STAM_REG(pVM, &pVM->vmm.s.StatGCRetTSSFault, STAMTYPE_COUNTER, "/VMM/GCRet/TSSFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_TSS_FAULT returns.");
494 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPDFault, STAMTYPE_COUNTER, "/VMM/GCRet/PDFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_PD_FAULT returns.");
495 STAM_REG(pVM, &pVM->vmm.s.StatGCRetCSAMTask, STAMTYPE_COUNTER, "/VMM/GCRet/CSAMTask", STAMUNIT_OCCURENCES, "Number of VINF_CSAM_PENDING_ACTION returns.");
496 STAM_REG(pVM, &pVM->vmm.s.StatGCRetSyncCR3, STAMTYPE_COUNTER, "/VMM/GCRet/SyncCR", STAMUNIT_OCCURENCES, "Number of VINF_PGM_SYNC_CR3 returns.");
497 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMisc, STAMTYPE_COUNTER, "/VMM/GCRet/Misc", STAMUNIT_OCCURENCES, "Number of misc returns.");
498 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchInt3, STAMTYPE_COUNTER, "/VMM/GCRet/PatchInt3", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_INT3 returns.");
499 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchPF, STAMTYPE_COUNTER, "/VMM/GCRet/PatchPF", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_TRAP_PF returns.");
500 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchGP, STAMTYPE_COUNTER, "/VMM/GCRet/PatchGP", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_TRAP_GP returns.");
501 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchIretIRQ, STAMTYPE_COUNTER, "/VMM/GCRet/PatchIret", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PENDING_IRQ_AFTER_IRET returns.");
502 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPageOverflow, STAMTYPE_COUNTER, "/VMM/GCRet/InvlpgOverflow", STAMUNIT_OCCURENCES, "Number of VERR_REM_FLUSHED_PAGES_OVERFLOW returns.");
503 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRescheduleREM, STAMTYPE_COUNTER, "/VMM/GCRet/ScheduleREM", STAMUNIT_OCCURENCES, "Number of VINF_EM_RESCHEDULE_REM returns.");
504 STAM_REG(pVM, &pVM->vmm.s.StatGCRetToR3, STAMTYPE_COUNTER, "/VMM/GCRet/ToR3", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TO_R3 returns.");
505 STAM_REG(pVM, &pVM->vmm.s.StatGCRetTimerPending, STAMTYPE_COUNTER, "/VMM/GCRet/TimerPending", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TIMER_PENDING returns.");
506 STAM_REG(pVM, &pVM->vmm.s.StatGCRetInterruptPending, STAMTYPE_COUNTER, "/VMM/GCRet/InterruptPending", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT_PENDING returns.");
507 STAM_REG(pVM, &pVM->vmm.s.StatGCRetCallHost, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/Misc", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
508 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMGrowRAM, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/GrowRAM", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
509 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPDMLock, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/PDMLock", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
510 STAM_REG(pVM, &pVM->vmm.s.StatGCRetLogFlush, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/LogFlush", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
511 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPDMQueueFlush, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/QueueFlush", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
512 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMPoolGrow, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/PGMPoolGrow",STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
513 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRemReplay, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/REMReplay", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
514 STAM_REG(pVM, &pVM->vmm.s.StatGCRetVMSetError, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/VMSetError", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
515 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMLock, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/PGMLock", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
516 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPATMDuplicateFn, STAMTYPE_COUNTER, "/VMM/GCRet/PATMDuplicateFn", STAMUNIT_OCCURENCES, "Number of VINF_PATM_DUPLICATE_FUNCTION returns.");
517 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMChangeMode, STAMTYPE_COUNTER, "/VMM/GCRet/PGMChangeMode", STAMUNIT_OCCURENCES, "Number of VINF_PGM_CHANGE_MODE returns.");
518 STAM_REG(pVM, &pVM->vmm.s.StatGCRetEmulHlt, STAMTYPE_COUNTER, "/VMM/GCRet/EmulHlt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_EMULATE_INSTR_HLT returns.");
519 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPendingRequest, STAMTYPE_COUNTER, "/VMM/GCRet/PendingRequest", STAMUNIT_OCCURENCES, "Number of VINF_EM_PENDING_REQUEST returns.");
520
521 return VINF_SUCCESS;
522 }
523 AssertRC(rc);
524 }
525 }
526 /** @todo: Need failure cleanup. */
527
528 //more todo in here?
529 //if (VBOX_SUCCESS(rc))
530 //{
531 //}
532 //int rc2 = vmmR3TermCoreCode(pVM);
533 //AssertRC(rc2));
534 }
535
536 return rc;
537}
538
539
540/**
541 * Ring-3 init finalizing.
542 *
543 * @returns VBox status code.
544 * @param pVM The VM handle.
545 */
546VMMR3DECL(int) VMMR3InitFinalize(PVM pVM)
547{
548#ifdef VBOX_STRICT_VMM_STACK
549 /*
550 * Two inaccessible pages at each sides of the stack to catch over/under-flows.
551 */
552 memset(pVM->vmm.s.pbHCStack - PAGE_SIZE, 0xcc, PAGE_SIZE);
553 PGMMapSetPage(pVM, MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack - PAGE_SIZE), PAGE_SIZE, 0);
554 RTMemProtect(pVM->vmm.s.pbHCStack - PAGE_SIZE, PAGE_SIZE, RTMEM_PROT_NONE);
555
556 memset(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE, 0xcc, PAGE_SIZE);
557 PGMMapSetPage(pVM, MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack + VMM_STACK_SIZE), PAGE_SIZE, 0);
558 RTMemProtect(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE, PAGE_SIZE, RTMEM_PROT_NONE);
559#endif
560
561 /*
562 * Set page attributes to r/w for stack pages.
563 */
564 int rc = PGMMapSetPage(pVM, pVM->vmm.s.pbGCStack, VMM_STACK_SIZE, X86_PTE_P | X86_PTE_A | X86_PTE_D | X86_PTE_RW);
565 AssertRC(rc);
566 if (VBOX_SUCCESS(rc))
567 {
568 /*
569 * Create the EMT yield timer.
570 */
571 rc = TMR3TimerCreateInternal(pVM, TMCLOCK_REAL, vmmR3YieldEMT, NULL, "EMT Yielder", &pVM->vmm.s.pYieldTimer);
572 if (VBOX_SUCCESS(rc))
573 rc = TMTimerSetMillies(pVM->vmm.s.pYieldTimer, pVM->vmm.s.cYieldEveryMillies);
574 }
575#ifdef VBOX_WITH_NMI
576 /*
577 * Map the host APIC into GC - This may be host os specific!
578 */
579 if (VBOX_SUCCESS(rc))
580 rc = PGMMap(pVM, pVM->vmm.s.GCPtrApicBase, 0xfee00000, PAGE_SIZE,
581 X86_PTE_P | X86_PTE_RW | X86_PTE_PWT | X86_PTE_PCD | X86_PTE_A | X86_PTE_D);
582#endif
583 return rc;
584}
585
586
587/**
588 * Initializes the R0 VMM.
589 *
590 * @returns VBox status code.
591 * @param pVM The VM to operate on.
592 */
593VMMR3DECL(int) VMMR3InitR0(PVM pVM)
594{
595 int rc;
596
597 /*
598 * Initialize the ring-0 logger if we haven't done so yet.
599 */
600 if ( pVM->vmm.s.pR0Logger
601 && !pVM->vmm.s.pR0Logger->fCreated)
602 {
603 rc = VMMR3UpdateLoggers(pVM);
604 if (VBOX_FAILURE(rc))
605 return rc;
606 }
607
608 /*
609 * Call Ring-0 entry with init code.
610 */
611 for (;;)
612 {
613#ifdef NO_SUPCALLR0VMM
614 //rc = VERR_GENERAL_FAILURE;
615 rc = VINF_SUCCESS;
616#else
617 rc = SUPCallVMMR0(pVM, VMMR0_DO_VMMR0_INIT, (void *)VBOX_VERSION);
618#endif
619 if ( pVM->vmm.s.pR0Logger
620 && pVM->vmm.s.pR0Logger->Logger.offScratch > 0)
621 RTLogFlushToLogger(&pVM->vmm.s.pR0Logger->Logger, NULL);
622 if (rc != VINF_VMM_CALL_HOST)
623 break;
624 rc = vmmR3ServiceCallHostRequest(pVM);
625 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
626 break;
627 break; // remove this when we do setjmp for all ring-0 stuff.
628 }
629
630 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
631 {
632 LogRel(("R0 init failed, rc=%Vra\n", rc));
633 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
634 rc = VERR_INTERNAL_ERROR;
635 }
636 return rc;
637}
638
639
640/**
641 * Initializes the GC VMM.
642 *
643 * @returns VBox status code.
644 * @param pVM The VM to operate on.
645 */
646VMMR3DECL(int) VMMR3InitGC(PVM pVM)
647{
648 /* In VMX mode, there's no need to init GC. */
649 if (pVM->vmm.s.fSwitcherDisabled)
650 return VINF_SUCCESS;
651
652 /*
653 * Call VMMGCInit():
654 * -# resolve the address.
655 * -# setup stackframe and EIP to use the trampoline.
656 * -# do a generic hypervisor call.
657 */
658 RTGCPTR GCPtrEP;
659 int rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &GCPtrEP);
660 if (VBOX_SUCCESS(rc))
661 {
662 CPUMHyperSetCtxCore(pVM, NULL);
663 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom); /* Clear the stack. */
664 CPUMPushHyper(pVM, VBOX_VERSION); /* Param 2: Version argument. */
665 CPUMPushHyper(pVM, VMMGC_DO_VMMGC_INIT); /* Param 1: Operation. */
666 CPUMPushHyper(pVM, pVM->pVMGC); /* Param 0: pVM */
667 CPUMPushHyper(pVM, 3 * sizeof(RTGCPTR)); /* trampoline param: stacksize. */
668 CPUMPushHyper(pVM, GCPtrEP); /* Call EIP. */
669 CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnGCCallTrampoline);
670
671 for (;;)
672 {
673#ifdef NO_SUPCALLR0VMM
674 //rc = VERR_GENERAL_FAILURE;
675 rc = VINF_SUCCESS;
676#else
677 rc = SUPCallVMMR0(pVM, VMMR0_DO_CALL_HYPERVISOR, NULL);
678#endif
679#ifdef LOG_ENABLED
680 PRTLOGGERGC pLogger = pVM->vmm.s.pLoggerHC;
681 if ( pLogger
682 && pLogger->offScratch > 0)
683 RTLogFlushGC(NULL, pLogger);
684#endif
685#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
686 PRTLOGGERGC pRelLogger = pVM->vmm.s.pRelLoggerHC;
687 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
688 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
689#endif
690 if (rc != VINF_VMM_CALL_HOST)
691 break;
692 rc = vmmR3ServiceCallHostRequest(pVM);
693 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
694 break;
695 }
696
697 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
698 {
699 VMMR3FatalDump(pVM, rc);
700 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
701 rc = VERR_INTERNAL_ERROR;
702 }
703 AssertRC(rc);
704 }
705 return rc;
706}
707
708
709/**
710 * Terminate the VMM bits.
711 *
712 * @returns VINF_SUCCESS.
713 * @param pVM The VM handle.
714 */
715VMMR3DECL(int) VMMR3Term(PVM pVM)
716{
717 /** @todo must call ring-0 so the logger thread instance can be properly removed. */
718
719#ifdef VBOX_STRICT_VMM_STACK
720 /*
721 * Make the two stack guard pages present again.
722 */
723 RTMemProtect(pVM->vmm.s.pbHCStack - PAGE_SIZE, PAGE_SIZE, RTMEM_PROT_READ | RTMEM_PROT_WRITE);
724 RTMemProtect(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE, PAGE_SIZE, RTMEM_PROT_READ | RTMEM_PROT_WRITE);
725#endif
726 return VINF_SUCCESS;
727}
728
729
730/**
731 * Applies relocations to data and code managed by this
732 * component. This function will be called at init and
733 * whenever the VMM need to relocate it self inside the GC.
734 *
735 * The VMM will need to apply relocations to the core code.
736 *
737 * @param pVM The VM handle.
738 * @param offDelta The relocation delta.
739 */
740VMMR3DECL(void) VMMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
741{
742 LogFlow(("VMMR3Relocate: offDelta=%VGv\n", offDelta));
743
744 /*
745 * Recalc the GC address.
746 */
747 pVM->vmm.s.pvGCCoreCode = MMHyperHC2GC(pVM, pVM->vmm.s.pvHCCoreCodeR3);
748
749 /*
750 * The stack.
751 */
752 CPUMSetHyperESP(pVM, CPUMGetHyperESP(pVM) + offDelta);
753 pVM->vmm.s.pbGCStack = MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack);
754 pVM->vmm.s.pbGCStackBottom = pVM->vmm.s.pbGCStack + VMM_STACK_SIZE;
755
756 /*
757 * All the switchers.
758 */
759 for (unsigned iSwitcher = 0; iSwitcher < ELEMENTS(s_apSwitchers); iSwitcher++)
760 {
761 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
762 if (pSwitcher && pSwitcher->pfnRelocate)
763 {
764 unsigned off = pVM->vmm.s.aoffSwitchers[iSwitcher];
765 pSwitcher->pfnRelocate(pVM,
766 pSwitcher,
767 (uint8_t *)pVM->vmm.s.pvHCCoreCodeR0 + off,
768 (uint8_t *)pVM->vmm.s.pvHCCoreCodeR3 + off,
769 pVM->vmm.s.pvGCCoreCode + off,
770 pVM->vmm.s.HCPhysCoreCode + off);
771 }
772 }
773
774 /*
775 * Recalc the GC address for the current switcher.
776 */
777 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[pVM->vmm.s.enmSwitcher];
778 RTGCPTR GCPtr = pVM->vmm.s.pvGCCoreCode + pVM->vmm.s.aoffSwitchers[pVM->vmm.s.enmSwitcher];
779 pVM->vmm.s.pfnGCGuestToHost = GCPtr + pSwitcher->offGCGuestToHost;
780 pVM->vmm.s.pfnGCCallTrampoline = GCPtr + pSwitcher->offGCCallTrampoline;
781 pVM->pfnVMMGCGuestToHostAsm = GCPtr + pSwitcher->offGCGuestToHostAsm;
782 pVM->pfnVMMGCGuestToHostAsmHyperCtx = GCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
783 pVM->pfnVMMGCGuestToHostAsmGuestCtx = GCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
784
785 /*
786 * Get other GC entry points.
787 */
788 int rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "CPUMGCResumeGuest", &pVM->vmm.s.pfnCPUMGCResumeGuest);
789 AssertReleaseMsgRC(rc, ("CPUMGCResumeGuest not found! rc=%Vra\n", rc));
790
791 rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "CPUMGCResumeGuestV86", &pVM->vmm.s.pfnCPUMGCResumeGuestV86);
792 AssertReleaseMsgRC(rc, ("CPUMGCResumeGuestV86 not found! rc=%Vra\n", rc));
793
794 /*
795 * Update the logger.
796 */
797 VMMR3UpdateLoggers(pVM);
798}
799
800
801/**
802 * Updates the settings for the GC and R0 loggers.
803 *
804 * @returns VBox status code.
805 * @param pVM The VM handle.
806 */
807VMMR3DECL(int) VMMR3UpdateLoggers(PVM pVM)
808{
809 /*
810 * Simply clone the logger instance (for GC).
811 */
812 int rc = VINF_SUCCESS;
813 RTGCPTR GCPtrLoggerFlush = 0;
814
815 if (pVM->vmm.s.pLoggerHC
816#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
817 || pVM->vmm.s.pRelLoggerHC
818#endif
819 )
820 {
821 rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCLoggerFlush", &GCPtrLoggerFlush);
822 AssertReleaseMsgRC(rc, ("vmmGCLoggerFlush not found! rc=%Vra\n", rc));
823 }
824
825 if (pVM->vmm.s.pLoggerHC)
826 {
827 RTGCPTR GCPtrLoggerWrapper = 0;
828 rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCLoggerWrapper", &GCPtrLoggerWrapper);
829 AssertReleaseMsgRC(rc, ("vmmGCLoggerWrapper not found! rc=%Vra\n", rc));
830 pVM->vmm.s.pLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pLoggerHC);
831 rc = RTLogCloneGC(NULL /* default */, pVM->vmm.s.pLoggerHC, pVM->vmm.s.cbLoggerGC,
832 GCPtrLoggerWrapper, GCPtrLoggerFlush, RTLOGFLAGS_BUFFERED);
833 AssertReleaseMsgRC(rc, ("RTLogCloneGC failed! rc=%Vra\n", rc));
834 }
835
836#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
837 if (pVM->vmm.s.pRelLoggerHC)
838 {
839 RTGCPTR GCPtrLoggerWrapper = 0;
840 rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCRelLoggerWrapper", &GCPtrLoggerWrapper);
841 AssertReleaseMsgRC(rc, ("vmmGCRelLoggerWrapper not found! rc=%Vra\n", rc));
842 pVM->vmm.s.pRelLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pRelLoggerHC);
843 rc = RTLogCloneGC(RTLogRelDefaultInstance(), pVM->vmm.s.pRelLoggerHC, pVM->vmm.s.cbRelLoggerGC,
844 GCPtrLoggerWrapper, GCPtrLoggerFlush, RTLOGFLAGS_BUFFERED);
845 AssertReleaseMsgRC(rc, ("RTLogCloneGC failed! rc=%Vra\n", rc));
846 }
847#endif /* VBOX_WITH_GC_AND_R0_RELEASE_LOG */
848
849 /*
850 * For the ring-0 EMT logger, we use a per-thread logger
851 * instance in ring-0. Only initialize it once.
852 */
853 PVMMR0LOGGER pR0Logger = pVM->vmm.s.pR0Logger;
854 if (pR0Logger)
855 {
856 if (!pR0Logger->fCreated)
857 {
858 RTHCPTR pfnLoggerWrapper = NULL;
859 rc = PDMR3GetSymbolR0(pVM, VMMR0_MAIN_MODULE_NAME, "vmmR0LoggerWrapper", &pfnLoggerWrapper);
860 AssertReleaseMsgRCReturn(rc, ("VMMLoggerWrapper not found! rc=%Vra\n", rc), rc);
861
862 RTHCPTR pfnLoggerFlush = NULL;
863 rc = PDMR3GetSymbolR0(pVM, VMMR0_MAIN_MODULE_NAME, "vmmR0LoggerFlush", &pfnLoggerFlush);
864 AssertReleaseMsgRCReturn(rc, ("VMMLoggerFlush not found! rc=%Vra\n", rc), rc);
865
866 rc = RTLogCreateForR0(&pR0Logger->Logger, pR0Logger->cbLogger,
867 *(PFNRTLOGGER *)&pfnLoggerWrapper, *(PFNRTLOGFLUSH *)&pfnLoggerFlush,
868 RTLOGFLAGS_BUFFERED, RTLOGDEST_DUMMY);
869 AssertReleaseMsgRCReturn(rc, ("RTLogCloneGC failed! rc=%Vra\n", rc), rc);
870 pR0Logger->fCreated = true;
871 }
872
873 rc = RTLogCopyGroupsAndFlags(&pR0Logger->Logger, NULL /* default */, RTLOGFLAGS_BUFFERED, 0);
874 AssertRC(rc);
875 }
876
877 return rc;
878}
879
880
881/**
882 * Generic switch code relocator.
883 *
884 * @param pVM The VM handle.
885 * @param pSwitcher The switcher definition.
886 * @param pu8CodeR3 Pointer to the core code block for the switcher, ring-3 mapping.
887 * @param pu8CodeR0 Pointer to the core code block for the switcher, ring-0 mapping.
888 * @param GCPtrCode The guest context address corresponding to pu8Code.
889 * @param u32IDCode The identity mapped (ID) address corresponding to pu8Code.
890 * @param SelCS The hypervisor CS selector.
891 * @param SelDS The hypervisor DS selector.
892 * @param SelTSS The hypervisor TSS selector.
893 * @param GCPtrGDT The GC address of the hypervisor GDT.
894 * @param SelCS64 The 64-bit mode hypervisor CS selector.
895 */
896static void vmmR3SwitcherGenericRelocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode,
897 RTSEL SelCS, RTSEL SelDS, RTSEL SelTSS, RTGCPTR GCPtrGDT, RTSEL SelCS64)
898{
899 union
900 {
901 const uint8_t *pu8;
902 const uint16_t *pu16;
903 const uint32_t *pu32;
904 const uint64_t *pu64;
905 const void *pv;
906 uintptr_t u;
907 } u;
908 u.pv = pSwitcher->pvFixups;
909
910 /*
911 * Process fixups.
912 */
913 uint8_t u8;
914 while ((u8 = *u.pu8++) != FIX_THE_END)
915 {
916 /*
917 * Get the source (where to write the fixup).
918 */
919 uint32_t offSrc = *u.pu32++;
920 Assert(offSrc < pSwitcher->cbCode);
921 union
922 {
923 uint8_t *pu8;
924 uint16_t *pu16;
925 uint32_t *pu32;
926 uint64_t *pu64;
927 uintptr_t u;
928 } uSrc;
929 uSrc.pu8 = pu8CodeR3 + offSrc;
930
931 /* The fixup target and method depends on the type. */
932 switch (u8)
933 {
934 /*
935 * 32-bit relative, source in HC and target in GC.
936 */
937 case FIX_HC_2_GC_NEAR_REL:
938 {
939 Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
940 uint32_t offTrg = *u.pu32++;
941 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
942 *uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (uSrc.u + 4));
943 break;
944 }
945
946 /*
947 * 32-bit relative, source in HC and target in ID.
948 */
949 case FIX_HC_2_ID_NEAR_REL:
950 {
951 Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
952 uint32_t offTrg = *u.pu32++;
953 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
954 *uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (uSrc.u + 4));
955 break;
956 }
957
958 /*
959 * 32-bit relative, source in GC and target in HC.
960 */
961 case FIX_GC_2_HC_NEAR_REL:
962 {
963 Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
964 uint32_t offTrg = *u.pu32++;
965 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
966 *uSrc.pu32 = (uint32_t)(((uintptr_t)pu8CodeR0 + offTrg) - (GCPtrCode + offSrc + 4));
967 break;
968 }
969
970 /*
971 * 32-bit relative, source in GC and target in ID.
972 */
973 case FIX_GC_2_ID_NEAR_REL:
974 {
975 Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
976 uint32_t offTrg = *u.pu32++;
977 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
978 *uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (GCPtrCode + offSrc + 4));
979 break;
980 }
981
982 /*
983 * 32-bit relative, source in ID and target in HC.
984 */
985 case FIX_ID_2_HC_NEAR_REL:
986 {
987 Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
988 uint32_t offTrg = *u.pu32++;
989 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
990 *uSrc.pu32 = (uint32_t)(((uintptr_t)pu8CodeR0 + offTrg) - (u32IDCode + offSrc + 4));
991 break;
992 }
993
994 /*
995 * 32-bit relative, source in ID and target in HC.
996 */
997 case FIX_ID_2_GC_NEAR_REL:
998 {
999 Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1000 uint32_t offTrg = *u.pu32++;
1001 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1002 *uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (u32IDCode + offSrc + 4));
1003 break;
1004 }
1005
1006 /*
1007 * 16:32 far jump, target in GC.
1008 */
1009 case FIX_GC_FAR32:
1010 {
1011 uint32_t offTrg = *u.pu32++;
1012 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1013 *uSrc.pu32++ = (uint32_t)(GCPtrCode + offTrg);
1014 *uSrc.pu16++ = SelCS;
1015 break;
1016 }
1017
1018 /*
1019 * Make 32-bit GC pointer given CPUM offset.
1020 */
1021 case FIX_GC_CPUM_OFF:
1022 {
1023 uint32_t offCPUM = *u.pu32++;
1024 Assert(offCPUM < sizeof(pVM->cpum));
1025 *uSrc.pu32 = (uint32_t)(VM_GUEST_ADDR(pVM, &pVM->cpum) + offCPUM);
1026 break;
1027 }
1028
1029 /*
1030 * Make 32-bit GC pointer given VM offset.
1031 */
1032 case FIX_GC_VM_OFF:
1033 {
1034 uint32_t offVM = *u.pu32++;
1035 Assert(offVM < sizeof(VM));
1036 *uSrc.pu32 = (uint32_t)(VM_GUEST_ADDR(pVM, pVM) + offVM);
1037 break;
1038 }
1039
1040 /*
1041 * Make 32-bit HC pointer given CPUM offset.
1042 */
1043 case FIX_HC_CPUM_OFF:
1044 {
1045 uint32_t offCPUM = *u.pu32++;
1046 Assert(offCPUM < sizeof(pVM->cpum));
1047 *uSrc.pu32 = (uint32_t)((uintptr_t)&pVM->cpum + offCPUM);
1048 break;
1049 }
1050
1051 /*
1052 * Make 32-bit HC pointer given VM offset.
1053 */
1054 case FIX_HC_VM_OFF:
1055 {
1056 uint32_t offVM = *u.pu32++;
1057 Assert(offVM < sizeof(VM));
1058 *uSrc.pu32 = (uint32_t)(uintptr_t)pVM + offVM;
1059 break;
1060 }
1061
1062 /*
1063 * Store the 32-Bit CR3 (32-bit) for the intermediate memory context.
1064 */
1065 case FIX_INTER_32BIT_CR3:
1066 {
1067
1068 *uSrc.pu32 = PGMGetInter32BitCR3(pVM);
1069 break;
1070 }
1071
1072 /*
1073 * Store the PAE CR3 (32-bit) for the intermediate memory context.
1074 */
1075 case FIX_INTER_PAE_CR3:
1076 {
1077
1078 *uSrc.pu32 = PGMGetInterPaeCR3(pVM);
1079 break;
1080 }
1081
1082 /*
1083 * Store the AMD64 CR3 (32-bit) for the intermediate memory context.
1084 */
1085 case FIX_INTER_AMD64_CR3:
1086 {
1087
1088 *uSrc.pu32 = PGMGetInterAmd64CR3(pVM);
1089 break;
1090 }
1091
1092 /*
1093 * Store the 32-Bit CR3 (32-bit) for the hypervisor (shadow) memory context.
1094 */
1095 case FIX_HYPER_32BIT_CR3:
1096 {
1097
1098 *uSrc.pu32 = PGMGetHyper32BitCR3(pVM);
1099 break;
1100 }
1101
1102 /*
1103 * Store the PAE CR3 (32-bit) for the hypervisor (shadow) memory context.
1104 */
1105 case FIX_HYPER_PAE_CR3:
1106 {
1107
1108 *uSrc.pu32 = PGMGetHyperPaeCR3(pVM);
1109 break;
1110 }
1111
1112 /*
1113 * Store the AMD64 CR3 (32-bit) for the hypervisor (shadow) memory context.
1114 */
1115 case FIX_HYPER_AMD64_CR3:
1116 {
1117
1118 *uSrc.pu32 = PGMGetHyperAmd64CR3(pVM);
1119 break;
1120 }
1121
1122 /*
1123 * Store Hypervisor CS (16-bit).
1124 */
1125 case FIX_HYPER_CS:
1126 {
1127 *uSrc.pu16 = SelCS;
1128 break;
1129 }
1130
1131 /*
1132 * Store Hypervisor DS (16-bit).
1133 */
1134 case FIX_HYPER_DS:
1135 {
1136 *uSrc.pu16 = SelDS;
1137 break;
1138 }
1139
1140 /*
1141 * Store Hypervisor TSS (16-bit).
1142 */
1143 case FIX_HYPER_TSS:
1144 {
1145 *uSrc.pu16 = SelTSS;
1146 break;
1147 }
1148
1149 /*
1150 * Store the 32-bit GC address of the 2nd dword of the TSS descriptor (in the GDT).
1151 */
1152 case FIX_GC_TSS_GDTE_DW2:
1153 {
1154 RTGCPTR GCPtr = GCPtrGDT + (SelTSS & ~7) + 4;
1155 *uSrc.pu32 = (uint32_t)GCPtr;
1156 break;
1157 }
1158
1159
1160 ///@todo case FIX_CR4_MASK:
1161 ///@todo case FIX_CR4_OSFSXR:
1162
1163 /*
1164 * Insert relative jump to specified target it FXSAVE/FXRSTOR isn't supported by the cpu.
1165 */
1166 case FIX_NO_FXSAVE_JMP:
1167 {
1168 uint32_t offTrg = *u.pu32++;
1169 Assert(offTrg < pSwitcher->cbCode);
1170 if (!CPUMSupportsFXSR(pVM))
1171 {
1172 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
1173 *uSrc.pu32++ = offTrg - (offSrc + 5);
1174 }
1175 else
1176 {
1177 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
1178 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
1179 }
1180 break;
1181 }
1182
1183 /*
1184 * Insert relative jump to specified target it SYSENTER isn't used by the host.
1185 */
1186 case FIX_NO_SYSENTER_JMP:
1187 {
1188 uint32_t offTrg = *u.pu32++;
1189 Assert(offTrg < pSwitcher->cbCode);
1190 if (!CPUMIsHostUsingSysEnter(pVM))
1191 {
1192 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
1193 *uSrc.pu32++ = offTrg - (offSrc + 5);
1194 }
1195 else
1196 {
1197 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
1198 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
1199 }
1200 break;
1201 }
1202
1203 /*
1204 * Insert relative jump to specified target it SYSENTER isn't used by the host.
1205 */
1206 case FIX_NO_SYSCALL_JMP:
1207 {
1208 uint32_t offTrg = *u.pu32++;
1209 Assert(offTrg < pSwitcher->cbCode);
1210 if (!CPUMIsHostUsingSysEnter(pVM))
1211 {
1212 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
1213 *uSrc.pu32++ = offTrg - (offSrc + 5);
1214 }
1215 else
1216 {
1217 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
1218 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
1219 }
1220 break;
1221 }
1222
1223#ifdef __AMD64__
1224 /*
1225 * 64-bit HC pointer fixup to (HC) target within the code (32-bit offset).
1226 */
1227 case FIX_HC_64BIT:
1228 {
1229 uint32_t offTrg = *u.pu32++;
1230 Assert(offSrc < pSwitcher->cbCode);
1231 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1232 *uSrc.pu64 = (uintptr_t)pu8CodeR0 + offTrg;
1233 break;
1234 }
1235
1236 /*
1237 * 64-bit HC pointer to the CPUM instance data (no argument).
1238 */
1239 case FIX_HC_64BIT_CPUM:
1240 {
1241 Assert(offSrc < pSwitcher->cbCode);
1242 *uSrc.pu64 = (uintptr_t)&pVM->cpum;
1243 break;
1244 }
1245#endif
1246
1247 /*
1248 * 32-bit ID pointer to (ID) target within the code (32-bit offset).
1249 */
1250 case FIX_ID_32BIT:
1251 {
1252 uint32_t offTrg = *u.pu32++;
1253 Assert(offSrc < pSwitcher->cbCode);
1254 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1255 *uSrc.pu32 = u32IDCode + offTrg;
1256 break;
1257 }
1258
1259 /*
1260 * 64-bit ID pointer to (ID) target within the code (32-bit offset).
1261 */
1262 case FIX_ID_64BIT:
1263 {
1264 uint32_t offTrg = *u.pu32++;
1265 Assert(offSrc < pSwitcher->cbCode);
1266 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1267 *uSrc.pu64 = u32IDCode + offTrg;
1268 break;
1269 }
1270
1271 /*
1272 * Far 16:32 ID pointer to 64-bit mode (ID) target within the code (32-bit offset).
1273 */
1274 case FIX_ID_FAR32_TO_64BIT_MODE:
1275 {
1276 uint32_t offTrg = *u.pu32++;
1277 Assert(offSrc < pSwitcher->cbCode);
1278 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1279 *uSrc.pu32++ = u32IDCode + offTrg;
1280 *uSrc.pu16 = SelCS64;
1281 AssertRelease(SelCS64);
1282 break;
1283 }
1284
1285#ifdef VBOX_WITH_NMI
1286 /*
1287 * 32-bit address to the APIC base.
1288 */
1289 case FIX_GC_APIC_BASE_32BIT:
1290 {
1291 *uSrc.pu32 = pVM->vmm.s.GCPtrApicBase;
1292 break;
1293 }
1294#endif
1295
1296 default:
1297 AssertReleaseMsgFailed(("Unknown fixup %d in switcher %s\n", u8, pSwitcher->pszDesc));
1298 break;
1299 }
1300 }
1301
1302#ifdef LOG_ENABLED
1303 /*
1304 * If Log2 is enabled disassemble the switcher code.
1305 *
1306 * The switcher code have 1-2 HC parts, 1 GC part and 0-2 ID parts.
1307 */
1308 if (LogIs2Enabled())
1309 {
1310 RTLogPrintf("*** Disassembly of switcher %d '%s' %#x bytes ***\n"
1311 " pu8CodeR0 = %p\n"
1312 " pu8CodeR3 = %p\n"
1313 " GCPtrCode = %VGv\n"
1314 " u32IDCode = %08x\n"
1315 " pVMGC = %VGv\n"
1316 " pCPUMGC = %VGv\n"
1317 " pVMHC = %p\n"
1318 " pCPUMHC = %p\n"
1319 " GCPtrGDT = %VGv\n"
1320 " InterCR3s = %08x, %08x, %08x (32-Bit, PAE, AMD64)\n"
1321 " HyperCR3s = %08x, %08x, %08x (32-Bit, PAE, AMD64)\n"
1322 " SelCS = %04x\n"
1323 " SelDS = %04x\n"
1324 " SelCS64 = %04x\n"
1325 " SelTSS = %04x\n",
1326 pSwitcher->enmType, pSwitcher->pszDesc, pSwitcher->cbCode,
1327 pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode, VM_GUEST_ADDR(pVM, pVM),
1328 VM_GUEST_ADDR(pVM, &pVM->cpum), pVM, &pVM->cpum,
1329 GCPtrGDT,
1330 PGMGetHyper32BitCR3(pVM), PGMGetHyperPaeCR3(pVM), PGMGetHyperAmd64CR3(pVM),
1331 PGMGetInter32BitCR3(pVM), PGMGetInterPaeCR3(pVM), PGMGetInterAmd64CR3(pVM),
1332 SelCS, SelDS, SelCS64, SelTSS);
1333
1334 uint32_t offCode = 0;
1335 while (offCode < pSwitcher->cbCode)
1336 {
1337 /*
1338 * Figure out where this is.
1339 */
1340 const char *pszDesc = NULL;
1341 RTUINTPTR uBase;
1342 uint32_t cbCode;
1343 if (offCode - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0)
1344 {
1345 pszDesc = "HCCode0";
1346 uBase = (RTUINTPTR)pu8CodeR0;
1347 offCode = pSwitcher->offHCCode0;
1348 cbCode = pSwitcher->cbHCCode0;
1349 }
1350 else if (offCode - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1)
1351 {
1352 pszDesc = "HCCode1";
1353 uBase = (RTUINTPTR)pu8CodeR0;
1354 offCode = pSwitcher->offHCCode1;
1355 cbCode = pSwitcher->cbHCCode1;
1356 }
1357 else if (offCode - pSwitcher->offGCCode < pSwitcher->cbGCCode)
1358 {
1359 pszDesc = "GCCode";
1360 uBase = GCPtrCode;
1361 offCode = pSwitcher->offGCCode;
1362 cbCode = pSwitcher->cbGCCode;
1363 }
1364 else if (offCode - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0)
1365 {
1366 pszDesc = "IDCode0";
1367 uBase = u32IDCode;
1368 offCode = pSwitcher->offIDCode0;
1369 cbCode = pSwitcher->cbIDCode0;
1370 }
1371 else if (offCode - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1)
1372 {
1373 pszDesc = "IDCode1";
1374 uBase = u32IDCode;
1375 offCode = pSwitcher->offIDCode1;
1376 cbCode = pSwitcher->cbIDCode1;
1377 }
1378 else
1379 {
1380 RTLogPrintf(" %04x: %02x '%c' (nowhere)\n",
1381 offCode, pu8CodeR3[offCode], isprint(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
1382 offCode++;
1383 continue;
1384 }
1385
1386 /*
1387 * Disassemble it.
1388 */
1389 RTLogPrintf(" %s: offCode=%#x cbCode=%#x\n", pszDesc, offCode, cbCode);
1390 DISCPUSTATE Cpu = {0};
1391 Cpu.mode = CPUMODE_32BIT;
1392 while (cbCode > 0)
1393 {
1394 /* try label it */
1395 if (pSwitcher->offR0HostToGuest == offCode)
1396 RTLogPrintf(" *R0HostToGuest:\n");
1397 if (pSwitcher->offGCGuestToHost == offCode)
1398 RTLogPrintf(" *GCGuestToHost:\n");
1399 if (pSwitcher->offGCCallTrampoline == offCode)
1400 RTLogPrintf(" *GCCallTrampoline:\n");
1401 if (pSwitcher->offGCGuestToHostAsm == offCode)
1402 RTLogPrintf(" *GCGuestToHostAsm:\n");
1403 if (pSwitcher->offGCGuestToHostAsmHyperCtx == offCode)
1404 RTLogPrintf(" *GCGuestToHostAsmHyperCtx:\n");
1405 if (pSwitcher->offGCGuestToHostAsmGuestCtx == offCode)
1406 RTLogPrintf(" *GCGuestToHostAsmGuestCtx:\n");
1407
1408 /* disas */
1409 uint32_t cbInstr = 0;
1410 char szDisas[256];
1411 if (DISInstr(&Cpu, (RTUINTPTR)pu8CodeR3 + offCode, uBase - (RTUINTPTR)pu8CodeR3, &cbInstr, szDisas))
1412 RTLogPrintf(" %04x: %s", offCode, szDisas); //for whatever reason szDisas includes '\n'.
1413 else
1414 {
1415 RTLogPrintf(" %04x: %02x '%c'\n",
1416 offCode, pu8CodeR3[offCode], isprint(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
1417 cbInstr = 1;
1418 }
1419 offCode += cbInstr;
1420 cbCode -= RT_MIN(cbInstr, cbCode);
1421 }
1422 }
1423 }
1424#endif
1425}
1426
1427
1428/**
1429 * Relocator for the 32-Bit to 32-Bit world switcher.
1430 */
1431DECLCALLBACK(void) vmmR3Switcher32BitTo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1432{
1433 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1434 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1435}
1436
1437
1438/**
1439 * Relocator for the 32-Bit to PAE world switcher.
1440 */
1441DECLCALLBACK(void) vmmR3Switcher32BitToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1442{
1443 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1444 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1445}
1446
1447
1448/**
1449 * Relocator for the PAE to 32-Bit world switcher.
1450 */
1451DECLCALLBACK(void) vmmR3SwitcherPAETo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1452{
1453 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1454 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1455}
1456
1457
1458/**
1459 * Relocator for the PAE to PAE world switcher.
1460 */
1461DECLCALLBACK(void) vmmR3SwitcherPAEToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1462{
1463 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1464 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1465}
1466
1467
1468/**
1469 * Relocator for the AMD64 to PAE world switcher.
1470 */
1471DECLCALLBACK(void) vmmR3SwitcherAMD64ToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1472{
1473 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1474 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
1475}
1476
1477
1478/**
1479 * Gets the pointer to g_szRTAssertMsg1 in GC.
1480 * @returns Pointer to VMMGC::g_szRTAssertMsg1.
1481 * Returns NULL if not present.
1482 * @param pVM The VM handle.
1483 */
1484VMMR3DECL(const char *) VMMR3GetGCAssertMsg1(PVM pVM)
1485{
1486 RTGCPTR GCPtr;
1487 int rc = PDMR3GetSymbolGC(pVM, NULL, "g_szRTAssertMsg1", &GCPtr);
1488 if (VBOX_SUCCESS(rc))
1489 return (const char *)MMHyperGC2HC(pVM, GCPtr);
1490 return NULL;
1491}
1492
1493
1494/**
1495 * Gets the pointer to g_szRTAssertMsg2 in GC.
1496 * @returns Pointer to VMMGC::g_szRTAssertMsg2.
1497 * Returns NULL if not present.
1498 * @param pVM The VM handle.
1499 */
1500VMMR3DECL(const char *) VMMR3GetGCAssertMsg2(PVM pVM)
1501{
1502 RTGCPTR GCPtr;
1503 int rc = PDMR3GetSymbolGC(pVM, NULL, "g_szRTAssertMsg2", &GCPtr);
1504 if (VBOX_SUCCESS(rc))
1505 return (const char *)MMHyperGC2HC(pVM, GCPtr);
1506 return NULL;
1507}
1508
1509
1510/**
1511 * Execute state save operation.
1512 *
1513 * @returns VBox status code.
1514 * @param pVM VM Handle.
1515 * @param pSSM SSM operation handle.
1516 */
1517static DECLCALLBACK(int) vmmR3Save(PVM pVM, PSSMHANDLE pSSM)
1518{
1519 LogFlow(("vmmR3Save:\n"));
1520
1521 /*
1522 * The hypervisor stack.
1523 */
1524 SSMR3PutGCPtr(pSSM, pVM->vmm.s.pbGCStackBottom);
1525 RTGCPTR GCPtrESP = CPUMGetHyperESP(pVM);
1526 Assert(pVM->vmm.s.pbGCStackBottom - GCPtrESP <= VMM_STACK_SIZE);
1527 SSMR3PutGCPtr(pSSM, GCPtrESP);
1528 SSMR3PutMem(pSSM, pVM->vmm.s.pbHCStack, VMM_STACK_SIZE);
1529 return SSMR3PutU32(pSSM, ~0); /* terminator */
1530}
1531
1532
1533/**
1534 * Execute state load operation.
1535 *
1536 * @returns VBox status code.
1537 * @param pVM VM Handle.
1538 * @param pSSM SSM operation handle.
1539 * @param u32Version Data layout version.
1540 */
1541static DECLCALLBACK(int) vmmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
1542{
1543 LogFlow(("vmmR3Load:\n"));
1544
1545 /*
1546 * Validate version.
1547 */
1548 if (u32Version != VMM_SAVED_STATE_VERSION)
1549 {
1550 Log(("vmmR3Load: Invalid version u32Version=%d!\n", u32Version));
1551 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1552 }
1553
1554 /*
1555 * Check that the stack is in the same place, or that it's fearly empty.
1556 */
1557 RTGCPTR GCPtrStackBottom;
1558 SSMR3GetGCPtr(pSSM, &GCPtrStackBottom);
1559 RTGCPTR GCPtrESP;
1560 int rc = SSMR3GetGCPtr(pSSM, &GCPtrESP);
1561 if (VBOX_FAILURE(rc))
1562 return rc;
1563 if ( GCPtrStackBottom == pVM->vmm.s.pbGCStackBottom
1564 || (GCPtrStackBottom - GCPtrESP < 32)) /** @todo This will break if we start preemting the hypervisor. */
1565 {
1566 /*
1567 * We *must* set the ESP because the CPUM load + PGM load relocations will render
1568 * the ESP in CPUM fatally invalid.
1569 */
1570 CPUMSetHyperESP(pVM, GCPtrESP);
1571
1572 /* restore the stack. */
1573 SSMR3GetMem(pSSM, pVM->vmm.s.pbHCStack, VMM_STACK_SIZE);
1574
1575 /* terminator */
1576 uint32_t u32;
1577 rc = SSMR3GetU32(pSSM, &u32);
1578 if (VBOX_FAILURE(rc))
1579 return rc;
1580 if (u32 != ~0U)
1581 {
1582 AssertMsgFailed(("u32=%#x\n", u32));
1583 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1584 }
1585 return VINF_SUCCESS;
1586 }
1587
1588 LogRel(("The stack is not in the same place and it's not empty! GCPtrStackBottom=%VGv pbGCStackBottom=%VGv ESP=%VGv\n",
1589 GCPtrStackBottom, pVM->vmm.s.pbGCStackBottom, GCPtrESP));
1590 AssertFailed();
1591 return VERR_SSM_LOAD_CONFIG_MISMATCH;
1592}
1593
1594
1595/**
1596 * Selects the switcher to be used for switching to GC.
1597 *
1598 * @returns VBox status code.
1599 * @param pVM VM handle.
1600 * @param enmSwitcher The new switcher.
1601 * @remark This function may be called before the VMM is initialized.
1602 */
1603VMMR3DECL(int) VMMR3SelectSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
1604{
1605 /*
1606 * Validate input.
1607 */
1608 if ( enmSwitcher < VMMSWITCHER_INVALID
1609 || enmSwitcher >= VMMSWITCHER_MAX)
1610 {
1611 AssertMsgFailed(("Invalid input enmSwitcher=%d\n", enmSwitcher));
1612 return VERR_INVALID_PARAMETER;
1613 }
1614
1615 /*
1616 * Select the new switcher.
1617 */
1618 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[enmSwitcher];
1619 if (pSwitcher)
1620 {
1621 Log(("VMMR3SelectSwitcher: enmSwitcher %d -> %d %s\n", pVM->vmm.s.enmSwitcher, enmSwitcher, pSwitcher->pszDesc));
1622 pVM->vmm.s.enmSwitcher = enmSwitcher;
1623
1624 RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvHCCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher]; /** @todo fix the pvHCCoreCodeR0 type */
1625 pVM->vmm.s.pfnR0HostToGuest = pbCodeR0 + pSwitcher->offR0HostToGuest;
1626
1627 RTGCPTR GCPtr = pVM->vmm.s.pvGCCoreCode + pVM->vmm.s.aoffSwitchers[enmSwitcher];
1628 pVM->vmm.s.pfnGCGuestToHost = GCPtr + pSwitcher->offGCGuestToHost;
1629 pVM->vmm.s.pfnGCCallTrampoline = GCPtr + pSwitcher->offGCCallTrampoline;
1630 pVM->pfnVMMGCGuestToHostAsm = GCPtr + pSwitcher->offGCGuestToHostAsm;
1631 pVM->pfnVMMGCGuestToHostAsmHyperCtx = GCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
1632 pVM->pfnVMMGCGuestToHostAsmGuestCtx = GCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
1633 return VINF_SUCCESS;
1634 }
1635 return VERR_NOT_IMPLEMENTED;
1636}
1637
1638/**
1639 * Disable the switcher logic permanently.
1640 *
1641 * @returns VBox status code.
1642 * @param pVM VM handle.
1643 */
1644VMMR3DECL(int) VMMR3DisableSwitcher(PVM pVM)
1645{
1646/** @todo r=bird: I would suggest that we create a dummy switcher which just does something like:
1647 * @code
1648 * mov eax, VERR_INTERNAL_ERROR
1649 * ret
1650 * @endcode
1651 * And then check for fSwitcherDisabled in VMMR3SelectSwitcher() in order to prevent it from being removed.
1652 */
1653 pVM->vmm.s.fSwitcherDisabled = true;
1654 return VINF_SUCCESS;
1655}
1656
1657
1658/**
1659 * Resolve a builtin GC symbol.
1660 * Called by PDM when loading or relocating GC modules.
1661 *
1662 * @returns VBox status
1663 * @param pVM VM Handle.
1664 * @param pszSymbol Symbol to resolv
1665 * @param pGCPtrValue Where to store the symbol value.
1666 * @remark This has to work before VMMR3Relocate() is called.
1667 */
1668VMMR3DECL(int) VMMR3GetImportGC(PVM pVM, const char *pszSymbol, PRTGCPTR pGCPtrValue)
1669{
1670 if (!strcmp(pszSymbol, "g_Logger"))
1671 {
1672 if (pVM->vmm.s.pLoggerHC)
1673 pVM->vmm.s.pLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pLoggerHC);
1674 *pGCPtrValue = pVM->vmm.s.pLoggerGC;
1675 }
1676 else if (!strcmp(pszSymbol, "g_RelLogger"))
1677 {
1678#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
1679 if (pVM->vmm.s.pRelLoggerHC)
1680 pVM->vmm.s.pRelLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pRelLoggerHC);
1681 *pGCPtrValue = pVM->vmm.s.pRelLoggerGC;
1682#else
1683 *pGCPtrValue = NIL_RTGCPTR;
1684#endif
1685 }
1686 else
1687 return VERR_SYMBOL_NOT_FOUND;
1688 return VINF_SUCCESS;
1689}
1690
1691
1692/**
1693 * Suspends the the CPU yielder.
1694 *
1695 * @param pVM The VM handle.
1696 */
1697VMMR3DECL(void) VMMR3YieldSuspend(PVM pVM)
1698{
1699 if (!pVM->vmm.s.cYieldResumeMillies)
1700 {
1701 uint64_t u64Now = TMTimerGet(pVM->vmm.s.pYieldTimer);
1702 uint64_t u64Expire = TMTimerGetExpire(pVM->vmm.s.pYieldTimer);
1703 if (u64Now >= u64Expire || u64Expire == ~(uint64_t)0)
1704 pVM->vmm.s.cYieldResumeMillies = pVM->vmm.s.cYieldEveryMillies;
1705 else
1706 pVM->vmm.s.cYieldResumeMillies = TMTimerToMilli(pVM->vmm.s.pYieldTimer, u64Expire - u64Now);
1707 TMTimerStop(pVM->vmm.s.pYieldTimer);
1708 }
1709}
1710
1711
1712/**
1713 * Stops the the CPU yielder.
1714 *
1715 * @param pVM The VM handle.
1716 */
1717VMMR3DECL(void) VMMR3YieldStop(PVM pVM)
1718{
1719 if (!pVM->vmm.s.cYieldResumeMillies)
1720 TMTimerStop(pVM->vmm.s.pYieldTimer);
1721 pVM->vmm.s.cYieldResumeMillies = pVM->vmm.s.cYieldEveryMillies;
1722}
1723
1724
1725/**
1726 * Resumes the CPU yielder when it has been a suspended or stopped.
1727 *
1728 * @param pVM The VM handle.
1729 */
1730VMMR3DECL(void) VMMR3YieldResume(PVM pVM)
1731{
1732 if (pVM->vmm.s.cYieldResumeMillies)
1733 {
1734 TMTimerSetMillies(pVM->vmm.s.pYieldTimer, pVM->vmm.s.cYieldResumeMillies);
1735 pVM->vmm.s.cYieldResumeMillies = 0;
1736 }
1737}
1738
1739
1740/**
1741 * Internal timer callback function.
1742 *
1743 * @param pVM The VM.
1744 * @param pTimer The timer handle.
1745 * @param pvUser User argument specified upon timer creation.
1746 */
1747static DECLCALLBACK(void) vmmR3YieldEMT(PVM pVM, PTMTIMER pTimer, void *pvUser)
1748{
1749#ifdef LOG_ENABLED
1750 uint64_t u64Elapsed = RTTimeNanoTS();
1751#endif
1752 RTThreadYield();
1753 TMTimerSetMillies(pTimer, pVM->vmm.s.cYieldEveryMillies);
1754 Log(("vmmR3YieldEMT: %RI64 ns\n", RTTimeNanoTS() - u64Elapsed));
1755}
1756
1757
1758/**
1759 * Acquire global VM lock.
1760 *
1761 * @returns VBox status code
1762 * @param pVM The VM to operate on.
1763 */
1764VMMR3DECL(int) VMMR3Lock(PVM pVM)
1765{
1766 return RTCritSectEnter(&pVM->vmm.s.CritSectVMLock);
1767}
1768
1769
1770/**
1771 * Release global VM lock.
1772 *
1773 * @returns VBox status code
1774 * @param pVM The VM to operate on.
1775 */
1776VMMR3DECL(int) VMMR3Unlock(PVM pVM)
1777{
1778 return RTCritSectLeave(&pVM->vmm.s.CritSectVMLock);
1779}
1780
1781
1782/**
1783 * Return global VM lock owner.
1784 *
1785 * @returns Thread id of owner.
1786 * @returns NIL_RTTHREAD if no owner.
1787 * @param pVM The VM to operate on.
1788 */
1789VMMR3DECL(RTNATIVETHREAD) VMMR3LockGetOwner(PVM pVM)
1790{
1791 return RTCritSectGetOwner(&pVM->vmm.s.CritSectVMLock);
1792}
1793
1794
1795/**
1796 * Checks if the current thread is the owner of the global VM lock.
1797 *
1798 * @returns true if owner.
1799 * @returns false if not owner.
1800 * @param pVM The VM to operate on.
1801 */
1802VMMR3DECL(bool) VMMR3LockIsOwner(PVM pVM)
1803{
1804 return RTCritSectIsOwner(&pVM->vmm.s.CritSectVMLock);
1805}
1806
1807
1808/**
1809 * Executes guest code.
1810 *
1811 * @param pVM VM handle.
1812 */
1813VMMR3DECL(int) VMMR3RawRunGC(PVM pVM)
1814{
1815 Log2(("VMMR3RawRunGC: (cs:eip=%04x:%08x)\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1816
1817 /*
1818 * Set the EIP and ESP.
1819 */
1820 CPUMSetHyperEIP(pVM, CPUMGetGuestEFlags(pVM) & X86_EFL_VM
1821 ? pVM->vmm.s.pfnCPUMGCResumeGuestV86
1822 : pVM->vmm.s.pfnCPUMGCResumeGuest);
1823 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom);
1824
1825 /*
1826 * We hide log flushes (outer) and hypervisor interrupts (inner).
1827 */
1828 for (;;)
1829 {
1830 int rc;
1831 do
1832 {
1833#ifdef NO_SUPCALLR0VMM
1834 rc = VERR_GENERAL_FAILURE;
1835#else
1836 rc = SUPCallVMMR0(pVM, VMMR0_DO_RAW_RUN, NULL);
1837#endif
1838 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
1839
1840 /*
1841 * Flush the logs.
1842 */
1843#ifdef LOG_ENABLED
1844 PRTLOGGERGC pLogger = pVM->vmm.s.pLoggerHC;
1845 if ( pLogger
1846 && pLogger->offScratch > 0)
1847 RTLogFlushGC(NULL, pLogger);
1848#endif
1849#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
1850 PRTLOGGERGC pRelLogger = pVM->vmm.s.pRelLoggerHC;
1851 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
1852 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
1853#endif
1854 if (rc != VINF_VMM_CALL_HOST)
1855 {
1856 Log2(("VMMR3RawRunGC: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1857 return rc;
1858 }
1859 rc = vmmR3ServiceCallHostRequest(pVM);
1860 if (VBOX_FAILURE(rc))
1861 return rc;
1862 /* Resume GC */
1863 }
1864}
1865
1866
1867/**
1868 * Executes guest code (Intel VMX and AMD SVM).
1869 *
1870 * @param pVM VM handle.
1871 */
1872VMMR3DECL(int) VMMR3HwAccRunGC(PVM pVM)
1873{
1874 Log2(("VMMR3HwAccRunGC: (cs:eip=%04x:%08x)\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1875
1876 for (;;)
1877 {
1878 int rc;
1879 do
1880 {
1881#ifdef NO_SUPCALLR0VMM
1882 rc = VERR_GENERAL_FAILURE;
1883#else
1884 rc = SUPCallVMMR0(pVM, VMMR0_DO_HWACC_RUN, NULL);
1885#endif
1886 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
1887
1888#ifdef LOG_ENABLED
1889 /*
1890 * Flush the log
1891 */
1892 PVMMR0LOGGER pR0Logger = pVM->vmm.s.pR0Logger;
1893 if ( pR0Logger
1894 && pR0Logger->Logger.offScratch > 0)
1895 RTLogFlushToLogger(&pR0Logger->Logger, NULL);
1896#endif /* !LOG_ENABLED */
1897 if (rc != VINF_VMM_CALL_HOST)
1898 {
1899 Log2(("VMMR3HwAccRunGC: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1900 return rc;
1901 }
1902 rc = vmmR3ServiceCallHostRequest(pVM);
1903 if (VBOX_FAILURE(rc))
1904 return rc;
1905 /* Resume R0 */
1906 }
1907}
1908
1909/**
1910 * Calls GC a function.
1911 *
1912 * @param pVM The VM handle.
1913 * @param GCPtrEntry The GC function address.
1914 * @param cArgs The number of arguments in the ....
1915 * @param ... Arguments to the function.
1916 */
1917VMMR3DECL(int) VMMR3CallGC(PVM pVM, RTGCPTR GCPtrEntry, unsigned cArgs, ...)
1918{
1919 va_list args;
1920 va_start(args, cArgs);
1921 int rc = VMMR3CallGCV(pVM, GCPtrEntry, cArgs, args);
1922 va_end(args);
1923 return rc;
1924}
1925
1926
1927/**
1928 * Calls GC a function.
1929 *
1930 * @param pVM The VM handle.
1931 * @param GCPtrEntry The GC function address.
1932 * @param cArgs The number of arguments in the ....
1933 * @param args Arguments to the function.
1934 */
1935VMMR3DECL(int) VMMR3CallGCV(PVM pVM, RTGCPTR GCPtrEntry, unsigned cArgs, va_list args)
1936{
1937 Log2(("VMMR3CallGCV: GCPtrEntry=%VGv cArgs=%d\n", GCPtrEntry, cArgs));
1938
1939 /*
1940 * Setup the call frame using the trampoline.
1941 */
1942 CPUMHyperSetCtxCore(pVM, NULL);
1943 memset(pVM->vmm.s.pbHCStack, 0xaa, VMM_STACK_SIZE); /* Clear the stack. */
1944 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom - cArgs * sizeof(RTGCUINTPTR));
1945 PRTGCUINTPTR pFrame = (PRTGCUINTPTR)(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE) - cArgs;
1946 int i = cArgs;
1947 while (i-- > 0)
1948 *pFrame++ = va_arg(args, RTGCUINTPTR);
1949
1950 CPUMPushHyper(pVM, cArgs * sizeof(RTGCUINTPTR)); /* stack frame size */
1951 CPUMPushHyper(pVM, GCPtrEntry); /* what to call */
1952 CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnGCCallTrampoline);
1953
1954 /*
1955 * We hide log flushes (outer) and hypervisor interrupts (inner).
1956 */
1957 for (;;)
1958 {
1959 int rc;
1960 do
1961 {
1962#ifdef NO_SUPCALLR0VMM
1963 rc = VERR_GENERAL_FAILURE;
1964#else
1965 rc = SUPCallVMMR0(pVM, VMMR0_DO_RAW_RUN, NULL);
1966#endif
1967 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
1968
1969 /*
1970 * Flush the logs.
1971 */
1972#ifdef LOG_ENABLED
1973 PRTLOGGERGC pLogger = pVM->vmm.s.pLoggerHC;
1974 if ( pLogger
1975 && pLogger->offScratch > 0)
1976 RTLogFlushGC(NULL, pLogger);
1977#endif
1978#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
1979 PRTLOGGERGC pRelLogger = pVM->vmm.s.pRelLoggerHC;
1980 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
1981 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
1982#endif
1983 if (rc == VERR_TRPM_PANIC || rc == VERR_TRPM_DONT_PANIC)
1984 VMMR3FatalDump(pVM, rc);
1985 if (rc != VINF_VMM_CALL_HOST)
1986 {
1987 Log2(("VMMR3CallGCV: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1988 return rc;
1989 }
1990 rc = vmmR3ServiceCallHostRequest(pVM);
1991 if (VBOX_FAILURE(rc))
1992 return rc;
1993 }
1994}
1995
1996
1997/**
1998 * Resumes executing hypervisor code when interrupted
1999 * by a queue flush or a debug event.
2000 *
2001 * @returns VBox status code.
2002 * @param pVM VM handle.
2003 */
2004VMMR3DECL(int) VMMR3ResumeHyper(PVM pVM)
2005{
2006 Log(("VMMR3ResumeHyper: eip=%VGv esp=%VGv\n", CPUMGetHyperEIP(pVM), CPUMGetHyperESP(pVM)));
2007
2008 /*
2009 * We hide log flushes (outer) and hypervisor interrupts (inner).
2010 */
2011 for (;;)
2012 {
2013 int rc;
2014 do
2015 {
2016#ifdef NO_SUPCALLR0VMM
2017 rc = VERR_GENERAL_FAILURE;
2018#else
2019 rc = SUPCallVMMR0(pVM, VMMR0_DO_RAW_RUN, NULL);
2020#endif
2021 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
2022
2023 /*
2024 * Flush the loggers,
2025 */
2026#ifdef LOG_ENABLED
2027 PRTLOGGERGC pLogger = pVM->vmm.s.pLoggerHC;
2028 if ( pLogger
2029 && pLogger->offScratch > 0)
2030 RTLogFlushGC(NULL, pLogger);
2031#endif
2032#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
2033 PRTLOGGERGC pRelLogger = pVM->vmm.s.pRelLoggerHC;
2034 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
2035 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
2036#endif
2037 if (rc == VERR_TRPM_PANIC || rc == VERR_TRPM_DONT_PANIC)
2038 VMMR3FatalDump(pVM, rc);
2039 if (rc != VINF_VMM_CALL_HOST)
2040 {
2041 Log(("VMMR3ResumeHyper: returns %Vrc\n", rc));
2042 return rc;
2043 }
2044 rc = vmmR3ServiceCallHostRequest(pVM);
2045 if (VBOX_FAILURE(rc))
2046 return rc;
2047 }
2048}
2049
2050
2051/**
2052 * Service a call to the ring-3 host code.
2053 *
2054 * @returns VBox status code.
2055 * @param pVM VM handle.
2056 * @remark Careful with critsects.
2057 */
2058static int vmmR3ServiceCallHostRequest(PVM pVM)
2059{
2060 switch (pVM->vmm.s.enmCallHostOperation)
2061 {
2062 /*
2063 * Acquire the PDM lock.
2064 */
2065 case VMMCALLHOST_PDM_LOCK:
2066 {
2067 pVM->vmm.s.rcCallHost = PDMR3LockCall(pVM);
2068 break;
2069 }
2070
2071 /*
2072 * Flush a PDM queue.
2073 */
2074 case VMMCALLHOST_PDM_QUEUE_FLUSH:
2075 {
2076 PDMR3QueueFlushWorker(pVM, NULL);
2077 pVM->vmm.s.rcCallHost = VINF_SUCCESS;
2078 break;
2079 }
2080
2081 /*
2082 * Grow the PGM pool.
2083 */
2084 case VMMCALLHOST_PGM_POOL_GROW:
2085 {
2086 pVM->vmm.s.rcCallHost = PGMR3PoolGrow(pVM);
2087 break;
2088 }
2089
2090 /*
2091 * Acquire the PGM lock.
2092 */
2093 case VMMCALLHOST_PGM_LOCK:
2094 {
2095 pVM->vmm.s.rcCallHost = PGMR3LockCall(pVM);
2096 break;
2097 }
2098
2099 /*
2100 * Flush REM handler notifications.
2101 */
2102 case VMMCALLHOST_REM_REPLAY_HANDLER_NOTIFICATIONS:
2103 {
2104 REMR3ReplayHandlerNotifications(pVM);
2105 break;
2106 }
2107
2108 case VMMCALLHOST_PGM_RAM_GROW_RANGE:
2109 {
2110 pVM->vmm.s.rcCallHost = PGM3PhysGrowRange(pVM, pVM->vmm.s.u64CallHostArg);
2111 break;
2112 }
2113
2114 /*
2115 * This is a noop. We just take this route to avoid unnecessary
2116 * tests in the loops.
2117 */
2118 case VMMCALLHOST_VMM_LOGGER_FLUSH:
2119 break;
2120
2121 /*
2122 * Set the VM error message.
2123 */
2124 case VMMCALLHOST_VM_SET_ERROR:
2125 VMR3SetErrorWorker(pVM);
2126 break;
2127
2128 /*
2129 * Set the VM runtime error message.
2130 */
2131 case VMMCALLHOST_VM_SET_RUNTIME_ERROR:
2132 VMR3SetRuntimeErrorWorker(pVM);
2133 break;
2134
2135 default:
2136 AssertMsgFailed(("enmCallHostOperation=%d\n", pVM->vmm.s.enmCallHostOperation));
2137 return VERR_INTERNAL_ERROR;
2138 }
2139
2140 pVM->vmm.s.enmCallHostOperation = VMMCALLHOST_INVALID;
2141 return VINF_SUCCESS;
2142}
2143
2144
2145
2146/**
2147 * Structure to pass to DBGFR3Info() and for doing all other
2148 * output during fatal dump.
2149 */
2150typedef struct VMMR3FATALDUMPINFOHLP
2151{
2152 /** The helper core. */
2153 DBGFINFOHLP Core;
2154 /** The release logger instance. */
2155 PRTLOGGER pRelLogger;
2156 /** The saved release logger flags. */
2157 RTUINT fRelLoggerFlags;
2158 /** The logger instance. */
2159 PRTLOGGER pLogger;
2160 /** The saved logger flags. */
2161 RTUINT fLoggerFlags;
2162 /** The saved logger destination flags. */
2163 RTUINT fLoggerDestFlags;
2164 /** Whether to output to stderr or not. */
2165 bool fStdErr;
2166} VMMR3FATALDUMPINFOHLP, *PVMMR3FATALDUMPINFOHLP;
2167typedef const VMMR3FATALDUMPINFOHLP *PCVMMR3FATALDUMPINFOHLP;
2168
2169
2170/**
2171 * Print formatted string.
2172 *
2173 * @param pHlp Pointer to this structure.
2174 * @param pszFormat The format string.
2175 * @param ... Arguments.
2176 */
2177static DECLCALLBACK(void) vmmR3FatalDumpInfoHlp_pfnPrintf(PCDBGFINFOHLP pHlp, const char *pszFormat, ...)
2178{
2179 va_list args;
2180 va_start(args, pszFormat);
2181 pHlp->pfnPrintfV(pHlp, pszFormat, args);
2182 va_end(args);
2183}
2184
2185
2186/**
2187 * Print formatted string.
2188 *
2189 * @param pHlp Pointer to this structure.
2190 * @param pszFormat The format string.
2191 * @param args Argument list.
2192 */
2193static DECLCALLBACK(void) vmmR3FatalDumpInfoHlp_pfnPrintfV(PCDBGFINFOHLP pHlp, const char *pszFormat, va_list args)
2194{
2195 PCVMMR3FATALDUMPINFOHLP pMyHlp = (PCVMMR3FATALDUMPINFOHLP)pHlp;
2196
2197 if (pMyHlp->pRelLogger)
2198 {
2199 va_list args2;
2200 va_copy(args2, args);
2201 RTLogLoggerV(pMyHlp->pRelLogger, pszFormat, args2);
2202 va_end(args2);
2203 }
2204 if (pMyHlp->pLogger)
2205 {
2206 va_list args2;
2207 va_copy(args2, args);
2208 RTLogLoggerV(pMyHlp->pLogger, pszFormat, args);
2209 va_end(args2);
2210 }
2211 if (pMyHlp->fStdErr)
2212 {
2213 va_list args2;
2214 va_copy(args2, args);
2215 RTStrmPrintfV(g_pStdErr, pszFormat, args);
2216 va_end(args2);
2217 }
2218}
2219
2220
2221/**
2222 * Initializes the fatal dump output helper.
2223 *
2224 * @param pHlp The structure to initialize.
2225 */
2226static void vmmR3FatalDumpInfoHlpInit(PVMMR3FATALDUMPINFOHLP pHlp)
2227{
2228 memset(pHlp, 0, sizeof(*pHlp));
2229
2230 pHlp->Core.pfnPrintf = vmmR3FatalDumpInfoHlp_pfnPrintf;
2231 pHlp->Core.pfnPrintfV = vmmR3FatalDumpInfoHlp_pfnPrintfV;
2232
2233 /*
2234 * The loggers.
2235 */
2236 pHlp->pRelLogger = RTLogRelDefaultInstance();
2237#ifndef LOG_ENABLED
2238 if (!pHlp->pRelLogger)
2239#endif
2240 pHlp->pLogger = RTLogDefaultInstance();
2241
2242 if (pHlp->pRelLogger)
2243 {
2244 pHlp->fRelLoggerFlags = pHlp->pRelLogger->fFlags;
2245 pHlp->pRelLogger->fFlags &= ~(RTLOGFLAGS_BUFFERED | RTLOGFLAGS_DISABLED);
2246 }
2247
2248 if (pHlp->pLogger)
2249 {
2250 pHlp->fLoggerFlags = pHlp->pLogger->fFlags;
2251 pHlp->fLoggerDestFlags = pHlp->pLogger->fDestFlags;
2252 pHlp->pLogger->fFlags &= ~(RTLOGFLAGS_BUFFERED | RTLOGFLAGS_DISABLED);
2253 pHlp->pLogger->fDestFlags |= RTLOGDEST_DEBUGGER;
2254 }
2255
2256 /*
2257 * Check if we need write to stderr.
2258 */
2259 pHlp->fStdErr = (!pHlp->pRelLogger || !(pHlp->pRelLogger->fDestFlags & (RTLOGDEST_STDOUT | RTLOGDEST_STDERR)))
2260 && (!pHlp->pLogger || !(pHlp->pLogger->fDestFlags & (RTLOGDEST_STDOUT | RTLOGDEST_STDERR)));
2261}
2262
2263
2264/**
2265 * Deletes the fatal dump output helper.
2266 *
2267 * @param pHlp The structure to delete.
2268 */
2269static void vmmR3FatalDumpInfoHlpDelete(PVMMR3FATALDUMPINFOHLP pHlp)
2270{
2271 if (pHlp->pRelLogger)
2272 {
2273 RTLogFlush(pHlp->pRelLogger);
2274 pHlp->pRelLogger->fFlags = pHlp->fRelLoggerFlags;
2275 }
2276
2277 if (pHlp->pLogger)
2278 {
2279 RTLogFlush(pHlp->pLogger);
2280 pHlp->pLogger->fFlags = pHlp->fLoggerFlags;
2281 pHlp->pLogger->fDestFlags = pHlp->fLoggerDestFlags;
2282 }
2283}
2284
2285
2286/**
2287 * Dumps the VM state on a fatal error.
2288 *
2289 * @param pVM VM Handle.
2290 * @param rcErr VBox status code.
2291 */
2292VMMR3DECL(void) VMMR3FatalDump(PVM pVM, int rcErr)
2293{
2294 /*
2295 * Create our output helper and sync it with the log settings.
2296 * This helper will be used for all the output.
2297 */
2298 VMMR3FATALDUMPINFOHLP Hlp;
2299 PCDBGFINFOHLP pHlp = &Hlp.Core;
2300 vmmR3FatalDumpInfoHlpInit(&Hlp);
2301
2302 /*
2303 * Header.
2304 */
2305 pHlp->pfnPrintf(pHlp,
2306 "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n"
2307 "!!\n"
2308 "!! Guru Meditation %d (%Vrc)\n"
2309 "!!\n",
2310 rcErr, rcErr);
2311
2312 /*
2313 * Continue according to context.
2314 */
2315 bool fDoneHyper = false;
2316 switch (rcErr)
2317 {
2318 /*
2319 * Hyper visor errors.
2320 */
2321 case VINF_EM_DBG_HYPER_ASSERTION:
2322 pHlp->pfnPrintf(pHlp, "%s%s!!\n", VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
2323 /* fall thru */
2324 case VERR_TRPM_DONT_PANIC:
2325 case VERR_TRPM_PANIC:
2326 case VINF_EM_RAW_STALE_SELECTOR:
2327 case VINF_EM_RAW_IRET_TRAP:
2328 case VINF_EM_DBG_HYPER_BREAKPOINT:
2329 case VINF_EM_DBG_HYPER_STEPPED:
2330 {
2331 /* Trap? */
2332 uint32_t uEIP = CPUMGetHyperEIP(pVM);
2333 bool fSoftwareInterrupt = false;
2334 uint8_t u8TrapNo = 0xce;
2335 RTGCUINT uErrorCode = 0xdeadface;
2336 RTGCUINTPTR uCR2 = 0xdeadface;
2337 int rc2 = TRPMQueryTrapAll(pVM, &u8TrapNo, &fSoftwareInterrupt, &uErrorCode, &uCR2);
2338 if (VBOX_SUCCESS(rc2))
2339 pHlp->pfnPrintf(pHlp,
2340 "!! TRAP=%02x ERRCD=%VGv CR2=%VGv EIP=%VGv fSoft=%d\n",
2341 u8TrapNo, uErrorCode, uCR2, uEIP, fSoftwareInterrupt);
2342 else
2343 pHlp->pfnPrintf(pHlp,
2344 "!! EIP=%VGv NOTRAP\n",
2345 uEIP);
2346
2347 /*
2348 * Try figure out where eip is.
2349 */
2350 /** @todo make query call for core code or move this function to VMM. */
2351 /* core code? */
2352 //if (uEIP - (RTGCUINTPTR)pVM->vmm.s.pvGCCoreCode < pVM->vmm.s.cbCoreCode)
2353 // pHlp->pfnPrintf(pHlp,
2354 // "!! EIP is in CoreCode, offset %#x\n",
2355 // uEIP - (RTGCUINTPTR)pVM->vmm.s.pvGCCoreCode);
2356 //else
2357 { /* ask PDM */
2358 /** @todo ask DBGFR3Sym later. */
2359 char szModName[64];
2360 RTGCPTR GCPtrMod;
2361 char szNearSym1[260];
2362 RTGCPTR GCPtrNearSym1;
2363 char szNearSym2[260];
2364 RTGCPTR GCPtrNearSym2;
2365 int rc = PDMR3QueryModFromEIP(pVM, uEIP,
2366 &szModName[0], sizeof(szModName), &GCPtrMod,
2367 &szNearSym1[0], sizeof(szNearSym1), &GCPtrNearSym1,
2368 &szNearSym2[0], sizeof(szNearSym2), &GCPtrNearSym2);
2369 if (VBOX_SUCCESS(rc))
2370 {
2371 pHlp->pfnPrintf(pHlp,
2372 "!! EIP in %s (%p) at rva %x near symbols:\n"
2373 "!! %VGv rva %VGv off %08x %s\n"
2374 "!! %VGv rva %VGv off -%08x %s\n",
2375 szModName, GCPtrMod, (unsigned)(uEIP - GCPtrMod),
2376 GCPtrNearSym1, GCPtrNearSym1 - GCPtrMod, (unsigned)(uEIP - GCPtrNearSym1), szNearSym1,
2377 GCPtrNearSym2, GCPtrNearSym2 - GCPtrMod, (unsigned)(GCPtrNearSym2 - uEIP), szNearSym2);
2378 }
2379 else
2380 pHlp->pfnPrintf(pHlp,
2381 "!! EIP is not in any code known to VMM!\n");
2382 }
2383
2384 /* Disassemble the instruction. */
2385 char szInstr[256];
2386 rc2 = DBGFR3DisasInstrEx(pVM, 0, 0, DBGF_DISAS_FLAGS_CURRENT_HYPER, &szInstr[0], sizeof(szInstr), NULL);
2387 if (VBOX_SUCCESS(rc2))
2388 pHlp->pfnPrintf(pHlp,
2389 "!! %s\n", szInstr);
2390
2391 /* Dump the hypervisor cpu state. */
2392 pHlp->pfnPrintf(pHlp,
2393 "!!\n"
2394 "!!\n"
2395 "!!\n");
2396 rc2 = DBGFR3Info(pVM, "cpumhyper", "verbose", pHlp);
2397 fDoneHyper = true;
2398
2399 /* Callstack. */
2400 DBGFSTACKFRAME Frame = {0};
2401 rc2 = DBGFR3StackWalkBeginHyper(pVM, &Frame);
2402 if (VBOX_SUCCESS(rc2))
2403 {
2404 pHlp->pfnPrintf(pHlp,
2405 "!!\n"
2406 "!! Call Stack:\n"
2407 "!!\n"
2408 "EBP Ret EBP Ret CS:EIP Arg0 Arg1 Arg2 Arg3 CS:EIP Symbol [line]\n");
2409 do
2410 {
2411 pHlp->pfnPrintf(pHlp,
2412 "%08RX32 %08RX32 %04RX32:%08RX32 %08RX32 %08RX32 %08RX32 %08RX32",
2413 (uint32_t)Frame.AddrFrame.off,
2414 (uint32_t)Frame.AddrReturnFrame.off,
2415 (uint32_t)Frame.AddrReturnPC.Sel,
2416 (uint32_t)Frame.AddrReturnPC.off,
2417 Frame.Args.au32[0],
2418 Frame.Args.au32[1],
2419 Frame.Args.au32[2],
2420 Frame.Args.au32[3]);
2421 pHlp->pfnPrintf(pHlp, " %RTsel:%08RGv", Frame.AddrPC.Sel, Frame.AddrPC.off);
2422 if (Frame.pSymPC)
2423 {
2424 RTGCINTPTR offDisp = Frame.AddrPC.FlatPtr - Frame.pSymPC->Value;
2425 if (offDisp > 0)
2426 pHlp->pfnPrintf(pHlp, " %s+%llx", Frame.pSymPC->szName, (int64_t)offDisp);
2427 else if (offDisp < 0)
2428 pHlp->pfnPrintf(pHlp, " %s-%llx", Frame.pSymPC->szName, -(int64_t)offDisp);
2429 else
2430 pHlp->pfnPrintf(pHlp, " %s", Frame.pSymPC->szName);
2431 }
2432 if (Frame.pLinePC)
2433 pHlp->pfnPrintf(pHlp, " [%s @ 0i%d]", Frame.pLinePC->szFilename, Frame.pLinePC->uLineNo);
2434 pHlp->pfnPrintf(pHlp, "\n");
2435
2436 /* next */
2437 rc2 = DBGFR3StackWalkNext(pVM, &Frame);
2438 } while (VBOX_SUCCESS(rc2));
2439 DBGFR3StackWalkEnd(pVM, &Frame);
2440 }
2441
2442 /* raw stack */
2443 pHlp->pfnPrintf(pHlp,
2444 "!!\n"
2445 "!! Raw stack (mind the direction).\n"
2446 "!!\n"
2447 "%.*Vhxd\n",
2448 VMM_STACK_SIZE, (char *)pVM->vmm.s.pbHCStack);
2449 break;
2450 }
2451
2452 default:
2453 {
2454 break;
2455 }
2456
2457 } /* switch (rcErr) */
2458
2459
2460 /*
2461 * Dump useful state information.
2462 */
2463 /** @todo convert these dumpers to DBGFR3Info() handlers!!! */
2464 pHlp->pfnPrintf(pHlp,
2465 "!!\n"
2466 "!! PGM Access Handlers & Stuff:\n"
2467 "!!\n");
2468 PGMR3DumpMappings(pVM);
2469
2470
2471 /*
2472 * Generic info dumper loop.
2473 */
2474 static struct
2475 {
2476 const char *pszInfo;
2477 const char *pszArgs;
2478 } const aInfo[] =
2479 {
2480 { "hma", NULL },
2481 { "cpumguest", "verbose" },
2482 { "cpumhyper", "verbose" },
2483 { "cpumhost", "verbose" },
2484 { "mode", "all" },
2485 { "cpuid", "verbose" },
2486 { "gdt", NULL },
2487 { "ldt", NULL },
2488 //{ "tss", NULL },
2489 { "ioport", NULL },
2490 { "mmio", NULL },
2491 { "phys", NULL },
2492 //{ "pgmpd", NULL }, - doesn't always work at init time...
2493 { "timers", NULL },
2494 { "activetimers", NULL },
2495 { "handlers", "phys virt stats" },
2496 { "cfgm", NULL },
2497 };
2498 for (unsigned i = 0; i < ELEMENTS(aInfo); i++)
2499 {
2500 if (fDoneHyper && !strcmp(aInfo[i].pszInfo, "cpumhyper"))
2501 continue;
2502 pHlp->pfnPrintf(pHlp,
2503 "!!\n"
2504 "!! {%s, %s}\n"
2505 "!!\n",
2506 aInfo[i].pszInfo, aInfo[i].pszArgs);
2507 DBGFR3Info(pVM, aInfo[i].pszInfo, aInfo[i].pszArgs, pHlp);
2508 }
2509
2510 /* done */
2511 pHlp->pfnPrintf(pHlp,
2512 "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n");
2513
2514
2515 /*
2516 * Delete the output instance (flushing and restoring of flags).
2517 */
2518 vmmR3FatalDumpInfoHlpDelete(&Hlp);
2519}
2520
2521
2522/**
2523 * Performs a testcase.
2524 *
2525 * @returns return value from the test.
2526 * @param pVM The VM handle.
2527 * @param enmTestcase The testcase operation to perform.
2528 * @param uVariation The testcase variation id.
2529 */
2530static int vmmR3DoGCTest(PVM pVM, VMMGCOPERATION enmTestcase, unsigned uVariation)
2531{
2532 RTGCPTR GCPtrEP;
2533 int rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &GCPtrEP);
2534 if (VBOX_FAILURE(rc))
2535 return rc;
2536
2537 CPUMHyperSetCtxCore(pVM, NULL);
2538 memset(pVM->vmm.s.pbHCStack, 0xaa, VMM_STACK_SIZE);
2539 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom); /* Clear the stack. */
2540 CPUMPushHyper(pVM, uVariation);
2541 CPUMPushHyper(pVM, enmTestcase);
2542 CPUMPushHyper(pVM, pVM->pVMGC);
2543 CPUMPushHyper(pVM, 3 * sizeof(RTGCPTR)); /* stack frame size */
2544 CPUMPushHyper(pVM, GCPtrEP); /* what to call */
2545 CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnGCCallTrampoline);
2546 return SUPCallVMMR0(pVM, VMMR0_DO_RAW_RUN, NULL);
2547}
2548
2549
2550/**
2551 * Performs a trap test.
2552 *
2553 * @returns Return value from the trap test.
2554 * @param pVM The VM handle.
2555 * @param u8Trap The trap number to test.
2556 * @param uVariation The testcase variation.
2557 * @param rcExpect The expected result.
2558 * @param u32Eax The expected eax value.
2559 * @param pszFaultEIP The fault address. Pass NULL if this isn't available or doesn't apply.
2560 * @param pszDesc The test description.
2561 */
2562static int vmmR3DoTrapTest(PVM pVM, uint8_t u8Trap, unsigned uVariation, int rcExpect, uint32_t u32Eax, const char *pszFaultEIP, const char *pszDesc)
2563{
2564 RTPrintf("VMM: testing 0%x / %d - %s\n", u8Trap, uVariation, pszDesc);
2565
2566 RTGCPTR GCPtrEP;
2567 int rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &GCPtrEP);
2568 if (VBOX_FAILURE(rc))
2569 return rc;
2570
2571 CPUMHyperSetCtxCore(pVM, NULL);
2572 memset(pVM->vmm.s.pbHCStack, 0xaa, VMM_STACK_SIZE);
2573 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom); /* Clear the stack. */
2574 CPUMPushHyper(pVM, uVariation);
2575 CPUMPushHyper(pVM, u8Trap + VMMGC_DO_TESTCASE_TRAP_FIRST);
2576 CPUMPushHyper(pVM, pVM->pVMGC);
2577 CPUMPushHyper(pVM, 3 * sizeof(RTGCPTR)); /* stack frame size */
2578 CPUMPushHyper(pVM, GCPtrEP); /* what to call */
2579 CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnGCCallTrampoline);
2580 rc = SUPCallVMMR0(pVM, VMMR0_DO_RAW_RUN, NULL);
2581 bool fDump = false;
2582 if (rc != rcExpect)
2583 {
2584 RTPrintf("VMM: FAILURE - rc=%Vrc expected %Vrc\n", rc, rcExpect);
2585 if (rc != VERR_NOT_IMPLEMENTED)
2586 fDump = true;
2587 }
2588 else if ( u8Trap != 8 /* double fault doesn't dare setting TrapNo. */
2589 && u8Trap != 3 /* guest only, we're not in guest. */
2590 && u8Trap != 1 /* guest only, we're not in guest. */
2591 && u8Trap != TRPMGetTrapNo(pVM))
2592 {
2593 RTPrintf("VMM: FAILURE - Trap %#x expected %#x\n", TRPMGetTrapNo(pVM), u8Trap);
2594 fDump = true;
2595 }
2596 else if (pszFaultEIP)
2597 {
2598 RTGCPTR GCPtrFault;
2599 int rc2 = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, pszFaultEIP, &GCPtrFault);
2600 if (VBOX_FAILURE(rc2))
2601 RTPrintf("VMM: FAILURE - Failed to resolve symbol '%s', %Vrc!\n", pszFaultEIP, rc);
2602 else if (GCPtrFault != CPUMGetHyperEIP(pVM))
2603 {
2604 RTPrintf("VMM: FAILURE - EIP=%VGv expected %VGv (%s)\n", CPUMGetHyperEIP(pVM), GCPtrFault, pszFaultEIP);
2605 fDump = true;
2606 }
2607 }
2608 else
2609 {
2610 if (CPUMGetHyperSS(pVM) == SELMGetHyperDS(pVM))
2611 RTPrintf("VMM: FAILURE - ss=%x expected %x\n", CPUMGetHyperSS(pVM), SELMGetHyperDS(pVM));
2612 if (CPUMGetHyperES(pVM) == SELMGetHyperDS(pVM))
2613 RTPrintf("VMM: FAILURE - es=%x expected %x\n", CPUMGetHyperES(pVM), SELMGetHyperDS(pVM));
2614 if (CPUMGetHyperDS(pVM) == SELMGetHyperDS(pVM))
2615 RTPrintf("VMM: FAILURE - ds=%x expected %x\n", CPUMGetHyperDS(pVM), SELMGetHyperDS(pVM));
2616 if (CPUMGetHyperFS(pVM) == SELMGetHyperDS(pVM))
2617 RTPrintf("VMM: FAILURE - fs=%x expected %x\n", CPUMGetHyperFS(pVM), SELMGetHyperDS(pVM));
2618 if (CPUMGetHyperGS(pVM) == SELMGetHyperDS(pVM))
2619 RTPrintf("VMM: FAILURE - gs=%x expected %x\n", CPUMGetHyperGS(pVM), SELMGetHyperDS(pVM));
2620 if (CPUMGetHyperEDI(pVM) == 0x01234567)
2621 RTPrintf("VMM: FAILURE - edi=%x expected %x\n", CPUMGetHyperEDI(pVM), 0x01234567);
2622 if (CPUMGetHyperESI(pVM) == 0x42000042)
2623 RTPrintf("VMM: FAILURE - esi=%x expected %x\n", CPUMGetHyperESI(pVM), 0x42000042);
2624 if (CPUMGetHyperEBP(pVM) == 0xffeeddcc)
2625 RTPrintf("VMM: FAILURE - ebp=%x expected %x\n", CPUMGetHyperEBP(pVM), 0xffeeddcc);
2626 if (CPUMGetHyperEBX(pVM) == 0x89abcdef)
2627 RTPrintf("VMM: FAILURE - ebx=%x expected %x\n", CPUMGetHyperEBX(pVM), 0x89abcdef);
2628 if (CPUMGetHyperECX(pVM) == 0xffffaaaa)
2629 RTPrintf("VMM: FAILURE - ecx=%x expected %x\n", CPUMGetHyperECX(pVM), 0xffffaaaa);
2630 if (CPUMGetHyperEDX(pVM) == 0x77778888)
2631 RTPrintf("VMM: FAILURE - edx=%x expected %x\n", CPUMGetHyperEDX(pVM), 0x77778888);
2632 if (CPUMGetHyperEAX(pVM) == u32Eax)
2633 RTPrintf("VMM: FAILURE - eax=%x expected %x\n", CPUMGetHyperEAX(pVM), u32Eax);
2634 }
2635 if (fDump)
2636 VMMR3FatalDump(pVM, rc);
2637 return rc;
2638}
2639
2640
2641/* execute the switch. */
2642VMMR3DECL(int) VMMDoTest(PVM pVM)
2643{
2644#if 1
2645#ifdef NO_SUPCALLR0VMM
2646 RTPrintf("NO_SUPCALLR0VMM\n");
2647 return VINF_SUCCESS;
2648#endif
2649
2650 /*
2651 * Setup stack for calling VMMGCEntry().
2652 */
2653 RTGCPTR GCPtrEP;
2654 int rc = PDMR3GetSymbolGC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &GCPtrEP);
2655 if (VBOX_SUCCESS(rc))
2656 {
2657 RTPrintf("VMM: VMMGCEntry=%VGv\n", GCPtrEP);
2658
2659 /*
2660 * Test various crashes which we must be able to recover from.
2661 */
2662 vmmR3DoTrapTest(pVM, 0x3, 0, VINF_EM_DBG_HYPER_ASSERTION, 0xf0f0f0f0, "vmmGCTestTrap3_FaultEIP", "int3");
2663 vmmR3DoTrapTest(pVM, 0x3, 1, VINF_EM_DBG_HYPER_ASSERTION, 0xf0f0f0f0, "vmmGCTestTrap3_FaultEIP", "int3 WP");
2664
2665#if defined(DEBUG_bird) /* guess most people would like to skip these since they write to com1. */
2666 vmmR3DoTrapTest(pVM, 0x8, 0, VERR_TRPM_PANIC, 0x00000000, "vmmGCTestTrap8_FaultEIP", "#DF [#PG]");
2667 SELMR3Relocate(pVM); /* this resets the busy flag of the Trap 08 TSS */
2668 bool f;
2669 rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "DoubleFault", &f);
2670#if !defined(DEBUG_bird)
2671 if (VBOX_SUCCESS(rc) && f)
2672#endif
2673 {
2674 /* see tripple fault warnings in SELM and VMMGC.cpp. */
2675 vmmR3DoTrapTest(pVM, 0x8, 1, VERR_TRPM_PANIC, 0x00000000, "vmmGCTestTrap8_FaultEIP", "#DF [#PG] WP");
2676 SELMR3Relocate(pVM); /* this resets the busy flag of the Trap 08 TSS */
2677 }
2678#endif
2679
2680 vmmR3DoTrapTest(pVM, 0xd, 0, VERR_TRPM_DONT_PANIC, 0xf0f0f0f0, "vmmGCTestTrap0d_FaultEIP", "ltr #GP");
2681 ///@todo find a better \#GP case, on intel ltr will \#PF (busy update?) and not \#GP.
2682 //vmmR3DoTrapTest(pVM, 0xd, 1, VERR_TRPM_DONT_PANIC, 0xf0f0f0f0, "vmmGCTestTrap0d_FaultEIP", "ltr #GP WP");
2683
2684 vmmR3DoTrapTest(pVM, 0xe, 0, VERR_TRPM_DONT_PANIC, 0x00000000, "vmmGCTestTrap0e_FaultEIP", "#PF (NULL)");
2685 vmmR3DoTrapTest(pVM, 0xe, 1, VERR_TRPM_DONT_PANIC, 0x00000000, "vmmGCTestTrap0e_FaultEIP", "#PF (NULL) WP");
2686
2687 /*
2688 * Set a debug register and perform a context switch.
2689 */
2690 rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_NOP, 0);
2691 if (rc != VINF_SUCCESS)
2692 {
2693 RTPrintf("VMM: Nop test failed, rc=%Vrc not VINF_SUCCESS\n", rc);
2694 return rc;
2695 }
2696
2697 /* a harmless breakpoint */
2698 RTPrintf("VMM: testing hardware bp at 0x10000 (not hit)\n");
2699 DBGFADDRESS Addr;
2700 DBGFR3AddrFromFlat(pVM, &Addr, 0x10000);
2701 RTUINT iBp0;
2702 rc = DBGFR3BpSetReg(pVM, &Addr, 0, ~(uint64_t)0, X86_DR7_RW_EO, 1, &iBp0);
2703 AssertReleaseRC(rc);
2704 rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_NOP, 0);
2705 if (rc != VINF_SUCCESS)
2706 {
2707 RTPrintf("VMM: DR0=0x10000 test failed with rc=%Vrc!\n", rc);
2708 return rc;
2709 }
2710
2711 /* a bad one at VMMGCEntry */
2712 RTPrintf("VMM: testing hardware bp at VMMGCEntry (hit)\n");
2713 DBGFR3AddrFromFlat(pVM, &Addr, GCPtrEP);
2714 RTUINT iBp1;
2715 rc = DBGFR3BpSetReg(pVM, &Addr, 0, ~(uint64_t)0, X86_DR7_RW_EO, 1, &iBp1);
2716 AssertReleaseRC(rc);
2717 rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_NOP, 0);
2718 if (rc != VINF_EM_DBG_HYPER_BREAKPOINT)
2719 {
2720 RTPrintf("VMM: DR1=VMMGCEntry test failed with rc=%Vrc! expected VINF_EM_RAW_BREAKPOINT_HYPER\n", rc);
2721 return rc;
2722 }
2723
2724 /* resume the breakpoint */
2725 RTPrintf("VMM: resuming hyper after breakpoint\n");
2726 CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) | X86_EFL_RF);
2727 rc = VMMR3ResumeHyper(pVM);
2728 if (rc != VINF_SUCCESS)
2729 {
2730 RTPrintf("VMM: failed to resume on hyper breakpoint, rc=%Vrc\n", rc);
2731 return rc;
2732 }
2733
2734 /* engage the breakpoint again and try single stepping. */
2735 RTPrintf("VMM: testing hardware bp at VMMGCEntry + stepping\n");
2736 rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_NOP, 0);
2737 if (rc != VINF_EM_DBG_HYPER_BREAKPOINT)
2738 {
2739 RTPrintf("VMM: DR1=VMMGCEntry test failed with rc=%Vrc! expected VINF_EM_RAW_BREAKPOINT_HYPER\n", rc);
2740 return rc;
2741 }
2742
2743 RTGCUINTREG OldPc = CPUMGetHyperEIP(pVM);
2744 RTPrintf("%RGr=>", OldPc);
2745 unsigned i;
2746 for (i = 0; i < 8; i++)
2747 {
2748 CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) | X86_EFL_TF | X86_EFL_RF);
2749 rc = VMMR3ResumeHyper(pVM);
2750 if (rc != VINF_EM_DBG_HYPER_STEPPED)
2751 {
2752 RTPrintf("\nVMM: failed to step on hyper breakpoint, rc=%Vrc\n", rc);
2753 return rc;
2754 }
2755 RTGCUINTREG Pc = CPUMGetHyperEIP(pVM);
2756 RTPrintf("%RGr=>", Pc);
2757 if (Pc == OldPc)
2758 {
2759 RTPrintf("\nVMM: step failed, PC: %RGr -> %RGr\n", OldPc, Pc);
2760 return VERR_GENERAL_FAILURE;
2761 }
2762 OldPc = Pc;
2763 }
2764 RTPrintf("ok\n");
2765
2766 /* done, clear it */
2767 if ( VBOX_FAILURE(DBGFR3BpClear(pVM, iBp0))
2768 || VBOX_FAILURE(DBGFR3BpClear(pVM, iBp1)))
2769 {
2770 RTPrintf("VMM: Failed to clear breakpoints!\n");
2771 return VERR_GENERAL_FAILURE;
2772 }
2773 rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_NOP, 0);
2774 if (rc != VINF_SUCCESS)
2775 {
2776 RTPrintf("VMM: NOP failed, rc=%Vrc\n", rc);
2777 return rc;
2778 }
2779
2780 /*
2781 * Interrupt masking.
2782 */
2783 RTPrintf("VMM: interrupt masking...\n"); RTStrmFlush(g_pStdOut); RTThreadSleep(250);
2784 for (i = 0; i < 10000; i++)
2785 {
2786 uint64_t StartTick = ASMReadTSC();
2787 rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_INTERRUPT_MASKING, 0);
2788 if (rc != VINF_SUCCESS)
2789 {
2790 RTPrintf("VMM: Interrupt masking failed: rc=%Vrc\n", rc);
2791 return rc;
2792 }
2793 uint64_t Ticks = ASMReadTSC() - StartTick;
2794 if (Ticks < (g_pSUPGlobalInfoPage->u64CpuHz / 10000))
2795 RTPrintf("Warning: Ticks=%RU64 (< %RU64)\n", Ticks, g_pSUPGlobalInfoPage->u64CpuHz / 10000);
2796 }
2797
2798 /*
2799 * Interrupt forwarding.
2800 */
2801 CPUMHyperSetCtxCore(pVM, NULL);
2802 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom); /* Clear the stack. */
2803 CPUMPushHyper(pVM, 0);
2804 CPUMPushHyper(pVM, VMMGC_DO_TESTCASE_HYPER_INTERRUPT);
2805 CPUMPushHyper(pVM, pVM->pVMGC);
2806 CPUMPushHyper(pVM, 3 * sizeof(RTGCPTR)); /* stack frame size */
2807 CPUMPushHyper(pVM, GCPtrEP); /* what to call */
2808 CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnGCCallTrampoline);
2809 Log(("trampoline=%x\n", pVM->vmm.s.pfnGCCallTrampoline));
2810
2811 /*
2812 * Switch and do da thing.
2813 */
2814 RTPrintf("VMM: interrupt forwarding...\n"); RTStrmFlush(g_pStdOut); RTThreadSleep(250);
2815 i = 0;
2816 uint64_t tsBegin = RTTimeNanoTS();
2817 uint64_t TickStart = ASMReadTSC();
2818 do
2819 {
2820 rc = SUPCallVMMR0(pVM, VMMR0_DO_RAW_RUN, NULL);
2821 if (VBOX_FAILURE(rc))
2822 {
2823 Log(("VMM: GC returned fatal %Vra in iteration %d\n", rc, i));
2824 VMMR3FatalDump(pVM, rc);
2825 return rc;
2826 }
2827 i++;
2828 if (!(i % 32))
2829 Log(("VMM: iteration %d, esi=%08x edi=%08x ebx=%08x\n",
2830 i, CPUMGetHyperESI(pVM), CPUMGetHyperEDI(pVM), CPUMGetHyperEBX(pVM)));
2831 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
2832 uint64_t TickEnd = ASMReadTSC();
2833 uint64_t tsEnd = RTTimeNanoTS();
2834
2835 uint64_t Elapsed = tsEnd - tsBegin;
2836 uint64_t PerIteration = Elapsed / (uint64_t)i;
2837 uint64_t cTicksElapsed = TickEnd - TickStart;
2838 uint64_t cTicksPerIteration = cTicksElapsed / (uint64_t)i;
2839
2840 RTPrintf("VMM: %8d interrupts in %11llu ns (%11llu ticks), %10llu ns/iteration (%11llu ticks)\n",
2841 i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration);
2842 Log(("VMM: %8d interrupts in %11llu ns (%11llu ticks), %10llu ns/iteration (%11llu ticks)\n",
2843 i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration));
2844
2845 /*
2846 * These forced actions are not necessary for the test and trigger breakpoints too.
2847 */
2848 VM_FF_CLEAR(pVM, VM_FF_TRPM_SYNC_IDT);
2849 VM_FF_CLEAR(pVM, VM_FF_SELM_SYNC_TSS);
2850
2851 /*
2852 * Profile switching.
2853 */
2854 RTPrintf("VMM: profiling switcher...\n");
2855 Log(("VMM: profiling switcher...\n"));
2856 uint64_t TickMin = ~0;
2857 tsBegin = RTTimeNanoTS();
2858 TickStart = ASMReadTSC();
2859 for (i = 0; i < 1000000; i++)
2860 {
2861 CPUMHyperSetCtxCore(pVM, NULL);
2862 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom); /* Clear the stack. */
2863 CPUMPushHyper(pVM, 0);
2864 CPUMPushHyper(pVM, VMMGC_DO_TESTCASE_NOP);
2865 CPUMPushHyper(pVM, pVM->pVMGC);
2866 CPUMPushHyper(pVM, 3 * sizeof(RTGCPTR)); /* stack frame size */
2867 CPUMPushHyper(pVM, GCPtrEP); /* what to call */
2868 CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnGCCallTrampoline);
2869
2870 uint64_t TickThisStart = ASMReadTSC();
2871 rc = SUPCallVMMR0(pVM, VMMR0_DO_RAW_RUN, NULL);
2872 uint64_t TickThisElapsed = ASMReadTSC() - TickThisStart;
2873 if (VBOX_FAILURE(rc))
2874 {
2875 Log(("VMM: GC returned fatal %Vra in iteration %d\n", rc, i));
2876 VMMR3FatalDump(pVM, rc);
2877 return rc;
2878 }
2879 if (TickThisElapsed < TickMin)
2880 TickMin = TickThisElapsed;
2881 }
2882 TickEnd = ASMReadTSC();
2883 tsEnd = RTTimeNanoTS();
2884
2885 Elapsed = tsEnd - tsBegin;
2886 PerIteration = Elapsed / (uint64_t)i;
2887 cTicksElapsed = TickEnd - TickStart;
2888 cTicksPerIteration = cTicksElapsed / (uint64_t)i;
2889
2890 RTPrintf("VMM: %8d cycles in %11llu ns (%11lld ticks), %10llu ns/iteration (%11lld ticks) Min %11lld ticks\n",
2891 i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration, TickMin);
2892 Log(("VMM: %8d cycles in %11llu ns (%11lld ticks), %10llu ns/iteration (%11lld ticks) Min %11lld ticks\n",
2893 i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration, TickMin));
2894
2895 rc = VINF_SUCCESS;
2896 }
2897 else
2898 AssertMsgFailed(("Failed to resolved VMMGC.gc::VMMGCEntry(), rc=%Vrc\n", rc));
2899#endif
2900 return rc;
2901}
2902
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