VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/APICAll.cpp@ 61568

Last change on this file since 61568 was 61557, checked in by vboxsync, 9 years ago

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1/* $Id: APICAll.cpp 61557 2016-06-08 07:59:01Z vboxsync $ */
2/** @file
3 * APIC - Advanced Programmable Interrupt Controller - All Contexts.
4 */
5
6/*
7 * Copyright (C) 2016 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_APIC
23#include "APICInternal.h"
24#include <VBox/vmm/pdmdev.h>
25#include <VBox/vmm/vm.h>
26#include <VBox/vmm/vmcpuset.h>
27
28/*********************************************************************************************************************************
29* Global Variables *
30*********************************************************************************************************************************/
31#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
32/** An ordered array of valid LVT masks. */
33static const uint32_t g_au32LvtValidMasks[] =
34{
35 XAPIC_LVT_TIMER_VALID,
36 XAPIC_LVT_THERMAL_VALID,
37 XAPIC_LVT_PERF_VALID,
38 XAPIC_LVT_LINT_VALID, /* LINT0 */
39 XAPIC_LVT_LINT_VALID, /* LINT1 */
40 XAPIC_LVT_ERROR_VALID
41};
42#endif
43
44#if 0
45/** @todo CMCI */
46static const uint32_t g_au32LvtExtValidMask[] =
47{
48 XAPIC_LVT_CMCI_VALID
49};
50#endif
51
52
53/**
54 * Checks if a vector is set in an APIC 256-bit sparse register.
55 *
56 * @returns true if the specified vector is set, false otherwise.
57 * @param pApicReg The APIC 256-bit spare register.
58 * @param uVector The vector to check if set.
59 */
60DECLINLINE(bool) apicTestVectorInReg(const volatile XAPIC256BITREG *pApicReg, uint8_t uVector)
61{
62 const volatile uint8_t *pbBitmap = (const volatile uint8_t *)&pApicReg->u[0];
63 return ASMBitTest(pbBitmap + XAPIC_REG256_VECTOR_OFF(uVector), XAPIC_REG256_VECTOR_BIT(uVector));
64}
65
66
67/**
68 * Sets the vector in an APIC 256-bit sparse register.
69 *
70 * @param pApicReg The APIC 256-bit spare register.
71 * @param uVector The vector to set.
72 */
73DECLINLINE(void) apicSetVectorInReg(volatile XAPIC256BITREG *pApicReg, uint8_t uVector)
74{
75 volatile uint8_t *pbBitmap = (volatile uint8_t *)&pApicReg->u[0];
76 ASMAtomicBitSet(pbBitmap + XAPIC_REG256_VECTOR_OFF(uVector), XAPIC_REG256_VECTOR_BIT(uVector));
77}
78
79
80/**
81 * Clears the vector in an APIC 256-bit sparse register.
82 *
83 * @param pApicReg The APIC 256-bit spare register.
84 * @param uVector The vector to clear.
85 */
86DECLINLINE(void) apicClearVectorInReg(volatile XAPIC256BITREG *pApicReg, uint8_t uVector)
87{
88 volatile uint8_t *pbBitmap = (volatile uint8_t *)&pApicReg->u[0];
89 ASMAtomicBitClear(pbBitmap + XAPIC_REG256_VECTOR_OFF(uVector), XAPIC_REG256_VECTOR_BIT(uVector));
90}
91
92
93/**
94 * Checks if a vector is set in an APIC Pending-Interrupt Bitmap (PIB).
95 *
96 * @returns true if the specified vector is set, false otherwise.
97 * @param pvPib Opaque pointer to the PIB.
98 * @param uVector The vector to check if set.
99 */
100DECLINLINE(bool) apicTestVectorInPib(volatile void *pvPib, uint8_t uVector)
101{
102 return ASMBitTest(pvPib, uVector);
103}
104
105
106/**
107 * Atomically sets the PIB notification bit.
108 *
109 * @returns non-zero if the bit was already set, 0 otherwise.
110 * @param pApicPib Pointer to the PIB.
111 */
112DECLINLINE(uint32_t) apicSetNotificationBitInPib(PAPICPIB pApicPib)
113{
114 return ASMAtomicXchgU32(&pApicPib->fOutstandingNotification, RT_BIT_32(31));
115}
116
117
118/**
119 * Atomically tests and clears the PIB notification bit.
120 *
121 * @returns non-zero if the bit was already set, 0 otherwise.
122 * @param pApicPib Pointer to the PIB.
123 */
124DECLINLINE(uint32_t) apicClearNotificationBitInPib(PAPICPIB pApicPib)
125{
126 return ASMAtomicXchgU32(&pApicPib->fOutstandingNotification, UINT32_C(0));
127}
128
129
130/**
131 * Sets the vector in an APIC Pending-Interrupt Bitmap (PIB).
132 *
133 * @param pvPib Opaque pointer to the PIB.
134 * @param uVector The vector to set.
135 */
136DECLINLINE(void) apicSetVectorInPib(volatile void *pvPib, uint8_t uVector)
137{
138 ASMAtomicBitSet(pvPib, uVector);
139}
140
141
142/**
143 * Clears the vector in an APIC Pending-Interrupt Bitmap (PIB).
144 *
145 * @param pvPib Opaque pointer to the PIB.
146 * @param uVector The vector to clear.
147 */
148DECLINLINE(void) apicClearVectorInPib(volatile void *pvPib, uint8_t uVector)
149{
150 ASMAtomicBitClear(pvPib, uVector);
151}
152
153
154/**
155 * Atomically OR's a fragment (32 vectors) into an APIC 256-bit sparse
156 * register.
157 *
158 * @param pApicReg The APIC 256-bit spare register.
159 * @param idxFragment The index of the 32-bit fragment in @a
160 * pApicReg.
161 * @param u32Fragment The 32-bit vector fragment to OR.
162 */
163DECLINLINE(void) apicOrVectorsToReg(volatile XAPIC256BITREG *pApicReg, size_t idxFragment, uint32_t u32Fragment)
164{
165 Assert(idxFragment < RT_ELEMENTS(pApicReg->u));
166 ASMAtomicOrU32(&pApicReg->u[idxFragment].u32Reg, u32Fragment);
167}
168
169
170/**
171 * Atomically AND's a fragment (32 vectors) into an APIC
172 * 256-bit sparse register.
173 *
174 * @param pApicReg The APIC 256-bit spare register.
175 * @param idxFragment The index of the 32-bit fragment in @a
176 * pApicReg.
177 * @param u32Fragment The 32-bit vector fragment to AND.
178 */
179DECLINLINE(void) apicAndVectorsToReg(volatile XAPIC256BITREG *pApicReg, size_t idxFragment, uint32_t u32Fragment)
180{
181 Assert(idxFragment < RT_ELEMENTS(pApicReg->u));
182 ASMAtomicAndU32(&pApicReg->u[idxFragment].u32Reg, u32Fragment);
183}
184
185
186/**
187 * Reports and returns appropriate error code for invalid MSR accesses.
188 *
189 * @returns Strict VBox status code.
190 * @retval VINF_CPUM_R3_MSR_WRITE if the MSR write could not be serviced in the
191 * current context (raw-mode or ring-0).
192 * @retval VINF_CPUM_R3_MSR_READ if the MSR read could not be serviced in the
193 * current context (raw-mode or ring-0).
194 * @retval VERR_CPUM_RAISE_GP_0 on failure, the caller is expected to take the
195 * appropriate actions.
196 *
197 * @param pVCpu The cross context virtual CPU structure.
198 * @param u32Reg The MSR being accessed.
199 * @param enmAccess The invalid-access type.
200 */
201static VBOXSTRICTRC apicMsrAccessError(PVMCPU pVCpu, uint32_t u32Reg, APICMSRACCESS enmAccess)
202{
203 static struct
204 {
205 const char *pszBefore; /* The error message before printing the MSR index */
206 const char *pszAfter; /* The error message after printing the MSR index */
207 int rcRZ; /* The RZ error code */
208 } const s_aAccess[] =
209 {
210 { "read MSR", " while not in x2APIC mode", VINF_CPUM_R3_MSR_READ },
211 { "write MSR", " while not in x2APIC mode", VINF_CPUM_R3_MSR_WRITE },
212 { "read reserved/unknown MSR", "", VINF_CPUM_R3_MSR_READ },
213 { "write reserved/unknown MSR", "", VINF_CPUM_R3_MSR_WRITE },
214 { "read write-only MSR", "", VINF_CPUM_R3_MSR_READ },
215 { "write read-only MSR", "", VINF_CPUM_R3_MSR_WRITE },
216 { "read reserved bits of MSR", "", VINF_CPUM_R3_MSR_READ },
217 { "write reserved bits of MSR", "", VINF_CPUM_R3_MSR_WRITE },
218 { "write an invalid value to MSR", "", VINF_CPUM_R3_MSR_WRITE },
219 { "write MSR", "disallowed by configuration", VINF_CPUM_R3_MSR_WRITE }
220 };
221 AssertCompile(RT_ELEMENTS(s_aAccess) == APICMSRACCESS_COUNT);
222
223 size_t const i = enmAccess;
224 Assert(i < RT_ELEMENTS(s_aAccess));
225#ifdef IN_RING3
226 LogRelMax(5, ("APIC%u: Attempt to %s (%#x)%s -> #GP(0)\n", pVCpu->idCpu, s_aAccess[i].pszBefore, u32Reg,
227 s_aAccess[i].pszAfter));
228 return VERR_CPUM_RAISE_GP_0;
229#else
230 return s_aAccess[i].rcRZ;
231#endif
232}
233
234
235/**
236 * Gets the descriptive APIC mode.
237 *
238 * @returns The name.
239 * @param enmMode The xAPIC mode.
240 */
241const char *apicGetModeName(APICMODE enmMode)
242{
243 switch (enmMode)
244 {
245 case APICMODE_DISABLED: return "Disabled";
246 case APICMODE_XAPIC: return "xAPIC";
247 case APICMODE_X2APIC: return "x2APIC";
248 default: break;
249 }
250 return "Invalid";
251}
252
253
254/**
255 * Gets the descriptive destination format name.
256 *
257 * @returns The destination format name.
258 * @param enmDestFormat The destination format.
259 */
260const char *apicGetDestFormatName(XAPICDESTFORMAT enmDestFormat)
261{
262 switch (enmDestFormat)
263 {
264 case XAPICDESTFORMAT_FLAT: return "Flat";
265 case XAPICDESTFORMAT_CLUSTER: return "Cluster";
266 default: break;
267 }
268 return "Invalid";
269}
270
271
272/**
273 * Gets the descriptive delivery mode name.
274 *
275 * @returns The delivery mode name.
276 * @param enmDeliveryMode The delivery mode.
277 */
278const char *apicGetDeliveryModeName(XAPICDELIVERYMODE enmDeliveryMode)
279{
280 switch (enmDeliveryMode)
281 {
282 case XAPICDELIVERYMODE_FIXED: return "Fixed";
283 case XAPICDELIVERYMODE_LOWEST_PRIO: return "Lowest-priority";
284 case XAPICDELIVERYMODE_SMI: return "SMI";
285 case XAPICDELIVERYMODE_NMI: return "NMI";
286 case XAPICDELIVERYMODE_INIT: return "INIT";
287 case XAPICDELIVERYMODE_STARTUP: return "SIPI";
288 case XAPICDELIVERYMODE_EXTINT: return "ExtINT";
289 default: break;
290 }
291 return "Invalid";
292}
293
294
295/**
296 * Gets the descriptive destination mode name.
297 *
298 * @returns The destination mode name.
299 * @param enmDestMode The destination mode.
300 */
301const char *apicGetDestModeName(XAPICDESTMODE enmDestMode)
302{
303 switch (enmDestMode)
304 {
305 case XAPICDESTMODE_PHYSICAL: return "Physical";
306 case XAPICDESTMODE_LOGICAL: return "Logical";
307 default: break;
308 }
309 return "Invalid";
310}
311
312
313/**
314 * Gets the descriptive trigger mode name.
315 *
316 * @returns The trigger mode name.
317 * @param enmTriggerMode The trigger mode.
318 */
319const char *apicGetTriggerModeName(XAPICTRIGGERMODE enmTriggerMode)
320{
321 switch (enmTriggerMode)
322 {
323 case XAPICTRIGGERMODE_EDGE: return "Edge";
324 case XAPICTRIGGERMODE_LEVEL: return "Level";
325 default: break;
326 }
327 return "Invalid";
328}
329
330
331/**
332 * Gets the destination shorthand name.
333 *
334 * @returns The destination shorthand name.
335 * @param enmDestShorthand The destination shorthand.
336 */
337const char *apicGetDestShorthandName(XAPICDESTSHORTHAND enmDestShorthand)
338{
339 switch (enmDestShorthand)
340 {
341 case XAPICDESTSHORTHAND_NONE: return "None";
342 case XAPICDESTSHORTHAND_SELF: return "Self";
343 case XAPIDDESTSHORTHAND_ALL_INCL_SELF: return "All including self";
344 case XAPICDESTSHORTHAND_ALL_EXCL_SELF: return "All excluding self";
345 default: break;
346 }
347 return "Invalid";
348}
349
350
351/**
352 * Gets the timer mode name.
353 *
354 * @returns The timer mode name.
355 * @param enmTimerMode The timer mode.
356 */
357const char *apicGetTimerModeName(XAPICTIMERMODE enmTimerMode)
358{
359 switch (enmTimerMode)
360 {
361 case XAPICTIMERMODE_ONESHOT: return "One-shot";
362 case XAPICTIMERMODE_PERIODIC: return "Periodic";
363 case XAPICTIMERMODE_TSC_DEADLINE: return "TSC deadline";
364 default: break;
365 }
366 return "Invalid";
367}
368
369
370/**
371 * Gets the APIC mode given the base MSR value.
372 *
373 * @returns The APIC mode.
374 * @param uApicBaseMsr The APIC Base MSR value.
375 */
376APICMODE apicGetMode(uint64_t uApicBaseMsr)
377{
378 uint32_t const uMode = (uApicBaseMsr >> 10) & UINT64_C(3);
379 APICMODE const enmMode = (APICMODE)uMode;
380#ifdef VBOX_STRICT
381 /* Paranoia. */
382 switch (uMode)
383 {
384 case APICMODE_DISABLED:
385 case APICMODE_INVALID:
386 case APICMODE_XAPIC:
387 case APICMODE_X2APIC:
388 break;
389 default:
390 AssertMsgFailed(("Invalid mode"));
391 }
392#endif
393 return enmMode;
394}
395
396
397/**
398 * Returns whether the APIC is hardware enabled or not.
399 *
400 * @returns true if enabled, false otherwise.
401 */
402DECLINLINE(bool) apicIsEnabled(PVMCPU pVCpu)
403{
404 PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
405 return RT_BOOL(pApicCpu->uApicBaseMsr & MSR_IA32_APICBASE_EN);
406}
407
408
409/**
410 * Finds the most significant set bit in an APIC 256-bit sparse register.
411 *
412 * @returns @a rcNotFound if no bit was set, 0-255 otherwise.
413 * @param pReg The APIC 256-bit sparse register.
414 * @param rcNotFound What to return when no bit is set.
415 */
416static int apicGetHighestSetBitInReg(volatile const XAPIC256BITREG *pReg, int rcNotFound)
417{
418 ssize_t const cFragments = RT_ELEMENTS(pReg->u);
419 unsigned const uFragmentShift = 5;
420 AssertCompile(1 << uFragmentShift == sizeof(pReg->u[0].u32Reg) * 8);
421 for (ssize_t i = cFragments - 1; i >= 0; i--)
422 {
423 uint32_t const uFragment = pReg->u[i].u32Reg;
424 if (uFragment)
425 {
426 unsigned idxSetBit = ASMBitLastSetU32(uFragment);
427 --idxSetBit;
428 idxSetBit |= i << uFragmentShift;
429 return idxSetBit;
430 }
431 }
432 return rcNotFound;
433}
434
435
436/**
437 * Reads a 32-bit register at a specified offset.
438 *
439 * @returns The value at the specified offset.
440 * @param pXApicPage The xAPIC page.
441 * @param offReg The offset of the register being read.
442 */
443DECLINLINE(uint32_t) apicReadRaw32(PCXAPICPAGE pXApicPage, uint16_t offReg)
444{
445 Assert(offReg < sizeof(*pXApicPage) - sizeof(uint32_t));
446 uint8_t const *pbXApic = (const uint8_t *)pXApicPage;
447 uint32_t const uValue = *(const uint32_t *)(pbXApic + offReg);
448 return uValue;
449}
450
451
452/**
453 * Writes a 32-bit register at a specified offset.
454 *
455 * @param pXApicPage The xAPIC page.
456 * @param offReg The offset of the register being written.
457 * @param uReg The value of the register.
458 */
459DECLINLINE(void) apicWriteRaw32(PXAPICPAGE pXApicPage, uint16_t offReg, uint32_t uReg)
460{
461 Assert(offReg < sizeof(*pXApicPage) - sizeof(uint32_t));
462 uint8_t *pbXApic = (uint8_t *)pXApicPage;
463 *(uint32_t *)(pbXApic + offReg) = uReg;
464}
465
466
467/**
468 * Broadcasts the EOI to the I/O APICs.
469 *
470 * @param pVCpu The cross context virtual CPU structure.
471 * @param uVector The interrupt vector corresponding to the EOI.
472 */
473DECLINLINE(void) apicBusBroadcastEoi(PVMCPU pVCpu, uint8_t uVector)
474{
475 PVM pVM = pVCpu->CTX_SUFF(pVM);
476 PAPICDEV pApicDev = VM_TO_APICDEV(pVM);
477 pApicDev->CTX_SUFF(pApicHlp)->pfnBusBroadcastEoi(pApicDev->CTX_SUFF(pDevIns), uVector);
478}
479
480
481/**
482 * Sets an error in the internal ESR of the specified APIC.
483 *
484 * @param pVCpu The cross context virtual CPU structure.
485 * @param uError The error.
486 * @thread Any.
487 */
488DECLINLINE(void) apicSetError(PVMCPU pVCpu, uint32_t uError)
489{
490 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
491 ASMAtomicOrU32(&pApicCpu->uEsrInternal, uError);
492}
493
494
495/**
496 * Clears all errors in the internal ESR.
497 *
498 * @returns The value of the internal ESR before clearing.
499 * @param pVCpu The cross context virtual CPU structure.
500 */
501DECLINLINE(uint32_t) apicClearAllErrors(PVMCPU pVCpu)
502{
503 VMCPU_ASSERT_EMT(pVCpu);
504 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
505 return ASMAtomicXchgU32(&pApicCpu->uEsrInternal, 0);
506}
507
508
509/**
510 * Signals the guest if a pending interrupt is ready to be serviced.
511 *
512 * @param pVCpu The cross context virtual CPU structure.
513 */
514static void apicSignalNextPendingIntr(PVMCPU pVCpu)
515{
516 VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
517
518 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
519 if (pXApicPage->svr.u.fApicSoftwareEnable)
520 {
521 int const irrv = apicGetHighestSetBitInReg(&pXApicPage->irr, -1 /* rcNotFound */);
522 if (irrv >= 0)
523 {
524 Assert(irrv <= (int)UINT8_MAX);
525 uint8_t const uVector = irrv;
526 uint8_t const uPpr = pXApicPage->ppr.u8Ppr;
527 if ( !uPpr
528 || XAPIC_PPR_GET_PP(uVector) > XAPIC_PPR_GET_PP(uPpr))
529 {
530 Log2(("APIC%u: apicSignalNextPendingIntr: Signaling pending interrupt. uVector=%#x\n", pVCpu->idCpu, uVector));
531 APICSetInterruptFF(pVCpu, PDMAPICIRQ_HARDWARE);
532 }
533 else
534 {
535 Log2(("APIC%u: apicSignalNextPendingIntr: Nothing to signal. uVector=%#x uPpr=%#x uTpr=%#x\n", pVCpu->idCpu,
536 uVector, uPpr, pXApicPage->tpr.u8Tpr));
537 }
538 }
539 }
540 else
541 {
542 Log2(("APIC%u: apicSignalNextPendingIntr: APIC software-disabled, clearing pending interrupt\n", pVCpu->idCpu));
543 APICClearInterruptFF(pVCpu, PDMAPICIRQ_HARDWARE);
544 }
545}
546
547
548/**
549 * Sets the Spurious-Interrupt Vector Register (SVR).
550 *
551 * @returns Strict VBox status code.
552 * @param pVCpu The cross context virtual CPU structure.
553 * @param uSvr The SVR value.
554 */
555static VBOXSTRICTRC apicSetSvr(PVMCPU pVCpu, uint32_t uSvr)
556{
557 VMCPU_ASSERT_EMT(pVCpu);
558
559 uint32_t uValidMask = XAPIC_SVR_VALID;
560 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
561 if (pXApicPage->version.u.fEoiBroadcastSupression)
562 uValidMask |= XAPIC_SVR_SUPRESS_EOI_BROADCAST;
563
564 if ( XAPIC_IN_X2APIC_MODE(pVCpu)
565 && (uSvr & ~uValidMask))
566 return apicMsrAccessError(pVCpu, MSR_IA32_X2APIC_SVR, APICMSRACCESS_WRITE_RSVD_BITS);
567
568 Log2(("APIC%u: apicSetSvr: uSvr=%#RX32\n", pVCpu->idCpu, uSvr));
569 apicWriteRaw32(pXApicPage, XAPIC_OFF_SVR, uSvr);
570 if (!pXApicPage->svr.u.fApicSoftwareEnable)
571 {
572 /** @todo CMCI. */
573 pXApicPage->lvt_timer.u.u1Mask = 1;
574#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
575 pXApicPage->lvt_thermal.u.u1Mask = 1;
576#endif
577 pXApicPage->lvt_perf.u.u1Mask = 1;
578 pXApicPage->lvt_lint0.u.u1Mask = 1;
579 pXApicPage->lvt_lint1.u.u1Mask = 1;
580 pXApicPage->lvt_error.u.u1Mask = 1;
581 }
582
583 apicSignalNextPendingIntr(pVCpu);
584 return VINF_SUCCESS;
585}
586
587
588/**
589 * Sends an interrupt to one or more APICs.
590 *
591 * @returns Strict VBox status code.
592 * @param pVM The cross context VM structure.
593 * @param pVCpu The cross context virtual CPU structure, can be
594 * NULL if the source of the interrupt is not an
595 * APIC (for e.g. a bus).
596 * @param uVector The interrupt vector.
597 * @param enmTriggerMode The trigger mode.
598 * @param enmDeliveryMode The delivery mode.
599 * @param pDestCpuSet The destination CPU set.
600 * @param rcRZ The return code if the operation cannot be
601 * performed in the current context.
602 */
603static VBOXSTRICTRC apicSendIntr(PVM pVM, PVMCPU pVCpu, uint8_t uVector, XAPICTRIGGERMODE enmTriggerMode,
604 XAPICDELIVERYMODE enmDeliveryMode, PCVMCPUSET pDestCpuSet, int rcRZ)
605{
606 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
607 VMCPUID const cCpus = pVM->cCpus;
608 switch (enmDeliveryMode)
609 {
610 case XAPICDELIVERYMODE_FIXED:
611 {
612 for (VMCPUID idCpu = 0; idCpu < cCpus; idCpu++)
613 {
614 if ( VMCPUSET_IS_PRESENT(pDestCpuSet, idCpu)
615 && apicIsEnabled(&pVM->aCpus[idCpu]))
616 APICPostInterrupt(&pVM->aCpus[idCpu], uVector, enmTriggerMode);
617 }
618 break;
619 }
620
621 case XAPICDELIVERYMODE_LOWEST_PRIO:
622 {
623 VMCPUID const idCpu = VMCPUSET_FIND_FIRST_PRESENT(pDestCpuSet);
624 if ( idCpu < pVM->cCpus
625 && apicIsEnabled(&pVM->aCpus[idCpu]))
626 APICPostInterrupt(&pVM->aCpus[idCpu], uVector, enmTriggerMode);
627 else
628 Log2(("APIC: apicSendIntr: No CPU found for lowest-priority delivery mode!\n"));
629 break;
630 }
631
632 case XAPICDELIVERYMODE_SMI:
633 {
634 for (VMCPUID idCpu = 0; idCpu < cCpus; idCpu++)
635 {
636 if (VMCPUSET_IS_PRESENT(pDestCpuSet, idCpu))
637 {
638 Log2(("APIC: apicSendIntr: Raising SMI on VCPU%u\n", idCpu));
639 APICSetInterruptFF(&pVM->aCpus[idCpu], PDMAPICIRQ_SMI);
640 }
641 }
642 break;
643 }
644
645 case XAPICDELIVERYMODE_NMI:
646 {
647 for (VMCPUID idCpu = 0; idCpu < cCpus; idCpu++)
648 {
649 if ( VMCPUSET_IS_PRESENT(pDestCpuSet, idCpu)
650 && apicIsEnabled(&pVM->aCpus[idCpu]))
651 {
652 Log2(("APIC: apicSendIntr: Raising NMI on VCPU%u\n", idCpu));
653 APICSetInterruptFF(&pVM->aCpus[idCpu], PDMAPICIRQ_NMI);
654 }
655 }
656 break;
657 }
658
659 case XAPICDELIVERYMODE_INIT:
660 {
661#ifdef IN_RING3
662 for (VMCPUID idCpu = 0; idCpu < cCpus; idCpu++)
663 if (VMCPUSET_IS_PRESENT(pDestCpuSet, idCpu))
664 {
665 Log2(("APIC: apicSendIntr: Issuing INIT to VCPU%u\n", idCpu));
666 VMMR3SendInitIpi(pVM, idCpu);
667 }
668#else
669 /* We need to return to ring-3 to deliver the INIT. */
670 rcStrict = rcRZ;
671#endif
672 break;
673 }
674
675 case XAPICDELIVERYMODE_STARTUP:
676 {
677#ifdef IN_RING3
678 for (VMCPUID idCpu = 0; idCpu < cCpus; idCpu++)
679 if (VMCPUSET_IS_PRESENT(pDestCpuSet, idCpu))
680 {
681 Log2(("APIC: apicSendIntr: Issuing SIPI to VCPU%u\n", idCpu));
682 VMMR3SendStartupIpi(pVM, idCpu, uVector);
683 }
684#else
685 /* We need to return to ring-3 to deliver the SIPI. */
686 rcStrict = rcRZ;
687 Log2(("APIC: apicSendIntr: SIPI issued, returning to RZ. rc=%Rrc\n", rcRZ));
688#endif
689 break;
690 }
691
692 case XAPICDELIVERYMODE_EXTINT:
693 {
694 for (VMCPUID idCpu = 0; idCpu < cCpus; idCpu++)
695 if (VMCPUSET_IS_PRESENT(pDestCpuSet, idCpu))
696 {
697 Log2(("APIC: apicSendIntr: Raising EXTINT on VCPU%u\n", idCpu));
698 APICSetInterruptFF(&pVM->aCpus[idCpu], PDMAPICIRQ_EXTINT);
699 }
700 break;
701 }
702
703 default:
704 {
705 AssertMsgFailed(("APIC: apicSendIntr: Unsupported delivery mode %#x (%s)\n", enmDeliveryMode,
706 apicGetDeliveryModeName(enmDeliveryMode)));
707 break;
708 }
709 }
710
711 /*
712 * If an illegal vector is programmed, set the 'send illegal vector' error here if the
713 * interrupt is being sent by an APIC.
714 *
715 * The 'receive illegal vector' will be set on the target APIC when the interrupt
716 * gets generated, see APICPostInterrupt().
717 *
718 * See Intel spec. 10.5.3 "Error Handling".
719 */
720 if ( rcStrict != rcRZ
721 && pVCpu)
722 {
723 /*
724 * Flag only errors when the delivery mode is fixed and not others.
725 *
726 * Ubuntu 10.04-3 amd64 live CD with 2 VCPUs gets upset as it sends an SIPI to the
727 * 2nd VCPU with vector 6 and checks the ESR for no errors, see @bugref{8245#c86}.
728 */
729 /** @todo The spec says this for LVT, but not explcitly for ICR-lo
730 * but it probably is true. */
731 if (enmDeliveryMode == XAPICDELIVERYMODE_FIXED)
732 {
733 if (RT_UNLIKELY(uVector <= XAPIC_ILLEGAL_VECTOR_END))
734 apicSetError(pVCpu, XAPIC_ESR_SEND_ILLEGAL_VECTOR);
735 }
736 }
737 return rcStrict;
738}
739
740
741/**
742 * Checks if this APIC belongs to a logical destination.
743 *
744 * @returns true if the APIC belongs to the logical
745 * destination, false otherwise.
746 * @param pVCpu The cross context virtual CPU structure.
747 * @param fDest The destination mask.
748 *
749 * @thread Any.
750 */
751static bool apicIsLogicalDest(PVMCPU pVCpu, uint32_t fDest)
752{
753 if (XAPIC_IN_X2APIC_MODE(pVCpu))
754 {
755 /*
756 * Flat logical mode is not supported in x2APIC mode.
757 * In clustered logical mode, the 32-bit logical ID in the LDR is interpreted as follows:
758 * - High 16 bits is the cluster ID.
759 * - Low 16 bits: each bit represents a unique APIC within the cluster.
760 */
761 PCX2APICPAGE pX2ApicPage = VMCPU_TO_CX2APICPAGE(pVCpu);
762 uint32_t const u32Ldr = pX2ApicPage->ldr.u32LogicalApicId;
763 if (X2APIC_LDR_GET_CLUSTER_ID(u32Ldr) == (fDest & X2APIC_LDR_CLUSTER_ID))
764 return RT_BOOL(u32Ldr & fDest & X2APIC_LDR_LOGICAL_ID);
765 return false;
766 }
767
768#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
769 /*
770 * In both flat and clustered logical mode, a destination mask of all set bits indicates a broadcast.
771 * See AMD spec. 16.6.1 "Receiving System and IPI Interrupts".
772 */
773 Assert(!XAPIC_IN_X2APIC_MODE(pVCpu));
774 if ((fDest & XAPIC_LDR_FLAT_LOGICAL_ID) == XAPIC_LDR_FLAT_LOGICAL_ID)
775 return true;
776
777 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
778 XAPICDESTFORMAT enmDestFormat = (XAPICDESTFORMAT)pXApicPage->dfr.u.u4Model;
779 if (enmDestFormat == XAPICDESTFORMAT_FLAT)
780 {
781 /* The destination mask is interpreted as a bitmap of 8 unique logical APIC IDs. */
782 uint8_t const u8Ldr = pXApicPage->ldr.u.u8LogicalApicId;
783 return RT_BOOL(u8Ldr & fDest & XAPIC_LDR_FLAT_LOGICAL_ID);
784 }
785
786 /*
787 * In clustered logical mode, the 8-bit logical ID in the LDR is interpreted as follows:
788 * - High 4 bits is the cluster ID.
789 * - Low 4 bits: each bit represents a unique APIC within the cluster.
790 */
791 Assert(enmDestFormat == XAPICDESTFORMAT_CLUSTER);
792 uint8_t const u8Ldr = pXApicPage->ldr.u.u8LogicalApicId;
793 if (XAPIC_LDR_CLUSTERED_GET_CLUSTER_ID(u8Ldr) == (fDest & XAPIC_LDR_CLUSTERED_CLUSTER_ID))
794 return RT_BOOL(u8Ldr & fDest & XAPIC_LDR_CLUSTERED_LOGICAL_ID);
795 return false;
796#else
797# error "Implement Pentium and P6 family APIC architectures"
798#endif
799}
800
801
802/**
803 * Figures out the set of destination CPUs for a given destination mode, format
804 * and delivery mode setting.
805 *
806 * @param pVM The cross context VM structure.
807 * @param fDestMask The destination mask.
808 * @param fBroadcastMask The broadcast mask.
809 * @param enmDestMode The destination mode.
810 * @param enmDeliveryMode The delivery mode.
811 * @param pDestCpuSet The destination CPU set to update.
812 */
813static void apicGetDestCpuSet(PVM pVM, uint32_t fDestMask, uint32_t fBroadcastMask, XAPICDESTMODE enmDestMode,
814 XAPICDELIVERYMODE enmDeliveryMode, PVMCPUSET pDestCpuSet)
815{
816 VMCPUSET_EMPTY(pDestCpuSet);
817
818 /*
819 * Physical destination mode only supports either a broadcast or a single target.
820 * - Broadcast with lowest-priority delivery mode is not supported[1], we deliver it
821 * as a regular broadcast like in fixed delivery mode.
822 * - For a single target, lowest-priority delivery mode makes no sense. We deliver
823 * to the target like in fixed delivery mode.
824 *
825 * [1] See Intel spec. 10.6.2.1 "Physical Destination Mode".
826 */
827 if ( enmDestMode == XAPICDESTMODE_PHYSICAL
828 && enmDeliveryMode == XAPICDELIVERYMODE_LOWEST_PRIO)
829 {
830 AssertMsgFailed(("APIC: Lowest-priority delivery using physical destination mode!"));
831 enmDeliveryMode = XAPICDELIVERYMODE_FIXED;
832 }
833
834 uint32_t const cCpus = pVM->cCpus;
835 if (enmDeliveryMode == XAPICDELIVERYMODE_LOWEST_PRIO)
836 {
837 Assert(enmDestMode == XAPICDESTMODE_LOGICAL);
838#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
839 VMCPUID idCpuLowestTpr = NIL_VMCPUID;
840 uint8_t u8LowestTpr = UINT8_C(0xff);
841 for (VMCPUID idCpu = 0; idCpu < cCpus; idCpu++)
842 {
843 PVMCPU pVCpuDest = &pVM->aCpus[idCpu];
844 if (apicIsLogicalDest(pVCpuDest, fDestMask))
845 {
846 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpuDest);
847 uint8_t const u8Tpr = pXApicPage->tpr.u8Tpr; /* PAV */
848
849 /*
850 * If there is a tie for lowest priority, the local APIC with the highest ID is chosen.
851 * Hence the use of "<=" in the check below.
852 * See AMD spec. 16.6.2 "Lowest Priority Messages and Arbitration".
853 */
854 if (u8Tpr <= u8LowestTpr)
855 {
856 u8LowestTpr = u8Tpr;
857 idCpuLowestTpr = idCpu;
858 }
859 }
860 }
861 if (idCpuLowestTpr != NIL_VMCPUID)
862 VMCPUSET_ADD(pDestCpuSet, idCpuLowestTpr);
863#else
864# error "Implement Pentium and P6 family APIC architectures"
865#endif
866 return;
867 }
868
869 /*
870 * x2APIC:
871 * - In both physical and logical destination mode, a destination mask of 0xffffffff implies a broadcast[1].
872 * xAPIC:
873 * - In physical destination mode, a destination mask of 0xff implies a broadcast[2].
874 * - In both flat and clustered logical mode, a destination mask of 0xff implies a broadcast[3].
875 *
876 * [1] See Intel spec. 10.12.9 "ICR Operation in x2APIC Mode".
877 * [2] See Intel spec. 10.6.2.1 "Physical Destination Mode".
878 * [2] See AMD spec. 16.6.1 "Receiving System and IPI Interrupts".
879 */
880 if ((fDestMask & fBroadcastMask) == fBroadcastMask)
881 {
882 VMCPUSET_FILL(pDestCpuSet);
883 return;
884 }
885
886 if (enmDestMode == XAPICDESTMODE_PHYSICAL)
887 {
888 /* The destination mask is interpreted as the physical APIC ID of a single target. */
889#if 1
890 /* Since our physical APIC ID is read-only to software, set the corresponding bit in the CPU set. */
891 if (RT_LIKELY(fDestMask < cCpus))
892 VMCPUSET_ADD(pDestCpuSet, fDestMask);
893#else
894 /* The physical APIC ID may not match our VCPU ID, search through the list of targets. */
895 for (VMCPUID idCpu = 0; idCpu < cCpus; idCpu++)
896 {
897 PVMCPU pVCpuDest = &pVM->aCpus[idCpu];
898 if (XAPIC_IN_X2APIC_MODE(pVCpuDest))
899 {
900 PCX2APICPAGE pX2ApicPage = VMCPU_TO_CX2APICPAGE(pVCpuDest);
901 if (pX2ApicPage->id.u32ApicId == fDestMask)
902 VMCPUSET_ADD(pDestCpuSet, pVCpuDest->idCpu);
903 }
904 else
905 {
906 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpuDest);
907 if (pXApicPage->id.u8ApicId == (uint8_t)fDestMask)
908 VMCPUSET_ADD(pDestCpuSet, pVCpuDest->idCpu);
909 }
910 }
911#endif
912 }
913 else
914 {
915 Assert(enmDestMode == XAPICDESTMODE_LOGICAL);
916
917 /* A destination mask of all 0's implies no target APICs (since it's interpreted as a bitmap or partial bitmap). */
918 if (RT_UNLIKELY(!fDestMask))
919 return;
920
921 /* The destination mask is interpreted as a bitmap of software-programmable logical APIC ID of the target APICs. */
922 for (VMCPUID idCpu = 0; idCpu < cCpus; idCpu++)
923 {
924 PVMCPU pVCpuDest = &pVM->aCpus[idCpu];
925 if (apicIsLogicalDest(pVCpuDest, fDestMask))
926 VMCPUSET_ADD(pDestCpuSet, pVCpuDest->idCpu);
927 }
928 }
929}
930
931
932/**
933 * Sends an Interprocessor Interrupt (IPI) using values from the Interrupt
934 * Command Register (ICR).
935 *
936 * @returns VBox status code.
937 * @param pVCpu The cross context virtual CPU structure.
938 * @param rcRZ The return code if the operation cannot be
939 * performed in the current context.
940 */
941DECLINLINE(VBOXSTRICTRC) apicSendIpi(PVMCPU pVCpu, int rcRZ)
942{
943 VMCPU_ASSERT_EMT(pVCpu);
944
945 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
946 XAPICDELIVERYMODE const enmDeliveryMode = (XAPICDELIVERYMODE)pXApicPage->icr_lo.u.u3DeliveryMode;
947 XAPICDESTMODE const enmDestMode = (XAPICDESTMODE)pXApicPage->icr_lo.u.u1DestMode;
948 XAPICINITLEVEL const enmInitLevel = (XAPICINITLEVEL)pXApicPage->icr_lo.u.u1Level;
949 XAPICTRIGGERMODE const enmTriggerMode = (XAPICTRIGGERMODE)pXApicPage->icr_lo.u.u1TriggerMode;
950 XAPICDESTSHORTHAND const enmDestShorthand = (XAPICDESTSHORTHAND)pXApicPage->icr_lo.u.u2DestShorthand;
951 uint8_t const uVector = pXApicPage->icr_lo.u.u8Vector;
952
953 PX2APICPAGE pX2ApicPage = VMCPU_TO_X2APICPAGE(pVCpu);
954 uint32_t const fDest = XAPIC_IN_X2APIC_MODE(pVCpu) ? pX2ApicPage->icr_hi.u32IcrHi : pXApicPage->icr_hi.u.u8Dest;
955
956#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
957 /*
958 * INIT Level De-assert is not support on Pentium 4 and Xeon processors.
959 * See AMD spec. 16.5 "Interprocessor Interrupts (IPI)" for a table of valid ICR combinations.
960 */
961 if (RT_UNLIKELY( enmDeliveryMode == XAPICDELIVERYMODE_INIT_LEVEL_DEASSERT
962 && enmInitLevel == XAPICINITLEVEL_DEASSERT
963 && enmTriggerMode == XAPICTRIGGERMODE_LEVEL))
964 {
965 Log2(("APIC%u: INIT level de-assert unsupported, ignoring!\n", pVCpu->idCpu));
966 return VINF_SUCCESS;
967 }
968#else
969# error "Implement Pentium and P6 family APIC architectures"
970#endif
971
972 /*
973 * The destination and delivery modes are ignored/by-passed when a destination shorthand is specified.
974 * See Intel spec. 10.6.2.3 "Broadcast/Self Delivery Mode".
975 */
976 VMCPUSET DestCpuSet;
977 switch (enmDestShorthand)
978 {
979 case XAPICDESTSHORTHAND_NONE:
980 {
981 PVM pVM = pVCpu->CTX_SUFF(pVM);
982 uint32_t const fBroadcastMask = XAPIC_IN_X2APIC_MODE(pVCpu) ? X2APIC_ID_BROADCAST_MASK : XAPIC_ID_BROADCAST_MASK;
983 apicGetDestCpuSet(pVM, fDest, fBroadcastMask, enmDestMode, enmDeliveryMode, &DestCpuSet);
984 break;
985 }
986
987 case XAPICDESTSHORTHAND_SELF:
988 {
989 VMCPUSET_EMPTY(&DestCpuSet);
990 VMCPUSET_ADD(&DestCpuSet, pVCpu->idCpu);
991 break;
992 }
993
994 case XAPIDDESTSHORTHAND_ALL_INCL_SELF:
995 {
996 VMCPUSET_FILL(&DestCpuSet);
997 break;
998 }
999
1000 case XAPICDESTSHORTHAND_ALL_EXCL_SELF:
1001 {
1002 VMCPUSET_FILL(&DestCpuSet);
1003 VMCPUSET_DEL(&DestCpuSet, pVCpu->idCpu);
1004 break;
1005 }
1006 }
1007
1008 return apicSendIntr(pVCpu->CTX_SUFF(pVM), pVCpu, uVector, enmTriggerMode, enmDeliveryMode, &DestCpuSet, rcRZ);
1009}
1010
1011
1012/**
1013 * Sets the Interrupt Command Register (ICR) high dword.
1014 *
1015 * @returns Strict VBox status code.
1016 * @param pVCpu The cross context virtual CPU structure.
1017 * @param uIcrHi The ICR high dword.
1018 */
1019static VBOXSTRICTRC apicSetIcrHi(PVMCPU pVCpu, uint32_t uIcrHi)
1020{
1021 VMCPU_ASSERT_EMT(pVCpu);
1022 Assert(!XAPIC_IN_X2APIC_MODE(pVCpu));
1023
1024 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1025 pXApicPage->icr_hi.all.u32IcrHi = uIcrHi & XAPIC_ICR_HI_DEST;
1026 Log2(("APIC%u: apicSetIcrHi: uIcrHi=%#RX32\n", pVCpu->idCpu, pXApicPage->icr_hi.all.u32IcrHi));
1027
1028 return VINF_SUCCESS;
1029}
1030
1031
1032/**
1033 * Sets the Interrupt Command Register (ICR) low dword.
1034 *
1035 * @returns Strict VBox status code.
1036 * @param pVCpu The cross context virtual CPU structure.
1037 * @param uIcrLo The ICR low dword.
1038 * @param rcRZ The return code if the operation cannot be performed
1039 * in the current context.
1040 */
1041static VBOXSTRICTRC apicSetIcrLo(PVMCPU pVCpu, uint32_t uIcrLo, int rcRZ)
1042{
1043 VMCPU_ASSERT_EMT(pVCpu);
1044
1045 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1046 pXApicPage->icr_lo.all.u32IcrLo = uIcrLo & XAPIC_ICR_LO_WR_VALID;
1047 Log2(("APIC%u: apicSetIcrLo: uIcrLo=%#RX32\n", pVCpu->idCpu, pXApicPage->icr_lo.all.u32IcrLo));
1048 STAM_COUNTER_INC(&pVCpu->apic.s.StatIcrLoWrite);
1049
1050 return apicSendIpi(pVCpu, rcRZ);
1051}
1052
1053
1054/**
1055 * Sets the Interrupt Command Register (ICR).
1056 *
1057 * @returns Strict VBox status code.
1058 * @param pVCpu The cross context virtual CPU structure.
1059 * @param u64Icr The ICR (High and Low combined).
1060 * @param rcRZ The return code if the operation cannot be performed
1061 * in the current context.
1062 */
1063static VBOXSTRICTRC apicSetIcr(PVMCPU pVCpu, uint64_t u64Icr, int rcRZ)
1064{
1065 VMCPU_ASSERT_EMT(pVCpu);
1066 Assert(XAPIC_IN_X2APIC_MODE(pVCpu));
1067
1068 /* Validate. */
1069 uint32_t const uLo = RT_LO_U32(u64Icr);
1070 if (RT_LIKELY(!(uLo & ~XAPIC_ICR_LO_WR_VALID)))
1071 {
1072 /* Update high dword first, then update the low dword which sends the IPI. */
1073 PX2APICPAGE pX2ApicPage = VMCPU_TO_X2APICPAGE(pVCpu);
1074 pX2ApicPage->icr_hi.u32IcrHi = RT_HI_U32(u64Icr);
1075 return apicSetIcrLo(pVCpu, uLo, rcRZ);
1076 }
1077 return apicMsrAccessError(pVCpu, MSR_IA32_X2APIC_ICR, APICMSRACCESS_WRITE_RSVD_BITS);
1078}
1079
1080
1081/**
1082 * Sets the Error Status Register (ESR).
1083 *
1084 * @returns Strict VBox status code.
1085 * @param pVCpu The cross context virtual CPU structure.
1086 * @param uEsr The ESR value.
1087 */
1088static VBOXSTRICTRC apicSetEsr(PVMCPU pVCpu, uint32_t uEsr)
1089{
1090 VMCPU_ASSERT_EMT(pVCpu);
1091
1092 Log2(("APIC%u: apicSetEsr: uEsr=%#RX32\n", pVCpu->idCpu, uEsr));
1093
1094 if ( XAPIC_IN_X2APIC_MODE(pVCpu)
1095 && (uEsr & ~XAPIC_ESR_WO_VALID))
1096 return apicMsrAccessError(pVCpu, MSR_IA32_X2APIC_ESR, APICMSRACCESS_WRITE_RSVD_BITS);
1097
1098 /*
1099 * Writes to the ESR causes the internal state to be updated in the register,
1100 * clearing the original state. See AMD spec. 16.4.6 "APIC Error Interrupts".
1101 */
1102 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1103 pXApicPage->esr.all.u32Errors = apicClearAllErrors(pVCpu);
1104 return VINF_SUCCESS;
1105}
1106
1107
1108/**
1109 * Updates the Processor Priority Register (PPR).
1110 *
1111 * @param pVCpu The cross context virtual CPU structure.
1112 */
1113static void apicUpdatePpr(PVMCPU pVCpu)
1114{
1115 VMCPU_ASSERT_EMT(pVCpu);
1116
1117 /* See Intel spec 10.8.3.1 "Task and Processor Priorities". */
1118 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1119 uint8_t const uIsrv = apicGetHighestSetBitInReg(&pXApicPage->isr, 0 /* rcNotFound */);
1120 uint8_t uPpr;
1121 if (XAPIC_TPR_GET_TP(pXApicPage->tpr.u8Tpr) >= XAPIC_PPR_GET_PP(uIsrv))
1122 uPpr = pXApicPage->tpr.u8Tpr;
1123 else
1124 uPpr = XAPIC_PPR_GET_PP(uIsrv);
1125 pXApicPage->ppr.u8Ppr = uPpr;
1126}
1127
1128
1129/**
1130 * Gets the Processor Priority Register (PPR).
1131 *
1132 * @returns The PPR value.
1133 * @param pVCpu The cross context virtual CPU structure.
1134 */
1135static uint8_t apicGetPpr(PVMCPU pVCpu)
1136{
1137 VMCPU_ASSERT_EMT(pVCpu);
1138 STAM_COUNTER_INC(&pVCpu->apic.s.StatTprRead);
1139
1140 /*
1141 * With virtualized APIC registers or with TPR virtualization, the hardware may
1142 * update ISR/TPR transparently. We thus re-calculate the PPR which may be out of sync.
1143 * See Intel spec. 29.2.2 "Virtual-Interrupt Delivery".
1144 *
1145 * In all other instances, whenever the TPR or ISR changes, we need to update the PPR
1146 * as well (e.g. like we do manually in apicR3InitIpi and by calling apicUpdatePpr).
1147 */
1148 PCAPIC pApic = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
1149 if (pApic->fVirtApicRegsEnabled) /** @todo re-think this */
1150 apicUpdatePpr(pVCpu);
1151 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
1152 return pXApicPage->ppr.u8Ppr;
1153}
1154
1155
1156/**
1157 * Sets the Task Priority Register (TPR).
1158 *
1159 * @returns Strict VBox status code.
1160 * @param pVCpu The cross context virtual CPU structure.
1161 * @param uTpr The TPR value.
1162 */
1163static VBOXSTRICTRC apicSetTpr(PVMCPU pVCpu, uint32_t uTpr)
1164{
1165 VMCPU_ASSERT_EMT(pVCpu);
1166
1167 Log2(("APIC%u: apicSetTpr: uTpr=%#RX32\n", pVCpu->idCpu, uTpr));
1168 STAM_COUNTER_INC(&pVCpu->apic.s.StatTprWrite);
1169
1170 if ( XAPIC_IN_X2APIC_MODE(pVCpu)
1171 && (uTpr & ~XAPIC_TPR_VALID))
1172 return apicMsrAccessError(pVCpu, MSR_IA32_X2APIC_TPR, APICMSRACCESS_WRITE_RSVD_BITS);
1173
1174 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1175 pXApicPage->tpr.u8Tpr = uTpr;
1176 apicUpdatePpr(pVCpu);
1177 apicSignalNextPendingIntr(pVCpu);
1178 return VINF_SUCCESS;
1179}
1180
1181
1182/**
1183 * Sets the End-Of-Interrupt (EOI) register.
1184 *
1185 * @returns Strict VBox status code.
1186 * @param pVCpu The cross context virtual CPU structure.
1187 * @param uEoi The EOI value.
1188 */
1189static VBOXSTRICTRC apicSetEoi(PVMCPU pVCpu, uint32_t uEoi)
1190{
1191 VMCPU_ASSERT_EMT(pVCpu);
1192
1193 Log2(("APIC%u: apicSetEoi: uEoi=%#RX32\n", pVCpu->idCpu, uEoi));
1194 STAM_COUNTER_INC(&pVCpu->apic.s.StatEoiWrite);
1195
1196 if ( XAPIC_IN_X2APIC_MODE(pVCpu)
1197 && (uEoi & ~XAPIC_EOI_WO_VALID))
1198 return apicMsrAccessError(pVCpu, MSR_IA32_X2APIC_EOI, APICMSRACCESS_WRITE_RSVD_BITS);
1199
1200 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1201 int isrv = apicGetHighestSetBitInReg(&pXApicPage->isr, -1 /* rcNotFound */);
1202 if (isrv >= 0)
1203 {
1204 Assert(isrv <= (int)UINT8_MAX);
1205 uint8_t const uVector = isrv;
1206 apicClearVectorInReg(&pXApicPage->isr, uVector);
1207 apicUpdatePpr(pVCpu);
1208 Log2(("APIC%u: apicSetEoi: Cleared interrupt from ISR. uVector=%#x\n", pVCpu->idCpu, uVector));
1209
1210 bool fLevelTriggered = apicTestVectorInReg(&pXApicPage->tmr, uVector);
1211 if (fLevelTriggered)
1212 {
1213 apicClearVectorInReg(&pXApicPage->tmr, uVector);
1214 apicBusBroadcastEoi(pVCpu, uVector);
1215 Log2(("APIC%u: apicSetEoi: Cleared level triggered interrupt from TMR. uVector=%#x\n", pVCpu->idCpu, uVector));
1216 }
1217
1218 apicSignalNextPendingIntr(pVCpu);
1219 }
1220
1221 return VINF_SUCCESS;
1222}
1223
1224
1225/**
1226 * Sets the Logical Destination Register (LDR).
1227 *
1228 * @returns Strict VBox status code.
1229 * @param pVCpu The cross context virtual CPU structure.
1230 * @param uLdr The LDR value.
1231 *
1232 * @remarks LDR is read-only in x2APIC mode.
1233 */
1234static VBOXSTRICTRC apicSetLdr(PVMCPU pVCpu, uint32_t uLdr)
1235{
1236 VMCPU_ASSERT_EMT(pVCpu);
1237 Assert(!XAPIC_IN_X2APIC_MODE(pVCpu));
1238
1239 Log2(("APIC%u: apicSetLdr: uLdr=%#RX32\n", pVCpu->idCpu, uLdr));
1240
1241 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1242 apicWriteRaw32(pXApicPage, XAPIC_OFF_LDR, uLdr & XAPIC_LDR_VALID);
1243 return VINF_SUCCESS;
1244}
1245
1246
1247/**
1248 * Sets the Destination Format Register (DFR).
1249 *
1250 * @returns Strict VBox status code.
1251 * @param pVCpu The cross context virtual CPU structure.
1252 * @param uDfr The DFR value.
1253 *
1254 * @remarks DFR is not available in x2APIC mode.
1255 */
1256static VBOXSTRICTRC apicSetDfr(PVMCPU pVCpu, uint32_t uDfr)
1257{
1258 VMCPU_ASSERT_EMT(pVCpu);
1259 Assert(!XAPIC_IN_X2APIC_MODE(pVCpu));
1260
1261 uDfr &= XAPIC_DFR_VALID;
1262 uDfr |= XAPIC_DFR_RSVD_MB1;
1263
1264 Log2(("APIC%u: apicSetDfr: uDfr=%#RX32\n", pVCpu->idCpu, uDfr));
1265
1266 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1267 apicWriteRaw32(pXApicPage, XAPIC_OFF_DFR, uDfr);
1268 return VINF_SUCCESS;
1269}
1270
1271
1272/**
1273 * Sets the Timer Divide Configuration Register (DCR).
1274 *
1275 * @returns Strict VBox status code.
1276 * @param pVCpu The cross context virtual CPU structure.
1277 * @param uTimerDcr The timer DCR value.
1278 */
1279static VBOXSTRICTRC apicSetTimerDcr(PVMCPU pVCpu, uint32_t uTimerDcr)
1280{
1281 VMCPU_ASSERT_EMT(pVCpu);
1282 if ( XAPIC_IN_X2APIC_MODE(pVCpu)
1283 && (uTimerDcr & ~XAPIC_TIMER_DCR_VALID))
1284 return apicMsrAccessError(pVCpu, MSR_IA32_X2APIC_TIMER_DCR, APICMSRACCESS_WRITE_RSVD_BITS);
1285
1286 Log2(("APIC%u: apicSetTimerDcr: uTimerDcr=%#RX32\n", pVCpu->idCpu, uTimerDcr));
1287
1288 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1289 apicWriteRaw32(pXApicPage, XAPIC_OFF_TIMER_DCR, uTimerDcr);
1290 return VINF_SUCCESS;
1291}
1292
1293
1294/**
1295 * Gets the timer's Current Count Register (CCR).
1296 *
1297 * @returns VBox status code.
1298 * @param pVCpu The cross context virtual CPU structure.
1299 * @param rcBusy The busy return code for the timer critical section.
1300 * @param puValue Where to store the LVT timer CCR.
1301 */
1302static VBOXSTRICTRC apicGetTimerCcr(PVMCPU pVCpu, int rcBusy, uint32_t *puValue)
1303{
1304 VMCPU_ASSERT_EMT(pVCpu);
1305 Assert(puValue);
1306
1307 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
1308 *puValue = 0;
1309
1310 /* In TSC-deadline mode, CCR returns 0, see Intel spec. 10.5.4.1 "TSC-Deadline Mode". */
1311 if (pXApicPage->lvt_timer.u.u2TimerMode == XAPIC_TIMER_MODE_TSC_DEADLINE)
1312 return VINF_SUCCESS;
1313
1314 /* If the initial-count register is 0, CCR returns 0 as it cannot exceed the ICR. */
1315 uint32_t const uInitialCount = pXApicPage->timer_icr.u32InitialCount;
1316 if (!uInitialCount)
1317 return VINF_SUCCESS;
1318
1319 /*
1320 * Reading the virtual-sync clock requires locking its timer because it's not
1321 * a simple atomic operation, see tmVirtualSyncGetEx().
1322 *
1323 * We also need to lock before reading the timer CCR, see apicR3TimerCallback().
1324 */
1325 PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1326 PTMTIMER pTimer = pApicCpu->CTX_SUFF(pTimer);
1327
1328 int rc = TMTimerLock(pTimer, rcBusy);
1329 if (rc == VINF_SUCCESS)
1330 {
1331 /* If the current-count register is 0, it implies the timer expired. */
1332 uint32_t const uCurrentCount = pXApicPage->timer_ccr.u32CurrentCount;
1333 if (uCurrentCount)
1334 {
1335 uint64_t const cTicksElapsed = TMTimerGet(pApicCpu->CTX_SUFF(pTimer)) - pApicCpu->u64TimerInitial;
1336 TMTimerUnlock(pTimer);
1337 uint8_t const uTimerShift = apicGetTimerShift(pXApicPage);
1338 uint64_t const uDelta = cTicksElapsed >> uTimerShift;
1339 if (uInitialCount > uDelta)
1340 *puValue = uInitialCount - uDelta;
1341 }
1342 else
1343 TMTimerUnlock(pTimer);
1344 }
1345 return rc;
1346}
1347
1348
1349/**
1350 * Sets the timer's Initial-Count Register (ICR).
1351 *
1352 * @returns Strict VBox status code.
1353 * @param pVCpu The cross context virtual CPU structure.
1354 * @param rcBusy The busy return code for the timer critical section.
1355 * @param uInitialCount The timer ICR.
1356 */
1357static VBOXSTRICTRC apicSetTimerIcr(PVMCPU pVCpu, int rcBusy, uint32_t uInitialCount)
1358{
1359 VMCPU_ASSERT_EMT(pVCpu);
1360
1361 PAPIC pApic = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
1362 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1363 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1364 PTMTIMER pTimer = pApicCpu->CTX_SUFF(pTimer);
1365
1366 Log2(("APIC%u: apicSetTimerIcr: uInitialCount=%#RX32\n", pVCpu->idCpu, uInitialCount));
1367 STAM_COUNTER_INC(&pApicCpu->StatTimerIcrWrite);
1368
1369 /* In TSC-deadline mode, timer ICR writes are ignored, see Intel spec. 10.5.4.1 "TSC-Deadline Mode". */
1370 if ( pApic->fSupportsTscDeadline
1371 && pXApicPage->lvt_timer.u.u2TimerMode == XAPIC_TIMER_MODE_TSC_DEADLINE)
1372 return VINF_SUCCESS;
1373
1374 /*
1375 * The timer CCR may be modified by apicR3TimerCallback() in parallel,
1376 * so obtain the lock -before- updating it here to be consistent with the
1377 * timer ICR. We rely on CCR being consistent in apicGetTimerCcr().
1378 */
1379 int rc = TMTimerLock(pTimer, rcBusy);
1380 if (rc == VINF_SUCCESS)
1381 {
1382 pXApicPage->timer_icr.u32InitialCount = uInitialCount;
1383 pXApicPage->timer_ccr.u32CurrentCount = uInitialCount;
1384 if (uInitialCount)
1385 APICStartTimer(pVCpu, uInitialCount);
1386 else
1387 APICStopTimer(pVCpu);
1388 TMTimerUnlock(pTimer);
1389 }
1390 return rc;
1391}
1392
1393
1394/**
1395 * Sets an LVT entry.
1396 *
1397 * @returns Strict VBox status code.
1398 * @param pVCpu The cross context virtual CPU structure.
1399 * @param offLvt The LVT entry offset in the xAPIC page.
1400 * @param uLvt The LVT value to set.
1401 */
1402static VBOXSTRICTRC apicSetLvtEntry(PVMCPU pVCpu, uint16_t offLvt, uint32_t uLvt)
1403{
1404 VMCPU_ASSERT_EMT(pVCpu);
1405
1406#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
1407 AssertMsg( offLvt == XAPIC_OFF_LVT_TIMER
1408 || offLvt == XAPIC_OFF_LVT_THERMAL
1409 || offLvt == XAPIC_OFF_LVT_PERF
1410 || offLvt == XAPIC_OFF_LVT_LINT0
1411 || offLvt == XAPIC_OFF_LVT_LINT1
1412 || offLvt == XAPIC_OFF_LVT_ERROR,
1413 ("APIC%u: apicSetLvtEntry: invalid offset, offLvt=%#RX16, uLvt=%#RX32\n", pVCpu->idCpu, offLvt, uLvt));
1414
1415 /*
1416 * If TSC-deadline mode isn't support, ignore the bit in xAPIC mode
1417 * and raise #GP(0) in x2APIC mode.
1418 */
1419 PCAPIC pApic = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
1420 if (offLvt == XAPIC_OFF_LVT_TIMER)
1421 {
1422 if ( !pApic->fSupportsTscDeadline
1423 && (uLvt & XAPIC_LVT_TIMER_TSCDEADLINE))
1424 {
1425 if (XAPIC_IN_X2APIC_MODE(pVCpu))
1426 return apicMsrAccessError(pVCpu, XAPIC_GET_X2APIC_MSR(offLvt), APICMSRACCESS_WRITE_RSVD_BITS);
1427 uLvt &= ~XAPIC_LVT_TIMER_TSCDEADLINE;
1428 /** @todo TSC-deadline timer mode transition */
1429 }
1430 }
1431
1432 /*
1433 * Validate rest of the LVT bits.
1434 */
1435 uint16_t const idxLvt = (offLvt - XAPIC_OFF_LVT_START) >> 4;
1436 AssertReturn(idxLvt < RT_ELEMENTS(g_au32LvtValidMasks), VERR_OUT_OF_RANGE);
1437
1438 /*
1439 * For x2APIC, disallow setting of invalid/reserved bits.
1440 * For xAPIC, mask out invalid/reserved bits (i.e. ignore them).
1441 */
1442 if ( XAPIC_IN_X2APIC_MODE(pVCpu)
1443 && (uLvt & ~g_au32LvtValidMasks[idxLvt]))
1444 return apicMsrAccessError(pVCpu, XAPIC_GET_X2APIC_MSR(offLvt), APICMSRACCESS_WRITE_RSVD_BITS);
1445
1446 uLvt &= g_au32LvtValidMasks[idxLvt];
1447
1448 /*
1449 * In the software-disabled state, LVT mask-bit must remain set and attempts to clear the mask
1450 * bit must be ignored. See Intel spec. 10.4.7.2 "Local APIC State After It Has Been Software Disabled".
1451 */
1452 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1453 if (!pXApicPage->svr.u.fApicSoftwareEnable)
1454 uLvt |= XAPIC_LVT_MASK;
1455
1456 /*
1457 * It is unclear whether we should signal a 'send illegal vector' error here and ignore updating
1458 * the LVT entry when the delivery mode is 'fixed'[1] or update it in addition to signaling the
1459 * error or not signal the error at all. For now, we'll allow setting illegal vectors into the LVT
1460 * but set the 'send illegal vector' error here. The 'receive illegal vector' error will be set if
1461 * the interrupt for the vector happens to be generated, see APICPostInterrupt().
1462 *
1463 * [1] See Intel spec. 10.5.2 "Valid Interrupt Vectors".
1464 */
1465 if (RT_UNLIKELY( XAPIC_LVT_GET_VECTOR(uLvt) <= XAPIC_ILLEGAL_VECTOR_END
1466 && XAPIC_LVT_GET_DELIVERY_MODE(uLvt) == XAPICDELIVERYMODE_FIXED))
1467 apicSetError(pVCpu, XAPIC_ESR_SEND_ILLEGAL_VECTOR);
1468
1469 Log2(("APIC%u: apicSetLvtEntry: offLvt=%#RX16 uLvt=%#RX32\n", pVCpu->idCpu, offLvt, uLvt));
1470
1471 apicWriteRaw32(pXApicPage, offLvt, uLvt);
1472 return VINF_SUCCESS;
1473#else
1474# error "Implement Pentium and P6 family APIC architectures"
1475#endif /* XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4 */
1476}
1477
1478
1479#if 0
1480/**
1481 * Sets an LVT entry in the extended LVT range.
1482 *
1483 * @returns VBox status code.
1484 * @param pVCpu The cross context virtual CPU structure.
1485 * @param offLvt The LVT entry offset in the xAPIC page.
1486 * @param uValue The LVT value to set.
1487 */
1488static int apicSetLvtExtEntry(PVMCPU pVCpu, uint16_t offLvt, uint32_t uLvt)
1489{
1490 VMCPU_ASSERT_EMT(pVCpu);
1491 AssertMsg(offLvt == XAPIC_OFF_CMCI, ("APIC%u: apicSetLvt1Entry: invalid offset %#RX16\n", pVCpu->idCpu, offLvt));
1492
1493 /** @todo support CMCI. */
1494 return VERR_NOT_IMPLEMENTED;
1495}
1496#endif
1497
1498
1499/**
1500 * Hints TM about the APIC timer frequency.
1501 *
1502 * @param pApicCpu The APIC CPU state.
1503 * @param uInitialCount The new initial count.
1504 * @param uTimerShift The new timer shift.
1505 * @thread Any.
1506 */
1507void apicHintTimerFreq(PAPICCPU pApicCpu, uint32_t uInitialCount, uint8_t uTimerShift)
1508{
1509 Assert(pApicCpu);
1510
1511 if ( pApicCpu->uHintedTimerInitialCount != uInitialCount
1512 || pApicCpu->uHintedTimerShift != uTimerShift)
1513 {
1514 uint32_t uHz;
1515 if (uInitialCount)
1516 {
1517 uint64_t cTicksPerPeriod = (uint64_t)uInitialCount << uTimerShift;
1518 uHz = TMTimerGetFreq(pApicCpu->CTX_SUFF(pTimer)) / cTicksPerPeriod;
1519 }
1520 else
1521 uHz = 0;
1522
1523 TMTimerSetFrequencyHint(pApicCpu->CTX_SUFF(pTimer), uHz);
1524 pApicCpu->uHintedTimerInitialCount = uInitialCount;
1525 pApicCpu->uHintedTimerShift = uTimerShift;
1526 }
1527}
1528
1529
1530/**
1531 * Reads an APIC register.
1532 *
1533 * @returns VBox status code.
1534 * @param pApicDev The APIC device instance.
1535 * @param pVCpu The cross context virtual CPU structure.
1536 * @param offReg The offset of the register being read.
1537 * @param puValue Where to store the register value.
1538 */
1539static int apicReadRegister(PAPICDEV pApicDev, PVMCPU pVCpu, uint16_t offReg, uint32_t *puValue)
1540{
1541 VMCPU_ASSERT_EMT(pVCpu);
1542 Assert(offReg <= XAPIC_OFF_MAX_VALID);
1543
1544 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1545 uint32_t uValue = 0;
1546 int rc = VINF_SUCCESS;
1547 switch (offReg)
1548 {
1549 case XAPIC_OFF_ID:
1550 case XAPIC_OFF_VERSION:
1551 case XAPIC_OFF_TPR:
1552 case XAPIC_OFF_EOI:
1553 case XAPIC_OFF_RRD:
1554 case XAPIC_OFF_LDR:
1555 case XAPIC_OFF_DFR:
1556 case XAPIC_OFF_SVR:
1557 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
1558 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
1559 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
1560 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
1561 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
1562 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
1563 case XAPIC_OFF_ESR:
1564 case XAPIC_OFF_ICR_LO:
1565 case XAPIC_OFF_ICR_HI:
1566 case XAPIC_OFF_LVT_TIMER:
1567#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
1568 case XAPIC_OFF_LVT_THERMAL:
1569#endif
1570 case XAPIC_OFF_LVT_PERF:
1571 case XAPIC_OFF_LVT_LINT0:
1572 case XAPIC_OFF_LVT_LINT1:
1573 case XAPIC_OFF_LVT_ERROR:
1574 case XAPIC_OFF_TIMER_ICR:
1575 case XAPIC_OFF_TIMER_DCR:
1576 {
1577 Assert( !XAPIC_IN_X2APIC_MODE(pVCpu)
1578 || ( offReg != XAPIC_OFF_DFR
1579 && offReg != XAPIC_OFF_ICR_HI
1580 && offReg != XAPIC_OFF_EOI));
1581 uValue = apicReadRaw32(pXApicPage, offReg);
1582 Log2(("APIC%u: apicReadRegister: offReg=%#x uValue=%#x\n", pVCpu->idCpu, offReg, uValue));
1583 break;
1584 }
1585
1586 case XAPIC_OFF_PPR:
1587 {
1588 uValue = apicGetPpr(pVCpu);
1589 break;
1590 }
1591
1592 case XAPIC_OFF_TIMER_CCR:
1593 {
1594 Assert(!XAPIC_IN_X2APIC_MODE(pVCpu));
1595 rc = VBOXSTRICTRC_VAL(apicGetTimerCcr(pVCpu, VINF_IOM_R3_MMIO_READ, &uValue));
1596 break;
1597 }
1598
1599 case XAPIC_OFF_APR:
1600 {
1601#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
1602 /* Unsupported on Pentium 4 and Xeon CPUs, invalid in x2APIC mode. */
1603 Assert(!XAPIC_IN_X2APIC_MODE(pVCpu));
1604#else
1605# error "Implement Pentium and P6 family APIC architectures"
1606#endif
1607 break;
1608 }
1609
1610 default:
1611 {
1612 Assert(!XAPIC_IN_X2APIC_MODE(pVCpu));
1613 rc = PDMDevHlpDBGFStop(pApicDev->CTX_SUFF(pDevIns), RT_SRC_POS, "VCPU[%u]: offReg=%#RX16\n", pVCpu->idCpu, offReg);
1614 apicSetError(pVCpu, XAPIC_ESR_ILLEGAL_REG_ADDRESS);
1615 break;
1616 }
1617 }
1618
1619 *puValue = uValue;
1620 return rc;
1621}
1622
1623
1624/**
1625 * Writes an APIC register.
1626 *
1627 * @returns Strict VBox status code.
1628 * @param pApicDev The APIC device instance.
1629 * @param pVCpu The cross context virtual CPU structure.
1630 * @param offReg The offset of the register being written.
1631 * @param uValue The register value.
1632 */
1633static VBOXSTRICTRC apicWriteRegister(PAPICDEV pApicDev, PVMCPU pVCpu, uint16_t offReg, uint32_t uValue)
1634{
1635 VMCPU_ASSERT_EMT(pVCpu);
1636 Assert(offReg <= XAPIC_OFF_MAX_VALID);
1637 Assert(!XAPIC_IN_X2APIC_MODE(pVCpu));
1638
1639 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1640 switch (offReg)
1641 {
1642 case XAPIC_OFF_TPR:
1643 {
1644 rcStrict = apicSetTpr(pVCpu, uValue);
1645 break;
1646 }
1647
1648 case XAPIC_OFF_LVT_TIMER:
1649#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
1650 case XAPIC_OFF_LVT_THERMAL:
1651#endif
1652 case XAPIC_OFF_LVT_PERF:
1653 case XAPIC_OFF_LVT_LINT0:
1654 case XAPIC_OFF_LVT_LINT1:
1655 case XAPIC_OFF_LVT_ERROR:
1656 {
1657 rcStrict = apicSetLvtEntry(pVCpu, offReg, uValue);
1658 break;
1659 }
1660
1661 case XAPIC_OFF_TIMER_ICR:
1662 {
1663 rcStrict = apicSetTimerIcr(pVCpu, VINF_IOM_R3_MMIO_WRITE, uValue);
1664 break;
1665 }
1666
1667 case XAPIC_OFF_EOI:
1668 {
1669 rcStrict = apicSetEoi(pVCpu, uValue);
1670 break;
1671 }
1672
1673 case XAPIC_OFF_LDR:
1674 {
1675 rcStrict = apicSetLdr(pVCpu, uValue);
1676 break;
1677 }
1678
1679 case XAPIC_OFF_DFR:
1680 {
1681 rcStrict = apicSetDfr(pVCpu, uValue);
1682 break;
1683 }
1684
1685 case XAPIC_OFF_SVR:
1686 {
1687 rcStrict = apicSetSvr(pVCpu, uValue);
1688 break;
1689 }
1690
1691 case XAPIC_OFF_ICR_LO:
1692 {
1693 rcStrict = apicSetIcrLo(pVCpu, uValue, VINF_IOM_R3_MMIO_WRITE);
1694 break;
1695 }
1696
1697 case XAPIC_OFF_ICR_HI:
1698 {
1699 rcStrict = apicSetIcrHi(pVCpu, uValue);
1700 break;
1701 }
1702
1703 case XAPIC_OFF_TIMER_DCR:
1704 {
1705 rcStrict = apicSetTimerDcr(pVCpu, uValue);
1706 break;
1707 }
1708
1709 case XAPIC_OFF_ESR:
1710 {
1711 rcStrict = apicSetEsr(pVCpu, uValue);
1712 break;
1713 }
1714
1715 case XAPIC_OFF_APR:
1716 case XAPIC_OFF_RRD:
1717 {
1718#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
1719 /* Unsupported on Pentium 4 and Xeon CPUs but writes do -not- set an illegal register access error. */
1720#else
1721# error "Implement Pentium and P6 family APIC architectures"
1722#endif
1723 break;
1724 }
1725
1726 /* Read-only, write ignored: */
1727 case XAPIC_OFF_VERSION:
1728 case XAPIC_OFF_ID:
1729 break;
1730
1731 /* Unavailable/reserved in xAPIC mode: */
1732 case X2APIC_OFF_SELF_IPI:
1733 /* Read-only registers: */
1734 case XAPIC_OFF_PPR:
1735 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
1736 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
1737 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
1738 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
1739 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
1740 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
1741 case XAPIC_OFF_TIMER_CCR:
1742 default:
1743 {
1744 rcStrict = PDMDevHlpDBGFStop(pApicDev->CTX_SUFF(pDevIns), RT_SRC_POS, "APIC%u: offReg=%#RX16\n", pVCpu->idCpu,
1745 offReg);
1746 apicSetError(pVCpu, XAPIC_ESR_ILLEGAL_REG_ADDRESS);
1747 break;
1748 }
1749 }
1750
1751 return rcStrict;
1752}
1753
1754
1755/**
1756 * @interface_method_impl{PDMAPICREG,pfnReadMsrR3}
1757 */
1758VMMDECL(VBOXSTRICTRC) APICReadMsr(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint32_t u32Reg, uint64_t *pu64Value)
1759{
1760 /*
1761 * Validate.
1762 */
1763 VMCPU_ASSERT_EMT(pVCpu);
1764 Assert(u32Reg >= MSR_IA32_X2APIC_START && u32Reg <= MSR_IA32_X2APIC_END);
1765 Assert(pu64Value);
1766
1767#ifndef IN_RING3
1768 PCAPIC pApic = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
1769 if (pApic->fRZEnabled)
1770 { /* likely */}
1771 else
1772 {
1773 return VINF_CPUM_R3_MSR_READ;
1774 }
1775#endif
1776
1777 STAM_COUNTER_INC(&pVCpu->apic.s.CTX_SUFF(StatMsrRead));
1778
1779 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1780 if (RT_LIKELY(XAPIC_IN_X2APIC_MODE(pVCpu)))
1781 {
1782 switch (u32Reg)
1783 {
1784 /* Special handling for x2APIC: */
1785 case MSR_IA32_X2APIC_ICR:
1786 {
1787 PCX2APICPAGE pX2ApicPage = VMCPU_TO_CX2APICPAGE(pVCpu);
1788 uint64_t const uHi = pX2ApicPage->icr_hi.u32IcrHi;
1789 uint64_t const uLo = pX2ApicPage->icr_lo.all.u32IcrLo;
1790 *pu64Value = RT_MAKE_U64(uLo, uHi);
1791 break;
1792 }
1793
1794 /* Special handling, compatible with xAPIC: */
1795 case MSR_IA32_X2APIC_TIMER_CCR:
1796 {
1797 uint32_t uValue;
1798 rcStrict = apicGetTimerCcr(pVCpu, VINF_CPUM_R3_MSR_READ, &uValue);
1799 *pu64Value = uValue;
1800 break;
1801 }
1802
1803 /* Special handling, compatible with xAPIC: */
1804 case MSR_IA32_X2APIC_PPR:
1805 {
1806 *pu64Value = apicGetPpr(pVCpu);
1807 break;
1808 }
1809
1810 /* Raw read, compatible with xAPIC: */
1811 case MSR_IA32_X2APIC_ID:
1812 case MSR_IA32_X2APIC_VERSION:
1813 case MSR_IA32_X2APIC_TPR:
1814 case MSR_IA32_X2APIC_LDR:
1815 case MSR_IA32_X2APIC_SVR:
1816 case MSR_IA32_X2APIC_ISR0: case MSR_IA32_X2APIC_ISR1: case MSR_IA32_X2APIC_ISR2: case MSR_IA32_X2APIC_ISR3:
1817 case MSR_IA32_X2APIC_ISR4: case MSR_IA32_X2APIC_ISR5: case MSR_IA32_X2APIC_ISR6: case MSR_IA32_X2APIC_ISR7:
1818 case MSR_IA32_X2APIC_TMR0: case MSR_IA32_X2APIC_TMR1: case MSR_IA32_X2APIC_TMR2: case MSR_IA32_X2APIC_TMR3:
1819 case MSR_IA32_X2APIC_TMR4: case MSR_IA32_X2APIC_TMR5: case MSR_IA32_X2APIC_TMR6: case MSR_IA32_X2APIC_TMR7:
1820 case MSR_IA32_X2APIC_IRR0: case MSR_IA32_X2APIC_IRR1: case MSR_IA32_X2APIC_IRR2: case MSR_IA32_X2APIC_IRR3:
1821 case MSR_IA32_X2APIC_IRR4: case MSR_IA32_X2APIC_IRR5: case MSR_IA32_X2APIC_IRR6: case MSR_IA32_X2APIC_IRR7:
1822 case MSR_IA32_X2APIC_ESR:
1823 case MSR_IA32_X2APIC_LVT_TIMER:
1824 case MSR_IA32_X2APIC_LVT_THERMAL:
1825 case MSR_IA32_X2APIC_LVT_PERF:
1826 case MSR_IA32_X2APIC_LVT_LINT0:
1827 case MSR_IA32_X2APIC_LVT_LINT1:
1828 case MSR_IA32_X2APIC_LVT_ERROR:
1829 case MSR_IA32_X2APIC_TIMER_ICR:
1830 case MSR_IA32_X2APIC_TIMER_DCR:
1831 {
1832 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1833 uint16_t const offReg = X2APIC_GET_XAPIC_OFF(u32Reg);
1834 *pu64Value = apicReadRaw32(pXApicPage, offReg);
1835 break;
1836 }
1837
1838 /* Write-only MSRs: */
1839 case MSR_IA32_X2APIC_SELF_IPI:
1840 case MSR_IA32_X2APIC_EOI:
1841 {
1842 rcStrict = apicMsrAccessError(pVCpu, u32Reg, APICMSRACCESS_READ_WRITE_ONLY);
1843 break;
1844 }
1845
1846 /* Reserved MSRs: */
1847 case MSR_IA32_X2APIC_LVT_CMCI:
1848 default:
1849 {
1850 rcStrict = apicMsrAccessError(pVCpu, u32Reg, APICMSRACCESS_READ_RSVD_OR_UNKNOWN);
1851 break;
1852 }
1853 }
1854 }
1855 else
1856 rcStrict = apicMsrAccessError(pVCpu, u32Reg, APICMSRACCESS_INVALID_READ_MODE);
1857
1858 return rcStrict;
1859}
1860
1861
1862/**
1863 * @interface_method_impl{PDMAPICREG,pfnWriteMsrR3}
1864 */
1865VMMDECL(VBOXSTRICTRC) APICWriteMsr(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint32_t u32Reg, uint64_t u64Value)
1866{
1867 /*
1868 * Validate.
1869 */
1870 VMCPU_ASSERT_EMT(pVCpu);
1871 Assert(u32Reg >= MSR_IA32_X2APIC_START && u32Reg <= MSR_IA32_X2APIC_END);
1872
1873#ifndef IN_RING3
1874 PCAPIC pApic = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
1875 if (pApic->fRZEnabled)
1876 { /* likely */ }
1877 else
1878 {
1879 return VINF_CPUM_R3_MSR_WRITE;
1880 }
1881#endif
1882
1883 STAM_COUNTER_INC(&pVCpu->apic.s.CTX_SUFF(StatMsrWrite));
1884
1885 /*
1886 * In x2APIC mode, we need to raise #GP(0) for writes to reserved bits, unlike MMIO
1887 * accesses where they are ignored. Hence, we need to validate each register before
1888 * invoking the generic/xAPIC write functions.
1889 *
1890 * Bits 63:32 of all registers except the ICR are reserved, we'll handle this common
1891 * case first and handle validating the remaining bits on a per-register basis.
1892 * See Intel spec. 10.12.1.2 "x2APIC Register Address Space".
1893 */
1894 if ( u32Reg != MSR_IA32_X2APIC_ICR
1895 && RT_HI_U32(u64Value))
1896 return apicMsrAccessError(pVCpu, u32Reg, APICMSRACCESS_WRITE_RSVD_BITS);
1897
1898 uint32_t u32Value = RT_LO_U32(u64Value);
1899 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1900 if (RT_LIKELY(XAPIC_IN_X2APIC_MODE(pVCpu)))
1901 {
1902 switch (u32Reg)
1903 {
1904 case MSR_IA32_X2APIC_TPR:
1905 {
1906 rcStrict = apicSetTpr(pVCpu, u32Value);
1907 break;
1908 }
1909
1910 case MSR_IA32_X2APIC_ICR:
1911 {
1912 rcStrict = apicSetIcr(pVCpu, u64Value, VINF_CPUM_R3_MSR_WRITE);
1913 break;
1914 }
1915
1916 case MSR_IA32_X2APIC_SVR:
1917 {
1918 rcStrict = apicSetSvr(pVCpu, u32Value);
1919 break;
1920 }
1921
1922 case MSR_IA32_X2APIC_ESR:
1923 {
1924 rcStrict = apicSetEsr(pVCpu, u32Value);
1925 break;
1926 }
1927
1928 case MSR_IA32_X2APIC_TIMER_DCR:
1929 {
1930 rcStrict = apicSetTimerDcr(pVCpu, u32Value);
1931 break;
1932 }
1933
1934 case MSR_IA32_X2APIC_LVT_TIMER:
1935 case MSR_IA32_X2APIC_LVT_THERMAL:
1936 case MSR_IA32_X2APIC_LVT_PERF:
1937 case MSR_IA32_X2APIC_LVT_LINT0:
1938 case MSR_IA32_X2APIC_LVT_LINT1:
1939 case MSR_IA32_X2APIC_LVT_ERROR:
1940 {
1941 rcStrict = apicSetLvtEntry(pVCpu, X2APIC_GET_XAPIC_OFF(u32Reg), u32Value);
1942 break;
1943 }
1944
1945 case MSR_IA32_X2APIC_TIMER_ICR:
1946 {
1947 rcStrict = apicSetTimerIcr(pVCpu, VINF_CPUM_R3_MSR_WRITE, u32Value);
1948 break;
1949 }
1950
1951 /* Write-only MSRs: */
1952 case MSR_IA32_X2APIC_SELF_IPI:
1953 {
1954 uint8_t const uVector = XAPIC_SELF_IPI_GET_VECTOR(u32Value);
1955 APICPostInterrupt(pVCpu, uVector, XAPICTRIGGERMODE_EDGE);
1956 rcStrict = VINF_SUCCESS;
1957 break;
1958 }
1959
1960 case MSR_IA32_X2APIC_EOI:
1961 {
1962 rcStrict = apicSetEoi(pVCpu, u32Value);
1963 break;
1964 }
1965
1966 /* Read-only MSRs: */
1967 case MSR_IA32_X2APIC_ID:
1968 case MSR_IA32_X2APIC_VERSION:
1969 case MSR_IA32_X2APIC_PPR:
1970 case MSR_IA32_X2APIC_LDR:
1971 case MSR_IA32_X2APIC_ISR0: case MSR_IA32_X2APIC_ISR1: case MSR_IA32_X2APIC_ISR2: case MSR_IA32_X2APIC_ISR3:
1972 case MSR_IA32_X2APIC_ISR4: case MSR_IA32_X2APIC_ISR5: case MSR_IA32_X2APIC_ISR6: case MSR_IA32_X2APIC_ISR7:
1973 case MSR_IA32_X2APIC_TMR0: case MSR_IA32_X2APIC_TMR1: case MSR_IA32_X2APIC_TMR2: case MSR_IA32_X2APIC_TMR3:
1974 case MSR_IA32_X2APIC_TMR4: case MSR_IA32_X2APIC_TMR5: case MSR_IA32_X2APIC_TMR6: case MSR_IA32_X2APIC_TMR7:
1975 case MSR_IA32_X2APIC_IRR0: case MSR_IA32_X2APIC_IRR1: case MSR_IA32_X2APIC_IRR2: case MSR_IA32_X2APIC_IRR3:
1976 case MSR_IA32_X2APIC_IRR4: case MSR_IA32_X2APIC_IRR5: case MSR_IA32_X2APIC_IRR6: case MSR_IA32_X2APIC_IRR7:
1977 case MSR_IA32_X2APIC_TIMER_CCR:
1978 {
1979 rcStrict = apicMsrAccessError(pVCpu, u32Reg, APICMSRACCESS_WRITE_READ_ONLY);
1980 break;
1981 }
1982
1983 /* Reserved MSRs: */
1984 case MSR_IA32_X2APIC_LVT_CMCI:
1985 default:
1986 {
1987 rcStrict = apicMsrAccessError(pVCpu, u32Reg, APICMSRACCESS_WRITE_RSVD_OR_UNKNOWN);
1988 break;
1989 }
1990 }
1991 }
1992 else
1993 rcStrict = apicMsrAccessError(pVCpu, u32Reg, APICMSRACCESS_INVALID_WRITE_MODE);
1994
1995 return rcStrict;
1996}
1997
1998
1999/**
2000 * @interface_method_impl{PDMAPICREG,pfnSetBaseMsrR3}
2001 */
2002VMMDECL(VBOXSTRICTRC) APICSetBaseMsr(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint64_t u64BaseMsr)
2003{
2004 Assert(pVCpu);
2005 NOREF(pDevIns);
2006
2007#ifdef IN_RING3
2008 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
2009 PAPIC pApic = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
2010 APICMODE enmOldMode = apicGetMode(pApicCpu->uApicBaseMsr);
2011 APICMODE enmNewMode = apicGetMode(u64BaseMsr);
2012 uint64_t uBaseMsr = pApicCpu->uApicBaseMsr;
2013
2014 Log2(("APIC%u: ApicSetBaseMsr: u64BaseMsr=%#RX64 enmNewMode=%s enmOldMode=%s\n", pVCpu->idCpu, u64BaseMsr,
2015 apicGetModeName(enmNewMode), apicGetModeName(enmOldMode)));
2016
2017 /*
2018 * We do not support re-mapping the APIC base address because:
2019 * - We'll have to manage all the mappings ourselves in the APIC (reference counting based unmapping etc.)
2020 * i.e. we can only unmap the MMIO region if no other APIC is mapped on that location.
2021 * - It's unclear how/if IOM can fallback to handling regions as regular memory (if the MMIO
2022 * region remains mapped but doesn't belong to the called VCPU's APIC).
2023 */
2024 /** @todo Handle per-VCPU APIC base relocation. */
2025 if (MSR_IA32_APICBASE_GET_ADDR(uBaseMsr) != MSR_IA32_APICBASE_ADDR)
2026 {
2027 LogRelMax(5, ("APIC%u: Attempt to relocate base to %#RGp, unsupported -> #GP(0)\n", pVCpu->idCpu,
2028 MSR_IA32_APICBASE_GET_ADDR(uBaseMsr)));
2029 return VERR_CPUM_RAISE_GP_0;
2030 }
2031
2032 /* Don't allow enabling xAPIC/x2APIC if the VM is configured with the APIC disabled. */
2033 if (pApic->enmOriginalMode == APICMODE_DISABLED)
2034 {
2035 LogRel(("APIC%u: Disallowing APIC base MSR write as the VM is configured with APIC disabled!\n",
2036 pVCpu->idCpu));
2037 return apicMsrAccessError(pVCpu, MSR_IA32_APICBASE, APICMSRACCESS_WRITE_DISALLOWED_CONFIG);
2038 }
2039
2040 /*
2041 * Act on state transition.
2042 */
2043 /** @todo We need to update the CPUID according to the state, which we
2044 * currently don't do as CPUMSetGuestCpuIdFeature() is setting
2045 * per-VM CPUID bits while we need per-VCPU specific bits. */
2046 if (enmNewMode != enmOldMode)
2047 {
2048 switch (enmNewMode)
2049 {
2050 case APICMODE_DISABLED:
2051 {
2052 /*
2053 * The APIC state needs to be reset (especially the APIC ID as x2APIC APIC ID bit layout
2054 * is different). We can start with a clean slate identical to the state after a power-up/reset.
2055 *
2056 * See Intel spec. 10.4.3 "Enabling or Disabling the Local APIC".
2057 *
2058 * We'll also manually manage the APIC base MSR here. We want a single-point of commit
2059 * at the end of this function rather than touching it in APICR3Reset. This means we also
2060 * need to update the CPUID leaf ourselves.
2061 */
2062 APICR3Reset(pVCpu, false /* fResetApicBaseMsr */);
2063 uBaseMsr &= ~(MSR_IA32_APICBASE_EN | MSR_IA32_APICBASE_EXTD);
2064 CPUMClearGuestCpuIdFeature(pVCpu->CTX_SUFF(pVM), CPUMCPUIDFEATURE_APIC);
2065 LogRel(("APIC%u: Switched mode to disabled\n", pVCpu->idCpu));
2066 break;
2067 }
2068
2069 case APICMODE_XAPIC:
2070 {
2071 if (enmOldMode != APICMODE_DISABLED)
2072 {
2073 LogRel(("APIC%u: Can only transition to xAPIC state from disabled state\n", pVCpu->idCpu));
2074 return apicMsrAccessError(pVCpu, MSR_IA32_APICBASE, APICMSRACCESS_WRITE_INVALID);
2075 }
2076
2077 uBaseMsr |= MSR_IA32_APICBASE_EN;
2078 CPUMSetGuestCpuIdFeature(pVCpu->CTX_SUFF(pVM), CPUMCPUIDFEATURE_APIC);
2079 LogRel(("APIC%u: Switched mode to xAPIC\n", pVCpu->idCpu));
2080 break;
2081 }
2082
2083 case APICMODE_X2APIC:
2084 {
2085 if (pApic->enmOriginalMode != APICMODE_X2APIC)
2086 {
2087 LogRel(("APIC%u: Disallowing transition to x2APIC mode as the VM is configured with the x2APIC disabled!\n",
2088 pVCpu->idCpu));
2089 return apicMsrAccessError(pVCpu, MSR_IA32_APICBASE, APICMSRACCESS_WRITE_INVALID);
2090 }
2091
2092 if (enmOldMode != APICMODE_XAPIC)
2093 {
2094 LogRel(("APIC%u: Can only transition to x2APIC state from xAPIC state\n", pVCpu->idCpu));
2095 return apicMsrAccessError(pVCpu, MSR_IA32_APICBASE, APICMSRACCESS_WRITE_INVALID);
2096 }
2097
2098 uBaseMsr |= MSR_IA32_APICBASE_EN | MSR_IA32_APICBASE_EXTD;
2099
2100 /*
2101 * The APIC ID needs updating when entering x2APIC mode.
2102 * Software written APIC ID in xAPIC mode isn't preserved.
2103 * The APIC ID becomes read-only to software in x2APIC mode.
2104 *
2105 * See Intel spec. 10.12.5.1 "x2APIC States".
2106 */
2107 PX2APICPAGE pX2ApicPage = VMCPU_TO_X2APICPAGE(pVCpu);
2108 ASMMemZero32(&pX2ApicPage->id, sizeof(pX2ApicPage->id));
2109 pX2ApicPage->id.u32ApicId = pVCpu->idCpu;
2110
2111 /*
2112 * LDR initialization occurs when entering x2APIC mode.
2113 * See Intel spec. 10.12.10.2 "Deriving Logical x2APIC ID from the Local x2APIC ID".
2114 */
2115 pX2ApicPage->ldr.u32LogicalApicId = ((pX2ApicPage->id.u32ApicId & UINT32_C(0xffff0)) << 16)
2116 | (UINT32_C(1) << pX2ApicPage->id.u32ApicId & UINT32_C(0xf));
2117
2118 LogRel(("APIC%u: Switched mode to x2APIC\n", pVCpu->idCpu));
2119 break;
2120 }
2121
2122 case APICMODE_INVALID:
2123 default:
2124 {
2125 Log(("APIC%u: Invalid state transition attempted\n", pVCpu->idCpu));
2126 return apicMsrAccessError(pVCpu, MSR_IA32_APICBASE, APICMSRACCESS_WRITE_INVALID);
2127 }
2128 }
2129 }
2130
2131 ASMAtomicWriteU64(&pApicCpu->uApicBaseMsr, uBaseMsr);
2132 return VINF_SUCCESS;
2133#else /* !IN_RING3 */
2134 return VINF_CPUM_R3_MSR_WRITE;
2135#endif /* IN_RING3 */
2136}
2137
2138
2139/**
2140 * @interface_method_impl{PDMAPICREG,pfnGetBaseMsrR3}
2141 */
2142VMMDECL(uint64_t) APICGetBaseMsr(PPDMDEVINS pDevIns, PVMCPU pVCpu)
2143{
2144 VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
2145
2146 PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
2147 return pApicCpu->uApicBaseMsr;
2148}
2149
2150
2151/**
2152 * @interface_method_impl{PDMAPICREG,pfnSetTprR3}
2153 */
2154VMMDECL(void) APICSetTpr(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint8_t u8Tpr)
2155{
2156 apicSetTpr(pVCpu, u8Tpr);
2157}
2158
2159
2160/**
2161 * Gets the highest priority pending interrupt.
2162 *
2163 * @returns true if any interrupt is pending, false otherwise.
2164 * @param pVCpu The cross context virtual CPU structure.
2165 * @param pu8PendingIntr Where to store the interrupt vector if the
2166 * interrupt is pending (optional, can be NULL).
2167 */
2168static bool apicGetHighestPendingInterrupt(PVMCPU pVCpu, uint8_t *pu8PendingIntr)
2169{
2170 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
2171 int const irrv = apicGetHighestSetBitInReg(&pXApicPage->irr, -1);
2172 if (irrv >= 0)
2173 {
2174 Assert(irrv <= (int)UINT8_MAX);
2175 if (pu8PendingIntr)
2176 *pu8PendingIntr = (uint8_t)irrv;
2177 return true;
2178 }
2179 return false;
2180}
2181
2182
2183/**
2184 * @interface_method_impl{PDMAPICREG,pfnGetTprR3}
2185 */
2186VMMDECL(uint8_t) APICGetTpr(PPDMDEVINS pDevIns, PVMCPU pVCpu, bool *pfPending, uint8_t *pu8PendingIntr)
2187{
2188 VMCPU_ASSERT_EMT(pVCpu);
2189 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
2190
2191 if (pfPending)
2192 {
2193 /*
2194 * Just return whatever the highest pending interrupt is in the IRR.
2195 * The caller is responsible for figuring out if it's masked by the TPR etc.
2196 */
2197 *pfPending = apicGetHighestPendingInterrupt(pVCpu, pu8PendingIntr);
2198 }
2199
2200 return pXApicPage->tpr.u8Tpr;
2201}
2202
2203
2204/**
2205 * @interface_method_impl{PDMAPICREG,pfnGetTimerFreqR3}
2206 */
2207VMMDECL(uint64_t) APICGetTimerFreq(PPDMDEVINS pDevIns)
2208{
2209 PVM pVM = PDMDevHlpGetVM(pDevIns);
2210 PVMCPU pVCpu = &pVM->aCpus[0];
2211 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
2212 uint64_t uTimer = TMTimerGetFreq(pApicCpu->CTX_SUFF(pTimer));
2213 return uTimer;
2214}
2215
2216
2217/**
2218 * @interface_method_impl{PDMAPICREG,pfnBusDeliverR3}
2219 * @remarks This is a private interface between the IOAPIC and the APIC.
2220 */
2221VMMDECL(int) APICBusDeliver(PPDMDEVINS pDevIns, uint8_t uDest, uint8_t uDestMode, uint8_t uDeliveryMode, uint8_t uVector,
2222 uint8_t uPolarity, uint8_t uTriggerMode, uint32_t uTagSrc)
2223{
2224 NOREF(uPolarity);
2225 NOREF(uTagSrc);
2226 PVM pVM = PDMDevHlpGetVM(pDevIns);
2227
2228 /*
2229 * The destination field (mask) in the IO APIC redirectable table entry is 8-bits.
2230 * Hence, the broadcast mask is 0xff.
2231 * See IO APIC spec. 3.2.4. "IOREDTBL[23:0] - I/O Redirectable Table Registers".
2232 */
2233 XAPICTRIGGERMODE enmTriggerMode = (XAPICTRIGGERMODE)uTriggerMode;
2234 XAPICDELIVERYMODE enmDeliveryMode = (XAPICDELIVERYMODE)uDeliveryMode;
2235 XAPICDESTMODE enmDestMode = (XAPICDESTMODE)uDestMode;
2236 uint32_t fDestMask = uDest;
2237 uint32_t fBroadcastMask = UINT32_C(0xff);
2238
2239 Log2(("APIC: apicBusDeliver: fDestMask=%#x enmDestMode=%s enmTriggerMode=%s enmDeliveryMode=%s uVector=%#x\n", fDestMask,
2240 apicGetDestModeName(enmDestMode), apicGetTriggerModeName(enmTriggerMode), apicGetDeliveryModeName(enmDeliveryMode),
2241 uVector));
2242
2243 VMCPUSET DestCpuSet;
2244 apicGetDestCpuSet(pVM, fDestMask, fBroadcastMask, enmDestMode, enmDeliveryMode, &DestCpuSet);
2245 VBOXSTRICTRC rcStrict = apicSendIntr(pVM, NULL /* pVCpu */, uVector, enmTriggerMode, enmDeliveryMode, &DestCpuSet,
2246 VINF_SUCCESS /* rcRZ */);
2247 return VBOXSTRICTRC_VAL(rcStrict);
2248}
2249
2250
2251/**
2252 * @interface_method_impl{PDMAPICREG,pfnLocalInterruptR3}
2253 * @remarks This is a private interface between the PIC and the APIC.
2254 */
2255VMMDECL(VBOXSTRICTRC) APICLocalInterrupt(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint8_t u8Pin, uint8_t u8Level, int rcRZ)
2256{
2257 NOREF(pDevIns);
2258 AssertReturn(u8Pin <= 1, VERR_INVALID_PARAMETER);
2259 AssertReturn(u8Level <= 1, VERR_INVALID_PARAMETER);
2260
2261 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
2262
2263 /* If the APIC is enabled, the interrupt is subject to LVT programming. */
2264 if (apicIsEnabled(pVCpu))
2265 {
2266 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
2267
2268 /* Pick the LVT entry corresponding to the interrupt pin. */
2269 static const uint16_t s_au16LvtOffsets[] =
2270 {
2271 XAPIC_OFF_LVT_LINT0,
2272 XAPIC_OFF_LVT_LINT1
2273 };
2274 Assert(u8Pin < RT_ELEMENTS(s_au16LvtOffsets));
2275 uint16_t const offLvt = s_au16LvtOffsets[u8Pin];
2276 uint32_t const uLvt = apicReadRaw32(pXApicPage, offLvt);
2277
2278 /* If software hasn't masked the interrupt in the LVT entry, proceed interrupt processing. */
2279 if (!XAPIC_LVT_IS_MASKED(uLvt))
2280 {
2281 XAPICDELIVERYMODE const enmDeliveryMode = XAPIC_LVT_GET_DELIVERY_MODE(uLvt);
2282 XAPICTRIGGERMODE enmTriggerMode = XAPIC_LVT_GET_TRIGGER_MODE(uLvt);
2283
2284 switch (enmDeliveryMode)
2285 {
2286 case XAPICDELIVERYMODE_INIT:
2287 {
2288 /** @todo won't work in R0/RC because callers don't care about rcRZ. */
2289 AssertMsgFailed(("INIT through LINT0/LINT1 is not yet supported\n"));
2290 /* fallthru */
2291 }
2292 case XAPICDELIVERYMODE_FIXED:
2293 {
2294 /* Level-sensitive interrupts are not supported for LINT1. See Intel spec. 10.5.1 "Local Vector Table". */
2295 if (offLvt == XAPIC_OFF_LVT_LINT1)
2296 enmTriggerMode = XAPICTRIGGERMODE_EDGE;
2297 /** @todo figure out what "If the local APIC is not used in conjunction with an I/O APIC and fixed
2298 delivery mode is selected; the Pentium 4, Intel Xeon, and P6 family processors will always
2299 use level-sensitive triggering, regardless if edge-sensitive triggering is selected."
2300 means. */
2301 /* fallthru */
2302 }
2303 case XAPICDELIVERYMODE_SMI:
2304 case XAPICDELIVERYMODE_NMI:
2305 {
2306 VMCPUSET DestCpuSet;
2307 VMCPUSET_EMPTY(&DestCpuSet);
2308 VMCPUSET_ADD(&DestCpuSet, pVCpu->idCpu);
2309 uint8_t const uVector = XAPIC_LVT_GET_VECTOR(uLvt);
2310 rcStrict = apicSendIntr(pVCpu->CTX_SUFF(pVM), pVCpu, uVector, enmTriggerMode, enmDeliveryMode, &DestCpuSet,
2311 rcRZ);
2312 break;
2313 }
2314
2315 case XAPICDELIVERYMODE_EXTINT:
2316 {
2317 Log2(("APIC%u: APICLocalInterrupt: %s ExtINT through LINT%u\n", pVCpu->idCpu,
2318 u8Level ? "Raising" : "Lowering", u8Pin));
2319 if (u8Level)
2320 APICSetInterruptFF(pVCpu, PDMAPICIRQ_EXTINT);
2321 else
2322 APICClearInterruptFF(pVCpu, PDMAPICIRQ_EXTINT);
2323 break;
2324 }
2325
2326 /* Reserved/unknown delivery modes: */
2327 case XAPICDELIVERYMODE_LOWEST_PRIO:
2328 case XAPICDELIVERYMODE_STARTUP:
2329 default:
2330 {
2331 rcStrict = VERR_INTERNAL_ERROR_3;
2332 AssertMsgFailed(("APIC%u: LocalInterrupt: Invalid delivery mode %#x (%s) on LINT%d\n", pVCpu->idCpu,
2333 enmDeliveryMode, apicGetDeliveryModeName(enmDeliveryMode), u8Pin));
2334 break;
2335 }
2336 }
2337 }
2338 }
2339 else
2340 {
2341 /* The APIC is hardware disabled. The CPU behaves as though there is no on-chip APIC. */
2342 if (u8Pin == 0)
2343 {
2344 /* LINT0 behaves as an external interrupt pin. */
2345 Log2(("APIC%u: APICLocalInterrupt: APIC hardware-disabled, %s INTR\n", pVCpu->idCpu,
2346 u8Level ? "raising" : "lowering"));
2347 if (u8Level)
2348 APICSetInterruptFF(pVCpu, PDMAPICIRQ_EXTINT);
2349 else
2350 APICClearInterruptFF(pVCpu, PDMAPICIRQ_EXTINT);
2351 }
2352 else
2353 {
2354 /* LINT1 behaves as NMI. */
2355 Log2(("APIC%u: APICLocalInterrupt: APIC hardware-disabled, raising NMI\n", pVCpu->idCpu));
2356 APICSetInterruptFF(pVCpu, PDMAPICIRQ_NMI);
2357 }
2358 }
2359
2360 return rcStrict;
2361}
2362
2363
2364/**
2365 * @interface_method_impl{PDMAPICREG,pfnGetInterruptR3}
2366 */
2367VMMDECL(int) APICGetInterrupt(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint8_t *pu8Vector, uint32_t *pu32TagSrc)
2368{
2369 VMCPU_ASSERT_EMT(pVCpu);
2370 Assert(pu8Vector);
2371 NOREF(pu32TagSrc);
2372
2373 LogFlow(("APIC%u: APICGetInterrupt:\n", pVCpu->idCpu));
2374
2375 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
2376 bool const fApicHwEnabled = apicIsEnabled(pVCpu);
2377 if ( fApicHwEnabled
2378 && pXApicPage->svr.u.fApicSoftwareEnable)
2379 {
2380 int const irrv = apicGetHighestSetBitInReg(&pXApicPage->irr, -1);
2381 if (RT_LIKELY(irrv >= 0))
2382 {
2383 Assert(irrv <= (int)UINT8_MAX);
2384 uint8_t const uVector = irrv;
2385
2386 /*
2387 * This can happen if the APIC receives an interrupt when the CPU has interrupts
2388 * disabled but the TPR is raised by the guest before re-enabling interrupts.
2389 */
2390 uint8_t const uTpr = pXApicPage->tpr.u8Tpr;
2391 if ( uTpr > 0
2392 && XAPIC_TPR_GET_TP(uVector) <= XAPIC_TPR_GET_TP(uTpr))
2393 {
2394 Log2(("APIC%u: APICGetInterrupt: Interrupt masked. uVector=%#x uTpr=%#x SpuriousVector=%#x\n", pVCpu->idCpu,
2395 uVector, uTpr, pXApicPage->svr.u.u8SpuriousVector));
2396 *pu8Vector = uVector;
2397 STAM_COUNTER_INC(&pVCpu->apic.s.StatMaskedByTpr);
2398 return VERR_APIC_INTR_MASKED_BY_TPR;
2399 }
2400
2401 /*
2402 * The PPR should be up-to-date at this point through apicSetEoi().
2403 * We're on EMT so no parallel updates possible.
2404 * Subject the pending vector to PPR prioritization.
2405 */
2406 uint8_t const uPpr = pXApicPage->ppr.u8Ppr;
2407 if ( !uPpr
2408 || XAPIC_PPR_GET_PP(uVector) > XAPIC_PPR_GET_PP(uPpr))
2409 {
2410 apicClearVectorInReg(&pXApicPage->irr, uVector);
2411 apicSetVectorInReg(&pXApicPage->isr, uVector);
2412 apicUpdatePpr(pVCpu);
2413 apicSignalNextPendingIntr(pVCpu);
2414
2415 Log2(("APIC%u: APICGetInterrupt: Valid Interrupt. uVector=%#x\n", pVCpu->idCpu, uVector));
2416 *pu8Vector = uVector;
2417 return VINF_SUCCESS;
2418 }
2419 else
2420 {
2421 STAM_COUNTER_INC(&pVCpu->apic.s.StatMaskedByPpr);
2422 Log2(("APIC%u: APICGetInterrupt: Interrupt's priority is not higher than the PPR. uVector=%#x PPR=%#x\n",
2423 pVCpu->idCpu, uVector, uPpr));
2424 }
2425 }
2426 else
2427 Log2(("APIC%u: APICGetInterrupt: No pending bits in IRR\n", pVCpu->idCpu));
2428 }
2429 else
2430 Log2(("APIC%u: APICGetInterrupt: APIC %s disabled\n", pVCpu->idCpu, !fApicHwEnabled ? "hardware" : "software"));
2431
2432 return VERR_APIC_INTR_NOT_PENDING;
2433}
2434
2435
2436/**
2437 * @callback_method_impl{FNIOMMMIOREAD}
2438 */
2439VMMDECL(int) APICReadMmio(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
2440{
2441 NOREF(pvUser);
2442 Assert(!(GCPhysAddr & 0xf));
2443 Assert(cb == 4);
2444
2445 PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
2446 PVMCPU pVCpu = PDMDevHlpGetVMCPU(pDevIns);
2447 uint16_t offReg = GCPhysAddr & 0xff0;
2448 uint32_t uValue = 0;
2449
2450 STAM_COUNTER_INC(&pVCpu->apic.s.CTX_SUFF(StatMmioRead));
2451
2452 int rc = apicReadRegister(pApicDev, pVCpu, offReg, &uValue);
2453 *(uint32_t *)pv = uValue;
2454
2455 Log2(("APIC%u: APICReadMmio: offReg=%#RX16 uValue=%#RX32\n", pVCpu->idCpu, offReg, uValue));
2456 return rc;
2457}
2458
2459
2460/**
2461 * @callback_method_impl{FNIOMMMIOWRITE}
2462 */
2463VMMDECL(int) APICWriteMmio(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
2464{
2465 NOREF(pvUser);
2466 Assert(!(GCPhysAddr & 0xf));
2467 Assert(cb == 4);
2468
2469 PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
2470 PVMCPU pVCpu = PDMDevHlpGetVMCPU(pDevIns);
2471 uint16_t offReg = GCPhysAddr & 0xff0;
2472 uint32_t uValue = *(uint32_t *)pv;
2473
2474 STAM_COUNTER_INC(&pVCpu->apic.s.CTX_SUFF(StatMmioWrite));
2475
2476 Log2(("APIC%u: APICWriteMmio: offReg=%#RX16 uValue=%#RX32\n", pVCpu->idCpu, offReg, uValue));
2477
2478 int rc = VBOXSTRICTRC_VAL(apicWriteRegister(pApicDev, pVCpu, offReg, uValue));
2479 return rc;
2480}
2481
2482
2483/**
2484 * Sets the interrupt pending force-flag and pokes the EMT if required.
2485 *
2486 * @param pVCpu The cross context virtual CPU structure.
2487 * @param enmType The IRQ type.
2488 */
2489VMMDECL(void) APICSetInterruptFF(PVMCPU pVCpu, PDMAPICIRQ enmType)
2490{
2491 PVM pVM = pVCpu->CTX_SUFF(pVM);
2492 PAPICDEV pApicDev = VM_TO_APICDEV(pVM);
2493 CTX_SUFF(pApicDev->pApicHlp)->pfnSetInterruptFF(pApicDev->CTX_SUFF(pDevIns), enmType, pVCpu->idCpu);
2494}
2495
2496
2497/**
2498 * Clears the interrupt pending force-flag.
2499 *
2500 * @param pVCpu The cross context virtual CPU structure.
2501 * @param enmType The IRQ type.
2502 */
2503VMMDECL(void) APICClearInterruptFF(PVMCPU pVCpu, PDMAPICIRQ enmType)
2504{
2505 PVM pVM = pVCpu->CTX_SUFF(pVM);
2506 PAPICDEV pApicDev = VM_TO_APICDEV(pVM);
2507 pApicDev->CTX_SUFF(pApicHlp)->pfnClearInterruptFF(pApicDev->CTX_SUFF(pDevIns), enmType, pVCpu->idCpu);
2508}
2509
2510
2511/**
2512 * Posts an interrupt to a target APIC.
2513 *
2514 * This function handles interrupts received from the system bus or
2515 * interrupts generated locally from the LVT or via a self IPI.
2516 *
2517 * Don't use this function to try and deliver ExtINT style interrupts.
2518 *
2519 * @param pVCpu The cross context virtual CPU structure.
2520 * @param uVector The vector of the interrupt to be posted.
2521 * @param enmTriggerMode The trigger mode of the interrupt.
2522 *
2523 * @thread Any.
2524 */
2525VMM_INT_DECL(void) APICPostInterrupt(PVMCPU pVCpu, uint8_t uVector, XAPICTRIGGERMODE enmTriggerMode)
2526{
2527 Assert(pVCpu);
2528 Assert(uVector > XAPIC_ILLEGAL_VECTOR_END);
2529
2530 PVM pVM = pVCpu->CTX_SUFF(pVM);
2531 PCAPIC pApic = VM_TO_APIC(pVM);
2532 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
2533
2534 STAM_PROFILE_START(&pApicCpu->StatPostIntr, a);
2535
2536 /*
2537 * Only post valid interrupt vectors.
2538 * See Intel spec. 10.5.2 "Valid Interrupt Vectors".
2539 */
2540 if (RT_LIKELY(uVector > XAPIC_ILLEGAL_VECTOR_END))
2541 {
2542 /*
2543 * If the interrupt is already pending in the IRR we can skip the
2544 * potential expensive operation of poking the guest EMT out of execution.
2545 */
2546 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
2547 if (!apicTestVectorInReg(&pXApicPage->irr, uVector)) /* PAV */
2548 {
2549 Log2(("APIC: APICPostInterrupt: SrcCpu=%u TargetCpu=%u uVector=%#x\n", VMMGetCpuId(pVM), pVCpu->idCpu, uVector));
2550 if (enmTriggerMode == XAPICTRIGGERMODE_EDGE)
2551 {
2552 if (pApic->fPostedIntrsEnabled)
2553 { /** @todo posted-interrupt call to hardware */ }
2554 else
2555 {
2556 apicSetVectorInPib(pApicCpu->CTX_SUFF(pvApicPib), uVector);
2557 uint32_t const fAlreadySet = apicSetNotificationBitInPib((PAPICPIB)pApicCpu->CTX_SUFF(pvApicPib));
2558 if (!fAlreadySet)
2559 {
2560 Log2(("APIC: APICPostInterrupt: Setting UPDATE_APIC FF for edge-triggered intr. uVector=%#x\n", uVector));
2561 APICSetInterruptFF(pVCpu, PDMAPICIRQ_UPDATE_PENDING);
2562 }
2563 }
2564 }
2565 else
2566 {
2567 /*
2568 * Level-triggered interrupts requires updating of the TMR and thus cannot be
2569 * delivered asynchronously.
2570 */
2571 apicSetVectorInPib(&pApicCpu->ApicPibLevel, uVector);
2572 uint32_t const fAlreadySet = apicSetNotificationBitInPib(&pApicCpu->ApicPibLevel);
2573 if (!fAlreadySet)
2574 {
2575 Log2(("APIC: APICPostInterrupt: Setting UPDATE_APIC FF for level-triggered intr. uVector=%#x\n", uVector));
2576 APICSetInterruptFF(pVCpu, PDMAPICIRQ_UPDATE_PENDING);
2577 }
2578 }
2579 }
2580 else
2581 {
2582 Log2(("APIC: APICPostInterrupt: SrcCpu=%u TargetCpu=%u. Vector %#x Already in IRR, skipping\n", VMMGetCpuId(pVM),
2583 pVCpu->idCpu, uVector));
2584 STAM_COUNTER_INC(&pApicCpu->StatPostIntrAlreadyPending);
2585 }
2586 }
2587 else
2588 apicSetError(pVCpu, XAPIC_ESR_RECV_ILLEGAL_VECTOR);
2589
2590 STAM_PROFILE_STOP(&pApicCpu->StatPostIntr, a);
2591}
2592
2593
2594/**
2595 * Starts the APIC timer.
2596 *
2597 * @param pVCpu The cross context virtual CPU structure.
2598 * @param uInitialCount The timer's Initial-Count Register (ICR), must be >
2599 * 0.
2600 * @thread Any.
2601 */
2602VMM_INT_DECL(void) APICStartTimer(PVMCPU pVCpu, uint32_t uInitialCount)
2603{
2604 Assert(pVCpu);
2605 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
2606 Assert(TMTimerIsLockOwner(pApicCpu->CTX_SUFF(pTimer)));
2607 Assert(uInitialCount > 0);
2608
2609 PCXAPICPAGE pXApicPage = APICCPU_TO_CXAPICPAGE(pApicCpu);
2610 uint8_t const uTimerShift = apicGetTimerShift(pXApicPage);
2611 uint64_t const cTicksToNext = (uint64_t)uInitialCount << uTimerShift;
2612
2613 Log2(("APIC%u: APICStartTimer: uInitialCount=%#RX32 uTimerShift=%u cTicksToNext=%RU64\n", pVCpu->idCpu, uInitialCount,
2614 uTimerShift, cTicksToNext));
2615
2616 /*
2617 * The assumption here is that the timer doesn't tick during this call
2618 * and thus setting a relative time to fire next is accurate. The advantage
2619 * however is updating u64TimerInitial 'atomically' while setting the next
2620 * tick.
2621 */
2622 PTMTIMER pTimer = pApicCpu->CTX_SUFF(pTimer);
2623 TMTimerSetRelative(pTimer, cTicksToNext, &pApicCpu->u64TimerInitial);
2624 apicHintTimerFreq(pApicCpu, uInitialCount, uTimerShift);
2625}
2626
2627
2628/**
2629 * Stops the APIC timer.
2630 *
2631 * @param pVCpu The cross context virtual CPU structure.
2632 * @thread Any.
2633 */
2634VMM_INT_DECL(void) APICStopTimer(PVMCPU pVCpu)
2635{
2636 Assert(pVCpu);
2637 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
2638 Assert(TMTimerIsLockOwner(pApicCpu->CTX_SUFF(pTimer)));
2639
2640 Log2(("APIC%u: APICStopTimer\n", pVCpu->idCpu));
2641
2642 PTMTIMER pTimer = pApicCpu->CTX_SUFF(pTimer);
2643 TMTimerStop(pTimer); /* This will reset the hint, no need to explicitly call TMTimerSetFrequencyHint(). */
2644 pApicCpu->uHintedTimerInitialCount = 0;
2645 pApicCpu->uHintedTimerShift = 0;
2646}
2647
2648
2649/**
2650 * Queues a pending interrupt as in-service.
2651 *
2652 * This function should only be needed without virtualized APIC
2653 * registers. With virtualized APIC registers, it's sufficient to keep
2654 * the interrupts pending in the IRR as the hardware takes care of
2655 * virtual interrupt delivery.
2656 *
2657 * @returns true if the interrupt was queued to in-service interrupts,
2658 * false otherwise.
2659 * @param pVCpu The cross context virtual CPU structure.
2660 * @param u8PendingIntr The pending interrupt to queue as
2661 * in-service.
2662 *
2663 * @remarks This assumes the caller has done the necessary checks and
2664 * is ready to take actually service the interrupt (TPR,
2665 * interrupt shadow etc.)
2666 */
2667VMMDECL(bool) APICQueueInterruptToService(PVMCPU pVCpu, uint8_t u8PendingIntr)
2668{
2669 VMCPU_ASSERT_EMT(pVCpu);
2670
2671 PVM pVM = pVCpu->CTX_SUFF(pVM);
2672 PAPIC pApic = VM_TO_APIC(pVM);
2673 Assert(!pApic->fVirtApicRegsEnabled);
2674 NOREF(pApic);
2675
2676 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
2677 bool const fIsPending = apicTestVectorInReg(&pXApicPage->irr, u8PendingIntr);
2678 if (fIsPending)
2679 {
2680 apicClearVectorInReg(&pXApicPage->irr, u8PendingIntr);
2681 apicSetVectorInReg(&pXApicPage->isr, u8PendingIntr);
2682 apicUpdatePpr(pVCpu);
2683 return true;
2684 }
2685 return false;
2686}
2687
2688
2689/**
2690 * De-queues a pending interrupt from in-service.
2691 *
2692 * This undoes APICQueueInterruptToService() for premature VM-exits before event
2693 * injection.
2694 *
2695 * @param pVCpu The cross context virtual CPU structure.
2696 * @param u8PendingIntr The pending interrupt to de-queue from
2697 * in-service.
2698 */
2699VMMDECL(void) APICDequeueInterruptFromService(PVMCPU pVCpu, uint8_t u8PendingIntr)
2700{
2701 VMCPU_ASSERT_EMT(pVCpu);
2702
2703 PVM pVM = pVCpu->CTX_SUFF(pVM);
2704 PAPIC pApic = VM_TO_APIC(pVM);
2705 Assert(!pApic->fVirtApicRegsEnabled);
2706 NOREF(pApic);
2707
2708 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
2709 bool const fInService = apicTestVectorInReg(&pXApicPage->isr, u8PendingIntr);
2710 if (fInService)
2711 {
2712 apicClearVectorInReg(&pXApicPage->isr, u8PendingIntr);
2713 apicSetVectorInReg(&pXApicPage->irr, u8PendingIntr);
2714 apicUpdatePpr(pVCpu);
2715 }
2716}
2717
2718
2719/**
2720 * Updates pending interrupts from the pending-interrupt bitmaps to the IRR.
2721 *
2722 * @param pVCpu The cross context virtual CPU structure.
2723 */
2724VMMDECL(void) APICUpdatePendingInterrupts(PVMCPU pVCpu)
2725{
2726 VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
2727
2728 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
2729 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
2730 bool fHasPendingIntrs = false;
2731
2732 Log3(("APIC%u: APICUpdatePendingInterrupts:\n", pVCpu->idCpu));
2733 STAM_PROFILE_START(&pApicCpu->StatUpdatePendingIntrs, a);
2734
2735 /* Update edge-triggered pending interrupts. */
2736 for (;;)
2737 {
2738 uint32_t const fAlreadySet = apicClearNotificationBitInPib((PAPICPIB)pApicCpu->CTX_SUFF(pvApicPib));
2739 if (!fAlreadySet)
2740 break;
2741
2742 PAPICPIB pPib = (PAPICPIB)pApicCpu->CTX_SUFF(pvApicPib);
2743 AssertCompile(RT_ELEMENTS(pXApicPage->irr.u) == 2 * RT_ELEMENTS(pPib->aVectorBitmap));
2744
2745 for (size_t idxPib = 0, idxReg = 0; idxPib < RT_ELEMENTS(pPib->aVectorBitmap); idxPib++, idxReg += 2)
2746 {
2747 uint64_t const u64Fragment = ASMAtomicXchgU64(&pPib->aVectorBitmap[idxPib], 0);
2748 if (u64Fragment)
2749 {
2750 uint32_t const u32FragmentLo = RT_LO_U32(u64Fragment);
2751 uint32_t const u32FragmentHi = RT_HI_U32(u64Fragment);
2752
2753 pXApicPage->irr.u[idxReg].u32Reg |= u32FragmentLo;
2754 pXApicPage->irr.u[idxReg + 1].u32Reg |= u32FragmentHi;
2755
2756 pXApicPage->tmr.u[idxReg].u32Reg &= ~u32FragmentLo;
2757 pXApicPage->tmr.u[idxReg + 1].u32Reg &= ~u32FragmentHi;
2758 fHasPendingIntrs = true;
2759 }
2760 }
2761 }
2762
2763 /* Update level-triggered pending interrupts. */
2764 for (;;)
2765 {
2766 uint32_t const fAlreadySet = apicClearNotificationBitInPib((PAPICPIB)&pApicCpu->ApicPibLevel);
2767 if (!fAlreadySet)
2768 break;
2769
2770 PAPICPIB pPib = (PAPICPIB)&pApicCpu->ApicPibLevel;
2771 AssertCompile(RT_ELEMENTS(pXApicPage->irr.u) == 2 * RT_ELEMENTS(pPib->aVectorBitmap));
2772
2773 for (size_t idxPib = 0, idxReg = 0; idxPib < RT_ELEMENTS(pPib->aVectorBitmap); idxPib++, idxReg += 2)
2774 {
2775 uint64_t const u64Fragment = ASMAtomicXchgU64(&pPib->aVectorBitmap[idxPib], 0);
2776 if (u64Fragment)
2777 {
2778 uint32_t const u32FragmentLo = RT_LO_U32(u64Fragment);
2779 uint32_t const u32FragmentHi = RT_HI_U32(u64Fragment);
2780
2781 pXApicPage->irr.u[idxReg].u32Reg |= u32FragmentLo;
2782 pXApicPage->irr.u[idxReg + 1].u32Reg |= u32FragmentHi;
2783
2784 pXApicPage->tmr.u[idxReg].u32Reg |= u32FragmentLo;
2785 pXApicPage->tmr.u[idxReg + 1].u32Reg |= u32FragmentHi;
2786 fHasPendingIntrs = true;
2787 }
2788 }
2789 }
2790
2791 STAM_PROFILE_STOP(&pApicCpu->StatUpdatePendingIntrs, a);
2792 Log3(("APIC%u: APICUpdatePendingInterrupts: fHasPendingIntrs=%RTbool\n", pVCpu->idCpu, fHasPendingIntrs));
2793
2794 if ( fHasPendingIntrs
2795 && !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC))
2796 apicSignalNextPendingIntr(pVCpu);
2797}
2798
2799
2800/**
2801 * Gets the highest priority pending interrupt.
2802 *
2803 * @returns true if any interrupt is pending, false otherwise.
2804 * @param pVCpu The cross context virtual CPU structure.
2805 * @param pu8PendingIntr Where to store the interrupt vector if the
2806 * interrupt is pending.
2807 */
2808VMMDECL(bool) APICGetHighestPendingInterrupt(PVMCPU pVCpu, uint8_t *pu8PendingIntr)
2809{
2810 VMCPU_ASSERT_EMT(pVCpu);
2811 return apicGetHighestPendingInterrupt(pVCpu, pu8PendingIntr);
2812}
2813
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