APICAll.cpp@ 61072

Last change on this file since 61072 was 61072, checked in by vboxsync, 9 years ago
VMM/APIC: Get rid of a couple of duplicate macros, and added a couple of ones to x86.h.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 96.1 KB

Line
1	/* $Id: APICAll.cpp 61072 2016-05-20 02:59:40Z vboxsync $ */
2	/** @file
3	* APIC - Advanced Programmable Interrupt Controller - All Contexts.
4	*/
5
6	/*
7	* Copyright (C) 2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_APIC
23	#include "APICInternal.h"
24	#include <VBox/vmm/pdmdev.h>
25	#include <VBox/vmm/vm.h>
26	#include <VBox/vmm/vmcpuset.h>
27
28	/*********************************************************************************************************************************
29	* Global Variables *
30	*********************************************************************************************************************************/
31	#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
32	/** An ordered array of valid LVT masks. */
33	static const uint32_t g_au32LvtValidMasks[] =
34	{
35	XAPIC_LVT_TIMER_VALID,
36	XAPIC_LVT_THERMAL_VALID,
37	XAPIC_LVT_PERF_VALID,
38	XAPIC_LVT_LINT_VALID, /* LINT0 */
39	XAPIC_LVT_LINT_VALID, /* LINT1 */
40	XAPIC_LVT_ERROR_VALID
41	};
42	#endif
43
44	#if 0
45	/** @todo CMCI */
46	static const uint32_t g_au32LvtExtValidMask[] =
47	{
48	XAPIC_LVT_CMCI_VALID
49	};
50	#endif
51
52
53	/**
54	* Checks if a vector is set in an APIC 256-bit sparse register.
55	*
56	* @returns true if the specified vector is set, false otherwise.
57	* @param pApicReg The APIC 256-bit spare register.
58	* @param uVector The vector to check if set.
59	*/
60	DECLINLINE(bool) apicTestVectorInReg(const volatile XAPIC256BITREG *pApicReg, uint8_t uVector)
61	{
62	const volatile uint8_t pbBitmap = (const volatile uint8_t )&pApicReg->u[0];
63	return ASMBitTest(pbBitmap + XAPIC_REG256_VECTOR_OFF(uVector), XAPIC_REG256_VECTOR_BIT(uVector));
64	}
65
66
67	/**
68	* Sets the vector in an APIC 256-bit sparse register.
69	*
70	* @param pApicReg The APIC 256-bit spare register.
71	* @param uVector The vector to set.
72	*/
73	DECLINLINE(void) apicSetVectorInReg(volatile XAPIC256BITREG *pApicReg, uint8_t uVector)
74	{
75	volatile uint8_t pbBitmap = (volatile uint8_t )&pApicReg->u[0];
76	ASMAtomicBitSet(pbBitmap + XAPIC_REG256_VECTOR_OFF(uVector), XAPIC_REG256_VECTOR_BIT(uVector));
77	}
78
79
80	/**
81	* Clears the vector in an APIC 256-bit sparse register.
82	*
83	* @param pApicReg The APIC 256-bit spare register.
84	* @param uVector The vector to clear.
85	*/
86	DECLINLINE(void) apicClearVectorInReg(volatile XAPIC256BITREG *pApicReg, uint8_t uVector)
87	{
88	volatile uint8_t pbBitmap = (volatile uint8_t )&pApicReg->u[0];
89	ASMAtomicBitClear(pbBitmap + XAPIC_REG256_VECTOR_OFF(uVector), XAPIC_REG256_VECTOR_BIT(uVector));
90	}
91
92
93	/**
94	* Checks if a vector is set in an APIC Pending-Interrupt Bitmap (PIB).
95	*
96	* @returns true if the specified vector is set, false otherwise.
97	* @param pvPib Opaque pointer to the PIB.
98	* @param uVector The vector to check if set.
99	*/
100	DECLINLINE(bool) apicTestVectorInPib(volatile void *pvPib, uint8_t uVector)
101	{
102	return ASMBitTest(pvPib, uVector);
103	}
104
105
106	/**
107	* Atomically sets the PIB notification bit.
108	*
109	* @returns non-zero if the bit was already set, 0 otherwise.
110	* @param pApicPib Pointer to the PIB.
111	*/
112	DECLINLINE(uint32_t) apicSetNotificationBitInPib(PAPICPIB pApicPib)
113	{
114	return ASMAtomicXchgU32(&pApicPib->fOutstandingNotification, RT_BIT_32(31));
115	}
116
117
118	/**
119	* Atomically tests and clears the PIB notification bit.
120	*
121	* @returns non-zero if the bit was already set, 0 otherwise.
122	* @param pApicPib Pointer to the PIB.
123	*/
124	DECLINLINE(uint32_t) apicClearNotificationBitInPib(PAPICPIB pApicPib)
125	{
126	return ASMAtomicXchgU32(&pApicPib->fOutstandingNotification, UINT32_C(0));
127	}
128
129
130	/**
131	* Sets the vector in an APIC Pending-Interrupt Bitmap (PIB).
132	*
133	* @param pvPib Opaque pointer to the PIB.
134	* @param uVector The vector to set.
135	*/
136	DECLINLINE(void) apicSetVectorInPib(volatile void *pvPib, uint8_t uVector)
137	{
138	ASMAtomicBitSet(pvPib, uVector);
139	}
140
141
142	/**
143	* Clears the vector in an APIC Pending-Interrupt Bitmap (PIB).
144	*
145	* @param pvPib Opaque pointer to the PIB.
146	* @param uVector The vector to clear.
147	*/
148	DECLINLINE(void) apicClearVectorInPib(volatile void *pvPib, uint8_t uVector)
149	{
150	ASMAtomicBitClear(pvPib, uVector);
151	}
152
153
154	/**
155	* Atomically OR's a fragment (32 vectors) into an APIC 256-bit sparse
156	* register.
157	*
158	* @param pApicReg The APIC 256-bit spare register.
159	* @param idxFragment The index of the 32-bit fragment in @a
160	* pApicReg.
161	* @param u32Fragment The 32-bit vector fragment to OR.
162	*/
163	DECLINLINE(void) apicOrVectorsToReg(volatile XAPIC256BITREG *pApicReg, size_t idxFragment, uint32_t u32Fragment)
164	{
165	Assert(idxFragment < RT_ELEMENTS(pApicReg->u));
166	ASMAtomicOrU32(&pApicReg->u[idxFragment].u32Reg, u32Fragment);
167	}
168
169
170	/**
171	* Atomically AND's a fragment (32 vectors) into an APIC
172	* 256-bit sparse register.
173	*
174	* @param pApicReg The APIC 256-bit spare register.
175	* @param idxFragment The index of the 32-bit fragment in @a
176	* pApicReg.
177	* @param u32Fragment The 32-bit vector fragment to AND.
178	*/
179	DECLINLINE(void) apicAndVectorsToReg(volatile XAPIC256BITREG *pApicReg, size_t idxFragment, uint32_t u32Fragment)
180	{
181	Assert(idxFragment < RT_ELEMENTS(pApicReg->u));
182	ASMAtomicAndU32(&pApicReg->u[idxFragment].u32Reg, u32Fragment);
183	}
184
185
186	/**
187	* Reports and returns appropriate error code for invalid MSR accesses.
188	*
189	* @returns Strict VBox status code.
190	* @retval VINF_CPUM_R3_MSR_WRITE if the MSR write could not be serviced in the
191	* current context (raw-mode or ring-0).
192	* @retval VINF_CPUM_R3_MSR_READ if the MSR read could not be serviced in the
193	* current context (raw-mode or ring-0).
194	* @retval VERR_CPUM_RAISE_GP_0 on failure, the caller is expected to take the
195	* appropriate actions.
196	*
197	* @param pVCpu The cross context virtual CPU structure.
198	* @param u32Reg The MSR being accessed.
199	* @param enmAccess The invalid-access type.
200	*/
201	static VBOXSTRICTRC apicMsrAccessError(PVMCPU pVCpu, uint32_t u32Reg, APICMSRACCESS enmAccess)
202	{
203	static struct
204	{
205	const char pszBefore; / The error message before printing the MSR index */
206	const char pszAfter; / The error message after printing the MSR index */
207	int rcRZ; /* The RZ error code */
208	} const s_aAccess[] =
209	{
210	{ "read MSR", " while not in x2APIC mode", VINF_CPUM_R3_MSR_READ },
211	{ "write MSR", " while not in x2APIC mode", VINF_CPUM_R3_MSR_WRITE },
212	{ "read reserved/unknown MSR", "", VINF_CPUM_R3_MSR_READ },
213	{ "write reserved/unknown MSR", "", VINF_CPUM_R3_MSR_WRITE },
214	{ "read write-only MSR", "", VINF_CPUM_R3_MSR_READ },
215	{ "write read-only MSR", "", VINF_CPUM_R3_MSR_WRITE },
216	{ "read reserved bits of MSR", "", VINF_CPUM_R3_MSR_READ },
217	{ "write reserved bits of MSR", "", VINF_CPUM_R3_MSR_WRITE },
218	{ "write an invalid value to MSR", "", VINF_CPUM_R3_MSR_WRITE },
219	{ "write MSR", "disallowed by configuration", VINF_CPUM_R3_MSR_WRITE }
220	};
221	AssertCompile(RT_ELEMENTS(s_aAccess) == APICMSRACCESS_COUNT);
222
223	size_t const i = enmAccess;
224	Assert(i < RT_ELEMENTS(s_aAccess));
225	#ifdef IN_RING3
226	LogRelMax(5, ("APIC%u: Attempt to %s (%#x)%s -> #GP(0)\n", pVCpu->idCpu, s_aAccess[i].pszBefore, u32Reg,
227	s_aAccess[i].pszAfter));
228	return VERR_CPUM_RAISE_GP_0;
229	#else
230	return s_aAccess[i].rcRZ;
231	#endif
232	}
233
234
235	/**
236	* Gets the descriptive APIC mode.
237	*
238	* @returns The name.
239	* @param enmMode The xAPIC mode.
240	*/
241	const char *apicGetModeName(APICMODE enmMode)
242	{
243	switch (enmMode)
244	{
245	case APICMODE_DISABLED: return "Disabled";
246	case APICMODE_XAPIC: return "xAPIC";
247	case APICMODE_X2APIC: return "x2APIC";
248	default: break;
249	}
250	return "Invalid";
251	}
252
253
254	/**
255	* Gets the descriptive destination format name.
256	*
257	* @returns The destination format name.
258	* @param enmDestFormat The destination format.
259	*/
260	const char *apicGetDestFormatName(XAPICDESTFORMAT enmDestFormat)
261	{
262	switch (enmDestFormat)
263	{
264	case XAPICDESTFORMAT_FLAT: return "Flat";
265	case XAPICDESTFORMAT_CLUSTER: return "Cluster";
266	default: break;
267	}
268	return "Invalid";
269	}
270
271
272	/**
273	* Gets the descriptive delivery mode name.
274	*
275	* @returns The delivery mode name.
276	* @param enmDeliveryMode The delivery mode.
277	*/
278	const char *apicGetDeliveryModeName(XAPICDELIVERYMODE enmDeliveryMode)
279	{
280	switch (enmDeliveryMode)
281	{
282	case XAPICDELIVERYMODE_FIXED: return "Fixed";
283	case XAPICDELIVERYMODE_LOWEST_PRIO: return "Lowest-priority";
284	case XAPICDELIVERYMODE_SMI: return "SMI";
285	case XAPICDELIVERYMODE_NMI: return "NMI";
286	case XAPICDELIVERYMODE_INIT: return "INIT";
287	case XAPICDELIVERYMODE_STARTUP: return "SIPI";
288	case XAPICDELIVERYMODE_EXTINT: return "ExtINT";
289	default: break;
290	}
291	return "Invalid";
292	}
293
294
295	/**
296	* Gets the descriptive destination mode name.
297	*
298	* @returns The destination mode name.
299	* @param enmDestMode The destination mode.
300	*/
301	const char *apicGetDestModeName(XAPICDESTMODE enmDestMode)
302	{
303	switch (enmDestMode)
304	{
305	case XAPICDESTMODE_PHYSICAL: return "Physical";
306	case XAPICDESTMODE_LOGICAL: return "Logical";
307	default: break;
308	}
309	return "Invalid";
310	}
311
312
313	/**
314	* Gets the descriptive trigger mode name.
315	*
316	* @returns The trigger mode name.
317	* @param enmTriggerMode The trigger mode.
318	*/
319	const char *apicGetTriggerModeName(XAPICTRIGGERMODE enmTriggerMode)
320	{
321	switch (enmTriggerMode)
322	{
323	case XAPICTRIGGERMODE_EDGE: return "Edge";
324	case XAPICTRIGGERMODE_LEVEL: return "Level";
325	default: break;
326	}
327	return "Invalid";
328	}
329
330
331	/**
332	* Gets the destination shorthand name.
333	*
334	* @returns The destination shorthand name.
335	* @param enmDestShorthand The destination shorthand.
336	*/
337	const char *apicGetDestShorthandName(XAPICDESTSHORTHAND enmDestShorthand)
338	{
339	switch (enmDestShorthand)
340	{
341	case XAPICDESTSHORTHAND_NONE: return "None";
342	case XAPICDESTSHORTHAND_SELF: return "Self";
343	case XAPIDDESTSHORTHAND_ALL_INCL_SELF: return "All including self";
344	case XAPICDESTSHORTHAND_ALL_EXCL_SELF: return "All excluding self";
345	default: break;
346	}
347	return "Invalid";
348	}
349
350
351	/**
352	* Gets the timer mode name.
353	*
354	* @returns The timer mode name.
355	* @param enmTimerMode The timer mode.
356	*/
357	const char *apicGetTimerModeName(XAPICTIMERMODE enmTimerMode)
358	{
359	switch (enmTimerMode)
360	{
361	case XAPICTIMERMODE_ONESHOT: return "One-shot";
362	case XAPICTIMERMODE_PERIODIC: return "Periodic";
363	case XAPICTIMERMODE_TSC_DEADLINE: return "TSC deadline";
364	default: break;
365	}
366	return "Invalid";
367	}
368
369
370	/**
371	* Gets the APIC mode given the base MSR value.
372	*
373	* @returns The APIC mode.
374	* @param uApicBaseMsr The APIC Base MSR value.
375	*/
376	APICMODE apicGetMode(uint64_t uApicBaseMsr)
377	{
378	uint32_t const uMode = (uApicBaseMsr >> 10) & UINT64_C(3);
379	APICMODE const enmMode = (APICMODE)uMode;
380	#ifdef VBOX_STRICT
381	/* Paranoia. */
382	switch (uMode)
383	{
384	case APICMODE_DISABLED:
385	case APICMODE_INVALID:
386	case APICMODE_XAPIC:
387	case APICMODE_X2APIC:
388	break;
389	default:
390	AssertMsgFailed(("Invalid mode"));
391	}
392	#endif
393	return enmMode;
394	}
395
396
397	/**
398	* Returns whether the APIC is hardware enabled or not.
399	*
400	* @returns true if enabled, false otherwise.
401	*/
402	DECLINLINE(bool) apicIsEnabled(PVMCPU pVCpu)
403	{
404	PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
405	return pApicCpu->uApicBaseMsr & MSR_IA32_APICBASE_EN;
406	}
407
408
409	/**
410	* Finds the most significant set bit in an APIC 256-bit sparse register.
411	*
412	* @returns @a rcNotFound if no bit was set, 0-255 otherwise.
413	* @param pReg The APIC 256-bit sparse register.
414	* @param rcNotFound What to return when no bit is set.
415	*/
416	static int apicGetHighestSetBit(volatile const XAPIC256BITREG *pReg, int rcNotFound)
417	{
418	ssize_t const cFragments = RT_ELEMENTS(pReg->u);
419	unsigned const uFragmentShift = 5;
420	AssertCompile(1 << uFragmentShift == sizeof(pReg->u[0].u32Reg) * 8);
421	for (ssize_t i = cFragments - 1; i >= 0; i--)
422	{
423	uint32_t const uFragment = pReg->u[i].u32Reg;
424	if (uFragment)
425	{
426	unsigned idxSetBit = ASMBitLastSetU32(uFragment);
427	--idxSetBit;
428	idxSetBit \|= i << uFragmentShift;
429	return idxSetBit;
430	}
431	}
432	return rcNotFound;
433	}
434
435
436	/**
437	* Reads a 32-bit register at a specified offset.
438	*
439	* @returns The value at the specified offset.
440	* @param pXApicPage The xAPIC page.
441	* @param offReg The offset of the register being read.
442	*/
443	DECLINLINE(uint32_t) apicReadRaw32(PCXAPICPAGE pXApicPage, uint16_t offReg)
444	{
445	Assert(offReg < sizeof(*pXApicPage) - sizeof(uint32_t));
446	uint8_t const pbXApic = (const uint8_t )pXApicPage;
447	uint32_t const uValue = (const uint32_t )(pbXApic + offReg);
448	return uValue;
449	}
450
451
452	/**
453	* Writes a 32-bit register at a specified offset.
454	*
455	* @param pXApicPage The xAPIC page.
456	* @param offReg The offset of the register being written.
457	* @param uReg The value of the register.
458	*/
459	DECLINLINE(void) apicWriteRaw32(PXAPICPAGE pXApicPage, uint16_t offReg, uint32_t uReg)
460	{
461	Assert(offReg < sizeof(*pXApicPage) - sizeof(uint32_t));
462	uint8_t pbXApic = (uint8_t )pXApicPage;
463	(uint32_t )(pbXApic + offReg) = uReg;
464	}
465
466
467	/**
468	* Sets an error in the internal ESR of the specified APIC.
469	*
470	* @param pVCpu The cross context virtual CPU structure.
471	* @param uError The error.
472	* @thread Any.
473	*/
474	DECLINLINE(void) apicSetError(PVMCPU pVCpu, uint32_t uError)
475	{
476	PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
477	ASMAtomicOrU32(&pApicCpu->uEsrInternal, uError);
478	}
479
480
481	/**
482	* Clears all errors in the internal ESR.
483	*
484	* @returns The value of the internal ESR before clearing.
485	* @param pVCpu The cross context virtual CPU structure.
486	*/
487	DECLINLINE(uint32_t) apicClearAllErrors(PVMCPU pVCpu)
488	{
489	VMCPU_ASSERT_EMT(pVCpu);
490	PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
491	return ASMAtomicXchgU32(&pApicCpu->uEsrInternal, 0);
492	}
493
494
495	/**
496	* Signals the guest if a pending interrupt is ready to be serviced.
497	*
498	* @param pVCpu The cross context virtual CPU structure.
499	*/
500	static void apicSignalNextPendingIntr(PVMCPU pVCpu)
501	{
502	VMCPU_ASSERT_EMT(pVCpu);
503
504	PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
505	if (pXApicPage->svr.u.fApicSoftwareEnable)
506	{
507	int const irrv = apicGetHighestSetBit(&pXApicPage->irr, -1 /* rcNotFound */);
508	if (irrv >= 0)
509	{
510	Assert(irrv <= (int)UINT8_MAX);
511	uint8_t const uVector = irrv;
512	uint8_t const uPpr = pXApicPage->ppr.u8Ppr;
513	if ( !uPpr
514	\|\| XAPIC_PPR_GET_PP(uVector) > XAPIC_PPR_GET_PP(uPpr))
515	{
516	Log2(("APIC%u: apicSignalNextPendingIntr: Signaling pending interrupt. uVector=%#x\n", pVCpu->idCpu, uVector));
517	APICSetInterruptFF(pVCpu, PDMAPICIRQ_HARDWARE);
518	}
519	else
520	{
521	Log2(("APIC%u: apicSignalNextPendingIntr: Nothing to signal. uVector=%#x uPpr=%#x uTpr=%#x\n", pVCpu->idCpu,
522	uVector, uPpr, pXApicPage->tpr.u8Tpr));
523	}
524	}
525	}
526	else
527	{
528	Log2(("APIC%u: apicSignalNextPendingIntr: APIC software-disabled, clearing pending interrupt\n", pVCpu->idCpu));
529	APICClearInterruptFF(pVCpu, PDMAPICIRQ_HARDWARE);
530	}
531	}
532
533
534	/**
535	* Sets the Spurious-Interrupt Vector Register (SVR).
536	*
537	* @returns Strict VBox status code.
538	* @param pVCpu The cross context virtual CPU structure.
539	* @param uSvr The SVR value.
540	*/
541	static VBOXSTRICTRC apicSetSvr(PVMCPU pVCpu, uint32_t uSvr)
542	{
543	VMCPU_ASSERT_EMT(pVCpu);
544
545	uint32_t uValidMask = XAPIC_SVR;
546	PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
547	if (pXApicPage->version.u.fEoiBroadcastSupression)
548	uValidMask \|= XAPIC_SVR_SUPRESS_EOI_BROADCAST;
549
550	if ( XAPIC_IN_X2APIC_MODE(pVCpu)
551	&& (uSvr & ~uValidMask))
552	return apicMsrAccessError(pVCpu, MSR_IA32_X2APIC_SVR, APICMSRACCESS_WRITE_RSVD_BITS);
553
554	Log2(("APIC%u: apicSetSvr: uSvr=%#RX32\n", pVCpu->idCpu, uSvr));
555	apicWriteRaw32(pXApicPage, XAPIC_OFF_SVR, uSvr);
556	if (!pXApicPage->svr.u.fApicSoftwareEnable)
557	{
558	/** @todo CMCI. */
559	pXApicPage->lvt_timer.u.u1Mask = 1;
560	#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
561	pXApicPage->lvt_thermal.u.u1Mask = 1;
562	#endif
563	pXApicPage->lvt_perf.u.u1Mask = 1;
564	pXApicPage->lvt_lint0.u.u1Mask = 1;
565	pXApicPage->lvt_lint1.u.u1Mask = 1;
566	pXApicPage->lvt_error.u.u1Mask = 1;
567	}
568
569	apicSignalNextPendingIntr(pVCpu);
570	return VINF_SUCCESS;
571	}
572
573
574	/**
575	* Sends an interrupt to one or more APICs.
576	*
577	* @returns Strict VBox status code.
578	* @param pVM The cross context VM structure.
579	* @param pVCpu The cross context virtual CPU structure, can be
580	* NULL if the source of the interrupt is not an
581	* APIC (for e.g. a bus).
582	* @param uVector The interrupt vector.
583	* @param enmTriggerMode The trigger mode.
584	* @param enmDeliveryMode The delivery mode.
585	* @param pDestCpuSet The destination CPU set.
586	* @param rcRZ The return code if the operation cannot be
587	* performed in the current context.
588	*/
589	static VBOXSTRICTRC apicSendIntr(PVM pVM, PVMCPU pVCpu, uint8_t uVector, XAPICTRIGGERMODE enmTriggerMode,
590	XAPICDELIVERYMODE enmDeliveryMode, PCVMCPUSET pDestCpuSet, int rcRZ)
591	{
592	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
593	VMCPUID const cCpus = pVM->cCpus;
594	switch (enmDeliveryMode)
595	{
596	case XAPICDELIVERYMODE_FIXED:
597	{
598	for (VMCPUID idCpu = 0; idCpu < cCpus; idCpu++)
599	{
600	if ( VMCPUSET_IS_PRESENT(pDestCpuSet, idCpu)
601	&& apicIsEnabled(&pVM->aCpus[idCpu]))
602	APICPostInterrupt(&pVM->aCpus[idCpu], uVector, enmTriggerMode);
603	}
604	break;
605	}
606
607	case XAPICDELIVERYMODE_LOWEST_PRIO:
608	{
609	VMCPUID const idCpu = VMCPUSET_FIND_FIRST_PRESENT(pDestCpuSet);
610	if ( idCpu < pVM->cCpus
611	&& apicIsEnabled(&pVM->aCpus[idCpu]))
612	APICPostInterrupt(&pVM->aCpus[idCpu], uVector, enmTriggerMode);
613	else
614	Log2(("APIC: apicSendIntr: No CPU found for lowest-priority delivery mode!\n"));
615	break;
616	}
617
618	case XAPICDELIVERYMODE_SMI:
619	{
620	for (VMCPUID idCpu = 0; idCpu < cCpus; idCpu++)
621	{
622	if (VMCPUSET_IS_PRESENT(pDestCpuSet, idCpu))
623	{
624	Log2(("APIC: apicSendIntr: Raising SMI on VCPU%u\n", idCpu));
625	APICSetInterruptFF(&pVM->aCpus[idCpu], PDMAPICIRQ_SMI);
626	}
627	}
628	break;
629	}
630
631	case XAPICDELIVERYMODE_NMI:
632	{
633	for (VMCPUID idCpu = 0; idCpu < cCpus; idCpu++)
634	{
635	if ( VMCPUSET_IS_PRESENT(pDestCpuSet, idCpu)
636	&& apicIsEnabled(&pVM->aCpus[idCpu]))
637	{
638	Log2(("APIC: apicSendIntr: Raising NMI on VCPU%u\n", idCpu));
639	APICSetInterruptFF(&pVM->aCpus[idCpu], PDMAPICIRQ_NMI);
640	}
641	}
642	break;
643	}
644
645	case XAPICDELIVERYMODE_INIT:
646	{
647	#ifdef IN_RING3
648	for (VMCPUID idCpu = 0; idCpu < cCpus; idCpu++)
649	if (VMCPUSET_IS_PRESENT(pDestCpuSet, idCpu))
650	{
651	Log2(("APIC: apicSendIntr: Issuing INIT to VCPU%u\n", idCpu));
652	VMMR3SendInitIpi(pVM, idCpu);
653	}
654	#else
655	/* We need to return to ring-3 to deliver the INIT. */
656	rcStrict = rcRZ;
657	#endif
658	break;
659	}
660
661	case XAPICDELIVERYMODE_STARTUP:
662	{
663	#ifdef IN_RING3
664	for (VMCPUID idCpu = 0; idCpu < cCpus; idCpu++)
665	if (VMCPUSET_IS_PRESENT(pDestCpuSet, idCpu))
666	{
667	Log2(("APIC: apicSendIntr: Issuing SIPI to VCPU%u\n", idCpu));
668	VMMR3SendStartupIpi(pVM, idCpu, uVector);
669	}
670	#else
671	/* We need to return to ring-3 to deliver the SIPI. */
672	rcStrict = rcRZ;
673	Log2(("APIC: apicSendIntr: SIPI issued, returning to RZ. rc=%Rrc\n", rcRZ));
674	#endif
675	break;
676	}
677
678	case XAPICDELIVERYMODE_EXTINT:
679	{
680	for (VMCPUID idCpu = 0; idCpu < cCpus; idCpu++)
681	if (VMCPUSET_IS_PRESENT(pDestCpuSet, idCpu))
682	{
683	Log2(("APIC: apicSendIntr: Raising EXTINT on VCPU%u\n", idCpu));
684	APICSetInterruptFF(&pVM->aCpus[idCpu], PDMAPICIRQ_EXTINT);
685	}
686	break;
687	}
688
689	default:
690	{
691	AssertMsgFailed(("APIC: apicSendIntr: Unsupported delivery mode %#x (%s)\n", enmDeliveryMode,
692	apicGetDeliveryModeName(enmDeliveryMode)));
693	break;
694	}
695	}
696
697	/*
698	* If an illegal vector is programmed, set the 'send illegal vector' error here if the
699	* interrupt is being sent by an APIC.
700	*
701	* The 'receive illegal vector' will be set on the target APIC when the interrupt
702	* gets generated, see APICPostInterrupt().
703	*
704	* See Intel spec. 10.5.3 "Error Handling".
705	*/
706	if ( rcStrict != rcRZ
707	&& pVCpu)
708	{
709	/*
710	* Flag only errors when the delivery mode is fixed and not others.
711	*
712	* Ubuntu 10.04-3 amd64 live CD with 2 VCPUs gets upset as it sends an SIPI to the
713	* 2nd VCPU with vector 6 and checks the ESR for no errors, see @bugref{8245#c86}.
714	*/
715	/** @todo The spec says this for LVT, but not explcitly for ICR-lo
716	* but it probably is true. */
717	if (enmDeliveryMode == XAPICDELIVERYMODE_FIXED)
718	{
719	if (RT_UNLIKELY(uVector <= XAPIC_ILLEGAL_VECTOR_END))
720	apicSetError(pVCpu, XAPIC_ESR_SEND_ILLEGAL_VECTOR);
721	}
722	}
723	return rcStrict;
724	}
725
726
727	/**
728	* Checks if this APIC belongs to a logical destination.
729	*
730	* @returns true if the APIC belongs to the logical
731	* destination, false otherwise.
732	* @param pVCpu The cross context virtual CPU structure.
733	* @param fDest The destination mask.
734	*
735	* @thread Any.
736	*/
737	static bool apicIsLogicalDest(PVMCPU pVCpu, uint32_t fDest)
738	{
739	if (XAPIC_IN_X2APIC_MODE(pVCpu))
740	{
741	/*
742	* Flat logical mode is not supported in x2APIC mode.
743	* In clustered logical mode, the 32-bit logical ID in the LDR is interpreted as follows:
744	* - High 16 bits is the cluster ID.
745	* - Low 16 bits: each bit represents a unique APIC within the cluster.
746	*/
747	PCX2APICPAGE pX2ApicPage = VMCPU_TO_CX2APICPAGE(pVCpu);
748	uint32_t const u32Ldr = pX2ApicPage->ldr.u32LogicalApicId;
749	if (X2APIC_LDR_GET_CLUSTER_ID(u32Ldr) == (fDest & X2APIC_LDR_CLUSTER_ID))
750	return RT_BOOL(u32Ldr & fDest & X2APIC_LDR_LOGICAL_ID);
751	return false;
752	}
753
754	#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
755	/*
756	* In both flat and clustered logical mode, a destination mask of all set bits indicates a broadcast.
757	* See AMD spec. 16.6.1 "Receiving System and IPI Interrupts".
758	*/
759	Assert(!XAPIC_IN_X2APIC_MODE(pVCpu));
760	if ((fDest & XAPIC_LDR_FLAT_LOGICAL_ID) == XAPIC_LDR_FLAT_LOGICAL_ID)
761	return true;
762
763	PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
764	XAPICDESTFORMAT enmDestFormat = (XAPICDESTFORMAT)pXApicPage->dfr.u.u4Model;
765	if (enmDestFormat == XAPICDESTFORMAT_FLAT)
766	{
767	/* The destination mask is interpreted as a bitmap of 8 unique logical APIC IDs. */
768	uint8_t const u8Ldr = pXApicPage->ldr.u.u8LogicalApicId;
769	return RT_BOOL(u8Ldr & fDest & XAPIC_LDR_FLAT_LOGICAL_ID);
770	}
771
772	/*
773	* In clustered logical mode, the 8-bit logical ID in the LDR is interpreted as follows:
774	* - High 4 bits is the cluster ID.
775	* - Low 4 bits: each bit represents a unique APIC within the cluster.
776	*/
777	Assert(enmDestFormat == XAPICDESTFORMAT_CLUSTER);
778	uint8_t const u8Ldr = pXApicPage->ldr.u.u8LogicalApicId;
779	if (XAPIC_LDR_CLUSTERED_GET_CLUSTER_ID(u8Ldr) == (fDest & XAPIC_LDR_CLUSTERED_CLUSTER_ID))
780	return RT_BOOL(u8Ldr & fDest & XAPIC_LDR_CLUSTERED_LOGICAL_ID);
781	return false;
782	#else
783	# error "Implement Pentium and P6 family APIC architectures"
784	#endif
785	}
786
787
788	/**
789	* Figures out the set of destination CPUs for a given destination mode, format
790	* and delivery mode setting.
791	*
792	* @param pVM The cross context VM structure.
793	* @param fDestMask The destination mask.
794	* @param fBroadcastMask The broadcast mask.
795	* @param enmDestMode The destination mode.
796	* @param enmDeliveryMode The delivery mode.
797	* @param pDestCpuSet The destination CPU set to update.
798	*/
799	static void apicGetDestCpuSet(PVM pVM, uint32_t fDestMask, uint32_t fBroadcastMask, XAPICDESTMODE enmDestMode,
800	XAPICDELIVERYMODE enmDeliveryMode, PVMCPUSET pDestCpuSet)
801	{
802	VMCPUSET_EMPTY(pDestCpuSet);
803
804	/*
805	* Physical destination mode only supports either a broadcast or a single target.
806	* - Broadcast with lowest-priority delivery mode is not supported[1], we deliver it
807	* as a regular broadcast like in fixed delivery mode.
808	* - For a single target, lowest-priority delivery mode makes no sense. We deliver
809	* to the target like in fixed delivery mode.
810	*
811	* [1] See Intel spec. 10.6.2.1 "Physical Destination Mode".
812	*/
813	if ( enmDestMode == XAPICDESTMODE_PHYSICAL
814	&& enmDeliveryMode == XAPICDELIVERYMODE_LOWEST_PRIO)
815	{
816	AssertMsgFailed(("APIC: Lowest-priority delivery using physical destination mode!"));
817	enmDeliveryMode = XAPICDELIVERYMODE_FIXED;
818	}
819
820	uint32_t const cCpus = pVM->cCpus;
821	if (enmDeliveryMode == XAPICDELIVERYMODE_LOWEST_PRIO)
822	{
823	Assert(enmDestMode == XAPICDESTMODE_LOGICAL);
824	#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
825	VMCPUID idCpuLowestTpr = NIL_VMCPUID;
826	uint8_t u8LowestTpr = UINT8_C(0xff);
827	for (VMCPUID idCpu = 0; idCpu < cCpus; idCpu++)
828	{
829	PVMCPU pVCpuDest = &pVM->aCpus[idCpu];
830	if (apicIsLogicalDest(pVCpuDest, fDestMask))
831	{
832	PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpuDest);
833	uint8_t const u8Tpr = pXApicPage->tpr.u8Tpr; /* PAV */
834
835	/*
836	* If there is a tie for lowest priority, the local APIC with the highest ID is chosen.
837	* Hence the use of "<=" in the check below.
838	* See AMD spec. 16.6.2 "Lowest Priority Messages and Arbitration".
839	*/
840	if (u8Tpr <= u8LowestTpr)
841	{
842	u8LowestTpr = u8Tpr;
843	idCpuLowestTpr = idCpu;
844	}
845	}
846	}
847	if (idCpuLowestTpr != NIL_VMCPUID)
848	VMCPUSET_ADD(pDestCpuSet, idCpuLowestTpr);
849	#else
850	# error "Implement Pentium and P6 family APIC architectures"
851	#endif
852	return;
853	}
854
855	/*
856	* x2APIC:
857	* - In both physical and logical destination mode, a destination mask of 0xffffffff implies a broadcast[1].
858	* xAPIC:
859	* - In physical destination mode, a destination mask of 0xff implies a broadcast[2].
860	* - In both flat and clustered logical mode, a destination mask of 0xff implies a broadcast[3].
861	*
862	* [1] See Intel spec. 10.12.9 "ICR Operation in x2APIC Mode".
863	* [2] See Intel spec. 10.6.2.1 "Physical Destination Mode".
864	* [2] See AMD spec. 16.6.1 "Receiving System and IPI Interrupts".
865	*/
866	if ((fDestMask & fBroadcastMask) == fBroadcastMask)
867	{
868	VMCPUSET_FILL(pDestCpuSet);
869	return;
870	}
871
872	if (enmDestMode == XAPICDESTMODE_PHYSICAL)
873	{
874	/* The destination mask is interpreted as the physical APIC ID of a single target. */
875	#if 1
876	/* Since our physical APIC ID is read-only to software, set the corresponding bit in the CPU set. */
877	if (RT_LIKELY(fDestMask < cCpus))
878	VMCPUSET_ADD(pDestCpuSet, fDestMask);
879	#else
880	/* The physical APIC ID may not match our VCPU ID, search through the list of targets. */
881	for (VMCPUID idCpu = 0; idCpu < cCpus; idCpu++)
882	{
883	PVMCPU pVCpuDest = &pVM->aCpus[idCpu];
884	if (XAPIC_IN_X2APIC_MODE(pVCpuDest))
885	{
886	PCX2APICPAGE pX2ApicPage = VMCPU_TO_CX2APICPAGE(pVCpuDest);
887	if (pX2ApicPage->id.u32ApicId == fDestMask)
888	VMCPUSET_ADD(pDestCpuSet, pVCpuDest->idCpu);
889	}
890	else
891	{
892	PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpuDest);
893	if (pXApicPage->id.u8ApicId == (uint8_t)fDestMask)
894	VMCPUSET_ADD(pDestCpuSet, pVCpuDest->idCpu);
895	}
896	}
897	#endif
898	}
899	else
900	{
901	Assert(enmDestMode == XAPICDESTMODE_LOGICAL);
902
903	/* A destination mask of all 0's implies no target APICs (since it's interpreted as a bitmap or partial bitmap). */
904	if (RT_UNLIKELY(!fDestMask))
905	return;
906
907	/* The destination mask is interpreted as a bitmap of software-programmable logical APIC ID of the target APICs. */
908	for (VMCPUID idCpu = 0; idCpu < cCpus; idCpu++)
909	{
910	PVMCPU pVCpuDest = &pVM->aCpus[idCpu];
911	if (apicIsLogicalDest(pVCpuDest, fDestMask))
912	VMCPUSET_ADD(pDestCpuSet, pVCpuDest->idCpu);
913	}
914	}
915	}
916
917
918	/**
919	* Sends an Interprocessor Interrupt (IPI) using values from the Interrupt
920	* Command Register (ICR).
921	*
922	* @returns VBox status code.
923	* @param pVCpu The cross context virtual CPU structure.
924	* @param rcRZ The return code if the operation cannot be
925	* performed in the current context.
926	*/
927	DECLINLINE(VBOXSTRICTRC) apicSendIpi(PVMCPU pVCpu, int rcRZ)
928	{
929	VMCPU_ASSERT_EMT(pVCpu);
930
931	PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
932	XAPICDELIVERYMODE const enmDeliveryMode = (XAPICDELIVERYMODE)pXApicPage->icr_lo.u.u3DeliveryMode;
933	XAPICDESTMODE const enmDestMode = (XAPICDESTMODE)pXApicPage->icr_lo.u.u1DestMode;
934	XAPICINITLEVEL const enmInitLevel = (XAPICINITLEVEL)pXApicPage->icr_lo.u.u1Level;
935	XAPICTRIGGERMODE const enmTriggerMode = (XAPICTRIGGERMODE)pXApicPage->icr_lo.u.u1TriggerMode;
936	XAPICDESTSHORTHAND const enmDestShorthand = (XAPICDESTSHORTHAND)pXApicPage->icr_lo.u.u2DestShorthand;
937	uint8_t const uVector = pXApicPage->icr_lo.u.u8Vector;
938
939	PX2APICPAGE pX2ApicPage = VMCPU_TO_X2APICPAGE(pVCpu);
940	uint32_t const fDest = XAPIC_IN_X2APIC_MODE(pVCpu) ? pX2ApicPage->icr_hi.u32IcrHi : pXApicPage->icr_hi.u.u8Dest;
941
942	#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
943	/*
944	* INIT Level De-assert is not support on Pentium 4 and Xeon processors.
945	* See AMD spec. 16.5 "Interprocessor Interrupts (IPI)" for a table of valid ICR combinations.
946	*/
947	if (RT_UNLIKELY( enmDeliveryMode == XAPICDELIVERYMODE_INIT_LEVEL_DEASSERT
948	&& enmInitLevel == XAPICINITLEVEL_DEASSERT
949	&& enmTriggerMode == XAPICTRIGGERMODE_LEVEL))
950	{
951	Log2(("APIC%u: INIT level de-assert unsupported, ignoring!\n", pVCpu->idCpu));
952	return VINF_SUCCESS;
953	}
954	#else
955	# error "Implement Pentium and P6 family APIC architectures"
956	#endif
957
958	/*
959	* The destination and delivery modes are ignored/by-passed when a destination shorthand is specified.
960	* See Intel spec. 10.6.2.3 "Broadcast/Self Delivery Mode".
961	*/
962	VMCPUSET DestCpuSet;
963	switch (enmDestShorthand)
964	{
965	case XAPICDESTSHORTHAND_NONE:
966	{
967	PVM pVM = pVCpu->CTX_SUFF(pVM);
968	uint32_t const fBroadcastMask = XAPIC_IN_X2APIC_MODE(pVCpu) ? X2APIC_ID_BROADCAST_MASK : XAPIC_ID_BROADCAST_MASK;
969	apicGetDestCpuSet(pVM, fDest, fBroadcastMask, enmDestMode, enmDeliveryMode, &DestCpuSet);
970	break;
971	}
972
973	case XAPICDESTSHORTHAND_SELF:
974	{
975	VMCPUSET_EMPTY(&DestCpuSet);
976	VMCPUSET_ADD(&DestCpuSet, pVCpu->idCpu);
977	break;
978	}
979
980	case XAPIDDESTSHORTHAND_ALL_INCL_SELF:
981	{
982	VMCPUSET_FILL(&DestCpuSet);
983	break;
984	}
985
986	case XAPICDESTSHORTHAND_ALL_EXCL_SELF:
987	{
988	VMCPUSET_FILL(&DestCpuSet);
989	VMCPUSET_DEL(&DestCpuSet, pVCpu->idCpu);
990	break;
991	}
992	}
993
994	return apicSendIntr(pVCpu->CTX_SUFF(pVM), pVCpu, uVector, enmTriggerMode, enmDeliveryMode, &DestCpuSet, rcRZ);
995	}
996
997
998	/**
999	* Sets the Interrupt Command Register (ICR) high dword.
1000	*
1001	* @returns Strict VBox status code.
1002	* @param pVCpu The cross context virtual CPU structure.
1003	* @param uIcrHi The ICR high dword.
1004	*/
1005	static VBOXSTRICTRC apicSetIcrHi(PVMCPU pVCpu, uint32_t uIcrHi)
1006	{
1007	VMCPU_ASSERT_EMT(pVCpu);
1008	Assert(!XAPIC_IN_X2APIC_MODE(pVCpu));
1009
1010	PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1011	pXApicPage->icr_hi.all.u32IcrHi = uIcrHi & XAPIC_ICR_HI_DEST;
1012	Log2(("APIC%u: apicSetIcrHi: uIcrHi=%#RX32\n", pVCpu->idCpu, pXApicPage->icr_hi.all.u32IcrHi));
1013
1014	return VINF_SUCCESS;
1015	}
1016
1017
1018	/**
1019	* Sets the Interrupt Command Register (ICR) low dword.
1020	*
1021	* @returns Strict VBox status code.
1022	* @param pVCpu The cross context virtual CPU structure.
1023	* @param uIcrLo The ICR low dword.
1024	* @param rcRZ The return code if the operation cannot be performed
1025	* in the current context.
1026	*/
1027	static VBOXSTRICTRC apicSetIcrLo(PVMCPU pVCpu, uint32_t uIcrLo, int rcRZ)
1028	{
1029	VMCPU_ASSERT_EMT(pVCpu);
1030
1031	PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1032	pXApicPage->icr_lo.all.u32IcrLo = uIcrLo & XAPIC_ICR_LO_WR;
1033	Log2(("APIC%u: apicSetIcrLo: uIcrLo=%#RX32\n", pVCpu->idCpu, pXApicPage->icr_lo.all.u32IcrLo));
1034
1035	return apicSendIpi(pVCpu, rcRZ);
1036	}
1037
1038
1039	/**
1040	* Sets the Interrupt Command Register (ICR).
1041	*
1042	* @returns Strict VBox status code.
1043	* @param pVCpu The cross context virtual CPU structure.
1044	* @param u64Icr The ICR (High and Low combined).
1045	* @param rcRZ The return code if the operation cannot be performed
1046	* in the current context.
1047	*/
1048	static VBOXSTRICTRC apicSetIcr(PVMCPU pVCpu, uint64_t u64Icr, int rcRZ)
1049	{
1050	VMCPU_ASSERT_EMT(pVCpu);
1051	Assert(XAPIC_IN_X2APIC_MODE(pVCpu));
1052
1053	/* Validate. */
1054	uint32_t const uLo = RT_LO_U32(u64Icr);
1055	if (RT_LIKELY(!(uLo & ~XAPIC_ICR_LO_WR)))
1056	{
1057	/* Update high dword first, then update the low dword which sends the IPI. */
1058	PX2APICPAGE pX2ApicPage = VMCPU_TO_X2APICPAGE(pVCpu);
1059	pX2ApicPage->icr_hi.u32IcrHi = RT_HI_U32(u64Icr);
1060	return apicSetIcrLo(pVCpu, uLo, rcRZ);
1061	}
1062	return apicMsrAccessError(pVCpu, MSR_IA32_X2APIC_ICR, APICMSRACCESS_WRITE_RSVD_BITS);
1063	}
1064
1065
1066	/**
1067	* Sets the Error Status Register (ESR).
1068	*
1069	* @returns Strict VBox status code.
1070	* @param pVCpu The cross context virtual CPU structure.
1071	* @param uEsr The ESR value.
1072	*/
1073	static VBOXSTRICTRC apicSetEsr(PVMCPU pVCpu, uint32_t uEsr)
1074	{
1075	VMCPU_ASSERT_EMT(pVCpu);
1076
1077	Log2(("APIC%u: apicSetEsr: uEsr=%#RX32\n", pVCpu->idCpu, uEsr));
1078
1079	if ( XAPIC_IN_X2APIC_MODE(pVCpu)
1080	&& (uEsr & ~XAPIC_ESR_WO))
1081	return apicMsrAccessError(pVCpu, MSR_IA32_X2APIC_ESR, APICMSRACCESS_WRITE_RSVD_BITS);
1082
1083	/*
1084	* Writes to the ESR causes the internal state to be updated in the register,
1085	* clearing the original state. See AMD spec. 16.4.6 "APIC Error Interrupts".
1086	*/
1087	PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1088	pXApicPage->esr.all.u32Errors = apicClearAllErrors(pVCpu);
1089	return VINF_SUCCESS;
1090	}
1091
1092
1093	/**
1094	* Updates the Processor Priority Register (PPR).
1095	*
1096	* @param pVCpu The cross context virtual CPU structure.
1097	*/
1098	static void apicUpdatePpr(PVMCPU pVCpu)
1099	{
1100	VMCPU_ASSERT_EMT(pVCpu);
1101
1102	/* See Intel spec 10.8.3.1 "Task and Processor Priorities". */
1103	PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1104	uint8_t const uIsrv = apicGetHighestSetBit(&pXApicPage->isr, 0 /* rcNotFound */);
1105	uint8_t uPpr;
1106	if (XAPIC_TPR_GET_TP(pXApicPage->tpr.u8Tpr) >= XAPIC_PPR_GET_PP(uIsrv))
1107	uPpr = pXApicPage->tpr.u8Tpr;
1108	else
1109	uPpr = XAPIC_PPR_GET_PP(uIsrv);
1110	pXApicPage->ppr.u8Ppr = uPpr;
1111	}
1112
1113
1114	/**
1115	* Gets the Processor Priority Register (PPR).
1116	*
1117	* @returns The PPR value.
1118	* @param pVCpu The cross context virtual CPU structure.
1119	*/
1120	static uint8_t apicGetPpr(PVMCPU pVCpu)
1121	{
1122	VMCPU_ASSERT_EMT(pVCpu);
1123	STAM_COUNTER_INC(&pVCpu->apic.s.StatTprRead);
1124
1125	/*
1126	* With virtualized APIC registers or with TPR virtualization, the hardware may
1127	* update ISR/TPR transparently. We thus re-calculate the PPR which may be out of sync.
1128	* See Intel spec. 29.2.2 "Virtual-Interrupt Delivery".
1129	*/
1130	PCAPIC pApic = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
1131	if (pApic->fVirtApicRegsEnabled) /** @todo re-think this */
1132	apicUpdatePpr(pVCpu);
1133	PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
1134	return pXApicPage->ppr.u8Ppr;
1135	}
1136
1137
1138	/**
1139	* Sets the Task Priority Register (TPR).
1140	*
1141	* @returns Strict VBox status code.
1142	* @param pVCpu The cross context virtual CPU structure.
1143	* @param uTpr The TPR value.
1144	*/
1145	static VBOXSTRICTRC apicSetTpr(PVMCPU pVCpu, uint32_t uTpr)
1146	{
1147	VMCPU_ASSERT_EMT(pVCpu);
1148
1149	Log2(("APIC%u: apicSetTpr: uTpr=%#RX32\n", pVCpu->idCpu, uTpr));
1150	STAM_COUNTER_INC(&pVCpu->apic.s.StatTprWrite);
1151
1152	if ( XAPIC_IN_X2APIC_MODE(pVCpu)
1153	&& (uTpr & ~XAPIC_TPR))
1154	return apicMsrAccessError(pVCpu, MSR_IA32_X2APIC_TPR, APICMSRACCESS_WRITE_RSVD_BITS);
1155
1156	PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1157	pXApicPage->tpr.u8Tpr = uTpr;
1158	apicUpdatePpr(pVCpu);
1159	apicSignalNextPendingIntr(pVCpu);
1160	return VINF_SUCCESS;
1161	}
1162
1163
1164	/**
1165	* Sets the End-Of-Interrupt (EOI) register.
1166	*
1167	* @returns Strict VBox status code.
1168	* @param pVCpu The cross context virtual CPU structure.
1169	* @param uEoi The EOI value.
1170	*/
1171	static VBOXSTRICTRC apicSetEoi(PVMCPU pVCpu, uint32_t uEoi)
1172	{
1173	VMCPU_ASSERT_EMT(pVCpu);
1174
1175	Log2(("APIC%u: apicSetEoi: uEoi=%#RX32\n", pVCpu->idCpu, uEoi));
1176	STAM_COUNTER_INC(&pVCpu->apic.s.StatEoiWrite);
1177
1178	if ( XAPIC_IN_X2APIC_MODE(pVCpu)
1179	&& (uEoi & ~XAPIC_EOI_WO))
1180	return apicMsrAccessError(pVCpu, MSR_IA32_X2APIC_EOI, APICMSRACCESS_WRITE_RSVD_BITS);
1181
1182	PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1183	int isrv = apicGetHighestSetBit(&pXApicPage->isr, -1 /* rcNotFound */);
1184	if (isrv >= 0)
1185	{
1186	Assert(isrv <= (int)UINT8_MAX);
1187	uint8_t const uVector = isrv;
1188	apicClearVectorInReg(&pXApicPage->isr, uVector);
1189	apicUpdatePpr(pVCpu);
1190	Log2(("APIC%u: apicSetEoi: Cleared interrupt from ISR. uVector=%#x\n", pVCpu->idCpu, uVector));
1191
1192	bool fLevelTriggered = apicTestVectorInReg(&pXApicPage->tmr, uVector);
1193	if (fLevelTriggered)
1194	{
1195	/** @todo We need to broadcast EOI to IO APICs here. */
1196	apicClearVectorInReg(&pXApicPage->tmr, uVector);
1197	Log2(("APIC%u: apicSetEoi: Cleared level triggered interrupt from TMR. uVector=%#x\n", pVCpu->idCpu, uVector));
1198	}
1199
1200	apicSignalNextPendingIntr(pVCpu);
1201	}
1202
1203	return VINF_SUCCESS;
1204	}
1205
1206
1207	/**
1208	* Sets the Logical Destination Register (LDR).
1209	*
1210	* @returns Strict VBox status code.
1211	* @param pVCpu The cross context virtual CPU structure.
1212	* @param uLdr The LDR value.
1213	*
1214	* @remarks LDR is read-only in x2APIC mode.
1215	*/
1216	static VBOXSTRICTRC apicSetLdr(PVMCPU pVCpu, uint32_t uLdr)
1217	{
1218	VMCPU_ASSERT_EMT(pVCpu);
1219	Assert(!XAPIC_IN_X2APIC_MODE(pVCpu));
1220
1221	Log2(("APIC%u: apicSetLdr: uLdr=%#RX32\n", pVCpu->idCpu, uLdr));
1222
1223	PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1224	apicWriteRaw32(pXApicPage, XAPIC_OFF_LDR, uLdr & XAPIC_LDR);
1225	return VINF_SUCCESS;
1226	}
1227
1228
1229	/**
1230	* Sets the Destination Format Register (DFR).
1231	*
1232	* @returns Strict VBox status code.
1233	* @param pVCpu The cross context virtual CPU structure.
1234	* @param uDfr The DFR value.
1235	*
1236	* @remarks DFR is not available in x2APIC mode.
1237	*/
1238	static VBOXSTRICTRC apicSetDfr(PVMCPU pVCpu, uint32_t uDfr)
1239	{
1240	VMCPU_ASSERT_EMT(pVCpu);
1241	Assert(!XAPIC_IN_X2APIC_MODE(pVCpu));
1242
1243	uDfr &= XAPIC_DFR;
1244	uDfr \|= XAPIC_DFR_RSVD_MB1;
1245
1246	Log2(("APIC%u: apicSetDfr: uDfr=%#RX32\n", pVCpu->idCpu, uDfr));
1247
1248	PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1249	apicWriteRaw32(pXApicPage, XAPIC_OFF_DFR, uDfr);
1250	return VINF_SUCCESS;
1251	}
1252
1253
1254	/**
1255	* Sets the Timer Divide Configuration Register (DCR).
1256	*
1257	* @returns Strict VBox status code.
1258	* @param pVCpu The cross context virtual CPU structure.
1259	* @param uTimerDcr The timer DCR value.
1260	*/
1261	static VBOXSTRICTRC apicSetTimerDcr(PVMCPU pVCpu, uint32_t uTimerDcr)
1262	{
1263	VMCPU_ASSERT_EMT(pVCpu);
1264	if ( XAPIC_IN_X2APIC_MODE(pVCpu)
1265	&& (uTimerDcr & ~XAPIC_TIMER_DCR))
1266	return apicMsrAccessError(pVCpu, MSR_IA32_X2APIC_TIMER_DCR, APICMSRACCESS_WRITE_RSVD_BITS);
1267
1268	Log2(("APIC%u: apicSetTimerDcr: uTimerDcr=%#RX32\n", pVCpu->idCpu, uTimerDcr));
1269
1270	PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1271	apicWriteRaw32(pXApicPage, XAPIC_OFF_TIMER_DCR, uTimerDcr);
1272	return VINF_SUCCESS;
1273	}
1274
1275
1276	/**
1277	* Gets the timer's Current Count Register (CCR).
1278	*
1279	* @returns VBox status code.
1280	* @param pVCpu The cross context virtual CPU structure.
1281	* @param rcBusy The busy return code for the timer critical section.
1282	* @param puValue Where to store the LVT timer CCR.
1283	*/
1284	static VBOXSTRICTRC apicGetTimerCcr(PVMCPU pVCpu, int rcBusy, uint32_t *puValue)
1285	{
1286	VMCPU_ASSERT_EMT(pVCpu);
1287	Assert(puValue);
1288
1289	PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
1290	*puValue = 0;
1291
1292	/* In TSC-deadline mode, CCR returns 0, see Intel spec. 10.5.4.1 "TSC-Deadline Mode". */
1293	if (pXApicPage->lvt_timer.u.u2TimerMode == XAPIC_TIMER_MODE_TSC_DEADLINE)
1294	return VINF_SUCCESS;
1295
1296	/* If the initial-count register is 0, CCR returns 0 as it cannot exceed the ICR. */
1297	uint32_t const uInitialCount = pXApicPage->timer_icr.u32InitialCount;
1298	if (!uInitialCount)
1299	return VINF_SUCCESS;
1300
1301	/*
1302	* Reading the virtual-sync clock requires locking its timer because it's not
1303	* a simple atomic operation, see tmVirtualSyncGetEx().
1304	*
1305	* We also need to lock before reading the timer CCR, see apicR3TimerCallback().
1306	*/
1307	PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1308	PTMTIMER pTimer = pApicCpu->CTX_SUFF(pTimer);
1309
1310	int rc = TMTimerLock(pTimer, rcBusy);
1311	if (rc == VINF_SUCCESS)
1312	{
1313	/* If the current-count register is 0, it implies the timer expired. */
1314	uint32_t const uCurrentCount = pXApicPage->timer_ccr.u32CurrentCount;
1315	if (uCurrentCount)
1316	{
1317	uint64_t const cTicksElapsed = TMTimerGet(pApicCpu->CTX_SUFF(pTimer)) - pApicCpu->u64TimerInitial;
1318	TMTimerUnlock(pTimer);
1319	uint8_t const uTimerShift = apicGetTimerShift(pXApicPage);
1320	uint64_t const uDelta = cTicksElapsed >> uTimerShift;
1321	if (uInitialCount > uDelta)
1322	*puValue = uInitialCount - uDelta;
1323	}
1324	else
1325	TMTimerUnlock(pTimer);
1326	}
1327	return rc;
1328	}
1329
1330
1331	/**
1332	* Sets the timer's Initial-Count Register (ICR).
1333	*
1334	* @returns Strict VBox status code.
1335	* @param pVCpu The cross context virtual CPU structure.
1336	* @param rcBusy The busy return code for the timer critical section.
1337	* @param uInitialCount The timer ICR.
1338	*/
1339	static VBOXSTRICTRC apicSetTimerIcr(PVMCPU pVCpu, int rcBusy, uint32_t uInitialCount)
1340	{
1341	VMCPU_ASSERT_EMT(pVCpu);
1342
1343	PAPIC pApic = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
1344	PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1345	PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1346	PTMTIMER pTimer = pApicCpu->CTX_SUFF(pTimer);
1347
1348	/* In TSC-deadline mode, timer ICR writes are ignored, see Intel spec. 10.5.4.1 "TSC-Deadline Mode". */
1349	if ( pApic->fSupportsTscDeadline
1350	&& pXApicPage->lvt_timer.u.u2TimerMode == XAPIC_TIMER_MODE_TSC_DEADLINE)
1351	return VINF_SUCCESS;
1352
1353	Log2(("APIC%u: apicSetTimerIcr: uInitialCount=%#RX32\n", pVCpu->idCpu, uInitialCount));
1354
1355	/*
1356	* The timer CCR may be modified by apicR3TimerCallback() in parallel,
1357	* so obtain the lock -before- updating it here to be consistent with the
1358	* timer ICR. We rely on CCR being consistent in apicGetTimerCcr().
1359	*/
1360	int rc = TMTimerLock(pTimer, rcBusy);
1361	if (rc == VINF_SUCCESS)
1362	{
1363	pXApicPage->timer_icr.u32InitialCount = uInitialCount;
1364	pXApicPage->timer_ccr.u32CurrentCount = uInitialCount;
1365	if (uInitialCount)
1366	APICStartTimer(pVCpu, uInitialCount);
1367	else
1368	APICStopTimer(pVCpu);
1369	TMTimerUnlock(pTimer);
1370	}
1371	return rc;
1372	}
1373
1374
1375	/**
1376	* Sets an LVT entry.
1377	*
1378	* @returns Strict VBox status code.
1379	* @param pVCpu The cross context virtual CPU structure.
1380	* @param offLvt The LVT entry offset in the xAPIC page.
1381	* @param uLvt The LVT value to set.
1382	*/
1383	static VBOXSTRICTRC apicSetLvtEntry(PVMCPU pVCpu, uint16_t offLvt, uint32_t uLvt)
1384	{
1385	VMCPU_ASSERT_EMT(pVCpu);
1386
1387	#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
1388	AssertMsg( offLvt == XAPIC_OFF_LVT_TIMER
1389	\|\| offLvt == XAPIC_OFF_LVT_THERMAL
1390	\|\| offLvt == XAPIC_OFF_LVT_PERF
1391	\|\| offLvt == XAPIC_OFF_LVT_LINT0
1392	\|\| offLvt == XAPIC_OFF_LVT_LINT1
1393	\|\| offLvt == XAPIC_OFF_LVT_ERROR,
1394	("APIC%u: apicSetLvtEntry: invalid offset, offLvt=%#RX16, uLvt=%#RX32\n", pVCpu->idCpu, offLvt, uLvt));
1395
1396	/*
1397	* If TSC-deadline mode isn't support, ignore the bit in xAPIC mode
1398	* and raise #GP(0) in x2APIC mode.
1399	*/
1400	PCAPIC pApic = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
1401	if (offLvt == XAPIC_OFF_LVT_TIMER)
1402	{
1403	if ( !pApic->fSupportsTscDeadline
1404	&& (uLvt & XAPIC_LVT_TIMER_TSCDEADLINE))
1405	{
1406	if (XAPIC_IN_X2APIC_MODE(pVCpu))
1407	return apicMsrAccessError(pVCpu, XAPIC_GET_X2APIC_MSR(offLvt), APICMSRACCESS_WRITE_RSVD_BITS);
1408	uLvt &= ~XAPIC_LVT_TIMER_TSCDEADLINE;
1409	/** @todo TSC-deadline timer mode transition */
1410	}
1411	}
1412
1413	/*
1414	* Validate rest of the LVT bits.
1415	*/
1416	uint16_t const idxLvt = (offLvt - XAPIC_OFF_LVT_START) >> 4;
1417	AssertReturn(idxLvt < RT_ELEMENTS(g_au32LvtValidMasks), VERR_OUT_OF_RANGE);
1418
1419	/*
1420	* For x2APIC, disallow setting of invalid/reserved bits.
1421	* For xAPIC, mask out invalid/reserved bits (i.e. ignore them).
1422	*/
1423	if ( XAPIC_IN_X2APIC_MODE(pVCpu)
1424	&& (uLvt & ~g_au32LvtValidMasks[idxLvt]))
1425	return apicMsrAccessError(pVCpu, XAPIC_GET_X2APIC_MSR(offLvt), APICMSRACCESS_WRITE_RSVD_BITS);
1426
1427	uLvt &= g_au32LvtValidMasks[idxLvt];
1428
1429	/*
1430	* In the software-disabled state, LVT mask-bit must remain set and attempts to clear the mask
1431	* bit must be ignored. See Intel spec. 10.4.7.2 "Local APIC State After It Has Been Software Disabled".
1432	*/
1433	PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1434	if (!pXApicPage->svr.u.fApicSoftwareEnable)
1435	uLvt \|= XAPIC_LVT_MASK;
1436
1437	/*
1438	* It is unclear whether we should signal a 'send illegal vector' error here and ignore updating
1439	* the LVT entry when the delivery mode is 'fixed'[1] or update it in addition to signaling the
1440	* error or not signal the error at all. For now, we'll allow setting illegal vectors into the LVT
1441	* but set the 'send illegal vector' error here. The 'receive illegal vector' error will be set if
1442	* the interrupt for the vector happens to be generated, see APICPostInterrupt().
1443	*
1444	* [1] See Intel spec. 10.5.2 "Valid Interrupt Vectors".
1445	*/
1446	if (RT_UNLIKELY( XAPIC_LVT_GET_VECTOR(uLvt) <= XAPIC_ILLEGAL_VECTOR_END
1447	&& XAPIC_LVT_GET_DELIVERY_MODE(uLvt) == XAPICDELIVERYMODE_FIXED))
1448	apicSetError(pVCpu, XAPIC_ESR_SEND_ILLEGAL_VECTOR);
1449
1450	Log2(("APIC%u: apicSetLvtEntry: offLvt=%#RX16 uLvt=%#RX32\n", pVCpu->idCpu, offLvt, uLvt));
1451
1452	apicWriteRaw32(pXApicPage, offLvt, uLvt);
1453	return VINF_SUCCESS;
1454	#else
1455	# error "Implement Pentium and P6 family APIC architectures"
1456	#endif /* XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4 */
1457	}
1458
1459
1460	#if 0
1461	/**
1462	* Sets an LVT entry in the extended LVT range.
1463	*
1464	* @returns VBox status code.
1465	* @param pVCpu The cross context virtual CPU structure.
1466	* @param offLvt The LVT entry offset in the xAPIC page.
1467	* @param uValue The LVT value to set.
1468	*/
1469	static int apicSetLvtExtEntry(PVMCPU pVCpu, uint16_t offLvt, uint32_t uLvt)
1470	{
1471	VMCPU_ASSERT_EMT(pVCpu);
1472	AssertMsg(offLvt == XAPIC_OFF_CMCI, ("APIC%u: apicSetLvt1Entry: invalid offset %#RX16\n", pVCpu->idCpu, offLvt));
1473
1474	/** @todo support CMCI. */
1475	return VERR_NOT_IMPLEMENTED;
1476	}
1477	#endif
1478
1479
1480	/**
1481	* Hints TM about the APIC timer frequency.
1482	*
1483	* @param pApicCpu The APIC CPU state.
1484	* @param uInitialCount The new initial count.
1485	* @param uTimerShift The new timer shift.
1486	* @thread Any.
1487	*/
1488	void apicHintTimerFreq(PAPICCPU pApicCpu, uint32_t uInitialCount, uint8_t uTimerShift)
1489	{
1490	Assert(pApicCpu);
1491
1492	if ( pApicCpu->uHintedTimerInitialCount != uInitialCount
1493	\|\| pApicCpu->uHintedTimerShift != uTimerShift)
1494	{
1495	uint32_t uHz;
1496	if (uInitialCount)
1497	{
1498	uint64_t cTicksPerPeriod = (uint64_t)uInitialCount << uTimerShift;
1499	uHz = TMTimerGetFreq(pApicCpu->CTX_SUFF(pTimer)) / cTicksPerPeriod;
1500	}
1501	else
1502	uHz = 0;
1503
1504	TMTimerSetFrequencyHint(pApicCpu->CTX_SUFF(pTimer), uHz);
1505	pApicCpu->uHintedTimerInitialCount = uInitialCount;
1506	pApicCpu->uHintedTimerShift = uTimerShift;
1507	}
1508	}
1509
1510
1511	/**
1512	* Reads an APIC register.
1513	*
1514	* @returns VBox status code.
1515	* @param pApicDev The APIC device instance.
1516	* @param pVCpu The cross context virtual CPU structure.
1517	* @param offReg The offset of the register being read.
1518	* @param puValue Where to store the register value.
1519	*/
1520	static int apicReadRegister(PAPICDEV pApicDev, PVMCPU pVCpu, uint16_t offReg, uint32_t *puValue)
1521	{
1522	VMCPU_ASSERT_EMT(pVCpu);
1523	Assert(offReg <= XAPIC_OFF_MAX_VALID);
1524
1525	PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1526	uint32_t uValue = 0;
1527	int rc = VINF_SUCCESS;
1528	switch (offReg)
1529	{
1530	case XAPIC_OFF_ID:
1531	case XAPIC_OFF_VERSION:
1532	case XAPIC_OFF_TPR:
1533	case XAPIC_OFF_EOI:
1534	case XAPIC_OFF_RRD:
1535	case XAPIC_OFF_LDR:
1536	case XAPIC_OFF_DFR:
1537	case XAPIC_OFF_SVR:
1538	case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
1539	case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
1540	case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
1541	case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
1542	case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
1543	case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
1544	case XAPIC_OFF_ESR:
1545	case XAPIC_OFF_ICR_LO:
1546	case XAPIC_OFF_ICR_HI:
1547	case XAPIC_OFF_LVT_TIMER:
1548	#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
1549	case XAPIC_OFF_LVT_THERMAL:
1550	#endif
1551	case XAPIC_OFF_LVT_PERF:
1552	case XAPIC_OFF_LVT_LINT0:
1553	case XAPIC_OFF_LVT_LINT1:
1554	case XAPIC_OFF_LVT_ERROR:
1555	case XAPIC_OFF_TIMER_ICR:
1556	case XAPIC_OFF_TIMER_DCR:
1557	{
1558	Assert( !XAPIC_IN_X2APIC_MODE(pVCpu)
1559	\|\| ( offReg != XAPIC_OFF_DFR
1560	&& offReg != XAPIC_OFF_ICR_HI
1561	&& offReg != XAPIC_OFF_EOI));
1562	uValue = apicReadRaw32(pXApicPage, offReg);
1563	Log2(("APIC%u: apicReadRegister: offReg=%#x uValue=%#x\n", pVCpu->idCpu, offReg, uValue));
1564	break;
1565	}
1566
1567	case XAPIC_OFF_PPR:
1568	{
1569	uValue = apicGetPpr(pVCpu);
1570	break;
1571	}
1572
1573	case XAPIC_OFF_TIMER_CCR:
1574	{
1575	Assert(!XAPIC_IN_X2APIC_MODE(pVCpu));
1576	rc = VBOXSTRICTRC_VAL(apicGetTimerCcr(pVCpu, VINF_IOM_R3_MMIO_READ, &uValue));
1577	break;
1578	}
1579
1580	case XAPIC_OFF_APR:
1581	{
1582	#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
1583	/* Unsupported on Pentium 4 and Xeon CPUs, invalid in x2APIC mode. */
1584	Assert(!XAPIC_IN_X2APIC_MODE(pVCpu));
1585	#else
1586	# error "Implement Pentium and P6 family APIC architectures"
1587	#endif
1588	break;
1589	}
1590
1591	default:
1592	{
1593	Assert(!XAPIC_IN_X2APIC_MODE(pVCpu));
1594	rc = PDMDevHlpDBGFStop(pApicDev->CTX_SUFF(pDevIns), RT_SRC_POS, "VCPU[%u]: offReg=%#RX16\n", pVCpu->idCpu, offReg);
1595	apicSetError(pVCpu, XAPIC_ESR_ILLEGAL_REG_ADDRESS);
1596	break;
1597	}
1598	}
1599
1600	*puValue = uValue;
1601	return rc;
1602	}
1603
1604
1605	/**
1606	* Writes an APIC register.
1607	*
1608	* @returns Strict VBox status code.
1609	* @param pApicDev The APIC device instance.
1610	* @param pVCpu The cross context virtual CPU structure.
1611	* @param offReg The offset of the register being written.
1612	* @param uValue The register value.
1613	*/
1614	static VBOXSTRICTRC apicWriteRegister(PAPICDEV pApicDev, PVMCPU pVCpu, uint16_t offReg, uint32_t uValue)
1615	{
1616	VMCPU_ASSERT_EMT(pVCpu);
1617	Assert(offReg <= XAPIC_OFF_MAX_VALID);
1618	Assert(!XAPIC_IN_X2APIC_MODE(pVCpu));
1619
1620	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1621	switch (offReg)
1622	{
1623	case XAPIC_OFF_TPR:
1624	{
1625	rcStrict = apicSetTpr(pVCpu, uValue);
1626	break;
1627	}
1628
1629	case XAPIC_OFF_LVT_TIMER:
1630	#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
1631	case XAPIC_OFF_LVT_THERMAL:
1632	#endif
1633	case XAPIC_OFF_LVT_PERF:
1634	case XAPIC_OFF_LVT_LINT0:
1635	case XAPIC_OFF_LVT_LINT1:
1636	case XAPIC_OFF_LVT_ERROR:
1637	{
1638	rcStrict = apicSetLvtEntry(pVCpu, offReg, uValue);
1639	break;
1640	}
1641
1642	case XAPIC_OFF_TIMER_ICR:
1643	{
1644	rcStrict = apicSetTimerIcr(pVCpu, VINF_IOM_R3_MMIO_WRITE, uValue);
1645	break;
1646	}
1647
1648	case XAPIC_OFF_EOI:
1649	{
1650	rcStrict = apicSetEoi(pVCpu, uValue);
1651	break;
1652	}
1653
1654	case XAPIC_OFF_LDR:
1655	{
1656	rcStrict = apicSetLdr(pVCpu, uValue);
1657	break;
1658	}
1659
1660	case XAPIC_OFF_DFR:
1661	{
1662	rcStrict = apicSetDfr(pVCpu, uValue);
1663	break;
1664	}
1665
1666	case XAPIC_OFF_SVR:
1667	{
1668	rcStrict = apicSetSvr(pVCpu, uValue);
1669	break;
1670	}
1671
1672	case XAPIC_OFF_ICR_LO:
1673	{
1674	rcStrict = apicSetIcrLo(pVCpu, uValue, VINF_IOM_R3_MMIO_WRITE);
1675	break;
1676	}
1677
1678	case XAPIC_OFF_ICR_HI:
1679	{
1680	rcStrict = apicSetIcrHi(pVCpu, uValue);
1681	break;
1682	}
1683
1684	case XAPIC_OFF_TIMER_DCR:
1685	{
1686	rcStrict = apicSetTimerDcr(pVCpu, uValue);
1687	break;
1688	}
1689
1690	case XAPIC_OFF_ESR:
1691	{
1692	rcStrict = apicSetEsr(pVCpu, uValue);
1693	break;
1694	}
1695
1696	case XAPIC_OFF_APR:
1697	case XAPIC_OFF_RRD:
1698	{
1699	#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
1700	/* Unsupported on Pentium 4 and Xeon CPUs but writes do -not- set an illegal register access error. */
1701	#else
1702	# error "Implement Pentium and P6 family APIC architectures"
1703	#endif
1704	break;
1705	}
1706
1707	/* Read-only, write ignored: */
1708	case XAPIC_OFF_VERSION:
1709	case XAPIC_OFF_ID:
1710	break;
1711
1712	/* Unavailable/reserved in xAPIC mode: */
1713	case X2APIC_OFF_SELF_IPI:
1714	/* Read-only registers: */
1715	case XAPIC_OFF_PPR:
1716	case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
1717	case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
1718	case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
1719	case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
1720	case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
1721	case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
1722	case XAPIC_OFF_TIMER_CCR:
1723	default:
1724	{
1725	rcStrict = PDMDevHlpDBGFStop(pApicDev->CTX_SUFF(pDevIns), RT_SRC_POS, "APIC%u: offReg=%#RX16\n", pVCpu->idCpu,
1726	offReg);
1727	apicSetError(pVCpu, XAPIC_ESR_ILLEGAL_REG_ADDRESS);
1728	break;
1729	}
1730	}
1731
1732	return rcStrict;
1733	}
1734
1735
1736	/**
1737	* @interface_method_impl{PDMAPICREG,pfnReadMsrR3}
1738	*/
1739	VMMDECL(VBOXSTRICTRC) APICReadMsr(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint32_t u32Reg, uint64_t *pu64Value)
1740	{
1741	/*
1742	* Validate.
1743	*/
1744	VMCPU_ASSERT_EMT(pVCpu);
1745	Assert(u32Reg >= MSR_IA32_X2APIC_START && u32Reg <= MSR_IA32_X2APIC_END);
1746	Assert(pu64Value);
1747
1748	PCAPIC pApic = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
1749	if (pApic->fRZEnabled)
1750	{ /* likely */}
1751	else
1752	return VINF_CPUM_R3_MSR_READ;
1753
1754	STAM_COUNTER_INC(&pVCpu->apic.s.CTX_SUFF(StatMsrRead));
1755
1756	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1757	if (RT_LIKELY(XAPIC_IN_X2APIC_MODE(pVCpu)))
1758	{
1759	switch (u32Reg)
1760	{
1761	/* Special handling for x2APIC: */
1762	case MSR_IA32_X2APIC_ICR:
1763	{
1764	PCX2APICPAGE pX2ApicPage = VMCPU_TO_CX2APICPAGE(pVCpu);
1765	uint64_t const uHi = pX2ApicPage->icr_hi.u32IcrHi;
1766	uint64_t const uLo = pX2ApicPage->icr_lo.all.u32IcrLo;
1767	*pu64Value = RT_MAKE_U64(uLo, uHi);
1768	break;
1769	}
1770
1771	/* Special handling, compatible with xAPIC: */
1772	case MSR_IA32_X2APIC_TIMER_CCR:
1773	{
1774	uint32_t uValue;
1775	rcStrict = apicGetTimerCcr(pVCpu, VINF_CPUM_R3_MSR_READ, &uValue);
1776	*pu64Value = uValue;
1777	break;
1778	}
1779
1780	/* Special handling, compatible with xAPIC: */
1781	case MSR_IA32_X2APIC_PPR:
1782	{
1783	*pu64Value = apicGetPpr(pVCpu);
1784	break;
1785	}
1786
1787	/* Raw read, compatible with xAPIC: */
1788	case MSR_IA32_X2APIC_ID:
1789	case MSR_IA32_X2APIC_VERSION:
1790	case MSR_IA32_X2APIC_TPR:
1791	case MSR_IA32_X2APIC_LDR:
1792	case MSR_IA32_X2APIC_SVR:
1793	case MSR_IA32_X2APIC_ISR0: case MSR_IA32_X2APIC_ISR1: case MSR_IA32_X2APIC_ISR2: case MSR_IA32_X2APIC_ISR3:
1794	case MSR_IA32_X2APIC_ISR4: case MSR_IA32_X2APIC_ISR5: case MSR_IA32_X2APIC_ISR6: case MSR_IA32_X2APIC_ISR7:
1795	case MSR_IA32_X2APIC_TMR0: case MSR_IA32_X2APIC_TMR1: case MSR_IA32_X2APIC_TMR2: case MSR_IA32_X2APIC_TMR3:
1796	case MSR_IA32_X2APIC_TMR4: case MSR_IA32_X2APIC_TMR5: case MSR_IA32_X2APIC_TMR6: case MSR_IA32_X2APIC_TMR7:
1797	case MSR_IA32_X2APIC_IRR0: case MSR_IA32_X2APIC_IRR1: case MSR_IA32_X2APIC_IRR2: case MSR_IA32_X2APIC_IRR3:
1798	case MSR_IA32_X2APIC_IRR4: case MSR_IA32_X2APIC_IRR5: case MSR_IA32_X2APIC_IRR6: case MSR_IA32_X2APIC_IRR7:
1799	case MSR_IA32_X2APIC_ESR:
1800	case MSR_IA32_X2APIC_LVT_TIMER:
1801	case MSR_IA32_X2APIC_LVT_THERMAL:
1802	case MSR_IA32_X2APIC_LVT_PERF:
1803	case MSR_IA32_X2APIC_LVT_LINT0:
1804	case MSR_IA32_X2APIC_LVT_LINT1:
1805	case MSR_IA32_X2APIC_LVT_ERROR:
1806	case MSR_IA32_X2APIC_TIMER_ICR:
1807	case MSR_IA32_X2APIC_TIMER_DCR:
1808	{
1809	PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1810	uint16_t const offReg = X2APIC_GET_XAPIC_OFF(u32Reg);
1811	*pu64Value = apicReadRaw32(pXApicPage, offReg);
1812	break;
1813	}
1814
1815	/* Write-only MSRs: */
1816	case MSR_IA32_X2APIC_SELF_IPI:
1817	case MSR_IA32_X2APIC_EOI:
1818	{
1819	rcStrict = apicMsrAccessError(pVCpu, u32Reg, APICMSRACCESS_READ_WRITE_ONLY);
1820	break;
1821	}
1822
1823	/* Reserved MSRs: */
1824	case MSR_IA32_X2APIC_LVT_CMCI:
1825	default:
1826	{
1827	rcStrict = apicMsrAccessError(pVCpu, u32Reg, APICMSRACCESS_READ_RSVD_OR_UNKNOWN);
1828	break;
1829	}
1830	}
1831	}
1832	else
1833	rcStrict = apicMsrAccessError(pVCpu, u32Reg, APICMSRACCESS_INVALID_READ_MODE);
1834
1835	return rcStrict;
1836	}
1837
1838
1839	/**
1840	* @interface_method_impl{PDMAPICREG,pfnWriteMsrR3}
1841	*/
1842	VMMDECL(VBOXSTRICTRC) APICWriteMsr(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint32_t u32Reg, uint64_t u64Value)
1843	{
1844	/*
1845	* Validate.
1846	*/
1847	VMCPU_ASSERT_EMT(pVCpu);
1848	Assert(u32Reg >= MSR_IA32_X2APIC_START && u32Reg <= MSR_IA32_X2APIC_END);
1849
1850	PCAPIC pApic = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
1851	if (pApic->fRZEnabled)
1852	{ /* likely */ }
1853	else
1854	return VINF_CPUM_R3_MSR_WRITE;
1855
1856	STAM_COUNTER_INC(&pVCpu->apic.s.CTX_SUFF(StatMsrWrite));
1857
1858	/*
1859	* In x2APIC mode, we need to raise #GP(0) for writes to reserved bits, unlike MMIO
1860	* accesses where they are ignored. Hence, we need to validate each register before
1861	* invoking the generic/xAPIC write functions.
1862	*
1863	* Bits 63:32 of all registers except the ICR are reserved, we'll handle this common
1864	* case first and handle validating the remaining bits on a per-register basis.
1865	* See Intel spec. 10.12.1.2 "x2APIC Register Address Space".
1866	*/
1867	if ( u32Reg != MSR_IA32_X2APIC_ICR
1868	&& RT_HI_U32(u64Value))
1869	return apicMsrAccessError(pVCpu, u32Reg, APICMSRACCESS_WRITE_RSVD_BITS);
1870
1871	uint32_t u32Value = RT_LO_U32(u64Value);
1872	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1873	if (RT_LIKELY(XAPIC_IN_X2APIC_MODE(pVCpu)))
1874	{
1875	switch (u32Reg)
1876	{
1877	case MSR_IA32_X2APIC_TPR:
1878	{
1879	rcStrict = apicSetTpr(pVCpu, u32Value);
1880	break;
1881	}
1882
1883	case MSR_IA32_X2APIC_ICR:
1884	{
1885	rcStrict = apicSetIcr(pVCpu, u64Value, VINF_CPUM_R3_MSR_WRITE);
1886	break;
1887	}
1888
1889	case MSR_IA32_X2APIC_SVR:
1890	{
1891	rcStrict = apicSetSvr(pVCpu, u32Value);
1892	break;
1893	}
1894
1895	case MSR_IA32_X2APIC_ESR:
1896	{
1897	rcStrict = apicSetEsr(pVCpu, u32Value);
1898	break;
1899	}
1900
1901	case MSR_IA32_X2APIC_TIMER_DCR:
1902	{
1903	rcStrict = apicSetTimerDcr(pVCpu, u32Value);
1904	break;
1905	}
1906
1907	case MSR_IA32_X2APIC_LVT_TIMER:
1908	case MSR_IA32_X2APIC_LVT_THERMAL:
1909	case MSR_IA32_X2APIC_LVT_PERF:
1910	case MSR_IA32_X2APIC_LVT_LINT0:
1911	case MSR_IA32_X2APIC_LVT_LINT1:
1912	case MSR_IA32_X2APIC_LVT_ERROR:
1913	{
1914	rcStrict = apicSetLvtEntry(pVCpu, X2APIC_GET_XAPIC_OFF(u32Reg), u32Value);
1915	break;
1916	}
1917
1918	case MSR_IA32_X2APIC_TIMER_ICR:
1919	{
1920	rcStrict = apicSetTimerIcr(pVCpu, VINF_CPUM_R3_MSR_WRITE, u32Value);
1921	break;
1922	}
1923
1924	/* Write-only MSRs: */
1925	case MSR_IA32_X2APIC_SELF_IPI:
1926	{
1927	uint8_t const uVector = XAPIC_SELF_IPI_GET_VECTOR(u32Value);
1928	APICPostInterrupt(pVCpu, uVector, XAPICTRIGGERMODE_EDGE);
1929	rcStrict = VINF_SUCCESS;
1930	break;
1931	}
1932
1933	case MSR_IA32_X2APIC_EOI:
1934	{
1935	rcStrict = apicSetEoi(pVCpu, u32Value);
1936	break;
1937	}
1938
1939	/* Read-only MSRs: */
1940	case MSR_IA32_X2APIC_ID:
1941	case MSR_IA32_X2APIC_VERSION:
1942	case MSR_IA32_X2APIC_PPR:
1943	case MSR_IA32_X2APIC_LDR:
1944	case MSR_IA32_X2APIC_ISR0: case MSR_IA32_X2APIC_ISR1: case MSR_IA32_X2APIC_ISR2: case MSR_IA32_X2APIC_ISR3:
1945	case MSR_IA32_X2APIC_ISR4: case MSR_IA32_X2APIC_ISR5: case MSR_IA32_X2APIC_ISR6: case MSR_IA32_X2APIC_ISR7:
1946	case MSR_IA32_X2APIC_TMR0: case MSR_IA32_X2APIC_TMR1: case MSR_IA32_X2APIC_TMR2: case MSR_IA32_X2APIC_TMR3:
1947	case MSR_IA32_X2APIC_TMR4: case MSR_IA32_X2APIC_TMR5: case MSR_IA32_X2APIC_TMR6: case MSR_IA32_X2APIC_TMR7:
1948	case MSR_IA32_X2APIC_IRR0: case MSR_IA32_X2APIC_IRR1: case MSR_IA32_X2APIC_IRR2: case MSR_IA32_X2APIC_IRR3:
1949	case MSR_IA32_X2APIC_IRR4: case MSR_IA32_X2APIC_IRR5: case MSR_IA32_X2APIC_IRR6: case MSR_IA32_X2APIC_IRR7:
1950	case MSR_IA32_X2APIC_TIMER_CCR:
1951	{
1952	rcStrict = apicMsrAccessError(pVCpu, u32Reg, APICMSRACCESS_WRITE_READ_ONLY);
1953	break;
1954	}
1955
1956	/* Reserved MSRs: */
1957	case MSR_IA32_X2APIC_LVT_CMCI:
1958	default:
1959	{
1960	rcStrict = apicMsrAccessError(pVCpu, u32Reg, APICMSRACCESS_WRITE_RSVD_OR_UNKNOWN);
1961	break;
1962	}
1963	}
1964	}
1965	else
1966	rcStrict = apicMsrAccessError(pVCpu, u32Reg, APICMSRACCESS_INVALID_WRITE_MODE);
1967
1968	return rcStrict;
1969	}
1970
1971
1972	/**
1973	* @interface_method_impl{PDMAPICREG,pfnSetBaseMsrR3}
1974	*/
1975	VMMDECL(VBOXSTRICTRC) APICSetBaseMsr(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint64_t u64BaseMsr)
1976	{
1977	Assert(pVCpu);
1978	NOREF(pDevIns);
1979
1980	#ifdef IN_RING3
1981	PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1982	PAPIC pApic = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
1983	APICMODE enmOldMode = apicGetMode(pApicCpu->uApicBaseMsr);
1984	APICMODE enmNewMode = apicGetMode(u64BaseMsr);
1985	uint64_t uBaseMsr = pApicCpu->uApicBaseMsr;
1986
1987	Log2(("APIC%u: ApicSetBaseMsr: u64BaseMsr=%#RX64 enmNewMode=%s enmOldMode=%s\n", pVCpu->idCpu, u64BaseMsr,
1988	apicGetModeName(enmNewMode), apicGetModeName(enmOldMode)));
1989
1990	/*
1991	* We do not support re-mapping the APIC base address because:
1992	* - We'll have to manage all the mappings ourselves in the APIC (reference counting based unmapping etc.)
1993	* i.e. we can only unmap the MMIO region if no other APIC is mapped on that location.
1994	* - It's unclear how/if IOM can fallback to handling regions as regular memory (if the MMIO
1995	* region remains mapped but doesn't belong to the called VCPU's APIC).
1996	*/
1997	/** @todo Handle per-VCPU APIC base relocation. */
1998	if (MSR_IA32_APICBASE_GET_ADDR(uBaseMsr) != MSR_IA32_APICBASE_ADDR)
1999	{
2000	LogRelMax(5, ("APIC%u: Attempt to relocate base to %#RGp, unsupported -> #GP(0)\n", pVCpu->idCpu,
2001	MSR_IA32_APICBASE_GET_ADDR(uBaseMsr)));
2002	return VERR_CPUM_RAISE_GP_0;
2003	}
2004
2005	/* Don't allow enabling xAPIC/x2APIC if the VM is configured with the APIC disabled. */
2006	if (pApic->enmOriginalMode == APICMODE_DISABLED)
2007	{
2008	LogRel(("APIC%u: Disallowing APIC base MSR write as the VM config is configured with APIC disabled!\n"));
2009	return apicMsrAccessError(pVCpu, MSR_IA32_APICBASE, APICMSRACCESS_WRITE_DISALLOWED_CONFIG);
2010	}
2011
2012	/*
2013	* Act on state transition.
2014	*/
2015	/** @todo We need to update the CPUID according to the state, which we
2016	* currently don't do as CPUMSetGuestCpuIdFeature() is setting
2017	* per-VM CPUID bits while we need per-VCPU specific bits. */
2018	if (enmNewMode != enmOldMode)
2019	{
2020	switch (enmNewMode)
2021	{
2022	case APICMODE_DISABLED:
2023	{
2024	/*
2025	* The APIC state needs to be reset (especially the APIC ID as x2APIC APIC ID bit layout
2026	* is different). We can start with a clean slate identical to the state after a power-up/reset.
2027	*
2028	* See Intel spec. 10.4.3 "Enabling or Disabling the Local APIC".
2029	*
2030	* We'll also manually manage the APIC base MSR here. We want a single-point of commit
2031	* at the end of this function rather than touching it in APICR3Reset. This means we also
2032	* need to update the CPUID leaf ourselves.
2033	*/
2034	APICR3Reset(pVCpu, false /* fResetApicBaseMsr */);
2035	uBaseMsr &= ~(MSR_IA32_APICBASE_EN \| MSR_IA32_APICBASE_EXTD);
2036	CPUMClearGuestCpuIdFeature(pVCpu->CTX_SUFF(pVM), CPUMCPUIDFEATURE_APIC);
2037	LogRel(("APIC%u: Switched mode to disabled\n", pVCpu->idCpu));
2038	break;
2039	}
2040
2041	case APICMODE_XAPIC:
2042	{
2043	if (enmOldMode != APICMODE_DISABLED)
2044	{
2045	LogRel(("APIC%u: Can only transition to xAPIC state from disabled state\n", pVCpu->idCpu));
2046	return apicMsrAccessError(pVCpu, MSR_IA32_APICBASE, APICMSRACCESS_WRITE_INVALID);
2047	}
2048
2049	uBaseMsr \|= MSR_IA32_APICBASE_EN;
2050	CPUMSetGuestCpuIdFeature(pVCpu->CTX_SUFF(pVM), CPUMCPUIDFEATURE_APIC);
2051	LogRel(("APIC%u: Switched mode to xAPIC\n", pVCpu->idCpu));
2052	break;
2053	}
2054
2055	case APICMODE_X2APIC:
2056	{
2057	if (enmOldMode != APICMODE_XAPIC)
2058	{
2059	LogRel(("APIC%u: Can only transition to x2APIC state from xAPIC state\n", pVCpu->idCpu));
2060	return apicMsrAccessError(pVCpu, MSR_IA32_APICBASE, APICMSRACCESS_WRITE_INVALID);
2061	}
2062
2063	uBaseMsr \|= MSR_IA32_APICBASE_EN \| MSR_IA32_APICBASE_EXTD;
2064
2065	/*
2066	* The APIC ID needs updating when entering x2APIC mode.
2067	* Software written APIC ID in xAPIC mode isn't preseved.
2068	* The APIC ID becomes read-only to software in x2APIC mode.
2069	*
2070	* See Intel spec. 10.12.5.1 "x2APIC States".
2071	*/
2072	PX2APICPAGE pX2ApicPage = VMCPU_TO_X2APICPAGE(pVCpu);
2073	ASMMemZero32(&pX2ApicPage->id, sizeof(pX2ApicPage->id));
2074	pX2ApicPage->id.u32ApicId = pVCpu->idCpu;
2075
2076	/*
2077	* LDR initialization occurs when entering x2APIC mode.
2078	* See Intel spec. 10.12.10.2 "Deriving Logical x2APIC ID from the Local x2APIC ID".
2079	*/
2080	pX2ApicPage->ldr.u32LogicalApicId = ((pX2ApicPage->id.u32ApicId & UINT32_C(0xffff0)) << 16)
2081	\| (UINT32_C(1) << pX2ApicPage->id.u32ApicId & UINT32_C(0xf));
2082
2083	LogRel(("APIC%u: Switched mode to x2APIC\n", pVCpu->idCpu));
2084	break;
2085	}
2086
2087	case APICMODE_INVALID:
2088	default:
2089	{
2090	Log(("APIC%u: Invalid state transition attempted\n", pVCpu->idCpu));
2091	return apicMsrAccessError(pVCpu, MSR_IA32_APICBASE, APICMSRACCESS_WRITE_INVALID);
2092	}
2093	}
2094	}
2095
2096	ASMAtomicWriteU64(&pApicCpu->uApicBaseMsr, uBaseMsr);
2097	return VINF_SUCCESS;
2098	#else /* !IN_RING3 */
2099	return VINF_CPUM_R3_MSR_WRITE;
2100	#endif /* IN_RING3 */
2101	}
2102
2103
2104	/**
2105	* @interface_method_impl{PDMAPICREG,pfnGetBaseMsrR3}
2106	*/
2107	VMMDECL(uint64_t) APICGetBaseMsr(PPDMDEVINS pDevIns, PVMCPU pVCpu)
2108	{
2109	VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
2110
2111	PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
2112	return pApicCpu->uApicBaseMsr;
2113	}
2114
2115
2116	/**
2117	* @interface_method_impl{PDMAPICREG,pfnSetTprR3}
2118	*/
2119	VMMDECL(void) APICSetTpr(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint8_t u8Tpr)
2120	{
2121	apicSetTpr(pVCpu, u8Tpr);
2122	}
2123
2124
2125	/**
2126	* Gets the highest priority pending interrupt.
2127	*
2128	* @returns true if any interrupt is pending, false otherwise.
2129	* @param pVCpu The cross context virtual CPU structure.
2130	* @param pu8PendingIntr Where to store the interrupt vector if the
2131	* interrupt is pending (optional, can be NULL).
2132	*/
2133	static bool apicGetHighestPendingInterrupt(PVMCPU pVCpu, uint8_t *pu8PendingIntr)
2134	{
2135	PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
2136	int const irrv = apicGetHighestSetBit(&pXApicPage->irr, -1);
2137	if (irrv >= 0)
2138	{
2139	Assert(irrv <= (int)UINT8_MAX);
2140	if (pu8PendingIntr)
2141	*pu8PendingIntr = (uint8_t)irrv;
2142	return true;
2143	}
2144	return false;
2145	}
2146
2147
2148	/**
2149	* @interface_method_impl{PDMAPICREG,pfnGetTprR3}
2150	*/
2151	VMMDECL(uint8_t) APICGetTpr(PPDMDEVINS pDevIns, PVMCPU pVCpu, bool pfPending, uint8_t pu8PendingIntr)
2152	{
2153	VMCPU_ASSERT_EMT(pVCpu);
2154	PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
2155
2156	if (pfPending)
2157	{
2158	/*
2159	* Just return whatever the highest pending interrupt is in the IRR.
2160	* The caller is responsible for figuring out if it's masked by the TPR etc.
2161	*/
2162	*pfPending = apicGetHighestPendingInterrupt(pVCpu, pu8PendingIntr);
2163	}
2164
2165	return pXApicPage->tpr.u8Tpr;
2166	}
2167
2168
2169	/**
2170	* @interface_method_impl{PDMAPICREG,pfnGetTimerFreqR3}
2171	*/
2172	VMMDECL(uint64_t) APICGetTimerFreq(PPDMDEVINS pDevIns)
2173	{
2174	PVM pVM = PDMDevHlpGetVM(pDevIns);
2175	PVMCPU pVCpu = &pVM->aCpus[0];
2176	PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
2177	uint64_t uTimer = TMTimerGetFreq(pApicCpu->CTX_SUFF(pTimer));
2178	return uTimer;
2179	}
2180
2181
2182	/**
2183	* @interface_method_impl{PDMAPICREG,pfnBusDeliverR3}
2184	* @remarks This is a private interface between the IOAPIC and the APIC.
2185	*/
2186	VMMDECL(int) APICBusDeliver(PPDMDEVINS pDevIns, uint8_t uDest, uint8_t uDestMode, uint8_t uDeliveryMode, uint8_t uVector,
2187	uint8_t uPolarity, uint8_t uTriggerMode, uint32_t uTagSrc)
2188	{
2189	NOREF(uPolarity);
2190	NOREF(uTagSrc);
2191	PVM pVM = PDMDevHlpGetVM(pDevIns);
2192
2193	/*
2194	* The destination field (mask) in the IO APIC redirectable table entry is 8-bits.
2195	* Hence, the broadcast mask is 0xff.
2196	* See IO APIC spec. 3.2.4. "IOREDTBL[23:0] - I/O Redirectable Table Registers".
2197	*/
2198	XAPICTRIGGERMODE enmTriggerMode = (XAPICTRIGGERMODE)uTriggerMode;
2199	XAPICDELIVERYMODE enmDeliveryMode = (XAPICDELIVERYMODE)uDeliveryMode;
2200	XAPICDESTMODE enmDestMode = (XAPICDESTMODE)uDestMode;
2201	uint32_t fDestMask = uDest;
2202	uint32_t fBroadcastMask = UINT32_C(0xff);
2203
2204	Log2(("APIC: apicBusDeliver: fDestMask=%#x enmDestMode=%s enmTriggerMode=%s enmDeliveryMode=%s uVector=%#x\n", fDestMask,
2205	apicGetDestModeName(enmDestMode), apicGetTriggerModeName(enmTriggerMode), apicGetDeliveryModeName(enmDeliveryMode),
2206	uVector));
2207
2208	VMCPUSET DestCpuSet;
2209	apicGetDestCpuSet(pVM, fDestMask, fBroadcastMask, enmDestMode, enmDeliveryMode, &DestCpuSet);
2210	VBOXSTRICTRC rcStrict = apicSendIntr(pVM, NULL /* pVCpu */, uVector, enmTriggerMode, enmDeliveryMode, &DestCpuSet,
2211	VINF_SUCCESS /* rcRZ */);
2212	return VBOXSTRICTRC_VAL(rcStrict);
2213	}
2214
2215
2216	/**
2217	* @interface_method_impl{PDMAPICREG,pfnLocalInterruptR3}
2218	* @remarks This is a private interface between the PIC and the APIC.
2219	*/
2220	VMMDECL(VBOXSTRICTRC) APICLocalInterrupt(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint8_t u8Pin, uint8_t u8Level, int rcRZ)
2221	{
2222	NOREF(pDevIns);
2223	AssertReturn(u8Pin <= 1, VERR_INVALID_PARAMETER);
2224	AssertReturn(u8Level <= 1, VERR_INVALID_PARAMETER);
2225
2226	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
2227
2228	/* If the APIC is enabled, the interrupt is subject to LVT programming. */
2229	if (apicIsEnabled(pVCpu))
2230	{
2231	PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
2232
2233	/* Pick the LVT entry corresponding to the interrupt pin. */
2234	static const uint16_t s_au16LvtOffsets[] =
2235	{
2236	XAPIC_OFF_LVT_LINT0,
2237	XAPIC_OFF_LVT_LINT1
2238	};
2239	Assert(u8Pin < RT_ELEMENTS(s_au16LvtOffsets));
2240	uint16_t const offLvt = s_au16LvtOffsets[u8Pin];
2241	uint32_t const uLvt = apicReadRaw32(pXApicPage, offLvt);
2242
2243	/* If software hasn't masked the interrupt in the LVT entry, proceed interrupt processing. */
2244	if (!XAPIC_LVT_IS_MASKED(uLvt))
2245	{
2246	XAPICDELIVERYMODE const enmDeliveryMode = XAPIC_LVT_GET_DELIVERY_MODE(uLvt);
2247	XAPICTRIGGERMODE enmTriggerMode = XAPIC_LVT_GET_TRIGGER_MODE(uLvt);
2248
2249	switch (enmDeliveryMode)
2250	{
2251	case XAPICDELIVERYMODE_INIT:
2252	{
2253	/** @todo won't work in R0/RC because callers don't care about rcRZ. */
2254	AssertMsgFailed(("INIT through LINT0/LINT1 is not yet supported\n"));
2255	/* fallthru */
2256	}
2257	case XAPICDELIVERYMODE_FIXED:
2258	{
2259	/* Level-sensitive interrupts are not supported for LINT1. See Intel spec. 10.5.1 "Local Vector Table". */
2260	if (offLvt == XAPIC_OFF_LVT_LINT1)
2261	enmTriggerMode = XAPICTRIGGERMODE_EDGE;
2262	/** @todo figure out what "If the local APIC is not used in conjunction with an I/O APIC and fixed
2263	delivery mode is selected; the Pentium 4, Intel Xeon, and P6 family processors will always
2264	use level-sensitive triggering, regardless if edge-sensitive triggering is selected."
2265	means. */
2266	/* fallthru */
2267	}
2268	case XAPICDELIVERYMODE_SMI:
2269	case XAPICDELIVERYMODE_NMI:
2270	{
2271	VMCPUSET DestCpuSet;
2272	VMCPUSET_EMPTY(&DestCpuSet);
2273	VMCPUSET_ADD(&DestCpuSet, pVCpu->idCpu);
2274	uint8_t const uVector = XAPIC_LVT_GET_VECTOR(uLvt);
2275	rcStrict = apicSendIntr(pVCpu->CTX_SUFF(pVM), pVCpu, uVector, enmTriggerMode, enmDeliveryMode, &DestCpuSet,
2276	rcRZ);
2277	break;
2278	}
2279
2280	case XAPICDELIVERYMODE_EXTINT:
2281	{
2282	Log2(("APIC%u: APICLocalInterrupt: %s ExtINT through LINT%u\n", pVCpu->idCpu,
2283	u8Level ? "Raising" : "Lowering", u8Pin));
2284	if (u8Level)
2285	APICSetInterruptFF(pVCpu, PDMAPICIRQ_EXTINT);
2286	else
2287	APICClearInterruptFF(pVCpu, PDMAPICIRQ_EXTINT);
2288	break;
2289	}
2290
2291	/* Reserved/unknown delivery modes: */
2292	case XAPICDELIVERYMODE_LOWEST_PRIO:
2293	case XAPICDELIVERYMODE_STARTUP:
2294	default:
2295	{
2296	rcStrict = VERR_INTERNAL_ERROR_3;
2297	AssertMsgFailed(("APIC%u: LocalInterrupt: Invalid delivery mode %#x (%s) on LINT%d\n", pVCpu->idCpu,
2298	enmDeliveryMode, apicGetDeliveryModeName(enmDeliveryMode), u8Pin));
2299	break;
2300	}
2301	}
2302	}
2303	}
2304	else
2305	{
2306	/* The APIC is hardware disabled. The CPU behaves as though there is no on-chip APIC. */
2307	if (u8Pin == 0)
2308	{
2309	/* LINT0 behaves as an external interrupt pin. */
2310	Log2(("APIC%u: APICLocalInterrupt: APIC hardware-disabled, %s INTR\n", pVCpu->idCpu,
2311	u8Level ? "raising" : "lowering"));
2312	if (u8Level)
2313	APICSetInterruptFF(pVCpu, PDMAPICIRQ_EXTINT);
2314	else
2315	APICClearInterruptFF(pVCpu, PDMAPICIRQ_EXTINT);
2316	}
2317	else
2318	{
2319	/* LINT1 behaves as NMI. */
2320	Log2(("APIC%u: APICLocalInterrupt: APIC hardware-disabled, raising NMI\n", pVCpu->idCpu));
2321	APICSetInterruptFF(pVCpu, PDMAPICIRQ_NMI);
2322	}
2323	}
2324
2325	return rcStrict;
2326	}
2327
2328
2329	/**
2330	* @interface_method_impl{PDMAPICREG,pfnGetInterruptR3}
2331	*/
2332	VMMDECL(int) APICGetInterrupt(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint8_t pu8Vector, uint32_t pu32TagSrc)
2333	{
2334	VMCPU_ASSERT_EMT(pVCpu);
2335	Assert(pu8Vector);
2336	NOREF(pu32TagSrc);
2337
2338	LogFlow(("APIC%u: APICGetInterrupt:\n", pVCpu->idCpu));
2339
2340	PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
2341	bool const fApicHwEnabled = apicIsEnabled(pVCpu);
2342	if ( fApicHwEnabled
2343	&& pXApicPage->svr.u.fApicSoftwareEnable)
2344	{
2345	int const irrv = apicGetHighestSetBit(&pXApicPage->irr, -1);
2346	if (RT_LIKELY(irrv >= 0))
2347	{
2348	Assert(irrv <= (int)UINT8_MAX);
2349	uint8_t const uVector = irrv;
2350
2351	/*
2352	* This can happen if the APIC receives an interrupt when the CPU has interrupts
2353	* disabled but the TPR is raised by the guest before re-enabling interrupts.
2354	*/
2355	uint8_t const uTpr = pXApicPage->tpr.u8Tpr;
2356	if ( uTpr > 0
2357	&& XAPIC_TPR_GET_TP(uVector) <= XAPIC_TPR_GET_TP(uTpr))
2358	{
2359	Log2(("APIC%u: APICGetInterrupt: Interrupt masked. uVector=%#x uTpr=%#x SpuriousVector=%#x\n", pVCpu->idCpu,
2360	uVector, uTpr, pXApicPage->svr.u.u8SpuriousVector));
2361	*pu8Vector = uVector;
2362	STAM_COUNTER_INC(&pVCpu->apic.s.StatMaskedByTpr);
2363	return VERR_APIC_INTR_MASKED_BY_TPR;
2364	}
2365
2366	/*
2367	* The PPR should be up-to-date at this point through apicSetEoi().
2368	* We're on EMT so no parallel updates possible.
2369	* Subject the pending vector to PPR prioritization.
2370	*/
2371	uint8_t const uPpr = pXApicPage->ppr.u8Ppr;
2372	if ( !uPpr
2373	\|\| XAPIC_PPR_GET_PP(uVector) > XAPIC_PPR_GET_PP(uPpr))
2374	{
2375	apicClearVectorInReg(&pXApicPage->irr, uVector);
2376	apicSetVectorInReg(&pXApicPage->isr, uVector);
2377	apicUpdatePpr(pVCpu);
2378	apicSignalNextPendingIntr(pVCpu);
2379
2380	Log2(("APIC%u: APICGetInterrupt: Valid Interrupt. uVector=%#x\n", pVCpu->idCpu, uVector));
2381	*pu8Vector = uVector;
2382	return VINF_SUCCESS;
2383	}
2384	else
2385	{
2386	STAM_COUNTER_INC(&pVCpu->apic.s.StatMaskedByPpr);
2387	Log2(("APIC%u: APICGetInterrupt: Interrupt's priority is not higher than the PPR. uVector=%#x PPR=%#x\n",
2388	pVCpu->idCpu, uVector, uPpr));
2389	}
2390	}
2391	else
2392	Log2(("APIC%u: APICGetInterrupt: No pending bits in IRR\n", pVCpu->idCpu));
2393	}
2394	else
2395	Log2(("APIC%u: APICGetInterrupt: APIC %s disabled\n", pVCpu->idCpu, !fApicHwEnabled ? "hardware" : "software"));
2396
2397	return VERR_APIC_INTR_NOT_PENDING;
2398	}
2399
2400
2401	/**
2402	* @callback_method_impl{FNIOMMMIOREAD}
2403	*/
2404	VMMDECL(int) APICReadMmio(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
2405	{
2406	NOREF(pvUser);
2407	Assert(!(GCPhysAddr & 0xf));
2408	Assert(cb == 4);
2409
2410	PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
2411	PVMCPU pVCpu = PDMDevHlpGetVMCPU(pDevIns);
2412	uint16_t offReg = (GCPhysAddr & 0xff0);
2413	uint32_t uValue = 0;
2414
2415	STAM_COUNTER_INC(&pVCpu->apic.s.CTX_SUFF(StatMmioRead));
2416
2417	int rc = apicReadRegister(pApicDev, pVCpu, offReg, &uValue);
2418	(uint32_t )pv = uValue;
2419
2420	Log2(("APIC%u: APICReadMmio: offReg=%#RX16 uValue=%#RX32\n", pVCpu->idCpu, offReg, uValue));
2421	return rc;
2422	}
2423
2424
2425	/**
2426	* @callback_method_impl{FNIOMMMIOWRITE}
2427	*/
2428	VMMDECL(int) APICWriteMmio(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void const pv, unsigned cb)
2429	{
2430	NOREF(pvUser);
2431	Assert(!(GCPhysAddr & 0xf));
2432	Assert(cb == 4);
2433
2434	PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
2435	PVMCPU pVCpu = PDMDevHlpGetVMCPU(pDevIns);
2436	uint16_t offReg = (GCPhysAddr & 0xff0);
2437	uint32_t uValue = (uint32_t )pv;
2438
2439	STAM_COUNTER_INC(&pVCpu->apic.s.CTX_SUFF(StatMmioWrite));
2440
2441	Log2(("APIC%u: APICWriteMmio: offReg=%#RX16 uValue=%#RX32\n", pVCpu->idCpu, offReg, uValue));
2442
2443	int rc = VBOXSTRICTRC_VAL(apicWriteRegister(pApicDev, pVCpu, offReg, uValue));
2444	return rc;
2445	}
2446
2447
2448	/**
2449	* Sets the interrupt pending force-flag and pokes the EMT if required.
2450	*
2451	* @param pVCpu The cross context virtual CPU structure.
2452	* @param enmType The IRQ type.
2453	*/
2454	VMMDECL(void) APICSetInterruptFF(PVMCPU pVCpu, PDMAPICIRQ enmType)
2455	{
2456	PVM pVM = pVCpu->CTX_SUFF(pVM);
2457	PAPICDEV pApicDev = VM_TO_APICDEV(pVM);
2458	CTX_SUFF(pApicDev->pApicHlp)->pfnSetInterruptFF(pApicDev->CTX_SUFF(pDevIns), enmType, pVCpu->idCpu);
2459	}
2460
2461
2462	/**
2463	* Clears the interrupt pending force-flag.
2464	*
2465	* @param pVCpu The cross context virtual CPU structure.
2466	* @param enmType The IRQ type.
2467	*/
2468	VMMDECL(void) APICClearInterruptFF(PVMCPU pVCpu, PDMAPICIRQ enmType)
2469	{
2470	PVM pVM = pVCpu->CTX_SUFF(pVM);
2471	PAPICDEV pApicDev = VM_TO_APICDEV(pVM);
2472	pApicDev->CTX_SUFF(pApicHlp)->pfnClearInterruptFF(pApicDev->CTX_SUFF(pDevIns), enmType, pVCpu->idCpu);
2473	}
2474
2475
2476	/**
2477	* Posts an interrupt to a target APIC.
2478	*
2479	* This function handles interrupts received from the system bus or
2480	* interrupts generated locally from the LVT or via a self IPI.
2481	*
2482	* Don't use this function to try and deliver ExtINT style interrupts.
2483	*
2484	* @param pVCpu The cross context virtual CPU structure.
2485	* @param uVector The vector of the interrupt to be posted.
2486	* @param enmTriggerMode The trigger mode of the interrupt.
2487	*
2488	* @thread Any.
2489	*/
2490	VMM_INT_DECL(void) APICPostInterrupt(PVMCPU pVCpu, uint8_t uVector, XAPICTRIGGERMODE enmTriggerMode)
2491	{
2492	Assert(pVCpu);
2493	Assert(uVector > XAPIC_ILLEGAL_VECTOR_END);
2494
2495	PVM pVM = pVCpu->CTX_SUFF(pVM);
2496	PCAPIC pApic = VM_TO_APIC(pVM);
2497	PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
2498
2499	STAM_PROFILE_START(&pApicCpu->StatPostIntr, a);
2500
2501	/*
2502	* Only post valid interrupt vectors.
2503	* See Intel spec. 10.5.2 "Valid Interrupt Vectors".
2504	*/
2505	if (RT_LIKELY(uVector > XAPIC_ILLEGAL_VECTOR_END))
2506	{
2507	/*
2508	* If the interrupt is already pending in the IRR we can skip the
2509	* potential expensive operation of poking the guest EMT out of execution.
2510	*/
2511	PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
2512	if (!apicTestVectorInReg(&pXApicPage->irr, uVector)) /* PAV */
2513	{
2514	Log2(("APIC: APICPostInterrupt: SrcCpu=%u TargetCpu=%u uVector=%#x\n", VMMGetCpuId(pVM), pVCpu->idCpu, uVector));
2515	if (enmTriggerMode == XAPICTRIGGERMODE_EDGE)
2516	{
2517	if (pApic->fPostedIntrsEnabled)
2518	{ /** @todo posted-interrupt call to hardware */ }
2519	else
2520	{
2521	apicSetVectorInPib(pApicCpu->CTX_SUFF(pvApicPib), uVector);
2522	uint32_t const fAlreadySet = apicSetNotificationBitInPib((PAPICPIB)pApicCpu->CTX_SUFF(pvApicPib));
2523	if (!fAlreadySet)
2524	{
2525	Log2(("APIC: APICPostInterrupt: Setting UPDATE_APIC FF for edge-triggered intr. uVector=%#x\n", uVector));
2526	APICSetInterruptFF(pVCpu, PDMAPICIRQ_UPDATE_PENDING);
2527	}
2528	}
2529	}
2530	else
2531	{
2532	/*
2533	* Level-triggered interrupts requires updating of the TMR and thus cannot be
2534	* delivered asynchronously.
2535	*/
2536	apicSetVectorInPib(&pApicCpu->ApicPibLevel, uVector);
2537	uint32_t const fAlreadySet = apicSetNotificationBitInPib(&pApicCpu->ApicPibLevel);
2538	if (!fAlreadySet)
2539	{
2540	Log2(("APIC: APICPostInterrupt: Setting UPDATE_APIC FF for level-triggered intr. uVector=%#x\n", uVector));
2541	APICSetInterruptFF(pVCpu, PDMAPICIRQ_UPDATE_PENDING);
2542	}
2543	}
2544	}
2545	else
2546	{
2547	Log2(("APIC: APICPostInterrupt: SrcCpu=%u TargetCpu=%u. Vector %#x Already in IRR, skipping\n", VMMGetCpuId(pVM),
2548	pVCpu->idCpu, uVector));
2549	STAM_COUNTER_INC(&pApicCpu->StatPostIntrAlreadyPending);
2550	}
2551	}
2552	else
2553	apicSetError(pVCpu, XAPIC_ESR_RECV_ILLEGAL_VECTOR);
2554
2555	STAM_PROFILE_STOP(&pApicCpu->StatPostIntr, a);
2556	}
2557
2558
2559	/**
2560	* Starts the APIC timer.
2561	*
2562	* @param pVCpu The cross context virtual CPU structure.
2563	* @param uInitialCount The timer's Initial-Count Register (ICR), must be >
2564	* 0.
2565	* @thread Any.
2566	*/
2567	VMM_INT_DECL(void) APICStartTimer(PVMCPU pVCpu, uint32_t uInitialCount)
2568	{
2569	Assert(pVCpu);
2570	PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
2571	Assert(TMTimerIsLockOwner(pApicCpu->CTX_SUFF(pTimer)));
2572	Assert(uInitialCount > 0);
2573
2574	PCXAPICPAGE pXApicPage = APICCPU_TO_CXAPICPAGE(pApicCpu);
2575	uint8_t const uTimerShift = apicGetTimerShift(pXApicPage);
2576	uint64_t const cTicksToNext = (uint64_t)uInitialCount << uTimerShift;
2577
2578	Log2(("APIC%u: APICStartTimer: uInitialCount=%#RX32 uTimerShift=%u cTicksToNext=%RU64\n", pVCpu->idCpu, uInitialCount,
2579	uTimerShift, cTicksToNext));
2580
2581	/*
2582	* The assumption here is that the timer doesn't tick during this call
2583	* and thus setting a relative time to fire next is accurate. The advantage
2584	* however is updating u64TimerInitial 'atomically' while setting the next
2585	* tick.
2586	*/
2587	PTMTIMER pTimer = pApicCpu->CTX_SUFF(pTimer);
2588	TMTimerSetRelative(pTimer, cTicksToNext, &pApicCpu->u64TimerInitial);
2589	apicHintTimerFreq(pApicCpu, uInitialCount, uTimerShift);
2590	}
2591
2592
2593	/**
2594	* Stops the APIC timer.
2595	*
2596	* @param pVCpu The cross context virtual CPU structure.
2597	* @thread Any.
2598	*/
2599	VMM_INT_DECL(void) APICStopTimer(PVMCPU pVCpu)
2600	{
2601	Assert(pVCpu);
2602	PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
2603	Assert(TMTimerIsLockOwner(pApicCpu->CTX_SUFF(pTimer)));
2604
2605	Log2(("APIC%u: APICStopTimer\n", pVCpu->idCpu));
2606
2607	PTMTIMER pTimer = pApicCpu->CTX_SUFF(pTimer);
2608	TMTimerStop(pTimer); /* This will reset the hint, no need to explicitly call TMTimerSetFrequencyHint(). */
2609	pApicCpu->uHintedTimerInitialCount = 0;
2610	pApicCpu->uHintedTimerShift = 0;
2611	}
2612
2613
2614	/**
2615	* Queues a pending interrupt as in-service.
2616	*
2617	* This function should only be needed without virtualized APIC
2618	* registers. With virtualized APIC registers, it's sufficient to keep
2619	* the interrupts pending in the IRR as the hardware takes care of
2620	* virtual interrupt delivery.
2621	*
2622	* @returns true if the interrupt was queued to in-service interrupts,
2623	* false otherwise.
2624	* @param pVCpu The cross context virtual CPU structure.
2625	* @param u8PendingIntr The pending interrupt to queue as
2626	* in-service.
2627	*
2628	* @remarks This assumes the caller has done the necessary checks and
2629	* is ready to take actually service the interrupt (TPR,
2630	* interrupt shadow etc.)
2631	*/
2632	VMMDECL(bool) APICQueueInterruptToService(PVMCPU pVCpu, uint8_t u8PendingIntr)
2633	{
2634	VMCPU_ASSERT_EMT(pVCpu);
2635
2636	PVM pVM = pVCpu->CTX_SUFF(pVM);
2637	PAPIC pApic = VM_TO_APIC(pVM);
2638	Assert(!pApic->fVirtApicRegsEnabled);
2639	NOREF(pApic);
2640
2641	PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
2642	bool const fIsPending = apicTestVectorInReg(&pXApicPage->irr, u8PendingIntr);
2643	if (fIsPending)
2644	{
2645	apicClearVectorInReg(&pXApicPage->irr, u8PendingIntr);
2646	apicSetVectorInReg(&pXApicPage->isr, u8PendingIntr);
2647	apicUpdatePpr(pVCpu);
2648	return true;
2649	}
2650	return false;
2651	}
2652
2653
2654	/**
2655	* Dequeues a pending interrupt from in-service.
2656	*
2657	* This undoes APICQueueInterruptToService() for premature VM-exits before event
2658	* injection.
2659	*
2660	* @param pVCpu The cross context virtual CPU structure.
2661	* @param u8PendingIntr The pending interrupt to dequeue from
2662	* in-service.
2663	*/
2664	VMMDECL(void) APICDequeueInterruptFromService(PVMCPU pVCpu, uint8_t u8PendingIntr)
2665	{
2666	VMCPU_ASSERT_EMT(pVCpu);
2667
2668	PVM pVM = pVCpu->CTX_SUFF(pVM);
2669	PAPIC pApic = VM_TO_APIC(pVM);
2670	Assert(!pApic->fVirtApicRegsEnabled);
2671	NOREF(pApic);
2672
2673	PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
2674	bool const fInService = apicTestVectorInReg(&pXApicPage->isr, u8PendingIntr);
2675	if (fInService)
2676	{
2677	apicClearVectorInReg(&pXApicPage->isr, u8PendingIntr);
2678	apicSetVectorInReg(&pXApicPage->irr, u8PendingIntr);
2679	apicUpdatePpr(pVCpu);
2680	}
2681	}
2682
2683
2684	/**
2685	* Updates pending interrupts from the pending-interrupt bitmaps to the IRR.
2686	*
2687	* @param pVCpu The cross context virtual CPU structure.
2688	*/
2689	VMMDECL(void) APICUpdatePendingInterrupts(PVMCPU pVCpu)
2690	{
2691	VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
2692
2693	PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
2694	PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
2695	bool fHasPendingIntrs = false;
2696
2697	Log3(("APIC%u: APICUpdatePendingInterrupts:\n", pVCpu->idCpu));
2698	STAM_PROFILE_START(&pApicCpu->StatUpdatePendingIntrs, a);
2699
2700	/* Update edge-triggered pending interrupts. */
2701	for (;;)
2702	{
2703	uint32_t const fAlreadySet = apicClearNotificationBitInPib((PAPICPIB)pApicCpu->CTX_SUFF(pvApicPib));
2704	if (!fAlreadySet)
2705	break;
2706
2707	PAPICPIB pPib = (PAPICPIB)pApicCpu->CTX_SUFF(pvApicPib);
2708	AssertCompile(RT_ELEMENTS(pXApicPage->irr.u) == 2 * RT_ELEMENTS(pPib->aVectorBitmap));
2709
2710	for (size_t idxPib = 0, idxReg = 0; idxPib < RT_ELEMENTS(pPib->aVectorBitmap); idxPib++, idxReg += 2)
2711	{
2712	uint64_t const u64Fragment = ASMAtomicXchgU64(&pPib->aVectorBitmap[idxPib], 0);
2713	if (u64Fragment)
2714	{
2715	uint32_t const u32FragmentLo = RT_LO_U32(u64Fragment);
2716	uint32_t const u32FragmentHi = RT_HI_U32(u64Fragment);
2717
2718	pXApicPage->irr.u[idxReg].u32Reg \|= u32FragmentLo;
2719	pXApicPage->irr.u[idxReg + 1].u32Reg \|= u32FragmentHi;
2720
2721	pXApicPage->tmr.u[idxReg].u32Reg &= ~u32FragmentLo;
2722	pXApicPage->tmr.u[idxReg + 1].u32Reg &= ~u32FragmentHi;
2723	fHasPendingIntrs = true;
2724	}
2725	}
2726	}
2727
2728	/* Update level-triggered pending interrupts. */
2729	for (;;)
2730	{
2731	uint32_t const fAlreadySet = apicClearNotificationBitInPib((PAPICPIB)&pApicCpu->ApicPibLevel);
2732	if (!fAlreadySet)
2733	break;
2734
2735	PAPICPIB pPib = (PAPICPIB)&pApicCpu->ApicPibLevel;
2736	AssertCompile(RT_ELEMENTS(pXApicPage->irr.u) == 2 * RT_ELEMENTS(pPib->aVectorBitmap));
2737
2738	for (size_t idxPib = 0, idxReg = 0; idxPib < RT_ELEMENTS(pPib->aVectorBitmap); idxPib++, idxReg += 2)
2739	{
2740	uint64_t const u64Fragment = ASMAtomicXchgU64(&pPib->aVectorBitmap[idxPib], 0);
2741	if (u64Fragment)
2742	{
2743	uint32_t const u32FragmentLo = RT_LO_U32(u64Fragment);
2744	uint32_t const u32FragmentHi = RT_HI_U32(u64Fragment);
2745
2746	pXApicPage->irr.u[idxReg].u32Reg \|= u32FragmentLo;
2747	pXApicPage->irr.u[idxReg + 1].u32Reg \|= u32FragmentHi;
2748
2749	pXApicPage->tmr.u[idxReg].u32Reg \|= u32FragmentLo;
2750	pXApicPage->tmr.u[idxReg + 1].u32Reg \|= u32FragmentHi;
2751	fHasPendingIntrs = true;
2752	}
2753	}
2754	}
2755
2756	STAM_PROFILE_STOP(&pApicCpu->StatUpdatePendingIntrs, a);
2757	Log3(("APIC%u: APICUpdatePendingInterrupts: fHasPendingIntrs=%RTbool\n", pVCpu->idCpu, fHasPendingIntrs));
2758
2759	if ( fHasPendingIntrs
2760	&& !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC))
2761	apicSignalNextPendingIntr(pVCpu);
2762	}
2763
2764
2765	/**
2766	* Gets the highest priority pending interrupt.
2767	*
2768	* @returns true if any interrupt is pending, false otherwise.
2769	* @param pVCpu The cross context virtual CPU structure.
2770	* @param pu8PendingIntr Where to store the interrupt vector if the
2771	* interrupt is pending.
2772	*/
2773	VMMDECL(bool) APICGetHighestPendingInterrupt(PVMCPU pVCpu, uint8_t *pu8PendingIntr)
2774	{
2775	VMCPU_ASSERT_EMT(pVCpu);
2776	return apicGetHighestPendingInterrupt(pVCpu, pu8PendingIntr);
2777	}
2778

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMAll/APICAll.cpp@ 61072

Download in other formats: