VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/APICAll.cpp@ 61685

Last change on this file since 61685 was 61608, checked in by vboxsync, 9 years ago

VMM/APIC: Manually register the x2APIC MSR ranges when x2APIC mode is configured for the APIC.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 100.5 KB
Line 
1/* $Id: APICAll.cpp 61608 2016-06-09 10:14:25Z vboxsync $ */
2/** @file
3 * APIC - Advanced Programmable Interrupt Controller - All Contexts.
4 */
5
6/*
7 * Copyright (C) 2016 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_APIC
23#include "APICInternal.h"
24#include <VBox/vmm/pdmdev.h>
25#include <VBox/vmm/vm.h>
26#include <VBox/vmm/vmcpuset.h>
27
28/*********************************************************************************************************************************
29* Global Variables *
30*********************************************************************************************************************************/
31#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
32/** An ordered array of valid LVT masks. */
33static const uint32_t g_au32LvtValidMasks[] =
34{
35 XAPIC_LVT_TIMER_VALID,
36 XAPIC_LVT_THERMAL_VALID,
37 XAPIC_LVT_PERF_VALID,
38 XAPIC_LVT_LINT_VALID, /* LINT0 */
39 XAPIC_LVT_LINT_VALID, /* LINT1 */
40 XAPIC_LVT_ERROR_VALID
41};
42#endif
43
44#if 0
45/** @todo CMCI */
46static const uint32_t g_au32LvtExtValidMask[] =
47{
48 XAPIC_LVT_CMCI_VALID
49};
50#endif
51
52
53/**
54 * Checks if a vector is set in an APIC 256-bit sparse register.
55 *
56 * @returns true if the specified vector is set, false otherwise.
57 * @param pApicReg The APIC 256-bit spare register.
58 * @param uVector The vector to check if set.
59 */
60DECLINLINE(bool) apicTestVectorInReg(const volatile XAPIC256BITREG *pApicReg, uint8_t uVector)
61{
62 const volatile uint8_t *pbBitmap = (const volatile uint8_t *)&pApicReg->u[0];
63 return ASMBitTest(pbBitmap + XAPIC_REG256_VECTOR_OFF(uVector), XAPIC_REG256_VECTOR_BIT(uVector));
64}
65
66
67/**
68 * Sets the vector in an APIC 256-bit sparse register.
69 *
70 * @param pApicReg The APIC 256-bit spare register.
71 * @param uVector The vector to set.
72 */
73DECLINLINE(void) apicSetVectorInReg(volatile XAPIC256BITREG *pApicReg, uint8_t uVector)
74{
75 volatile uint8_t *pbBitmap = (volatile uint8_t *)&pApicReg->u[0];
76 ASMAtomicBitSet(pbBitmap + XAPIC_REG256_VECTOR_OFF(uVector), XAPIC_REG256_VECTOR_BIT(uVector));
77}
78
79
80/**
81 * Clears the vector in an APIC 256-bit sparse register.
82 *
83 * @param pApicReg The APIC 256-bit spare register.
84 * @param uVector The vector to clear.
85 */
86DECLINLINE(void) apicClearVectorInReg(volatile XAPIC256BITREG *pApicReg, uint8_t uVector)
87{
88 volatile uint8_t *pbBitmap = (volatile uint8_t *)&pApicReg->u[0];
89 ASMAtomicBitClear(pbBitmap + XAPIC_REG256_VECTOR_OFF(uVector), XAPIC_REG256_VECTOR_BIT(uVector));
90}
91
92
93/**
94 * Checks if a vector is set in an APIC Pending-Interrupt Bitmap (PIB).
95 *
96 * @returns true if the specified vector is set, false otherwise.
97 * @param pvPib Opaque pointer to the PIB.
98 * @param uVector The vector to check if set.
99 */
100DECLINLINE(bool) apicTestVectorInPib(volatile void *pvPib, uint8_t uVector)
101{
102 return ASMBitTest(pvPib, uVector);
103}
104
105
106/**
107 * Atomically sets the PIB notification bit.
108 *
109 * @returns non-zero if the bit was already set, 0 otherwise.
110 * @param pApicPib Pointer to the PIB.
111 */
112DECLINLINE(uint32_t) apicSetNotificationBitInPib(PAPICPIB pApicPib)
113{
114 return ASMAtomicXchgU32(&pApicPib->fOutstandingNotification, RT_BIT_32(31));
115}
116
117
118/**
119 * Atomically tests and clears the PIB notification bit.
120 *
121 * @returns non-zero if the bit was already set, 0 otherwise.
122 * @param pApicPib Pointer to the PIB.
123 */
124DECLINLINE(uint32_t) apicClearNotificationBitInPib(PAPICPIB pApicPib)
125{
126 return ASMAtomicXchgU32(&pApicPib->fOutstandingNotification, UINT32_C(0));
127}
128
129
130/**
131 * Sets the vector in an APIC Pending-Interrupt Bitmap (PIB).
132 *
133 * @param pvPib Opaque pointer to the PIB.
134 * @param uVector The vector to set.
135 */
136DECLINLINE(void) apicSetVectorInPib(volatile void *pvPib, uint8_t uVector)
137{
138 ASMAtomicBitSet(pvPib, uVector);
139}
140
141
142/**
143 * Clears the vector in an APIC Pending-Interrupt Bitmap (PIB).
144 *
145 * @param pvPib Opaque pointer to the PIB.
146 * @param uVector The vector to clear.
147 */
148DECLINLINE(void) apicClearVectorInPib(volatile void *pvPib, uint8_t uVector)
149{
150 ASMAtomicBitClear(pvPib, uVector);
151}
152
153
154/**
155 * Atomically OR's a fragment (32 vectors) into an APIC 256-bit sparse
156 * register.
157 *
158 * @param pApicReg The APIC 256-bit spare register.
159 * @param idxFragment The index of the 32-bit fragment in @a
160 * pApicReg.
161 * @param u32Fragment The 32-bit vector fragment to OR.
162 */
163DECLINLINE(void) apicOrVectorsToReg(volatile XAPIC256BITREG *pApicReg, size_t idxFragment, uint32_t u32Fragment)
164{
165 Assert(idxFragment < RT_ELEMENTS(pApicReg->u));
166 ASMAtomicOrU32(&pApicReg->u[idxFragment].u32Reg, u32Fragment);
167}
168
169
170/**
171 * Atomically AND's a fragment (32 vectors) into an APIC
172 * 256-bit sparse register.
173 *
174 * @param pApicReg The APIC 256-bit spare register.
175 * @param idxFragment The index of the 32-bit fragment in @a
176 * pApicReg.
177 * @param u32Fragment The 32-bit vector fragment to AND.
178 */
179DECLINLINE(void) apicAndVectorsToReg(volatile XAPIC256BITREG *pApicReg, size_t idxFragment, uint32_t u32Fragment)
180{
181 Assert(idxFragment < RT_ELEMENTS(pApicReg->u));
182 ASMAtomicAndU32(&pApicReg->u[idxFragment].u32Reg, u32Fragment);
183}
184
185
186/**
187 * Reports and returns appropriate error code for invalid MSR accesses.
188 *
189 * @returns Strict VBox status code.
190 * @retval VINF_CPUM_R3_MSR_WRITE if the MSR write could not be serviced in the
191 * current context (raw-mode or ring-0).
192 * @retval VINF_CPUM_R3_MSR_READ if the MSR read could not be serviced in the
193 * current context (raw-mode or ring-0).
194 * @retval VERR_CPUM_RAISE_GP_0 on failure, the caller is expected to take the
195 * appropriate actions.
196 *
197 * @param pVCpu The cross context virtual CPU structure.
198 * @param u32Reg The MSR being accessed.
199 * @param enmAccess The invalid-access type.
200 */
201static VBOXSTRICTRC apicMsrAccessError(PVMCPU pVCpu, uint32_t u32Reg, APICMSRACCESS enmAccess)
202{
203 static struct
204 {
205 const char *pszBefore; /* The error message before printing the MSR index */
206 const char *pszAfter; /* The error message after printing the MSR index */
207 int rcRZ; /* The RZ error code */
208 } const s_aAccess[] =
209 {
210 { "read MSR", " while not in x2APIC mode", VINF_CPUM_R3_MSR_READ },
211 { "write MSR", " while not in x2APIC mode", VINF_CPUM_R3_MSR_WRITE },
212 { "read reserved/unknown MSR", "", VINF_CPUM_R3_MSR_READ },
213 { "write reserved/unknown MSR", "", VINF_CPUM_R3_MSR_WRITE },
214 { "read write-only MSR", "", VINF_CPUM_R3_MSR_READ },
215 { "write read-only MSR", "", VINF_CPUM_R3_MSR_WRITE },
216 { "read reserved bits of MSR", "", VINF_CPUM_R3_MSR_READ },
217 { "write reserved bits of MSR", "", VINF_CPUM_R3_MSR_WRITE },
218 { "write an invalid value to MSR", "", VINF_CPUM_R3_MSR_WRITE },
219 { "write MSR", "disallowed by configuration", VINF_CPUM_R3_MSR_WRITE }
220 };
221 AssertCompile(RT_ELEMENTS(s_aAccess) == APICMSRACCESS_COUNT);
222
223 size_t const i = enmAccess;
224 Assert(i < RT_ELEMENTS(s_aAccess));
225#ifdef IN_RING3
226 LogRelMax(5, ("APIC%u: Attempt to %s (%#x)%s -> #GP(0)\n", pVCpu->idCpu, s_aAccess[i].pszBefore, u32Reg,
227 s_aAccess[i].pszAfter));
228 return VERR_CPUM_RAISE_GP_0;
229#else
230 return s_aAccess[i].rcRZ;
231#endif
232}
233
234
235/**
236 * Gets the descriptive APIC mode.
237 *
238 * @returns The name.
239 * @param enmMode The xAPIC mode.
240 */
241const char *apicGetModeName(APICMODE enmMode)
242{
243 switch (enmMode)
244 {
245 case APICMODE_DISABLED: return "Disabled";
246 case APICMODE_XAPIC: return "xAPIC";
247 case APICMODE_X2APIC: return "x2APIC";
248 default: break;
249 }
250 return "Invalid";
251}
252
253
254/**
255 * Gets the descriptive destination format name.
256 *
257 * @returns The destination format name.
258 * @param enmDestFormat The destination format.
259 */
260const char *apicGetDestFormatName(XAPICDESTFORMAT enmDestFormat)
261{
262 switch (enmDestFormat)
263 {
264 case XAPICDESTFORMAT_FLAT: return "Flat";
265 case XAPICDESTFORMAT_CLUSTER: return "Cluster";
266 default: break;
267 }
268 return "Invalid";
269}
270
271
272/**
273 * Gets the descriptive delivery mode name.
274 *
275 * @returns The delivery mode name.
276 * @param enmDeliveryMode The delivery mode.
277 */
278const char *apicGetDeliveryModeName(XAPICDELIVERYMODE enmDeliveryMode)
279{
280 switch (enmDeliveryMode)
281 {
282 case XAPICDELIVERYMODE_FIXED: return "Fixed";
283 case XAPICDELIVERYMODE_LOWEST_PRIO: return "Lowest-priority";
284 case XAPICDELIVERYMODE_SMI: return "SMI";
285 case XAPICDELIVERYMODE_NMI: return "NMI";
286 case XAPICDELIVERYMODE_INIT: return "INIT";
287 case XAPICDELIVERYMODE_STARTUP: return "SIPI";
288 case XAPICDELIVERYMODE_EXTINT: return "ExtINT";
289 default: break;
290 }
291 return "Invalid";
292}
293
294
295/**
296 * Gets the descriptive destination mode name.
297 *
298 * @returns The destination mode name.
299 * @param enmDestMode The destination mode.
300 */
301const char *apicGetDestModeName(XAPICDESTMODE enmDestMode)
302{
303 switch (enmDestMode)
304 {
305 case XAPICDESTMODE_PHYSICAL: return "Physical";
306 case XAPICDESTMODE_LOGICAL: return "Logical";
307 default: break;
308 }
309 return "Invalid";
310}
311
312
313/**
314 * Gets the descriptive trigger mode name.
315 *
316 * @returns The trigger mode name.
317 * @param enmTriggerMode The trigger mode.
318 */
319const char *apicGetTriggerModeName(XAPICTRIGGERMODE enmTriggerMode)
320{
321 switch (enmTriggerMode)
322 {
323 case XAPICTRIGGERMODE_EDGE: return "Edge";
324 case XAPICTRIGGERMODE_LEVEL: return "Level";
325 default: break;
326 }
327 return "Invalid";
328}
329
330
331/**
332 * Gets the destination shorthand name.
333 *
334 * @returns The destination shorthand name.
335 * @param enmDestShorthand The destination shorthand.
336 */
337const char *apicGetDestShorthandName(XAPICDESTSHORTHAND enmDestShorthand)
338{
339 switch (enmDestShorthand)
340 {
341 case XAPICDESTSHORTHAND_NONE: return "None";
342 case XAPICDESTSHORTHAND_SELF: return "Self";
343 case XAPIDDESTSHORTHAND_ALL_INCL_SELF: return "All including self";
344 case XAPICDESTSHORTHAND_ALL_EXCL_SELF: return "All excluding self";
345 default: break;
346 }
347 return "Invalid";
348}
349
350
351/**
352 * Gets the timer mode name.
353 *
354 * @returns The timer mode name.
355 * @param enmTimerMode The timer mode.
356 */
357const char *apicGetTimerModeName(XAPICTIMERMODE enmTimerMode)
358{
359 switch (enmTimerMode)
360 {
361 case XAPICTIMERMODE_ONESHOT: return "One-shot";
362 case XAPICTIMERMODE_PERIODIC: return "Periodic";
363 case XAPICTIMERMODE_TSC_DEADLINE: return "TSC deadline";
364 default: break;
365 }
366 return "Invalid";
367}
368
369
370/**
371 * Gets the APIC mode given the base MSR value.
372 *
373 * @returns The APIC mode.
374 * @param uApicBaseMsr The APIC Base MSR value.
375 */
376APICMODE apicGetMode(uint64_t uApicBaseMsr)
377{
378 uint32_t const uMode = (uApicBaseMsr >> 10) & UINT64_C(3);
379 APICMODE const enmMode = (APICMODE)uMode;
380#ifdef VBOX_STRICT
381 /* Paranoia. */
382 switch (uMode)
383 {
384 case APICMODE_DISABLED:
385 case APICMODE_INVALID:
386 case APICMODE_XAPIC:
387 case APICMODE_X2APIC:
388 break;
389 default:
390 AssertMsgFailed(("Invalid mode"));
391 }
392#endif
393 return enmMode;
394}
395
396
397/**
398 * Returns whether the APIC is hardware enabled or not.
399 *
400 * @returns true if enabled, false otherwise.
401 */
402DECLINLINE(bool) apicIsEnabled(PVMCPU pVCpu)
403{
404 PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
405 return RT_BOOL(pApicCpu->uApicBaseMsr & MSR_IA32_APICBASE_EN);
406}
407
408
409/**
410 * Finds the most significant set bit in an APIC 256-bit sparse register.
411 *
412 * @returns @a rcNotFound if no bit was set, 0-255 otherwise.
413 * @param pReg The APIC 256-bit sparse register.
414 * @param rcNotFound What to return when no bit is set.
415 */
416static int apicGetHighestSetBitInReg(volatile const XAPIC256BITREG *pReg, int rcNotFound)
417{
418 ssize_t const cFragments = RT_ELEMENTS(pReg->u);
419 unsigned const uFragmentShift = 5;
420 AssertCompile(1 << uFragmentShift == sizeof(pReg->u[0].u32Reg) * 8);
421 for (ssize_t i = cFragments - 1; i >= 0; i--)
422 {
423 uint32_t const uFragment = pReg->u[i].u32Reg;
424 if (uFragment)
425 {
426 unsigned idxSetBit = ASMBitLastSetU32(uFragment);
427 --idxSetBit;
428 idxSetBit |= i << uFragmentShift;
429 return idxSetBit;
430 }
431 }
432 return rcNotFound;
433}
434
435
436/**
437 * Reads a 32-bit register at a specified offset.
438 *
439 * @returns The value at the specified offset.
440 * @param pXApicPage The xAPIC page.
441 * @param offReg The offset of the register being read.
442 */
443DECLINLINE(uint32_t) apicReadRaw32(PCXAPICPAGE pXApicPage, uint16_t offReg)
444{
445 Assert(offReg < sizeof(*pXApicPage) - sizeof(uint32_t));
446 uint8_t const *pbXApic = (const uint8_t *)pXApicPage;
447 uint32_t const uValue = *(const uint32_t *)(pbXApic + offReg);
448 return uValue;
449}
450
451
452/**
453 * Writes a 32-bit register at a specified offset.
454 *
455 * @param pXApicPage The xAPIC page.
456 * @param offReg The offset of the register being written.
457 * @param uReg The value of the register.
458 */
459DECLINLINE(void) apicWriteRaw32(PXAPICPAGE pXApicPage, uint16_t offReg, uint32_t uReg)
460{
461 Assert(offReg < sizeof(*pXApicPage) - sizeof(uint32_t));
462 uint8_t *pbXApic = (uint8_t *)pXApicPage;
463 *(uint32_t *)(pbXApic + offReg) = uReg;
464}
465
466
467/**
468 * Broadcasts the EOI to the I/O APICs.
469 *
470 * @param pVCpu The cross context virtual CPU structure.
471 * @param uVector The interrupt vector corresponding to the EOI.
472 */
473DECLINLINE(void) apicBusBroadcastEoi(PVMCPU pVCpu, uint8_t uVector)
474{
475 PVM pVM = pVCpu->CTX_SUFF(pVM);
476 PAPICDEV pApicDev = VM_TO_APICDEV(pVM);
477 pApicDev->CTX_SUFF(pApicHlp)->pfnBusBroadcastEoi(pApicDev->CTX_SUFF(pDevIns), uVector);
478}
479
480
481/**
482 * Sets an error in the internal ESR of the specified APIC.
483 *
484 * @param pVCpu The cross context virtual CPU structure.
485 * @param uError The error.
486 * @thread Any.
487 */
488DECLINLINE(void) apicSetError(PVMCPU pVCpu, uint32_t uError)
489{
490 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
491 ASMAtomicOrU32(&pApicCpu->uEsrInternal, uError);
492}
493
494
495/**
496 * Clears all errors in the internal ESR.
497 *
498 * @returns The value of the internal ESR before clearing.
499 * @param pVCpu The cross context virtual CPU structure.
500 */
501DECLINLINE(uint32_t) apicClearAllErrors(PVMCPU pVCpu)
502{
503 VMCPU_ASSERT_EMT(pVCpu);
504 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
505 return ASMAtomicXchgU32(&pApicCpu->uEsrInternal, 0);
506}
507
508
509/**
510 * Signals the guest if a pending interrupt is ready to be serviced.
511 *
512 * @param pVCpu The cross context virtual CPU structure.
513 */
514static void apicSignalNextPendingIntr(PVMCPU pVCpu)
515{
516 VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
517
518 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
519 if (pXApicPage->svr.u.fApicSoftwareEnable)
520 {
521 int const irrv = apicGetHighestSetBitInReg(&pXApicPage->irr, -1 /* rcNotFound */);
522 if (irrv >= 0)
523 {
524 Assert(irrv <= (int)UINT8_MAX);
525 uint8_t const uVector = irrv;
526 uint8_t const uPpr = pXApicPage->ppr.u8Ppr;
527 if ( !uPpr
528 || XAPIC_PPR_GET_PP(uVector) > XAPIC_PPR_GET_PP(uPpr))
529 {
530 Log2(("APIC%u: apicSignalNextPendingIntr: Signaling pending interrupt. uVector=%#x\n", pVCpu->idCpu, uVector));
531 APICSetInterruptFF(pVCpu, PDMAPICIRQ_HARDWARE);
532 }
533 else
534 {
535 Log2(("APIC%u: apicSignalNextPendingIntr: Nothing to signal. uVector=%#x uPpr=%#x uTpr=%#x\n", pVCpu->idCpu,
536 uVector, uPpr, pXApicPage->tpr.u8Tpr));
537 }
538 }
539 }
540 else
541 {
542 Log2(("APIC%u: apicSignalNextPendingIntr: APIC software-disabled, clearing pending interrupt\n", pVCpu->idCpu));
543 APICClearInterruptFF(pVCpu, PDMAPICIRQ_HARDWARE);
544 }
545}
546
547
548/**
549 * Sets the Spurious-Interrupt Vector Register (SVR).
550 *
551 * @returns Strict VBox status code.
552 * @param pVCpu The cross context virtual CPU structure.
553 * @param uSvr The SVR value.
554 */
555static VBOXSTRICTRC apicSetSvr(PVMCPU pVCpu, uint32_t uSvr)
556{
557 VMCPU_ASSERT_EMT(pVCpu);
558
559 uint32_t uValidMask = XAPIC_SVR_VALID;
560 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
561 if (pXApicPage->version.u.fEoiBroadcastSupression)
562 uValidMask |= XAPIC_SVR_SUPRESS_EOI_BROADCAST;
563
564 if ( XAPIC_IN_X2APIC_MODE(pVCpu)
565 && (uSvr & ~uValidMask))
566 return apicMsrAccessError(pVCpu, MSR_IA32_X2APIC_SVR, APICMSRACCESS_WRITE_RSVD_BITS);
567
568 Log2(("APIC%u: apicSetSvr: uSvr=%#RX32\n", pVCpu->idCpu, uSvr));
569 apicWriteRaw32(pXApicPage, XAPIC_OFF_SVR, uSvr);
570 if (!pXApicPage->svr.u.fApicSoftwareEnable)
571 {
572 /** @todo CMCI. */
573 pXApicPage->lvt_timer.u.u1Mask = 1;
574#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
575 pXApicPage->lvt_thermal.u.u1Mask = 1;
576#endif
577 pXApicPage->lvt_perf.u.u1Mask = 1;
578 pXApicPage->lvt_lint0.u.u1Mask = 1;
579 pXApicPage->lvt_lint1.u.u1Mask = 1;
580 pXApicPage->lvt_error.u.u1Mask = 1;
581 }
582
583 apicSignalNextPendingIntr(pVCpu);
584 return VINF_SUCCESS;
585}
586
587
588/**
589 * Sends an interrupt to one or more APICs.
590 *
591 * @returns Strict VBox status code.
592 * @param pVM The cross context VM structure.
593 * @param pVCpu The cross context virtual CPU structure, can be
594 * NULL if the source of the interrupt is not an
595 * APIC (for e.g. a bus).
596 * @param uVector The interrupt vector.
597 * @param enmTriggerMode The trigger mode.
598 * @param enmDeliveryMode The delivery mode.
599 * @param pDestCpuSet The destination CPU set.
600 * @param rcRZ The return code if the operation cannot be
601 * performed in the current context.
602 */
603static VBOXSTRICTRC apicSendIntr(PVM pVM, PVMCPU pVCpu, uint8_t uVector, XAPICTRIGGERMODE enmTriggerMode,
604 XAPICDELIVERYMODE enmDeliveryMode, PCVMCPUSET pDestCpuSet, int rcRZ)
605{
606 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
607 VMCPUID const cCpus = pVM->cCpus;
608 switch (enmDeliveryMode)
609 {
610 case XAPICDELIVERYMODE_FIXED:
611 {
612 for (VMCPUID idCpu = 0; idCpu < cCpus; idCpu++)
613 {
614 if ( VMCPUSET_IS_PRESENT(pDestCpuSet, idCpu)
615 && apicIsEnabled(&pVM->aCpus[idCpu]))
616 APICPostInterrupt(&pVM->aCpus[idCpu], uVector, enmTriggerMode);
617 }
618 break;
619 }
620
621 case XAPICDELIVERYMODE_LOWEST_PRIO:
622 {
623 VMCPUID const idCpu = VMCPUSET_FIND_FIRST_PRESENT(pDestCpuSet);
624 if ( idCpu < pVM->cCpus
625 && apicIsEnabled(&pVM->aCpus[idCpu]))
626 APICPostInterrupt(&pVM->aCpus[idCpu], uVector, enmTriggerMode);
627 else
628 Log2(("APIC: apicSendIntr: No CPU found for lowest-priority delivery mode!\n"));
629 break;
630 }
631
632 case XAPICDELIVERYMODE_SMI:
633 {
634 for (VMCPUID idCpu = 0; idCpu < cCpus; idCpu++)
635 {
636 if (VMCPUSET_IS_PRESENT(pDestCpuSet, idCpu))
637 {
638 Log2(("APIC: apicSendIntr: Raising SMI on VCPU%u\n", idCpu));
639 APICSetInterruptFF(&pVM->aCpus[idCpu], PDMAPICIRQ_SMI);
640 }
641 }
642 break;
643 }
644
645 case XAPICDELIVERYMODE_NMI:
646 {
647 for (VMCPUID idCpu = 0; idCpu < cCpus; idCpu++)
648 {
649 if ( VMCPUSET_IS_PRESENT(pDestCpuSet, idCpu)
650 && apicIsEnabled(&pVM->aCpus[idCpu]))
651 {
652 Log2(("APIC: apicSendIntr: Raising NMI on VCPU%u\n", idCpu));
653 APICSetInterruptFF(&pVM->aCpus[idCpu], PDMAPICIRQ_NMI);
654 }
655 }
656 break;
657 }
658
659 case XAPICDELIVERYMODE_INIT:
660 {
661#ifdef IN_RING3
662 for (VMCPUID idCpu = 0; idCpu < cCpus; idCpu++)
663 if (VMCPUSET_IS_PRESENT(pDestCpuSet, idCpu))
664 {
665 Log2(("APIC: apicSendIntr: Issuing INIT to VCPU%u\n", idCpu));
666 VMMR3SendInitIpi(pVM, idCpu);
667 }
668#else
669 /* We need to return to ring-3 to deliver the INIT. */
670 rcStrict = rcRZ;
671#endif
672 break;
673 }
674
675 case XAPICDELIVERYMODE_STARTUP:
676 {
677#ifdef IN_RING3
678 for (VMCPUID idCpu = 0; idCpu < cCpus; idCpu++)
679 if (VMCPUSET_IS_PRESENT(pDestCpuSet, idCpu))
680 {
681 Log2(("APIC: apicSendIntr: Issuing SIPI to VCPU%u\n", idCpu));
682 VMMR3SendStartupIpi(pVM, idCpu, uVector);
683 }
684#else
685 /* We need to return to ring-3 to deliver the SIPI. */
686 rcStrict = rcRZ;
687 Log2(("APIC: apicSendIntr: SIPI issued, returning to RZ. rc=%Rrc\n", rcRZ));
688#endif
689 break;
690 }
691
692 case XAPICDELIVERYMODE_EXTINT:
693 {
694 for (VMCPUID idCpu = 0; idCpu < cCpus; idCpu++)
695 if (VMCPUSET_IS_PRESENT(pDestCpuSet, idCpu))
696 {
697 Log2(("APIC: apicSendIntr: Raising EXTINT on VCPU%u\n", idCpu));
698 APICSetInterruptFF(&pVM->aCpus[idCpu], PDMAPICIRQ_EXTINT);
699 }
700 break;
701 }
702
703 default:
704 {
705 AssertMsgFailed(("APIC: apicSendIntr: Unsupported delivery mode %#x (%s)\n", enmDeliveryMode,
706 apicGetDeliveryModeName(enmDeliveryMode)));
707 break;
708 }
709 }
710
711 /*
712 * If an illegal vector is programmed, set the 'send illegal vector' error here if the
713 * interrupt is being sent by an APIC.
714 *
715 * The 'receive illegal vector' will be set on the target APIC when the interrupt
716 * gets generated, see APICPostInterrupt().
717 *
718 * See Intel spec. 10.5.3 "Error Handling".
719 */
720 if ( rcStrict != rcRZ
721 && pVCpu)
722 {
723 /*
724 * Flag only errors when the delivery mode is fixed and not others.
725 *
726 * Ubuntu 10.04-3 amd64 live CD with 2 VCPUs gets upset as it sends an SIPI to the
727 * 2nd VCPU with vector 6 and checks the ESR for no errors, see @bugref{8245#c86}.
728 */
729 /** @todo The spec says this for LVT, but not explcitly for ICR-lo
730 * but it probably is true. */
731 if (enmDeliveryMode == XAPICDELIVERYMODE_FIXED)
732 {
733 if (RT_UNLIKELY(uVector <= XAPIC_ILLEGAL_VECTOR_END))
734 apicSetError(pVCpu, XAPIC_ESR_SEND_ILLEGAL_VECTOR);
735 }
736 }
737 return rcStrict;
738}
739
740
741/**
742 * Checks if this APIC belongs to a logical destination.
743 *
744 * @returns true if the APIC belongs to the logical
745 * destination, false otherwise.
746 * @param pVCpu The cross context virtual CPU structure.
747 * @param fDest The destination mask.
748 *
749 * @thread Any.
750 */
751static bool apicIsLogicalDest(PVMCPU pVCpu, uint32_t fDest)
752{
753 if (XAPIC_IN_X2APIC_MODE(pVCpu))
754 {
755 /*
756 * Flat logical mode is not supported in x2APIC mode.
757 * In clustered logical mode, the 32-bit logical ID in the LDR is interpreted as follows:
758 * - High 16 bits is the cluster ID.
759 * - Low 16 bits: each bit represents a unique APIC within the cluster.
760 */
761 PCX2APICPAGE pX2ApicPage = VMCPU_TO_CX2APICPAGE(pVCpu);
762 uint32_t const u32Ldr = pX2ApicPage->ldr.u32LogicalApicId;
763 if (X2APIC_LDR_GET_CLUSTER_ID(u32Ldr) == (fDest & X2APIC_LDR_CLUSTER_ID))
764 return RT_BOOL(u32Ldr & fDest & X2APIC_LDR_LOGICAL_ID);
765 return false;
766 }
767
768#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
769 /*
770 * In both flat and clustered logical mode, a destination mask of all set bits indicates a broadcast.
771 * See AMD spec. 16.6.1 "Receiving System and IPI Interrupts".
772 */
773 Assert(!XAPIC_IN_X2APIC_MODE(pVCpu));
774 if ((fDest & XAPIC_LDR_FLAT_LOGICAL_ID) == XAPIC_LDR_FLAT_LOGICAL_ID)
775 return true;
776
777 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
778 XAPICDESTFORMAT enmDestFormat = (XAPICDESTFORMAT)pXApicPage->dfr.u.u4Model;
779 if (enmDestFormat == XAPICDESTFORMAT_FLAT)
780 {
781 /* The destination mask is interpreted as a bitmap of 8 unique logical APIC IDs. */
782 uint8_t const u8Ldr = pXApicPage->ldr.u.u8LogicalApicId;
783 return RT_BOOL(u8Ldr & fDest & XAPIC_LDR_FLAT_LOGICAL_ID);
784 }
785
786 /*
787 * In clustered logical mode, the 8-bit logical ID in the LDR is interpreted as follows:
788 * - High 4 bits is the cluster ID.
789 * - Low 4 bits: each bit represents a unique APIC within the cluster.
790 */
791 Assert(enmDestFormat == XAPICDESTFORMAT_CLUSTER);
792 uint8_t const u8Ldr = pXApicPage->ldr.u.u8LogicalApicId;
793 if (XAPIC_LDR_CLUSTERED_GET_CLUSTER_ID(u8Ldr) == (fDest & XAPIC_LDR_CLUSTERED_CLUSTER_ID))
794 return RT_BOOL(u8Ldr & fDest & XAPIC_LDR_CLUSTERED_LOGICAL_ID);
795 return false;
796#else
797# error "Implement Pentium and P6 family APIC architectures"
798#endif
799}
800
801
802/**
803 * Figures out the set of destination CPUs for a given destination mode, format
804 * and delivery mode setting.
805 *
806 * @param pVM The cross context VM structure.
807 * @param fDestMask The destination mask.
808 * @param fBroadcastMask The broadcast mask.
809 * @param enmDestMode The destination mode.
810 * @param enmDeliveryMode The delivery mode.
811 * @param pDestCpuSet The destination CPU set to update.
812 */
813static void apicGetDestCpuSet(PVM pVM, uint32_t fDestMask, uint32_t fBroadcastMask, XAPICDESTMODE enmDestMode,
814 XAPICDELIVERYMODE enmDeliveryMode, PVMCPUSET pDestCpuSet)
815{
816 VMCPUSET_EMPTY(pDestCpuSet);
817
818 /*
819 * Physical destination mode only supports either a broadcast or a single target.
820 * - Broadcast with lowest-priority delivery mode is not supported[1], we deliver it
821 * as a regular broadcast like in fixed delivery mode.
822 * - For a single target, lowest-priority delivery mode makes no sense. We deliver
823 * to the target like in fixed delivery mode.
824 *
825 * [1] See Intel spec. 10.6.2.1 "Physical Destination Mode".
826 */
827 if ( enmDestMode == XAPICDESTMODE_PHYSICAL
828 && enmDeliveryMode == XAPICDELIVERYMODE_LOWEST_PRIO)
829 {
830 AssertMsgFailed(("APIC: Lowest-priority delivery using physical destination mode!"));
831 enmDeliveryMode = XAPICDELIVERYMODE_FIXED;
832 }
833
834 uint32_t const cCpus = pVM->cCpus;
835 if (enmDeliveryMode == XAPICDELIVERYMODE_LOWEST_PRIO)
836 {
837 Assert(enmDestMode == XAPICDESTMODE_LOGICAL);
838#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
839 VMCPUID idCpuLowestTpr = NIL_VMCPUID;
840 uint8_t u8LowestTpr = UINT8_C(0xff);
841 for (VMCPUID idCpu = 0; idCpu < cCpus; idCpu++)
842 {
843 PVMCPU pVCpuDest = &pVM->aCpus[idCpu];
844 if (apicIsLogicalDest(pVCpuDest, fDestMask))
845 {
846 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpuDest);
847 uint8_t const u8Tpr = pXApicPage->tpr.u8Tpr; /* PAV */
848
849 /*
850 * If there is a tie for lowest priority, the local APIC with the highest ID is chosen.
851 * Hence the use of "<=" in the check below.
852 * See AMD spec. 16.6.2 "Lowest Priority Messages and Arbitration".
853 */
854 if (u8Tpr <= u8LowestTpr)
855 {
856 u8LowestTpr = u8Tpr;
857 idCpuLowestTpr = idCpu;
858 }
859 }
860 }
861 if (idCpuLowestTpr != NIL_VMCPUID)
862 VMCPUSET_ADD(pDestCpuSet, idCpuLowestTpr);
863#else
864# error "Implement Pentium and P6 family APIC architectures"
865#endif
866 return;
867 }
868
869 /*
870 * x2APIC:
871 * - In both physical and logical destination mode, a destination mask of 0xffffffff implies a broadcast[1].
872 * xAPIC:
873 * - In physical destination mode, a destination mask of 0xff implies a broadcast[2].
874 * - In both flat and clustered logical mode, a destination mask of 0xff implies a broadcast[3].
875 *
876 * [1] See Intel spec. 10.12.9 "ICR Operation in x2APIC Mode".
877 * [2] See Intel spec. 10.6.2.1 "Physical Destination Mode".
878 * [2] See AMD spec. 16.6.1 "Receiving System and IPI Interrupts".
879 */
880 if ((fDestMask & fBroadcastMask) == fBroadcastMask)
881 {
882 VMCPUSET_FILL(pDestCpuSet);
883 return;
884 }
885
886 if (enmDestMode == XAPICDESTMODE_PHYSICAL)
887 {
888 /* The destination mask is interpreted as the physical APIC ID of a single target. */
889#if 1
890 /* Since our physical APIC ID is read-only to software, set the corresponding bit in the CPU set. */
891 if (RT_LIKELY(fDestMask < cCpus))
892 VMCPUSET_ADD(pDestCpuSet, fDestMask);
893#else
894 /* The physical APIC ID may not match our VCPU ID, search through the list of targets. */
895 for (VMCPUID idCpu = 0; idCpu < cCpus; idCpu++)
896 {
897 PVMCPU pVCpuDest = &pVM->aCpus[idCpu];
898 if (XAPIC_IN_X2APIC_MODE(pVCpuDest))
899 {
900 PCX2APICPAGE pX2ApicPage = VMCPU_TO_CX2APICPAGE(pVCpuDest);
901 if (pX2ApicPage->id.u32ApicId == fDestMask)
902 VMCPUSET_ADD(pDestCpuSet, pVCpuDest->idCpu);
903 }
904 else
905 {
906 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpuDest);
907 if (pXApicPage->id.u8ApicId == (uint8_t)fDestMask)
908 VMCPUSET_ADD(pDestCpuSet, pVCpuDest->idCpu);
909 }
910 }
911#endif
912 }
913 else
914 {
915 Assert(enmDestMode == XAPICDESTMODE_LOGICAL);
916
917 /* A destination mask of all 0's implies no target APICs (since it's interpreted as a bitmap or partial bitmap). */
918 if (RT_UNLIKELY(!fDestMask))
919 return;
920
921 /* The destination mask is interpreted as a bitmap of software-programmable logical APIC ID of the target APICs. */
922 for (VMCPUID idCpu = 0; idCpu < cCpus; idCpu++)
923 {
924 PVMCPU pVCpuDest = &pVM->aCpus[idCpu];
925 if (apicIsLogicalDest(pVCpuDest, fDestMask))
926 VMCPUSET_ADD(pDestCpuSet, pVCpuDest->idCpu);
927 }
928 }
929}
930
931
932/**
933 * Sends an Interprocessor Interrupt (IPI) using values from the Interrupt
934 * Command Register (ICR).
935 *
936 * @returns VBox status code.
937 * @param pVCpu The cross context virtual CPU structure.
938 * @param rcRZ The return code if the operation cannot be
939 * performed in the current context.
940 */
941DECLINLINE(VBOXSTRICTRC) apicSendIpi(PVMCPU pVCpu, int rcRZ)
942{
943 VMCPU_ASSERT_EMT(pVCpu);
944
945 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
946 XAPICDELIVERYMODE const enmDeliveryMode = (XAPICDELIVERYMODE)pXApicPage->icr_lo.u.u3DeliveryMode;
947 XAPICDESTMODE const enmDestMode = (XAPICDESTMODE)pXApicPage->icr_lo.u.u1DestMode;
948 XAPICINITLEVEL const enmInitLevel = (XAPICINITLEVEL)pXApicPage->icr_lo.u.u1Level;
949 XAPICTRIGGERMODE const enmTriggerMode = (XAPICTRIGGERMODE)pXApicPage->icr_lo.u.u1TriggerMode;
950 XAPICDESTSHORTHAND const enmDestShorthand = (XAPICDESTSHORTHAND)pXApicPage->icr_lo.u.u2DestShorthand;
951 uint8_t const uVector = pXApicPage->icr_lo.u.u8Vector;
952
953 PX2APICPAGE pX2ApicPage = VMCPU_TO_X2APICPAGE(pVCpu);
954 uint32_t const fDest = XAPIC_IN_X2APIC_MODE(pVCpu) ? pX2ApicPage->icr_hi.u32IcrHi : pXApicPage->icr_hi.u.u8Dest;
955
956#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
957 /*
958 * INIT Level De-assert is not support on Pentium 4 and Xeon processors.
959 * See AMD spec. 16.5 "Interprocessor Interrupts (IPI)" for a table of valid ICR combinations.
960 */
961 if (RT_UNLIKELY( enmDeliveryMode == XAPICDELIVERYMODE_INIT_LEVEL_DEASSERT
962 && enmInitLevel == XAPICINITLEVEL_DEASSERT
963 && enmTriggerMode == XAPICTRIGGERMODE_LEVEL))
964 {
965 Log2(("APIC%u: INIT level de-assert unsupported, ignoring!\n", pVCpu->idCpu));
966 return VINF_SUCCESS;
967 }
968#else
969# error "Implement Pentium and P6 family APIC architectures"
970#endif
971
972 /*
973 * The destination and delivery modes are ignored/by-passed when a destination shorthand is specified.
974 * See Intel spec. 10.6.2.3 "Broadcast/Self Delivery Mode".
975 */
976 VMCPUSET DestCpuSet;
977 switch (enmDestShorthand)
978 {
979 case XAPICDESTSHORTHAND_NONE:
980 {
981 PVM pVM = pVCpu->CTX_SUFF(pVM);
982 uint32_t const fBroadcastMask = XAPIC_IN_X2APIC_MODE(pVCpu) ? X2APIC_ID_BROADCAST_MASK : XAPIC_ID_BROADCAST_MASK;
983 apicGetDestCpuSet(pVM, fDest, fBroadcastMask, enmDestMode, enmDeliveryMode, &DestCpuSet);
984 break;
985 }
986
987 case XAPICDESTSHORTHAND_SELF:
988 {
989 VMCPUSET_EMPTY(&DestCpuSet);
990 VMCPUSET_ADD(&DestCpuSet, pVCpu->idCpu);
991 break;
992 }
993
994 case XAPIDDESTSHORTHAND_ALL_INCL_SELF:
995 {
996 VMCPUSET_FILL(&DestCpuSet);
997 break;
998 }
999
1000 case XAPICDESTSHORTHAND_ALL_EXCL_SELF:
1001 {
1002 VMCPUSET_FILL(&DestCpuSet);
1003 VMCPUSET_DEL(&DestCpuSet, pVCpu->idCpu);
1004 break;
1005 }
1006 }
1007
1008 return apicSendIntr(pVCpu->CTX_SUFF(pVM), pVCpu, uVector, enmTriggerMode, enmDeliveryMode, &DestCpuSet, rcRZ);
1009}
1010
1011
1012/**
1013 * Sets the Interrupt Command Register (ICR) high dword.
1014 *
1015 * @returns Strict VBox status code.
1016 * @param pVCpu The cross context virtual CPU structure.
1017 * @param uIcrHi The ICR high dword.
1018 */
1019static VBOXSTRICTRC apicSetIcrHi(PVMCPU pVCpu, uint32_t uIcrHi)
1020{
1021 VMCPU_ASSERT_EMT(pVCpu);
1022 Assert(!XAPIC_IN_X2APIC_MODE(pVCpu));
1023
1024 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1025 pXApicPage->icr_hi.all.u32IcrHi = uIcrHi & XAPIC_ICR_HI_DEST;
1026 Log2(("APIC%u: apicSetIcrHi: uIcrHi=%#RX32\n", pVCpu->idCpu, pXApicPage->icr_hi.all.u32IcrHi));
1027
1028 return VINF_SUCCESS;
1029}
1030
1031
1032/**
1033 * Sets the Interrupt Command Register (ICR) low dword.
1034 *
1035 * @returns Strict VBox status code.
1036 * @param pVCpu The cross context virtual CPU structure.
1037 * @param uIcrLo The ICR low dword.
1038 * @param rcRZ The return code if the operation cannot be performed
1039 * in the current context.
1040 */
1041static VBOXSTRICTRC apicSetIcrLo(PVMCPU pVCpu, uint32_t uIcrLo, int rcRZ)
1042{
1043 VMCPU_ASSERT_EMT(pVCpu);
1044
1045 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1046 pXApicPage->icr_lo.all.u32IcrLo = uIcrLo & XAPIC_ICR_LO_WR_VALID;
1047 Log2(("APIC%u: apicSetIcrLo: uIcrLo=%#RX32\n", pVCpu->idCpu, pXApicPage->icr_lo.all.u32IcrLo));
1048 STAM_COUNTER_INC(&pVCpu->apic.s.StatIcrLoWrite);
1049
1050 return apicSendIpi(pVCpu, rcRZ);
1051}
1052
1053
1054/**
1055 * Sets the Interrupt Command Register (ICR).
1056 *
1057 * @returns Strict VBox status code.
1058 * @param pVCpu The cross context virtual CPU structure.
1059 * @param u64Icr The ICR (High and Low combined).
1060 * @param rcRZ The return code if the operation cannot be performed
1061 * in the current context.
1062 */
1063static VBOXSTRICTRC apicSetIcr(PVMCPU pVCpu, uint64_t u64Icr, int rcRZ)
1064{
1065 VMCPU_ASSERT_EMT(pVCpu);
1066 Assert(XAPIC_IN_X2APIC_MODE(pVCpu));
1067
1068 /* Validate. */
1069 uint32_t const uLo = RT_LO_U32(u64Icr);
1070 if (RT_LIKELY(!(uLo & ~XAPIC_ICR_LO_WR_VALID)))
1071 {
1072 /* Update high dword first, then update the low dword which sends the IPI. */
1073 PX2APICPAGE pX2ApicPage = VMCPU_TO_X2APICPAGE(pVCpu);
1074 pX2ApicPage->icr_hi.u32IcrHi = RT_HI_U32(u64Icr);
1075 return apicSetIcrLo(pVCpu, uLo, rcRZ);
1076 }
1077 return apicMsrAccessError(pVCpu, MSR_IA32_X2APIC_ICR, APICMSRACCESS_WRITE_RSVD_BITS);
1078}
1079
1080
1081/**
1082 * Sets the Error Status Register (ESR).
1083 *
1084 * @returns Strict VBox status code.
1085 * @param pVCpu The cross context virtual CPU structure.
1086 * @param uEsr The ESR value.
1087 */
1088static VBOXSTRICTRC apicSetEsr(PVMCPU pVCpu, uint32_t uEsr)
1089{
1090 VMCPU_ASSERT_EMT(pVCpu);
1091
1092 Log2(("APIC%u: apicSetEsr: uEsr=%#RX32\n", pVCpu->idCpu, uEsr));
1093
1094 if ( XAPIC_IN_X2APIC_MODE(pVCpu)
1095 && (uEsr & ~XAPIC_ESR_WO_VALID))
1096 return apicMsrAccessError(pVCpu, MSR_IA32_X2APIC_ESR, APICMSRACCESS_WRITE_RSVD_BITS);
1097
1098 /*
1099 * Writes to the ESR causes the internal state to be updated in the register,
1100 * clearing the original state. See AMD spec. 16.4.6 "APIC Error Interrupts".
1101 */
1102 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1103 pXApicPage->esr.all.u32Errors = apicClearAllErrors(pVCpu);
1104 return VINF_SUCCESS;
1105}
1106
1107
1108/**
1109 * Updates the Processor Priority Register (PPR).
1110 *
1111 * @param pVCpu The cross context virtual CPU structure.
1112 */
1113static void apicUpdatePpr(PVMCPU pVCpu)
1114{
1115 VMCPU_ASSERT_EMT(pVCpu);
1116
1117 /* See Intel spec 10.8.3.1 "Task and Processor Priorities". */
1118 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1119 uint8_t const uIsrv = apicGetHighestSetBitInReg(&pXApicPage->isr, 0 /* rcNotFound */);
1120 uint8_t uPpr;
1121 if (XAPIC_TPR_GET_TP(pXApicPage->tpr.u8Tpr) >= XAPIC_PPR_GET_PP(uIsrv))
1122 uPpr = pXApicPage->tpr.u8Tpr;
1123 else
1124 uPpr = XAPIC_PPR_GET_PP(uIsrv);
1125 pXApicPage->ppr.u8Ppr = uPpr;
1126}
1127
1128
1129/**
1130 * Gets the Processor Priority Register (PPR).
1131 *
1132 * @returns The PPR value.
1133 * @param pVCpu The cross context virtual CPU structure.
1134 */
1135static uint8_t apicGetPpr(PVMCPU pVCpu)
1136{
1137 VMCPU_ASSERT_EMT(pVCpu);
1138 STAM_COUNTER_INC(&pVCpu->apic.s.StatTprRead);
1139
1140 /*
1141 * With virtualized APIC registers or with TPR virtualization, the hardware may
1142 * update ISR/TPR transparently. We thus re-calculate the PPR which may be out of sync.
1143 * See Intel spec. 29.2.2 "Virtual-Interrupt Delivery".
1144 *
1145 * In all other instances, whenever the TPR or ISR changes, we need to update the PPR
1146 * as well (e.g. like we do manually in apicR3InitIpi and by calling apicUpdatePpr).
1147 */
1148 PCAPIC pApic = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
1149 if (pApic->fVirtApicRegsEnabled) /** @todo re-think this */
1150 apicUpdatePpr(pVCpu);
1151 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
1152 return pXApicPage->ppr.u8Ppr;
1153}
1154
1155
1156/**
1157 * Sets the Task Priority Register (TPR).
1158 *
1159 * @returns Strict VBox status code.
1160 * @param pVCpu The cross context virtual CPU structure.
1161 * @param uTpr The TPR value.
1162 */
1163static VBOXSTRICTRC apicSetTpr(PVMCPU pVCpu, uint32_t uTpr)
1164{
1165 VMCPU_ASSERT_EMT(pVCpu);
1166
1167 Log2(("APIC%u: apicSetTpr: uTpr=%#RX32\n", pVCpu->idCpu, uTpr));
1168 STAM_COUNTER_INC(&pVCpu->apic.s.StatTprWrite);
1169
1170 if ( XAPIC_IN_X2APIC_MODE(pVCpu)
1171 && (uTpr & ~XAPIC_TPR_VALID))
1172 return apicMsrAccessError(pVCpu, MSR_IA32_X2APIC_TPR, APICMSRACCESS_WRITE_RSVD_BITS);
1173
1174 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1175 pXApicPage->tpr.u8Tpr = uTpr;
1176 apicUpdatePpr(pVCpu);
1177 apicSignalNextPendingIntr(pVCpu);
1178 return VINF_SUCCESS;
1179}
1180
1181
1182/**
1183 * Sets the End-Of-Interrupt (EOI) register.
1184 *
1185 * @returns Strict VBox status code.
1186 * @param pVCpu The cross context virtual CPU structure.
1187 * @param uEoi The EOI value.
1188 */
1189static VBOXSTRICTRC apicSetEoi(PVMCPU pVCpu, uint32_t uEoi)
1190{
1191 VMCPU_ASSERT_EMT(pVCpu);
1192
1193 Log2(("APIC%u: apicSetEoi: uEoi=%#RX32\n", pVCpu->idCpu, uEoi));
1194 STAM_COUNTER_INC(&pVCpu->apic.s.StatEoiWrite);
1195
1196 if ( XAPIC_IN_X2APIC_MODE(pVCpu)
1197 && (uEoi & ~XAPIC_EOI_WO_VALID))
1198 return apicMsrAccessError(pVCpu, MSR_IA32_X2APIC_EOI, APICMSRACCESS_WRITE_RSVD_BITS);
1199
1200 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1201 int isrv = apicGetHighestSetBitInReg(&pXApicPage->isr, -1 /* rcNotFound */);
1202 if (isrv >= 0)
1203 {
1204 Assert(isrv <= (int)UINT8_MAX);
1205 uint8_t const uVector = isrv;
1206 apicClearVectorInReg(&pXApicPage->isr, uVector);
1207 apicUpdatePpr(pVCpu);
1208 Log2(("APIC%u: apicSetEoi: Cleared interrupt from ISR. uVector=%#x\n", pVCpu->idCpu, uVector));
1209
1210 bool fLevelTriggered = apicTestVectorInReg(&pXApicPage->tmr, uVector);
1211 if (fLevelTriggered)
1212 {
1213 apicClearVectorInReg(&pXApicPage->tmr, uVector);
1214 apicBusBroadcastEoi(pVCpu, uVector);
1215
1216 /*
1217 * Clear the remote IRR bit for level-triggered, fixed mode LINT0 interrupt.
1218 * The LINT1 pin does not support level-triggered interrupts.
1219 * See Intel spec. 10.5.1 "Local Vector Table".
1220 */
1221 uint32_t const uLvtLint0 = pXApicPage->lvt_lint0.all.u32LvtLint0;
1222 if ( XAPIC_LVT_GET_REMOTE_IRR(uLvtLint0)
1223 && XAPIC_LVT_GET_VECTOR(uLvtLint0) == uVector
1224 && XAPIC_LVT_GET_DELIVERY_MODE(uLvtLint0) == XAPICDELIVERYMODE_FIXED)
1225 {
1226 ASMAtomicAndU32((volatile uint32_t *)&pXApicPage->lvt_lint0.all.u32LvtLint0, ~XAPIC_LVT_REMOTE_IRR);
1227 Log2(("APIC%u: apicSetEoi: Cleared remote-IRR for LINT0. uVector=%#x\n", pVCpu->idCpu, uVector));
1228 }
1229
1230 Log2(("APIC%u: apicSetEoi: Cleared level triggered interrupt from TMR. uVector=%#x\n", pVCpu->idCpu, uVector));
1231 }
1232
1233 apicSignalNextPendingIntr(pVCpu);
1234 }
1235
1236 return VINF_SUCCESS;
1237}
1238
1239
1240/**
1241 * Sets the Logical Destination Register (LDR).
1242 *
1243 * @returns Strict VBox status code.
1244 * @param pVCpu The cross context virtual CPU structure.
1245 * @param uLdr The LDR value.
1246 *
1247 * @remarks LDR is read-only in x2APIC mode.
1248 */
1249static VBOXSTRICTRC apicSetLdr(PVMCPU pVCpu, uint32_t uLdr)
1250{
1251 VMCPU_ASSERT_EMT(pVCpu);
1252 Assert(!XAPIC_IN_X2APIC_MODE(pVCpu));
1253
1254 Log2(("APIC%u: apicSetLdr: uLdr=%#RX32\n", pVCpu->idCpu, uLdr));
1255
1256 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1257 apicWriteRaw32(pXApicPage, XAPIC_OFF_LDR, uLdr & XAPIC_LDR_VALID);
1258 return VINF_SUCCESS;
1259}
1260
1261
1262/**
1263 * Sets the Destination Format Register (DFR).
1264 *
1265 * @returns Strict VBox status code.
1266 * @param pVCpu The cross context virtual CPU structure.
1267 * @param uDfr The DFR value.
1268 *
1269 * @remarks DFR is not available in x2APIC mode.
1270 */
1271static VBOXSTRICTRC apicSetDfr(PVMCPU pVCpu, uint32_t uDfr)
1272{
1273 VMCPU_ASSERT_EMT(pVCpu);
1274 Assert(!XAPIC_IN_X2APIC_MODE(pVCpu));
1275
1276 uDfr &= XAPIC_DFR_VALID;
1277 uDfr |= XAPIC_DFR_RSVD_MB1;
1278
1279 Log2(("APIC%u: apicSetDfr: uDfr=%#RX32\n", pVCpu->idCpu, uDfr));
1280
1281 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1282 apicWriteRaw32(pXApicPage, XAPIC_OFF_DFR, uDfr);
1283 return VINF_SUCCESS;
1284}
1285
1286
1287/**
1288 * Sets the Timer Divide Configuration Register (DCR).
1289 *
1290 * @returns Strict VBox status code.
1291 * @param pVCpu The cross context virtual CPU structure.
1292 * @param uTimerDcr The timer DCR value.
1293 */
1294static VBOXSTRICTRC apicSetTimerDcr(PVMCPU pVCpu, uint32_t uTimerDcr)
1295{
1296 VMCPU_ASSERT_EMT(pVCpu);
1297 if ( XAPIC_IN_X2APIC_MODE(pVCpu)
1298 && (uTimerDcr & ~XAPIC_TIMER_DCR_VALID))
1299 return apicMsrAccessError(pVCpu, MSR_IA32_X2APIC_TIMER_DCR, APICMSRACCESS_WRITE_RSVD_BITS);
1300
1301 Log2(("APIC%u: apicSetTimerDcr: uTimerDcr=%#RX32\n", pVCpu->idCpu, uTimerDcr));
1302
1303 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1304 apicWriteRaw32(pXApicPage, XAPIC_OFF_TIMER_DCR, uTimerDcr);
1305 return VINF_SUCCESS;
1306}
1307
1308
1309/**
1310 * Gets the timer's Current Count Register (CCR).
1311 *
1312 * @returns VBox status code.
1313 * @param pVCpu The cross context virtual CPU structure.
1314 * @param rcBusy The busy return code for the timer critical section.
1315 * @param puValue Where to store the LVT timer CCR.
1316 */
1317static VBOXSTRICTRC apicGetTimerCcr(PVMCPU pVCpu, int rcBusy, uint32_t *puValue)
1318{
1319 VMCPU_ASSERT_EMT(pVCpu);
1320 Assert(puValue);
1321
1322 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
1323 *puValue = 0;
1324
1325 /* In TSC-deadline mode, CCR returns 0, see Intel spec. 10.5.4.1 "TSC-Deadline Mode". */
1326 if (pXApicPage->lvt_timer.u.u2TimerMode == XAPIC_TIMER_MODE_TSC_DEADLINE)
1327 return VINF_SUCCESS;
1328
1329 /* If the initial-count register is 0, CCR returns 0 as it cannot exceed the ICR. */
1330 uint32_t const uInitialCount = pXApicPage->timer_icr.u32InitialCount;
1331 if (!uInitialCount)
1332 return VINF_SUCCESS;
1333
1334 /*
1335 * Reading the virtual-sync clock requires locking its timer because it's not
1336 * a simple atomic operation, see tmVirtualSyncGetEx().
1337 *
1338 * We also need to lock before reading the timer CCR, see apicR3TimerCallback().
1339 */
1340 PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1341 PTMTIMER pTimer = pApicCpu->CTX_SUFF(pTimer);
1342
1343 int rc = TMTimerLock(pTimer, rcBusy);
1344 if (rc == VINF_SUCCESS)
1345 {
1346 /* If the current-count register is 0, it implies the timer expired. */
1347 uint32_t const uCurrentCount = pXApicPage->timer_ccr.u32CurrentCount;
1348 if (uCurrentCount)
1349 {
1350 uint64_t const cTicksElapsed = TMTimerGet(pApicCpu->CTX_SUFF(pTimer)) - pApicCpu->u64TimerInitial;
1351 TMTimerUnlock(pTimer);
1352 uint8_t const uTimerShift = apicGetTimerShift(pXApicPage);
1353 uint64_t const uDelta = cTicksElapsed >> uTimerShift;
1354 if (uInitialCount > uDelta)
1355 *puValue = uInitialCount - uDelta;
1356 }
1357 else
1358 TMTimerUnlock(pTimer);
1359 }
1360 return rc;
1361}
1362
1363
1364/**
1365 * Sets the timer's Initial-Count Register (ICR).
1366 *
1367 * @returns Strict VBox status code.
1368 * @param pVCpu The cross context virtual CPU structure.
1369 * @param rcBusy The busy return code for the timer critical section.
1370 * @param uInitialCount The timer ICR.
1371 */
1372static VBOXSTRICTRC apicSetTimerIcr(PVMCPU pVCpu, int rcBusy, uint32_t uInitialCount)
1373{
1374 VMCPU_ASSERT_EMT(pVCpu);
1375
1376 PAPIC pApic = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
1377 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1378 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1379 PTMTIMER pTimer = pApicCpu->CTX_SUFF(pTimer);
1380
1381 Log2(("APIC%u: apicSetTimerIcr: uInitialCount=%#RX32\n", pVCpu->idCpu, uInitialCount));
1382 STAM_COUNTER_INC(&pApicCpu->StatTimerIcrWrite);
1383
1384 /* In TSC-deadline mode, timer ICR writes are ignored, see Intel spec. 10.5.4.1 "TSC-Deadline Mode". */
1385 if ( pApic->fSupportsTscDeadline
1386 && pXApicPage->lvt_timer.u.u2TimerMode == XAPIC_TIMER_MODE_TSC_DEADLINE)
1387 return VINF_SUCCESS;
1388
1389 /*
1390 * The timer CCR may be modified by apicR3TimerCallback() in parallel,
1391 * so obtain the lock -before- updating it here to be consistent with the
1392 * timer ICR. We rely on CCR being consistent in apicGetTimerCcr().
1393 */
1394 int rc = TMTimerLock(pTimer, rcBusy);
1395 if (rc == VINF_SUCCESS)
1396 {
1397 pXApicPage->timer_icr.u32InitialCount = uInitialCount;
1398 pXApicPage->timer_ccr.u32CurrentCount = uInitialCount;
1399 if (uInitialCount)
1400 APICStartTimer(pVCpu, uInitialCount);
1401 else
1402 APICStopTimer(pVCpu);
1403 TMTimerUnlock(pTimer);
1404 }
1405 return rc;
1406}
1407
1408
1409/**
1410 * Sets an LVT entry.
1411 *
1412 * @returns Strict VBox status code.
1413 * @param pVCpu The cross context virtual CPU structure.
1414 * @param offLvt The LVT entry offset in the xAPIC page.
1415 * @param uLvt The LVT value to set.
1416 */
1417static VBOXSTRICTRC apicSetLvtEntry(PVMCPU pVCpu, uint16_t offLvt, uint32_t uLvt)
1418{
1419 VMCPU_ASSERT_EMT(pVCpu);
1420
1421#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
1422 AssertMsg( offLvt == XAPIC_OFF_LVT_TIMER
1423 || offLvt == XAPIC_OFF_LVT_THERMAL
1424 || offLvt == XAPIC_OFF_LVT_PERF
1425 || offLvt == XAPIC_OFF_LVT_LINT0
1426 || offLvt == XAPIC_OFF_LVT_LINT1
1427 || offLvt == XAPIC_OFF_LVT_ERROR,
1428 ("APIC%u: apicSetLvtEntry: invalid offset, offLvt=%#RX16, uLvt=%#RX32\n", pVCpu->idCpu, offLvt, uLvt));
1429
1430 /*
1431 * If TSC-deadline mode isn't support, ignore the bit in xAPIC mode
1432 * and raise #GP(0) in x2APIC mode.
1433 */
1434 PCAPIC pApic = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
1435 if (offLvt == XAPIC_OFF_LVT_TIMER)
1436 {
1437 if ( !pApic->fSupportsTscDeadline
1438 && (uLvt & XAPIC_LVT_TIMER_TSCDEADLINE))
1439 {
1440 if (XAPIC_IN_X2APIC_MODE(pVCpu))
1441 return apicMsrAccessError(pVCpu, XAPIC_GET_X2APIC_MSR(offLvt), APICMSRACCESS_WRITE_RSVD_BITS);
1442 uLvt &= ~XAPIC_LVT_TIMER_TSCDEADLINE;
1443 /** @todo TSC-deadline timer mode transition */
1444 }
1445 }
1446
1447 /*
1448 * Validate rest of the LVT bits.
1449 */
1450 uint16_t const idxLvt = (offLvt - XAPIC_OFF_LVT_START) >> 4;
1451 AssertReturn(idxLvt < RT_ELEMENTS(g_au32LvtValidMasks), VERR_OUT_OF_RANGE);
1452
1453 /*
1454 * For x2APIC, disallow setting of invalid/reserved bits.
1455 * For xAPIC, mask out invalid/reserved bits (i.e. ignore them).
1456 */
1457 if ( XAPIC_IN_X2APIC_MODE(pVCpu)
1458 && (uLvt & ~g_au32LvtValidMasks[idxLvt]))
1459 return apicMsrAccessError(pVCpu, XAPIC_GET_X2APIC_MSR(offLvt), APICMSRACCESS_WRITE_RSVD_BITS);
1460
1461 uLvt &= g_au32LvtValidMasks[idxLvt];
1462
1463 /*
1464 * In the software-disabled state, LVT mask-bit must remain set and attempts to clear the mask
1465 * bit must be ignored. See Intel spec. 10.4.7.2 "Local APIC State After It Has Been Software Disabled".
1466 */
1467 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1468 if (!pXApicPage->svr.u.fApicSoftwareEnable)
1469 uLvt |= XAPIC_LVT_MASK;
1470
1471 /*
1472 * It is unclear whether we should signal a 'send illegal vector' error here and ignore updating
1473 * the LVT entry when the delivery mode is 'fixed'[1] or update it in addition to signaling the
1474 * error or not signal the error at all. For now, we'll allow setting illegal vectors into the LVT
1475 * but set the 'send illegal vector' error here. The 'receive illegal vector' error will be set if
1476 * the interrupt for the vector happens to be generated, see APICPostInterrupt().
1477 *
1478 * [1] See Intel spec. 10.5.2 "Valid Interrupt Vectors".
1479 */
1480 if (RT_UNLIKELY( XAPIC_LVT_GET_VECTOR(uLvt) <= XAPIC_ILLEGAL_VECTOR_END
1481 && XAPIC_LVT_GET_DELIVERY_MODE(uLvt) == XAPICDELIVERYMODE_FIXED))
1482 apicSetError(pVCpu, XAPIC_ESR_SEND_ILLEGAL_VECTOR);
1483
1484 Log2(("APIC%u: apicSetLvtEntry: offLvt=%#RX16 uLvt=%#RX32\n", pVCpu->idCpu, offLvt, uLvt));
1485
1486 apicWriteRaw32(pXApicPage, offLvt, uLvt);
1487 return VINF_SUCCESS;
1488#else
1489# error "Implement Pentium and P6 family APIC architectures"
1490#endif /* XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4 */
1491}
1492
1493
1494#if 0
1495/**
1496 * Sets an LVT entry in the extended LVT range.
1497 *
1498 * @returns VBox status code.
1499 * @param pVCpu The cross context virtual CPU structure.
1500 * @param offLvt The LVT entry offset in the xAPIC page.
1501 * @param uValue The LVT value to set.
1502 */
1503static int apicSetLvtExtEntry(PVMCPU pVCpu, uint16_t offLvt, uint32_t uLvt)
1504{
1505 VMCPU_ASSERT_EMT(pVCpu);
1506 AssertMsg(offLvt == XAPIC_OFF_CMCI, ("APIC%u: apicSetLvt1Entry: invalid offset %#RX16\n", pVCpu->idCpu, offLvt));
1507
1508 /** @todo support CMCI. */
1509 return VERR_NOT_IMPLEMENTED;
1510}
1511#endif
1512
1513
1514/**
1515 * Hints TM about the APIC timer frequency.
1516 *
1517 * @param pApicCpu The APIC CPU state.
1518 * @param uInitialCount The new initial count.
1519 * @param uTimerShift The new timer shift.
1520 * @thread Any.
1521 */
1522void apicHintTimerFreq(PAPICCPU pApicCpu, uint32_t uInitialCount, uint8_t uTimerShift)
1523{
1524 Assert(pApicCpu);
1525
1526 if ( pApicCpu->uHintedTimerInitialCount != uInitialCount
1527 || pApicCpu->uHintedTimerShift != uTimerShift)
1528 {
1529 uint32_t uHz;
1530 if (uInitialCount)
1531 {
1532 uint64_t cTicksPerPeriod = (uint64_t)uInitialCount << uTimerShift;
1533 uHz = TMTimerGetFreq(pApicCpu->CTX_SUFF(pTimer)) / cTicksPerPeriod;
1534 }
1535 else
1536 uHz = 0;
1537
1538 TMTimerSetFrequencyHint(pApicCpu->CTX_SUFF(pTimer), uHz);
1539 pApicCpu->uHintedTimerInitialCount = uInitialCount;
1540 pApicCpu->uHintedTimerShift = uTimerShift;
1541 }
1542}
1543
1544
1545/**
1546 * Reads an APIC register.
1547 *
1548 * @returns VBox status code.
1549 * @param pApicDev The APIC device instance.
1550 * @param pVCpu The cross context virtual CPU structure.
1551 * @param offReg The offset of the register being read.
1552 * @param puValue Where to store the register value.
1553 */
1554static int apicReadRegister(PAPICDEV pApicDev, PVMCPU pVCpu, uint16_t offReg, uint32_t *puValue)
1555{
1556 VMCPU_ASSERT_EMT(pVCpu);
1557 Assert(offReg <= XAPIC_OFF_MAX_VALID);
1558
1559 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1560 uint32_t uValue = 0;
1561 int rc = VINF_SUCCESS;
1562 switch (offReg)
1563 {
1564 case XAPIC_OFF_ID:
1565 case XAPIC_OFF_VERSION:
1566 case XAPIC_OFF_TPR:
1567 case XAPIC_OFF_EOI:
1568 case XAPIC_OFF_RRD:
1569 case XAPIC_OFF_LDR:
1570 case XAPIC_OFF_DFR:
1571 case XAPIC_OFF_SVR:
1572 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
1573 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
1574 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
1575 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
1576 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
1577 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
1578 case XAPIC_OFF_ESR:
1579 case XAPIC_OFF_ICR_LO:
1580 case XAPIC_OFF_ICR_HI:
1581 case XAPIC_OFF_LVT_TIMER:
1582#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
1583 case XAPIC_OFF_LVT_THERMAL:
1584#endif
1585 case XAPIC_OFF_LVT_PERF:
1586 case XAPIC_OFF_LVT_LINT0:
1587 case XAPIC_OFF_LVT_LINT1:
1588 case XAPIC_OFF_LVT_ERROR:
1589 case XAPIC_OFF_TIMER_ICR:
1590 case XAPIC_OFF_TIMER_DCR:
1591 {
1592 Assert( !XAPIC_IN_X2APIC_MODE(pVCpu)
1593 || ( offReg != XAPIC_OFF_DFR
1594 && offReg != XAPIC_OFF_ICR_HI
1595 && offReg != XAPIC_OFF_EOI));
1596 uValue = apicReadRaw32(pXApicPage, offReg);
1597 Log2(("APIC%u: apicReadRegister: offReg=%#x uValue=%#x\n", pVCpu->idCpu, offReg, uValue));
1598 break;
1599 }
1600
1601 case XAPIC_OFF_PPR:
1602 {
1603 uValue = apicGetPpr(pVCpu);
1604 break;
1605 }
1606
1607 case XAPIC_OFF_TIMER_CCR:
1608 {
1609 Assert(!XAPIC_IN_X2APIC_MODE(pVCpu));
1610 rc = VBOXSTRICTRC_VAL(apicGetTimerCcr(pVCpu, VINF_IOM_R3_MMIO_READ, &uValue));
1611 break;
1612 }
1613
1614 case XAPIC_OFF_APR:
1615 {
1616#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
1617 /* Unsupported on Pentium 4 and Xeon CPUs, invalid in x2APIC mode. */
1618 Assert(!XAPIC_IN_X2APIC_MODE(pVCpu));
1619#else
1620# error "Implement Pentium and P6 family APIC architectures"
1621#endif
1622 break;
1623 }
1624
1625 default:
1626 {
1627 Assert(!XAPIC_IN_X2APIC_MODE(pVCpu));
1628 rc = PDMDevHlpDBGFStop(pApicDev->CTX_SUFF(pDevIns), RT_SRC_POS, "VCPU[%u]: offReg=%#RX16\n", pVCpu->idCpu, offReg);
1629 apicSetError(pVCpu, XAPIC_ESR_ILLEGAL_REG_ADDRESS);
1630 break;
1631 }
1632 }
1633
1634 *puValue = uValue;
1635 return rc;
1636}
1637
1638
1639/**
1640 * Writes an APIC register.
1641 *
1642 * @returns Strict VBox status code.
1643 * @param pApicDev The APIC device instance.
1644 * @param pVCpu The cross context virtual CPU structure.
1645 * @param offReg The offset of the register being written.
1646 * @param uValue The register value.
1647 */
1648static VBOXSTRICTRC apicWriteRegister(PAPICDEV pApicDev, PVMCPU pVCpu, uint16_t offReg, uint32_t uValue)
1649{
1650 VMCPU_ASSERT_EMT(pVCpu);
1651 Assert(offReg <= XAPIC_OFF_MAX_VALID);
1652 Assert(!XAPIC_IN_X2APIC_MODE(pVCpu));
1653
1654 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1655 switch (offReg)
1656 {
1657 case XAPIC_OFF_TPR:
1658 {
1659 rcStrict = apicSetTpr(pVCpu, uValue);
1660 break;
1661 }
1662
1663 case XAPIC_OFF_LVT_TIMER:
1664#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
1665 case XAPIC_OFF_LVT_THERMAL:
1666#endif
1667 case XAPIC_OFF_LVT_PERF:
1668 case XAPIC_OFF_LVT_LINT0:
1669 case XAPIC_OFF_LVT_LINT1:
1670 case XAPIC_OFF_LVT_ERROR:
1671 {
1672 rcStrict = apicSetLvtEntry(pVCpu, offReg, uValue);
1673 break;
1674 }
1675
1676 case XAPIC_OFF_TIMER_ICR:
1677 {
1678 rcStrict = apicSetTimerIcr(pVCpu, VINF_IOM_R3_MMIO_WRITE, uValue);
1679 break;
1680 }
1681
1682 case XAPIC_OFF_EOI:
1683 {
1684 rcStrict = apicSetEoi(pVCpu, uValue);
1685 break;
1686 }
1687
1688 case XAPIC_OFF_LDR:
1689 {
1690 rcStrict = apicSetLdr(pVCpu, uValue);
1691 break;
1692 }
1693
1694 case XAPIC_OFF_DFR:
1695 {
1696 rcStrict = apicSetDfr(pVCpu, uValue);
1697 break;
1698 }
1699
1700 case XAPIC_OFF_SVR:
1701 {
1702 rcStrict = apicSetSvr(pVCpu, uValue);
1703 break;
1704 }
1705
1706 case XAPIC_OFF_ICR_LO:
1707 {
1708 rcStrict = apicSetIcrLo(pVCpu, uValue, VINF_IOM_R3_MMIO_WRITE);
1709 break;
1710 }
1711
1712 case XAPIC_OFF_ICR_HI:
1713 {
1714 rcStrict = apicSetIcrHi(pVCpu, uValue);
1715 break;
1716 }
1717
1718 case XAPIC_OFF_TIMER_DCR:
1719 {
1720 rcStrict = apicSetTimerDcr(pVCpu, uValue);
1721 break;
1722 }
1723
1724 case XAPIC_OFF_ESR:
1725 {
1726 rcStrict = apicSetEsr(pVCpu, uValue);
1727 break;
1728 }
1729
1730 case XAPIC_OFF_APR:
1731 case XAPIC_OFF_RRD:
1732 {
1733#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
1734 /* Unsupported on Pentium 4 and Xeon CPUs but writes do -not- set an illegal register access error. */
1735#else
1736# error "Implement Pentium and P6 family APIC architectures"
1737#endif
1738 break;
1739 }
1740
1741 /* Read-only, write ignored: */
1742 case XAPIC_OFF_VERSION:
1743 case XAPIC_OFF_ID:
1744 break;
1745
1746 /* Unavailable/reserved in xAPIC mode: */
1747 case X2APIC_OFF_SELF_IPI:
1748 /* Read-only registers: */
1749 case XAPIC_OFF_PPR:
1750 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
1751 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
1752 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
1753 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
1754 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
1755 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
1756 case XAPIC_OFF_TIMER_CCR:
1757 default:
1758 {
1759 rcStrict = PDMDevHlpDBGFStop(pApicDev->CTX_SUFF(pDevIns), RT_SRC_POS, "APIC%u: offReg=%#RX16\n", pVCpu->idCpu,
1760 offReg);
1761 apicSetError(pVCpu, XAPIC_ESR_ILLEGAL_REG_ADDRESS);
1762 break;
1763 }
1764 }
1765
1766 return rcStrict;
1767}
1768
1769
1770/**
1771 * @interface_method_impl{PDMAPICREG,pfnReadMsrR3}
1772 */
1773VMMDECL(VBOXSTRICTRC) APICReadMsr(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint32_t u32Reg, uint64_t *pu64Value)
1774{
1775 /*
1776 * Validate.
1777 */
1778 VMCPU_ASSERT_EMT(pVCpu);
1779 Assert(u32Reg >= MSR_IA32_X2APIC_ID && u32Reg <= MSR_IA32_X2APIC_SELF_IPI);
1780 Assert(pu64Value);
1781
1782#ifndef IN_RING3
1783 PCAPIC pApic = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
1784 if (pApic->fRZEnabled)
1785 { /* likely */}
1786 else
1787 {
1788 return VINF_CPUM_R3_MSR_READ;
1789 }
1790#endif
1791
1792 STAM_COUNTER_INC(&pVCpu->apic.s.CTX_SUFF(StatMsrRead));
1793
1794 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1795 if (RT_LIKELY(XAPIC_IN_X2APIC_MODE(pVCpu)))
1796 {
1797 switch (u32Reg)
1798 {
1799 /* Special handling for x2APIC: */
1800 case MSR_IA32_X2APIC_ICR:
1801 {
1802 PCX2APICPAGE pX2ApicPage = VMCPU_TO_CX2APICPAGE(pVCpu);
1803 uint64_t const uHi = pX2ApicPage->icr_hi.u32IcrHi;
1804 uint64_t const uLo = pX2ApicPage->icr_lo.all.u32IcrLo;
1805 *pu64Value = RT_MAKE_U64(uLo, uHi);
1806 break;
1807 }
1808
1809 /* Special handling, compatible with xAPIC: */
1810 case MSR_IA32_X2APIC_TIMER_CCR:
1811 {
1812 uint32_t uValue;
1813 rcStrict = apicGetTimerCcr(pVCpu, VINF_CPUM_R3_MSR_READ, &uValue);
1814 *pu64Value = uValue;
1815 break;
1816 }
1817
1818 /* Special handling, compatible with xAPIC: */
1819 case MSR_IA32_X2APIC_PPR:
1820 {
1821 *pu64Value = apicGetPpr(pVCpu);
1822 break;
1823 }
1824
1825 /* Raw read, compatible with xAPIC: */
1826 case MSR_IA32_X2APIC_ID:
1827 case MSR_IA32_X2APIC_VERSION:
1828 case MSR_IA32_X2APIC_TPR:
1829 case MSR_IA32_X2APIC_LDR:
1830 case MSR_IA32_X2APIC_SVR:
1831 case MSR_IA32_X2APIC_ISR0: case MSR_IA32_X2APIC_ISR1: case MSR_IA32_X2APIC_ISR2: case MSR_IA32_X2APIC_ISR3:
1832 case MSR_IA32_X2APIC_ISR4: case MSR_IA32_X2APIC_ISR5: case MSR_IA32_X2APIC_ISR6: case MSR_IA32_X2APIC_ISR7:
1833 case MSR_IA32_X2APIC_TMR0: case MSR_IA32_X2APIC_TMR1: case MSR_IA32_X2APIC_TMR2: case MSR_IA32_X2APIC_TMR3:
1834 case MSR_IA32_X2APIC_TMR4: case MSR_IA32_X2APIC_TMR5: case MSR_IA32_X2APIC_TMR6: case MSR_IA32_X2APIC_TMR7:
1835 case MSR_IA32_X2APIC_IRR0: case MSR_IA32_X2APIC_IRR1: case MSR_IA32_X2APIC_IRR2: case MSR_IA32_X2APIC_IRR3:
1836 case MSR_IA32_X2APIC_IRR4: case MSR_IA32_X2APIC_IRR5: case MSR_IA32_X2APIC_IRR6: case MSR_IA32_X2APIC_IRR7:
1837 case MSR_IA32_X2APIC_ESR:
1838 case MSR_IA32_X2APIC_LVT_TIMER:
1839 case MSR_IA32_X2APIC_LVT_THERMAL:
1840 case MSR_IA32_X2APIC_LVT_PERF:
1841 case MSR_IA32_X2APIC_LVT_LINT0:
1842 case MSR_IA32_X2APIC_LVT_LINT1:
1843 case MSR_IA32_X2APIC_LVT_ERROR:
1844 case MSR_IA32_X2APIC_TIMER_ICR:
1845 case MSR_IA32_X2APIC_TIMER_DCR:
1846 {
1847 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1848 uint16_t const offReg = X2APIC_GET_XAPIC_OFF(u32Reg);
1849 *pu64Value = apicReadRaw32(pXApicPage, offReg);
1850 break;
1851 }
1852
1853 /* Write-only MSRs: */
1854 case MSR_IA32_X2APIC_SELF_IPI:
1855 case MSR_IA32_X2APIC_EOI:
1856 {
1857 rcStrict = apicMsrAccessError(pVCpu, u32Reg, APICMSRACCESS_READ_WRITE_ONLY);
1858 break;
1859 }
1860
1861 /* Reserved MSRs: */
1862 case MSR_IA32_X2APIC_LVT_CMCI:
1863 default:
1864 {
1865 rcStrict = apicMsrAccessError(pVCpu, u32Reg, APICMSRACCESS_READ_RSVD_OR_UNKNOWN);
1866 break;
1867 }
1868 }
1869 }
1870 else
1871 rcStrict = apicMsrAccessError(pVCpu, u32Reg, APICMSRACCESS_INVALID_READ_MODE);
1872
1873 return rcStrict;
1874}
1875
1876
1877/**
1878 * @interface_method_impl{PDMAPICREG,pfnWriteMsrR3}
1879 */
1880VMMDECL(VBOXSTRICTRC) APICWriteMsr(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint32_t u32Reg, uint64_t u64Value)
1881{
1882 /*
1883 * Validate.
1884 */
1885 VMCPU_ASSERT_EMT(pVCpu);
1886 Assert(u32Reg >= MSR_IA32_X2APIC_ID && u32Reg <= MSR_IA32_X2APIC_SELF_IPI);
1887
1888#ifndef IN_RING3
1889 PCAPIC pApic = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
1890 if (pApic->fRZEnabled)
1891 { /* likely */ }
1892 else
1893 {
1894 return VINF_CPUM_R3_MSR_WRITE;
1895 }
1896#endif
1897
1898 STAM_COUNTER_INC(&pVCpu->apic.s.CTX_SUFF(StatMsrWrite));
1899
1900 /*
1901 * In x2APIC mode, we need to raise #GP(0) for writes to reserved bits, unlike MMIO
1902 * accesses where they are ignored. Hence, we need to validate each register before
1903 * invoking the generic/xAPIC write functions.
1904 *
1905 * Bits 63:32 of all registers except the ICR are reserved, we'll handle this common
1906 * case first and handle validating the remaining bits on a per-register basis.
1907 * See Intel spec. 10.12.1.2 "x2APIC Register Address Space".
1908 */
1909 if ( u32Reg != MSR_IA32_X2APIC_ICR
1910 && RT_HI_U32(u64Value))
1911 return apicMsrAccessError(pVCpu, u32Reg, APICMSRACCESS_WRITE_RSVD_BITS);
1912
1913 uint32_t u32Value = RT_LO_U32(u64Value);
1914 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1915 if (RT_LIKELY(XAPIC_IN_X2APIC_MODE(pVCpu)))
1916 {
1917 switch (u32Reg)
1918 {
1919 case MSR_IA32_X2APIC_TPR:
1920 {
1921 rcStrict = apicSetTpr(pVCpu, u32Value);
1922 break;
1923 }
1924
1925 case MSR_IA32_X2APIC_ICR:
1926 {
1927 rcStrict = apicSetIcr(pVCpu, u64Value, VINF_CPUM_R3_MSR_WRITE);
1928 break;
1929 }
1930
1931 case MSR_IA32_X2APIC_SVR:
1932 {
1933 rcStrict = apicSetSvr(pVCpu, u32Value);
1934 break;
1935 }
1936
1937 case MSR_IA32_X2APIC_ESR:
1938 {
1939 rcStrict = apicSetEsr(pVCpu, u32Value);
1940 break;
1941 }
1942
1943 case MSR_IA32_X2APIC_TIMER_DCR:
1944 {
1945 rcStrict = apicSetTimerDcr(pVCpu, u32Value);
1946 break;
1947 }
1948
1949 case MSR_IA32_X2APIC_LVT_TIMER:
1950 case MSR_IA32_X2APIC_LVT_THERMAL:
1951 case MSR_IA32_X2APIC_LVT_PERF:
1952 case MSR_IA32_X2APIC_LVT_LINT0:
1953 case MSR_IA32_X2APIC_LVT_LINT1:
1954 case MSR_IA32_X2APIC_LVT_ERROR:
1955 {
1956 rcStrict = apicSetLvtEntry(pVCpu, X2APIC_GET_XAPIC_OFF(u32Reg), u32Value);
1957 break;
1958 }
1959
1960 case MSR_IA32_X2APIC_TIMER_ICR:
1961 {
1962 rcStrict = apicSetTimerIcr(pVCpu, VINF_CPUM_R3_MSR_WRITE, u32Value);
1963 break;
1964 }
1965
1966 /* Write-only MSRs: */
1967 case MSR_IA32_X2APIC_SELF_IPI:
1968 {
1969 uint8_t const uVector = XAPIC_SELF_IPI_GET_VECTOR(u32Value);
1970 APICPostInterrupt(pVCpu, uVector, XAPICTRIGGERMODE_EDGE);
1971 rcStrict = VINF_SUCCESS;
1972 break;
1973 }
1974
1975 case MSR_IA32_X2APIC_EOI:
1976 {
1977 rcStrict = apicSetEoi(pVCpu, u32Value);
1978 break;
1979 }
1980
1981 /* Read-only MSRs: */
1982 case MSR_IA32_X2APIC_ID:
1983 case MSR_IA32_X2APIC_VERSION:
1984 case MSR_IA32_X2APIC_PPR:
1985 case MSR_IA32_X2APIC_LDR:
1986 case MSR_IA32_X2APIC_ISR0: case MSR_IA32_X2APIC_ISR1: case MSR_IA32_X2APIC_ISR2: case MSR_IA32_X2APIC_ISR3:
1987 case MSR_IA32_X2APIC_ISR4: case MSR_IA32_X2APIC_ISR5: case MSR_IA32_X2APIC_ISR6: case MSR_IA32_X2APIC_ISR7:
1988 case MSR_IA32_X2APIC_TMR0: case MSR_IA32_X2APIC_TMR1: case MSR_IA32_X2APIC_TMR2: case MSR_IA32_X2APIC_TMR3:
1989 case MSR_IA32_X2APIC_TMR4: case MSR_IA32_X2APIC_TMR5: case MSR_IA32_X2APIC_TMR6: case MSR_IA32_X2APIC_TMR7:
1990 case MSR_IA32_X2APIC_IRR0: case MSR_IA32_X2APIC_IRR1: case MSR_IA32_X2APIC_IRR2: case MSR_IA32_X2APIC_IRR3:
1991 case MSR_IA32_X2APIC_IRR4: case MSR_IA32_X2APIC_IRR5: case MSR_IA32_X2APIC_IRR6: case MSR_IA32_X2APIC_IRR7:
1992 case MSR_IA32_X2APIC_TIMER_CCR:
1993 {
1994 rcStrict = apicMsrAccessError(pVCpu, u32Reg, APICMSRACCESS_WRITE_READ_ONLY);
1995 break;
1996 }
1997
1998 /* Reserved MSRs: */
1999 case MSR_IA32_X2APIC_LVT_CMCI:
2000 default:
2001 {
2002 rcStrict = apicMsrAccessError(pVCpu, u32Reg, APICMSRACCESS_WRITE_RSVD_OR_UNKNOWN);
2003 break;
2004 }
2005 }
2006 }
2007 else
2008 rcStrict = apicMsrAccessError(pVCpu, u32Reg, APICMSRACCESS_INVALID_WRITE_MODE);
2009
2010 return rcStrict;
2011}
2012
2013
2014/**
2015 * @interface_method_impl{PDMAPICREG,pfnSetBaseMsrR3}
2016 */
2017VMMDECL(VBOXSTRICTRC) APICSetBaseMsr(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint64_t u64BaseMsr)
2018{
2019 Assert(pVCpu);
2020 NOREF(pDevIns);
2021
2022#ifdef IN_RING3
2023 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
2024 PAPIC pApic = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
2025 APICMODE enmOldMode = apicGetMode(pApicCpu->uApicBaseMsr);
2026 APICMODE enmNewMode = apicGetMode(u64BaseMsr);
2027 uint64_t uBaseMsr = pApicCpu->uApicBaseMsr;
2028
2029 Log2(("APIC%u: ApicSetBaseMsr: u64BaseMsr=%#RX64 enmNewMode=%s enmOldMode=%s\n", pVCpu->idCpu, u64BaseMsr,
2030 apicGetModeName(enmNewMode), apicGetModeName(enmOldMode)));
2031
2032 /*
2033 * We do not support re-mapping the APIC base address because:
2034 * - We'll have to manage all the mappings ourselves in the APIC (reference counting based unmapping etc.)
2035 * i.e. we can only unmap the MMIO region if no other APIC is mapped on that location.
2036 * - It's unclear how/if IOM can fallback to handling regions as regular memory (if the MMIO
2037 * region remains mapped but doesn't belong to the called VCPU's APIC).
2038 */
2039 /** @todo Handle per-VCPU APIC base relocation. */
2040 if (MSR_IA32_APICBASE_GET_ADDR(uBaseMsr) != MSR_IA32_APICBASE_ADDR)
2041 {
2042 LogRelMax(5, ("APIC%u: Attempt to relocate base to %#RGp, unsupported -> #GP(0)\n", pVCpu->idCpu,
2043 MSR_IA32_APICBASE_GET_ADDR(uBaseMsr)));
2044 return VERR_CPUM_RAISE_GP_0;
2045 }
2046
2047 /* Don't allow enabling xAPIC/x2APIC if the VM is configured with the APIC disabled. */
2048 if (pApic->enmOriginalMode == APICMODE_DISABLED)
2049 {
2050 LogRel(("APIC%u: Disallowing APIC base MSR write as the VM is configured with APIC disabled!\n",
2051 pVCpu->idCpu));
2052 return apicMsrAccessError(pVCpu, MSR_IA32_APICBASE, APICMSRACCESS_WRITE_DISALLOWED_CONFIG);
2053 }
2054
2055 /*
2056 * Act on state transition.
2057 */
2058 /** @todo We need to update the CPUID according to the state, which we
2059 * currently don't do as CPUMSetGuestCpuIdFeature() is setting
2060 * per-VM CPUID bits while we need per-VCPU specific bits. */
2061 if (enmNewMode != enmOldMode)
2062 {
2063 switch (enmNewMode)
2064 {
2065 case APICMODE_DISABLED:
2066 {
2067 /*
2068 * The APIC state needs to be reset (especially the APIC ID as x2APIC APIC ID bit layout
2069 * is different). We can start with a clean slate identical to the state after a power-up/reset.
2070 *
2071 * See Intel spec. 10.4.3 "Enabling or Disabling the Local APIC".
2072 *
2073 * We'll also manually manage the APIC base MSR here. We want a single-point of commit
2074 * at the end of this function rather than touching it in APICR3Reset. This means we also
2075 * need to update the CPUID leaf ourselves.
2076 */
2077 APICR3Reset(pVCpu, false /* fResetApicBaseMsr */);
2078 uBaseMsr &= ~(MSR_IA32_APICBASE_EN | MSR_IA32_APICBASE_EXTD);
2079 CPUMClearGuestCpuIdFeature(pVCpu->CTX_SUFF(pVM), CPUMCPUIDFEATURE_APIC);
2080 LogRel(("APIC%u: Switched mode to disabled\n", pVCpu->idCpu));
2081 break;
2082 }
2083
2084 case APICMODE_XAPIC:
2085 {
2086 if (enmOldMode != APICMODE_DISABLED)
2087 {
2088 LogRel(("APIC%u: Can only transition to xAPIC state from disabled state\n", pVCpu->idCpu));
2089 return apicMsrAccessError(pVCpu, MSR_IA32_APICBASE, APICMSRACCESS_WRITE_INVALID);
2090 }
2091
2092 uBaseMsr |= MSR_IA32_APICBASE_EN;
2093 CPUMSetGuestCpuIdFeature(pVCpu->CTX_SUFF(pVM), CPUMCPUIDFEATURE_APIC);
2094 LogRel(("APIC%u: Switched mode to xAPIC\n", pVCpu->idCpu));
2095 break;
2096 }
2097
2098 case APICMODE_X2APIC:
2099 {
2100 if (pApic->enmOriginalMode != APICMODE_X2APIC)
2101 {
2102 LogRel(("APIC%u: Disallowing transition to x2APIC mode as the VM is configured with the x2APIC disabled!\n",
2103 pVCpu->idCpu));
2104 return apicMsrAccessError(pVCpu, MSR_IA32_APICBASE, APICMSRACCESS_WRITE_INVALID);
2105 }
2106
2107 if (enmOldMode != APICMODE_XAPIC)
2108 {
2109 LogRel(("APIC%u: Can only transition to x2APIC state from xAPIC state\n", pVCpu->idCpu));
2110 return apicMsrAccessError(pVCpu, MSR_IA32_APICBASE, APICMSRACCESS_WRITE_INVALID);
2111 }
2112
2113 uBaseMsr |= MSR_IA32_APICBASE_EN | MSR_IA32_APICBASE_EXTD;
2114
2115 /*
2116 * The APIC ID needs updating when entering x2APIC mode.
2117 * Software written APIC ID in xAPIC mode isn't preserved.
2118 * The APIC ID becomes read-only to software in x2APIC mode.
2119 *
2120 * See Intel spec. 10.12.5.1 "x2APIC States".
2121 */
2122 PX2APICPAGE pX2ApicPage = VMCPU_TO_X2APICPAGE(pVCpu);
2123 ASMMemZero32(&pX2ApicPage->id, sizeof(pX2ApicPage->id));
2124 pX2ApicPage->id.u32ApicId = pVCpu->idCpu;
2125
2126 /*
2127 * LDR initialization occurs when entering x2APIC mode.
2128 * See Intel spec. 10.12.10.2 "Deriving Logical x2APIC ID from the Local x2APIC ID".
2129 */
2130 pX2ApicPage->ldr.u32LogicalApicId = ((pX2ApicPage->id.u32ApicId & UINT32_C(0xffff0)) << 16)
2131 | (UINT32_C(1) << pX2ApicPage->id.u32ApicId & UINT32_C(0xf));
2132
2133 LogRel(("APIC%u: Switched mode to x2APIC\n", pVCpu->idCpu));
2134 break;
2135 }
2136
2137 case APICMODE_INVALID:
2138 default:
2139 {
2140 Log(("APIC%u: Invalid state transition attempted\n", pVCpu->idCpu));
2141 return apicMsrAccessError(pVCpu, MSR_IA32_APICBASE, APICMSRACCESS_WRITE_INVALID);
2142 }
2143 }
2144 }
2145
2146 ASMAtomicWriteU64(&pApicCpu->uApicBaseMsr, uBaseMsr);
2147 return VINF_SUCCESS;
2148#else /* !IN_RING3 */
2149 return VINF_CPUM_R3_MSR_WRITE;
2150#endif /* IN_RING3 */
2151}
2152
2153
2154/**
2155 * @interface_method_impl{PDMAPICREG,pfnGetBaseMsrR3}
2156 */
2157VMMDECL(uint64_t) APICGetBaseMsr(PPDMDEVINS pDevIns, PVMCPU pVCpu)
2158{
2159 VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
2160
2161 PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
2162 return pApicCpu->uApicBaseMsr;
2163}
2164
2165
2166/**
2167 * @interface_method_impl{PDMAPICREG,pfnSetTprR3}
2168 */
2169VMMDECL(void) APICSetTpr(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint8_t u8Tpr)
2170{
2171 apicSetTpr(pVCpu, u8Tpr);
2172}
2173
2174
2175/**
2176 * Gets the highest priority pending interrupt.
2177 *
2178 * @returns true if any interrupt is pending, false otherwise.
2179 * @param pVCpu The cross context virtual CPU structure.
2180 * @param pu8PendingIntr Where to store the interrupt vector if the
2181 * interrupt is pending (optional, can be NULL).
2182 */
2183static bool apicGetHighestPendingInterrupt(PVMCPU pVCpu, uint8_t *pu8PendingIntr)
2184{
2185 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
2186 int const irrv = apicGetHighestSetBitInReg(&pXApicPage->irr, -1);
2187 if (irrv >= 0)
2188 {
2189 Assert(irrv <= (int)UINT8_MAX);
2190 if (pu8PendingIntr)
2191 *pu8PendingIntr = (uint8_t)irrv;
2192 return true;
2193 }
2194 return false;
2195}
2196
2197
2198/**
2199 * @interface_method_impl{PDMAPICREG,pfnGetTprR3}
2200 */
2201VMMDECL(uint8_t) APICGetTpr(PPDMDEVINS pDevIns, PVMCPU pVCpu, bool *pfPending, uint8_t *pu8PendingIntr)
2202{
2203 VMCPU_ASSERT_EMT(pVCpu);
2204 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
2205
2206 if (pfPending)
2207 {
2208 /*
2209 * Just return whatever the highest pending interrupt is in the IRR.
2210 * The caller is responsible for figuring out if it's masked by the TPR etc.
2211 */
2212 *pfPending = apicGetHighestPendingInterrupt(pVCpu, pu8PendingIntr);
2213 }
2214
2215 return pXApicPage->tpr.u8Tpr;
2216}
2217
2218
2219/**
2220 * @interface_method_impl{PDMAPICREG,pfnGetTimerFreqR3}
2221 */
2222VMMDECL(uint64_t) APICGetTimerFreq(PPDMDEVINS pDevIns)
2223{
2224 PVM pVM = PDMDevHlpGetVM(pDevIns);
2225 PVMCPU pVCpu = &pVM->aCpus[0];
2226 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
2227 uint64_t uTimer = TMTimerGetFreq(pApicCpu->CTX_SUFF(pTimer));
2228 return uTimer;
2229}
2230
2231
2232/**
2233 * @interface_method_impl{PDMAPICREG,pfnBusDeliverR3}
2234 * @remarks This is a private interface between the IOAPIC and the APIC.
2235 */
2236VMMDECL(int) APICBusDeliver(PPDMDEVINS pDevIns, uint8_t uDest, uint8_t uDestMode, uint8_t uDeliveryMode, uint8_t uVector,
2237 uint8_t uPolarity, uint8_t uTriggerMode, uint32_t uTagSrc)
2238{
2239 NOREF(uPolarity);
2240 NOREF(uTagSrc);
2241 PVM pVM = PDMDevHlpGetVM(pDevIns);
2242
2243 /*
2244 * The destination field (mask) in the IO APIC redirectable table entry is 8-bits.
2245 * Hence, the broadcast mask is 0xff.
2246 * See IO APIC spec. 3.2.4. "IOREDTBL[23:0] - I/O Redirectable Table Registers".
2247 */
2248 XAPICTRIGGERMODE enmTriggerMode = (XAPICTRIGGERMODE)uTriggerMode;
2249 XAPICDELIVERYMODE enmDeliveryMode = (XAPICDELIVERYMODE)uDeliveryMode;
2250 XAPICDESTMODE enmDestMode = (XAPICDESTMODE)uDestMode;
2251 uint32_t fDestMask = uDest;
2252 uint32_t fBroadcastMask = UINT32_C(0xff);
2253
2254 Log2(("APIC: apicBusDeliver: fDestMask=%#x enmDestMode=%s enmTriggerMode=%s enmDeliveryMode=%s uVector=%#x\n", fDestMask,
2255 apicGetDestModeName(enmDestMode), apicGetTriggerModeName(enmTriggerMode), apicGetDeliveryModeName(enmDeliveryMode),
2256 uVector));
2257
2258 VMCPUSET DestCpuSet;
2259 apicGetDestCpuSet(pVM, fDestMask, fBroadcastMask, enmDestMode, enmDeliveryMode, &DestCpuSet);
2260 VBOXSTRICTRC rcStrict = apicSendIntr(pVM, NULL /* pVCpu */, uVector, enmTriggerMode, enmDeliveryMode, &DestCpuSet,
2261 VINF_SUCCESS /* rcRZ */);
2262 return VBOXSTRICTRC_VAL(rcStrict);
2263}
2264
2265
2266/**
2267 * @interface_method_impl{PDMAPICREG,pfnLocalInterruptR3}
2268 * @remarks This is a private interface between the PIC and the APIC.
2269 */
2270VMMDECL(VBOXSTRICTRC) APICLocalInterrupt(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint8_t u8Pin, uint8_t u8Level, int rcRZ)
2271{
2272 NOREF(pDevIns);
2273 AssertReturn(u8Pin <= 1, VERR_INVALID_PARAMETER);
2274 AssertReturn(u8Level <= 1, VERR_INVALID_PARAMETER);
2275
2276 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
2277
2278 /* If the APIC is enabled, the interrupt is subject to LVT programming. */
2279 if (apicIsEnabled(pVCpu))
2280 {
2281 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
2282
2283 /* Pick the LVT entry corresponding to the interrupt pin. */
2284 static const uint16_t s_au16LvtOffsets[] =
2285 {
2286 XAPIC_OFF_LVT_LINT0,
2287 XAPIC_OFF_LVT_LINT1
2288 };
2289 Assert(u8Pin < RT_ELEMENTS(s_au16LvtOffsets));
2290 uint16_t const offLvt = s_au16LvtOffsets[u8Pin];
2291 uint32_t const uLvt = apicReadRaw32(pXApicPage, offLvt);
2292
2293 /* If software hasn't masked the interrupt in the LVT entry, proceed interrupt processing. */
2294 if (!XAPIC_LVT_IS_MASKED(uLvt))
2295 {
2296 XAPICDELIVERYMODE const enmDeliveryMode = XAPIC_LVT_GET_DELIVERY_MODE(uLvt);
2297 XAPICTRIGGERMODE enmTriggerMode = XAPIC_LVT_GET_TRIGGER_MODE(uLvt);
2298
2299 switch (enmDeliveryMode)
2300 {
2301 case XAPICDELIVERYMODE_INIT:
2302 {
2303 /** @todo won't work in R0/RC because callers don't care about rcRZ. */
2304 AssertMsgFailed(("INIT through LINT0/LINT1 is not yet supported\n"));
2305 /* fallthru */
2306 }
2307 case XAPICDELIVERYMODE_FIXED:
2308 {
2309 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
2310 uint8_t const uVector = XAPIC_LVT_GET_VECTOR(uLvt);
2311 bool fActive = RT_BOOL(u8Level & 1);
2312 bool volatile *pfActiveLine = u8Pin == 0 ? &pApicCpu->fActiveLint0 : &pApicCpu->fActiveLint1;
2313 /** @todo Polarity is busted elsewhere, we need to fix that
2314 * first. See @bugref{8386#c7}. */
2315#if 0
2316 uint8_t const u8Polarity = XAPIC_LVT_GET_POLARITY(uLvt);
2317 fActive ^= u8Polarity; */
2318#endif
2319 if (!fActive)
2320 {
2321 ASMAtomicCmpXchgBool(pfActiveLine, false, true);
2322 break;
2323 }
2324
2325 /* Level-sensitive interrupts are not supported for LINT1. See Intel spec. 10.5.1 "Local Vector Table". */
2326 if (offLvt == XAPIC_OFF_LVT_LINT1)
2327 enmTriggerMode = XAPICTRIGGERMODE_EDGE;
2328 /** @todo figure out what "If the local APIC is not used in conjunction with an I/O APIC and fixed
2329 delivery mode is selected; the Pentium 4, Intel Xeon, and P6 family processors will always
2330 use level-sensitive triggering, regardless if edge-sensitive triggering is selected."
2331 means. */
2332
2333 bool fSendIntr;
2334 if (enmTriggerMode == XAPICTRIGGERMODE_EDGE)
2335 {
2336 /* Recognize and send the interrupt only on an edge transition. */
2337 fSendIntr = ASMAtomicCmpXchgBool(pfActiveLine, true, false);
2338 }
2339 else
2340 {
2341 /* For level-triggered interrupts, redundant interrupts are not a problem. */
2342 Assert(enmTriggerMode == XAPICTRIGGERMODE_LEVEL);
2343 ASMAtomicCmpXchgBool(pfActiveLine, true, false);
2344
2345 /* Only when the remote IRR isn't set, set it and send the interrupt. */
2346 if (!(pXApicPage->lvt_lint0.all.u32LvtLint0 & XAPIC_LVT_REMOTE_IRR))
2347 {
2348 Assert(offLvt == XAPIC_OFF_LVT_LINT0);
2349 ASMAtomicOrU32((volatile uint32_t *)&pXApicPage->lvt_lint0.all.u32LvtLint0, XAPIC_LVT_REMOTE_IRR);
2350 fSendIntr = true;
2351 }
2352 else
2353 fSendIntr = false;
2354 }
2355
2356 if (fSendIntr)
2357 {
2358 VMCPUSET DestCpuSet;
2359 VMCPUSET_EMPTY(&DestCpuSet);
2360 VMCPUSET_ADD(&DestCpuSet, pVCpu->idCpu);
2361 rcStrict = apicSendIntr(pVCpu->CTX_SUFF(pVM), pVCpu, uVector, enmTriggerMode, enmDeliveryMode,
2362 &DestCpuSet, rcRZ);
2363 }
2364 break;
2365 }
2366
2367 case XAPICDELIVERYMODE_SMI:
2368 case XAPICDELIVERYMODE_NMI:
2369 {
2370 VMCPUSET DestCpuSet;
2371 VMCPUSET_EMPTY(&DestCpuSet);
2372 VMCPUSET_ADD(&DestCpuSet, pVCpu->idCpu);
2373 uint8_t const uVector = XAPIC_LVT_GET_VECTOR(uLvt);
2374 rcStrict = apicSendIntr(pVCpu->CTX_SUFF(pVM), pVCpu, uVector, enmTriggerMode, enmDeliveryMode, &DestCpuSet,
2375 rcRZ);
2376 break;
2377 }
2378
2379 case XAPICDELIVERYMODE_EXTINT:
2380 {
2381 Log2(("APIC%u: APICLocalInterrupt: %s ExtINT through LINT%u\n", pVCpu->idCpu,
2382 u8Level ? "Raising" : "Lowering", u8Pin));
2383 if (u8Level)
2384 APICSetInterruptFF(pVCpu, PDMAPICIRQ_EXTINT);
2385 else
2386 APICClearInterruptFF(pVCpu, PDMAPICIRQ_EXTINT);
2387 break;
2388 }
2389
2390 /* Reserved/unknown delivery modes: */
2391 case XAPICDELIVERYMODE_LOWEST_PRIO:
2392 case XAPICDELIVERYMODE_STARTUP:
2393 default:
2394 {
2395 rcStrict = VERR_INTERNAL_ERROR_3;
2396 AssertMsgFailed(("APIC%u: LocalInterrupt: Invalid delivery mode %#x (%s) on LINT%d\n", pVCpu->idCpu,
2397 enmDeliveryMode, apicGetDeliveryModeName(enmDeliveryMode), u8Pin));
2398 break;
2399 }
2400 }
2401 }
2402 }
2403 else
2404 {
2405 /* The APIC is hardware disabled. The CPU behaves as though there is no on-chip APIC. */
2406 if (u8Pin == 0)
2407 {
2408 /* LINT0 behaves as an external interrupt pin. */
2409 Log2(("APIC%u: APICLocalInterrupt: APIC hardware-disabled, %s INTR\n", pVCpu->idCpu,
2410 u8Level ? "raising" : "lowering"));
2411 if (u8Level)
2412 APICSetInterruptFF(pVCpu, PDMAPICIRQ_EXTINT);
2413 else
2414 APICClearInterruptFF(pVCpu, PDMAPICIRQ_EXTINT);
2415 }
2416 else
2417 {
2418 /* LINT1 behaves as NMI. */
2419 Log2(("APIC%u: APICLocalInterrupt: APIC hardware-disabled, raising NMI\n", pVCpu->idCpu));
2420 APICSetInterruptFF(pVCpu, PDMAPICIRQ_NMI);
2421 }
2422 }
2423
2424 return rcStrict;
2425}
2426
2427
2428/**
2429 * @interface_method_impl{PDMAPICREG,pfnGetInterruptR3}
2430 */
2431VMMDECL(int) APICGetInterrupt(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint8_t *pu8Vector, uint32_t *pu32TagSrc)
2432{
2433 VMCPU_ASSERT_EMT(pVCpu);
2434 Assert(pu8Vector);
2435 NOREF(pu32TagSrc);
2436
2437 LogFlow(("APIC%u: APICGetInterrupt:\n", pVCpu->idCpu));
2438
2439 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
2440 bool const fApicHwEnabled = apicIsEnabled(pVCpu);
2441 if ( fApicHwEnabled
2442 && pXApicPage->svr.u.fApicSoftwareEnable)
2443 {
2444 int const irrv = apicGetHighestSetBitInReg(&pXApicPage->irr, -1);
2445 if (RT_LIKELY(irrv >= 0))
2446 {
2447 Assert(irrv <= (int)UINT8_MAX);
2448 uint8_t const uVector = irrv;
2449
2450 /*
2451 * This can happen if the APIC receives an interrupt when the CPU has interrupts
2452 * disabled but the TPR is raised by the guest before re-enabling interrupts.
2453 */
2454 uint8_t const uTpr = pXApicPage->tpr.u8Tpr;
2455 if ( uTpr > 0
2456 && XAPIC_TPR_GET_TP(uVector) <= XAPIC_TPR_GET_TP(uTpr))
2457 {
2458 Log2(("APIC%u: APICGetInterrupt: Interrupt masked. uVector=%#x uTpr=%#x SpuriousVector=%#x\n", pVCpu->idCpu,
2459 uVector, uTpr, pXApicPage->svr.u.u8SpuriousVector));
2460 *pu8Vector = uVector;
2461 STAM_COUNTER_INC(&pVCpu->apic.s.StatMaskedByTpr);
2462 return VERR_APIC_INTR_MASKED_BY_TPR;
2463 }
2464
2465 /*
2466 * The PPR should be up-to-date at this point through apicSetEoi().
2467 * We're on EMT so no parallel updates possible.
2468 * Subject the pending vector to PPR prioritization.
2469 */
2470 uint8_t const uPpr = pXApicPage->ppr.u8Ppr;
2471 if ( !uPpr
2472 || XAPIC_PPR_GET_PP(uVector) > XAPIC_PPR_GET_PP(uPpr))
2473 {
2474 apicClearVectorInReg(&pXApicPage->irr, uVector);
2475 apicSetVectorInReg(&pXApicPage->isr, uVector);
2476 apicUpdatePpr(pVCpu);
2477 apicSignalNextPendingIntr(pVCpu);
2478
2479 Log2(("APIC%u: APICGetInterrupt: Valid Interrupt. uVector=%#x\n", pVCpu->idCpu, uVector));
2480 *pu8Vector = uVector;
2481 return VINF_SUCCESS;
2482 }
2483 else
2484 {
2485 STAM_COUNTER_INC(&pVCpu->apic.s.StatMaskedByPpr);
2486 Log2(("APIC%u: APICGetInterrupt: Interrupt's priority is not higher than the PPR. uVector=%#x PPR=%#x\n",
2487 pVCpu->idCpu, uVector, uPpr));
2488 }
2489 }
2490 else
2491 Log2(("APIC%u: APICGetInterrupt: No pending bits in IRR\n", pVCpu->idCpu));
2492 }
2493 else
2494 Log2(("APIC%u: APICGetInterrupt: APIC %s disabled\n", pVCpu->idCpu, !fApicHwEnabled ? "hardware" : "software"));
2495
2496 return VERR_APIC_INTR_NOT_PENDING;
2497}
2498
2499
2500/**
2501 * @callback_method_impl{FNIOMMMIOREAD}
2502 */
2503VMMDECL(int) APICReadMmio(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
2504{
2505 NOREF(pvUser);
2506 Assert(!(GCPhysAddr & 0xf));
2507 Assert(cb == 4);
2508
2509 PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
2510 PVMCPU pVCpu = PDMDevHlpGetVMCPU(pDevIns);
2511 uint16_t offReg = GCPhysAddr & 0xff0;
2512 uint32_t uValue = 0;
2513
2514 STAM_COUNTER_INC(&pVCpu->apic.s.CTX_SUFF(StatMmioRead));
2515
2516 int rc = apicReadRegister(pApicDev, pVCpu, offReg, &uValue);
2517 *(uint32_t *)pv = uValue;
2518
2519 Log2(("APIC%u: APICReadMmio: offReg=%#RX16 uValue=%#RX32\n", pVCpu->idCpu, offReg, uValue));
2520 return rc;
2521}
2522
2523
2524/**
2525 * @callback_method_impl{FNIOMMMIOWRITE}
2526 */
2527VMMDECL(int) APICWriteMmio(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
2528{
2529 NOREF(pvUser);
2530 Assert(!(GCPhysAddr & 0xf));
2531 Assert(cb == 4);
2532
2533 PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
2534 PVMCPU pVCpu = PDMDevHlpGetVMCPU(pDevIns);
2535 uint16_t offReg = GCPhysAddr & 0xff0;
2536 uint32_t uValue = *(uint32_t *)pv;
2537
2538 STAM_COUNTER_INC(&pVCpu->apic.s.CTX_SUFF(StatMmioWrite));
2539
2540 Log2(("APIC%u: APICWriteMmio: offReg=%#RX16 uValue=%#RX32\n", pVCpu->idCpu, offReg, uValue));
2541
2542 int rc = VBOXSTRICTRC_VAL(apicWriteRegister(pApicDev, pVCpu, offReg, uValue));
2543 return rc;
2544}
2545
2546
2547/**
2548 * Sets the interrupt pending force-flag and pokes the EMT if required.
2549 *
2550 * @param pVCpu The cross context virtual CPU structure.
2551 * @param enmType The IRQ type.
2552 */
2553VMMDECL(void) APICSetInterruptFF(PVMCPU pVCpu, PDMAPICIRQ enmType)
2554{
2555 PVM pVM = pVCpu->CTX_SUFF(pVM);
2556 PAPICDEV pApicDev = VM_TO_APICDEV(pVM);
2557 CTX_SUFF(pApicDev->pApicHlp)->pfnSetInterruptFF(pApicDev->CTX_SUFF(pDevIns), enmType, pVCpu->idCpu);
2558}
2559
2560
2561/**
2562 * Clears the interrupt pending force-flag.
2563 *
2564 * @param pVCpu The cross context virtual CPU structure.
2565 * @param enmType The IRQ type.
2566 */
2567VMMDECL(void) APICClearInterruptFF(PVMCPU pVCpu, PDMAPICIRQ enmType)
2568{
2569 PVM pVM = pVCpu->CTX_SUFF(pVM);
2570 PAPICDEV pApicDev = VM_TO_APICDEV(pVM);
2571 pApicDev->CTX_SUFF(pApicHlp)->pfnClearInterruptFF(pApicDev->CTX_SUFF(pDevIns), enmType, pVCpu->idCpu);
2572}
2573
2574
2575/**
2576 * Posts an interrupt to a target APIC.
2577 *
2578 * This function handles interrupts received from the system bus or
2579 * interrupts generated locally from the LVT or via a self IPI.
2580 *
2581 * Don't use this function to try and deliver ExtINT style interrupts.
2582 *
2583 * @param pVCpu The cross context virtual CPU structure.
2584 * @param uVector The vector of the interrupt to be posted.
2585 * @param enmTriggerMode The trigger mode of the interrupt.
2586 *
2587 * @thread Any.
2588 */
2589VMM_INT_DECL(void) APICPostInterrupt(PVMCPU pVCpu, uint8_t uVector, XAPICTRIGGERMODE enmTriggerMode)
2590{
2591 Assert(pVCpu);
2592 Assert(uVector > XAPIC_ILLEGAL_VECTOR_END);
2593
2594 PVM pVM = pVCpu->CTX_SUFF(pVM);
2595 PCAPIC pApic = VM_TO_APIC(pVM);
2596 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
2597
2598 STAM_PROFILE_START(&pApicCpu->StatPostIntr, a);
2599
2600 /*
2601 * Only post valid interrupt vectors.
2602 * See Intel spec. 10.5.2 "Valid Interrupt Vectors".
2603 */
2604 if (RT_LIKELY(uVector > XAPIC_ILLEGAL_VECTOR_END))
2605 {
2606 /*
2607 * If the interrupt is already pending in the IRR we can skip the
2608 * potential expensive operation of poking the guest EMT out of execution.
2609 */
2610 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
2611 if (!apicTestVectorInReg(&pXApicPage->irr, uVector)) /* PAV */
2612 {
2613 Log2(("APIC: APICPostInterrupt: SrcCpu=%u TargetCpu=%u uVector=%#x\n", VMMGetCpuId(pVM), pVCpu->idCpu, uVector));
2614 if (enmTriggerMode == XAPICTRIGGERMODE_EDGE)
2615 {
2616 if (pApic->fPostedIntrsEnabled)
2617 { /** @todo posted-interrupt call to hardware */ }
2618 else
2619 {
2620 apicSetVectorInPib(pApicCpu->CTX_SUFF(pvApicPib), uVector);
2621 uint32_t const fAlreadySet = apicSetNotificationBitInPib((PAPICPIB)pApicCpu->CTX_SUFF(pvApicPib));
2622 if (!fAlreadySet)
2623 {
2624 Log2(("APIC: APICPostInterrupt: Setting UPDATE_APIC FF for edge-triggered intr. uVector=%#x\n", uVector));
2625 APICSetInterruptFF(pVCpu, PDMAPICIRQ_UPDATE_PENDING);
2626 }
2627 }
2628 }
2629 else
2630 {
2631 /*
2632 * Level-triggered interrupts requires updating of the TMR and thus cannot be
2633 * delivered asynchronously.
2634 */
2635 apicSetVectorInPib(&pApicCpu->ApicPibLevel, uVector);
2636 uint32_t const fAlreadySet = apicSetNotificationBitInPib(&pApicCpu->ApicPibLevel);
2637 if (!fAlreadySet)
2638 {
2639 Log2(("APIC: APICPostInterrupt: Setting UPDATE_APIC FF for level-triggered intr. uVector=%#x\n", uVector));
2640 APICSetInterruptFF(pVCpu, PDMAPICIRQ_UPDATE_PENDING);
2641 }
2642 }
2643 }
2644 else
2645 {
2646 Log2(("APIC: APICPostInterrupt: SrcCpu=%u TargetCpu=%u. Vector %#x Already in IRR, skipping\n", VMMGetCpuId(pVM),
2647 pVCpu->idCpu, uVector));
2648 STAM_COUNTER_INC(&pApicCpu->StatPostIntrAlreadyPending);
2649 }
2650 }
2651 else
2652 apicSetError(pVCpu, XAPIC_ESR_RECV_ILLEGAL_VECTOR);
2653
2654 STAM_PROFILE_STOP(&pApicCpu->StatPostIntr, a);
2655}
2656
2657
2658/**
2659 * Starts the APIC timer.
2660 *
2661 * @param pVCpu The cross context virtual CPU structure.
2662 * @param uInitialCount The timer's Initial-Count Register (ICR), must be >
2663 * 0.
2664 * @thread Any.
2665 */
2666VMM_INT_DECL(void) APICStartTimer(PVMCPU pVCpu, uint32_t uInitialCount)
2667{
2668 Assert(pVCpu);
2669 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
2670 Assert(TMTimerIsLockOwner(pApicCpu->CTX_SUFF(pTimer)));
2671 Assert(uInitialCount > 0);
2672
2673 PCXAPICPAGE pXApicPage = APICCPU_TO_CXAPICPAGE(pApicCpu);
2674 uint8_t const uTimerShift = apicGetTimerShift(pXApicPage);
2675 uint64_t const cTicksToNext = (uint64_t)uInitialCount << uTimerShift;
2676
2677 Log2(("APIC%u: APICStartTimer: uInitialCount=%#RX32 uTimerShift=%u cTicksToNext=%RU64\n", pVCpu->idCpu, uInitialCount,
2678 uTimerShift, cTicksToNext));
2679
2680 /*
2681 * The assumption here is that the timer doesn't tick during this call
2682 * and thus setting a relative time to fire next is accurate. The advantage
2683 * however is updating u64TimerInitial 'atomically' while setting the next
2684 * tick.
2685 */
2686 PTMTIMER pTimer = pApicCpu->CTX_SUFF(pTimer);
2687 TMTimerSetRelative(pTimer, cTicksToNext, &pApicCpu->u64TimerInitial);
2688 apicHintTimerFreq(pApicCpu, uInitialCount, uTimerShift);
2689}
2690
2691
2692/**
2693 * Stops the APIC timer.
2694 *
2695 * @param pVCpu The cross context virtual CPU structure.
2696 * @thread Any.
2697 */
2698VMM_INT_DECL(void) APICStopTimer(PVMCPU pVCpu)
2699{
2700 Assert(pVCpu);
2701 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
2702 Assert(TMTimerIsLockOwner(pApicCpu->CTX_SUFF(pTimer)));
2703
2704 Log2(("APIC%u: APICStopTimer\n", pVCpu->idCpu));
2705
2706 PTMTIMER pTimer = pApicCpu->CTX_SUFF(pTimer);
2707 TMTimerStop(pTimer); /* This will reset the hint, no need to explicitly call TMTimerSetFrequencyHint(). */
2708 pApicCpu->uHintedTimerInitialCount = 0;
2709 pApicCpu->uHintedTimerShift = 0;
2710}
2711
2712
2713/**
2714 * Queues a pending interrupt as in-service.
2715 *
2716 * This function should only be needed without virtualized APIC
2717 * registers. With virtualized APIC registers, it's sufficient to keep
2718 * the interrupts pending in the IRR as the hardware takes care of
2719 * virtual interrupt delivery.
2720 *
2721 * @returns true if the interrupt was queued to in-service interrupts,
2722 * false otherwise.
2723 * @param pVCpu The cross context virtual CPU structure.
2724 * @param u8PendingIntr The pending interrupt to queue as
2725 * in-service.
2726 *
2727 * @remarks This assumes the caller has done the necessary checks and
2728 * is ready to take actually service the interrupt (TPR,
2729 * interrupt shadow etc.)
2730 */
2731VMMDECL(bool) APICQueueInterruptToService(PVMCPU pVCpu, uint8_t u8PendingIntr)
2732{
2733 VMCPU_ASSERT_EMT(pVCpu);
2734
2735 PVM pVM = pVCpu->CTX_SUFF(pVM);
2736 PAPIC pApic = VM_TO_APIC(pVM);
2737 Assert(!pApic->fVirtApicRegsEnabled);
2738 NOREF(pApic);
2739
2740 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
2741 bool const fIsPending = apicTestVectorInReg(&pXApicPage->irr, u8PendingIntr);
2742 if (fIsPending)
2743 {
2744 apicClearVectorInReg(&pXApicPage->irr, u8PendingIntr);
2745 apicSetVectorInReg(&pXApicPage->isr, u8PendingIntr);
2746 apicUpdatePpr(pVCpu);
2747 return true;
2748 }
2749 return false;
2750}
2751
2752
2753/**
2754 * De-queues a pending interrupt from in-service.
2755 *
2756 * This undoes APICQueueInterruptToService() for premature VM-exits before event
2757 * injection.
2758 *
2759 * @param pVCpu The cross context virtual CPU structure.
2760 * @param u8PendingIntr The pending interrupt to de-queue from
2761 * in-service.
2762 */
2763VMMDECL(void) APICDequeueInterruptFromService(PVMCPU pVCpu, uint8_t u8PendingIntr)
2764{
2765 VMCPU_ASSERT_EMT(pVCpu);
2766
2767 PVM pVM = pVCpu->CTX_SUFF(pVM);
2768 PAPIC pApic = VM_TO_APIC(pVM);
2769 Assert(!pApic->fVirtApicRegsEnabled);
2770 NOREF(pApic);
2771
2772 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
2773 bool const fInService = apicTestVectorInReg(&pXApicPage->isr, u8PendingIntr);
2774 if (fInService)
2775 {
2776 apicClearVectorInReg(&pXApicPage->isr, u8PendingIntr);
2777 apicSetVectorInReg(&pXApicPage->irr, u8PendingIntr);
2778 apicUpdatePpr(pVCpu);
2779 }
2780}
2781
2782
2783/**
2784 * Updates pending interrupts from the pending-interrupt bitmaps to the IRR.
2785 *
2786 * @param pVCpu The cross context virtual CPU structure.
2787 */
2788VMMDECL(void) APICUpdatePendingInterrupts(PVMCPU pVCpu)
2789{
2790 VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
2791
2792 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
2793 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
2794 bool fHasPendingIntrs = false;
2795
2796 Log3(("APIC%u: APICUpdatePendingInterrupts:\n", pVCpu->idCpu));
2797 STAM_PROFILE_START(&pApicCpu->StatUpdatePendingIntrs, a);
2798
2799 /* Update edge-triggered pending interrupts. */
2800 for (;;)
2801 {
2802 uint32_t const fAlreadySet = apicClearNotificationBitInPib((PAPICPIB)pApicCpu->CTX_SUFF(pvApicPib));
2803 if (!fAlreadySet)
2804 break;
2805
2806 PAPICPIB pPib = (PAPICPIB)pApicCpu->CTX_SUFF(pvApicPib);
2807 AssertCompile(RT_ELEMENTS(pXApicPage->irr.u) == 2 * RT_ELEMENTS(pPib->aVectorBitmap));
2808
2809 for (size_t idxPib = 0, idxReg = 0; idxPib < RT_ELEMENTS(pPib->aVectorBitmap); idxPib++, idxReg += 2)
2810 {
2811 uint64_t const u64Fragment = ASMAtomicXchgU64(&pPib->aVectorBitmap[idxPib], 0);
2812 if (u64Fragment)
2813 {
2814 uint32_t const u32FragmentLo = RT_LO_U32(u64Fragment);
2815 uint32_t const u32FragmentHi = RT_HI_U32(u64Fragment);
2816
2817 pXApicPage->irr.u[idxReg].u32Reg |= u32FragmentLo;
2818 pXApicPage->irr.u[idxReg + 1].u32Reg |= u32FragmentHi;
2819
2820 pXApicPage->tmr.u[idxReg].u32Reg &= ~u32FragmentLo;
2821 pXApicPage->tmr.u[idxReg + 1].u32Reg &= ~u32FragmentHi;
2822 fHasPendingIntrs = true;
2823 }
2824 }
2825 }
2826
2827 /* Update level-triggered pending interrupts. */
2828 for (;;)
2829 {
2830 uint32_t const fAlreadySet = apicClearNotificationBitInPib((PAPICPIB)&pApicCpu->ApicPibLevel);
2831 if (!fAlreadySet)
2832 break;
2833
2834 PAPICPIB pPib = (PAPICPIB)&pApicCpu->ApicPibLevel;
2835 AssertCompile(RT_ELEMENTS(pXApicPage->irr.u) == 2 * RT_ELEMENTS(pPib->aVectorBitmap));
2836
2837 for (size_t idxPib = 0, idxReg = 0; idxPib < RT_ELEMENTS(pPib->aVectorBitmap); idxPib++, idxReg += 2)
2838 {
2839 uint64_t const u64Fragment = ASMAtomicXchgU64(&pPib->aVectorBitmap[idxPib], 0);
2840 if (u64Fragment)
2841 {
2842 uint32_t const u32FragmentLo = RT_LO_U32(u64Fragment);
2843 uint32_t const u32FragmentHi = RT_HI_U32(u64Fragment);
2844
2845 pXApicPage->irr.u[idxReg].u32Reg |= u32FragmentLo;
2846 pXApicPage->irr.u[idxReg + 1].u32Reg |= u32FragmentHi;
2847
2848 pXApicPage->tmr.u[idxReg].u32Reg |= u32FragmentLo;
2849 pXApicPage->tmr.u[idxReg + 1].u32Reg |= u32FragmentHi;
2850 fHasPendingIntrs = true;
2851 }
2852 }
2853 }
2854
2855 STAM_PROFILE_STOP(&pApicCpu->StatUpdatePendingIntrs, a);
2856 Log3(("APIC%u: APICUpdatePendingInterrupts: fHasPendingIntrs=%RTbool\n", pVCpu->idCpu, fHasPendingIntrs));
2857
2858 if ( fHasPendingIntrs
2859 && !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC))
2860 apicSignalNextPendingIntr(pVCpu);
2861}
2862
2863
2864/**
2865 * Gets the highest priority pending interrupt.
2866 *
2867 * @returns true if any interrupt is pending, false otherwise.
2868 * @param pVCpu The cross context virtual CPU structure.
2869 * @param pu8PendingIntr Where to store the interrupt vector if the
2870 * interrupt is pending.
2871 */
2872VMMDECL(bool) APICGetHighestPendingInterrupt(PVMCPU pVCpu, uint8_t *pu8PendingIntr)
2873{
2874 VMCPU_ASSERT_EMT(pVCpu);
2875 return apicGetHighestPendingInterrupt(pVCpu, pu8PendingIntr);
2876}
2877
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette