CPUMAllA.asm@ 14082

Last change on this file since 14082 was 13960, checked in by vboxsync, 16 years ago
Moved guest and host CPU contexts into per-VCPU array.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 12.1 KB

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1	; $Id: CPUMAllA.asm 13960 2008-11-07 13:04:45Z vboxsync $
2	;; @file
3	; CPUM - Guest Context Assembly Routines.
4	;
5
6	;
7	; Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	;
9	; This file is part of VirtualBox Open Source Edition (OSE), as
10	; available from http://www.virtualbox.org. This file is free software;
11	; you can redistribute it and/or modify it under the terms of the GNU
12	; General Public License (GPL) as published by the Free Software
13	; Foundation, in version 2 as it comes in the "COPYING" file of the
14	; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	;
17	; Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	; Clara, CA 95054 USA or visit http://www.sun.com if you need
19	; additional information or have any questions.
20	;
21
22	;*******************************************************************************
23	;* Header Files *
24	;*******************************************************************************
25	%include "VBox/asmdefs.mac"
26	%include "VBox/vm.mac"
27	%include "VBox/err.mac"
28	%include "VBox/stam.mac"
29	%include "CPUMInternal.mac"
30	%include "VBox/x86.mac"
31	%include "VBox/cpum.mac"
32
33	%ifdef IN_RING3
34	%error "The jump table doesn't link on leopard."
35	%endif
36
37	;
38	; Enables write protection of Hypervisor memory pages.
39	; !note! Must be commented out for Trap8 debug handler.
40	;
41	%define ENABLE_WRITE_PROTECTION 1
42
43	BEGINCODE
44
45
46	;;
47	; Handles lazy FPU saving and restoring.
48	;
49	; This handler will implement lazy fpu (sse/mmx/stuff) saving.
50	; Two actions may be taken in this handler since the Guest OS may
51	; be doing lazy fpu switching. So, we'll have to generate those
52	; traps which the Guest CPU CTX shall have according to the
53	; its CR0 flags. If no traps for the Guest OS, we'll save the host
54	; context and restore the guest context.
55	;
56	; @returns 0 if caller should continue execution.
57	; @returns VINF_EM_RAW_GUEST_TRAP if a guest trap should be generated.
58	; @param pCPUMCPU x86:[esp+4] GCC:rdi MSC:rcx CPUMCPU pointer
59	;
60	align 16
61	BEGINPROC CPUMHandleLazyFPUAsm
62	;
63	; Figure out what to do.
64	;
65	; There are two basic actions:
66	; 1. Save host fpu and restore guest fpu.
67	; 2. Generate guest trap.
68	;
69	; When entering the hypervisor we'll always enable MP (for proper wait
70	; trapping) and TS (for intercepting all fpu/mmx/sse stuff). The EM flag
71	; is taken from the guest OS in order to get proper SSE handling.
72	;
73	;
74	; Actions taken depending on the guest CR0 flags:
75	;
76	; 3 2 1
77	; TS \| EM \| MP \| FPUInstr \| WAIT :: VMM Action
78	; ------------------------------------------------------------------------
79	; 0 \| 0 \| 0 \| Exec \| Exec :: Clear TS & MP, Save HC, Load GC.
80	; 0 \| 0 \| 1 \| Exec \| Exec :: Clear TS, Save HC, Load GC.
81	; 0 \| 1 \| 0 \| #NM \| Exec :: Clear TS & MP, Save HC, Load GC;
82	; 0 \| 1 \| 1 \| #NM \| Exec :: Clear TS, Save HC, Load GC.
83	; 1 \| 0 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already cleared.)
84	; 1 \| 0 \| 1 \| #NM \| #NM :: Go to host taking trap there.
85	; 1 \| 1 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already set.)
86	; 1 \| 1 \| 1 \| #NM \| #NM :: Go to host taking trap there.
87
88	;
89	; Before taking any of these actions we're checking if we have already
90	; loaded the GC FPU. Because if we have, this is an trap for the guest - raw ring-3.
91	;
92	%ifdef RT_ARCH_AMD64
93	%ifdef RT_OS_WINDOWS
94	mov xDX, rcx
95	%else
96	mov xDX, rdi
97	%endif
98	%else
99	mov xDX, dword [esp + 4]
100	%endif
101	test dword [xDX + CPUMCPU.fUseFlags], CPUM_USED_FPU
102	jz hlfpua_not_loaded
103	jmp hlfpua_to_host
104
105	;
106	; Take action.
107	;
108	align 16
109	hlfpua_not_loaded:
110	mov eax, [xDX + CPUMCPU.Guest.cr0]
111	and eax, X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS
112	%ifdef RT_ARCH_AMD64
113	lea r8, [hlfpuajmp1 wrt rip]
114	jmp qword [rax*4 + r8]
115	%else
116	jmp dword [eax*2 + hlfpuajmp1]
117	%endif
118	align 16
119	;; jump table using fpu related cr0 flags as index.
120	hlfpuajmp1:
121	RTCCPTR_DEF hlfpua_switch_fpu_ctx
122	RTCCPTR_DEF hlfpua_switch_fpu_ctx
123	RTCCPTR_DEF hlfpua_switch_fpu_ctx
124	RTCCPTR_DEF hlfpua_switch_fpu_ctx
125	RTCCPTR_DEF hlfpua_switch_fpu_ctx
126	RTCCPTR_DEF hlfpua_to_host
127	RTCCPTR_DEF hlfpua_switch_fpu_ctx
128	RTCCPTR_DEF hlfpua_to_host
129	;; and mask for cr0.
130	hlfpu_afFlags:
131	RTCCPTR_DEF ~(X86_CR0_TS \| X86_CR0_MP)
132	RTCCPTR_DEF ~(X86_CR0_TS)
133	RTCCPTR_DEF ~(X86_CR0_TS \| X86_CR0_MP)
134	RTCCPTR_DEF ~(X86_CR0_TS)
135	RTCCPTR_DEF ~(X86_CR0_MP)
136	RTCCPTR_DEF 0
137	RTCCPTR_DEF ~(X86_CR0_MP)
138	RTCCPTR_DEF 0
139
140	;
141	; Action - switch FPU context and change cr0 flags.
142	;
143	align 16
144	hlfpua_switch_fpu_ctx:
145	%ifndef IN_RING3 ; IN_RC or IN_RING0
146	mov xCX, cr0
147	%ifdef RT_ARCH_AMD64
148	lea r8, [hlfpu_afFlags wrt rip]
149	and rcx, [rax*4 + r8] ; calc the new cr0 flags.
150	%else
151	and ecx, [eax*2 + hlfpu_afFlags] ; calc the new cr0 flags.
152	%endif
153	mov xAX, cr0
154	and xAX, ~(X86_CR0_TS \| X86_CR0_EM)
155	mov cr0, xAX ; clear flags so we don't trap here.
156	%endif
157	%ifndef RT_ARCH_AMD64
158	mov eax, edx
159	; Calculate the PCPUM pointer
160	sub eax, [edx + CPUMCPU.ulOffCPUM]
161	test dword [eax + CPUM.CPUFeatures.edx], X86_CPUID_FEATURE_EDX_FXSR
162	jz short hlfpua_no_fxsave
163	%endif
164
165	fxsave [xDX + CPUMCPU.Host.fpu]
166	or dword [xDX + CPUMCPU.fUseFlags], (CPUM_USED_FPU \| CPUM_USED_FPU_SINCE_REM)
167	fxrstor [xDX + CPUMCPU.Guest.fpu]
168	hlfpua_finished_switch:
169	%ifdef IN_RC
170	mov cr0, xCX ; load the new cr0 flags.
171	%endif
172	; return continue execution.
173	xor eax, eax
174	ret
175
176	%ifndef RT_ARCH_AMD64
177	; legacy support.
178	hlfpua_no_fxsave:
179	fnsave [xDX + CPUMCPU.Host.fpu]
180	or dword [xDX + CPUMCPU.fUseFlags], dword (CPUM_USED_FPU \| CPUM_USED_FPU_SINCE_REM) ; yasm / nasm
181	mov eax, [xDX + CPUMCPU.Guest.fpu] ; control word
182	not eax ; 1 means exception ignored (6 LS bits)
183	and eax, byte 03Fh ; 6 LS bits only
184	test eax, [xDX + CPUMCPU.Guest.fpu + 4]; status word
185	jz short hlfpua_no_exceptions_pending
186	; technically incorrect, but we certainly don't want any exceptions now!!
187	and dword [xDX + CPUMCPU.Guest.fpu + 4], ~03Fh
188	hlfpua_no_exceptions_pending:
189	frstor [xDX + CPUMCPU.Guest.fpu]
190	jmp near hlfpua_finished_switch
191	%endif ; !RT_ARCH_AMD64
192
193
194	;
195	; Action - Generate Guest trap.
196	;
197	hlfpua_action_4:
198	hlfpua_to_host:
199	mov eax, VINF_EM_RAW_GUEST_TRAP
200	ret
201	ENDPROC CPUMHandleLazyFPUAsm
202
203
204	;;
205	; Restores the host's FPU/XMM state
206	;
207	; @returns 0
208	; @param pCPUMCPU x86:[esp+4] GCC:rdi MSC:rcx CPUMCPU pointer
209	;
210	align 16
211	BEGINPROC CPUMRestoreHostFPUStateAsm
212	%ifdef RT_ARCH_AMD64
213	%ifdef RT_OS_WINDOWS
214	mov xDX, rcx
215	%else
216	mov xDX, rdi
217	%endif
218	%else
219	mov xDX, dword [esp + 4]
220	%endif
221
222	; Restore FPU if guest has used it.
223	; Using fxrstor should ensure that we're not causing unwanted exception on the host.
224	test dword [xDX + CPUMCPU.fUseFlags], CPUM_USED_FPU
225	jz short gth_fpu_no
226
227	mov xAX, cr0
228	mov xCX, xAX ; save old CR0
229	and xAX, ~(X86_CR0_TS \| X86_CR0_EM)
230	mov cr0, xAX
231
232	fxsave [xDX + CPUMCPU.Guest.fpu]
233	fxrstor [xDX + CPUMCPU.Host.fpu]
234
235	mov cr0, xCX ; and restore old CR0 again
236	and dword [xDX + CPUMCPU.fUseFlags], ~CPUM_USED_FPU
237	gth_fpu_no:
238	xor eax, eax
239	ret
240	ENDPROC CPUMRestoreHostFPUStateAsm
241
242
243	;;
244	; Restores the guest's FPU/XMM state
245	;
246	; @param pCtx x86:[esp+4] GCC:rdi MSC:rcx CPUMCTX pointer
247	;
248	align 16
249	BEGINPROC CPUMLoadFPUAsm
250	%ifdef RT_ARCH_AMD64
251	%ifdef RT_OS_WINDOWS
252	mov xDX, rcx
253	%else
254	mov xDX, rdi
255	%endif
256	%else
257	mov xDX, dword [esp + 4]
258	%endif
259	fxrstor [xDX + CPUMCTX.fpu]
260	ret
261	ENDPROC CPUMLoadFPUAsm
262
263
264	;;
265	; Restores the guest's FPU/XMM state
266	;
267	; @param pCtx x86:[esp+4] GCC:rdi MSC:rcx CPUMCTX pointer
268	;
269	align 16
270	BEGINPROC CPUMSaveFPUAsm
271	%ifdef RT_ARCH_AMD64
272	%ifdef RT_OS_WINDOWS
273	mov xDX, rcx
274	%else
275	mov xDX, rdi
276	%endif
277	%else
278	mov xDX, dword [esp + 4]
279	%endif
280	fxsave [xDX + CPUMCTX.fpu]
281	ret
282	ENDPROC CPUMSaveFPUAsm
283
284
285	;;
286	; Restores the guest's XMM state
287	;
288	; @param pCtx x86:[esp+4] GCC:rdi MSC:rcx CPUMCTX pointer
289	;
290	align 16
291	BEGINPROC CPUMLoadXMMAsm
292	%ifdef RT_ARCH_AMD64
293	%ifdef RT_OS_WINDOWS
294	mov xDX, rcx
295	%else
296	mov xDX, rdi
297	%endif
298	%else
299	mov xDX, dword [esp + 4]
300	%endif
301	movdqa xmm0, [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*0]
302	movdqa xmm1, [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*1]
303	movdqa xmm2, [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*2]
304	movdqa xmm3, [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*3]
305	movdqa xmm4, [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*4]
306	movdqa xmm5, [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*5]
307	movdqa xmm6, [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*6]
308	movdqa xmm7, [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*7]
309
310	%ifdef RT_ARCH_AMD64
311	test qword [xDX + CPUMCTX.msrEFER], MSR_K6_EFER_LMA
312	jz CPUMLoadXMMAsm_done
313
314	movdqa xmm8, [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*8]
315	movdqa xmm9, [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*9]
316	movdqa xmm10, [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*10]
317	movdqa xmm11, [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*11]
318	movdqa xmm12, [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*12]
319	movdqa xmm13, [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*13]
320	movdqa xmm14, [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*14]
321	movdqa xmm15, [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*15]
322	CPUMLoadXMMAsm_done:
323	%endif
324
325	ret
326	ENDPROC CPUMLoadXMMAsm
327
328
329	;;
330	; Restores the guest's XMM state
331	;
332	; @param pCtx x86:[esp+4] GCC:rdi MSC:rcx CPUMCTX pointer
333	;
334	align 16
335	BEGINPROC CPUMSaveXMMAsm
336	%ifdef RT_ARCH_AMD64
337	%ifdef RT_OS_WINDOWS
338	mov xDX, rcx
339	%else
340	mov xDX, rdi
341	%endif
342	%else
343	mov xDX, dword [esp + 4]
344	%endif
345	movdqa [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*0], xmm0
346	movdqa [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*1], xmm1
347	movdqa [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*2], xmm2
348	movdqa [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*3], xmm3
349	movdqa [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*4], xmm4
350	movdqa [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*5], xmm5
351	movdqa [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*6], xmm6
352	movdqa [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*7], xmm7
353
354	%ifdef RT_ARCH_AMD64
355	test qword [xDX + CPUMCTX.msrEFER], MSR_K6_EFER_LMA
356	jz CPUMSaveXMMAsm_done
357
358	movdqa [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*8], xmm8
359	movdqa [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*9], xmm9
360	movdqa [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*10], xmm10
361	movdqa [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*11], xmm11
362	movdqa [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*12], xmm12
363	movdqa [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*13], xmm13
364	movdqa [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*14], xmm14
365	movdqa [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*15], xmm15
366
367	CPUMSaveXMMAsm_done:
368	%endif
369	ret
370	ENDPROC CPUMSaveXMMAsm
371
372
373	;;
374	; Set the FPU control word; clearing exceptions first
375	;
376	; @param u16FCW x86:[esp+4] GCC:rdi MSC:rcx New FPU control word
377	align 16
378	BEGINPROC CPUMSetFCW
379	%ifdef RT_ARCH_AMD64
380	%ifdef RT_OS_WINDOWS
381	mov xAX, rcx
382	%else
383	mov xAX, rdi
384	%endif
385	%else
386	mov xAX, dword [esp + 4]
387	%endif
388	fnclex
389	push xAX
390	fldcw [xSP]
391	pop xAX
392	ret
393	ENDPROC CPUMSetFCW
394
395
396	;;
397	; Get the FPU control word
398	;
399	align 16
400	BEGINPROC CPUMGetFCW
401	fnstcw [xSP - 8]
402	mov ax, word [xSP - 8]
403	ret
404	ENDPROC CPUMGetFCW
405
406
407	;;
408	; Set the MXCSR;
409	;
410	; @param u32MXCSR x86:[esp+4] GCC:rdi MSC:rcx New MXCSR
411	align 16
412	BEGINPROC CPUMSetMXCSR
413	%ifdef RT_ARCH_AMD64
414	%ifdef RT_OS_WINDOWS
415	mov xAX, rcx
416	%else
417	mov xAX, rdi
418	%endif
419	%else
420	mov xAX, dword [esp + 4]
421	%endif
422	push xAX
423	ldmxcsr [xSP]
424	pop xAX
425	ret
426	ENDPROC CPUMSetMXCSR
427
428
429	;;
430	; Get the MXCSR
431	;
432	align 16
433	BEGINPROC CPUMGetMXCSR
434	stmxcsr [xSP - 8]
435	mov eax, dword [xSP - 8]
436	ret
437	ENDPROC CPUMGetMXCSR

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source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllA.asm@ 14082

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