CPUMAllCpuId.cpp@ 107703

Last change on this file since 107703 was 107703, checked in by vboxsync, 9 days ago
VMM/CPUM: Try consolidate the MSR_IA32_ARCH_CAPABILITIES handling in CPUM and do better sanitizing of what's exposed to the guest. jiraref:VBP-947
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 108.1 KB

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1	/* $Id: CPUMAllCpuId.cpp 107703 2025-01-11 22:55:53Z vboxsync $ */
2	/** @file
3	* CPUM - CPU ID part, common bits.
4	*/
5
6	/*
7	* Copyright (C) 2013-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_CPUM
33	#include <VBox/vmm/cpum.h>
34	#include <VBox/vmm/hm.h>
35	#include <VBox/vmm/ssm.h>
36	#include "CPUMInternal.h"
37	#include <VBox/vmm/vmcc.h>
38	#include <VBox/sup.h>
39
40	#include <VBox/err.h>
41	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
42	# include <iprt/asm-amd64-x86.h>
43	#endif
44	#include <iprt/ctype.h>
45	#include <iprt/mem.h>
46	#include <iprt/string.h>
47	#include <iprt/x86-helpers.h>
48	#if defined(RT_ARCH_ARM64) \|\| defined(VBOX_VMM_TARGET_ARMV8)
49	# include <iprt/armv8.h>
50	#endif
51
52
53	/*********************************************************************************************************************************
54	* Global Variables *
55	*********************************************************************************************************************************/
56	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64) \|\| defined(VBOX_VMM_TARGET_X86)
57	/**
58	* The intel pentium family.
59	*/
60	static const CPUMMICROARCH g_aenmIntelFamily06[] =
61	{
62	/* [ 0(0x00)] = / kCpumMicroarch_Intel_P6, / Pentium Pro A-step (says sandpile.org). */
63	/* [ 1(0x01)] = / kCpumMicroarch_Intel_P6, / Pentium Pro */
64	/* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
65	/* [ 3(0x03)] = / kCpumMicroarch_Intel_P6_II, / PII Klamath */
66	/* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
67	/* [ 5(0x05)] = / kCpumMicroarch_Intel_P6_II, / PII Deschutes */
68	/* [ 6(0x06)] = / kCpumMicroarch_Intel_P6_II, / Celeron Mendocino. */
69	/* [ 7(0x07)] = / kCpumMicroarch_Intel_P6_III, / PIII Katmai. */
70	/* [ 8(0x08)] = / kCpumMicroarch_Intel_P6_III, / PIII Coppermine (includes Celeron). */
71	/* [ 9(0x09)] = / kCpumMicroarch_Intel_P6_M_Banias, / Pentium/Celeron M Banias. */
72	/* [10(0x0a)] = / kCpumMicroarch_Intel_P6_III, / PIII Xeon */
73	/* [11(0x0b)] = / kCpumMicroarch_Intel_P6_III, / PIII Tualatin (includes Celeron). */
74	/* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
75	/* [13(0x0d)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Pentium/Celeron M Dothan. */
76	/* [14(0x0e)] = / kCpumMicroarch_Intel_Core_Yonah, / Core Yonah (Enhanced Pentium M). */
77	/* [15(0x0f)] = / kCpumMicroarch_Intel_Core2_Merom, / Merom */
78	/* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
79	/* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
80	/* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
81	/* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
82	/* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
83	/* [21(0x15)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Tolapai - System-on-a-chip. */
84	/* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
85	/* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
86	/* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
87	/* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
88	/* [26(0x1a)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Nehalem-EP */
89	/* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
90	/* [28(0x1c)] = / kCpumMicroarch_Intel_Atom_Bonnell, / Diamonville, Pineview, */
91	/* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
92	/* [30(0x1e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Clarksfield, Lynnfield, Jasper Forest. */
93	/* [31(0x1f)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
94	/* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
95	/* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
96	/* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
97	/* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
98	/* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
99	/* [37(0x25)] = / kCpumMicroarch_Intel_Core7_Westmere, / Arrandale, Clarksdale. */
100	/* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
101	/* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
102	/* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
103	/* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
104	/* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
105	/* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
106	/* [44(0x2c)] = / kCpumMicroarch_Intel_Core7_Westmere, / Gulftown, Westmere-EP. */
107	/* [45(0x2d)] = / kCpumMicroarch_Intel_Core7_SandyBridge, / SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
108	/* [46(0x2e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Beckton (Xeon). */
109	/* [47(0x2f)] = / kCpumMicroarch_Intel_Core7_Westmere, / Westmere-EX. */
110	/* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
111	/* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
112	/* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
113	/* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
114	/* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
115	/* [53(0x35)] = / kCpumMicroarch_Intel_Atom_Saltwell, / ?? */
116	/* [54(0x36)] = / kCpumMicroarch_Intel_Atom_Saltwell, / Cedarview, ++ */
117	/* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
118	/* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
119	/* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
120	/* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
121	/* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
122	/* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
123	/* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
124	/* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
125	/* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
126	/* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
127	/* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
128	/* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
129	/* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
130	/* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
131	/* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
132	/* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
133	/* [71(0x47)] = / kCpumMicroarch_Intel_Core7_Broadwell, / i7-5775C */
134	/* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
135	/* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
136	/* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
137	/* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
138	/* [76(0x4c)] = */ kCpumMicroarch_Intel_Atom_Airmount,
139	/* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
140	/* [78(0x4e)] = */ kCpumMicroarch_Intel_Core7_Skylake,
141	/* [79(0x4f)] = / kCpumMicroarch_Intel_Core7_Broadwell, / Broadwell-E */
142	/* [80(0x50)] = */ kCpumMicroarch_Intel_Unknown,
143	/* [81(0x51)] = */ kCpumMicroarch_Intel_Unknown,
144	/* [82(0x52)] = */ kCpumMicroarch_Intel_Unknown,
145	/* [83(0x53)] = */ kCpumMicroarch_Intel_Unknown,
146	/* [84(0x54)] = */ kCpumMicroarch_Intel_Unknown,
147	/* [85(0x55)] = / kCpumMicroarch_Intel_Core7_Skylake, / server cpu; skylake <= 4, cascade lake > 5 */
148	/* [86(0x56)] = / kCpumMicroarch_Intel_Core7_Broadwell, / Xeon D-1540, Broadwell-DE */
149	/* [87(0x57)] = */ kCpumMicroarch_Intel_Phi_KnightsLanding,
150	/* [88(0x58)] = */ kCpumMicroarch_Intel_Unknown,
151	/* [89(0x59)] = */ kCpumMicroarch_Intel_Unknown,
152	/* [90(0x5a)] = / kCpumMicroarch_Intel_Atom_Silvermont, / Moorefield */
153	/* [91(0x5b)] = */ kCpumMicroarch_Intel_Unknown,
154	/* [92(0x5c)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Apollo Lake */
155	/* [93(0x5d)] = / kCpumMicroarch_Intel_Atom_Silvermont, / x3-C3230 */
156	/* [94(0x5e)] = / kCpumMicroarch_Intel_Core7_Skylake, / i7-6700K */
157	/* [95(0x5f)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Denverton */
158	/* [96(0x60)] = */ kCpumMicroarch_Intel_Unknown,
159	/* [97(0x61)] = */ kCpumMicroarch_Intel_Unknown,
160	/* [98(0x62)] = */ kCpumMicroarch_Intel_Unknown,
161	/* [99(0x63)] = */ kCpumMicroarch_Intel_Unknown,
162	/[100(0x64)] = / kCpumMicroarch_Intel_Unknown,
163	/[101(0x65)] = / kCpumMicroarch_Intel_Atom_Silvermont, /* SoFIA */
164	/[102(0x66)] = / kCpumMicroarch_Intel_Core7_CannonLake, /* unconfirmed */
165	/[103(0x67)] = / kCpumMicroarch_Intel_Unknown,
166	/[104(0x68)] = / kCpumMicroarch_Intel_Unknown,
167	/[105(0x69)] = / kCpumMicroarch_Intel_Unknown,
168	/[106(0x6a)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed server */
169	/[107(0x6b)] = / kCpumMicroarch_Intel_Unknown,
170	/[108(0x6c)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed server */
171	/[109(0x6d)] = / kCpumMicroarch_Intel_Unknown,
172	/[110(0x6e)] = / kCpumMicroarch_Intel_Atom_Airmount, /* or silvermount? */
173	/[111(0x6f)] = / kCpumMicroarch_Intel_Unknown,
174	/[112(0x70)] = / kCpumMicroarch_Intel_Unknown,
175	/[113(0x71)] = / kCpumMicroarch_Intel_Unknown,
176	/[114(0x72)] = / kCpumMicroarch_Intel_Unknown,
177	/[115(0x73)] = / kCpumMicroarch_Intel_Unknown,
178	/[116(0x74)] = / kCpumMicroarch_Intel_Unknown,
179	/[117(0x75)] = / kCpumMicroarch_Intel_Atom_Airmount, /* or silvermount? */
180	/[118(0x76)] = / kCpumMicroarch_Intel_Unknown,
181	/[119(0x77)] = / kCpumMicroarch_Intel_Unknown,
182	/[120(0x78)] = / kCpumMicroarch_Intel_Unknown,
183	/[121(0x79)] = / kCpumMicroarch_Intel_Unknown,
184	/[122(0x7a)] = / kCpumMicroarch_Intel_Atom_GoldmontPlus,
185	/[123(0x7b)] = / kCpumMicroarch_Intel_Unknown,
186	/[124(0x7c)] = / kCpumMicroarch_Intel_Unknown,
187	/[125(0x7d)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed */
188	/[126(0x7e)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed */
189	/[127(0x7f)] = / kCpumMicroarch_Intel_Unknown,
190	/[128(0x80)] = / kCpumMicroarch_Intel_Unknown,
191	/[129(0x81)] = / kCpumMicroarch_Intel_Unknown,
192	/[130(0x82)] = / kCpumMicroarch_Intel_Unknown,
193	/[131(0x83)] = / kCpumMicroarch_Intel_Unknown,
194	/[132(0x84)] = / kCpumMicroarch_Intel_Unknown,
195	/[133(0x85)] = / kCpumMicroarch_Intel_Phi_KnightsMill,
196	/[134(0x86)] = / kCpumMicroarch_Intel_Unknown,
197	/[135(0x87)] = / kCpumMicroarch_Intel_Unknown,
198	/[136(0x88)] = / kCpumMicroarch_Intel_Unknown,
199	/[137(0x89)] = / kCpumMicroarch_Intel_Unknown,
200	/[138(0x8a)] = / kCpumMicroarch_Intel_Unknown,
201	/[139(0x8b)] = / kCpumMicroarch_Intel_Unknown,
202	/[140(0x8c)] = / kCpumMicroarch_Intel_Core7_TigerLake, /* 11th Gen Intel(R) Core(TM) i7-1185G7 @ 3.00GHz (bird) */
203	/[141(0x8d)] = / kCpumMicroarch_Intel_Core7_TigerLake, /* unconfirmed */
204	/[142(0x8e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping >= 0xB is Whiskey Lake, 0xA is CoffeeLake. */
205	/[143(0x8f)] = / kCpumMicroarch_Intel_Core7_SapphireRapids,
206	/[144(0x90)] = / kCpumMicroarch_Intel_Unknown,
207	/[145(0x91)] = / kCpumMicroarch_Intel_Unknown,
208	/[146(0x92)] = / kCpumMicroarch_Intel_Unknown,
209	/[147(0x93)] = / kCpumMicroarch_Intel_Unknown,
210	/[148(0x94)] = / kCpumMicroarch_Intel_Unknown,
211	/[149(0x95)] = / kCpumMicroarch_Intel_Unknown,
212	/[150(0x96)] = / kCpumMicroarch_Intel_Unknown,
213	/[151(0x97)] = / kCpumMicroarch_Intel_Core7_AlderLake, /* unconfirmed, unreleased */
214	/[152(0x98)] = / kCpumMicroarch_Intel_Unknown,
215	/[153(0x99)] = / kCpumMicroarch_Intel_Unknown,
216	/[154(0x9a)] = / kCpumMicroarch_Intel_Core7_AlderLake, /* unconfirmed, unreleased */
217	/[155(0x9b)] = / kCpumMicroarch_Intel_Unknown,
218	/[156(0x9c)] = / kCpumMicroarch_Intel_Unknown,
219	/[157(0x9d)] = / kCpumMicroarch_Intel_Unknown,
220	/[158(0x9e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping >= 0xB is Whiskey Lake, 0xA is CoffeeLake. */
221	/[159(0x9f)] = / kCpumMicroarch_Intel_Unknown,
222	/[160(0xa0)] = / kCpumMicroarch_Intel_Unknown,
223	/[161(0xa1)] = / kCpumMicroarch_Intel_Unknown,
224	/[162(0xa2)] = / kCpumMicroarch_Intel_Unknown,
225	/[163(0xa3)] = / kCpumMicroarch_Intel_Unknown,
226	/[164(0xa4)] = / kCpumMicroarch_Intel_Unknown,
227	/[165(0xa5)] = / kCpumMicroarch_Intel_Core7_CometLake, /* unconfirmed */
228	/[166(0xa6)] = / kCpumMicroarch_Intel_Unknown,
229	/[167(0xa7)] = / kCpumMicroarch_Intel_Core7_CypressCove, /* 14nm backport, unconfirmed */
230	};
231	AssertCompile(RT_ELEMENTS(g_aenmIntelFamily06) == 0xa7+1);
232
233
234	/**
235	* Figures out the (sub-)micro architecture given a bit of CPUID info.
236	*
237	* @returns Micro architecture.
238	* @param enmVendor The CPU vendor.
239	* @param bFamily The CPU family.
240	* @param bModel The CPU model.
241	* @param bStepping The CPU stepping.
242	*/
243	VMMDECL(CPUMMICROARCH) CPUMCpuIdDetermineX86MicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
244	uint8_t bModel, uint8_t bStepping)
245	{
246	if (enmVendor == CPUMCPUVENDOR_AMD)
247	{
248	switch (bFamily)
249	{
250	case 0x02: return kCpumMicroarch_AMD_Am286; /* Not really kosher... */
251	case 0x03: return kCpumMicroarch_AMD_Am386;
252	case 0x23: return kCpumMicroarch_AMD_Am386; /* SX*/
253	case 0x04: return bModel < 14 ? kCpumMicroarch_AMD_Am486 : kCpumMicroarch_AMD_Am486Enh;
254	case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
255	case 0x06:
256	switch (bModel)
257	{
258	case 0: return kCpumMicroarch_AMD_K7_Palomino;
259	case 1: return kCpumMicroarch_AMD_K7_Palomino;
260	case 2: return kCpumMicroarch_AMD_K7_Palomino;
261	case 3: return kCpumMicroarch_AMD_K7_Spitfire;
262	case 4: return kCpumMicroarch_AMD_K7_Thunderbird;
263	case 6: return kCpumMicroarch_AMD_K7_Palomino;
264	case 7: return kCpumMicroarch_AMD_K7_Morgan;
265	case 8: return kCpumMicroarch_AMD_K7_Thoroughbred;
266	case 10: return kCpumMicroarch_AMD_K7_Barton; /* Thorton too. */
267	}
268	return kCpumMicroarch_AMD_K7_Unknown;
269	case 0x0f:
270	/*
271	* This family is a friggin mess. Trying my best to make some
272	* sense out of it. Too much happened in the 0x0f family to
273	* lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
274	*
275	* Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
276	* cpu-world.com, and other places:
277	* - 130nm:
278	* - ClawHammer: F7A/SH-CG, F5A/-CG, F4A/-CG, F50/-B0, F48/-C0, F58/-C0,
279	* - SledgeHammer: F50/SH-B0, F48/-C0, F58/-C0, F4A/-CG, F5A/-CG, F7A/-CG, F51/-B3
280	* - Newcastle: FC0/DH-CG (erratum #180: FE0/DH-CG), FF0/DH-CG
281	* - Dublin: FC0/-CG, FF0/-CG, F82/CH-CG, F4A/-CG, F48/SH-C0,
282	* - Odessa: FC0/DH-CG (erratum #180: FE0/DH-CG)
283	* - Paris: FF0/DH-CG, FC0/DH-CG (erratum #180: FE0/DH-CG),
284	* - 90nm:
285	* - Winchester: 10FF0/DH-D0, 20FF0/DH-E3.
286	* - Oakville: 10FC0/DH-D0.
287	* - Georgetown: 10FC0/DH-D0.
288	* - Sonora: 10FC0/DH-D0.
289	* - Venus: 20F71/SH-E4
290	* - Troy: 20F51/SH-E4
291	* - Athens: 20F51/SH-E4
292	* - San Diego: 20F71/SH-E4.
293	* - Lancaster: 20F42/SH-E5
294	* - Newark: 20F42/SH-E5.
295	* - Albany: 20FC2/DH-E6.
296	* - Roma: 20FC2/DH-E6.
297	* - Venice: 20FF0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6.
298	* - Palermo: 10FC0/DH-D0, 20FF0/DH-E3, 20FC0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6
299	* - 90nm introducing Dual core:
300	* - Denmark: 20F30/JH-E1, 20F32/JH-E6
301	* - Italy: 20F10/JH-E1, 20F12/JH-E6
302	* - Egypt: 20F10/JH-E1, 20F12/JH-E6
303	* - Toledo: 20F32/JH-E6, 30F72/DH-E6 (single code variant).
304	* - Manchester: 20FB1/BH-E4, 30FF2/BH-E4.
305	* - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheaper models):
306	* - Santa Ana: 40F32/JH-F2, /-F3
307	* - Santa Rosa: 40F12/JH-F2, 40F13/JH-F3
308	* - Windsor: 40F32/JH-F2, 40F33/JH-F3, C0F13/JH-F3, 40FB2/BH-F2, ??20FB1/BH-E4??.
309	* - Manila: 50FF2/DH-F2, 40FF2/DH-F2
310	* - Orleans: 40FF2/DH-F2, 50FF2/DH-F2, 50FF3/DH-F3.
311	* - Keene: 40FC2/DH-F2.
312	* - Richmond: 40FC2/DH-F2
313	* - Taylor: 40F82/BH-F2
314	* - Trinidad: 40F82/BH-F2
315	*
316	* - 65nm:
317	* - Brisbane: 60FB1/BH-G1, 60FB2/BH-G2.
318	* - Tyler: 60F81/BH-G1, 60F82/BH-G2.
319	* - Sparta: 70FF1/DH-G1, 70FF2/DH-G2.
320	* - Lima: 70FF1/DH-G1, 70FF2/DH-G2.
321	* - Sherman: /-G1, 70FC2/DH-G2.
322	* - Huron: 70FF2/DH-G2.
323	*/
324	if (bModel < 0x10)
325	return kCpumMicroarch_AMD_K8_130nm;
326	if (bModel >= 0x60 && bModel < 0x80)
327	return kCpumMicroarch_AMD_K8_65nm;
328	if (bModel >= 0x40)
329	return kCpumMicroarch_AMD_K8_90nm_AMDV;
330	switch (bModel)
331	{
332	case 0x21:
333	case 0x23:
334	case 0x2b:
335	case 0x2f:
336	case 0x37:
337	case 0x3f:
338	return kCpumMicroarch_AMD_K8_90nm_DualCore;
339	}
340	return kCpumMicroarch_AMD_K8_90nm;
341	case 0x10:
342	return kCpumMicroarch_AMD_K10;
343	case 0x11:
344	return kCpumMicroarch_AMD_K10_Lion;
345	case 0x12:
346	return kCpumMicroarch_AMD_K10_Llano;
347	case 0x14:
348	return kCpumMicroarch_AMD_Bobcat;
349	case 0x15:
350	switch (bModel)
351	{
352	case 0x00: return kCpumMicroarch_AMD_15h_Bulldozer; /* Any? prerelease? */
353	case 0x01: return kCpumMicroarch_AMD_15h_Bulldozer; /* Opteron 4200, FX-81xx. */
354	case 0x02: return kCpumMicroarch_AMD_15h_Piledriver; /* Opteron 4300, FX-83xx. */
355	case 0x10: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-5800K for e.g. */
356	case 0x11: /* ?? */
357	case 0x12: /* ?? */
358	case 0x13: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-6800K for e.g. */
359	}
360	return kCpumMicroarch_AMD_15h_Unknown;
361	case 0x16:
362	return kCpumMicroarch_AMD_Jaguar;
363	case 0x17:
364	return kCpumMicroarch_AMD_Zen_Ryzen;
365	}
366	return kCpumMicroarch_AMD_Unknown;
367	}
368
369	if (enmVendor == CPUMCPUVENDOR_INTEL)
370	{
371	switch (bFamily)
372	{
373	case 3:
374	return kCpumMicroarch_Intel_80386;
375	case 4:
376	return kCpumMicroarch_Intel_80486;
377	case 5:
378	return kCpumMicroarch_Intel_P5;
379	case 6:
380	if (bModel < RT_ELEMENTS(g_aenmIntelFamily06))
381	{
382	CPUMMICROARCH enmMicroArch = g_aenmIntelFamily06[bModel];
383	if (enmMicroArch == kCpumMicroarch_Intel_Core7_KabyLake)
384	{
385	if (bStepping >= 0xa && bStepping <= 0xc)
386	enmMicroArch = kCpumMicroarch_Intel_Core7_CoffeeLake;
387	else if (bStepping >= 0xc)
388	enmMicroArch = kCpumMicroarch_Intel_Core7_WhiskeyLake;
389	}
390	else if ( enmMicroArch == kCpumMicroarch_Intel_Core7_Skylake
391	&& bModel == 0x55
392	&& bStepping >= 5)
393	enmMicroArch = kCpumMicroarch_Intel_Core7_CascadeLake;
394	return enmMicroArch;
395	}
396	return kCpumMicroarch_Intel_Atom_Unknown;
397	case 15:
398	switch (bModel)
399	{
400	case 0: return kCpumMicroarch_Intel_NB_Willamette;
401	case 1: return kCpumMicroarch_Intel_NB_Willamette;
402	case 2: return kCpumMicroarch_Intel_NB_Northwood;
403	case 3: return kCpumMicroarch_Intel_NB_Prescott;
404	case 4: return kCpumMicroarch_Intel_NB_Prescott2M; /* ?? */
405	case 5: return kCpumMicroarch_Intel_NB_Unknown; /??/
406	case 6: return kCpumMicroarch_Intel_NB_CedarMill;
407	case 7: return kCpumMicroarch_Intel_NB_Gallatin;
408	default: return kCpumMicroarch_Intel_NB_Unknown;
409	}
410	break;
411	/* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
412	case 0:
413	return kCpumMicroarch_Intel_8086;
414	case 1:
415	return kCpumMicroarch_Intel_80186;
416	case 2:
417	return kCpumMicroarch_Intel_80286;
418	}
419	return kCpumMicroarch_Intel_Unknown;
420	}
421
422	if (enmVendor == CPUMCPUVENDOR_VIA)
423	{
424	switch (bFamily)
425	{
426	case 5:
427	switch (bModel)
428	{
429	case 1: return kCpumMicroarch_Centaur_C6;
430	case 4: return kCpumMicroarch_Centaur_C6;
431	case 8: return kCpumMicroarch_Centaur_C2;
432	case 9: return kCpumMicroarch_Centaur_C3;
433	}
434	break;
435
436	case 6:
437	switch (bModel)
438	{
439	case 5: return kCpumMicroarch_VIA_C3_M2;
440	case 6: return kCpumMicroarch_VIA_C3_C5A;
441	case 7: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5B : kCpumMicroarch_VIA_C3_C5C;
442	case 8: return kCpumMicroarch_VIA_C3_C5N;
443	case 9: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5XL : kCpumMicroarch_VIA_C3_C5P;
444	case 10: return kCpumMicroarch_VIA_C7_C5J;
445	case 15: return kCpumMicroarch_VIA_Isaiah;
446	}
447	break;
448	}
449	return kCpumMicroarch_VIA_Unknown;
450	}
451
452	if (enmVendor == CPUMCPUVENDOR_SHANGHAI)
453	{
454	switch (bFamily)
455	{
456	case 6:
457	case 7:
458	return kCpumMicroarch_Shanghai_Wudaokou;
459	default:
460	break;
461	}
462	return kCpumMicroarch_Shanghai_Unknown;
463	}
464
465	if (enmVendor == CPUMCPUVENDOR_CYRIX)
466	{
467	switch (bFamily)
468	{
469	case 4:
470	switch (bModel)
471	{
472	case 9: return kCpumMicroarch_Cyrix_5x86;
473	}
474	break;
475
476	case 5:
477	switch (bModel)
478	{
479	case 2: return kCpumMicroarch_Cyrix_M1;
480	case 4: return kCpumMicroarch_Cyrix_MediaGX;
481	case 5: return kCpumMicroarch_Cyrix_MediaGXm;
482	}
483	break;
484
485	case 6:
486	switch (bModel)
487	{
488	case 0: return kCpumMicroarch_Cyrix_M2;
489	}
490	break;
491
492	}
493	return kCpumMicroarch_Cyrix_Unknown;
494	}
495
496	if (enmVendor == CPUMCPUVENDOR_HYGON)
497	{
498	switch (bFamily)
499	{
500	case 0x18:
501	return kCpumMicroarch_Hygon_Dhyana;
502	default:
503	break;
504	}
505	return kCpumMicroarch_Hygon_Unknown;
506	}
507
508	return kCpumMicroarch_Unknown;
509	}
510
511	#endif /* if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64) \|\| defined(VBOX_VMM_TARGET_X86) */
512
513
514
515	/**
516	* Translates a microarchitecture enum value to the corresponding string
517	* constant.
518	*
519	* @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
520	* NULL if the value is invalid.
521	*
522	* @param enmMicroarch The enum value to convert.
523	*/
524	VMMDECL(const char *) CPUMMicroarchName(CPUMMICROARCH enmMicroarch)
525	{
526	switch (enmMicroarch)
527	{
528	#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("kCpumMicroarch_") - 1)
529	CASE_RET_STR(kCpumMicroarch_Intel_8086);
530	CASE_RET_STR(kCpumMicroarch_Intel_80186);
531	CASE_RET_STR(kCpumMicroarch_Intel_80286);
532	CASE_RET_STR(kCpumMicroarch_Intel_80386);
533	CASE_RET_STR(kCpumMicroarch_Intel_80486);
534	CASE_RET_STR(kCpumMicroarch_Intel_P5);
535
536	CASE_RET_STR(kCpumMicroarch_Intel_P6);
537	CASE_RET_STR(kCpumMicroarch_Intel_P6_II);
538	CASE_RET_STR(kCpumMicroarch_Intel_P6_III);
539
540	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Banias);
541	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Dothan);
542	CASE_RET_STR(kCpumMicroarch_Intel_Core_Yonah);
543
544	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Merom);
545	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Penryn);
546
547	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Nehalem);
548	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Westmere);
549	CASE_RET_STR(kCpumMicroarch_Intel_Core7_SandyBridge);
550	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IvyBridge);
551	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Haswell);
552	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Broadwell);
553	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Skylake);
554	CASE_RET_STR(kCpumMicroarch_Intel_Core7_KabyLake);
555	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CoffeeLake);
556	CASE_RET_STR(kCpumMicroarch_Intel_Core7_WhiskeyLake);
557	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CascadeLake);
558	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CannonLake);
559	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CometLake);
560	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IceLake);
561	CASE_RET_STR(kCpumMicroarch_Intel_Core7_RocketLake);
562	CASE_RET_STR(kCpumMicroarch_Intel_Core7_TigerLake);
563	CASE_RET_STR(kCpumMicroarch_Intel_Core7_AlderLake);
564	CASE_RET_STR(kCpumMicroarch_Intel_Core7_SapphireRapids);
565
566	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Bonnell);
567	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Lincroft);
568	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Saltwell);
569	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Silvermont);
570	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Airmount);
571	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Goldmont);
572	CASE_RET_STR(kCpumMicroarch_Intel_Atom_GoldmontPlus);
573	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Unknown);
574
575	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsFerry);
576	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsCorner);
577	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsLanding);
578	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsHill);
579	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsMill);
580
581	CASE_RET_STR(kCpumMicroarch_Intel_NB_Willamette);
582	CASE_RET_STR(kCpumMicroarch_Intel_NB_Northwood);
583	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott);
584	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott2M);
585	CASE_RET_STR(kCpumMicroarch_Intel_NB_CedarMill);
586	CASE_RET_STR(kCpumMicroarch_Intel_NB_Gallatin);
587	CASE_RET_STR(kCpumMicroarch_Intel_NB_Unknown);
588
589	CASE_RET_STR(kCpumMicroarch_Intel_Unknown);
590
591	CASE_RET_STR(kCpumMicroarch_AMD_Am286);
592	CASE_RET_STR(kCpumMicroarch_AMD_Am386);
593	CASE_RET_STR(kCpumMicroarch_AMD_Am486);
594	CASE_RET_STR(kCpumMicroarch_AMD_Am486Enh);
595	CASE_RET_STR(kCpumMicroarch_AMD_K5);
596	CASE_RET_STR(kCpumMicroarch_AMD_K6);
597
598	CASE_RET_STR(kCpumMicroarch_AMD_K7_Palomino);
599	CASE_RET_STR(kCpumMicroarch_AMD_K7_Spitfire);
600	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thunderbird);
601	CASE_RET_STR(kCpumMicroarch_AMD_K7_Morgan);
602	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thoroughbred);
603	CASE_RET_STR(kCpumMicroarch_AMD_K7_Barton);
604	CASE_RET_STR(kCpumMicroarch_AMD_K7_Unknown);
605
606	CASE_RET_STR(kCpumMicroarch_AMD_K8_130nm);
607	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm);
608	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_DualCore);
609	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_AMDV);
610	CASE_RET_STR(kCpumMicroarch_AMD_K8_65nm);
611
612	CASE_RET_STR(kCpumMicroarch_AMD_K10);
613	CASE_RET_STR(kCpumMicroarch_AMD_K10_Lion);
614	CASE_RET_STR(kCpumMicroarch_AMD_K10_Llano);
615	CASE_RET_STR(kCpumMicroarch_AMD_Bobcat);
616	CASE_RET_STR(kCpumMicroarch_AMD_Jaguar);
617
618	CASE_RET_STR(kCpumMicroarch_AMD_15h_Bulldozer);
619	CASE_RET_STR(kCpumMicroarch_AMD_15h_Piledriver);
620	CASE_RET_STR(kCpumMicroarch_AMD_15h_Steamroller);
621	CASE_RET_STR(kCpumMicroarch_AMD_15h_Excavator);
622	CASE_RET_STR(kCpumMicroarch_AMD_15h_Unknown);
623
624	CASE_RET_STR(kCpumMicroarch_AMD_16h_First);
625
626	CASE_RET_STR(kCpumMicroarch_AMD_Zen_Ryzen);
627
628	CASE_RET_STR(kCpumMicroarch_AMD_Unknown);
629
630	CASE_RET_STR(kCpumMicroarch_Hygon_Dhyana);
631	CASE_RET_STR(kCpumMicroarch_Hygon_Unknown);
632
633	CASE_RET_STR(kCpumMicroarch_Centaur_C6);
634	CASE_RET_STR(kCpumMicroarch_Centaur_C2);
635	CASE_RET_STR(kCpumMicroarch_Centaur_C3);
636	CASE_RET_STR(kCpumMicroarch_VIA_C3_M2);
637	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5A);
638	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5B);
639	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5C);
640	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5N);
641	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5XL);
642	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5P);
643	CASE_RET_STR(kCpumMicroarch_VIA_C7_C5J);
644	CASE_RET_STR(kCpumMicroarch_VIA_Isaiah);
645	CASE_RET_STR(kCpumMicroarch_VIA_Unknown);
646
647	CASE_RET_STR(kCpumMicroarch_Shanghai_Wudaokou);
648	CASE_RET_STR(kCpumMicroarch_Shanghai_Unknown);
649
650	CASE_RET_STR(kCpumMicroarch_Cyrix_5x86);
651	CASE_RET_STR(kCpumMicroarch_Cyrix_M1);
652	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGX);
653	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGXm);
654	CASE_RET_STR(kCpumMicroarch_Cyrix_M2);
655	CASE_RET_STR(kCpumMicroarch_Cyrix_Unknown);
656
657	CASE_RET_STR(kCpumMicroarch_NEC_V20);
658	CASE_RET_STR(kCpumMicroarch_NEC_V30);
659
660	CASE_RET_STR(kCpumMicroarch_Apple_M1);
661	CASE_RET_STR(kCpumMicroarch_Apple_M2);
662
663	CASE_RET_STR(kCpumMicroarch_Unknown);
664
665	#undef CASE_RET_STR
666	case kCpumMicroarch_Invalid:
667	case kCpumMicroarch_Intel_End:
668	case kCpumMicroarch_Intel_Core2_End:
669	case kCpumMicroarch_Intel_Core7_End:
670	case kCpumMicroarch_Intel_Atom_End:
671	case kCpumMicroarch_Intel_P6_Core_Atom_End:
672	case kCpumMicroarch_Intel_Phi_End:
673	case kCpumMicroarch_Intel_NB_End:
674	case kCpumMicroarch_AMD_K7_End:
675	case kCpumMicroarch_AMD_K8_End:
676	case kCpumMicroarch_AMD_15h_End:
677	case kCpumMicroarch_AMD_16h_End:
678	case kCpumMicroarch_AMD_Zen_End:
679	case kCpumMicroarch_AMD_End:
680	case kCpumMicroarch_Hygon_End:
681	case kCpumMicroarch_VIA_End:
682	case kCpumMicroarch_Shanghai_End:
683	case kCpumMicroarch_Cyrix_End:
684	case kCpumMicroarch_NEC_End:
685	case kCpumMicroarch_Apple_End:
686	case kCpumMicroarch_32BitHack:
687	break;
688	/* no default! */
689	}
690
691	return NULL;
692	}
693
694	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64) \|\| defined(VBOX_VMM_TARGET_X86)
695
696	/**
697	* Gets a matching leaf in the CPUID leaf array.
698	*
699	* @returns Pointer to the matching leaf, or NULL if not found.
700	* @param paLeaves The CPUID leaves to search. This is sorted.
701	* @param cLeaves The number of leaves in the array.
702	* @param uLeaf The leaf to locate.
703	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
704	*/
705	PCPUMCPUIDLEAF cpumCpuIdGetLeafInt(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
706	{
707	/* Lazy bird does linear lookup here since this is only used for the
708	occational CPUID overrides. */
709	for (uint32_t i = 0; i < cLeaves; i++)
710	if ( paLeaves[i].uLeaf == uLeaf
711	&& paLeaves[i].uSubLeaf == (uSubLeaf & paLeaves[i].fSubLeafMask))
712	return &paLeaves[i];
713	return NULL;
714	}
715
716
717	/**
718	* Ensures that the CPUID leaf array can hold one more leaf.
719	*
720	* @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
721	* failure.
722	* @param pVM The cross context VM structure. If NULL, use
723	* the process heap, otherwise the VM's hyper heap.
724	* @param ppaLeaves Pointer to the variable holding the array pointer
725	* (input/output).
726	* @param cLeaves The current array size.
727	*
728	* @remarks This function will automatically update the R0 and RC pointers when
729	* using the hyper heap, which means @a ppaLeaves and @a cLeaves must
730	* be the corresponding VM's CPUID arrays (which is asserted).
731	*/
732	PCPUMCPUIDLEAF cpumCpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves)
733	{
734	/*
735	* If pVM is not specified, we're on the regular heap and can waste a
736	* little space to speed things up.
737	*/
738	uint32_t cAllocated;
739	if (!pVM)
740	{
741	cAllocated = RT_ALIGN(cLeaves, 16);
742	if (cLeaves + 1 > cAllocated)
743	{
744	void pvNew = RTMemRealloc(ppaLeaves, (cAllocated + 16) * sizeof(**ppaLeaves));
745	if (pvNew)
746	*ppaLeaves = (PCPUMCPUIDLEAF)pvNew;
747	else
748	{
749	RTMemFree(*ppaLeaves);
750	*ppaLeaves = NULL;
751	}
752	}
753	}
754	/*
755	* Otherwise, we're on the hyper heap and are probably just inserting
756	* one or two leaves and should conserve space.
757	*/
758	else
759	{
760	# ifdef IN_VBOX_CPU_REPORT
761	AssertReleaseFailed();
762	# else
763	# ifdef IN_RING3
764	Assert(ppaLeaves == &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
765	Assert(*ppaLeaves == pVM->cpum.s.GuestInfo.aCpuIdLeaves);
766	Assert(cLeaves == pVM->cpum.s.GuestInfo.cCpuIdLeaves);
767
768	if (cLeaves + 1 <= RT_ELEMENTS(pVM->cpum.s.GuestInfo.aCpuIdLeaves))
769	{ }
770	else
771	# endif
772	{
773	*ppaLeaves = NULL;
774	LogRel(("CPUM: cpumR3CpuIdEnsureSpace: Out of CPUID space!\n"));
775	}
776	# endif
777	}
778	return *ppaLeaves;
779	}
780
781
782	# ifdef VBOX_STRICT
783	/**
784	* Checks that we've updated the CPUID leaves array correctly.
785	*
786	* This is a no-op in non-strict builds.
787	*
788	* @param paLeaves The leaves array.
789	* @param cLeaves The number of leaves.
790	*/
791	void cpumCpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
792	{
793	for (uint32_t i = 1; i < cLeaves; i++)
794	if (paLeaves[i].uLeaf != paLeaves[i - 1].uLeaf)
795	AssertMsg(paLeaves[i].uLeaf > paLeaves[i - 1].uLeaf, ("%#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i - 1].uLeaf));
796	else
797	{
798	AssertMsg(paLeaves[i].uSubLeaf > paLeaves[i - 1].uSubLeaf,
799	("%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i - 1].uSubLeaf));
800	AssertMsg(paLeaves[i].fSubLeafMask == paLeaves[i - 1].fSubLeafMask,
801	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fSubLeafMask, paLeaves[i - 1].fSubLeafMask));
802	AssertMsg(paLeaves[i].fFlags == paLeaves[i - 1].fFlags,
803	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fFlags, paLeaves[i - 1].fFlags));
804	}
805	}
806	# endif
807
808	#endif /* defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64) \|\| defined(VBOX_VMM_TARGET_X86) */
809
810	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
811
812	/**
813	* Append a CPUID leaf or sub-leaf.
814	*
815	* ASSUMES linear insertion order, so we'll won't need to do any searching or
816	* replace anything. Use cpumR3CpuIdInsert() for those cases.
817	*
818	* @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
819	* the caller need do no more work.
820	* @param ppaLeaves Pointer to the pointer to the array of sorted
821	* CPUID leaves and sub-leaves.
822	* @param pcLeaves Where we keep the leaf count for *ppaLeaves.
823	* @param uLeaf The leaf we're adding.
824	* @param uSubLeaf The sub-leaf number.
825	* @param fSubLeafMask The sub-leaf mask.
826	* @param uEax The EAX value.
827	* @param uEbx The EBX value.
828	* @param uEcx The ECX value.
829	* @param uEdx The EDX value.
830	* @param fFlags The flags.
831	*/
832	static int cpumCollectCpuIdInfoAddOne(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves,
833	uint32_t uLeaf, uint32_t uSubLeaf, uint32_t fSubLeafMask,
834	uint32_t uEax, uint32_t uEbx, uint32_t uEcx, uint32_t uEdx, uint32_t fFlags)
835	{
836	if (!cpumCpuIdEnsureSpace(NULL /* pVM /, ppaLeaves, pcLeaves))
837	return VERR_NO_MEMORY;
838
839	PCPUMCPUIDLEAF pNew = &(ppaLeaves)[pcLeaves];
840	Assert( *pcLeaves == 0
841	\|\| pNew[-1].uLeaf < uLeaf
842	\|\| (pNew[-1].uLeaf == uLeaf && pNew[-1].uSubLeaf < uSubLeaf) );
843
844	pNew->uLeaf = uLeaf;
845	pNew->uSubLeaf = uSubLeaf;
846	pNew->fSubLeafMask = fSubLeafMask;
847	pNew->uEax = uEax;
848	pNew->uEbx = uEbx;
849	pNew->uEcx = uEcx;
850	pNew->uEdx = uEdx;
851	pNew->fFlags = fFlags;
852
853	*pcLeaves += 1;
854	return VINF_SUCCESS;
855	}
856
857
858	/**
859	* Checks if ECX make a difference when reading a given CPUID leaf.
860	*
861	* @returns @c true if it does, @c false if it doesn't.
862	* @param uLeaf The leaf we're reading.
863	* @param pcSubLeaves Number of sub-leaves accessible via ECX.
864	* @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
865	* final sub-leaf (for leaf 0xb only).
866	*/
867	static bool cpumIsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t pcSubLeaves, bool pfFinalEcxUnchanged)
868	{
869	*pfFinalEcxUnchanged = false;
870
871	uint32_t auCur[4];
872	uint32_t auPrev[4];
873	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auPrev[0], &auPrev[1], &auPrev[2], &auPrev[3]);
874
875	/* Look for sub-leaves. */
876	uint32_t uSubLeaf = 1;
877	for (;;)
878	{
879	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
880	if (memcmp(auCur, auPrev, sizeof(auCur)))
881	break;
882
883	/* Advance / give up. */
884	uSubLeaf++;
885	if (uSubLeaf >= 64)
886	{
887	*pcSubLeaves = 1;
888	return false;
889	}
890	}
891
892	/* Count sub-leaves. */
893	uint32_t cMinLeaves = uLeaf == 0xd ? 64 : 0;
894	uint32_t cRepeats = 0;
895	uSubLeaf = 0;
896	for (;;)
897	{
898	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
899
900	/* Figuring out when to stop isn't entirely straight forward as we need
901	to cover undocumented behavior up to a point and implementation shortcuts. */
902
903	/* 1. Look for more than 4 repeating value sets. */
904	if ( auCur[0] == auPrev[0]
905	&& auCur[1] == auPrev[1]
906	&& ( auCur[2] == auPrev[2]
907	\|\| ( auCur[2] == uSubLeaf
908	&& auPrev[2] == uSubLeaf - 1) )
909	&& auCur[3] == auPrev[3])
910	{
911	if ( uLeaf != 0xd
912	\|\| uSubLeaf >= 64
913	\|\| ( auCur[0] == 0
914	&& auCur[1] == 0
915	&& auCur[2] == 0
916	&& auCur[3] == 0
917	&& auPrev[2] == 0) )
918	cRepeats++;
919	if (cRepeats > 4 && uSubLeaf >= cMinLeaves)
920	break;
921	}
922	else
923	cRepeats = 0;
924
925	/* 2. Look for zero values. */
926	if ( auCur[0] == 0
927	&& auCur[1] == 0
928	&& (auCur[2] == 0 \|\| auCur[2] == uSubLeaf)
929	&& (auCur[3] == 0 \|\| uLeaf == 0xb /* edx is fixed */)
930	&& uSubLeaf >= cMinLeaves)
931	{
932	cRepeats = 0;
933	break;
934	}
935
936	/* 3. Leaf 0xb level type 0 check. */
937	if ( uLeaf == 0xb
938	&& (auCur[2] & 0xff00) == 0
939	&& (auPrev[2] & 0xff00) == 0)
940	{
941	cRepeats = 0;
942	break;
943	}
944
945	/* 99. Give up. */
946	if (uSubLeaf >= 128)
947	{
948	# ifndef IN_VBOX_CPU_REPORT
949	/* Ok, limit it according to the documentation if possible just to
950	avoid annoying users with these detection issues. */
951	uint32_t cDocLimit = UINT32_MAX;
952	if (uLeaf == 0x4)
953	cDocLimit = 4;
954	else if (uLeaf == 0x7)
955	cDocLimit = 1;
956	else if (uLeaf == 0xd)
957	cDocLimit = 63;
958	else if (uLeaf == 0xf)
959	cDocLimit = 2;
960	if (cDocLimit != UINT32_MAX)
961	{
962	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
963	*pcSubLeaves = cDocLimit + 3;
964	return true;
965	}
966	# endif
967	*pcSubLeaves = UINT32_MAX;
968	return true;
969	}
970
971	/* Advance. */
972	uSubLeaf++;
973	memcpy(auPrev, auCur, sizeof(auCur));
974	}
975
976	/* Standard exit. */
977	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
978	*pcSubLeaves = uSubLeaf + 1 - cRepeats;
979	if (*pcSubLeaves == 0)
980	*pcSubLeaves = 1;
981	return true;
982	}
983
984
985	/**
986	* Collects CPUID leaves and sub-leaves, returning a sorted array of them.
987	*
988	* @returns VBox status code.
989	* @param ppaLeaves Where to return the array pointer on success.
990	* Use RTMemFree to release.
991	* @param pcLeaves Where to return the size of the array on
992	* success.
993	*/
994	VMMDECL(int) CPUMCpuIdCollectLeavesFromX86Host(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
995	{
996	*ppaLeaves = NULL;
997	*pcLeaves = 0;
998
999	/*
1000	* Try out various candidates. This must be sorted!
1001	*/
1002	static struct { uint32_t uMsr; bool fSpecial; } const s_aCandidates[] =
1003	{
1004	{ UINT32_C(0x00000000), false },
1005	{ UINT32_C(0x10000000), false },
1006	{ UINT32_C(0x20000000), false },
1007	{ UINT32_C(0x30000000), false },
1008	{ UINT32_C(0x40000000), false },
1009	{ UINT32_C(0x50000000), false },
1010	{ UINT32_C(0x60000000), false },
1011	{ UINT32_C(0x70000000), false },
1012	{ UINT32_C(0x80000000), false },
1013	{ UINT32_C(0x80860000), false },
1014	{ UINT32_C(0x8ffffffe), true },
1015	{ UINT32_C(0x8fffffff), true },
1016	{ UINT32_C(0x90000000), false },
1017	{ UINT32_C(0xa0000000), false },
1018	{ UINT32_C(0xb0000000), false },
1019	{ UINT32_C(0xc0000000), false },
1020	{ UINT32_C(0xd0000000), false },
1021	{ UINT32_C(0xe0000000), false },
1022	{ UINT32_C(0xf0000000), false },
1023	};
1024
1025	for (uint32_t iOuter = 0; iOuter < RT_ELEMENTS(s_aCandidates); iOuter++)
1026	{
1027	uint32_t uLeaf = s_aCandidates[iOuter].uMsr;
1028	uint32_t uEax, uEbx, uEcx, uEdx;
1029	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1030
1031	/*
1032	* Does EAX look like a typical leaf count value?
1033	*/
1034	if ( uEax > uLeaf
1035	&& uEax - uLeaf < UINT32_C(0xff)) /* Adjust 0xff limit when exceeded by real HW. */
1036	{
1037	/* Yes, dump them. */
1038	uint32_t cLeaves = uEax - uLeaf + 1;
1039	while (cLeaves-- > 0)
1040	{
1041	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1042
1043	uint32_t fFlags = 0;
1044
1045	/* There are currently three known leaves containing an APIC ID
1046	that needs EMT specific attention */
1047	if (uLeaf == 1)
1048	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1049	else if (uLeaf == 0xb && uEcx != 0)
1050	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1051	else if ( uLeaf == UINT32_C(0x8000001e)
1052	&& ( uEax
1053	\|\| uEbx
1054	\|\| uEdx
1055	\|\| RTX86IsAmdCpu((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)
1056	\|\| RTX86IsHygonCpu((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1057	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1058
1059	/* The APIC bit is per-VCpu and needs flagging. */
1060	if (uLeaf == 1)
1061	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1062	else if ( uLeaf == UINT32_C(0x80000001)
1063	&& ( (uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC)
1064	\|\| RTX86IsAmdCpu((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)
1065	\|\| RTX86IsHygonCpu((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1066	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1067
1068	/* Check three times here to reduce the chance of CPU migration
1069	resulting in false positives with things like the APIC ID. */
1070	uint32_t cSubLeaves;
1071	bool fFinalEcxUnchanged;
1072	if ( cpumIsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1073	&& cpumIsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1074	&& cpumIsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged))
1075	{
1076	if (cSubLeaves > (uLeaf == 0xd ? 68U : 16U))
1077	{
1078	/* This shouldn't happen. But in case it does, file all
1079	relevant details in the release log. */
1080	LogRel(("CPUM: VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES! uLeaf=%#x cSubLeaves=%#x\n", uLeaf, cSubLeaves));
1081	LogRel(("------------------ dump of problematic sub-leaves -----------------\n"));
1082	for (uint32_t uSubLeaf = 0; uSubLeaf < 128; uSubLeaf++)
1083	{
1084	uint32_t auTmp[4];
1085	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auTmp[0], &auTmp[1], &auTmp[2], &auTmp[3]);
1086	LogRel(("CPUM: %#010x, %#010x => %#010x %#010x %#010x %#010x\n",
1087	uLeaf, uSubLeaf, auTmp[0], auTmp[1], auTmp[2], auTmp[3]));
1088	}
1089	LogRel(("----------------- dump of what we've found so far -----------------\n"));
1090	for (uint32_t i = 0 ; i < *pcLeaves; i++)
1091	LogRel(("CPUM: %#010x, %#010x/%#010x => %#010x %#010x %#010x %#010x\n",
1092	(ppaLeaves)[i].uLeaf, (ppaLeaves)[i].uSubLeaf, (*ppaLeaves)[i].fSubLeafMask,
1093	(ppaLeaves)[i].uEax, (ppaLeaves)[i].uEbx, (ppaLeaves)[i].uEcx, (ppaLeaves)[i].uEdx));
1094	LogRel(("\nPlease create a defect on virtualbox.org and attach this log file!\n\n"));
1095	return VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES;
1096	}
1097
1098	if (fFinalEcxUnchanged)
1099	fFlags \|= CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES;
1100
1101	for (uint32_t uSubLeaf = 0; uSubLeaf < cSubLeaves; uSubLeaf++)
1102	{
1103	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &uEax, &uEbx, &uEcx, &uEdx);
1104	int rc = cpumCollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1105	uLeaf, uSubLeaf, UINT32_MAX, uEax, uEbx, uEcx, uEdx, fFlags);
1106	if (RT_FAILURE(rc))
1107	return rc;
1108	}
1109	}
1110	else
1111	{
1112	int rc = cpumCollectCpuIdInfoAddOne(ppaLeaves, pcLeaves, uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, fFlags);
1113	if (RT_FAILURE(rc))
1114	return rc;
1115	}
1116
1117	/* next */
1118	uLeaf++;
1119	}
1120	}
1121	/*
1122	* Special CPUIDs needs special handling as they don't follow the
1123	* leaf count principle used above.
1124	*/
1125	else if (s_aCandidates[iOuter].fSpecial)
1126	{
1127	bool fKeep = false;
1128	if (uLeaf == 0x8ffffffe && uEax == UINT32_C(0x00494544))
1129	fKeep = true;
1130	else if ( uLeaf == 0x8fffffff
1131	&& RT_C_IS_PRINT(RT_BYTE1(uEax))
1132	&& RT_C_IS_PRINT(RT_BYTE2(uEax))
1133	&& RT_C_IS_PRINT(RT_BYTE3(uEax))
1134	&& RT_C_IS_PRINT(RT_BYTE4(uEax))
1135	&& RT_C_IS_PRINT(RT_BYTE1(uEbx))
1136	&& RT_C_IS_PRINT(RT_BYTE2(uEbx))
1137	&& RT_C_IS_PRINT(RT_BYTE3(uEbx))
1138	&& RT_C_IS_PRINT(RT_BYTE4(uEbx))
1139	&& RT_C_IS_PRINT(RT_BYTE1(uEcx))
1140	&& RT_C_IS_PRINT(RT_BYTE2(uEcx))
1141	&& RT_C_IS_PRINT(RT_BYTE3(uEcx))
1142	&& RT_C_IS_PRINT(RT_BYTE4(uEcx))
1143	&& RT_C_IS_PRINT(RT_BYTE1(uEdx))
1144	&& RT_C_IS_PRINT(RT_BYTE2(uEdx))
1145	&& RT_C_IS_PRINT(RT_BYTE3(uEdx))
1146	&& RT_C_IS_PRINT(RT_BYTE4(uEdx)) )
1147	fKeep = true;
1148	if (fKeep)
1149	{
1150	int rc = cpumCollectCpuIdInfoAddOne(ppaLeaves, pcLeaves, uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
1151	if (RT_FAILURE(rc))
1152	return rc;
1153	}
1154	}
1155	}
1156
1157	# ifdef VBOX_STRICT
1158	cpumCpuIdAssertOrder(ppaLeaves, pcLeaves);
1159	# endif
1160	return VINF_SUCCESS;
1161	}
1162
1163	#endif /* RT_ARCH_X86 \|\| RT_ARCH_AMD64 */
1164
1165	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64) \|\| defined(VBOX_VMM_TARGET_X86)
1166	/**
1167	* Detect the CPU vendor give n the
1168	*
1169	* @returns The vendor.
1170	* @param uEAX EAX from CPUID(0).
1171	* @param uEBX EBX from CPUID(0).
1172	* @param uECX ECX from CPUID(0).
1173	* @param uEDX EDX from CPUID(0).
1174	*/
1175	VMMDECL(CPUMCPUVENDOR) CPUMCpuIdDetectX86VendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1176	{
1177	if (RTX86IsValidStdRange(uEAX))
1178	{
1179	if (RTX86IsAmdCpu(uEBX, uECX, uEDX))
1180	return CPUMCPUVENDOR_AMD;
1181
1182	if (RTX86IsIntelCpu(uEBX, uECX, uEDX))
1183	return CPUMCPUVENDOR_INTEL;
1184
1185	if (RTX86IsViaCentaurCpu(uEBX, uECX, uEDX))
1186	return CPUMCPUVENDOR_VIA;
1187
1188	if (RTX86IsShanghaiCpu(uEBX, uECX, uEDX))
1189	return CPUMCPUVENDOR_SHANGHAI;
1190
1191	if ( uEBX == UINT32_C(0x69727943) /* CyrixInstead */
1192	&& uECX == UINT32_C(0x64616574)
1193	&& uEDX == UINT32_C(0x736E4978))
1194	return CPUMCPUVENDOR_CYRIX;
1195
1196	if (RTX86IsHygonCpu(uEBX, uECX, uEDX))
1197	return CPUMCPUVENDOR_HYGON;
1198
1199	/* "Geode by NSC", example: family 5, model 9. */
1200
1201	/** @todo detect the other buggers... */
1202	}
1203
1204	return CPUMCPUVENDOR_UNKNOWN;
1205	}
1206	#endif /* defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64) \|\| defined(VBOX_VMM_TARGET_X86) */
1207
1208
1209	/**
1210	* Translates a CPU vendor enum value into the corresponding string constant.
1211	*
1212	* The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
1213	* value name. This can be useful when generating code.
1214	*
1215	* @returns Read only name string.
1216	* @param enmVendor The CPU vendor value.
1217	*/
1218	VMMDECL(const char *) CPUMCpuVendorName(CPUMCPUVENDOR enmVendor)
1219	{
1220	switch (enmVendor)
1221	{
1222	case CPUMCPUVENDOR_INTEL: return "INTEL";
1223	case CPUMCPUVENDOR_AMD: return "AMD";
1224	case CPUMCPUVENDOR_VIA: return "VIA";
1225	case CPUMCPUVENDOR_CYRIX: return "CYRIX";
1226	case CPUMCPUVENDOR_SHANGHAI: return "SHANGHAI";
1227	case CPUMCPUVENDOR_HYGON: return "HYGON";
1228	case CPUMCPUVENDOR_APPLE: return "APPLE";
1229	case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
1230
1231	case CPUMCPUVENDOR_INVALID:
1232	case CPUMCPUVENDOR_32BIT_HACK:
1233	break;
1234	}
1235	return "Invalid-cpu-vendor";
1236	}
1237
1238	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64) \|\| defined(VBOX_VMM_TARGET_X86)
1239
1240	static PCCPUMCPUIDLEAF cpumCpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
1241	{
1242	/* Could do binary search, doing linear now because I'm lazy. */
1243	PCCPUMCPUIDLEAF pLeaf = paLeaves;
1244	while (cLeaves-- > 0)
1245	{
1246	if (pLeaf->uLeaf == uLeaf)
1247	return pLeaf;
1248	pLeaf++;
1249	}
1250	return NULL;
1251	}
1252
1253
1254	static PCCPUMCPUIDLEAF cpumCpuIdFindLeafEx(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
1255	{
1256	PCCPUMCPUIDLEAF pLeaf = cpumCpuIdFindLeaf(paLeaves, cLeaves, uLeaf);
1257	if ( !pLeaf
1258	\|\| pLeaf->uSubLeaf != (uSubLeaf & pLeaf->fSubLeafMask))
1259	return pLeaf;
1260
1261	/* Linear sub-leaf search. Lazy as usual. */
1262	cLeaves -= pLeaf - paLeaves;
1263	while ( cLeaves-- > 0
1264	&& pLeaf->uLeaf == uLeaf)
1265	{
1266	if (pLeaf->uSubLeaf == (uSubLeaf & pLeaf->fSubLeafMask))
1267	return pLeaf;
1268	pLeaf++;
1269	}
1270
1271	return NULL;
1272	}
1273
1274
1275	static void cpumExplodeVmxFeatures(PCVMXMSRS pVmxMsrs, CPUMFEATURESX86 *pFeatures)
1276	{
1277	Assert(pVmxMsrs);
1278	Assert(pFeatures);
1279	Assert(pFeatures->fVmx);
1280
1281	/* Basic information. */
1282	bool const fVmxTrueMsrs = RT_BOOL(pVmxMsrs->u64Basic & VMX_BF_BASIC_TRUE_CTLS_MASK);
1283	{
1284	uint64_t const u64Basic = pVmxMsrs->u64Basic;
1285	pFeatures->fVmxInsOutInfo = RT_BF_GET(u64Basic, VMX_BF_BASIC_VMCS_INS_OUTS);
1286	}
1287
1288	/* Pin-based VM-execution controls. */
1289	{
1290	uint32_t const fPinCtls = fVmxTrueMsrs ? pVmxMsrs->TruePinCtls.n.allowed1 : pVmxMsrs->PinCtls.n.allowed1;
1291	pFeatures->fVmxExtIntExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_EXT_INT_EXIT);
1292	pFeatures->fVmxNmiExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_NMI_EXIT);
1293	pFeatures->fVmxVirtNmi = RT_BOOL(fPinCtls & VMX_PIN_CTLS_VIRT_NMI);
1294	pFeatures->fVmxPreemptTimer = RT_BOOL(fPinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
1295	pFeatures->fVmxPostedInt = RT_BOOL(fPinCtls & VMX_PIN_CTLS_POSTED_INT);
1296	}
1297
1298	/* Processor-based VM-execution controls. */
1299	{
1300	uint32_t const fProcCtls = fVmxTrueMsrs ? pVmxMsrs->TrueProcCtls.n.allowed1 : pVmxMsrs->ProcCtls.n.allowed1;
1301	pFeatures->fVmxIntWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT);
1302	pFeatures->fVmxTscOffsetting = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1303	pFeatures->fVmxHltExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_HLT_EXIT);
1304	pFeatures->fVmxInvlpgExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INVLPG_EXIT);
1305	pFeatures->fVmxMwaitExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MWAIT_EXIT);
1306	pFeatures->fVmxRdpmcExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDPMC_EXIT);
1307	pFeatures->fVmxRdtscExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDTSC_EXIT);
1308	pFeatures->fVmxCr3LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT);
1309	pFeatures->fVmxCr3StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT);
1310	pFeatures->fVmxTertiaryExecCtls = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TERTIARY_CTLS);
1311	pFeatures->fVmxCr8LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT);
1312	pFeatures->fVmxCr8StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT);
1313	pFeatures->fVmxUseTprShadow = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
1314	pFeatures->fVmxNmiWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1315	pFeatures->fVmxMovDRxExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT);
1316	pFeatures->fVmxUncondIoExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_UNCOND_IO_EXIT);
1317	pFeatures->fVmxUseIoBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS);
1318	pFeatures->fVmxMonitorTrapFlag = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1319	pFeatures->fVmxUseMsrBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS);
1320	pFeatures->fVmxMonitorExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_EXIT);
1321	pFeatures->fVmxPauseExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_PAUSE_EXIT);
1322	pFeatures->fVmxSecondaryExecCtls = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1323	}
1324
1325	/* Secondary processor-based VM-execution controls. */
1326	{
1327	uint32_t const fProcCtls2 = pFeatures->fVmxSecondaryExecCtls ? pVmxMsrs->ProcCtls2.n.allowed1 : 0;
1328	pFeatures->fVmxVirtApicAccess = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1329	pFeatures->fVmxEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT);
1330	pFeatures->fVmxDescTableExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1331	pFeatures->fVmxRdtscp = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDTSCP);
1332	pFeatures->fVmxVirtX2ApicMode = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
1333	pFeatures->fVmxVpid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VPID);
1334	pFeatures->fVmxWbinvdExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_WBINVD_EXIT);
1335	pFeatures->fVmxUnrestrictedGuest = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1336	pFeatures->fVmxApicRegVirt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT);
1337	pFeatures->fVmxVirtIntDelivery = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
1338	pFeatures->fVmxPauseLoopExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1339	pFeatures->fVmxRdrandExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDRAND_EXIT);
1340	pFeatures->fVmxInvpcid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_INVPCID);
1341	pFeatures->fVmxVmFunc = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VMFUNC);
1342	pFeatures->fVmxVmcsShadowing = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING);
1343	pFeatures->fVmxRdseedExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDSEED_EXIT);
1344	pFeatures->fVmxPml = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PML);
1345	pFeatures->fVmxEptXcptVe = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT_XCPT_VE);
1346	pFeatures->fVmxConcealVmxFromPt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
1347	pFeatures->fVmxXsavesXrstors = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_XSAVES_XRSTORS);
1348	pFeatures->fVmxPasidTranslate = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PASID_TRANSLATE);
1349	pFeatures->fVmxModeBasedExecuteEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
1350	pFeatures->fVmxSppEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_SPP_EPT);
1351	pFeatures->fVmxPtEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PT_EPT);
1352	pFeatures->fVmxUseTscScaling = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_TSC_SCALING);
1353	pFeatures->fVmxUserWaitPause = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_USER_WAIT_PAUSE);
1354	pFeatures->fVmxPconfig = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PCONFIG);
1355	pFeatures->fVmxEnclvExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_ENCLV_EXIT);
1356	pFeatures->fVmxBusLockDetect = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_BUS_LOCK_DETECT);
1357	pFeatures->fVmxInstrTimeout = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_INSTR_TIMEOUT);
1358	}
1359
1360	/* Tertiary processor-based VM-execution controls. */
1361	{
1362	uint64_t const fProcCtls3 = pFeatures->fVmxTertiaryExecCtls ? pVmxMsrs->u64ProcCtls3 : 0;
1363	pFeatures->fVmxLoadIwKeyExit = RT_BOOL(fProcCtls3 & VMX_PROC_CTLS3_LOADIWKEY_EXIT);
1364	pFeatures->fVmxHlat = RT_BOOL(fProcCtls3 & VMX_PROC_CTLS3_HLAT);
1365	pFeatures->fVmxEptPagingWrite = RT_BOOL(fProcCtls3 & VMX_PROC_CTLS3_EPT_PAGING_WRITE);
1366	pFeatures->fVmxGstPagingVerify = RT_BOOL(fProcCtls3 & VMX_PROC_CTLS3_GST_PAGING_VERIFY);
1367	pFeatures->fVmxIpiVirt = RT_BOOL(fProcCtls3 & VMX_PROC_CTLS3_IPI_VIRT);
1368	pFeatures->fVmxVirtSpecCtrl = RT_BOOL(fProcCtls3 & VMX_PROC_CTLS3_VIRT_SPEC_CTRL);
1369	}
1370
1371	/* VM-exit controls. */
1372	{
1373	uint32_t const fExitCtls = fVmxTrueMsrs ? pVmxMsrs->TrueExitCtls.n.allowed1 : pVmxMsrs->ExitCtls.n.allowed1;
1374	pFeatures->fVmxExitSaveDebugCtls = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG);
1375	pFeatures->fVmxHostAddrSpaceSize = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1376	pFeatures->fVmxExitAckExtInt = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT);
1377	pFeatures->fVmxExitSavePatMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR);
1378	pFeatures->fVmxExitLoadPatMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR);
1379	pFeatures->fVmxExitSaveEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR);
1380	pFeatures->fVmxExitLoadEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR);
1381	pFeatures->fVmxSavePreemptTimer = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER);
1382	pFeatures->fVmxSecondaryExitCtls = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_USE_SECONDARY_CTLS);
1383	}
1384
1385	/* VM-entry controls. */
1386	{
1387	uint32_t const fEntryCtls = fVmxTrueMsrs ? pVmxMsrs->TrueEntryCtls.n.allowed1 : pVmxMsrs->EntryCtls.n.allowed1;
1388	pFeatures->fVmxEntryLoadDebugCtls = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG);
1389	pFeatures->fVmxIa32eModeGuest = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1390	pFeatures->fVmxEntryLoadEferMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1391	pFeatures->fVmxEntryLoadPatMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR);
1392	}
1393
1394	/* Miscellaneous data. */
1395	{
1396	uint32_t const fMiscData = pVmxMsrs->u64Misc;
1397	pFeatures->fVmxExitSaveEferLma = RT_BOOL(fMiscData & VMX_MISC_EXIT_SAVE_EFER_LMA);
1398	pFeatures->fVmxPt = RT_BOOL(fMiscData & VMX_MISC_INTEL_PT);
1399	pFeatures->fVmxVmwriteAll = RT_BOOL(fMiscData & VMX_MISC_VMWRITE_ALL);
1400	pFeatures->fVmxEntryInjectSoftInt = RT_BOOL(fMiscData & VMX_MISC_ENTRY_INJECT_SOFT_INT);
1401	}
1402	}
1403
1404
1405	int cpumCpuIdExplodeFeaturesX86(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs, CPUMFEATURESX86 *pFeatures)
1406	{
1407	Assert(pMsrs);
1408	RT_ZERO(*pFeatures);
1409	if (cLeaves >= 2)
1410	{
1411	AssertLogRelReturn(paLeaves[0].uLeaf == 0, VERR_CPUM_IPE_1);
1412	AssertLogRelReturn(paLeaves[1].uLeaf == 1, VERR_CPUM_IPE_1);
1413	PCCPUMCPUIDLEAF const pStd0Leaf = cpumCpuIdFindLeafEx(paLeaves, cLeaves, 0, 0);
1414	AssertLogRelReturn(pStd0Leaf, VERR_CPUM_IPE_1);
1415	PCCPUMCPUIDLEAF const pStd1Leaf = cpumCpuIdFindLeafEx(paLeaves, cLeaves, 1, 0);
1416	AssertLogRelReturn(pStd1Leaf, VERR_CPUM_IPE_1);
1417
1418	pFeatures->enmCpuVendor = CPUMCpuIdDetectX86VendorEx(pStd0Leaf->uEax,
1419	pStd0Leaf->uEbx,
1420	pStd0Leaf->uEcx,
1421	pStd0Leaf->uEdx);
1422	pFeatures->uFamily = RTX86GetCpuFamily(pStd1Leaf->uEax);
1423	pFeatures->uModel = RTX86GetCpuModel(pStd1Leaf->uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
1424	pFeatures->uStepping = RTX86GetCpuStepping(pStd1Leaf->uEax);
1425	pFeatures->enmMicroarch = CPUMCpuIdDetermineX86MicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor,
1426	pFeatures->uFamily,
1427	pFeatures->uModel,
1428	pFeatures->uStepping);
1429
1430	PCCPUMCPUIDLEAF const pExtLeaf8 = cpumCpuIdFindLeaf(paLeaves, cLeaves, 0x80000008);
1431	if (pExtLeaf8)
1432	{
1433	pFeatures->cMaxPhysAddrWidth = pExtLeaf8->uEax & 0xff;
1434	pFeatures->cMaxLinearAddrWidth = (pExtLeaf8->uEax >> 8) & 0xff;
1435	}
1436	else if (pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36)
1437	{
1438	pFeatures->cMaxPhysAddrWidth = 36;
1439	pFeatures->cMaxLinearAddrWidth = 36;
1440	}
1441	else
1442	{
1443	pFeatures->cMaxPhysAddrWidth = 32;
1444	pFeatures->cMaxLinearAddrWidth = 32;
1445	}
1446
1447	/* Standard features. */
1448	pFeatures->fMsr = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MSR);
1449	pFeatures->fApic = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_APIC);
1450	pFeatures->fX2Apic = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_X2APIC);
1451	pFeatures->fPse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE);
1452	pFeatures->fPse36 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36);
1453	pFeatures->fPae = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAE);
1454	pFeatures->fPge = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PGE);
1455	pFeatures->fPat = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAT);
1456	pFeatures->fFxSaveRstor = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_FXSR);
1457	pFeatures->fXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE);
1458	pFeatures->fOpSysXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_OSXSAVE);
1459	pFeatures->fMmx = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MMX);
1460	pFeatures->fSse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE);
1461	pFeatures->fSse2 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE2);
1462	pFeatures->fSse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE3);
1463	pFeatures->fSsse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSSE3);
1464	pFeatures->fFma = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_FMA);
1465	pFeatures->fSse41 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_1);
1466	pFeatures->fSse42 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_2);
1467	pFeatures->fAesNi = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_AES);
1468	pFeatures->fAvx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_AVX);
1469	pFeatures->fTsc = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_TSC);
1470	pFeatures->fSysEnter = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SEP);
1471	pFeatures->fMtrr = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MTRR);
1472	pFeatures->fHypervisorPresent = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_HVP);
1473	pFeatures->fMonitorMWait = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR);
1474	pFeatures->fCmpXchg8b = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_CX8);
1475	pFeatures->fCmpXchg16b = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_CX16);
1476	pFeatures->fClFlush = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_CLFSH);
1477	pFeatures->fPcid = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_PCID);
1478	pFeatures->fPopCnt = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_POPCNT);
1479	pFeatures->fRdRand = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_RDRAND);
1480	pFeatures->fVmx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_VMX);
1481	pFeatures->fPclMul = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_PCLMUL);
1482	pFeatures->fMovBe = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_MOVBE);
1483	pFeatures->fF16c = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_F16C);
1484	if (pFeatures->fVmx)
1485	cpumExplodeVmxFeatures(&pMsrs->hwvirt.vmx, pFeatures);
1486
1487	/* Structured extended features. */
1488	PCCPUMCPUIDLEAF const pSxfLeaf0 = cpumCpuIdFindLeafEx(paLeaves, cLeaves, 7, 0);
1489	if (pSxfLeaf0)
1490	{
1491	pFeatures->fFsGsBase = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE);
1492	pFeatures->fAvx2 = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
1493	pFeatures->fAvx512Foundation = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
1494	pFeatures->fClFlushOpt = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT);
1495	pFeatures->fInvpcid = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID);
1496	pFeatures->fBmi1 = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_BMI1);
1497	pFeatures->fBmi2 = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_BMI2);
1498	pFeatures->fRdSeed = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_RDSEED);
1499	pFeatures->fHle = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_HLE);
1500	pFeatures->fRtm = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_RTM);
1501	pFeatures->fSha = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_SHA);
1502	pFeatures->fAdx = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_ADX);
1503
1504	pFeatures->fIbpb = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB);
1505	pFeatures->fIbrs = pFeatures->fIbpb;
1506	pFeatures->fStibp = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_STIBP);
1507	pFeatures->fFlushCmd = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD);
1508	pFeatures->fArchCap = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP);
1509	pFeatures->fMdsClear = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR);
1510	}
1511
1512	/* MWAIT/MONITOR leaf. */
1513	PCCPUMCPUIDLEAF const pMWaitLeaf = cpumCpuIdFindLeaf(paLeaves, cLeaves, 5);
1514	if (pMWaitLeaf)
1515	pFeatures->fMWaitExtensions = (pMWaitLeaf->uEcx & (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1516	== (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
1517
1518	/* Extended features. */
1519	PCCPUMCPUIDLEAF const pExtLeaf = cpumCpuIdFindLeaf(paLeaves, cLeaves, 0x80000001);
1520	if (pExtLeaf)
1521	{
1522	pFeatures->fLongMode = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1523	pFeatures->fSysCall = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
1524	pFeatures->fNoExecute = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX);
1525	pFeatures->fLahfSahf = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1526	pFeatures->fRdTscP = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1527	pFeatures->fMovCr8In32Bit = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_CMPL);
1528	pFeatures->f3DNow = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1529	pFeatures->f3DNowPrefetch = (pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
1530	\|\| (pExtLeaf->uEdx & ( X86_CPUID_EXT_FEATURE_EDX_LONG_MODE
1531	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW));
1532	pFeatures->fAbm = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_ABM);
1533	}
1534
1535	/* VMX (VMXON, VMCS region and related data structures) physical address width (depends on long-mode). */
1536	pFeatures->cVmxMaxPhysAddrWidth = pFeatures->fLongMode ? pFeatures->cMaxPhysAddrWidth : 32;
1537
1538	if ( pExtLeaf
1539	&& ( pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1540	\|\| pFeatures->enmCpuVendor == CPUMCPUVENDOR_HYGON))
1541	{
1542	/* AMD features. */
1543	pFeatures->fMsr \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MSR);
1544	pFeatures->fApic \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC);
1545	pFeatures->fPse \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE);
1546	pFeatures->fPse36 \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE36);
1547	pFeatures->fPae \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAE);
1548	pFeatures->fPge \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PGE);
1549	pFeatures->fPat \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAT);
1550	pFeatures->fFxSaveRstor \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FXSR);
1551	pFeatures->fMmx \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MMX);
1552	pFeatures->fTsc \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_TSC);
1553	pFeatures->fIbpb \|= pExtLeaf8 && (pExtLeaf8->uEbx & X86_CPUID_AMD_EFEID_EBX_IBPB);
1554	pFeatures->fAmdMmxExts = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1555	pFeatures->fXop = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_XOP);
1556	pFeatures->fTbm = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_TBM);
1557	pFeatures->fSvm = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM);
1558	if (pFeatures->fSvm)
1559	{
1560	PCCPUMCPUIDLEAF pSvmLeaf = cpumCpuIdFindLeaf(paLeaves, cLeaves, 0x8000000a);
1561	AssertLogRelReturn(pSvmLeaf, VERR_CPUM_IPE_1);
1562	pFeatures->fSvmNestedPaging = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING);
1563	pFeatures->fSvmLbrVirt = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT);
1564	pFeatures->fSvmSvmLock = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK);
1565	pFeatures->fSvmNextRipSave = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
1566	pFeatures->fSvmTscRateMsr = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR);
1567	pFeatures->fSvmVmcbClean = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
1568	pFeatures->fSvmFlusbByAsid = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID);
1569	pFeatures->fSvmDecodeAssists = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
1570	pFeatures->fSvmPauseFilter = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
1571	pFeatures->fSvmPauseFilterThreshold = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
1572	pFeatures->fSvmAvic = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_AVIC);
1573	pFeatures->fSvmVirtVmsaveVmload = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD);
1574	pFeatures->fSvmVGif = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VGIF);
1575	pFeatures->fSvmGmet = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_GMET);
1576	pFeatures->fSvmX2Avic = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_X2AVIC);
1577	pFeatures->fSvmSSSCheck = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_SSSCHECK);
1578	pFeatures->fSvmSpecCtrl = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_SPEC_CTRL);
1579	pFeatures->fSvmRoGpt = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_ROGPT);
1580	pFeatures->fSvmHostMceOverride = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_HOST_MCE_OVERRIDE);
1581	pFeatures->fSvmTlbiCtl = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_TLBICTL);
1582	pFeatures->fSvmVNmi = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VNMI);
1583	pFeatures->fSvmIbsVirt = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_IBS_VIRT);
1584	pFeatures->fSvmExtLvtAvicAccessChg = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_EXT_LVT_AVIC_ACCESS_CHG);
1585	pFeatures->fSvmNstVirtVmcbAddrChk = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NST_VIRT_VMCB_ADDR_CHK);
1586	pFeatures->fSvmBusLockThreshold = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_BUS_LOCK_THRESHOLD);
1587	pFeatures->uSvmMaxAsid = pSvmLeaf->uEbx;
1588	}
1589	}
1590
1591	/*
1592	* Quirks.
1593	*/
1594	pFeatures->fLeakyFxSR = pExtLeaf
1595	&& (pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1596	&& ( ( pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1597	&& pFeatures->uFamily >= 6 /* K7 and up */)
1598	\|\| pFeatures->enmCpuVendor == CPUMCPUVENDOR_HYGON);
1599
1600	/*
1601	* Max extended (/FPU) state.
1602	*/
1603	pFeatures->cbMaxExtendedState = pFeatures->fFxSaveRstor ? sizeof(X86FXSTATE) : sizeof(X86FPUSTATE);
1604	if (pFeatures->fXSaveRstor)
1605	{
1606	PCCPUMCPUIDLEAF const pXStateLeaf0 = cpumCpuIdFindLeafEx(paLeaves, cLeaves, 13, 0);
1607	if (pXStateLeaf0)
1608	{
1609	if ( pXStateLeaf0->uEcx >= sizeof(X86FXSTATE)
1610	&& pXStateLeaf0->uEcx <= CPUM_MAX_XSAVE_AREA_SIZE
1611	&& RT_ALIGN_32(pXStateLeaf0->uEcx, 8) == pXStateLeaf0->uEcx
1612	&& pXStateLeaf0->uEbx >= sizeof(X86FXSTATE)
1613	&& pXStateLeaf0->uEbx <= pXStateLeaf0->uEcx
1614	&& RT_ALIGN_32(pXStateLeaf0->uEbx, 8) == pXStateLeaf0->uEbx)
1615	{
1616	pFeatures->cbMaxExtendedState = pXStateLeaf0->uEcx;
1617
1618	/* (paranoia:) */
1619	PCCPUMCPUIDLEAF const pXStateLeaf1 = cpumCpuIdFindLeafEx(paLeaves, cLeaves, 13, 1);
1620	if ( pXStateLeaf1
1621	&& pXStateLeaf1->uEbx > pFeatures->cbMaxExtendedState
1622	&& pXStateLeaf1->uEbx <= CPUM_MAX_XSAVE_AREA_SIZE
1623	&& (pXStateLeaf1->uEcx \|\| pXStateLeaf1->uEdx) )
1624	pFeatures->cbMaxExtendedState = pXStateLeaf1->uEbx;
1625	}
1626	else
1627	AssertLogRelMsgFailedStmt(("Unexpected max/cur XSAVE area sizes: %#x/%#x\n", pXStateLeaf0->uEcx, pXStateLeaf0->uEbx),
1628	pFeatures->fXSaveRstor = 0);
1629	}
1630	else
1631	AssertLogRelMsgFailedStmt(("Expected leaf eax=0xd/ecx=0 with the XSAVE/XRSTOR feature!\n"),
1632	pFeatures->fXSaveRstor = 0);
1633	}
1634
1635	/*
1636	* Enable or disable VEX support depending on whether it's needed. Note that AVX,
1637	* BMI1, and BMI2 all use VEX encoding but are theoretically independent of each other.
1638	*/
1639	pFeatures->fVex = pFeatures->fAvx \| pFeatures->fBmi1 \| pFeatures->fBmi2;
1640	}
1641	else
1642	AssertLogRelReturn(cLeaves == 0, VERR_CPUM_IPE_1);
1643	return VINF_SUCCESS;
1644	}
1645
1646
1647	/**
1648	* Helper for extracting feature bits from IA32_ARCH_CAPABILITIES.
1649	*/
1650	static void cpumCpuIdExplodeArchCapabilities(CPUMFEATURESX86 *pFeatures, bool fHasArchCap, uint64_t fArchVal)
1651	{
1652	Assert(fHasArchCap \|\| fArchVal == 0);
1653	pFeatures->fArchCap = fHasArchCap;
1654	pFeatures->fArchRdclNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RDCL_NO);
1655	pFeatures->fArchIbrsAll = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_IBRS_ALL);
1656	pFeatures->fArchRsbOverride = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RSBO);
1657	pFeatures->fArchVmmNeedNotFlushL1d = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D);
1658	#if 0
1659	pFeatures->fArchSsbNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_SSB_NO);
1660	#endif
1661	pFeatures->fArchMdsNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_MDS_NO);
1662	#if 0
1663	pFeatures->fArchIfPschangeMscNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_IF_PSCHANGE_MC_NO);
1664	pFeatures->fArchTsxCtrl = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_TSX_CTRL);
1665	pFeatures->fArchTaaNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_TAA_NO);
1666	pFeatures->fArchMiscPackageCtrls = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_MISC_PACKAGE_CTRLS);
1667	pFeatures->fArchEnergyFilteringCtl = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_ENERGY_FILTERING_CTL);
1668	pFeatures->fArchDoitm = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_DOITM);
1669	pFeatures->fArchSbdrSsdpNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_SBDR_SSDP_NO);
1670	pFeatures->fArchFbsdpNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_FBSDP_NO);
1671	pFeatures->fArchPsdpNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_PSDP_NO);
1672	pFeatures->fArchFbClear = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_FB_CLEAR);
1673	pFeatures->fArchFbClearCtrl = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_FB_CLEAR_CTRL);
1674	pFeatures->fArchRrsba = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RRSBA);
1675	pFeatures->fArchBhiNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_BHI_NO);
1676	pFeatures->fArchXapicDisableStatus = RT_BOOL(fArchVal & XAPIC_DISABLE_STATUS);
1677	pFeatures->fArchOverclockingStatus = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_OVERCLOCKING_STATUS);
1678	pFeatures->fArchPbrsbNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_PBRSB_NO);
1679	pFeatures->fArchGdsCtrl = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_GDS_CTRL);
1680	pFeatures->fArchGdsNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_GDS_NO);
1681	pFeatures->fArchRfdsNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RFDS_NO);
1682	pFeatures->fArchRfdsClear = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RFDS_CLEAR);
1683	pFeatures->fArchIgnUmonitorSupport = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_IGN_UMONITOR_SUPPORT);
1684	pFeatures->fArchMonUmonMitigSupport= RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_MON_UMON_MITIG_SUPPORT);
1685	#endif
1686	}
1687
1688
1689	# if defined(VBOX_VMM_TARGET_X86) \|\| defined(VBOX_VMM_TARGET_AGNOSTIC)
1690	/**
1691	* Sets the guest IA32_ARCH_CAPABILITIES value and associated feature bits.
1692	*/
1693	void cpumCpuIdSetGuestArchCapabilities(PVMCC pVM, bool fHasArchCap, uint64_t fArchVal, bool fHasIbrs)
1694	{
1695	if (!fHasArchCap)
1696	fArchVal = 0;
1697	else if (!fHasIbrs)
1698	fArchVal &= ~MSR_IA32_ARCH_CAP_F_IBRS_ALL;
1699	fArchVal &= ~( RT_BIT_64(9)
1700	\| MSR_IA32_ARCH_CAP_F_MISC_PACKAGE_CTRLS
1701	\| MSR_IA32_ARCH_CAP_F_ENERGY_FILTERING_CTL
1702	\| MSR_IA32_ARCH_CAP_F_DOITM
1703	\| RT_BIT_64(16)
1704	\| RT_BIT_64(22)
1705	\| MSR_IA32_ARCH_CAP_F_FB_CLEAR_CTRL
1706	/** @todo mask off MSR_IA32_ARCH_CAP_F_RRSBA ? */
1707	\| MSR_IA32_ARCH_CAP_F_XAPIC_DISABLE_STATUS
1708	\| MSR_IA32_ARCH_CAP_F_OVERCLOCKING_STATUS /** @todo expose IA32_OVERCLOCKING_STATUS */
1709	\| MSR_IA32_ARCH_CAP_F_GDS_CTRL
1710	\| MSR_IA32_ARCH_CAP_F_IGN_UMONITOR_SUPPORT
1711	\| MSR_IA32_ARCH_CAP_F_MON_UMON_MITIG_SUPPORT
1712	\| ~(RT_BIT_64(31) - 1U)
1713	);
1714	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.GuestMsrs.msr.ArchCaps = fArchVal);
1715
1716	cpumCpuIdExplodeArchCapabilities(&pVM->cpum.s.GuestFeatures, fHasArchCap, fArchVal);
1717	LogRel(("CPUM: Guest IA32_ARCH_CAPABILITIES = %#RX64\n", fArchVal));
1718	}
1719	# endif
1720
1721
1722	# if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
1723	/**
1724	* Sets host & guest feature bits & MSRs related to IA32_ARCH_CAPABILITIES.
1725	*
1726	* ASSUMES this is called after the basic guest features has been exploded.
1727	*/
1728	VMM_INT_DECL(void) CPUMCpuIdApplyX86HostArchCapabilities(PVMCC pVM, bool fHasArchCap, uint64_t fHostArchVal)
1729	{
1730	cpumCpuIdExplodeArchCapabilities(const_cast<CPUMFEATURESX86 *>(&pVM->cpum.s.HostFeatures.s), fHasArchCap, fHostArchVal);
1731	LogRel(("CPUM: Host IA32_ARCH_CAPABILITIES = %#RX64\n", fHostArchVal));
1732
1733	# if defined(VBOX_VMM_TARGET_X86) \|\| defined(VBOX_VMM_TARGET_AGNOSTIC)
1734	# ifdef VBOX_VMM_TARGET_AGNOSTIC
1735	/** @todo arm on x86: check VM target. */
1736	# endif
1737	cpumCpuIdSetGuestArchCapabilities(pVM, fHasArchCap && pVM->cpum.s.GuestFeatures.fArchCap,
1738	fHostArchVal, pVM->cpum.s.GuestFeatures.fIbrs);
1739	# endif
1740	}
1741	# endif /* defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64) */
1742
1743	#endif /* defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64) \|\| defined(VBOX_VMM_TARGET_X86) */
1744
1745	#if defined(RT_ARCH_ARM64)
1746	/**
1747	* Collects the ID registers from an ARMv8 host.
1748	*
1749	* This isn't trivial an all hosts when running in userland and there is no
1750	* support driver handy.
1751	*/
1752	VMMDECL(int) CPUMCpuIdCollectIdRegistersFromArmV8Host(PCPUMARMV8IDREGS pIdRegs)
1753	{
1754	# ifdef _MSC_VER
1755	# define READ_SYS_REG(a_u64Dst, a_SysRegName) do { \
1756	(a_u64Dst) = (uint64_t)_ReadStatusReg(RT_CONCAT(ARMV8_AARCH64_SYSREG_,a_SysRegName) & 0x7fff); \
1757	} while (0)
1758	# else
1759	# define READ_SYS_REG(a_u64Dst, a_SysRegName) do { \
1760	__asm__ __volatile__ ("mrs %0, " #a_SysRegName : "=r" (a_u64Dst)); \
1761	} while (0)
1762	# endif
1763
1764	RT_ZERO(*pIdRegs);
1765
1766	/*
1767	* CTR_EL0 can be trapped when executed in L0 (SCTLR_EL0.UCT) and macOS
1768	* & Windows does so by default. Linux OTOH typically exposes all the
1769	* feature registers to user land with some sanitizing.
1770	*/
1771	# if !defined(IN_RING3) \|\| defined(RT_OS_LINUX)
1772	READ_SYS_REG(pIdRegs->u64RegCtrEl0, CTR_EL0);
1773	# endif
1774	READ_SYS_REG(pIdRegs->u64RegDczidEl0, DCZID_EL0);
1775
1776	# if defined(IN_RING0) \|\| defined(RT_OS_LINUX)
1777	# ifdef IN_RING3
1778	if (getauxval(AT_HWCAP) & HWCAP_CPUID)
1779	# endif
1780	{
1781	READ_SYS_REG(pIdRegs->u64RegIdAa64Pfr0El1, ID_AA64PFR0_EL1);
1782	READ_SYS_REG(pIdRegs->u64RegIdAa64Pfr1El1, ID_AA64PFR1_EL1);
1783	READ_SYS_REG(pIdRegs->u64RegIdAa64Dfr0El1, ID_AA64DFR0_EL1);
1784	READ_SYS_REG(pIdRegs->u64RegIdAa64Dfr1El1, ID_AA64DFR1_EL1);
1785	/// @todo READ_SYS_REG(pIdRegs->u64RegIdAa64Dfr2El1, ID_AA64DFR2_EL1);
1786	READ_SYS_REG(pIdRegs->u64RegIdAa64Afr0El1, ID_AA64AFR0_EL1);
1787	READ_SYS_REG(pIdRegs->u64RegIdAa64Afr1El1, ID_AA64AFR1_EL1);
1788	READ_SYS_REG(pIdRegs->u64RegIdAa64Isar0El1, ID_AA64ISAR0_EL1);
1789	READ_SYS_REG(pIdRegs->u64RegIdAa64Isar1El1, ID_AA64ISAR1_EL1);
1790	READ_SYS_REG(pIdRegs->u64RegIdAa64Isar2El1, ID_AA64ISAR2_EL1);
1791	/// @todo READ_SYS_REG(pIdRegs->u64RegIdAa64Isar3El1, ID_AA64ISAR3_EL1);
1792	READ_SYS_REG(pIdRegs->u64RegIdAa64Mmfr0El1, ID_AA64MMFR0_EL1);
1793	READ_SYS_REG(pIdRegs->u64RegIdAa64Mmfr1El1, ID_AA64MMFR1_EL1);
1794	READ_SYS_REG(pIdRegs->u64RegIdAa64Mmfr2El1, ID_AA64MMFR2_EL1);
1795	/// @todo READ_SYS_REG(pIdRegs->u64RegIdAa64Mmfr3El1, ID_AA64MMFR3_EL1);
1796	/// @todo READ_SYS_REG(pIdRegs->u64RegIdAa64Mmfr4El1, ID_AA64MMFR4_EL1);
1797	READ_SYS_REG(pIdRegs->u64RegClidrEl1, CLIDR_EL1);
1798
1799	/// @todo READ_SYS_REG(pIdRegs->uMainIdRegEl1, MIDR_EL1);
1800	/// @todo READ_SYS_REG(pIdRegs->uMpIdRegEl1, MPIDR_EL1);
1801	/// @todo READ_SYS_REG(pIdRegs->uRevIdRegEl1, REVIDR_EL1);
1802	return VINF_SUCCESS;
1803	}
1804	# endif
1805	# ifndef IN_RING0
1806	/** @todo On darwin we should just cache the information (CPU DB) and figure
1807	* out which Apple Mx we're running on. */
1808	/** @todo Make the info available via the support driver... */
1809	return VINF_SUCCESS;
1810	# endif
1811	}
1812	#endif /* defined(RT_ARCH_ARM64) */
1813
1814	#if defined(RT_ARCH_ARM64) \|\| defined(VBOX_VMM_TARGET_ARMV8)
1815	/**
1816	* Explode the CPU features from the given ID registers.
1817	*
1818	* @returns VBox status code.
1819	* @param pIdRegs The ID registers to explode the features from.
1820	* @param pFeatures Where to store the features to.
1821	*/
1822	int cpumCpuIdExplodeFeaturesArmV8(PCCPUMARMV8IDREGS pIdRegs, CPUMFEATURESARMV8 *pFeatures)
1823	{
1824	uint64_t u64IdReg = pIdRegs->u64RegIdAa64Mmfr0El1;
1825
1826	static uint8_t s_aPaRange[] = { 32, 36, 40, 42, 44, 48, 52 };
1827	AssertLogRelMsgReturn(RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR0_EL1_PARANGE) < RT_ELEMENTS(s_aPaRange),
1828	("CPUM: Invalid/Unsupported PARange value in ID_AA64MMFR0_EL1 register: %u\n",
1829	RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR0_EL1_PARANGE)),
1830	VERR_CPUM_IPE_1);
1831
1832	pFeatures->cMaxPhysAddrWidth = s_aPaRange[RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR0_EL1_PARANGE)];
1833	pFeatures->fTGran4K = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR0_EL1_TGRAN4) != ARMV8_ID_AA64MMFR0_EL1_TGRAN4_NOT_IMPL;
1834	pFeatures->fTGran16K = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR0_EL1_TGRAN16) != ARMV8_ID_AA64MMFR0_EL1_TGRAN16_NOT_IMPL;
1835	pFeatures->fTGran64K = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR0_EL1_TGRAN64) != ARMV8_ID_AA64MMFR0_EL1_TGRAN64_NOT_IMPL;
1836
1837	/* ID_AA64ISAR0_EL1 features. */
1838	u64IdReg = pIdRegs->u64RegIdAa64Isar0El1;
1839	pFeatures->fAes = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_AES) >= ARMV8_ID_AA64ISAR0_EL1_AES_SUPPORTED;
1840	pFeatures->fPmull = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_AES) >= ARMV8_ID_AA64ISAR0_EL1_AES_SUPPORTED_PMULL;
1841	pFeatures->fSha1 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_SHA1) >= ARMV8_ID_AA64ISAR0_EL1_SHA1_SUPPORTED;
1842	pFeatures->fSha256 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_SHA2) >= ARMV8_ID_AA64ISAR0_EL1_SHA2_SUPPORTED_SHA256;
1843	pFeatures->fSha512 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_SHA2) >= ARMV8_ID_AA64ISAR0_EL1_SHA2_SUPPORTED_SHA256_SHA512;
1844	pFeatures->fCrc32 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_CRC32) >= ARMV8_ID_AA64ISAR0_EL1_CRC32_SUPPORTED;
1845	pFeatures->fLse = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_ATOMIC) >= ARMV8_ID_AA64ISAR0_EL1_ATOMIC_SUPPORTED;
1846	pFeatures->fTme = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_TME) >= ARMV8_ID_AA64ISAR0_EL1_TME_SUPPORTED;
1847	pFeatures->fRdm = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_RDM) >= ARMV8_ID_AA64ISAR0_EL1_RDM_SUPPORTED;
1848	pFeatures->fSha3 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_SHA3) >= ARMV8_ID_AA64ISAR0_EL1_SHA3_SUPPORTED;
1849	pFeatures->fSm3 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_SM3) >= ARMV8_ID_AA64ISAR0_EL1_SM3_SUPPORTED;
1850	pFeatures->fSm4 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_SM4) >= ARMV8_ID_AA64ISAR0_EL1_SM4_SUPPORTED;
1851	pFeatures->fDotProd = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_DP) >= ARMV8_ID_AA64ISAR0_EL1_DP_SUPPORTED;
1852	pFeatures->fFhm = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_FHM) >= ARMV8_ID_AA64ISAR0_EL1_FHM_SUPPORTED;
1853	pFeatures->fFlagM = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_TS) >= ARMV8_ID_AA64ISAR0_EL1_TS_SUPPORTED;
1854	pFeatures->fFlagM2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_TS) >= ARMV8_ID_AA64ISAR0_EL1_TS_SUPPORTED_2;
1855	pFeatures->fTlbios = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_TLB) >= ARMV8_ID_AA64ISAR0_EL1_TLB_SUPPORTED;
1856	pFeatures->fTlbirange = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_TLB) >= ARMV8_ID_AA64ISAR0_EL1_TLB_SUPPORTED_RANGE;
1857	pFeatures->fRng = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_RNDR) >= ARMV8_ID_AA64ISAR0_EL1_RNDR_SUPPORTED;
1858
1859	/* ID_AA64ISAR1_EL1 features. */
1860	u64IdReg = pIdRegs->u64RegIdAa64Isar1El1;
1861	pFeatures->fDpb = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_DPB) >= ARMV8_ID_AA64ISAR1_EL1_DPB_SUPPORTED;
1862	pFeatures->fDpb2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_DPB) >= ARMV8_ID_AA64ISAR1_EL1_DPB_SUPPORTED_2;
1863
1864	/* PAuth using QARMA5. */
1865	pFeatures->fPacQarma5 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_APA) != ARMV8_ID_AA64ISAR1_EL1_APA_NOT_IMPL;
1866	if (pFeatures->fPacQarma5)
1867	{
1868	pFeatures->fPAuth = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_APA) >= ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_PAUTH;
1869	pFeatures->fEpac = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_APA) >= ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_EPAC;
1870	pFeatures->fPAuth2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_APA) >= ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_PAUTH2;
1871	pFeatures->fFpac = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_APA) >= ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_FPAC;
1872	pFeatures->fFpacCombine = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_APA) >= ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_FPACCOMBINE;
1873	}
1874
1875	/* PAuth using implementation defined algorithm. */
1876	pFeatures->fPacImp = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_API) != ARMV8_ID_AA64ISAR1_EL1_API_NOT_IMPL;
1877	if (pFeatures->fPacQarma5)
1878	{
1879	pFeatures->fPAuth = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_API) >= ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_PAUTH;
1880	pFeatures->fEpac = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_API) >= ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_EPAC;
1881	pFeatures->fPAuth2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_API) >= ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_PAUTH2;
1882	pFeatures->fFpac = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_API) >= ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_FPAC;
1883	pFeatures->fFpacCombine = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_API) >= ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_FPACCOMBINE;
1884	}
1885
1886	pFeatures->fJscvt = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_FJCVTZS) >= ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_SUPPORTED;
1887	pFeatures->fFcma = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_FCMA) >= ARMV8_ID_AA64ISAR1_EL1_FCMA_SUPPORTED;
1888	pFeatures->fLrcpc = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_LRCPC) >= ARMV8_ID_AA64ISAR1_EL1_LRCPC_SUPPORTED;
1889	pFeatures->fLrcpc2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_LRCPC) >= ARMV8_ID_AA64ISAR1_EL1_LRCPC_SUPPORTED_2;
1890	pFeatures->fFrintts = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_FRINTTS) >= ARMV8_ID_AA64ISAR1_EL1_FRINTTS_SUPPORTED;
1891	pFeatures->fSb = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_SB) >= ARMV8_ID_AA64ISAR1_EL1_SB_SUPPORTED;
1892	pFeatures->fSpecres = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_SPECRES) >= ARMV8_ID_AA64ISAR1_EL1_SPECRES_SUPPORTED;
1893	pFeatures->fBf16 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_BF16) >= ARMV8_ID_AA64ISAR1_EL1_BF16_SUPPORTED_BF16;
1894	pFeatures->fEbf16 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_BF16) >= ARMV8_ID_AA64ISAR1_EL1_BF16_SUPPORTED_EBF16;
1895	pFeatures->fDgh = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_DGH) >= ARMV8_ID_AA64ISAR1_EL1_DGH_SUPPORTED;
1896	pFeatures->fI8mm = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_I8MM) >= ARMV8_ID_AA64ISAR1_EL1_I8MM_SUPPORTED;
1897	pFeatures->fXs = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_XS) >= ARMV8_ID_AA64ISAR1_EL1_XS_SUPPORTED;
1898	pFeatures->fLs64 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_LS64) >= ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED;
1899	pFeatures->fLs64V = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_LS64) >= ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED_V;
1900	pFeatures->fLs64Accdata = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_LS64) >= ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED_ACCDATA;
1901
1902	/* ID_AA64ISAR2_EL1 features. */
1903	u64IdReg = pIdRegs->u64RegIdAa64Isar2El1;
1904	pFeatures->fWfxt = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_WFXT) >= ARMV8_ID_AA64ISAR2_EL1_WFXT_SUPPORTED;
1905	pFeatures->fRpres = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_RPRES) >= ARMV8_ID_AA64ISAR2_EL1_RPRES_SUPPORTED;
1906
1907	/* PAuth using QARMA3. */
1908	pFeatures->fPacQarma3 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_GPA3) >= ARMV8_ID_AA64ISAR2_EL1_GPA3_SUPPORTED;
1909	pFeatures->fPacQarma3 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_APA3) != ARMV8_ID_AA64ISAR2_EL1_APA3_NOT_IMPL;
1910	if (pFeatures->fPacQarma5)
1911	{
1912	pFeatures->fPAuth = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_APA3) >= ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_PAUTH;
1913	pFeatures->fEpac = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_APA3) >= ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_EPAC;
1914	pFeatures->fPAuth2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_APA3) >= ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_PAUTH2;
1915	pFeatures->fFpac = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_APA3) >= ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_FPAC;
1916	pFeatures->fFpacCombine = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_APA3) >= ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_FPACCOMBINE;
1917	}
1918
1919	pFeatures->fMops = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_MOPS) >= ARMV8_ID_AA64ISAR2_EL1_MOPS_SUPPORTED;
1920	pFeatures->fHbc = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_BC) >= ARMV8_ID_AA64ISAR2_EL1_BC_SUPPORTED;
1921	pFeatures->fConstPacField = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_PACFRAC) >= ARMV8_ID_AA64ISAR2_EL1_PACFRAC_TRUE;
1922
1923	/* ID_AA64PFR0_EL1 */
1924	u64IdReg = pIdRegs->u64RegIdAa64Pfr0El1;
1925	/* The FP and AdvSIMD field must have the same value. */
1926	Assert(RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_FP) == RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_ADVSIMD));
1927	pFeatures->fFp = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_FP) != ARMV8_ID_AA64PFR0_EL1_FP_NOT_IMPL;
1928	pFeatures->fFp16 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_FP) == ARMV8_ID_AA64PFR0_EL1_FP_IMPL_SP_DP_HP;
1929	pFeatures->fAdvSimd = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_ADVSIMD) != ARMV8_ID_AA64PFR0_EL1_ADVSIMD_NOT_IMPL;
1930	pFeatures->fFp16 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_ADVSIMD) == ARMV8_ID_AA64PFR0_EL1_ADVSIMD_IMPL_SP_DP_HP;
1931	pFeatures->fRas = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_RAS) >= ARMV8_ID_AA64PFR0_EL1_RAS_SUPPORTED;
1932	pFeatures->fRasV1p1 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_RAS) >= ARMV8_ID_AA64PFR0_EL1_RAS_V1P1;
1933	pFeatures->fSve = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_SVE) >= ARMV8_ID_AA64PFR0_EL1_SVE_SUPPORTED;
1934	pFeatures->fSecEl2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_SEL2) >= ARMV8_ID_AA64PFR0_EL1_SEL2_SUPPORTED;
1935	pFeatures->fAmuV1 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_AMU) >= ARMV8_ID_AA64PFR0_EL1_AMU_V1;
1936	pFeatures->fAmuV1p1 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_AMU) >= ARMV8_ID_AA64PFR0_EL1_AMU_V1P1;
1937	pFeatures->fDit = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_DIT) >= ARMV8_ID_AA64PFR0_EL1_DIT_SUPPORTED;
1938	pFeatures->fRme = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_RME) >= ARMV8_ID_AA64PFR0_EL1_RME_SUPPORTED;
1939	pFeatures->fCsv2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_CSV2) >= ARMV8_ID_AA64PFR0_EL1_CSV2_SUPPORTED;
1940	pFeatures->fCsv2v3 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_CSV2) >= ARMV8_ID_AA64PFR0_EL1_CSV2_3_SUPPORTED;
1941
1942	/* ID_AA64PFR1_EL1 */
1943	u64IdReg = pIdRegs->u64RegIdAa64Pfr1El1;
1944	pFeatures->fBti = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR1_EL1_BT) >= ARMV8_ID_AA64PFR1_EL1_BT_SUPPORTED;
1945	pFeatures->fSsbs = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR1_EL1_SSBS) >= ARMV8_ID_AA64PFR1_EL1_SSBS_SUPPORTED;
1946	pFeatures->fSsbs2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR1_EL1_SSBS) >= ARMV8_ID_AA64PFR1_EL1_SSBS_SUPPORTED_MSR_MRS;
1947	pFeatures->fMte = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR1_EL1_MTE) >= ARMV8_ID_AA64PFR1_EL1_MTE_INSN_ONLY;
1948	pFeatures->fMte2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR1_EL1_MTE) >= ARMV8_ID_AA64PFR1_EL1_MTE_FULL;
1949	pFeatures->fMte3 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR1_EL1_MTE) >= ARMV8_ID_AA64PFR1_EL1_MTE_FULL_ASYM_TAG_FAULT_CHK;
1950	/** @todo RAS_frac, MPAM_frac, CSV2_frac. */
1951	pFeatures->fSme = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR1_EL1_SME) >= ARMV8_ID_AA64PFR1_EL1_SME_SUPPORTED;
1952	pFeatures->fSme2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR1_EL1_SME) >= ARMV8_ID_AA64PFR1_EL1_SME_SME2;
1953	pFeatures->fRngTrap = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR1_EL1_RNDRTRAP) >= ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_SUPPORTED;
1954	pFeatures->fNmi = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR1_EL1_NMI) >= ARMV8_ID_AA64PFR1_EL1_NMI_SUPPORTED;
1955
1956	/* ID_AA64MMFR0_EL1 */
1957	u64IdReg = pIdRegs->u64RegIdAa64Mmfr0El1;
1958	pFeatures->fExs = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR0_EL1_EXS) >= ARMV8_ID_AA64MMFR0_EL1_EXS_SUPPORTED;
1959	pFeatures->fFgt = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR0_EL1_FGT) >= ARMV8_ID_AA64MMFR0_EL1_FGT_SUPPORTED;
1960	pFeatures->fEcv = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR0_EL1_ECV) >= ARMV8_ID_AA64MMFR0_EL1_ECV_SUPPORTED;
1961
1962	/* ID_AA64MMFR1_EL1 */
1963	u64IdReg = pIdRegs->u64RegIdAa64Mmfr1El1;
1964	pFeatures->fHafdbs = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_HAFDBS) >= ARMV8_ID_AA64MMFR1_EL1_HAFDBS_SUPPORTED;
1965	pFeatures->fVmid16 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_VMIDBITS) >= ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_16;
1966	pFeatures->fVhe = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_VHE) >= ARMV8_ID_AA64MMFR1_EL1_VHE_SUPPORTED;
1967	pFeatures->fHpds = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_HPDS) >= ARMV8_ID_AA64MMFR1_EL1_HPDS_SUPPORTED;
1968	pFeatures->fHpds2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_HPDS) >= ARMV8_ID_AA64MMFR1_EL1_HPDS_SUPPORTED_2;
1969	pFeatures->fLor = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_LO) >= ARMV8_ID_AA64MMFR1_EL1_LO_SUPPORTED;
1970	pFeatures->fPan = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_PAN) >= ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED;
1971	pFeatures->fPan2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_PAN) >= ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED_2;
1972	pFeatures->fPan3 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_PAN) >= ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED_3;
1973	pFeatures->fXnx = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_XNX) >= ARMV8_ID_AA64MMFR1_EL1_XNX_SUPPORTED;
1974	pFeatures->fTwed = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_TWED) >= ARMV8_ID_AA64MMFR1_EL1_TWED_SUPPORTED;
1975	pFeatures->fEts2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_ETS) >= ARMV8_ID_AA64MMFR1_EL1_ETS_SUPPORTED;
1976	pFeatures->fHcx = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_HCX) >= ARMV8_ID_AA64MMFR1_EL1_HCX_SUPPORTED;
1977	pFeatures->fAfp = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_AFP) >= ARMV8_ID_AA64MMFR1_EL1_AFP_SUPPORTED;
1978	pFeatures->fNTlbpa = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_NTLBPA) >= ARMV8_ID_AA64MMFR1_EL1_NTLBPA_INCLUDE_COHERENT_ONLY;
1979	pFeatures->fTidcp1 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_TIDCP1) >= ARMV8_ID_AA64MMFR1_EL1_TIDCP1_SUPPORTED;
1980	pFeatures->fCmow = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_CMOW) >= ARMV8_ID_AA64MMFR1_EL1_CMOW_SUPPORTED;
1981
1982	/* ID_AA64MMFR2_EL1 */
1983	u64IdReg = pIdRegs->u64RegIdAa64Mmfr2El1;
1984	pFeatures->fTtcnp = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_CNP) >= ARMV8_ID_AA64MMFR2_EL1_CNP_SUPPORTED;
1985	pFeatures->fUao = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_UAO) >= ARMV8_ID_AA64MMFR2_EL1_UAO_SUPPORTED;
1986	pFeatures->fLsmaoc = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_LSM) >= ARMV8_ID_AA64MMFR2_EL1_LSM_SUPPORTED;
1987	pFeatures->fIesb = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_IESB) >= ARMV8_ID_AA64MMFR2_EL1_IESB_SUPPORTED;
1988	pFeatures->fLva = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_VARANGE) >= ARMV8_ID_AA64MMFR2_EL1_VARANGE_52BITS_64KB_GRAN;
1989	pFeatures->fCcidx = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_CCIDX) >= ARMV8_ID_AA64MMFR2_EL1_CCIDX_64BIT;
1990	pFeatures->fNv = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_NV) >= ARMV8_ID_AA64MMFR2_EL1_NV_SUPPORTED;
1991	pFeatures->fNv2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_NV) >= ARMV8_ID_AA64MMFR2_EL1_NV_SUPPORTED_2;
1992	pFeatures->fTtst = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_ST) >= ARMV8_ID_AA64MMFR2_EL1_ST_SUPPORTED;
1993	pFeatures->fLse2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_AT) >= ARMV8_ID_AA64MMFR2_EL1_AT_SUPPORTED;
1994	pFeatures->fIdst = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_IDS) >= ARMV8_ID_AA64MMFR2_EL1_IDS_EC_18H;
1995	pFeatures->fS2Fwb = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_FWB) >= ARMV8_ID_AA64MMFR2_EL1_FWB_SUPPORTED;
1996	pFeatures->fTtl = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_TTL) >= ARMV8_ID_AA64MMFR2_EL1_TTL_SUPPORTED;
1997	pFeatures->fEvt = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_EVT) >= ARMV8_ID_AA64MMFR2_EL1_EVT_SUPPORTED;
1998	pFeatures->fE0Pd = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_E0PD) >= ARMV8_ID_AA64MMFR2_EL1_E0PD_SUPPORTED;
1999
2000	/* ID_AA64DFR0_EL1 */
2001	u64IdReg = pIdRegs->u64RegIdAa64Dfr0El1;
2002	pFeatures->fDebugV8p1 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_DEBUGVER) >= ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8_VHE;
2003	pFeatures->fDebugV8p2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_DEBUGVER) >= ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p2;
2004	pFeatures->fDebugV8p4 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_DEBUGVER) >= ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p4;
2005	pFeatures->fDebugV8p8 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_DEBUGVER) >= ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p8;
2006	pFeatures->fPmuV3 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_PMUVER) >= ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3;
2007	pFeatures->fPmuV3p1 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_PMUVER) >= ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P1;
2008	pFeatures->fPmuV3p4 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_PMUVER) >= ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P4;
2009	pFeatures->fPmuV3p5 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_PMUVER) >= ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P5;
2010	pFeatures->fPmuV3p7 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_PMUVER) >= ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P7;
2011	pFeatures->fPmuV3p8 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_PMUVER) >= ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P8;
2012	pFeatures->fSpe = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_PMSVER) >= ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED;
2013	pFeatures->fSpeV1p1 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_PMSVER) >= ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P1;
2014	pFeatures->fSpeV1p2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_PMSVER) >= ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P2;
2015	pFeatures->fSpeV1p3 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_PMSVER) >= ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P3;
2016	pFeatures->fDoubleLock = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK) == ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_SUPPORTED;
2017	pFeatures->fTrf = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_TRACEFILT) >= ARMV8_ID_AA64DFR0_EL1_TRACEFILT_SUPPORTED;
2018	pFeatures->fTrbe = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER) >= ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_SUPPORTED;
2019	pFeatures->fMtPmu = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_MTPMU) == ARMV8_ID_AA64DFR0_EL1_MTPMU_SUPPORTED;
2020	pFeatures->fBrbe = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_BRBE) >= ARMV8_ID_AA64DFR0_EL1_BRBE_SUPPORTED;
2021	pFeatures->fBrbeV1p1 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_BRBE) >= ARMV8_ID_AA64DFR0_EL1_BRBE_SUPPORTED_V1P1;
2022	pFeatures->fHpmn0 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_HPMN0) >= ARMV8_ID_AA64DFR0_EL1_HPMN0_SUPPORTED;
2023
2024	return VINF_SUCCESS;
2025	}
2026	#endif /* defined(RT_ARCH_ARM64) \|\| defined(VBOX_VMM_TARGET_ARMV8) */
2027

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source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllCpuId.cpp@ 107703

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