CPUMAllMsrs.cpp@ 107817

Last change on this file since 107817 was 107762, checked in by vboxsync, 5 weeks ago
VMM/CPUM: Pass thru more MSR_IA32_SPEC_CTRL related stuff to the guest. [bugfix] jiraref:VBP-947
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1	/* $Id: CPUMAllMsrs.cpp 107762 2025-01-14 16:10:51Z vboxsync $ */
2	/** @file
3	* CPUM - CPU MSR Registers.
4	*/
5
6	/*
7	* Copyright (C) 2013-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_CPUM
33	#include <VBox/vmm/cpum.h>
34	#include <VBox/vmm/pdmapic.h>
35	#include <VBox/vmm/hm.h>
36	#include <VBox/vmm/hm_vmx.h>
37	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
38	# include <VBox/vmm/iem.h>
39	#endif
40	#include <VBox/vmm/tm.h>
41	#include <VBox/vmm/gim.h>
42	#include "CPUMInternal.h"
43	#include <VBox/vmm/vmcc.h>
44	#include <VBox/err.h>
45
46
47	/*********************************************************************************************************************************
48	* Defined Constants And Macros *
49	*********************************************************************************************************************************/
50	/**
51	* Validates the CPUMMSRRANGE::offCpumCpu value and declares a local variable
52	* pointing to it.
53	*
54	* ASSUMES sizeof(a_Type) is a power of two and that the member is aligned
55	* correctly.
56	*/
57	#define CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(a_pVCpu, a_pRange, a_Type, a_VarName) \
58	AssertMsgReturn( (a_pRange)->offCpumCpu >= 8 \
59	&& (a_pRange)->offCpumCpu < sizeof(CPUMCPU) \
60	&& !((a_pRange)->offCpumCpu & (RT_MIN(sizeof(a_Type), 8) - 1)) \
61	, ("offCpumCpu=%#x %s\n", (a_pRange)->offCpumCpu, (a_pRange)->szName), \
62	VERR_CPUM_MSR_BAD_CPUMCPU_OFFSET); \
63	a_Type a_VarName = (a_Type )((uintptr_t)&(a_pVCpu)->cpum.s + (a_pRange)->offCpumCpu)
64
65
66	/*********************************************************************************************************************************
67	* Structures and Typedefs *
68	*********************************************************************************************************************************/
69
70	/**
71	* Implements reading one or more MSRs.
72	*
73	* @returns VBox status code.
74	* @retval VINF_SUCCESS on success.
75	* @retval VINF_CPUM_R3_MSR_READ if the MSR read could not be serviced in the
76	* current context (raw-mode or ring-0).
77	* @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR).
78	*
79	* @param pVCpu The cross context virtual CPU structure.
80	* @param idMsr The MSR we're reading.
81	* @param pRange The MSR range descriptor.
82	* @param puValue Where to return the value.
83	*/
84	typedef DECLCALLBACKTYPE(VBOXSTRICTRC, FNCPUMRDMSR,(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue));
85	/** Pointer to a RDMSR worker for a specific MSR or range of MSRs. */
86	typedef FNCPUMRDMSR *PFNCPUMRDMSR;
87
88
89	/**
90	* Implements writing one or more MSRs.
91	*
92	* @retval VINF_SUCCESS on success.
93	* @retval VINF_CPUM_R3_MSR_WRITE if the MSR write could not be serviced in the
94	* current context (raw-mode or ring-0).
95	* @retval VERR_CPUM_RAISE_GP_0 on failure.
96	*
97	* @param pVCpu The cross context virtual CPU structure.
98	* @param idMsr The MSR we're writing.
99	* @param pRange The MSR range descriptor.
100	* @param uValue The value to set, ignored bits masked.
101	* @param uRawValue The raw value with the ignored bits not masked.
102	*/
103	typedef DECLCALLBACKTYPE(VBOXSTRICTRC, FNCPUMWRMSR,(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange,
104	uint64_t uValue, uint64_t uRawValue));
105	/** Pointer to a WRMSR worker for a specific MSR or range of MSRs. */
106	typedef FNCPUMWRMSR *PFNCPUMWRMSR;
107
108
109
110	/*
111	* Generic functions.
112	* Generic functions.
113	* Generic functions.
114	*/
115
116
117	/** @callback_method_impl{FNCPUMRDMSR} */
118	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_FixedValue(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
119	{
120	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
121	*puValue = pRange->uValue;
122	return VINF_SUCCESS;
123	}
124
125
126	/** @callback_method_impl{FNCPUMWRMSR} */
127	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IgnoreWrite(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
128	{
129	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
130	Log(("CPUM: Ignoring WRMSR %#x (%s), %#llx\n", idMsr, pRange->szName, uValue));
131	return VINF_SUCCESS;
132	}
133
134
135	/** @callback_method_impl{FNCPUMRDMSR} */
136	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_WriteOnly(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
137	{
138	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(puValue);
139	return VERR_CPUM_RAISE_GP_0;
140	}
141
142
143	/** @callback_method_impl{FNCPUMWRMSR} */
144	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_ReadOnly(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
145	{
146	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
147	Assert(pRange->fWrGpMask == UINT64_MAX);
148	return VERR_CPUM_RAISE_GP_0;
149	}
150
151
152
153
154	/*
155	* IA32
156	* IA32
157	* IA32
158	*/
159
160	/** @callback_method_impl{FNCPUMRDMSR} */
161	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32P5McAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
162	{
163	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
164	puValue = 0; /* @todo implement machine check injection. */
165	return VINF_SUCCESS;
166	}
167
168
169	/** @callback_method_impl{FNCPUMWRMSR} */
170	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32P5McAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
171	{
172	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
173	/** @todo implement machine check injection. */
174	return VINF_SUCCESS;
175	}
176
177
178	/** @callback_method_impl{FNCPUMRDMSR} */
179	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32P5McType(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
180	{
181	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
182	puValue = 0; /* @todo implement machine check injection. */
183	return VINF_SUCCESS;
184	}
185
186
187	/** @callback_method_impl{FNCPUMWRMSR} */
188	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32P5McType(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
189	{
190	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
191	/** @todo implement machine check injection. */
192	return VINF_SUCCESS;
193	}
194
195
196	/** @callback_method_impl{FNCPUMRDMSR} */
197	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32TimestampCounter(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
198	{
199	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
200	*puValue = TMCpuTickGet(pVCpu);
201	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
202	puValue = CPUMApplyNestedGuestTscOffset(pVCpu, puValue);
203	#endif
204	return VINF_SUCCESS;
205	}
206
207
208	/** @callback_method_impl{FNCPUMWRMSR} */
209	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32TimestampCounter(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
210	{
211	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
212	TMCpuTickSet(pVCpu->CTX_SUFF(pVM), pVCpu, uValue);
213	return VINF_SUCCESS;
214	}
215
216
217	/** @callback_method_impl{FNCPUMRDMSR} */
218	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PlatformId(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
219	{
220	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
221	uint64_t uValue = pRange->uValue;
222	if (uValue & 0x1f00)
223	{
224	/* Max allowed bus ratio present. */
225	/** @todo Implement scaled BUS frequency. */
226	}
227
228	*puValue = uValue;
229	return VINF_SUCCESS;
230	}
231
232
233	/** @callback_method_impl{FNCPUMRDMSR} */
234	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ApicBase(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
235	{
236	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
237	return PDMApicGetBaseMsr(pVCpu, puValue);
238	}
239
240
241	/** @callback_method_impl{FNCPUMWRMSR} */
242	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ApicBase(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
243	{
244	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
245	return PDMApicSetBaseMsr(pVCpu, uValue);
246	}
247
248
249	/**
250	* Gets IA32_FEATURE_CONTROL value for IEM, NEM and cpumMsrRd_Ia32FeatureControl.
251	*
252	* @returns IA32_FEATURE_CONTROL value.
253	* @param pVCpu The cross context per CPU structure.
254	*/
255	VMM_INT_DECL(uint64_t) CPUMGetGuestIa32FeatCtrl(PCVMCPUCC pVCpu)
256	{
257	uint64_t uFeatCtrlMsr = MSR_IA32_FEATURE_CONTROL_LOCK;
258	if (pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fVmx)
259	uFeatCtrlMsr \|= MSR_IA32_FEATURE_CONTROL_VMXON;
260	return uFeatCtrlMsr;
261	}
262
263
264	/** @callback_method_impl{FNCPUMRDMSR} */
265	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32FeatureControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
266	{
267	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
268	*puValue = CPUMGetGuestIa32FeatCtrl(pVCpu);
269	return VINF_SUCCESS;
270	}
271
272
273	/** @callback_method_impl{FNCPUMWRMSR} */
274	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32FeatureControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
275	{
276	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
277	return VERR_CPUM_RAISE_GP_0;
278	}
279
280
281	/** @callback_method_impl{FNCPUMRDMSR} */
282	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32BiosSignId(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
283	{
284	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
285	/** @todo fake microcode update. */
286	PVM const pVM = pVCpu->CTX_SUFF(pVM);
287	if (pVM->cpum.s.GuestInfo.uMicrocodeRevision != UINT32_MAX)
288	*puValue = RT_MAKE_U64(RT_LO_U32(pRange->uValue), pVM->cpum.s.GuestInfo.uMicrocodeRevision);
289	else
290	*puValue = pRange->uValue;
291	return VINF_SUCCESS;
292	}
293
294
295	/** @callback_method_impl{FNCPUMWRMSR} */
296	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32BiosSignId(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
297	{
298	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
299	/* Normally, zero is written to Ia32BiosSignId before reading it in order
300	to select the signature instead of the BBL_CR_D3 behaviour. The GP mask
301	of the database entry should take care of most illegal writes for now, so
302	just ignore all writes atm. */
303	return VINF_SUCCESS;
304	}
305
306
307	/** @callback_method_impl{FNCPUMWRMSR} */
308	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32BiosUpdateTrigger(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
309	{
310	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
311
312	/* Microcode updates cannot be loaded in VMX non-root mode. */
313	if (CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.s.Guest))
314	return VINF_SUCCESS;
315
316	/** @todo Fake bios update trigger better. The value is the address to an
317	* update package, I think. We should probably GP if it's invalid. */
318	return VINF_SUCCESS;
319	}
320
321
322	/**
323	* Get MSR_IA32_SMM_MONITOR_CTL value for IEM and cpumMsrRd_Ia32SmmMonitorCtl.
324	*
325	* @returns The MSR_IA32_SMM_MONITOR_CTL value.
326	* @param pVCpu The cross context per CPU structure.
327	*/
328	VMM_INT_DECL(uint64_t) CPUMGetGuestIa32SmmMonitorCtl(PCVMCPUCC pVCpu)
329	{
330	/* We do not support dual-monitor treatment for SMI and SMM. */
331	/** @todo SMM. */
332	RT_NOREF(pVCpu);
333	return 0;
334	}
335
336
337	/** @callback_method_impl{FNCPUMRDMSR} */
338	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SmmMonitorCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
339	{
340	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
341	*puValue = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
342	return VINF_SUCCESS;
343	}
344
345
346	/** @callback_method_impl{FNCPUMWRMSR} */
347	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SmmMonitorCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
348	{
349	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
350	/** @todo SMM. */
351	return VINF_SUCCESS;
352	}
353
354
355	/** @callback_method_impl{FNCPUMRDMSR} */
356	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PmcN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
357	{
358	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
359	/** @todo check CPUID leaf 0ah. */
360	*puValue = 0;
361	return VINF_SUCCESS;
362	}
363
364
365	/** @callback_method_impl{FNCPUMWRMSR} */
366	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PmcN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
367	{
368	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
369	/** @todo check CPUID leaf 0ah. */
370	return VINF_SUCCESS;
371	}
372
373
374	/** @callback_method_impl{FNCPUMRDMSR} */
375	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MonitorFilterLineSize(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
376	{
377	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
378	/** @todo return 0x1000 if we try emulate mwait 100% correctly. */
379	puValue = 0x40; /* @todo Change to CPU cache line size. */
380	return VINF_SUCCESS;
381	}
382
383
384	/** @callback_method_impl{FNCPUMWRMSR} */
385	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MonitorFilterLineSize(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
386	{
387	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
388	/** @todo should remember writes, though it's supposedly something only a BIOS
389	* would write so, it's not extremely important. */
390	return VINF_SUCCESS;
391	}
392
393	/** @callback_method_impl{FNCPUMRDMSR} */
394	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MPerf(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
395	{
396	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
397	/** @todo Read MPERF: Adjust against previously written MPERF value. Is TSC
398	* what we want? */
399	*puValue = TMCpuTickGet(pVCpu);
400	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
401	puValue = CPUMApplyNestedGuestTscOffset(pVCpu, puValue);
402	#endif
403	return VINF_SUCCESS;
404	}
405
406
407	/** @callback_method_impl{FNCPUMWRMSR} */
408	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MPerf(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
409	{
410	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
411	/** @todo Write MPERF: Calc adjustment. */
412	return VINF_SUCCESS;
413	}
414
415
416	/** @callback_method_impl{FNCPUMRDMSR} */
417	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32APerf(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
418	{
419	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
420	/** @todo Read APERF: Adjust against previously written MPERF value. Is TSC
421	* what we want? */
422	*puValue = TMCpuTickGet(pVCpu);
423	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
424	puValue = CPUMApplyNestedGuestTscOffset(pVCpu, puValue);
425	#endif
426	return VINF_SUCCESS;
427	}
428
429
430	/** @callback_method_impl{FNCPUMWRMSR} */
431	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32APerf(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
432	{
433	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
434	/** @todo Write APERF: Calc adjustment. */
435	return VINF_SUCCESS;
436	}
437
438
439	/**
440	* Get fixed IA32_MTRR_CAP value for NEM and cpumMsrRd_Ia32MtrrCap.
441	*
442	* @returns Fixed IA32_MTRR_CAP value.
443	* @param pVCpu The cross context per CPU structure.
444	*/
445	VMM_INT_DECL(uint64_t) CPUMGetGuestIa32MtrrCap(PCVMCPUCC pVCpu)
446	{
447	if (pVCpu->CTX_SUFF(pVM)->cpum.s.fMtrrRead)
448	return pVCpu->cpum.s.GuestMsrs.msr.MtrrCap;
449
450	/* This is currently a bit weird. :-) */
451	uint8_t const cVariableRangeRegs = 0;
452	bool const fSystemManagementRangeRegisters = false;
453	bool const fFixedRangeRegisters = false;
454	bool const fWriteCombiningType = false;
455	bool const fProcRsvdRangeRegisters = false;
456	return cVariableRangeRegs
457	\| (fFixedRangeRegisters ? MSR_IA32_MTRR_CAP_FIX : 0)
458	\| (fWriteCombiningType ? MSR_IA32_MTRR_CAP_WC : 0)
459	\| (fSystemManagementRangeRegisters ? MSR_IA32_MTRR_CAP_SMRR : 0)
460	\| (fProcRsvdRangeRegisters ? MSR_IA32_MTRR_CAP_PRMRR : 0);
461	}
462
463	/** @callback_method_impl{FNCPUMRDMSR} */
464	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrCap(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
465	{
466	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
467	*puValue = CPUMGetGuestIa32MtrrCap(pVCpu);
468	return VINF_SUCCESS;
469	}
470
471
472	/** @callback_method_impl{FNCPUMRDMSR} */
473	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrPhysBaseN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
474	{
475	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
476	Assert(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fMtrr);
477	Assert(pRange->uValue == (idMsr - MSR_IA32_MTRR_PHYSBASE0) / 2);
478	if (pVCpu->CTX_SUFF(pVM)->cpum.s.fMtrrRead)
479	{
480	AssertLogRelMsgReturn(pRange->uValue < RT_ELEMENTS(pVCpu->cpum.s.GuestMsrs.msr.aMtrrVarMsrs),
481	("MTRR MSR (%#RX32) out-of-bounds, must be <= %#RX32\n", idMsr, CPUMCTX_MAX_MTRRVAR_COUNT),
482	VERR_CPUM_RAISE_GP_0);
483	AssertLogRelMsgReturn(!(idMsr % 2),
484	("MTRR MSR (%#RX32) invalid, must be at even offset\n", idMsr), VERR_CPUM_RAISE_GP_0);
485	*puValue = pVCpu->cpum.s.GuestMsrs.msr.aMtrrVarMsrs[pRange->uValue].MtrrPhysBase;
486	}
487	else
488	*puValue = 0;
489	return VINF_SUCCESS;
490	}
491
492
493	/** @callback_method_impl{FNCPUMWRMSR} */
494	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrPhysBaseN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
495	{
496	/*
497	* Validate the value.
498	*/
499	Assert(pRange->uValue == (idMsr - MSR_IA32_MTRR_PHYSBASE0) / 2);
500	RT_NOREF_PV(uRawValue);
501	Assert(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fMtrr);
502
503	uint8_t uType = uValue & 0xff;
504	if ((uType >= 7) \|\| (uType == 2) \|\| (uType == 3))
505	{
506	Log(("CPUM: Invalid type set writing MTRR PhysBase MSR %#x: %#llx (%#llx)\n", idMsr, uValue, uType));
507	return VERR_CPUM_RAISE_GP_0;
508	}
509
510	uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
511	if (fInvPhysMask & uValue)
512	{
513	Log(("CPUM: Invalid physical address bits set writing MTRR PhysBase MSR %#x: %#llx (%#llx)\n",
514	idMsr, uValue, uValue & fInvPhysMask));
515	return VERR_CPUM_RAISE_GP_0;
516	}
517
518	/*
519	* Store it.
520	*/
521	if (pVCpu->CTX_SUFF(pVM)->cpum.s.fMtrrWrite)
522	{
523	AssertCompile(CPUMCTX_MAX_MTRRVAR_COUNT == RT_ELEMENTS(pVCpu->cpum.s.GuestMsrs.msr.aMtrrVarMsrs));
524	AssertLogRelMsgReturn(pRange->uValue < CPUMCTX_MAX_MTRRVAR_COUNT,
525	("MTRR MSR (%#RX32) out-of-bounds, must be <= %#RX32\n", idMsr, CPUMCTX_MAX_MTRRVAR_COUNT),
526	VERR_CPUM_RAISE_GP_0);
527	AssertLogRelMsgReturn(!(idMsr % 2),
528	("MTRR MSR (%#RX32) invalid, must be at even offset\n", idMsr), VERR_CPUM_RAISE_GP_0);
529	pVCpu->cpum.s.GuestMsrs.msr.aMtrrVarMsrs[pRange->uValue].MtrrPhysBase = uValue;
530	/** @todo Act on the potential memory type change. */
531	}
532	return VINF_SUCCESS;
533	}
534
535
536	/** @callback_method_impl{FNCPUMRDMSR} */
537	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrPhysMaskN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
538	{
539	RT_NOREF_PV(idMsr);
540	Assert(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fMtrr);
541	Assert(pRange->uValue == (idMsr - MSR_IA32_MTRR_PHYSBASE0) / 2);
542	if (pVCpu->CTX_SUFF(pVM)->cpum.s.fMtrrRead)
543	{
544	AssertLogRelMsgReturn(pRange->uValue < RT_ELEMENTS(pVCpu->cpum.s.GuestMsrs.msr.aMtrrVarMsrs),
545	("MTRR MSR (%#RX32) out-of-bounds, must be <= %#RX32\n", idMsr, CPUMCTX_MAX_MTRRVAR_COUNT),
546	VERR_CPUM_RAISE_GP_0);
547	AssertLogRelMsgReturn(idMsr % 2,
548	("MTRR MSR (%#RX32) invalid, must be at odd offset\n", idMsr), VERR_CPUM_RAISE_GP_0);
549	*puValue = pVCpu->cpum.s.GuestMsrs.msr.aMtrrVarMsrs[pRange->uValue].MtrrPhysMask;
550	}
551	else
552	*puValue = 0;
553	return VINF_SUCCESS;
554	}
555
556
557	/** @callback_method_impl{FNCPUMWRMSR} */
558	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrPhysMaskN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
559	{
560	/*
561	* Validate the value.
562	*/
563	Assert(pRange->uValue == (idMsr - MSR_IA32_MTRR_PHYSBASE0) / 2);
564	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(uRawValue); RT_NOREF_PV(pRange);
565	Assert(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fMtrr);
566
567	uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
568	if (fInvPhysMask & uValue)
569	{
570	Log(("CPUM: Invalid physical address bits set writing MTRR PhysMask MSR %#x: %#llx (%#llx)\n",
571	idMsr, uValue, uValue & fInvPhysMask));
572	return VERR_CPUM_RAISE_GP_0;
573	}
574
575	/*
576	* Store it.
577	*/
578	if (pVCpu->CTX_SUFF(pVM)->cpum.s.fMtrrWrite)
579	{
580	AssertLogRelMsgReturn(pRange->uValue < RT_ELEMENTS(pVCpu->cpum.s.GuestMsrs.msr.aMtrrVarMsrs),
581	("MTRR MSR (%#RX32) out-of-bounds, must be <= %#RX32\n", idMsr, CPUMCTX_MAX_MTRRVAR_COUNT),
582	VERR_CPUM_RAISE_GP_0);
583	AssertLogRelMsgReturn(idMsr % 2,
584	("MTRR MSR (%#RX32) invalid, must be at odd offset\n", idMsr), VERR_CPUM_RAISE_GP_0);
585	pVCpu->cpum.s.GuestMsrs.msr.aMtrrVarMsrs[pRange->uValue].MtrrPhysMask = uValue;
586	/** @todo Act on the potential memory type change. */
587	}
588	return VINF_SUCCESS;
589	}
590
591
592	/** @callback_method_impl{FNCPUMRDMSR} */
593	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrFixed(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
594	{
595	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
596	CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(pVCpu, pRange, uint64_t, puFixedMtrr);
597	Assert(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fMtrr);
598	puValue = puFixedMtrr;
599	return VINF_SUCCESS;
600	}
601
602
603	/** @callback_method_impl{FNCPUMWRMSR} */
604	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrFixed(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
605	{
606	CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(pVCpu, pRange, uint64_t, puFixedMtrr);
607	RT_NOREF_PV(idMsr); RT_NOREF_PV(uRawValue);
608	Assert(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fMtrr);
609
610	for (uint32_t cShift = 0; cShift < 63; cShift += 8)
611	{
612	uint8_t uType = (uint8_t)(uValue >> cShift);
613	if ((uType >= 7) \|\| (uType == 2) \|\| (uType == 3))
614	{
615	Log(("CPUM: Invalid MTRR type at %u:%u in fixed range (%#x/%s): %#llx (%#llx)\n",
616	cShift + 7, cShift, idMsr, pRange->szName, uValue, uType));
617	return VERR_CPUM_RAISE_GP_0;
618	}
619	}
620	*puFixedMtrr = uValue;
621	return VINF_SUCCESS;
622	}
623
624
625	/** @callback_method_impl{FNCPUMRDMSR} */
626	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrDefType(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
627	{
628	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
629	Assert(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fMtrr);
630	*puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType;
631	return VINF_SUCCESS;
632	}
633
634
635	/** @callback_method_impl{FNCPUMWRMSR} */
636	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrDefType(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
637	{
638	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
639	Assert(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fMtrr);
640
641	uint8_t uType = uValue & MSR_IA32_MTRR_DEF_TYPE_DEF_MT_MASK;
642	if ((uType >= 7) \|\| (uType == 2) \|\| (uType == 3))
643	{
644	Log(("CPUM: Invalid MTRR default type value on %s: %#llx (%#llx)\n", pRange->szName, uValue, uType));
645	return VERR_CPUM_RAISE_GP_0;
646	}
647
648	pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType = uValue;
649	return VINF_SUCCESS;
650	}
651
652
653	/** @callback_method_impl{FNCPUMRDMSR} */
654	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32Pat(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
655	{
656	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
657	*puValue = pVCpu->cpum.s.Guest.msrPAT;
658	return VINF_SUCCESS;
659	}
660
661
662	/** @callback_method_impl{FNCPUMWRMSR} */
663	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32Pat(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
664	{
665	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
666	if (CPUMIsPatMsrValid(uValue))
667	{
668	pVCpu->cpum.s.Guest.msrPAT = uValue;
669	return VINF_SUCCESS;
670	}
671	return VERR_CPUM_RAISE_GP_0;
672	}
673
674
675	/** @callback_method_impl{FNCPUMRDMSR} */
676	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SysEnterCs(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
677	{
678	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
679	*puValue = pVCpu->cpum.s.Guest.SysEnter.cs;
680	return VINF_SUCCESS;
681	}
682
683
684	/** @callback_method_impl{FNCPUMWRMSR} */
685	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SysEnterCs(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
686	{
687	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
688
689	/* Note! We used to mask this by 0xffff, but turns out real HW doesn't and
690	there are generally 32-bit working bits backing this register. */
691	pVCpu->cpum.s.Guest.SysEnter.cs = uValue;
692	return VINF_SUCCESS;
693	}
694
695
696	/** @callback_method_impl{FNCPUMRDMSR} */
697	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SysEnterEsp(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
698	{
699	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
700	*puValue = pVCpu->cpum.s.Guest.SysEnter.esp;
701	return VINF_SUCCESS;
702	}
703
704
705	/** @callback_method_impl{FNCPUMWRMSR} */
706	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SysEnterEsp(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
707	{
708	if (X86_IS_CANONICAL(uValue))
709	{
710	pVCpu->cpum.s.Guest.SysEnter.esp = uValue;
711	return VINF_SUCCESS;
712	}
713	Log(("CPUM: IA32_SYSENTER_ESP not canonical! %#llx\n", uValue));
714	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
715	return VERR_CPUM_RAISE_GP_0;
716	}
717
718
719	/** @callback_method_impl{FNCPUMRDMSR} */
720	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SysEnterEip(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
721	{
722	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
723	*puValue = pVCpu->cpum.s.Guest.SysEnter.eip;
724	return VINF_SUCCESS;
725	}
726
727
728	/** @callback_method_impl{FNCPUMWRMSR} */
729	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SysEnterEip(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
730	{
731	if (X86_IS_CANONICAL(uValue))
732	{
733	pVCpu->cpum.s.Guest.SysEnter.eip = uValue;
734	return VINF_SUCCESS;
735	}
736	LogRel(("CPUM: IA32_SYSENTER_EIP not canonical! %#llx\n", uValue));
737	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
738	return VERR_CPUM_RAISE_GP_0;
739	}
740
741
742	/** @callback_method_impl{FNCPUMRDMSR} */
743	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McgCap(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
744	{
745	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
746	#if 0 /** @todo implement machine checks. */
747	*puValue = pRange->uValue & (RT_BIT_64(8) \| 0);
748	#else
749	*puValue = 0;
750	#endif
751	return VINF_SUCCESS;
752	}
753
754
755	/** @callback_method_impl{FNCPUMRDMSR} */
756	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McgStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
757	{
758	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
759	/** @todo implement machine checks. */
760	*puValue = 0;
761	return VINF_SUCCESS;
762	}
763
764
765	/** @callback_method_impl{FNCPUMWRMSR} */
766	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McgStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
767	{
768	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
769	/** @todo implement machine checks. */
770	return VINF_SUCCESS;
771	}
772
773
774	/** @callback_method_impl{FNCPUMRDMSR} */
775	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McgCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
776	{
777	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
778	/** @todo implement machine checks. */
779	*puValue = 0;
780	return VINF_SUCCESS;
781	}
782
783
784	/** @callback_method_impl{FNCPUMWRMSR} */
785	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McgCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
786	{
787	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
788	/** @todo implement machine checks. */
789	return VINF_SUCCESS;
790	}
791
792
793	/** @callback_method_impl{FNCPUMRDMSR} */
794	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32DebugCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
795	{
796	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
797	/** @todo implement IA32_DEBUGCTL. */
798	*puValue = 0;
799	return VINF_SUCCESS;
800	}
801
802
803	/** @callback_method_impl{FNCPUMWRMSR} */
804	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32DebugCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
805	{
806	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
807	/** @todo implement IA32_DEBUGCTL. */
808	return VINF_SUCCESS;
809	}
810
811
812	/** @callback_method_impl{FNCPUMRDMSR} */
813	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SmrrPhysBase(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
814	{
815	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
816	/** @todo implement intel SMM. */
817	*puValue = 0;
818	return VINF_SUCCESS;
819	}
820
821
822	/** @callback_method_impl{FNCPUMWRMSR} */
823	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SmrrPhysBase(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
824	{
825	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
826	/** @todo implement intel SMM. */
827	return VERR_CPUM_RAISE_GP_0;
828	}
829
830
831	/** @callback_method_impl{FNCPUMRDMSR} */
832	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SmrrPhysMask(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
833	{
834	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
835	/** @todo implement intel SMM. */
836	*puValue = 0;
837	return VINF_SUCCESS;
838	}
839
840
841	/** @callback_method_impl{FNCPUMWRMSR} */
842	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SmrrPhysMask(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
843	{
844	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
845	/** @todo implement intel SMM. */
846	return VERR_CPUM_RAISE_GP_0;
847	}
848
849
850	/** @callback_method_impl{FNCPUMRDMSR} */
851	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PlatformDcaCap(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
852	{
853	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
854	/** @todo implement intel direct cache access (DCA)?? */
855	*puValue = 0;
856	return VINF_SUCCESS;
857	}
858
859
860	/** @callback_method_impl{FNCPUMWRMSR} */
861	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PlatformDcaCap(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
862	{
863	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
864	/** @todo implement intel direct cache access (DCA)?? */
865	return VINF_SUCCESS;
866	}
867
868
869	/** @callback_method_impl{FNCPUMRDMSR} */
870	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32CpuDcaCap(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
871	{
872	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
873	/** @todo implement intel direct cache access (DCA)?? */
874	*puValue = 0;
875	return VINF_SUCCESS;
876	}
877
878
879	/** @callback_method_impl{FNCPUMRDMSR} */
880	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32Dca0Cap(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
881	{
882	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
883	/** @todo implement intel direct cache access (DCA)?? */
884	*puValue = 0;
885	return VINF_SUCCESS;
886	}
887
888
889	/** @callback_method_impl{FNCPUMWRMSR} */
890	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32Dca0Cap(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
891	{
892	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
893	/** @todo implement intel direct cache access (DCA)?? */
894	return VINF_SUCCESS;
895	}
896
897
898	/** @callback_method_impl{FNCPUMRDMSR} */
899	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfEvtSelN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
900	{
901	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
902	/** @todo implement IA32_PERFEVTSEL0+. */
903	*puValue = 0;
904	return VINF_SUCCESS;
905	}
906
907
908	/** @callback_method_impl{FNCPUMWRMSR} */
909	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfEvtSelN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
910	{
911	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
912	/** @todo implement IA32_PERFEVTSEL0+. */
913	return VINF_SUCCESS;
914	}
915
916
917	/** @callback_method_impl{FNCPUMRDMSR} */
918	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
919	{
920	RT_NOREF_PV(idMsr);
921	uint64_t uValue = pRange->uValue;
922
923	/* Always provide the max bus ratio for now. XNU expects it. */
924	uValue &= ~((UINT64_C(0x1f) << 40) \| RT_BIT_64(46));
925
926	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
927	uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
928	uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
929	uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
930	if (uTscRatio > 0x1f)
931	uTscRatio = 0x1f;
932	uValue \|= (uint64_t)uTscRatio << 40;
933
934	*puValue = uValue;
935	return VINF_SUCCESS;
936	}
937
938
939	/** @callback_method_impl{FNCPUMWRMSR} */
940	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
941	{
942	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
943	/* Pentium4 allows writing, but all bits are ignored. */
944	return VINF_SUCCESS;
945	}
946
947
948	/** @callback_method_impl{FNCPUMRDMSR} */
949	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
950	{
951	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
952	/** @todo implement IA32_PERFCTL. */
953	*puValue = 0;
954	return VINF_SUCCESS;
955	}
956
957
958	/** @callback_method_impl{FNCPUMWRMSR} */
959	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
960	{
961	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
962	/** @todo implement IA32_PERFCTL. */
963	return VINF_SUCCESS;
964	}
965
966
967	/** @callback_method_impl{FNCPUMRDMSR} */
968	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32FixedCtrN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
969	{
970	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
971	/** @todo implement IA32_FIXED_CTRn (fixed performance counters). */
972	*puValue = 0;
973	return VINF_SUCCESS;
974	}
975
976
977	/** @callback_method_impl{FNCPUMWRMSR} */
978	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32FixedCtrN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
979	{
980	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
981	/** @todo implement IA32_FIXED_CTRn (fixed performance counters). */
982	return VINF_SUCCESS;
983	}
984
985
986	/** @callback_method_impl{FNCPUMRDMSR} */
987	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfCapabilities(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
988	{
989	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
990	/** @todo implement performance counters. */
991	*puValue = 0;
992	return VINF_SUCCESS;
993	}
994
995
996	/** @callback_method_impl{FNCPUMWRMSR} */
997	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfCapabilities(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
998	{
999	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1000	/** @todo implement performance counters. */
1001	return VINF_SUCCESS;
1002	}
1003
1004
1005	/** @callback_method_impl{FNCPUMRDMSR} */
1006	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32FixedCtrCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1007	{
1008	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1009	/** @todo implement performance counters. */
1010	*puValue = 0;
1011	return VINF_SUCCESS;
1012	}
1013
1014
1015	/** @callback_method_impl{FNCPUMWRMSR} */
1016	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32FixedCtrCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1017	{
1018	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1019	/** @todo implement performance counters. */
1020	return VINF_SUCCESS;
1021	}
1022
1023
1024	/** @callback_method_impl{FNCPUMRDMSR} */
1025	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfGlobalStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1026	{
1027	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1028	/** @todo implement performance counters. */
1029	*puValue = 0;
1030	return VINF_SUCCESS;
1031	}
1032
1033
1034	/** @callback_method_impl{FNCPUMWRMSR} */
1035	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfGlobalStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1036	{
1037	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1038	/** @todo implement performance counters. */
1039	return VINF_SUCCESS;
1040	}
1041
1042
1043	/** @callback_method_impl{FNCPUMRDMSR} */
1044	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfGlobalCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1045	{
1046	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1047	/** @todo implement performance counters. */
1048	*puValue = 0;
1049	return VINF_SUCCESS;
1050	}
1051
1052
1053	/** @callback_method_impl{FNCPUMWRMSR} */
1054	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfGlobalCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1055	{
1056	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1057	/** @todo implement performance counters. */
1058	return VINF_SUCCESS;
1059	}
1060
1061
1062	/** @callback_method_impl{FNCPUMRDMSR} */
1063	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfGlobalOvfCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1064	{
1065	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1066	/** @todo implement performance counters. */
1067	*puValue = 0;
1068	return VINF_SUCCESS;
1069	}
1070
1071
1072	/** @callback_method_impl{FNCPUMWRMSR} */
1073	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfGlobalOvfCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1074	{
1075	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1076	/** @todo implement performance counters. */
1077	return VINF_SUCCESS;
1078	}
1079
1080
1081	/** @callback_method_impl{FNCPUMRDMSR} */
1082	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PebsEnable(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1083	{
1084	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1085	/** @todo implement performance counters. */
1086	*puValue = 0;
1087	return VINF_SUCCESS;
1088	}
1089
1090
1091	/** @callback_method_impl{FNCPUMWRMSR} */
1092	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PebsEnable(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1093	{
1094	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1095	/** @todo implement performance counters. */
1096	return VINF_SUCCESS;
1097	}
1098
1099
1100	/** @callback_method_impl{FNCPUMRDMSR} */
1101	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ClockModulation(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1102	{
1103	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1104	/** @todo implement IA32_CLOCK_MODULATION. */
1105	*puValue = 0;
1106	return VINF_SUCCESS;
1107	}
1108
1109
1110	/** @callback_method_impl{FNCPUMWRMSR} */
1111	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ClockModulation(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1112	{
1113	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1114	/** @todo implement IA32_CLOCK_MODULATION. */
1115	return VINF_SUCCESS;
1116	}
1117
1118
1119	/** @callback_method_impl{FNCPUMRDMSR} */
1120	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ThermInterrupt(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1121	{
1122	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1123	/** @todo implement IA32_THERM_INTERRUPT. */
1124	*puValue = 0;
1125	return VINF_SUCCESS;
1126	}
1127
1128
1129	/** @callback_method_impl{FNCPUMWRMSR} */
1130	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ThermInterrupt(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1131	{
1132	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1133	/** @todo implement IA32_THERM_STATUS. */
1134	return VINF_SUCCESS;
1135	}
1136
1137
1138	/** @callback_method_impl{FNCPUMRDMSR} */
1139	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ThermStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1140	{
1141	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1142	/** @todo implement IA32_THERM_STATUS. */
1143	*puValue = 0;
1144	return VINF_SUCCESS;
1145	}
1146
1147
1148	/** @callback_method_impl{FNCPUMWRMSR} */
1149	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ThermStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1150	{
1151	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1152	/** @todo implement IA32_THERM_INTERRUPT. */
1153	return VINF_SUCCESS;
1154	}
1155
1156
1157	/** @callback_method_impl{FNCPUMRDMSR} */
1158	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32Therm2Ctl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1159	{
1160	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1161	/** @todo implement IA32_THERM2_CTL. */
1162	*puValue = 0;
1163	return VINF_SUCCESS;
1164	}
1165
1166
1167	/** @callback_method_impl{FNCPUMWRMSR} */
1168	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32Therm2Ctl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1169	{
1170	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1171	/** @todo implement IA32_THERM2_CTL. */
1172	return VINF_SUCCESS;
1173	}
1174
1175
1176	/** @callback_method_impl{FNCPUMRDMSR} */
1177	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MiscEnable(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1178	{
1179	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1180	*puValue = pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
1181	return VINF_SUCCESS;
1182	}
1183
1184
1185	/** @callback_method_impl{FNCPUMWRMSR} */
1186	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MiscEnable(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1187	{
1188	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1189	#ifdef LOG_ENABLED
1190	uint64_t const uOld = pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
1191	#endif
1192
1193	/* Unsupported bits are generally ignored and stripped by the MSR range
1194	entry that got us here. So, we just need to preserve fixed bits. */
1195	pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = uValue
1196	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
1197	\| MSR_IA32_MISC_ENABLE_BTS_UNAVAIL;
1198
1199	Log(("CPUM: IA32_MISC_ENABLE; old=%#llx written=%#llx => %#llx\n",
1200	uOld, uValue, pVCpu->cpum.s.GuestMsrs.msr.MiscEnable));
1201
1202	/** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
1203	/** @todo Wire up MSR_IA32_MISC_ENABLE_XD_DISABLE. */
1204	return VINF_SUCCESS;
1205	}
1206
1207
1208	/** @callback_method_impl{FNCPUMRDMSR} */
1209	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McCtlStatusAddrMiscN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1210	{
1211	RT_NOREF_PV(pVCpu); RT_NOREF_PV(pRange);
1212
1213	/** @todo Implement machine check exception injection. */
1214	switch (idMsr & 3)
1215	{
1216	case 0:
1217	case 1:
1218	*puValue = 0;
1219	break;
1220
1221	/* The ADDR and MISC registers aren't accessible since the
1222	corresponding STATUS bits are zero. */
1223	case 2:
1224	Log(("CPUM: Reading IA32_MCi_ADDR %#x -> #GP\n", idMsr));
1225	return VERR_CPUM_RAISE_GP_0;
1226	case 3:
1227	Log(("CPUM: Reading IA32_MCi_MISC %#x -> #GP\n", idMsr));
1228	return VERR_CPUM_RAISE_GP_0;
1229	}
1230	return VINF_SUCCESS;
1231	}
1232
1233
1234	/** @callback_method_impl{FNCPUMWRMSR} */
1235	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McCtlStatusAddrMiscN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1236	{
1237	RT_NOREF_PV(pVCpu); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1238	switch (idMsr & 3)
1239	{
1240	case 0:
1241	/* Ignore writes to the CTL register. */
1242	break;
1243
1244	case 1:
1245	/* According to specs, the STATUS register can only be written to
1246	with the value 0. VBoxCpuReport thinks different for a
1247	Pentium M Dothan, but implementing according to specs now. */
1248	if (uValue != 0)
1249	{
1250	Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_STATUS %#x -> #GP\n", uValue, idMsr));
1251	return VERR_CPUM_RAISE_GP_0;
1252	}
1253	break;
1254
1255	/* Specs states that ADDR and MISC can be cleared by writing zeros.
1256	Writing 1s will GP. Need to figure out how this relates to the
1257	ADDRV and MISCV status flags. If writing is independent of those
1258	bits, we need to know whether the CPU really implements them since
1259	that is exposed by writing 0 to them.
1260	Implementing the solution with the fewer GPs for now. */
1261	case 2:
1262	if (uValue != 0)
1263	{
1264	Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_ADDR %#x -> #GP\n", uValue, idMsr));
1265	return VERR_CPUM_RAISE_GP_0;
1266	}
1267	break;
1268	case 3:
1269	if (uValue != 0)
1270	{
1271	Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_MISC %#x -> #GP\n", uValue, idMsr));
1272	return VERR_CPUM_RAISE_GP_0;
1273	}
1274	break;
1275	}
1276	return VINF_SUCCESS;
1277	}
1278
1279
1280	/** @callback_method_impl{FNCPUMRDMSR} */
1281	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McNCtl2(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1282	{
1283	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1284	/** @todo Implement machine check exception injection. */
1285	*puValue = 0;
1286	return VINF_SUCCESS;
1287	}
1288
1289
1290	/** @callback_method_impl{FNCPUMWRMSR} */
1291	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McNCtl2(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1292	{
1293	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1294	/** @todo Implement machine check exception injection. */
1295	return VINF_SUCCESS;
1296	}
1297
1298
1299	/** @callback_method_impl{FNCPUMRDMSR} */
1300	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32DsArea(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1301	{
1302	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1303	/** @todo implement IA32_DS_AREA. */
1304	*puValue = 0;
1305	return VINF_SUCCESS;
1306	}
1307
1308
1309	/** @callback_method_impl{FNCPUMWRMSR} */
1310	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32DsArea(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1311	{
1312	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1313	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1314	return VINF_SUCCESS;
1315	}
1316
1317
1318	/** @callback_method_impl{FNCPUMRDMSR} */
1319	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32TscDeadline(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1320	{
1321	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1322	/** @todo implement TSC deadline timer. */
1323	*puValue = 0;
1324	return VINF_SUCCESS;
1325	}
1326
1327
1328	/** @callback_method_impl{FNCPUMWRMSR} */
1329	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32TscDeadline(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1330	{
1331	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1332	/** @todo implement TSC deadline timer. */
1333	return VINF_SUCCESS;
1334	}
1335
1336
1337	/** @callback_method_impl{FNCPUMRDMSR} */
1338	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32X2ApicN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1339	{
1340	RT_NOREF_PV(pRange);
1341	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1342	if ( CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.s.Guest)
1343	&& CPUMIsGuestVmxProcCtls2Set(&pVCpu->cpum.s.Guest, VMX_PROC_CTLS2_VIRT_X2APIC_MODE))
1344	{
1345	VBOXSTRICTRC rcStrict = IEMExecVmxVirtApicAccessMsr(pVCpu, idMsr, puValue, false /* fWrite */);
1346	if (rcStrict == VINF_VMX_MODIFIES_BEHAVIOR)
1347	return VINF_SUCCESS;
1348	if (rcStrict == VERR_OUT_OF_RANGE)
1349	return VERR_CPUM_RAISE_GP_0;
1350	Assert(rcStrict == VINF_VMX_INTERCEPT_NOT_ACTIVE);
1351	}
1352	#endif
1353	return PDMApicReadMsr(pVCpu, idMsr, puValue);
1354	}
1355
1356
1357	/** @callback_method_impl{FNCPUMWRMSR} */
1358	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32X2ApicN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1359	{
1360	RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1361	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1362	if ( CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.s.Guest)
1363	&& CPUMIsGuestVmxProcCtls2Set(&pVCpu->cpum.s.Guest, VMX_PROC_CTLS2_VIRT_X2APIC_MODE))
1364	{
1365	VBOXSTRICTRC rcStrict = IEMExecVmxVirtApicAccessMsr(pVCpu, idMsr, &uValue, true /* fWrite */);
1366	if (rcStrict == VINF_VMX_MODIFIES_BEHAVIOR)
1367	return VINF_SUCCESS;
1368	if (rcStrict == VERR_OUT_OF_RANGE)
1369	return VERR_CPUM_RAISE_GP_0;
1370	Assert(rcStrict == VINF_VMX_INTERCEPT_NOT_ACTIVE);
1371	}
1372	#endif
1373	return PDMApicWriteMsr(pVCpu, idMsr, uValue);
1374	}
1375
1376
1377	/** @callback_method_impl{FNCPUMRDMSR} */
1378	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32DebugInterface(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1379	{
1380	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1381	/** @todo IA32_DEBUG_INTERFACE (no docs) */
1382	*puValue = 0;
1383	return VINF_SUCCESS;
1384	}
1385
1386
1387	/** @callback_method_impl{FNCPUMWRMSR} */
1388	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32DebugInterface(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1389	{
1390	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1391	/** @todo IA32_DEBUG_INTERFACE (no docs) */
1392	return VINF_SUCCESS;
1393	}
1394
1395
1396	/** @callback_method_impl{FNCPUMRDMSR} */
1397	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxBasic(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1398	{
1399	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1400	if (pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fVmx)
1401	*puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Basic;
1402	else
1403	*puValue = 0;
1404	return VINF_SUCCESS;
1405	}
1406
1407
1408	/** @callback_method_impl{FNCPUMRDMSR} */
1409	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxPinbasedCtls(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1410	{
1411	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1412	if (pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fVmx)
1413	*puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.PinCtls.u;
1414	else
1415	*puValue = 0;
1416	return VINF_SUCCESS;
1417	}
1418
1419	/** @callback_method_impl{FNCPUMRDMSR} */
1420	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxProcbasedCtls(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1421	{
1422	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1423	if (pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fVmx)
1424	*puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.ProcCtls.u;
1425	else
1426	*puValue = 0;
1427	return VINF_SUCCESS;
1428	}
1429
1430
1431	/** @callback_method_impl{FNCPUMRDMSR} */
1432	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxExitCtls(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1433	{
1434	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1435	if (pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fVmx)
1436	*puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.ExitCtls.u;
1437	else
1438	*puValue = 0;
1439	return VINF_SUCCESS;
1440	}
1441
1442
1443	/** @callback_method_impl{FNCPUMRDMSR} */
1444	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxEntryCtls(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1445	{
1446	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1447	if (pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fVmx)
1448	*puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.EntryCtls.u;
1449	else
1450	*puValue = 0;
1451	return VINF_SUCCESS;
1452	}
1453
1454
1455
1456	/** @callback_method_impl{FNCPUMRDMSR} */
1457	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxMisc(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1458	{
1459	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1460	if (pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fVmx)
1461	*puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Misc;
1462	else
1463	*puValue = 0;
1464	return VINF_SUCCESS;
1465	}
1466
1467
1468	/** @callback_method_impl{FNCPUMRDMSR} */
1469	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr0Fixed0(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1470	{
1471	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1472	if (pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fVmx)
1473	*puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Cr0Fixed0;
1474	else
1475	*puValue = 0;
1476	return VINF_SUCCESS;
1477	}
1478
1479
1480	/** @callback_method_impl{FNCPUMRDMSR} */
1481	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr0Fixed1(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1482	{
1483	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1484	if (pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fVmx)
1485	*puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Cr0Fixed1;
1486	else
1487	*puValue = 0;
1488	return VINF_SUCCESS;
1489	}
1490
1491
1492	/** @callback_method_impl{FNCPUMRDMSR} */
1493	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr4Fixed0(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1494	{
1495	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1496	if (pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fVmx)
1497	*puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Cr4Fixed0;
1498	else
1499	*puValue = 0;
1500	return VINF_SUCCESS;
1501	}
1502
1503
1504	/** @callback_method_impl{FNCPUMRDMSR} */
1505	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr4Fixed1(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1506	{
1507	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1508	if (pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fVmx)
1509	*puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Cr4Fixed1;
1510	else
1511	*puValue = 0;
1512	return VINF_SUCCESS;
1513	}
1514
1515
1516	/** @callback_method_impl{FNCPUMRDMSR} */
1517	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxVmcsEnum(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1518	{
1519	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1520	if (pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fVmx)
1521	*puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64VmcsEnum;
1522	else
1523	*puValue = 0;
1524	return VINF_SUCCESS;
1525	}
1526
1527
1528	/** @callback_method_impl{FNCPUMRDMSR} */
1529	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxProcBasedCtls2(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1530	{
1531	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1532	if (pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fVmx)
1533	*puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.ProcCtls2.u;
1534	else
1535	*puValue = 0;
1536	return VINF_SUCCESS;
1537	}
1538
1539
1540	/**
1541	* Get fixed IA32_VMX_EPT_VPID_CAP value for PGM and cpumMsrRd_Ia32VmxEptVpidCap.
1542	*
1543	* @returns Fixed IA32_VMX_EPT_VPID_CAP value.
1544	* @param pVCpu The cross context per CPU structure.
1545	*/
1546	VMM_INT_DECL(uint64_t) CPUMGetGuestIa32VmxEptVpidCap(PCVMCPUCC pVCpu)
1547	{
1548	if (pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fVmx)
1549	return pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64EptVpidCaps;
1550	return 0;
1551	}
1552
1553
1554	/** @callback_method_impl{FNCPUMRDMSR} */
1555	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxEptVpidCap(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1556	{
1557	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1558	*puValue = CPUMGetGuestIa32VmxEptVpidCap(pVCpu);
1559	return VINF_SUCCESS;
1560	}
1561
1562
1563	/** @callback_method_impl{FNCPUMRDMSR} */
1564	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTruePinbasedCtls(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1565	{
1566	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1567	if (pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fVmx)
1568	*puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.TruePinCtls.u;
1569	else
1570	*puValue = 0;
1571	return VINF_SUCCESS;
1572	}
1573
1574
1575	/** @callback_method_impl{FNCPUMRDMSR} */
1576	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTrueProcbasedCtls(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1577	{
1578	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1579	if (pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fVmx)
1580	*puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.TrueProcCtls.u;
1581	else
1582	*puValue = 0;
1583	return VINF_SUCCESS;
1584	}
1585
1586
1587	/** @callback_method_impl{FNCPUMRDMSR} */
1588	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTrueExitCtls(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1589	{
1590	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1591	if (pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fVmx)
1592	*puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.TrueExitCtls.u;
1593	else
1594	*puValue = 0;
1595	return VINF_SUCCESS;
1596	}
1597
1598
1599	/** @callback_method_impl{FNCPUMRDMSR} */
1600	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTrueEntryCtls(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1601	{
1602	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1603	if (pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fVmx)
1604	*puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.TrueEntryCtls.u;
1605	else
1606	*puValue = 0;
1607	return VINF_SUCCESS;
1608	}
1609
1610
1611	/** @callback_method_impl{FNCPUMRDMSR} */
1612	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxVmFunc(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1613	{
1614	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1615	if (pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fVmx)
1616	*puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64VmFunc;
1617	else
1618	*puValue = 0;
1619	return VINF_SUCCESS;
1620	}
1621
1622
1623	/** @callback_method_impl{FNCPUMRDMSR} */
1624	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SpecCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1625	{
1626	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1627	*puValue = pVCpu->cpum.s.GuestMsrs.msr.SpecCtrl;
1628	return VINF_SUCCESS;
1629	}
1630
1631
1632	/** @callback_method_impl{FNCPUMWRMSR} */
1633	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SpecCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1634	{
1635	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1636
1637	/* NB: The STIBP bit can be set even when IBRS is present, regardless of whether STIBP is actually implemented. */
1638	PCPUMFEATURES const pFeatures = &pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures;
1639	uint64_t const fValidMask = (pFeatures->fIbrs ? MSR_IA32_SPEC_CTRL_F_IBRS : 0)
1640	\| (pFeatures->fStibp ? MSR_IA32_SPEC_CTRL_F_STIBP : 0)
1641	\| (pFeatures->fSsbd ? MSR_IA32_SPEC_CTRL_F_SSBD : 0)
1642	\| (pFeatures->fIpredCtrl ? MSR_IA32_SPEC_CTRL_F_IPRED_DIS_U \| MSR_IA32_SPEC_CTRL_F_IPRED_DIS_S : 0)
1643	\| (pFeatures->fRrsbaCtrl ? MSR_IA32_SPEC_CTRL_F_RRSBA_DIS_U \| MSR_IA32_SPEC_CTRL_F_RRSBA_DIS_S : 0)
1644	\| (pFeatures->fPsfd ? MSR_IA32_SPEC_CTRL_F_PSFD : 0)
1645	\| (pFeatures->fDdpdU ? MSR_IA32_SPEC_CTRL_F_DDPD_U : 0)
1646	\| (pFeatures->fBhiCtrl ? MSR_IA32_SPEC_CTRL_F_BHI_DIS_S : 0);
1647	if (uValue & ~fValidMask)
1648	{
1649	Log(("CPUM: Invalid IA32_SPEC_CTRL bits (trying to write %#llx)\n", uValue));
1650	return VERR_CPUM_RAISE_GP_0;
1651	}
1652
1653	pVCpu->cpum.s.GuestMsrs.msr.SpecCtrl = uValue;
1654	return VINF_SUCCESS;
1655	}
1656
1657
1658	/** @callback_method_impl{FNCPUMWRMSR} */
1659	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PredCmd(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1660	{
1661	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1662	return VINF_SUCCESS;
1663	}
1664
1665
1666	/** @callback_method_impl{FNCPUMRDMSR} */
1667	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ArchCapabilities(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1668	{
1669	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1670	*puValue = pVCpu->cpum.s.GuestMsrs.msr.ArchCaps;
1671	return VINF_SUCCESS;
1672	}
1673
1674
1675	/** @callback_method_impl{FNCPUMWRMSR} */
1676	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32FlushCmd(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1677	{
1678	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1679	if ((uValue & ~MSR_IA32_FLUSH_CMD_F_L1D) == 0)
1680	return VINF_SUCCESS;
1681	Log(("CPUM: Invalid MSR_IA32_FLUSH_CMD_ bits (trying to write %#llx)\n", uValue));
1682	return VERR_CPUM_RAISE_GP_0;
1683	}
1684
1685
1686
1687	/*
1688	* AMD64
1689	* AMD64
1690	* AMD64
1691	*/
1692
1693
1694	/** @callback_method_impl{FNCPUMRDMSR} */
1695	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64Efer(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1696	{
1697	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1698	*puValue = pVCpu->cpum.s.Guest.msrEFER;
1699	return VINF_SUCCESS;
1700	}
1701
1702
1703	/** @callback_method_impl{FNCPUMWRMSR} */
1704	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64Efer(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1705	{
1706	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1707	uint64_t uValidatedEfer;
1708	uint64_t const uOldEfer = pVCpu->cpum.s.Guest.msrEFER;
1709	int rc = CPUMIsGuestEferMsrWriteValid(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.s.Guest.cr0, uOldEfer, uValue, &uValidatedEfer);
1710	if (RT_FAILURE(rc))
1711	return VERR_CPUM_RAISE_GP_0;
1712
1713	CPUMSetGuestEferMsrNoChecks(pVCpu, uOldEfer, uValidatedEfer);
1714	return VINF_SUCCESS;
1715	}
1716
1717
1718	/** @callback_method_impl{FNCPUMRDMSR} */
1719	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64SyscallTarget(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1720	{
1721	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1722	*puValue = pVCpu->cpum.s.Guest.msrSTAR;
1723	return VINF_SUCCESS;
1724	}
1725
1726
1727	/** @callback_method_impl{FNCPUMWRMSR} */
1728	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64SyscallTarget(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1729	{
1730	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1731	pVCpu->cpum.s.Guest.msrSTAR = uValue;
1732	return VINF_SUCCESS;
1733	}
1734
1735
1736	/** @callback_method_impl{FNCPUMRDMSR} */
1737	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64LongSyscallTarget(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1738	{
1739	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1740	*puValue = pVCpu->cpum.s.Guest.msrLSTAR;
1741	return VINF_SUCCESS;
1742	}
1743
1744
1745	/** @callback_method_impl{FNCPUMWRMSR} */
1746	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64LongSyscallTarget(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1747	{
1748	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1749	if (!X86_IS_CANONICAL(uValue))
1750	{
1751	Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
1752	return VERR_CPUM_RAISE_GP_0;
1753	}
1754	pVCpu->cpum.s.Guest.msrLSTAR = uValue;
1755	return VINF_SUCCESS;
1756	}
1757
1758
1759	/** @callback_method_impl{FNCPUMRDMSR} */
1760	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64CompSyscallTarget(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1761	{
1762	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1763	*puValue = pVCpu->cpum.s.Guest.msrCSTAR;
1764	return VINF_SUCCESS;
1765	}
1766
1767
1768	/** @callback_method_impl{FNCPUMWRMSR} */
1769	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64CompSyscallTarget(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1770	{
1771	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1772	if (!X86_IS_CANONICAL(uValue))
1773	{
1774	Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
1775	return VERR_CPUM_RAISE_GP_0;
1776	}
1777	pVCpu->cpum.s.Guest.msrCSTAR = uValue;
1778	return VINF_SUCCESS;
1779	}
1780
1781
1782	/** @callback_method_impl{FNCPUMRDMSR} */
1783	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64SyscallFlagMask(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1784	{
1785	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1786	*puValue = pVCpu->cpum.s.Guest.msrSFMASK;
1787	return VINF_SUCCESS;
1788	}
1789
1790
1791	/** @callback_method_impl{FNCPUMWRMSR} */
1792	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64SyscallFlagMask(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1793	{
1794	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1795	/* The high bits are ignored and read-as-zero, writing to them does not raise #GP. See @bugref{10610}.*/
1796	pVCpu->cpum.s.Guest.msrSFMASK = uValue & UINT32_MAX;
1797	return VINF_SUCCESS;
1798	}
1799
1800
1801	/** @callback_method_impl{FNCPUMRDMSR} */
1802	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64FsBase(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1803	{
1804	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1805	*puValue = pVCpu->cpum.s.Guest.fs.u64Base;
1806	return VINF_SUCCESS;
1807	}
1808
1809
1810	/** @callback_method_impl{FNCPUMWRMSR} */
1811	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64FsBase(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1812	{
1813	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1814	if (X86_IS_CANONICAL(uValue))
1815	{
1816	pVCpu->cpum.s.Guest.fs.u64Base = uValue;
1817	return VINF_SUCCESS;
1818	}
1819	Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
1820	return VERR_CPUM_RAISE_GP_0;
1821	}
1822
1823
1824	/** @callback_method_impl{FNCPUMRDMSR} */
1825	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64GsBase(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1826	{
1827	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1828	*puValue = pVCpu->cpum.s.Guest.gs.u64Base;
1829	return VINF_SUCCESS;
1830	}
1831
1832	/** @callback_method_impl{FNCPUMWRMSR} */
1833	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64GsBase(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1834	{
1835	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1836	if (X86_IS_CANONICAL(uValue))
1837	{
1838	pVCpu->cpum.s.Guest.gs.u64Base = uValue;
1839	return VINF_SUCCESS;
1840	}
1841	Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
1842	return VERR_CPUM_RAISE_GP_0;
1843	}
1844
1845
1846
1847	/** @callback_method_impl{FNCPUMRDMSR} */
1848	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64KernelGsBase(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1849	{
1850	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1851	*puValue = pVCpu->cpum.s.Guest.msrKERNELGSBASE;
1852	return VINF_SUCCESS;
1853	}
1854
1855	/** @callback_method_impl{FNCPUMWRMSR} */
1856	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64KernelGsBase(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1857	{
1858	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1859	if (X86_IS_CANONICAL(uValue))
1860	{
1861	pVCpu->cpum.s.Guest.msrKERNELGSBASE = uValue;
1862	return VINF_SUCCESS;
1863	}
1864	Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
1865	return VERR_CPUM_RAISE_GP_0;
1866	}
1867
1868
1869	/** @callback_method_impl{FNCPUMRDMSR} */
1870	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64TscAux(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1871	{
1872	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1873	*puValue = pVCpu->cpum.s.GuestMsrs.msr.TscAux;
1874	return VINF_SUCCESS;
1875	}
1876
1877	/** @callback_method_impl{FNCPUMWRMSR} */
1878	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64TscAux(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1879	{
1880	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1881	pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
1882	return VINF_SUCCESS;
1883	}
1884
1885
1886	/*
1887	* Intel specific
1888	* Intel specific
1889	* Intel specific
1890	*/
1891
1892	/** @callback_method_impl{FNCPUMRDMSR} */
1893	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelEblCrPowerOn(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1894	{
1895	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
1896	/** @todo recalc clock frequency ratio? */
1897	*puValue = pRange->uValue;
1898	return VINF_SUCCESS;
1899	}
1900
1901
1902	/** @callback_method_impl{FNCPUMWRMSR} */
1903	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelEblCrPowerOn(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1904	{
1905	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1906	/** @todo Write EBL_CR_POWERON: Remember written bits. */
1907	return VINF_SUCCESS;
1908	}
1909
1910
1911	/** @callback_method_impl{FNCPUMRDMSR} */
1912	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7CoreThreadCount(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1913	{
1914	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1915
1916	/* Note! According to cpuid_set_info in XNU (10.7.0), Westmere CPU only
1917	have a 4-bit core count. */
1918	uint16_t cCores = pVCpu->CTX_SUFF(pVM)->cCpus;
1919	uint16_t cThreads = cCores; /** @todo hyper-threading. */
1920	*puValue = RT_MAKE_U32(cThreads, cCores);
1921	return VINF_SUCCESS;
1922	}
1923
1924
1925	/** @callback_method_impl{FNCPUMRDMSR} */
1926	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP4EbcHardPowerOn(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1927	{
1928	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
1929	/** @todo P4 hard power on config */
1930	*puValue = pRange->uValue;
1931	return VINF_SUCCESS;
1932	}
1933
1934
1935	/** @callback_method_impl{FNCPUMWRMSR} */
1936	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP4EbcHardPowerOn(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1937	{
1938	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1939	/** @todo P4 hard power on config */
1940	return VINF_SUCCESS;
1941	}
1942
1943
1944	/** @callback_method_impl{FNCPUMRDMSR} */
1945	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP4EbcSoftPowerOn(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1946	{
1947	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
1948	/** @todo P4 soft power on config */
1949	*puValue = pRange->uValue;
1950	return VINF_SUCCESS;
1951	}
1952
1953
1954	/** @callback_method_impl{FNCPUMWRMSR} */
1955	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP4EbcSoftPowerOn(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1956	{
1957	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1958	/** @todo P4 soft power on config */
1959	return VINF_SUCCESS;
1960	}
1961
1962
1963	/** @callback_method_impl{FNCPUMRDMSR} */
1964	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP4EbcFrequencyId(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1965	{
1966	RT_NOREF_PV(idMsr);
1967
1968	uint64_t uValue;
1969	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1970	uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
1971	if (pVM->cpum.s.GuestFeatures.uModel >= 2)
1972	{
1973	if (uScalableBusHz <= CPUM_SBUSFREQ_100MHZ && pVM->cpum.s.GuestFeatures.uModel <= 2)
1974	{
1975	uScalableBusHz = CPUM_SBUSFREQ_100MHZ;
1976	uValue = 0;
1977	}
1978	else if (uScalableBusHz <= CPUM_SBUSFREQ_133MHZ)
1979	{
1980	uScalableBusHz = CPUM_SBUSFREQ_133MHZ;
1981	uValue = 1;
1982	}
1983	else if (uScalableBusHz <= CPUM_SBUSFREQ_167MHZ)
1984	{
1985	uScalableBusHz = CPUM_SBUSFREQ_167MHZ;
1986	uValue = 3;
1987	}
1988	else if (uScalableBusHz <= CPUM_SBUSFREQ_200MHZ)
1989	{
1990	uScalableBusHz = CPUM_SBUSFREQ_200MHZ;
1991	uValue = 2;
1992	}
1993	else if (uScalableBusHz <= CPUM_SBUSFREQ_267MHZ && pVM->cpum.s.GuestFeatures.uModel > 2)
1994	{
1995	uScalableBusHz = CPUM_SBUSFREQ_267MHZ;
1996	uValue = 0;
1997	}
1998	else
1999	{
2000	uScalableBusHz = CPUM_SBUSFREQ_333MHZ;
2001	uValue = 6;
2002	}
2003	uValue <<= 16;
2004
2005	uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
2006	uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
2007	uValue \|= (uint32_t)uTscRatio << 24;
2008
2009	uValue \|= pRange->uValue & ~UINT64_C(0xff0f0000);
2010	}
2011	else
2012	{
2013	/* Probably more stuff here, but intel doesn't want to tell us. */
2014	uValue = pRange->uValue;
2015	uValue &= ~(RT_BIT_64(21) \| RT_BIT_64(22) \| RT_BIT_64(23)); /* 100 MHz is only documented value */
2016	}
2017
2018	*puValue = uValue;
2019	return VINF_SUCCESS;
2020	}
2021
2022
2023	/** @callback_method_impl{FNCPUMWRMSR} */
2024	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP4EbcFrequencyId(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2025	{
2026	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2027	/** @todo P4 bus frequency config */
2028	return VINF_SUCCESS;
2029	}
2030
2031
2032	/** @callback_method_impl{FNCPUMRDMSR} */
2033	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP6FsbFrequency(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2034	{
2035	RT_NOREF_PV(idMsr);
2036
2037	/* Convert the scalable bus frequency to the encoding in the intel manual (for core+). */
2038	uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVCpu->CTX_SUFF(pVM));
2039	if (uScalableBusHz <= CPUM_SBUSFREQ_100MHZ)
2040	*puValue = 5;
2041	else if (uScalableBusHz <= CPUM_SBUSFREQ_133MHZ)
2042	*puValue = 1;
2043	else if (uScalableBusHz <= CPUM_SBUSFREQ_167MHZ)
2044	*puValue = 3;
2045	else if (uScalableBusHz <= CPUM_SBUSFREQ_200MHZ)
2046	*puValue = 2;
2047	else if (uScalableBusHz <= CPUM_SBUSFREQ_267MHZ)
2048	*puValue = 0;
2049	else if (uScalableBusHz <= CPUM_SBUSFREQ_333MHZ)
2050	*puValue = 4;
2051	else /if (uScalableBusHz <= CPUM_SBUSFREQ_400MHZ)/
2052	*puValue = 6;
2053
2054	*puValue \|= pRange->uValue & ~UINT64_C(0x7);
2055
2056	return VINF_SUCCESS;
2057	}
2058
2059
2060	/** @callback_method_impl{FNCPUMRDMSR} */
2061	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelPlatformInfo(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2062	{
2063	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2064
2065	/* Just indicate a fixed TSC, no turbo boost, no programmable anything. */
2066	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2067	uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
2068	uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
2069	uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
2070	uint64_t uValue = ((uint32_t)uTscRatio << 8) /* TSC invariant frequency. */
2071	\| ((uint64_t)uTscRatio << 40); /* The max turbo frequency. */
2072
2073	/* Ivy bridge has a minimum operating ratio as well. */
2074	if (true) /** @todo detect sandy bridge. */
2075	uValue \|= (uint64_t)uTscRatio << 48;
2076
2077	*puValue = uValue;
2078	return VINF_SUCCESS;
2079	}
2080
2081
2082	/** @callback_method_impl{FNCPUMRDMSR} */
2083	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelFlexRatio(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2084	{
2085	RT_NOREF_PV(idMsr);
2086
2087	uint64_t uValue = pRange->uValue & ~UINT64_C(0x1ff00);
2088
2089	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2090	uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
2091	uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
2092	uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
2093	uValue \|= (uint32_t)uTscRatio << 8;
2094
2095	*puValue = uValue;
2096	return VINF_SUCCESS;
2097	}
2098
2099
2100	/** @callback_method_impl{FNCPUMWRMSR} */
2101	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelFlexRatio(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2102	{
2103	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2104	/** @todo implement writing MSR_FLEX_RATIO. */
2105	return VINF_SUCCESS;
2106	}
2107
2108
2109	/** @callback_method_impl{FNCPUMRDMSR} */
2110	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelPkgCStConfigControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2111	{
2112	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2113	*puValue = pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl;
2114	return VINF_SUCCESS;
2115	}
2116
2117
2118	/** @callback_method_impl{FNCPUMWRMSR} */
2119	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelPkgCStConfigControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2120	{
2121	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
2122
2123	if (pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl & RT_BIT_64(15))
2124	{
2125	Log(("CPUM: WRMSR %#x (%s), %#llx: Write protected -> #GP\n", idMsr, pRange->szName, uValue));
2126	return VERR_CPUM_RAISE_GP_0;
2127	}
2128	#if 0 /** @todo check what real (old) hardware does. */
2129	if ((uValue & 7) >= 5)
2130	{
2131	Log(("CPUM: WRMSR %#x (%s), %#llx: Invalid limit (%d) -> #GP\n", idMsr, pRange->szName, uValue, (uint32_t)(uValue & 7)));
2132	return VERR_CPUM_RAISE_GP_0;
2133	}
2134	#endif
2135	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = uValue;
2136	return VINF_SUCCESS;
2137	}
2138
2139
2140	/** @callback_method_impl{FNCPUMRDMSR} */
2141	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelPmgIoCaptureBase(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2142	{
2143	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2144	/** @todo implement I/O mwait wakeup. */
2145	*puValue = 0;
2146	return VINF_SUCCESS;
2147	}
2148
2149
2150	/** @callback_method_impl{FNCPUMWRMSR} */
2151	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelPmgIoCaptureBase(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2152	{
2153	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2154	/** @todo implement I/O mwait wakeup. */
2155	return VINF_SUCCESS;
2156	}
2157
2158
2159	/** @callback_method_impl{FNCPUMRDMSR} */
2160	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchFromToN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2161	{
2162	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2163	/** @todo implement last branch records. */
2164	*puValue = 0;
2165	return VINF_SUCCESS;
2166	}
2167
2168
2169	/** @callback_method_impl{FNCPUMWRMSR} */
2170	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchFromToN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2171	{
2172	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2173	/** @todo implement last branch records. */
2174	return VINF_SUCCESS;
2175	}
2176
2177
2178	/** @callback_method_impl{FNCPUMRDMSR} */
2179	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchFromN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2180	{
2181	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2182	/** @todo implement last branch records. */
2183	*puValue = 0;
2184	return VINF_SUCCESS;
2185	}
2186
2187
2188	/** @callback_method_impl{FNCPUMWRMSR} */
2189	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchFromN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2190	{
2191	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
2192	/** @todo implement last branch records. */
2193	/** @todo Probing indicates that bit 63 is settable on SandyBridge, at least
2194	* if the rest of the bits are zero. Automatic sign extending?
2195	* Investigate! */
2196	if (!X86_IS_CANONICAL(uValue))
2197	{
2198	Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
2199	return VERR_CPUM_RAISE_GP_0;
2200	}
2201	return VINF_SUCCESS;
2202	}
2203
2204
2205	/** @callback_method_impl{FNCPUMRDMSR} */
2206	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchToN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2207	{
2208	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2209	/** @todo implement last branch records. */
2210	*puValue = 0;
2211	return VINF_SUCCESS;
2212	}
2213
2214
2215	/** @callback_method_impl{FNCPUMWRMSR} */
2216	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchToN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2217	{
2218	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2219	/** @todo implement last branch records. */
2220	/** @todo Probing indicates that bit 63 is settable on SandyBridge, at least
2221	* if the rest of the bits are zero. Automatic sign extending?
2222	* Investigate! */
2223	if (!X86_IS_CANONICAL(uValue))
2224	{
2225	Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
2226	return VERR_CPUM_RAISE_GP_0;
2227	}
2228	return VINF_SUCCESS;
2229	}
2230
2231
2232	/** @callback_method_impl{FNCPUMRDMSR} */
2233	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchTos(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2234	{
2235	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2236	/** @todo implement last branch records. */
2237	*puValue = 0;
2238	return VINF_SUCCESS;
2239	}
2240
2241
2242	/** @callback_method_impl{FNCPUMWRMSR} */
2243	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchTos(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2244	{
2245	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2246	/** @todo implement last branch records. */
2247	return VINF_SUCCESS;
2248	}
2249
2250
2251	/** @callback_method_impl{FNCPUMRDMSR} */
2252	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelBblCrCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2253	{
2254	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
2255	*puValue = pRange->uValue;
2256	return VINF_SUCCESS;
2257	}
2258
2259
2260	/** @callback_method_impl{FNCPUMWRMSR} */
2261	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelBblCrCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2262	{
2263	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2264	return VINF_SUCCESS;
2265	}
2266
2267
2268	/** @callback_method_impl{FNCPUMRDMSR} */
2269	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelBblCrCtl3(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2270	{
2271	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
2272	*puValue = pRange->uValue;
2273	return VINF_SUCCESS;
2274	}
2275
2276
2277	/** @callback_method_impl{FNCPUMWRMSR} */
2278	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelBblCrCtl3(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2279	{
2280	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2281	return VINF_SUCCESS;
2282	}
2283
2284
2285	/** @callback_method_impl{FNCPUMRDMSR} */
2286	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7TemperatureTarget(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2287	{
2288	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
2289	*puValue = pRange->uValue;
2290	return VINF_SUCCESS;
2291	}
2292
2293
2294	/** @callback_method_impl{FNCPUMWRMSR} */
2295	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7TemperatureTarget(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2296	{
2297	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2298	return VINF_SUCCESS;
2299	}
2300
2301
2302	/** @callback_method_impl{FNCPUMRDMSR} */
2303	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7MsrOffCoreResponseN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2304	{
2305	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
2306	/** @todo machine check. */
2307	*puValue = pRange->uValue;
2308	return VINF_SUCCESS;
2309	}
2310
2311
2312	/** @callback_method_impl{FNCPUMWRMSR} */
2313	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7MsrOffCoreResponseN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2314	{
2315	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2316	/** @todo machine check. */
2317	return VINF_SUCCESS;
2318	}
2319
2320
2321	/** @callback_method_impl{FNCPUMRDMSR} */
2322	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7MiscPwrMgmt(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2323	{
2324	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2325	*puValue = 0;
2326	return VINF_SUCCESS;
2327	}
2328
2329
2330	/** @callback_method_impl{FNCPUMWRMSR} */
2331	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7MiscPwrMgmt(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2332	{
2333	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2334	return VINF_SUCCESS;
2335	}
2336
2337
2338	/** @callback_method_impl{FNCPUMRDMSR} */
2339	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP6CrN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2340	{
2341	RT_NOREF_PV(idMsr);
2342	int rc = CPUMGetGuestCRx(pVCpu, pRange->uValue, puValue);
2343	AssertRC(rc);
2344	return VINF_SUCCESS;
2345	}
2346
2347
2348	/** @callback_method_impl{FNCPUMWRMSR} */
2349	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP6CrN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2350	{
2351	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2352	/* This CRx interface differs from the MOV CRx, GReg interface in that
2353	#GP(0) isn't raised if unsupported bits are written to. Instead they
2354	are simply ignored and masked off. (Pentium M Dothan) */
2355	/** @todo Implement MSR_P6_CRx writing. Too much effort for very little, if
2356	* any, gain. */
2357	return VINF_SUCCESS;
2358	}
2359
2360
2361	/** @callback_method_impl{FNCPUMRDMSR} */
2362	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCpuId1FeatureMaskEcdx(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2363	{
2364	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2365	/** @todo implement CPUID masking. */
2366	*puValue = UINT64_MAX;
2367	return VINF_SUCCESS;
2368	}
2369
2370
2371	/** @callback_method_impl{FNCPUMWRMSR} */
2372	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCpuId1FeatureMaskEcdx(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2373	{
2374	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2375	/** @todo implement CPUID masking. */
2376	return VINF_SUCCESS;
2377	}
2378
2379
2380	/** @callback_method_impl{FNCPUMRDMSR} */
2381	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCpuId1FeatureMaskEax(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2382	{
2383	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2384	/** @todo implement CPUID masking. */
2385	*puValue = 0;
2386	return VINF_SUCCESS;
2387	}
2388
2389
2390	/** @callback_method_impl{FNCPUMWRMSR} */
2391	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCpuId1FeatureMaskEax(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2392	{
2393	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2394	/** @todo implement CPUID masking. */
2395	return VINF_SUCCESS;
2396	}
2397
2398
2399
2400	/** @callback_method_impl{FNCPUMRDMSR} */
2401	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCpuId80000001FeatureMaskEcdx(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2402	{
2403	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2404	/** @todo implement CPUID masking. */
2405	*puValue = UINT64_MAX;
2406	return VINF_SUCCESS;
2407	}
2408
2409
2410	/** @callback_method_impl{FNCPUMWRMSR} */
2411	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCpuId80000001FeatureMaskEcdx(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2412	{
2413	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2414	/** @todo implement CPUID masking. */
2415	return VINF_SUCCESS;
2416	}
2417
2418
2419
2420	/** @callback_method_impl{FNCPUMRDMSR} */
2421	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyAesNiCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2422	{
2423	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2424	/** @todo implement AES-NI. */
2425	puValue = 3; / Bit 0 is lock bit, bit 1 disables AES-NI. That's what they say. */
2426	return VINF_SUCCESS;
2427	}
2428
2429
2430	/** @callback_method_impl{FNCPUMWRMSR} */
2431	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyAesNiCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2432	{
2433	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2434	/** @todo implement AES-NI. */
2435	return VERR_CPUM_RAISE_GP_0;
2436	}
2437
2438
2439	/** @callback_method_impl{FNCPUMRDMSR} */
2440	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7TurboRatioLimit(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2441	{
2442	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
2443	/** @todo implement intel C states. */
2444	*puValue = pRange->uValue;
2445	return VINF_SUCCESS;
2446	}
2447
2448
2449	/** @callback_method_impl{FNCPUMWRMSR} */
2450	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7TurboRatioLimit(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2451	{
2452	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2453	/** @todo implement intel C states. */
2454	return VINF_SUCCESS;
2455	}
2456
2457
2458	/** @callback_method_impl{FNCPUMRDMSR} */
2459	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7LbrSelect(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2460	{
2461	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2462	/** @todo implement last-branch-records. */
2463	*puValue = 0;
2464	return VINF_SUCCESS;
2465	}
2466
2467
2468	/** @callback_method_impl{FNCPUMWRMSR} */
2469	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7LbrSelect(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2470	{
2471	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2472	/** @todo implement last-branch-records. */
2473	return VINF_SUCCESS;
2474	}
2475
2476
2477	/** @callback_method_impl{FNCPUMRDMSR} */
2478	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyErrorControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2479	{
2480	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2481	/** @todo implement memory error injection (MSR_ERROR_CONTROL). */
2482	*puValue = 0;
2483	return VINF_SUCCESS;
2484	}
2485
2486
2487	/** @callback_method_impl{FNCPUMWRMSR} */
2488	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyErrorControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2489	{
2490	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2491	/** @todo implement memory error injection (MSR_ERROR_CONTROL). */
2492	return VINF_SUCCESS;
2493	}
2494
2495
2496	/** @callback_method_impl{FNCPUMRDMSR} */
2497	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7VirtualLegacyWireCap(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2498	{
2499	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
2500	/** @todo implement memory VLW? */
2501	*puValue = pRange->uValue;
2502	/* Note: A20M is known to be bit 1 as this was disclosed in spec update
2503	AAJ49/AAK51/????, which documents the inversion of this bit. The
2504	Sandy bridge CPU here has value 0x74, so it probably doesn't have a BIOS
2505	that correct things. Some guesses at the other bits:
2506	bit 2 = INTR
2507	bit 4 = SMI
2508	bit 5 = INIT
2509	bit 6 = NMI */
2510	return VINF_SUCCESS;
2511	}
2512
2513
2514	/** @callback_method_impl{FNCPUMRDMSR} */
2515	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7PowerCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2516	{
2517	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2518	/** @todo intel power management */
2519	*puValue = 0;
2520	return VINF_SUCCESS;
2521	}
2522
2523
2524	/** @callback_method_impl{FNCPUMWRMSR} */
2525	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7PowerCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2526	{
2527	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2528	/** @todo intel power management */
2529	return VINF_SUCCESS;
2530	}
2531
2532
2533	/** @callback_method_impl{FNCPUMRDMSR} */
2534	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyPebsNumAlt(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2535	{
2536	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2537	/** @todo intel performance counters. */
2538	*puValue = 0;
2539	return VINF_SUCCESS;
2540	}
2541
2542
2543	/** @callback_method_impl{FNCPUMWRMSR} */
2544	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyPebsNumAlt(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2545	{
2546	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2547	/** @todo intel performance counters. */
2548	return VINF_SUCCESS;
2549	}
2550
2551
2552	/** @callback_method_impl{FNCPUMRDMSR} */
2553	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7PebsLdLat(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2554	{
2555	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2556	/** @todo intel performance counters. */
2557	*puValue = 0;
2558	return VINF_SUCCESS;
2559	}
2560
2561
2562	/** @callback_method_impl{FNCPUMWRMSR} */
2563	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7PebsLdLat(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2564	{
2565	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2566	/** @todo intel performance counters. */
2567	return VINF_SUCCESS;
2568	}
2569
2570
2571	/** @callback_method_impl{FNCPUMRDMSR} */
2572	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7PkgCnResidencyN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2573	{
2574	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2575	/** @todo intel power management. */
2576	*puValue = 0;
2577	return VINF_SUCCESS;
2578	}
2579
2580
2581	/** @callback_method_impl{FNCPUMRDMSR} */
2582	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7CoreCnResidencyN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2583	{
2584	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2585	/** @todo intel power management. */
2586	*puValue = 0;
2587	return VINF_SUCCESS;
2588	}
2589
2590
2591	/** @callback_method_impl{FNCPUMRDMSR} */
2592	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyVrCurrentConfig(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2593	{
2594	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2595	/** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2596	*puValue = 0;
2597	return VINF_SUCCESS;
2598	}
2599
2600
2601	/** @callback_method_impl{FNCPUMWRMSR} */
2602	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyVrCurrentConfig(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2603	{
2604	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2605	/** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2606	return VINF_SUCCESS;
2607	}
2608
2609
2610	/** @callback_method_impl{FNCPUMRDMSR} */
2611	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyVrMiscConfig(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2612	{
2613	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2614	/** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2615	*puValue = 0;
2616	return VINF_SUCCESS;
2617	}
2618
2619
2620	/** @callback_method_impl{FNCPUMWRMSR} */
2621	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyVrMiscConfig(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2622	{
2623	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2624	/** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2625	return VINF_SUCCESS;
2626	}
2627
2628
2629	/** @callback_method_impl{FNCPUMRDMSR} */
2630	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyRaplPowerUnit(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2631	{
2632	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
2633	/** @todo intel RAPL. */
2634	*puValue = pRange->uValue;
2635	return VINF_SUCCESS;
2636	}
2637
2638
2639	/** @callback_method_impl{FNCPUMWRMSR} */
2640	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyRaplPowerUnit(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2641	{
2642	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2643	/* Note! This is documented as read only and except for a Silvermont sample has
2644	always been classified as read only. This is just here to make it compile. */
2645	return VINF_SUCCESS;
2646	}
2647
2648
2649	/** @callback_method_impl{FNCPUMRDMSR} */
2650	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyPkgCnIrtlN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2651	{
2652	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2653	/** @todo intel power management. */
2654	*puValue = 0;
2655	return VINF_SUCCESS;
2656	}
2657
2658
2659	/** @callback_method_impl{FNCPUMWRMSR} */
2660	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyPkgCnIrtlN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2661	{
2662	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2663	/** @todo intel power management. */
2664	return VINF_SUCCESS;
2665	}
2666
2667
2668	/** @callback_method_impl{FNCPUMRDMSR} */
2669	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyPkgC2Residency(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2670	{
2671	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2672	/** @todo intel power management. */
2673	*puValue = 0;
2674	return VINF_SUCCESS;
2675	}
2676
2677
2678	/** @callback_method_impl{FNCPUMWRMSR} */
2679	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyPkgC2Residency(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2680	{
2681	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2682	/* Note! This is documented as read only and except for a Silvermont sample has
2683	always been classified as read only. This is just here to make it compile. */
2684	return VINF_SUCCESS;
2685	}
2686
2687
2688	/** @callback_method_impl{FNCPUMRDMSR} */
2689	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgPowerLimit(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2690	{
2691	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2692	/** @todo intel RAPL. */
2693	*puValue = 0;
2694	return VINF_SUCCESS;
2695	}
2696
2697
2698	/** @callback_method_impl{FNCPUMWRMSR} */
2699	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPkgPowerLimit(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2700	{
2701	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2702	/** @todo intel RAPL. */
2703	return VINF_SUCCESS;
2704	}
2705
2706
2707	/** @callback_method_impl{FNCPUMRDMSR} */
2708	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgEnergyStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2709	{
2710	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2711	/** @todo intel power management. */
2712	*puValue = 0;
2713	return VINF_SUCCESS;
2714	}
2715
2716
2717	/** @callback_method_impl{FNCPUMRDMSR} */
2718	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgPerfStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2719	{
2720	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2721	/** @todo intel power management. */
2722	*puValue = 0;
2723	return VINF_SUCCESS;
2724	}
2725
2726
2727	/** @callback_method_impl{FNCPUMRDMSR} */
2728	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgPowerInfo(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2729	{
2730	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2731	/** @todo intel power management. */
2732	*puValue = 0;
2733	return VINF_SUCCESS;
2734	}
2735
2736
2737	/** @callback_method_impl{FNCPUMRDMSR} */
2738	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramPowerLimit(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2739	{
2740	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2741	/** @todo intel RAPL. */
2742	*puValue = 0;
2743	return VINF_SUCCESS;
2744	}
2745
2746
2747	/** @callback_method_impl{FNCPUMWRMSR} */
2748	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplDramPowerLimit(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2749	{
2750	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2751	/** @todo intel RAPL. */
2752	return VINF_SUCCESS;
2753	}
2754
2755
2756	/** @callback_method_impl{FNCPUMRDMSR} */
2757	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramEnergyStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2758	{
2759	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2760	/** @todo intel power management. */
2761	*puValue = 0;
2762	return VINF_SUCCESS;
2763	}
2764
2765
2766	/** @callback_method_impl{FNCPUMRDMSR} */
2767	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramPerfStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2768	{
2769	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2770	/** @todo intel power management. */
2771	*puValue = 0;
2772	return VINF_SUCCESS;
2773	}
2774
2775
2776	/** @callback_method_impl{FNCPUMRDMSR} */
2777	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramPowerInfo(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2778	{
2779	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2780	/** @todo intel power management. */
2781	*puValue = 0;
2782	return VINF_SUCCESS;
2783	}
2784
2785
2786	/** @callback_method_impl{FNCPUMRDMSR} */
2787	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0PowerLimit(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2788	{
2789	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2790	/** @todo intel RAPL. */
2791	*puValue = 0;
2792	return VINF_SUCCESS;
2793	}
2794
2795
2796	/** @callback_method_impl{FNCPUMWRMSR} */
2797	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp0PowerLimit(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2798	{
2799	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2800	/** @todo intel RAPL. */
2801	return VINF_SUCCESS;
2802	}
2803
2804
2805	/** @callback_method_impl{FNCPUMRDMSR} */
2806	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0EnergyStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2807	{
2808	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2809	/** @todo intel power management. */
2810	*puValue = 0;
2811	return VINF_SUCCESS;
2812	}
2813
2814
2815	/** @callback_method_impl{FNCPUMRDMSR} */
2816	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0Policy(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2817	{
2818	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2819	/** @todo intel RAPL. */
2820	*puValue = 0;
2821	return VINF_SUCCESS;
2822	}
2823
2824
2825	/** @callback_method_impl{FNCPUMWRMSR} */
2826	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp0Policy(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2827	{
2828	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2829	/** @todo intel RAPL. */
2830	return VINF_SUCCESS;
2831	}
2832
2833
2834	/** @callback_method_impl{FNCPUMRDMSR} */
2835	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0PerfStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2836	{
2837	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2838	/** @todo intel power management. */
2839	*puValue = 0;
2840	return VINF_SUCCESS;
2841	}
2842
2843
2844	/** @callback_method_impl{FNCPUMRDMSR} */
2845	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp1PowerLimit(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2846	{
2847	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2848	/** @todo intel RAPL. */
2849	*puValue = 0;
2850	return VINF_SUCCESS;
2851	}
2852
2853
2854	/** @callback_method_impl{FNCPUMWRMSR} */
2855	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp1PowerLimit(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2856	{
2857	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2858	/** @todo intel RAPL. */
2859	return VINF_SUCCESS;
2860	}
2861
2862
2863	/** @callback_method_impl{FNCPUMRDMSR} */
2864	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp1EnergyStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2865	{
2866	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2867	/** @todo intel power management. */
2868	*puValue = 0;
2869	return VINF_SUCCESS;
2870	}
2871
2872
2873	/** @callback_method_impl{FNCPUMRDMSR} */
2874	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp1Policy(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2875	{
2876	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2877	/** @todo intel RAPL. */
2878	*puValue = 0;
2879	return VINF_SUCCESS;
2880	}
2881
2882
2883	/** @callback_method_impl{FNCPUMWRMSR} */
2884	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp1Policy(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2885	{
2886	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2887	/** @todo intel RAPL. */
2888	return VINF_SUCCESS;
2889	}
2890
2891
2892	/** @callback_method_impl{FNCPUMRDMSR} */
2893	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpNominal(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2894	{
2895	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
2896	/** @todo intel power management. */
2897	*puValue = pRange->uValue;
2898	return VINF_SUCCESS;
2899	}
2900
2901
2902	/** @callback_method_impl{FNCPUMRDMSR} */
2903	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpLevel1(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2904	{
2905	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
2906	/** @todo intel power management. */
2907	*puValue = pRange->uValue;
2908	return VINF_SUCCESS;
2909	}
2910
2911
2912	/** @callback_method_impl{FNCPUMRDMSR} */
2913	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpLevel2(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2914	{
2915	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
2916	/** @todo intel power management. */
2917	*puValue = pRange->uValue;
2918	return VINF_SUCCESS;
2919	}
2920
2921
2922	/** @callback_method_impl{FNCPUMRDMSR} */
2923	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2924	{
2925	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2926	/** @todo intel power management. */
2927	*puValue = 0;
2928	return VINF_SUCCESS;
2929	}
2930
2931
2932	/** @callback_method_impl{FNCPUMWRMSR} */
2933	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7IvyConfigTdpControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2934	{
2935	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2936	/** @todo intel power management. */
2937	return VINF_SUCCESS;
2938	}
2939
2940
2941	/** @callback_method_impl{FNCPUMRDMSR} */
2942	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyTurboActivationRatio(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2943	{
2944	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2945	/** @todo intel power management. */
2946	*puValue = 0;
2947	return VINF_SUCCESS;
2948	}
2949
2950
2951	/** @callback_method_impl{FNCPUMWRMSR} */
2952	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7IvyTurboActivationRatio(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2953	{
2954	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2955	/** @todo intel power management. */
2956	return VINF_SUCCESS;
2957	}
2958
2959
2960	/** @callback_method_impl{FNCPUMRDMSR} */
2961	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfGlobalCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2962	{
2963	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2964	/** @todo uncore msrs. */
2965	*puValue = 0;
2966	return VINF_SUCCESS;
2967	}
2968
2969
2970	/** @callback_method_impl{FNCPUMWRMSR} */
2971	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfGlobalCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2972	{
2973	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2974	/** @todo uncore msrs. */
2975	return VINF_SUCCESS;
2976	}
2977
2978
2979	/** @callback_method_impl{FNCPUMRDMSR} */
2980	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfGlobalStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2981	{
2982	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2983	/** @todo uncore msrs. */
2984	*puValue = 0;
2985	return VINF_SUCCESS;
2986	}
2987
2988
2989	/** @callback_method_impl{FNCPUMWRMSR} */
2990	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfGlobalStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2991	{
2992	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2993	/** @todo uncore msrs. */
2994	return VINF_SUCCESS;
2995	}
2996
2997
2998	/** @callback_method_impl{FNCPUMRDMSR} */
2999	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfGlobalOvfCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3000	{
3001	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3002	/** @todo uncore msrs. */
3003	*puValue = 0;
3004	return VINF_SUCCESS;
3005	}
3006
3007
3008	/** @callback_method_impl{FNCPUMWRMSR} */
3009	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfGlobalOvfCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3010	{
3011	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3012	/** @todo uncore msrs. */
3013	return VINF_SUCCESS;
3014	}
3015
3016
3017	/** @callback_method_impl{FNCPUMRDMSR} */
3018	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfFixedCtrCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3019	{
3020	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3021	/** @todo uncore msrs. */
3022	*puValue = 0;
3023	return VINF_SUCCESS;
3024	}
3025
3026
3027	/** @callback_method_impl{FNCPUMWRMSR} */
3028	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfFixedCtrCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3029	{
3030	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3031	/** @todo uncore msrs. */
3032	return VINF_SUCCESS;
3033	}
3034
3035
3036	/** @callback_method_impl{FNCPUMRDMSR} */
3037	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfFixedCtr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3038	{
3039	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3040	/** @todo uncore msrs. */
3041	*puValue = 0;
3042	return VINF_SUCCESS;
3043	}
3044
3045
3046	/** @callback_method_impl{FNCPUMWRMSR} */
3047	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfFixedCtr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3048	{
3049	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3050	/** @todo uncore msrs. */
3051	return VINF_SUCCESS;
3052	}
3053
3054
3055	/** @callback_method_impl{FNCPUMRDMSR} */
3056	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncCBoxConfig(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3057	{
3058	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3059	/** @todo uncore msrs. */
3060	*puValue = 0;
3061	return VINF_SUCCESS;
3062	}
3063
3064
3065	/** @callback_method_impl{FNCPUMRDMSR} */
3066	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncArbPerfCtrN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3067	{
3068	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3069	/** @todo uncore msrs. */
3070	*puValue = 0;
3071	return VINF_SUCCESS;
3072	}
3073
3074
3075	/** @callback_method_impl{FNCPUMWRMSR} */
3076	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncArbPerfCtrN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3077	{
3078	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3079	/** @todo uncore msrs. */
3080	return VINF_SUCCESS;
3081	}
3082
3083
3084	/** @callback_method_impl{FNCPUMRDMSR} */
3085	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncArbPerfEvtSelN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3086	{
3087	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3088	/** @todo uncore msrs. */
3089	*puValue = 0;
3090	return VINF_SUCCESS;
3091	}
3092
3093
3094	/** @callback_method_impl{FNCPUMWRMSR} */
3095	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncArbPerfEvtSelN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3096	{
3097	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3098	/** @todo uncore msrs. */
3099	return VINF_SUCCESS;
3100	}
3101
3102
3103	/** @callback_method_impl{FNCPUMRDMSR} */
3104	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SmiCount(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3105	{
3106	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3107
3108	/*
3109	* 31:0 is SMI count (read only), 63:32 reserved.
3110	* Since we don't do SMI, the count is always zero.
3111	*/
3112	*puValue = 0;
3113	return VINF_SUCCESS;
3114	}
3115
3116
3117	/** @callback_method_impl{FNCPUMRDMSR} */
3118	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore2EmttmCrTablesN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3119	{
3120	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
3121	/** @todo implement enhanced multi thread termal monitoring? */
3122	*puValue = pRange->uValue;
3123	return VINF_SUCCESS;
3124	}
3125
3126
3127	/** @callback_method_impl{FNCPUMWRMSR} */
3128	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore2EmttmCrTablesN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3129	{
3130	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3131	/** @todo implement enhanced multi thread termal monitoring? */
3132	return VINF_SUCCESS;
3133	}
3134
3135
3136	/** @callback_method_impl{FNCPUMRDMSR} */
3137	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore2SmmCStMiscInfo(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3138	{
3139	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3140	/** @todo SMM & C-states? */
3141	*puValue = 0;
3142	return VINF_SUCCESS;
3143	}
3144
3145
3146	/** @callback_method_impl{FNCPUMWRMSR} */
3147	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore2SmmCStMiscInfo(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3148	{
3149	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3150	/** @todo SMM & C-states? */
3151	return VINF_SUCCESS;
3152	}
3153
3154
3155	/** @callback_method_impl{FNCPUMRDMSR} */
3156	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore1ExtConfig(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3157	{
3158	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3159	/** @todo Core1&2 EXT_CONFIG (whatever that is)? */
3160	*puValue = 0;
3161	return VINF_SUCCESS;
3162	}
3163
3164
3165	/** @callback_method_impl{FNCPUMWRMSR} */
3166	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore1ExtConfig(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3167	{
3168	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3169	/** @todo Core1&2 EXT_CONFIG (whatever that is)? */
3170	return VINF_SUCCESS;
3171	}
3172
3173
3174	/** @callback_method_impl{FNCPUMRDMSR} */
3175	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore1DtsCalControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3176	{
3177	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3178	/** @todo Core1&2(?) DTS_CAL_CTRL (whatever that is)? */
3179	*puValue = 0;
3180	return VINF_SUCCESS;
3181	}
3182
3183
3184	/** @callback_method_impl{FNCPUMWRMSR} */
3185	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore1DtsCalControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3186	{
3187	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3188	/** @todo Core1&2(?) DTS_CAL_CTRL (whatever that is)? */
3189	return VINF_SUCCESS;
3190	}
3191
3192
3193	/** @callback_method_impl{FNCPUMRDMSR} */
3194	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore2PeciControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3195	{
3196	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3197	/** @todo Core2+ platform environment control interface control register? */
3198	*puValue = 0;
3199	return VINF_SUCCESS;
3200	}
3201
3202
3203	/** @callback_method_impl{FNCPUMWRMSR} */
3204	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore2PeciControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3205	{
3206	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3207	/** @todo Core2+ platform environment control interface control register? */
3208	return VINF_SUCCESS;
3209	}
3210
3211
3212	/** @callback_method_impl{FNCPUMRDMSR} */
3213	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelAtSilvCoreC1Recidency(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3214	{
3215	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3216	*puValue = 0;
3217	return VINF_SUCCESS;
3218	}
3219
3220
3221	/*
3222	* Multiple vendor P6 MSRs.
3223	* Multiple vendor P6 MSRs.
3224	* Multiple vendor P6 MSRs.
3225	*
3226	* These MSRs were introduced with the P6 but not elevated to architectural
3227	* MSRs, despite other vendors implementing them.
3228	*/
3229
3230
3231	/** @callback_method_impl{FNCPUMRDMSR} */
3232	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastBranchFromIp(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3233	{
3234	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3235	/* AMD seems to just record RIP, while intel claims to record RIP+CS.BASE
3236	if I read the docs correctly, thus the need for separate functions. */
3237	/** @todo implement last branch records. */
3238	*puValue = 0;
3239	return VINF_SUCCESS;
3240	}
3241
3242
3243	/** @callback_method_impl{FNCPUMRDMSR} */
3244	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastBranchToIp(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3245	{
3246	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3247	/** @todo implement last branch records. */
3248	*puValue = 0;
3249	return VINF_SUCCESS;
3250	}
3251
3252
3253	/** @callback_method_impl{FNCPUMRDMSR} */
3254	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastIntFromIp(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3255	{
3256	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3257	/** @todo implement last exception records. */
3258	*puValue = 0;
3259	return VINF_SUCCESS;
3260	}
3261
3262
3263	/** @callback_method_impl{FNCPUMWRMSR} */
3264	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_P6LastIntFromIp(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3265	{
3266	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3267	/** @todo implement last exception records. */
3268	/* Note! On many CPUs, the high bit of the 0x000001dd register is always writable, even when the result is
3269	a non-cannonical address. */
3270	return VINF_SUCCESS;
3271	}
3272
3273
3274	/** @callback_method_impl{FNCPUMRDMSR} */
3275	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastIntToIp(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3276	{
3277	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3278	/** @todo implement last exception records. */
3279	*puValue = 0;
3280	return VINF_SUCCESS;
3281	}
3282
3283
3284	/** @callback_method_impl{FNCPUMWRMSR} */
3285	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_P6LastIntToIp(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3286	{
3287	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3288	/** @todo implement last exception records. */
3289	return VINF_SUCCESS;
3290	}
3291
3292
3293
3294	/*
3295	* AMD specific
3296	* AMD specific
3297	* AMD specific
3298	*/
3299
3300
3301	/** @callback_method_impl{FNCPUMRDMSR} */
3302	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hTscRate(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3303	{
3304	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3305	/** @todo Implement TscRateMsr */
3306	puValue = RT_MAKE_U64(0, 1); / 1.0 = reset value. */
3307	return VINF_SUCCESS;
3308	}
3309
3310
3311	/** @callback_method_impl{FNCPUMWRMSR} */
3312	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hTscRate(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3313	{
3314	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3315	/** @todo Implement TscRateMsr */
3316	return VINF_SUCCESS;
3317	}
3318
3319
3320	/** @callback_method_impl{FNCPUMRDMSR} */
3321	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hLwpCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3322	{
3323	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3324	/** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
3325	/* Note: Only listes in BKDG for Family 15H. */
3326	*puValue = 0;
3327	return VINF_SUCCESS;
3328	}
3329
3330
3331	/** @callback_method_impl{FNCPUMWRMSR} */
3332	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hLwpCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3333	{
3334	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3335	/** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
3336	return VINF_SUCCESS;
3337	}
3338
3339
3340	/** @callback_method_impl{FNCPUMRDMSR} */
3341	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hLwpCbAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3342	{
3343	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3344	/** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
3345	/* Note: Only listes in BKDG for Family 15H. */
3346	*puValue = 0;
3347	return VINF_SUCCESS;
3348	}
3349
3350
3351	/** @callback_method_impl{FNCPUMWRMSR} */
3352	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hLwpCbAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3353	{
3354	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3355	/** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
3356	return VINF_SUCCESS;
3357	}
3358
3359
3360	/** @callback_method_impl{FNCPUMRDMSR} */
3361	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hMc4MiscN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3362	{
3363	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3364	/** @todo machine check. */
3365	*puValue = 0;
3366	return VINF_SUCCESS;
3367	}
3368
3369
3370	/** @callback_method_impl{FNCPUMWRMSR} */
3371	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hMc4MiscN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3372	{
3373	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3374	/** @todo machine check. */
3375	return VINF_SUCCESS;
3376	}
3377
3378
3379	/** @callback_method_impl{FNCPUMRDMSR} */
3380	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8PerfCtlN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3381	{
3382	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3383	/** @todo AMD performance events. */
3384	*puValue = 0;
3385	return VINF_SUCCESS;
3386	}
3387
3388
3389	/** @callback_method_impl{FNCPUMWRMSR} */
3390	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8PerfCtlN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3391	{
3392	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3393	/** @todo AMD performance events. */
3394	return VINF_SUCCESS;
3395	}
3396
3397
3398	/** @callback_method_impl{FNCPUMRDMSR} */
3399	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8PerfCtrN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3400	{
3401	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3402	/** @todo AMD performance events. */
3403	*puValue = 0;
3404	return VINF_SUCCESS;
3405	}
3406
3407
3408	/** @callback_method_impl{FNCPUMWRMSR} */
3409	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8PerfCtrN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3410	{
3411	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3412	/** @todo AMD performance events. */
3413	return VINF_SUCCESS;
3414	}
3415
3416
3417	/** @callback_method_impl{FNCPUMRDMSR} */
3418	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SysCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3419	{
3420	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
3421	/** @todo AMD SYS_CFG */
3422	*puValue = pRange->uValue;
3423	return VINF_SUCCESS;
3424	}
3425
3426
3427	/** @callback_method_impl{FNCPUMWRMSR} */
3428	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SysCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3429	{
3430	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3431	/** @todo AMD SYS_CFG */
3432	return VINF_SUCCESS;
3433	}
3434
3435
3436	/** @callback_method_impl{FNCPUMRDMSR} */
3437	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8HwCr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3438	{
3439	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3440	/** @todo AMD HW_CFG */
3441	*puValue = 0;
3442	return VINF_SUCCESS;
3443	}
3444
3445
3446	/** @callback_method_impl{FNCPUMWRMSR} */
3447	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8HwCr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3448	{
3449	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3450	/** @todo AMD HW_CFG */
3451	return VINF_SUCCESS;
3452	}
3453
3454
3455	/** @callback_method_impl{FNCPUMRDMSR} */
3456	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IorrBaseN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3457	{
3458	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3459	/** @todo AMD IorrMask/IorrBase */
3460	*puValue = 0;
3461	return VINF_SUCCESS;
3462	}
3463
3464
3465	/** @callback_method_impl{FNCPUMWRMSR} */
3466	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IorrBaseN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3467	{
3468	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3469	/** @todo AMD IorrMask/IorrBase */
3470	return VINF_SUCCESS;
3471	}
3472
3473
3474	/** @callback_method_impl{FNCPUMRDMSR} */
3475	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IorrMaskN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3476	{
3477	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3478	/** @todo AMD IorrMask/IorrBase */
3479	*puValue = 0;
3480	return VINF_SUCCESS;
3481	}
3482
3483
3484	/** @callback_method_impl{FNCPUMWRMSR} */
3485	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IorrMaskN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3486	{
3487	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3488	/** @todo AMD IorrMask/IorrBase */
3489	return VINF_SUCCESS;
3490	}
3491
3492
3493	/** @callback_method_impl{FNCPUMRDMSR} */
3494	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8TopOfMemN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3495	{
3496	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3497	*puValue = 0;
3498	/** @todo return 4GB - RamHoleSize here for TOPMEM. Figure out what to return
3499	* for TOPMEM2. */
3500	//if (pRange->uValue == 0)
3501	// *puValue = _4G - RamHoleSize;
3502	return VINF_SUCCESS;
3503	}
3504
3505
3506	/** @callback_method_impl{FNCPUMWRMSR} */
3507	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8TopOfMemN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3508	{
3509	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3510	/** @todo AMD TOPMEM and TOPMEM2/TOM2. */
3511	return VINF_SUCCESS;
3512	}
3513
3514
3515	/** @callback_method_impl{FNCPUMRDMSR} */
3516	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8NbCfg1(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3517	{
3518	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3519	/** @todo AMD NB_CFG1 */
3520	*puValue = 0;
3521	return VINF_SUCCESS;
3522	}
3523
3524
3525	/** @callback_method_impl{FNCPUMWRMSR} */
3526	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8NbCfg1(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3527	{
3528	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3529	/** @todo AMD NB_CFG1 */
3530	return VINF_SUCCESS;
3531	}
3532
3533
3534	/** @callback_method_impl{FNCPUMRDMSR} */
3535	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8McXcptRedir(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3536	{
3537	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3538	/** @todo machine check. */
3539	*puValue = 0;
3540	return VINF_SUCCESS;
3541	}
3542
3543
3544	/** @callback_method_impl{FNCPUMWRMSR} */
3545	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8McXcptRedir(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3546	{
3547	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3548	/** @todo machine check. */
3549	return VINF_SUCCESS;
3550	}
3551
3552
3553	/** @callback_method_impl{FNCPUMRDMSR} */
3554	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuNameN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3555	{
3556	RT_NOREF_PV(idMsr);
3557	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), pRange->uValue / 2 + 0x80000001);
3558	if (pLeaf)
3559	{
3560	if (!(pRange->uValue & 1))
3561	*puValue = RT_MAKE_U64(pLeaf->uEax, pLeaf->uEbx);
3562	else
3563	*puValue = RT_MAKE_U64(pLeaf->uEcx, pLeaf->uEdx);
3564	}
3565	else
3566	*puValue = 0;
3567	return VINF_SUCCESS;
3568	}
3569
3570
3571	/** @callback_method_impl{FNCPUMWRMSR} */
3572	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuNameN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3573	{
3574	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3575	/** @todo Remember guest programmed CPU name. */
3576	return VINF_SUCCESS;
3577	}
3578
3579
3580	/** @callback_method_impl{FNCPUMRDMSR} */
3581	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8HwThermalCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3582	{
3583	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
3584	/** @todo AMD HTC. */
3585	*puValue = pRange->uValue;
3586	return VINF_SUCCESS;
3587	}
3588
3589
3590	/** @callback_method_impl{FNCPUMWRMSR} */
3591	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8HwThermalCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3592	{
3593	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3594	/** @todo AMD HTC. */
3595	return VINF_SUCCESS;
3596	}
3597
3598
3599	/** @callback_method_impl{FNCPUMRDMSR} */
3600	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SwThermalCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3601	{
3602	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3603	/** @todo AMD STC. */
3604	*puValue = 0;
3605	return VINF_SUCCESS;
3606	}
3607
3608
3609	/** @callback_method_impl{FNCPUMWRMSR} */
3610	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SwThermalCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3611	{
3612	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3613	/** @todo AMD STC. */
3614	return VINF_SUCCESS;
3615	}
3616
3617
3618	/** @callback_method_impl{FNCPUMRDMSR} */
3619	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8FidVidControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3620	{
3621	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
3622	/** @todo AMD FIDVID_CTL. */
3623	*puValue = pRange->uValue;
3624	return VINF_SUCCESS;
3625	}
3626
3627
3628	/** @callback_method_impl{FNCPUMWRMSR} */
3629	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8FidVidControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3630	{
3631	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3632	/** @todo AMD FIDVID_CTL. */
3633	return VINF_SUCCESS;
3634	}
3635
3636
3637	/** @callback_method_impl{FNCPUMRDMSR} */
3638	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8FidVidStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3639	{
3640	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
3641	/** @todo AMD FIDVID_STATUS. */
3642	*puValue = pRange->uValue;
3643	return VINF_SUCCESS;
3644	}
3645
3646
3647	/** @callback_method_impl{FNCPUMRDMSR} */
3648	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8McCtlMaskN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3649	{
3650	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3651	/** @todo AMD MC. */
3652	*puValue = 0;
3653	return VINF_SUCCESS;
3654	}
3655
3656
3657	/** @callback_method_impl{FNCPUMWRMSR} */
3658	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8McCtlMaskN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3659	{
3660	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3661	/** @todo AMD MC. */
3662	return VINF_SUCCESS;
3663	}
3664
3665
3666	/** @callback_method_impl{FNCPUMRDMSR} */
3667	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmiOnIoTrapN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3668	{
3669	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3670	/** @todo AMD SMM/SMI and I/O trap. */
3671	*puValue = 0;
3672	return VINF_SUCCESS;
3673	}
3674
3675
3676	/** @callback_method_impl{FNCPUMWRMSR} */
3677	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmiOnIoTrapN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3678	{
3679	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3680	/** @todo AMD SMM/SMI and I/O trap. */
3681	return VINF_SUCCESS;
3682	}
3683
3684
3685	/** @callback_method_impl{FNCPUMRDMSR} */
3686	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmiOnIoTrapCtlSts(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3687	{
3688	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3689	/** @todo AMD SMM/SMI and I/O trap. */
3690	*puValue = 0;
3691	return VINF_SUCCESS;
3692	}
3693
3694
3695	/** @callback_method_impl{FNCPUMWRMSR} */
3696	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmiOnIoTrapCtlSts(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3697	{
3698	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3699	/** @todo AMD SMM/SMI and I/O trap. */
3700	return VINF_SUCCESS;
3701	}
3702
3703
3704	/** @callback_method_impl{FNCPUMRDMSR} */
3705	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IntPendingMessage(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3706	{
3707	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3708	/** @todo Interrupt pending message. */
3709	*puValue = 0;
3710	return VINF_SUCCESS;
3711	}
3712
3713
3714	/** @callback_method_impl{FNCPUMWRMSR} */
3715	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IntPendingMessage(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3716	{
3717	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3718	/** @todo Interrupt pending message. */
3719	return VINF_SUCCESS;
3720	}
3721
3722
3723	/** @callback_method_impl{FNCPUMRDMSR} */
3724	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmiTriggerIoCycle(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3725	{
3726	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3727	/** @todo AMD SMM/SMI and trigger I/O cycle. */
3728	*puValue = 0;
3729	return VINF_SUCCESS;
3730	}
3731
3732
3733	/** @callback_method_impl{FNCPUMWRMSR} */
3734	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmiTriggerIoCycle(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3735	{
3736	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3737	/** @todo AMD SMM/SMI and trigger I/O cycle. */
3738	return VINF_SUCCESS;
3739	}
3740
3741
3742	/** @callback_method_impl{FNCPUMRDMSR} */
3743	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hMmioCfgBaseAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3744	{
3745	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3746	/** @todo AMD MMIO Configuration base address. */
3747	*puValue = 0;
3748	return VINF_SUCCESS;
3749	}
3750
3751
3752	/** @callback_method_impl{FNCPUMWRMSR} */
3753	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hMmioCfgBaseAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3754	{
3755	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3756	/** @todo AMD MMIO Configuration base address. */
3757	return VINF_SUCCESS;
3758	}
3759
3760
3761	/** @callback_method_impl{FNCPUMRDMSR} */
3762	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hTrapCtlMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3763	{
3764	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3765	/** @todo AMD 0xc0010059. */
3766	*puValue = 0;
3767	return VINF_SUCCESS;
3768	}
3769
3770
3771	/** @callback_method_impl{FNCPUMWRMSR} */
3772	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hTrapCtlMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3773	{
3774	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3775	/** @todo AMD 0xc0010059. */
3776	return VINF_SUCCESS;
3777	}
3778
3779
3780	/** @callback_method_impl{FNCPUMRDMSR} */
3781	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateCurLimit(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3782	{
3783	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
3784	/** @todo AMD P-states. */
3785	*puValue = pRange->uValue;
3786	return VINF_SUCCESS;
3787	}
3788
3789
3790	/** @callback_method_impl{FNCPUMRDMSR} */
3791	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3792	{
3793	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
3794	/** @todo AMD P-states. */
3795	*puValue = pRange->uValue;
3796	return VINF_SUCCESS;
3797	}
3798
3799
3800	/** @callback_method_impl{FNCPUMWRMSR} */
3801	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hPStateControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3802	{
3803	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3804	/** @todo AMD P-states. */
3805	return VINF_SUCCESS;
3806	}
3807
3808
3809	/** @callback_method_impl{FNCPUMRDMSR} */
3810	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3811	{
3812	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
3813	/** @todo AMD P-states. */
3814	*puValue = pRange->uValue;
3815	return VINF_SUCCESS;
3816	}
3817
3818
3819	/** @callback_method_impl{FNCPUMWRMSR} */
3820	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hPStateStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3821	{
3822	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3823	/** @todo AMD P-states. */
3824	return VINF_SUCCESS;
3825	}
3826
3827
3828	/** @callback_method_impl{FNCPUMRDMSR} */
3829	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3830	{
3831	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
3832	/** @todo AMD P-states. */
3833	*puValue = pRange->uValue;
3834	return VINF_SUCCESS;
3835	}
3836
3837
3838	/** @callback_method_impl{FNCPUMWRMSR} */
3839	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hPStateN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3840	{
3841	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3842	/** @todo AMD P-states. */
3843	return VINF_SUCCESS;
3844	}
3845
3846
3847	/** @callback_method_impl{FNCPUMRDMSR} */
3848	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCofVidControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3849	{
3850	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
3851	/** @todo AMD P-states. */
3852	*puValue = pRange->uValue;
3853	return VINF_SUCCESS;
3854	}
3855
3856
3857	/** @callback_method_impl{FNCPUMWRMSR} */
3858	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCofVidControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3859	{
3860	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3861	/** @todo AMD P-states. */
3862	return VINF_SUCCESS;
3863	}
3864
3865
3866	/** @callback_method_impl{FNCPUMRDMSR} */
3867	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCofVidStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3868	{
3869	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
3870	/** @todo AMD P-states. */
3871	*puValue = pRange->uValue;
3872	return VINF_SUCCESS;
3873	}
3874
3875
3876	/** @callback_method_impl{FNCPUMWRMSR} */
3877	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCofVidStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3878	{
3879	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3880	/* Note! Writing 0 seems to not GP, not sure if it does anything to the value... */
3881	/** @todo AMD P-states. */
3882	return VINF_SUCCESS;
3883	}
3884
3885
3886	/** @callback_method_impl{FNCPUMRDMSR} */
3887	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCStateIoBaseAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3888	{
3889	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3890	/** @todo AMD C-states. */
3891	*puValue = 0;
3892	return VINF_SUCCESS;
3893	}
3894
3895
3896	/** @callback_method_impl{FNCPUMWRMSR} */
3897	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCStateIoBaseAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3898	{
3899	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3900	/** @todo AMD C-states. */
3901	return VINF_SUCCESS;
3902	}
3903
3904
3905	/** @callback_method_impl{FNCPUMRDMSR} */
3906	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCpuWatchdogTimer(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3907	{
3908	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3909	/** @todo AMD machine checks. */
3910	*puValue = 0;
3911	return VINF_SUCCESS;
3912	}
3913
3914
3915	/** @callback_method_impl{FNCPUMWRMSR} */
3916	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCpuWatchdogTimer(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3917	{
3918	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3919	/** @todo AMD machine checks. */
3920	return VINF_SUCCESS;
3921	}
3922
3923
3924	/** @callback_method_impl{FNCPUMRDMSR} */
3925	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmBase(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3926	{
3927	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3928	/** @todo AMD SMM. */
3929	*puValue = 0;
3930	return VINF_SUCCESS;
3931	}
3932
3933
3934	/** @callback_method_impl{FNCPUMWRMSR} */
3935	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmBase(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3936	{
3937	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3938	/** @todo AMD SMM. */
3939	return VINF_SUCCESS;
3940	}
3941
3942
3943	/** @callback_method_impl{FNCPUMRDMSR} */
3944	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3945	{
3946	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3947	/** @todo AMD SMM. */
3948	*puValue = 0;
3949	return VINF_SUCCESS;
3950	}
3951
3952
3953	/** @callback_method_impl{FNCPUMWRMSR} */
3954	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3955	{
3956	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3957	/** @todo AMD SMM. */
3958	return VINF_SUCCESS;
3959	}
3960
3961
3962
3963	/** @callback_method_impl{FNCPUMRDMSR} */
3964	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmMask(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3965	{
3966	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3967	/** @todo AMD SMM. */
3968	*puValue = 0;
3969	return VINF_SUCCESS;
3970	}
3971
3972
3973	/** @callback_method_impl{FNCPUMWRMSR} */
3974	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmMask(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3975	{
3976	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3977	/** @todo AMD SMM. */
3978	return VINF_SUCCESS;
3979	}
3980
3981
3982	/** @callback_method_impl{FNCPUMRDMSR} */
3983	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8VmCr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3984	{
3985	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3986	PVM pVM = pVCpu->CTX_SUFF(pVM);
3987	if (pVM->cpum.s.GuestFeatures.fSvm)
3988	*puValue = MSR_K8_VM_CR_LOCK;
3989	else
3990	*puValue = 0;
3991	return VINF_SUCCESS;
3992	}
3993
3994
3995	/** @callback_method_impl{FNCPUMWRMSR} */
3996	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8VmCr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3997	{
3998	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
3999	PVM pVM = pVCpu->CTX_SUFF(pVM);
4000	if (pVM->cpum.s.GuestFeatures.fSvm)
4001	{
4002	/* Silently ignore writes to LOCK and SVM_DISABLE bit when the LOCK bit is set (see cpumMsrRd_AmdK8VmCr). */
4003	if (uValue & (MSR_K8_VM_CR_DPD \| MSR_K8_VM_CR_R_INIT \| MSR_K8_VM_CR_DIS_A20M))
4004	return VERR_CPUM_RAISE_GP_0;
4005	return VINF_SUCCESS;
4006	}
4007	return VERR_CPUM_RAISE_GP_0;
4008	}
4009
4010
4011	/** @callback_method_impl{FNCPUMRDMSR} */
4012	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IgnNe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4013	{
4014	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4015	/** @todo AMD IGNNE\# control. */
4016	*puValue = 0;
4017	return VINF_SUCCESS;
4018	}
4019
4020
4021	/** @callback_method_impl{FNCPUMWRMSR} */
4022	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IgnNe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4023	{
4024	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4025	/** @todo AMD IGNNE\# control. */
4026	return VINF_SUCCESS;
4027	}
4028
4029
4030	/** @callback_method_impl{FNCPUMRDMSR} */
4031	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4032	{
4033	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4034	/** @todo AMD SMM. */
4035	*puValue = 0;
4036	return VINF_SUCCESS;
4037	}
4038
4039
4040	/** @callback_method_impl{FNCPUMWRMSR} */
4041	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4042	{
4043	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4044	/** @todo AMD SMM. */
4045	return VINF_SUCCESS;
4046	}
4047
4048
4049	/** @callback_method_impl{FNCPUMRDMSR} */
4050	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8VmHSavePa(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4051	{
4052	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4053	*puValue = pVCpu->cpum.s.Guest.hwvirt.svm.uMsrHSavePa;
4054	return VINF_SUCCESS;
4055	}
4056
4057
4058	/** @callback_method_impl{FNCPUMWRMSR} */
4059	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8VmHSavePa(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4060	{
4061	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
4062	if (uValue & UINT64_C(0xfff))
4063	{
4064	Log(("CPUM: Invalid setting of low 12 bits set writing host-state save area MSR %#x: %#llx\n", idMsr, uValue));
4065	return VERR_CPUM_RAISE_GP_0;
4066	}
4067
4068	uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
4069	if (fInvPhysMask & uValue)
4070	{
4071	Log(("CPUM: Invalid physical address bits set writing host-state save area MSR %#x: %#llx (%#llx)\n",
4072	idMsr, uValue, uValue & fInvPhysMask));
4073	return VERR_CPUM_RAISE_GP_0;
4074	}
4075
4076	pVCpu->cpum.s.Guest.hwvirt.svm.uMsrHSavePa = uValue;
4077	return VINF_SUCCESS;
4078	}
4079
4080
4081	/** @callback_method_impl{FNCPUMRDMSR} */
4082	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hVmLockKey(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4083	{
4084	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4085	/** @todo AMD SVM. */
4086	puValue = 0; / RAZ */
4087	return VINF_SUCCESS;
4088	}
4089
4090
4091	/** @callback_method_impl{FNCPUMWRMSR} */
4092	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hVmLockKey(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4093	{
4094	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4095	/** @todo AMD SVM. */
4096	return VINF_SUCCESS;
4097	}
4098
4099
4100	/** @callback_method_impl{FNCPUMRDMSR} */
4101	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hSmmLockKey(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4102	{
4103	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4104	/** @todo AMD SMM. */
4105	puValue = 0; / RAZ */
4106	return VINF_SUCCESS;
4107	}
4108
4109
4110	/** @callback_method_impl{FNCPUMWRMSR} */
4111	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hSmmLockKey(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4112	{
4113	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4114	/** @todo AMD SMM. */
4115	return VINF_SUCCESS;
4116	}
4117
4118
4119	/** @callback_method_impl{FNCPUMRDMSR} */
4120	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hLocalSmiStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4121	{
4122	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4123	/** @todo AMD SMM/SMI. */
4124	*puValue = 0;
4125	return VINF_SUCCESS;
4126	}
4127
4128
4129	/** @callback_method_impl{FNCPUMWRMSR} */
4130	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hLocalSmiStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4131	{
4132	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4133	/** @todo AMD SMM/SMI. */
4134	return VINF_SUCCESS;
4135	}
4136
4137
4138	/** @callback_method_impl{FNCPUMRDMSR} */
4139	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hOsVisWrkIdLength(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4140	{
4141	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
4142	/** @todo AMD OS visible workaround. */
4143	*puValue = pRange->uValue;
4144	return VINF_SUCCESS;
4145	}
4146
4147
4148	/** @callback_method_impl{FNCPUMWRMSR} */
4149	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hOsVisWrkIdLength(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4150	{
4151	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4152	/** @todo AMD OS visible workaround. */
4153	return VINF_SUCCESS;
4154	}
4155
4156
4157	/** @callback_method_impl{FNCPUMRDMSR} */
4158	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hOsVisWrkStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4159	{
4160	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4161	/** @todo AMD OS visible workaround. */
4162	*puValue = 0;
4163	return VINF_SUCCESS;
4164	}
4165
4166
4167	/** @callback_method_impl{FNCPUMWRMSR} */
4168	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hOsVisWrkStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4169	{
4170	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4171	/** @todo AMD OS visible workaround. */
4172	return VINF_SUCCESS;
4173	}
4174
4175
4176	/** @callback_method_impl{FNCPUMRDMSR} */
4177	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam16hL2IPerfCtlN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4178	{
4179	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4180	/** @todo AMD L2I performance counters. */
4181	*puValue = 0;
4182	return VINF_SUCCESS;
4183	}
4184
4185
4186	/** @callback_method_impl{FNCPUMWRMSR} */
4187	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam16hL2IPerfCtlN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4188	{
4189	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4190	/** @todo AMD L2I performance counters. */
4191	return VINF_SUCCESS;
4192	}
4193
4194
4195	/** @callback_method_impl{FNCPUMRDMSR} */
4196	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam16hL2IPerfCtrN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4197	{
4198	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4199	/** @todo AMD L2I performance counters. */
4200	*puValue = 0;
4201	return VINF_SUCCESS;
4202	}
4203
4204
4205	/** @callback_method_impl{FNCPUMWRMSR} */
4206	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam16hL2IPerfCtrN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4207	{
4208	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4209	/** @todo AMD L2I performance counters. */
4210	return VINF_SUCCESS;
4211	}
4212
4213
4214	/** @callback_method_impl{FNCPUMRDMSR} */
4215	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hNorthbridgePerfCtlN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4216	{
4217	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4218	/** @todo AMD Northbridge performance counters. */
4219	*puValue = 0;
4220	return VINF_SUCCESS;
4221	}
4222
4223
4224	/** @callback_method_impl{FNCPUMWRMSR} */
4225	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hNorthbridgePerfCtlN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4226	{
4227	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4228	/** @todo AMD Northbridge performance counters. */
4229	return VINF_SUCCESS;
4230	}
4231
4232
4233	/** @callback_method_impl{FNCPUMRDMSR} */
4234	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hNorthbridgePerfCtrN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4235	{
4236	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4237	/** @todo AMD Northbridge performance counters. */
4238	*puValue = 0;
4239	return VINF_SUCCESS;
4240	}
4241
4242
4243	/** @callback_method_impl{FNCPUMWRMSR} */
4244	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hNorthbridgePerfCtrN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4245	{
4246	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4247	/** @todo AMD Northbridge performance counters. */
4248	return VINF_SUCCESS;
4249	}
4250
4251
4252	/** @callback_method_impl{FNCPUMRDMSR} */
4253	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7MicrocodeCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4254	{
4255	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
4256	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4257	* cpus. Need to be explored and verify K7 presence. */
4258	/** @todo Undocumented register only seen mentioned in fam15h erratum \#608. */
4259	*puValue = pRange->uValue;
4260	return VINF_SUCCESS;
4261	}
4262
4263
4264	/** @callback_method_impl{FNCPUMWRMSR} */
4265	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7MicrocodeCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4266	{
4267	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4268	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4269	* cpus. Need to be explored and verify K7 presence. */
4270	/** @todo Undocumented register only seen mentioned in fam15h erratum \#608. */
4271	return VINF_SUCCESS;
4272	}
4273
4274
4275	/** @callback_method_impl{FNCPUMRDMSR} */
4276	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7ClusterIdMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4277	{
4278	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
4279	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4280	* cpus. Need to be explored and verify K7 presence. */
4281	/** @todo Undocumented register only seen mentioned in fam16h BKDG r3.00 when
4282	* describing EBL_CR_POWERON. */
4283	*puValue = pRange->uValue;
4284	return VINF_SUCCESS;
4285	}
4286
4287
4288	/** @callback_method_impl{FNCPUMWRMSR} */
4289	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7ClusterIdMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4290	{
4291	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4292	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4293	* cpus. Need to be explored and verify K7 presence. */
4294	/** @todo Undocumented register only seen mentioned in fam16h BKDG r3.00 when
4295	* describing EBL_CR_POWERON. */
4296	return VINF_SUCCESS;
4297	}
4298
4299
4300	/** @callback_method_impl{FNCPUMRDMSR} */
4301	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlStd07hEbax(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4302	{
4303	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4304	bool fIgnored;
4305	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafEx(pVCpu->CTX_SUFF(pVM), 0x00000007, 0, &fIgnored);
4306	if (pLeaf)
4307	*puValue = RT_MAKE_U64(pLeaf->uEbx, pLeaf->uEax);
4308	else
4309	*puValue = 0;
4310	return VINF_SUCCESS;
4311	}
4312
4313
4314	/** @callback_method_impl{FNCPUMWRMSR} */
4315	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlStd07hEbax(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4316	{
4317	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4318	/** @todo Changing CPUID leaf 7/0. */
4319	return VINF_SUCCESS;
4320	}
4321
4322
4323	/** @callback_method_impl{FNCPUMRDMSR} */
4324	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlStd06hEcx(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4325	{
4326	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4327	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000006);
4328	if (pLeaf)
4329	*puValue = pLeaf->uEcx;
4330	else
4331	*puValue = 0;
4332	return VINF_SUCCESS;
4333	}
4334
4335
4336	/** @callback_method_impl{FNCPUMWRMSR} */
4337	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlStd06hEcx(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4338	{
4339	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4340	/** @todo Changing CPUID leaf 6. */
4341	return VINF_SUCCESS;
4342	}
4343
4344
4345	/** @callback_method_impl{FNCPUMRDMSR} */
4346	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlStd01hEdcx(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4347	{
4348	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4349	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000001);
4350	if (pLeaf)
4351	*puValue = RT_MAKE_U64(pLeaf->uEdx, pLeaf->uEcx);
4352	else
4353	*puValue = 0;
4354	return VINF_SUCCESS;
4355	}
4356
4357
4358	/** @callback_method_impl{FNCPUMWRMSR} */
4359	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlStd01hEdcx(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4360	{
4361	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4362	/** @todo Changing CPUID leaf 0x80000001. */
4363	return VINF_SUCCESS;
4364	}
4365
4366
4367	/** @callback_method_impl{FNCPUMRDMSR} */
4368	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlExt01hEdcx(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4369	{
4370	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4371	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x80000001);
4372	if (pLeaf)
4373	*puValue = RT_MAKE_U64(pLeaf->uEdx, pLeaf->uEcx);
4374	else
4375	*puValue = 0;
4376	return VINF_SUCCESS;
4377	}
4378
4379
4380	/** @callback_method_impl{FNCPUMWRMSR} */
4381	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlExt01hEdcx(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4382	{
4383	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4384	/** @todo Changing CPUID leaf 0x80000001. */
4385	return VINF_SUCCESS;
4386	}
4387
4388
4389	/** @callback_method_impl{FNCPUMRDMSR} */
4390	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8PatchLevel(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4391	{
4392	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
4393	/** @todo Fake AMD microcode patching. */
4394	PVM const pVM = pVCpu->CTX_SUFF(pVM);
4395	if (pVM->cpum.s.GuestInfo.uMicrocodeRevision != UINT32_MAX)
4396	*puValue = RT_MAKE_U64(pVM->cpum.s.GuestInfo.uMicrocodeRevision, RT_HI_U32(pRange->uValue));
4397	else
4398	*puValue = pRange->uValue;
4399	return VINF_SUCCESS;
4400	}
4401
4402
4403	/** @callback_method_impl{FNCPUMWRMSR} */
4404	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8PatchLoader(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4405	{
4406	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4407	/** @todo Fake AMD microcode patching. */
4408	return VINF_SUCCESS;
4409	}
4410
4411
4412	/** @callback_method_impl{FNCPUMRDMSR} */
4413	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DebugStatusMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4414	{
4415	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4416	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4417	* cpus. Need to be explored and verify K7 presence. */
4418	/** @todo undocumented */
4419	*puValue = 0;
4420	return VINF_SUCCESS;
4421	}
4422
4423
4424	/** @callback_method_impl{FNCPUMWRMSR} */
4425	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DebugStatusMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4426	{
4427	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4428	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4429	* cpus. Need to be explored and verify K7 presence. */
4430	/** @todo undocumented */
4431	return VINF_SUCCESS;
4432	}
4433
4434
4435	/** @callback_method_impl{FNCPUMRDMSR} */
4436	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BHTraceBaseMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4437	{
4438	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4439	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4440	* cpus. Need to be explored and verify K7 presence. */
4441	/** @todo undocumented */
4442	*puValue = 0;
4443	return VINF_SUCCESS;
4444	}
4445
4446
4447	/** @callback_method_impl{FNCPUMWRMSR} */
4448	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BHTraceBaseMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4449	{
4450	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4451	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4452	* cpus. Need to be explored and verify K7 presence. */
4453	/** @todo undocumented */
4454	return VINF_SUCCESS;
4455	}
4456
4457
4458	/** @callback_method_impl{FNCPUMRDMSR} */
4459	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BHTracePtrMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4460	{
4461	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4462	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4463	* cpus. Need to be explored and verify K7 presence. */
4464	/** @todo undocumented */
4465	*puValue = 0;
4466	return VINF_SUCCESS;
4467	}
4468
4469
4470	/** @callback_method_impl{FNCPUMWRMSR} */
4471	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BHTracePtrMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4472	{
4473	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4474	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4475	* cpus. Need to be explored and verify K7 presence. */
4476	/** @todo undocumented */
4477	return VINF_SUCCESS;
4478	}
4479
4480
4481	/** @callback_method_impl{FNCPUMRDMSR} */
4482	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BHTraceLimitMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4483	{
4484	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4485	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4486	* cpus. Need to be explored and verify K7 presence. */
4487	/** @todo undocumented */
4488	*puValue = 0;
4489	return VINF_SUCCESS;
4490	}
4491
4492
4493	/** @callback_method_impl{FNCPUMWRMSR} */
4494	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BHTraceLimitMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4495	{
4496	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4497	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4498	* cpus. Need to be explored and verify K7 presence. */
4499	/** @todo undocumented */
4500	return VINF_SUCCESS;
4501	}
4502
4503
4504	/** @callback_method_impl{FNCPUMRDMSR} */
4505	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7HardwareDebugToolCfgMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4506	{
4507	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4508	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4509	* cpus. Need to be explored and verify K7 presence. */
4510	/** @todo undocumented */
4511	*puValue = 0;
4512	return VINF_SUCCESS;
4513	}
4514
4515
4516	/** @callback_method_impl{FNCPUMWRMSR} */
4517	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7HardwareDebugToolCfgMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4518	{
4519	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4520	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4521	* cpus. Need to be explored and verify K7 presence. */
4522	/** @todo undocumented */
4523	return VINF_SUCCESS;
4524	}
4525
4526
4527	/** @callback_method_impl{FNCPUMRDMSR} */
4528	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7FastFlushCountMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4529	{
4530	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4531	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4532	* cpus. Need to be explored and verify K7 presence. */
4533	/** @todo undocumented */
4534	*puValue = 0;
4535	return VINF_SUCCESS;
4536	}
4537
4538
4539	/** @callback_method_impl{FNCPUMWRMSR} */
4540	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7FastFlushCountMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4541	{
4542	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4543	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4544	* cpus. Need to be explored and verify K7 presence. */
4545	/** @todo undocumented */
4546	return VINF_SUCCESS;
4547	}
4548
4549
4550	/** @callback_method_impl{FNCPUMRDMSR} */
4551	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7NodeId(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4552	{
4553	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4554	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4555	* cpus. Need to be explored and verify K7 presence. */
4556	/** @todo AMD node ID and bios scratch. */
4557	puValue = 0; / nodeid = 0; nodes-per-cpu = 1 */
4558	return VINF_SUCCESS;
4559	}
4560
4561
4562	/** @callback_method_impl{FNCPUMWRMSR} */
4563	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7NodeId(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4564	{
4565	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4566	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4567	* cpus. Need to be explored and verify K7 presence. */
4568	/** @todo AMD node ID and bios scratch. */
4569	return VINF_SUCCESS;
4570	}
4571
4572
4573	/** @callback_method_impl{FNCPUMRDMSR} */
4574	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DrXAddrMaskN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4575	{
4576	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4577	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4578	* cpus. Need to be explored and verify K7 presence. */
4579	/** @todo AMD DRx address masking (range breakpoints). */
4580	*puValue = 0;
4581	return VINF_SUCCESS;
4582	}
4583
4584
4585	/** @callback_method_impl{FNCPUMWRMSR} */
4586	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DrXAddrMaskN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4587	{
4588	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4589	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4590	* cpus. Need to be explored and verify K7 presence. */
4591	/** @todo AMD DRx address masking (range breakpoints). */
4592	return VINF_SUCCESS;
4593	}
4594
4595
4596	/** @callback_method_impl{FNCPUMRDMSR} */
4597	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7Dr0DataMatchMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4598	{
4599	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4600	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4601	* cpus. Need to be explored and verify K7 presence. */
4602	/** @todo AMD undocument debugging features. */
4603	*puValue = 0;
4604	return VINF_SUCCESS;
4605	}
4606
4607
4608	/** @callback_method_impl{FNCPUMWRMSR} */
4609	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7Dr0DataMatchMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4610	{
4611	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4612	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4613	* cpus. Need to be explored and verify K7 presence. */
4614	/** @todo AMD undocument debugging features. */
4615	return VINF_SUCCESS;
4616	}
4617
4618
4619	/** @callback_method_impl{FNCPUMRDMSR} */
4620	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7Dr0DataMaskMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4621	{
4622	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4623	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4624	* cpus. Need to be explored and verify K7 presence. */
4625	/** @todo AMD undocument debugging features. */
4626	*puValue = 0;
4627	return VINF_SUCCESS;
4628	}
4629
4630
4631	/** @callback_method_impl{FNCPUMWRMSR} */
4632	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7Dr0DataMaskMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4633	{
4634	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4635	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4636	* cpus. Need to be explored and verify K7 presence. */
4637	/** @todo AMD undocument debugging features. */
4638	return VINF_SUCCESS;
4639	}
4640
4641
4642	/** @callback_method_impl{FNCPUMRDMSR} */
4643	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7LoadStoreCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4644	{
4645	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4646	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4647	* cpus. Need to be explored and verify K7 presence. */
4648	/** @todo AMD load-store config. */
4649	*puValue = 0;
4650	return VINF_SUCCESS;
4651	}
4652
4653
4654	/** @callback_method_impl{FNCPUMWRMSR} */
4655	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7LoadStoreCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4656	{
4657	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4658	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4659	* cpus. Need to be explored and verify K7 presence. */
4660	/** @todo AMD load-store config. */
4661	return VINF_SUCCESS;
4662	}
4663
4664
4665	/** @callback_method_impl{FNCPUMRDMSR} */
4666	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7InstrCacheCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4667	{
4668	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4669	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4670	* cpus. Need to be explored and verify K7 presence. */
4671	/** @todo AMD instruction cache config. */
4672	*puValue = 0;
4673	return VINF_SUCCESS;
4674	}
4675
4676
4677	/** @callback_method_impl{FNCPUMWRMSR} */
4678	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7InstrCacheCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4679	{
4680	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4681	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4682	* cpus. Need to be explored and verify K7 presence. */
4683	/** @todo AMD instruction cache config. */
4684	return VINF_SUCCESS;
4685	}
4686
4687
4688	/** @callback_method_impl{FNCPUMRDMSR} */
4689	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DataCacheCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4690	{
4691	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4692	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4693	* cpus. Need to be explored and verify K7 presence. */
4694	/** @todo AMD data cache config. */
4695	*puValue = 0;
4696	return VINF_SUCCESS;
4697	}
4698
4699
4700	/** @callback_method_impl{FNCPUMWRMSR} */
4701	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DataCacheCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4702	{
4703	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4704	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4705	* cpus. Need to be explored and verify K7 presence. */
4706	/** @todo AMD data cache config. */
4707	return VINF_SUCCESS;
4708	}
4709
4710
4711	/** @callback_method_impl{FNCPUMRDMSR} */
4712	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BusUnitCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4713	{
4714	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4715	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4716	* cpus. Need to be explored and verify K7 presence. */
4717	/** @todo AMD bus unit config. */
4718	*puValue = 0;
4719	return VINF_SUCCESS;
4720	}
4721
4722
4723	/** @callback_method_impl{FNCPUMWRMSR} */
4724	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BusUnitCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4725	{
4726	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4727	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4728	* cpus. Need to be explored and verify K7 presence. */
4729	/** @todo AMD bus unit config. */
4730	return VINF_SUCCESS;
4731	}
4732
4733
4734	/** @callback_method_impl{FNCPUMRDMSR} */
4735	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DebugCtl2Maybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4736	{
4737	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4738	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4739	* cpus. Need to be explored and verify K7 presence. */
4740	/** @todo Undocument AMD debug control register \#2. */
4741	*puValue = 0;
4742	return VINF_SUCCESS;
4743	}
4744
4745
4746	/** @callback_method_impl{FNCPUMWRMSR} */
4747	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DebugCtl2Maybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4748	{
4749	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4750	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4751	* cpus. Need to be explored and verify K7 presence. */
4752	/** @todo Undocument AMD debug control register \#2. */
4753	return VINF_SUCCESS;
4754	}
4755
4756
4757	/** @callback_method_impl{FNCPUMRDMSR} */
4758	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hFpuCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4759	{
4760	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4761	/** @todo AMD FPU config. */
4762	*puValue = 0;
4763	return VINF_SUCCESS;
4764	}
4765
4766
4767	/** @callback_method_impl{FNCPUMWRMSR} */
4768	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hFpuCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4769	{
4770	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4771	/** @todo AMD FPU config. */
4772	return VINF_SUCCESS;
4773	}
4774
4775
4776	/** @callback_method_impl{FNCPUMRDMSR} */
4777	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hDecoderCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4778	{
4779	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4780	/** @todo AMD decoder config. */
4781	*puValue = 0;
4782	return VINF_SUCCESS;
4783	}
4784
4785
4786	/** @callback_method_impl{FNCPUMWRMSR} */
4787	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hDecoderCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4788	{
4789	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4790	/** @todo AMD decoder config. */
4791	return VINF_SUCCESS;
4792	}
4793
4794
4795	/** @callback_method_impl{FNCPUMRDMSR} */
4796	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hBusUnitCfg2(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4797	{
4798	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4799	/* Note! 10h and 16h */
4800	/** @todo AMD bus unit config. */
4801	*puValue = 0;
4802	return VINF_SUCCESS;
4803	}
4804
4805
4806	/** @callback_method_impl{FNCPUMWRMSR} */
4807	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hBusUnitCfg2(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4808	{
4809	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4810	/* Note! 10h and 16h */
4811	/** @todo AMD bus unit config. */
4812	return VINF_SUCCESS;
4813	}
4814
4815
4816	/** @callback_method_impl{FNCPUMRDMSR} */
4817	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hCombUnitCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4818	{
4819	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4820	/** @todo AMD unit config. */
4821	*puValue = 0;
4822	return VINF_SUCCESS;
4823	}
4824
4825
4826	/** @callback_method_impl{FNCPUMWRMSR} */
4827	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hCombUnitCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4828	{
4829	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4830	/** @todo AMD unit config. */
4831	return VINF_SUCCESS;
4832	}
4833
4834
4835	/** @callback_method_impl{FNCPUMRDMSR} */
4836	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hCombUnitCfg2(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4837	{
4838	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4839	/** @todo AMD unit config 2. */
4840	*puValue = 0;
4841	return VINF_SUCCESS;
4842	}
4843
4844
4845	/** @callback_method_impl{FNCPUMWRMSR} */
4846	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hCombUnitCfg2(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4847	{
4848	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4849	/** @todo AMD unit config 2. */
4850	return VINF_SUCCESS;
4851	}
4852
4853
4854	/** @callback_method_impl{FNCPUMRDMSR} */
4855	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hCombUnitCfg3(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4856	{
4857	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4858	/** @todo AMD combined unit config 3. */
4859	*puValue = 0;
4860	return VINF_SUCCESS;
4861	}
4862
4863
4864	/** @callback_method_impl{FNCPUMWRMSR} */
4865	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hCombUnitCfg3(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4866	{
4867	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4868	/** @todo AMD combined unit config 3. */
4869	return VINF_SUCCESS;
4870	}
4871
4872
4873	/** @callback_method_impl{FNCPUMRDMSR} */
4874	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hExecUnitCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4875	{
4876	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4877	/** @todo AMD execution unit config. */
4878	*puValue = 0;
4879	return VINF_SUCCESS;
4880	}
4881
4882
4883	/** @callback_method_impl{FNCPUMWRMSR} */
4884	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hExecUnitCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4885	{
4886	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4887	/** @todo AMD execution unit config. */
4888	return VINF_SUCCESS;
4889	}
4890
4891
4892	/** @callback_method_impl{FNCPUMRDMSR} */
4893	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hLoadStoreCfg2(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4894	{
4895	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4896	/** @todo AMD load-store config 2. */
4897	*puValue = 0;
4898	return VINF_SUCCESS;
4899	}
4900
4901
4902	/** @callback_method_impl{FNCPUMWRMSR} */
4903	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hLoadStoreCfg2(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4904	{
4905	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4906	/** @todo AMD load-store config 2. */
4907	return VINF_SUCCESS;
4908	}
4909
4910
4911	/** @callback_method_impl{FNCPUMRDMSR} */
4912	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsFetchCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4913	{
4914	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4915	/** @todo AMD IBS. */
4916	*puValue = 0;
4917	return VINF_SUCCESS;
4918	}
4919
4920
4921	/** @callback_method_impl{FNCPUMWRMSR} */
4922	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsFetchCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4923	{
4924	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4925	/** @todo AMD IBS. */
4926	return VINF_SUCCESS;
4927	}
4928
4929
4930	/** @callback_method_impl{FNCPUMRDMSR} */
4931	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsFetchLinAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4932	{
4933	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4934	/** @todo AMD IBS. */
4935	*puValue = 0;
4936	return VINF_SUCCESS;
4937	}
4938
4939
4940	/** @callback_method_impl{FNCPUMWRMSR} */
4941	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsFetchLinAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4942	{
4943	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4944	/** @todo AMD IBS. */
4945	return VINF_SUCCESS;
4946	}
4947
4948
4949	/** @callback_method_impl{FNCPUMRDMSR} */
4950	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsFetchPhysAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4951	{
4952	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4953	/** @todo AMD IBS. */
4954	*puValue = 0;
4955	return VINF_SUCCESS;
4956	}
4957
4958
4959	/** @callback_method_impl{FNCPUMWRMSR} */
4960	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsFetchPhysAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4961	{
4962	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4963	/** @todo AMD IBS. */
4964	return VINF_SUCCESS;
4965	}
4966
4967
4968	/** @callback_method_impl{FNCPUMRDMSR} */
4969	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpExecCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4970	{
4971	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4972	/** @todo AMD IBS. */
4973	*puValue = 0;
4974	return VINF_SUCCESS;
4975	}
4976
4977
4978	/** @callback_method_impl{FNCPUMWRMSR} */
4979	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpExecCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4980	{
4981	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4982	/** @todo AMD IBS. */
4983	return VINF_SUCCESS;
4984	}
4985
4986
4987	/** @callback_method_impl{FNCPUMRDMSR} */
4988	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpRip(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4989	{
4990	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4991	/** @todo AMD IBS. */
4992	*puValue = 0;
4993	return VINF_SUCCESS;
4994	}
4995
4996
4997	/** @callback_method_impl{FNCPUMWRMSR} */
4998	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpRip(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4999	{
5000	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
5001	/** @todo AMD IBS. */
5002	if (!X86_IS_CANONICAL(uValue))
5003	{
5004	Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
5005	return VERR_CPUM_RAISE_GP_0;
5006	}
5007	return VINF_SUCCESS;
5008	}
5009
5010
5011	/** @callback_method_impl{FNCPUMRDMSR} */
5012	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpData(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
5013	{
5014	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
5015	/** @todo AMD IBS. */
5016	*puValue = 0;
5017	return VINF_SUCCESS;
5018	}
5019
5020
5021	/** @callback_method_impl{FNCPUMWRMSR} */
5022	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpData(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
5023	{
5024	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
5025	/** @todo AMD IBS. */
5026	return VINF_SUCCESS;
5027	}
5028
5029
5030	/** @callback_method_impl{FNCPUMRDMSR} */
5031	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpData2(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
5032	{
5033	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
5034	/** @todo AMD IBS. */
5035	*puValue = 0;
5036	return VINF_SUCCESS;
5037	}
5038
5039
5040	/** @callback_method_impl{FNCPUMWRMSR} */
5041	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpData2(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
5042	{
5043	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
5044	/** @todo AMD IBS. */
5045	return VINF_SUCCESS;
5046	}
5047
5048
5049	/** @callback_method_impl{FNCPUMRDMSR} */
5050	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpData3(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
5051	{
5052	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
5053	/** @todo AMD IBS. */
5054	*puValue = 0;
5055	return VINF_SUCCESS;
5056	}
5057
5058
5059	/** @callback_method_impl{FNCPUMWRMSR} */
5060	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpData3(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
5061	{
5062	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
5063	/** @todo AMD IBS. */
5064	return VINF_SUCCESS;
5065	}
5066
5067
5068	/** @callback_method_impl{FNCPUMRDMSR} */
5069	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsDcLinAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
5070	{
5071	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
5072	/** @todo AMD IBS. */
5073	*puValue = 0;
5074	return VINF_SUCCESS;
5075	}
5076
5077
5078	/** @callback_method_impl{FNCPUMWRMSR} */
5079	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsDcLinAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
5080	{
5081	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
5082	/** @todo AMD IBS. */
5083	if (!X86_IS_CANONICAL(uValue))
5084	{
5085	Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
5086	return VERR_CPUM_RAISE_GP_0;
5087	}
5088	return VINF_SUCCESS;
5089	}
5090
5091
5092	/** @callback_method_impl{FNCPUMRDMSR} */
5093	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsDcPhysAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
5094	{
5095	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
5096	/** @todo AMD IBS. */
5097	*puValue = 0;
5098	return VINF_SUCCESS;
5099	}
5100
5101
5102	/** @callback_method_impl{FNCPUMWRMSR} */
5103	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsDcPhysAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
5104	{
5105	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
5106	/** @todo AMD IBS. */
5107	return VINF_SUCCESS;
5108	}
5109
5110
5111	/** @callback_method_impl{FNCPUMRDMSR} */
5112	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
5113	{
5114	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
5115	/** @todo AMD IBS. */
5116	*puValue = 0;
5117	return VINF_SUCCESS;
5118	}
5119
5120
5121	/** @callback_method_impl{FNCPUMWRMSR} */
5122	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
5123	{
5124	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
5125	/** @todo AMD IBS. */
5126	return VINF_SUCCESS;
5127	}
5128
5129
5130	/** @callback_method_impl{FNCPUMRDMSR} */
5131	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam14hIbsBrTarget(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
5132	{
5133	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
5134	/** @todo AMD IBS. */
5135	*puValue = 0;
5136	return VINF_SUCCESS;
5137	}
5138
5139
5140	/** @callback_method_impl{FNCPUMWRMSR} */
5141	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam14hIbsBrTarget(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
5142	{
5143	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
5144	/** @todo AMD IBS. */
5145	if (!X86_IS_CANONICAL(uValue))
5146	{
5147	Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
5148	return VERR_CPUM_RAISE_GP_0;
5149	}
5150	return VINF_SUCCESS;
5151	}
5152
5153
5154
5155	/*
5156	* GIM MSRs.
5157	* GIM MSRs.
5158	* GIM MSRs.
5159	*/
5160
5161
5162	/** @callback_method_impl{FNCPUMRDMSR} */
5163	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Gim(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
5164	{
5165	#if defined(VBOX_WITH_NESTED_HWVIRT_SVM) \|\| defined(VBOX_WITH_NESTED_HWVIRT_VMX)
5166	/* Raise #GP(0) like a physical CPU would since the nested-hypervisor hasn't intercept these MSRs. */
5167	if ( CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.s.Guest)
5168	\|\| CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.s.Guest))
5169	return VERR_CPUM_RAISE_GP_0;
5170	#endif
5171	return GIMReadMsr(pVCpu, idMsr, pRange, puValue);
5172	}
5173
5174
5175	/** @callback_method_impl{FNCPUMWRMSR} */
5176	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Gim(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
5177	{
5178	#if defined(VBOX_WITH_NESTED_HWVIRT_SVM) \|\| defined(VBOX_WITH_NESTED_HWVIRT_VMX)
5179	/* Raise #GP(0) like a physical CPU would since the nested-hypervisor hasn't intercept these MSRs. */
5180	if ( CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.s.Guest)
5181	\|\| CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.s.Guest))
5182	return VERR_CPUM_RAISE_GP_0;
5183	#endif
5184	return GIMWriteMsr(pVCpu, idMsr, pRange, uValue, uRawValue);
5185	}
5186
5187
5188	/**
5189	* MSR read function table.
5190	*/
5191	static const struct READMSRCLANG11WEIRDNOTHROW { PFNCPUMRDMSR pfnRdMsr; } g_aCpumRdMsrFns[kCpumMsrRdFn_End] =
5192	{
5193	{ NULL }, /* Invalid */
5194	{ cpumMsrRd_FixedValue },
5195	{ NULL }, /* Alias */
5196	{ cpumMsrRd_WriteOnly },
5197	{ cpumMsrRd_Ia32P5McAddr },
5198	{ cpumMsrRd_Ia32P5McType },
5199	{ cpumMsrRd_Ia32TimestampCounter },
5200	{ cpumMsrRd_Ia32PlatformId },
5201	{ cpumMsrRd_Ia32ApicBase },
5202	{ cpumMsrRd_Ia32FeatureControl },
5203	{ cpumMsrRd_Ia32BiosSignId },
5204	{ cpumMsrRd_Ia32SmmMonitorCtl },
5205	{ cpumMsrRd_Ia32PmcN },
5206	{ cpumMsrRd_Ia32MonitorFilterLineSize },
5207	{ cpumMsrRd_Ia32MPerf },
5208	{ cpumMsrRd_Ia32APerf },
5209	{ cpumMsrRd_Ia32MtrrCap },
5210	{ cpumMsrRd_Ia32MtrrPhysBaseN },
5211	{ cpumMsrRd_Ia32MtrrPhysMaskN },
5212	{ cpumMsrRd_Ia32MtrrFixed },
5213	{ cpumMsrRd_Ia32MtrrDefType },
5214	{ cpumMsrRd_Ia32Pat },
5215	{ cpumMsrRd_Ia32SysEnterCs },
5216	{ cpumMsrRd_Ia32SysEnterEsp },
5217	{ cpumMsrRd_Ia32SysEnterEip },
5218	{ cpumMsrRd_Ia32McgCap },
5219	{ cpumMsrRd_Ia32McgStatus },
5220	{ cpumMsrRd_Ia32McgCtl },
5221	{ cpumMsrRd_Ia32DebugCtl },
5222	{ cpumMsrRd_Ia32SmrrPhysBase },
5223	{ cpumMsrRd_Ia32SmrrPhysMask },
5224	{ cpumMsrRd_Ia32PlatformDcaCap },
5225	{ cpumMsrRd_Ia32CpuDcaCap },
5226	{ cpumMsrRd_Ia32Dca0Cap },
5227	{ cpumMsrRd_Ia32PerfEvtSelN },
5228	{ cpumMsrRd_Ia32PerfStatus },
5229	{ cpumMsrRd_Ia32PerfCtl },
5230	{ cpumMsrRd_Ia32FixedCtrN },
5231	{ cpumMsrRd_Ia32PerfCapabilities },
5232	{ cpumMsrRd_Ia32FixedCtrCtrl },
5233	{ cpumMsrRd_Ia32PerfGlobalStatus },
5234	{ cpumMsrRd_Ia32PerfGlobalCtrl },
5235	{ cpumMsrRd_Ia32PerfGlobalOvfCtrl },
5236	{ cpumMsrRd_Ia32PebsEnable },
5237	{ cpumMsrRd_Ia32ClockModulation },
5238	{ cpumMsrRd_Ia32ThermInterrupt },
5239	{ cpumMsrRd_Ia32ThermStatus },
5240	{ cpumMsrRd_Ia32Therm2Ctl },
5241	{ cpumMsrRd_Ia32MiscEnable },
5242	{ cpumMsrRd_Ia32McCtlStatusAddrMiscN },
5243	{ cpumMsrRd_Ia32McNCtl2 },
5244	{ cpumMsrRd_Ia32DsArea },
5245	{ cpumMsrRd_Ia32TscDeadline },
5246	{ cpumMsrRd_Ia32X2ApicN },
5247	{ cpumMsrRd_Ia32DebugInterface },
5248	{ cpumMsrRd_Ia32VmxBasic },
5249	{ cpumMsrRd_Ia32VmxPinbasedCtls },
5250	{ cpumMsrRd_Ia32VmxProcbasedCtls },
5251	{ cpumMsrRd_Ia32VmxExitCtls },
5252	{ cpumMsrRd_Ia32VmxEntryCtls },
5253	{ cpumMsrRd_Ia32VmxMisc },
5254	{ cpumMsrRd_Ia32VmxCr0Fixed0 },
5255	{ cpumMsrRd_Ia32VmxCr0Fixed1 },
5256	{ cpumMsrRd_Ia32VmxCr4Fixed0 },
5257	{ cpumMsrRd_Ia32VmxCr4Fixed1 },
5258	{ cpumMsrRd_Ia32VmxVmcsEnum },
5259	{ cpumMsrRd_Ia32VmxProcBasedCtls2 },
5260	{ cpumMsrRd_Ia32VmxEptVpidCap },
5261	{ cpumMsrRd_Ia32VmxTruePinbasedCtls },
5262	{ cpumMsrRd_Ia32VmxTrueProcbasedCtls },
5263	{ cpumMsrRd_Ia32VmxTrueExitCtls },
5264	{ cpumMsrRd_Ia32VmxTrueEntryCtls },
5265	{ cpumMsrRd_Ia32VmxVmFunc },
5266	{ cpumMsrRd_Ia32SpecCtrl },
5267	{ cpumMsrRd_Ia32ArchCapabilities },
5268
5269	{ cpumMsrRd_Amd64Efer },
5270	{ cpumMsrRd_Amd64SyscallTarget },
5271	{ cpumMsrRd_Amd64LongSyscallTarget },
5272	{ cpumMsrRd_Amd64CompSyscallTarget },
5273	{ cpumMsrRd_Amd64SyscallFlagMask },
5274	{ cpumMsrRd_Amd64FsBase },
5275	{ cpumMsrRd_Amd64GsBase },
5276	{ cpumMsrRd_Amd64KernelGsBase },
5277	{ cpumMsrRd_Amd64TscAux },
5278
5279	{ cpumMsrRd_IntelEblCrPowerOn },
5280	{ cpumMsrRd_IntelI7CoreThreadCount },
5281	{ cpumMsrRd_IntelP4EbcHardPowerOn },
5282	{ cpumMsrRd_IntelP4EbcSoftPowerOn },
5283	{ cpumMsrRd_IntelP4EbcFrequencyId },
5284	{ cpumMsrRd_IntelP6FsbFrequency },
5285	{ cpumMsrRd_IntelPlatformInfo },
5286	{ cpumMsrRd_IntelFlexRatio },
5287	{ cpumMsrRd_IntelPkgCStConfigControl },
5288	{ cpumMsrRd_IntelPmgIoCaptureBase },
5289	{ cpumMsrRd_IntelLastBranchFromToN },
5290	{ cpumMsrRd_IntelLastBranchFromN },
5291	{ cpumMsrRd_IntelLastBranchToN },
5292	{ cpumMsrRd_IntelLastBranchTos },
5293	{ cpumMsrRd_IntelBblCrCtl },
5294	{ cpumMsrRd_IntelBblCrCtl3 },
5295	{ cpumMsrRd_IntelI7TemperatureTarget },
5296	{ cpumMsrRd_IntelI7MsrOffCoreResponseN },
5297	{ cpumMsrRd_IntelI7MiscPwrMgmt },
5298	{ cpumMsrRd_IntelP6CrN },
5299	{ cpumMsrRd_IntelCpuId1FeatureMaskEcdx },
5300	{ cpumMsrRd_IntelCpuId1FeatureMaskEax },
5301	{ cpumMsrRd_IntelCpuId80000001FeatureMaskEcdx },
5302	{ cpumMsrRd_IntelI7SandyAesNiCtl },
5303	{ cpumMsrRd_IntelI7TurboRatioLimit },
5304	{ cpumMsrRd_IntelI7LbrSelect },
5305	{ cpumMsrRd_IntelI7SandyErrorControl },
5306	{ cpumMsrRd_IntelI7VirtualLegacyWireCap },
5307	{ cpumMsrRd_IntelI7PowerCtl },
5308	{ cpumMsrRd_IntelI7SandyPebsNumAlt },
5309	{ cpumMsrRd_IntelI7PebsLdLat },
5310	{ cpumMsrRd_IntelI7PkgCnResidencyN },
5311	{ cpumMsrRd_IntelI7CoreCnResidencyN },
5312	{ cpumMsrRd_IntelI7SandyVrCurrentConfig },
5313	{ cpumMsrRd_IntelI7SandyVrMiscConfig },
5314	{ cpumMsrRd_IntelI7SandyRaplPowerUnit },
5315	{ cpumMsrRd_IntelI7SandyPkgCnIrtlN },
5316	{ cpumMsrRd_IntelI7SandyPkgC2Residency },
5317	{ cpumMsrRd_IntelI7RaplPkgPowerLimit },
5318	{ cpumMsrRd_IntelI7RaplPkgEnergyStatus },
5319	{ cpumMsrRd_IntelI7RaplPkgPerfStatus },
5320	{ cpumMsrRd_IntelI7RaplPkgPowerInfo },
5321	{ cpumMsrRd_IntelI7RaplDramPowerLimit },
5322	{ cpumMsrRd_IntelI7RaplDramEnergyStatus },
5323	{ cpumMsrRd_IntelI7RaplDramPerfStatus },
5324	{ cpumMsrRd_IntelI7RaplDramPowerInfo },
5325	{ cpumMsrRd_IntelI7RaplPp0PowerLimit },
5326	{ cpumMsrRd_IntelI7RaplPp0EnergyStatus },
5327	{ cpumMsrRd_IntelI7RaplPp0Policy },
5328	{ cpumMsrRd_IntelI7RaplPp0PerfStatus },
5329	{ cpumMsrRd_IntelI7RaplPp1PowerLimit },
5330	{ cpumMsrRd_IntelI7RaplPp1EnergyStatus },
5331	{ cpumMsrRd_IntelI7RaplPp1Policy },
5332	{ cpumMsrRd_IntelI7IvyConfigTdpNominal },
5333	{ cpumMsrRd_IntelI7IvyConfigTdpLevel1 },
5334	{ cpumMsrRd_IntelI7IvyConfigTdpLevel2 },
5335	{ cpumMsrRd_IntelI7IvyConfigTdpControl },
5336	{ cpumMsrRd_IntelI7IvyTurboActivationRatio },
5337	{ cpumMsrRd_IntelI7UncPerfGlobalCtrl },
5338	{ cpumMsrRd_IntelI7UncPerfGlobalStatus },
5339	{ cpumMsrRd_IntelI7UncPerfGlobalOvfCtrl },
5340	{ cpumMsrRd_IntelI7UncPerfFixedCtrCtrl },
5341	{ cpumMsrRd_IntelI7UncPerfFixedCtr },
5342	{ cpumMsrRd_IntelI7UncCBoxConfig },
5343	{ cpumMsrRd_IntelI7UncArbPerfCtrN },
5344	{ cpumMsrRd_IntelI7UncArbPerfEvtSelN },
5345	{ cpumMsrRd_IntelI7SmiCount },
5346	{ cpumMsrRd_IntelCore2EmttmCrTablesN },
5347	{ cpumMsrRd_IntelCore2SmmCStMiscInfo },
5348	{ cpumMsrRd_IntelCore1ExtConfig },
5349	{ cpumMsrRd_IntelCore1DtsCalControl },
5350	{ cpumMsrRd_IntelCore2PeciControl },
5351	{ cpumMsrRd_IntelAtSilvCoreC1Recidency },
5352
5353	{ cpumMsrRd_P6LastBranchFromIp },
5354	{ cpumMsrRd_P6LastBranchToIp },
5355	{ cpumMsrRd_P6LastIntFromIp },
5356	{ cpumMsrRd_P6LastIntToIp },
5357
5358	{ cpumMsrRd_AmdFam15hTscRate },
5359	{ cpumMsrRd_AmdFam15hLwpCfg },
5360	{ cpumMsrRd_AmdFam15hLwpCbAddr },
5361	{ cpumMsrRd_AmdFam10hMc4MiscN },
5362	{ cpumMsrRd_AmdK8PerfCtlN },
5363	{ cpumMsrRd_AmdK8PerfCtrN },
5364	{ cpumMsrRd_AmdK8SysCfg },
5365	{ cpumMsrRd_AmdK8HwCr },
5366	{ cpumMsrRd_AmdK8IorrBaseN },
5367	{ cpumMsrRd_AmdK8IorrMaskN },
5368	{ cpumMsrRd_AmdK8TopOfMemN },
5369	{ cpumMsrRd_AmdK8NbCfg1 },
5370	{ cpumMsrRd_AmdK8McXcptRedir },
5371	{ cpumMsrRd_AmdK8CpuNameN },
5372	{ cpumMsrRd_AmdK8HwThermalCtrl },
5373	{ cpumMsrRd_AmdK8SwThermalCtrl },
5374	{ cpumMsrRd_AmdK8FidVidControl },
5375	{ cpumMsrRd_AmdK8FidVidStatus },
5376	{ cpumMsrRd_AmdK8McCtlMaskN },
5377	{ cpumMsrRd_AmdK8SmiOnIoTrapN },
5378	{ cpumMsrRd_AmdK8SmiOnIoTrapCtlSts },
5379	{ cpumMsrRd_AmdK8IntPendingMessage },
5380	{ cpumMsrRd_AmdK8SmiTriggerIoCycle },
5381	{ cpumMsrRd_AmdFam10hMmioCfgBaseAddr },
5382	{ cpumMsrRd_AmdFam10hTrapCtlMaybe },
5383	{ cpumMsrRd_AmdFam10hPStateCurLimit },
5384	{ cpumMsrRd_AmdFam10hPStateControl },
5385	{ cpumMsrRd_AmdFam10hPStateStatus },
5386	{ cpumMsrRd_AmdFam10hPStateN },
5387	{ cpumMsrRd_AmdFam10hCofVidControl },
5388	{ cpumMsrRd_AmdFam10hCofVidStatus },
5389	{ cpumMsrRd_AmdFam10hCStateIoBaseAddr },
5390	{ cpumMsrRd_AmdFam10hCpuWatchdogTimer },
5391	{ cpumMsrRd_AmdK8SmmBase },
5392	{ cpumMsrRd_AmdK8SmmAddr },
5393	{ cpumMsrRd_AmdK8SmmMask },
5394	{ cpumMsrRd_AmdK8VmCr },
5395	{ cpumMsrRd_AmdK8IgnNe },
5396	{ cpumMsrRd_AmdK8SmmCtl },
5397	{ cpumMsrRd_AmdK8VmHSavePa },
5398	{ cpumMsrRd_AmdFam10hVmLockKey },
5399	{ cpumMsrRd_AmdFam10hSmmLockKey },
5400	{ cpumMsrRd_AmdFam10hLocalSmiStatus },
5401	{ cpumMsrRd_AmdFam10hOsVisWrkIdLength },
5402	{ cpumMsrRd_AmdFam10hOsVisWrkStatus },
5403	{ cpumMsrRd_AmdFam16hL2IPerfCtlN },
5404	{ cpumMsrRd_AmdFam16hL2IPerfCtrN },
5405	{ cpumMsrRd_AmdFam15hNorthbridgePerfCtlN },
5406	{ cpumMsrRd_AmdFam15hNorthbridgePerfCtrN },
5407	{ cpumMsrRd_AmdK7MicrocodeCtl },
5408	{ cpumMsrRd_AmdK7ClusterIdMaybe },
5409	{ cpumMsrRd_AmdK8CpuIdCtlStd07hEbax },
5410	{ cpumMsrRd_AmdK8CpuIdCtlStd06hEcx },
5411	{ cpumMsrRd_AmdK8CpuIdCtlStd01hEdcx },
5412	{ cpumMsrRd_AmdK8CpuIdCtlExt01hEdcx },
5413	{ cpumMsrRd_AmdK8PatchLevel },
5414	{ cpumMsrRd_AmdK7DebugStatusMaybe },
5415	{ cpumMsrRd_AmdK7BHTraceBaseMaybe },
5416	{ cpumMsrRd_AmdK7BHTracePtrMaybe },
5417	{ cpumMsrRd_AmdK7BHTraceLimitMaybe },
5418	{ cpumMsrRd_AmdK7HardwareDebugToolCfgMaybe },
5419	{ cpumMsrRd_AmdK7FastFlushCountMaybe },
5420	{ cpumMsrRd_AmdK7NodeId },
5421	{ cpumMsrRd_AmdK7DrXAddrMaskN },
5422	{ cpumMsrRd_AmdK7Dr0DataMatchMaybe },
5423	{ cpumMsrRd_AmdK7Dr0DataMaskMaybe },
5424	{ cpumMsrRd_AmdK7LoadStoreCfg },
5425	{ cpumMsrRd_AmdK7InstrCacheCfg },
5426	{ cpumMsrRd_AmdK7DataCacheCfg },
5427	{ cpumMsrRd_AmdK7BusUnitCfg },
5428	{ cpumMsrRd_AmdK7DebugCtl2Maybe },
5429	{ cpumMsrRd_AmdFam15hFpuCfg },
5430	{ cpumMsrRd_AmdFam15hDecoderCfg },
5431	{ cpumMsrRd_AmdFam10hBusUnitCfg2 },
5432	{ cpumMsrRd_AmdFam15hCombUnitCfg },
5433	{ cpumMsrRd_AmdFam15hCombUnitCfg2 },
5434	{ cpumMsrRd_AmdFam15hCombUnitCfg3 },
5435	{ cpumMsrRd_AmdFam15hExecUnitCfg },
5436	{ cpumMsrRd_AmdFam15hLoadStoreCfg2 },
5437	{ cpumMsrRd_AmdFam10hIbsFetchCtl },
5438	{ cpumMsrRd_AmdFam10hIbsFetchLinAddr },
5439	{ cpumMsrRd_AmdFam10hIbsFetchPhysAddr },
5440	{ cpumMsrRd_AmdFam10hIbsOpExecCtl },
5441	{ cpumMsrRd_AmdFam10hIbsOpRip },
5442	{ cpumMsrRd_AmdFam10hIbsOpData },
5443	{ cpumMsrRd_AmdFam10hIbsOpData2 },
5444	{ cpumMsrRd_AmdFam10hIbsOpData3 },
5445	{ cpumMsrRd_AmdFam10hIbsDcLinAddr },
5446	{ cpumMsrRd_AmdFam10hIbsDcPhysAddr },
5447	{ cpumMsrRd_AmdFam10hIbsCtl },
5448	{ cpumMsrRd_AmdFam14hIbsBrTarget },
5449
5450	{ cpumMsrRd_Gim },
5451	};
5452
5453
5454	/**
5455	* MSR write function table.
5456	*/
5457	static const struct WRITEMSRCLANG11WEIRDNOTHROW { PFNCPUMWRMSR pfnWrMsr; } g_aCpumWrMsrFns[kCpumMsrWrFn_End] =
5458	{
5459	{ NULL }, /* Invalid */
5460	{ cpumMsrWr_IgnoreWrite },
5461	{ cpumMsrWr_ReadOnly },
5462	{ NULL }, /* Alias */
5463	{ cpumMsrWr_Ia32P5McAddr },
5464	{ cpumMsrWr_Ia32P5McType },
5465	{ cpumMsrWr_Ia32TimestampCounter },
5466	{ cpumMsrWr_Ia32ApicBase },
5467	{ cpumMsrWr_Ia32FeatureControl },
5468	{ cpumMsrWr_Ia32BiosSignId },
5469	{ cpumMsrWr_Ia32BiosUpdateTrigger },
5470	{ cpumMsrWr_Ia32SmmMonitorCtl },
5471	{ cpumMsrWr_Ia32PmcN },
5472	{ cpumMsrWr_Ia32MonitorFilterLineSize },
5473	{ cpumMsrWr_Ia32MPerf },
5474	{ cpumMsrWr_Ia32APerf },
5475	{ cpumMsrWr_Ia32MtrrPhysBaseN },
5476	{ cpumMsrWr_Ia32MtrrPhysMaskN },
5477	{ cpumMsrWr_Ia32MtrrFixed },
5478	{ cpumMsrWr_Ia32MtrrDefType },
5479	{ cpumMsrWr_Ia32Pat },
5480	{ cpumMsrWr_Ia32SysEnterCs },
5481	{ cpumMsrWr_Ia32SysEnterEsp },
5482	{ cpumMsrWr_Ia32SysEnterEip },
5483	{ cpumMsrWr_Ia32McgStatus },
5484	{ cpumMsrWr_Ia32McgCtl },
5485	{ cpumMsrWr_Ia32DebugCtl },
5486	{ cpumMsrWr_Ia32SmrrPhysBase },
5487	{ cpumMsrWr_Ia32SmrrPhysMask },
5488	{ cpumMsrWr_Ia32PlatformDcaCap },
5489	{ cpumMsrWr_Ia32Dca0Cap },
5490	{ cpumMsrWr_Ia32PerfEvtSelN },
5491	{ cpumMsrWr_Ia32PerfStatus },
5492	{ cpumMsrWr_Ia32PerfCtl },
5493	{ cpumMsrWr_Ia32FixedCtrN },
5494	{ cpumMsrWr_Ia32PerfCapabilities },
5495	{ cpumMsrWr_Ia32FixedCtrCtrl },
5496	{ cpumMsrWr_Ia32PerfGlobalStatus },
5497	{ cpumMsrWr_Ia32PerfGlobalCtrl },
5498	{ cpumMsrWr_Ia32PerfGlobalOvfCtrl },
5499	{ cpumMsrWr_Ia32PebsEnable },
5500	{ cpumMsrWr_Ia32ClockModulation },
5501	{ cpumMsrWr_Ia32ThermInterrupt },
5502	{ cpumMsrWr_Ia32ThermStatus },
5503	{ cpumMsrWr_Ia32Therm2Ctl },
5504	{ cpumMsrWr_Ia32MiscEnable },
5505	{ cpumMsrWr_Ia32McCtlStatusAddrMiscN },
5506	{ cpumMsrWr_Ia32McNCtl2 },
5507	{ cpumMsrWr_Ia32DsArea },
5508	{ cpumMsrWr_Ia32TscDeadline },
5509	{ cpumMsrWr_Ia32X2ApicN },
5510	{ cpumMsrWr_Ia32DebugInterface },
5511	{ cpumMsrWr_Ia32SpecCtrl },
5512	{ cpumMsrWr_Ia32PredCmd },
5513	{ cpumMsrWr_Ia32FlushCmd },
5514
5515	{ cpumMsrWr_Amd64Efer },
5516	{ cpumMsrWr_Amd64SyscallTarget },
5517	{ cpumMsrWr_Amd64LongSyscallTarget },
5518	{ cpumMsrWr_Amd64CompSyscallTarget },
5519	{ cpumMsrWr_Amd64SyscallFlagMask },
5520	{ cpumMsrWr_Amd64FsBase },
5521	{ cpumMsrWr_Amd64GsBase },
5522	{ cpumMsrWr_Amd64KernelGsBase },
5523	{ cpumMsrWr_Amd64TscAux },
5524
5525	{ cpumMsrWr_IntelEblCrPowerOn },
5526	{ cpumMsrWr_IntelP4EbcHardPowerOn },
5527	{ cpumMsrWr_IntelP4EbcSoftPowerOn },
5528	{ cpumMsrWr_IntelP4EbcFrequencyId },
5529	{ cpumMsrWr_IntelFlexRatio },
5530	{ cpumMsrWr_IntelPkgCStConfigControl },
5531	{ cpumMsrWr_IntelPmgIoCaptureBase },
5532	{ cpumMsrWr_IntelLastBranchFromToN },
5533	{ cpumMsrWr_IntelLastBranchFromN },
5534	{ cpumMsrWr_IntelLastBranchToN },
5535	{ cpumMsrWr_IntelLastBranchTos },
5536	{ cpumMsrWr_IntelBblCrCtl },
5537	{ cpumMsrWr_IntelBblCrCtl3 },
5538	{ cpumMsrWr_IntelI7TemperatureTarget },
5539	{ cpumMsrWr_IntelI7MsrOffCoreResponseN },
5540	{ cpumMsrWr_IntelI7MiscPwrMgmt },
5541	{ cpumMsrWr_IntelP6CrN },
5542	{ cpumMsrWr_IntelCpuId1FeatureMaskEcdx },
5543	{ cpumMsrWr_IntelCpuId1FeatureMaskEax },
5544	{ cpumMsrWr_IntelCpuId80000001FeatureMaskEcdx },
5545	{ cpumMsrWr_IntelI7SandyAesNiCtl },
5546	{ cpumMsrWr_IntelI7TurboRatioLimit },
5547	{ cpumMsrWr_IntelI7LbrSelect },
5548	{ cpumMsrWr_IntelI7SandyErrorControl },
5549	{ cpumMsrWr_IntelI7PowerCtl },
5550	{ cpumMsrWr_IntelI7SandyPebsNumAlt },
5551	{ cpumMsrWr_IntelI7PebsLdLat },
5552	{ cpumMsrWr_IntelI7SandyVrCurrentConfig },
5553	{ cpumMsrWr_IntelI7SandyVrMiscConfig },
5554	{ cpumMsrWr_IntelI7SandyRaplPowerUnit },
5555	{ cpumMsrWr_IntelI7SandyPkgCnIrtlN },
5556	{ cpumMsrWr_IntelI7SandyPkgC2Residency },
5557	{ cpumMsrWr_IntelI7RaplPkgPowerLimit },
5558	{ cpumMsrWr_IntelI7RaplDramPowerLimit },
5559	{ cpumMsrWr_IntelI7RaplPp0PowerLimit },
5560	{ cpumMsrWr_IntelI7RaplPp0Policy },
5561	{ cpumMsrWr_IntelI7RaplPp1PowerLimit },
5562	{ cpumMsrWr_IntelI7RaplPp1Policy },
5563	{ cpumMsrWr_IntelI7IvyConfigTdpControl },
5564	{ cpumMsrWr_IntelI7IvyTurboActivationRatio },
5565	{ cpumMsrWr_IntelI7UncPerfGlobalCtrl },
5566	{ cpumMsrWr_IntelI7UncPerfGlobalStatus },
5567	{ cpumMsrWr_IntelI7UncPerfGlobalOvfCtrl },
5568	{ cpumMsrWr_IntelI7UncPerfFixedCtrCtrl },
5569	{ cpumMsrWr_IntelI7UncPerfFixedCtr },
5570	{ cpumMsrWr_IntelI7UncArbPerfCtrN },
5571	{ cpumMsrWr_IntelI7UncArbPerfEvtSelN },
5572	{ cpumMsrWr_IntelCore2EmttmCrTablesN },
5573	{ cpumMsrWr_IntelCore2SmmCStMiscInfo },
5574	{ cpumMsrWr_IntelCore1ExtConfig },
5575	{ cpumMsrWr_IntelCore1DtsCalControl },
5576	{ cpumMsrWr_IntelCore2PeciControl },
5577
5578	{ cpumMsrWr_P6LastIntFromIp },
5579	{ cpumMsrWr_P6LastIntToIp },
5580
5581	{ cpumMsrWr_AmdFam15hTscRate },
5582	{ cpumMsrWr_AmdFam15hLwpCfg },
5583	{ cpumMsrWr_AmdFam15hLwpCbAddr },
5584	{ cpumMsrWr_AmdFam10hMc4MiscN },
5585	{ cpumMsrWr_AmdK8PerfCtlN },
5586	{ cpumMsrWr_AmdK8PerfCtrN },
5587	{ cpumMsrWr_AmdK8SysCfg },
5588	{ cpumMsrWr_AmdK8HwCr },
5589	{ cpumMsrWr_AmdK8IorrBaseN },
5590	{ cpumMsrWr_AmdK8IorrMaskN },
5591	{ cpumMsrWr_AmdK8TopOfMemN },
5592	{ cpumMsrWr_AmdK8NbCfg1 },
5593	{ cpumMsrWr_AmdK8McXcptRedir },
5594	{ cpumMsrWr_AmdK8CpuNameN },
5595	{ cpumMsrWr_AmdK8HwThermalCtrl },
5596	{ cpumMsrWr_AmdK8SwThermalCtrl },
5597	{ cpumMsrWr_AmdK8FidVidControl },
5598	{ cpumMsrWr_AmdK8McCtlMaskN },
5599	{ cpumMsrWr_AmdK8SmiOnIoTrapN },
5600	{ cpumMsrWr_AmdK8SmiOnIoTrapCtlSts },
5601	{ cpumMsrWr_AmdK8IntPendingMessage },
5602	{ cpumMsrWr_AmdK8SmiTriggerIoCycle },
5603	{ cpumMsrWr_AmdFam10hMmioCfgBaseAddr },
5604	{ cpumMsrWr_AmdFam10hTrapCtlMaybe },
5605	{ cpumMsrWr_AmdFam10hPStateControl },
5606	{ cpumMsrWr_AmdFam10hPStateStatus },
5607	{ cpumMsrWr_AmdFam10hPStateN },
5608	{ cpumMsrWr_AmdFam10hCofVidControl },
5609	{ cpumMsrWr_AmdFam10hCofVidStatus },
5610	{ cpumMsrWr_AmdFam10hCStateIoBaseAddr },
5611	{ cpumMsrWr_AmdFam10hCpuWatchdogTimer },
5612	{ cpumMsrWr_AmdK8SmmBase },
5613	{ cpumMsrWr_AmdK8SmmAddr },
5614	{ cpumMsrWr_AmdK8SmmMask },
5615	{ cpumMsrWr_AmdK8VmCr },
5616	{ cpumMsrWr_AmdK8IgnNe },
5617	{ cpumMsrWr_AmdK8SmmCtl },
5618	{ cpumMsrWr_AmdK8VmHSavePa },
5619	{ cpumMsrWr_AmdFam10hVmLockKey },
5620	{ cpumMsrWr_AmdFam10hSmmLockKey },
5621	{ cpumMsrWr_AmdFam10hLocalSmiStatus },
5622	{ cpumMsrWr_AmdFam10hOsVisWrkIdLength },
5623	{ cpumMsrWr_AmdFam10hOsVisWrkStatus },
5624	{ cpumMsrWr_AmdFam16hL2IPerfCtlN },
5625	{ cpumMsrWr_AmdFam16hL2IPerfCtrN },
5626	{ cpumMsrWr_AmdFam15hNorthbridgePerfCtlN },
5627	{ cpumMsrWr_AmdFam15hNorthbridgePerfCtrN },
5628	{ cpumMsrWr_AmdK7MicrocodeCtl },
5629	{ cpumMsrWr_AmdK7ClusterIdMaybe },
5630	{ cpumMsrWr_AmdK8CpuIdCtlStd07hEbax },
5631	{ cpumMsrWr_AmdK8CpuIdCtlStd06hEcx },
5632	{ cpumMsrWr_AmdK8CpuIdCtlStd01hEdcx },
5633	{ cpumMsrWr_AmdK8CpuIdCtlExt01hEdcx },
5634	{ cpumMsrWr_AmdK8PatchLoader },
5635	{ cpumMsrWr_AmdK7DebugStatusMaybe },
5636	{ cpumMsrWr_AmdK7BHTraceBaseMaybe },
5637	{ cpumMsrWr_AmdK7BHTracePtrMaybe },
5638	{ cpumMsrWr_AmdK7BHTraceLimitMaybe },
5639	{ cpumMsrWr_AmdK7HardwareDebugToolCfgMaybe },
5640	{ cpumMsrWr_AmdK7FastFlushCountMaybe },
5641	{ cpumMsrWr_AmdK7NodeId },
5642	{ cpumMsrWr_AmdK7DrXAddrMaskN },
5643	{ cpumMsrWr_AmdK7Dr0DataMatchMaybe },
5644	{ cpumMsrWr_AmdK7Dr0DataMaskMaybe },
5645	{ cpumMsrWr_AmdK7LoadStoreCfg },
5646	{ cpumMsrWr_AmdK7InstrCacheCfg },
5647	{ cpumMsrWr_AmdK7DataCacheCfg },
5648	{ cpumMsrWr_AmdK7BusUnitCfg },
5649	{ cpumMsrWr_AmdK7DebugCtl2Maybe },
5650	{ cpumMsrWr_AmdFam15hFpuCfg },
5651	{ cpumMsrWr_AmdFam15hDecoderCfg },
5652	{ cpumMsrWr_AmdFam10hBusUnitCfg2 },
5653	{ cpumMsrWr_AmdFam15hCombUnitCfg },
5654	{ cpumMsrWr_AmdFam15hCombUnitCfg2 },
5655	{ cpumMsrWr_AmdFam15hCombUnitCfg3 },
5656	{ cpumMsrWr_AmdFam15hExecUnitCfg },
5657	{ cpumMsrWr_AmdFam15hLoadStoreCfg2 },
5658	{ cpumMsrWr_AmdFam10hIbsFetchCtl },
5659	{ cpumMsrWr_AmdFam10hIbsFetchLinAddr },
5660	{ cpumMsrWr_AmdFam10hIbsFetchPhysAddr },
5661	{ cpumMsrWr_AmdFam10hIbsOpExecCtl },
5662	{ cpumMsrWr_AmdFam10hIbsOpRip },
5663	{ cpumMsrWr_AmdFam10hIbsOpData },
5664	{ cpumMsrWr_AmdFam10hIbsOpData2 },
5665	{ cpumMsrWr_AmdFam10hIbsOpData3 },
5666	{ cpumMsrWr_AmdFam10hIbsDcLinAddr },
5667	{ cpumMsrWr_AmdFam10hIbsDcPhysAddr },
5668	{ cpumMsrWr_AmdFam10hIbsCtl },
5669	{ cpumMsrWr_AmdFam14hIbsBrTarget },
5670
5671	{ cpumMsrWr_Gim },
5672	};
5673
5674
5675	/**
5676	* Looks up the range for the given MSR.
5677	*
5678	* @returns Pointer to the range if found, NULL if not.
5679	* @param pVM The cross context VM structure.
5680	* @param idMsr The MSR to look up.
5681	*/
5682	# ifndef IN_RING3
5683	static
5684	# endif
5685	PCPUMMSRRANGE cpumLookupMsrRange(PVM pVM, uint32_t idMsr)
5686	{
5687	/*
5688	* Binary lookup.
5689	*/
5690	uint32_t cRanges = RT_MIN(pVM->cpum.s.GuestInfo.cMsrRanges, RT_ELEMENTS(pVM->cpum.s.GuestInfo.aMsrRanges));
5691	if (!cRanges)
5692	return NULL;
5693	# ifdef IN_RING3 /* Must use paMsrRangesR3 for it to work during early init (fudging). */
5694	PCPUMMSRRANGE paRanges = pVM->cpum.s.GuestInfo.paMsrRangesR3;
5695	# else
5696	PCPUMMSRRANGE paRanges = pVM->cpum.s.GuestInfo.aMsrRanges;
5697	# endif
5698	for (;;)
5699	{
5700	uint32_t i = cRanges / 2;
5701	if (idMsr < paRanges[i].uFirst)
5702	{
5703	if (i == 0)
5704	break;
5705	cRanges = i;
5706	}
5707	else if (idMsr > paRanges[i].uLast)
5708	{
5709	i++;
5710	if (i >= cRanges)
5711	break;
5712	cRanges -= i;
5713	paRanges = &paRanges[i];
5714	}
5715	else
5716	{
5717	if (paRanges[i].enmRdFn == kCpumMsrRdFn_MsrAlias)
5718	return cpumLookupMsrRange(pVM, paRanges[i].uValue);
5719	return &paRanges[i];
5720	}
5721	}
5722
5723	# ifdef VBOX_STRICT
5724	/*
5725	* Linear lookup to verify the above binary search.
5726	*/
5727	uint32_t cLeft = RT_MIN(pVM->cpum.s.GuestInfo.cMsrRanges, RT_ELEMENTS(pVM->cpum.s.GuestInfo.aMsrRanges));
5728	PCPUMMSRRANGE pCur = pVM->cpum.s.GuestInfo.aMsrRanges;
5729	while (cLeft-- > 0)
5730	{
5731	if (idMsr >= pCur->uFirst && idMsr <= pCur->uLast)
5732	{
5733	AssertFailed();
5734	if (pCur->enmRdFn == kCpumMsrRdFn_MsrAlias)
5735	return cpumLookupMsrRange(pVM, pCur->uValue);
5736	return pCur;
5737	}
5738	pCur++;
5739	}
5740	# endif
5741	return NULL;
5742	}
5743
5744
5745	/**
5746	* Query a guest MSR.
5747	*
5748	* The caller is responsible for checking privilege if the call is the result of
5749	* a RDMSR instruction. We'll do the rest.
5750	*
5751	* @retval VINF_SUCCESS on success.
5752	* @retval VINF_CPUM_R3_MSR_READ if the MSR read could not be serviced in the
5753	* current context (raw-mode or ring-0).
5754	* @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR), the caller is
5755	* expected to take the appropriate actions. @a *puValue is set to 0.
5756	* @param pVCpu The cross context virtual CPU structure.
5757	* @param idMsr The MSR.
5758	* @param puValue Where to return the value.
5759	*
5760	* @remarks This will always return the right values, even when we're in the
5761	* recompiler.
5762	*/
5763	VMMDECL(VBOXSTRICTRC) CPUMQueryGuestMsr(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *puValue)
5764	{
5765	*puValue = 0;
5766
5767	VBOXSTRICTRC rcStrict;
5768	PVM pVM = pVCpu->CTX_SUFF(pVM);
5769	PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, idMsr);
5770	if (pRange)
5771	{
5772	CPUMMSRRDFN enmRdFn = (CPUMMSRRDFN)pRange->enmRdFn;
5773	AssertReturn(enmRdFn > kCpumMsrRdFn_Invalid && enmRdFn < kCpumMsrRdFn_End, VERR_CPUM_IPE_1);
5774
5775	PFNCPUMRDMSR pfnRdMsr = g_aCpumRdMsrFns[enmRdFn].pfnRdMsr;
5776	AssertReturn(pfnRdMsr, VERR_CPUM_IPE_2);
5777
5778	STAM_COUNTER_INC(&pRange->cReads);
5779	STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReads);
5780
5781	rcStrict = pfnRdMsr(pVCpu, idMsr, pRange, puValue);
5782	if (rcStrict == VINF_SUCCESS)
5783	Log2(("CPUM: RDMSR %#x (%s) -> %#llx\n", idMsr, pRange->szName, *puValue));
5784	else if (rcStrict == VERR_CPUM_RAISE_GP_0)
5785	{
5786	Log(("CPUM: RDMSR %#x (%s) -> #GP(0)\n", idMsr, pRange->szName));
5787	STAM_COUNTER_INC(&pRange->cGps);
5788	STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReadsRaiseGp);
5789	}
5790	#ifndef IN_RING3
5791	else if (rcStrict == VINF_CPUM_R3_MSR_READ)
5792	Log(("CPUM: RDMSR %#x (%s) -> ring-3\n", idMsr, pRange->szName));
5793	#endif
5794	else
5795	{
5796	Log(("CPUM: RDMSR %#x (%s) -> rcStrict=%Rrc\n", idMsr, pRange->szName, VBOXSTRICTRC_VAL(rcStrict)));
5797	AssertMsgStmt(RT_FAILURE_NP(rcStrict), ("%Rrc idMsr=%#x\n", VBOXSTRICTRC_VAL(rcStrict), idMsr),
5798	rcStrict = VERR_IPE_UNEXPECTED_INFO_STATUS);
5799	Assert(rcStrict != VERR_EM_INTERPRETER);
5800	}
5801	}
5802	else
5803	{
5804	Log(("CPUM: Unknown RDMSR %#x -> #GP(0)\n", idMsr));
5805	STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReads);
5806	STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReadsUnknown);
5807	rcStrict = VERR_CPUM_RAISE_GP_0;
5808	}
5809	return rcStrict;
5810	}
5811
5812
5813	/**
5814	* Writes to a guest MSR.
5815	*
5816	* The caller is responsible for checking privilege if the call is the result of
5817	* a WRMSR instruction. We'll do the rest.
5818	*
5819	* @retval VINF_SUCCESS on success.
5820	* @retval VINF_CPUM_R3_MSR_WRITE if the MSR write could not be serviced in the
5821	* current context (raw-mode or ring-0).
5822	* @retval VERR_CPUM_RAISE_GP_0 on failure, the caller is expected to take the
5823	* appropriate actions.
5824	*
5825	* @param pVCpu The cross context virtual CPU structure.
5826	* @param idMsr The MSR id.
5827	* @param uValue The value to set.
5828	*
5829	* @remarks Everyone changing MSR values, including the recompiler, shall do it
5830	* by calling this method. This makes sure we have current values and
5831	* that we trigger all the right actions when something changes.
5832	*
5833	* For performance reasons, this actually isn't entirely true for some
5834	* MSRs when in HM mode. The code here and in HM must be aware of
5835	* this.
5836	*/
5837	VMMDECL(VBOXSTRICTRC) CPUMSetGuestMsr(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t uValue)
5838	{
5839	VBOXSTRICTRC rcStrict;
5840	PVM pVM = pVCpu->CTX_SUFF(pVM);
5841	PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, idMsr);
5842	if (pRange)
5843	{
5844	STAM_COUNTER_INC(&pRange->cWrites);
5845	STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWrites);
5846
5847	if (!(uValue & pRange->fWrGpMask))
5848	{
5849	CPUMMSRWRFN enmWrFn = (CPUMMSRWRFN)pRange->enmWrFn;
5850	AssertReturn(enmWrFn > kCpumMsrWrFn_Invalid && enmWrFn < kCpumMsrWrFn_End, VERR_CPUM_IPE_1);
5851
5852	PFNCPUMWRMSR pfnWrMsr = g_aCpumWrMsrFns[enmWrFn].pfnWrMsr;
5853	AssertReturn(pfnWrMsr, VERR_CPUM_IPE_2);
5854
5855	uint64_t uValueAdjusted = uValue & ~pRange->fWrIgnMask;
5856	if (uValueAdjusted != uValue)
5857	{
5858	STAM_COUNTER_INC(&pRange->cIgnoredBits);
5859	STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesToIgnoredBits);
5860	}
5861
5862	rcStrict = pfnWrMsr(pVCpu, idMsr, pRange, uValueAdjusted, uValue);
5863	if (rcStrict == VINF_SUCCESS)
5864	Log2(("CPUM: WRMSR %#x (%s), %#llx [%#llx]\n", idMsr, pRange->szName, uValueAdjusted, uValue));
5865	else if (rcStrict == VERR_CPUM_RAISE_GP_0)
5866	{
5867	Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> #GP(0)\n", idMsr, pRange->szName, uValueAdjusted, uValue));
5868	STAM_COUNTER_INC(&pRange->cGps);
5869	STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesRaiseGp);
5870	}
5871	#ifndef IN_RING3
5872	else if (rcStrict == VINF_CPUM_R3_MSR_WRITE)
5873	Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> ring-3\n", idMsr, pRange->szName, uValueAdjusted, uValue));
5874	#endif
5875	else
5876	{
5877	Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> rcStrict=%Rrc\n",
5878	idMsr, pRange->szName, uValueAdjusted, uValue, VBOXSTRICTRC_VAL(rcStrict)));
5879	AssertMsgStmt(RT_FAILURE_NP(rcStrict), ("%Rrc idMsr=%#x\n", VBOXSTRICTRC_VAL(rcStrict), idMsr),
5880	rcStrict = VERR_IPE_UNEXPECTED_INFO_STATUS);
5881	Assert(rcStrict != VERR_EM_INTERPRETER);
5882	}
5883	}
5884	else
5885	{
5886	Log(("CPUM: WRMSR %#x (%s), %#llx -> #GP(0) - invalid bits %#llx\n",
5887	idMsr, pRange->szName, uValue, uValue & pRange->fWrGpMask));
5888	STAM_COUNTER_INC(&pRange->cGps);
5889	STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesRaiseGp);
5890	rcStrict = VERR_CPUM_RAISE_GP_0;
5891	}
5892	}
5893	else
5894	{
5895	Log(("CPUM: Unknown WRMSR %#x, %#llx -> #GP(0)\n", idMsr, uValue));
5896	STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWrites);
5897	STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesUnknown);
5898	rcStrict = VERR_CPUM_RAISE_GP_0;
5899	}
5900	return rcStrict;
5901	}
5902
5903
5904	#if defined(VBOX_STRICT) && defined(IN_RING3)
5905	/**
5906	* Performs some checks on the static data related to MSRs.
5907	*
5908	* @returns VINF_SUCCESS on success, error on failure.
5909	*/
5910	int cpumR3MsrStrictInitChecks(void)
5911	{
5912	#define CPUM_ASSERT_RD_MSR_FN(a_Register) \
5913	AssertReturn(g_aCpumRdMsrFns[kCpumMsrRdFn_##a_Register].pfnRdMsr == cpumMsrRd_##a_Register, VERR_CPUM_IPE_2);
5914	#define CPUM_ASSERT_WR_MSR_FN(a_Register) \
5915	AssertReturn(g_aCpumWrMsrFns[kCpumMsrWrFn_##a_Register].pfnWrMsr == cpumMsrWr_##a_Register, VERR_CPUM_IPE_2);
5916
5917	AssertReturn(g_aCpumRdMsrFns[kCpumMsrRdFn_Invalid].pfnRdMsr == NULL, VERR_CPUM_IPE_2);
5918	CPUM_ASSERT_RD_MSR_FN(FixedValue);
5919	CPUM_ASSERT_RD_MSR_FN(WriteOnly);
5920	CPUM_ASSERT_RD_MSR_FN(Ia32P5McAddr);
5921	CPUM_ASSERT_RD_MSR_FN(Ia32P5McType);
5922	CPUM_ASSERT_RD_MSR_FN(Ia32TimestampCounter);
5923	CPUM_ASSERT_RD_MSR_FN(Ia32PlatformId);
5924	CPUM_ASSERT_RD_MSR_FN(Ia32ApicBase);
5925	CPUM_ASSERT_RD_MSR_FN(Ia32FeatureControl);
5926	CPUM_ASSERT_RD_MSR_FN(Ia32BiosSignId);
5927	CPUM_ASSERT_RD_MSR_FN(Ia32SmmMonitorCtl);
5928	CPUM_ASSERT_RD_MSR_FN(Ia32PmcN);
5929	CPUM_ASSERT_RD_MSR_FN(Ia32MonitorFilterLineSize);
5930	CPUM_ASSERT_RD_MSR_FN(Ia32MPerf);
5931	CPUM_ASSERT_RD_MSR_FN(Ia32APerf);
5932	CPUM_ASSERT_RD_MSR_FN(Ia32MtrrCap);
5933	CPUM_ASSERT_RD_MSR_FN(Ia32MtrrPhysBaseN);
5934	CPUM_ASSERT_RD_MSR_FN(Ia32MtrrPhysMaskN);
5935	CPUM_ASSERT_RD_MSR_FN(Ia32MtrrFixed);
5936	CPUM_ASSERT_RD_MSR_FN(Ia32MtrrDefType);
5937	CPUM_ASSERT_RD_MSR_FN(Ia32Pat);
5938	CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterCs);
5939	CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterEsp);
5940	CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterEip);
5941	CPUM_ASSERT_RD_MSR_FN(Ia32McgCap);
5942	CPUM_ASSERT_RD_MSR_FN(Ia32McgStatus);
5943	CPUM_ASSERT_RD_MSR_FN(Ia32McgCtl);
5944	CPUM_ASSERT_RD_MSR_FN(Ia32DebugCtl);
5945	CPUM_ASSERT_RD_MSR_FN(Ia32SmrrPhysBase);
5946	CPUM_ASSERT_RD_MSR_FN(Ia32SmrrPhysMask);
5947	CPUM_ASSERT_RD_MSR_FN(Ia32PlatformDcaCap);
5948	CPUM_ASSERT_RD_MSR_FN(Ia32CpuDcaCap);
5949	CPUM_ASSERT_RD_MSR_FN(Ia32Dca0Cap);
5950	CPUM_ASSERT_RD_MSR_FN(Ia32PerfEvtSelN);
5951	CPUM_ASSERT_RD_MSR_FN(Ia32PerfStatus);
5952	CPUM_ASSERT_RD_MSR_FN(Ia32PerfCtl);
5953	CPUM_ASSERT_RD_MSR_FN(Ia32FixedCtrN);
5954	CPUM_ASSERT_RD_MSR_FN(Ia32PerfCapabilities);
5955	CPUM_ASSERT_RD_MSR_FN(Ia32FixedCtrCtrl);
5956	CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalStatus);
5957	CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalCtrl);
5958	CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalOvfCtrl);
5959	CPUM_ASSERT_RD_MSR_FN(Ia32PebsEnable);
5960	CPUM_ASSERT_RD_MSR_FN(Ia32ClockModulation);
5961	CPUM_ASSERT_RD_MSR_FN(Ia32ThermInterrupt);
5962	CPUM_ASSERT_RD_MSR_FN(Ia32ThermStatus);
5963	CPUM_ASSERT_RD_MSR_FN(Ia32MiscEnable);
5964	CPUM_ASSERT_RD_MSR_FN(Ia32McCtlStatusAddrMiscN);
5965	CPUM_ASSERT_RD_MSR_FN(Ia32McNCtl2);
5966	CPUM_ASSERT_RD_MSR_FN(Ia32DsArea);
5967	CPUM_ASSERT_RD_MSR_FN(Ia32TscDeadline);
5968	CPUM_ASSERT_RD_MSR_FN(Ia32X2ApicN);
5969	CPUM_ASSERT_RD_MSR_FN(Ia32DebugInterface);
5970	CPUM_ASSERT_RD_MSR_FN(Ia32VmxBasic);
5971	CPUM_ASSERT_RD_MSR_FN(Ia32VmxPinbasedCtls);
5972	CPUM_ASSERT_RD_MSR_FN(Ia32VmxProcbasedCtls);
5973	CPUM_ASSERT_RD_MSR_FN(Ia32VmxExitCtls);
5974	CPUM_ASSERT_RD_MSR_FN(Ia32VmxEntryCtls);
5975	CPUM_ASSERT_RD_MSR_FN(Ia32VmxMisc);
5976	CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr0Fixed0);
5977	CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr0Fixed1);
5978	CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr4Fixed0);
5979	CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr4Fixed1);
5980	CPUM_ASSERT_RD_MSR_FN(Ia32VmxVmcsEnum);
5981	CPUM_ASSERT_RD_MSR_FN(Ia32VmxProcBasedCtls2);
5982	CPUM_ASSERT_RD_MSR_FN(Ia32VmxEptVpidCap);
5983	CPUM_ASSERT_RD_MSR_FN(Ia32VmxTruePinbasedCtls);
5984	CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueProcbasedCtls);
5985	CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueExitCtls);
5986	CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueEntryCtls);
5987	CPUM_ASSERT_RD_MSR_FN(Ia32VmxVmFunc);
5988	CPUM_ASSERT_RD_MSR_FN(Ia32SpecCtrl);
5989	CPUM_ASSERT_RD_MSR_FN(Ia32ArchCapabilities);
5990
5991	CPUM_ASSERT_RD_MSR_FN(Amd64Efer);
5992	CPUM_ASSERT_RD_MSR_FN(Amd64SyscallTarget);
5993	CPUM_ASSERT_RD_MSR_FN(Amd64LongSyscallTarget);
5994	CPUM_ASSERT_RD_MSR_FN(Amd64CompSyscallTarget);
5995	CPUM_ASSERT_RD_MSR_FN(Amd64SyscallFlagMask);
5996	CPUM_ASSERT_RD_MSR_FN(Amd64FsBase);
5997	CPUM_ASSERT_RD_MSR_FN(Amd64GsBase);
5998	CPUM_ASSERT_RD_MSR_FN(Amd64KernelGsBase);
5999	CPUM_ASSERT_RD_MSR_FN(Amd64TscAux);
6000
6001	CPUM_ASSERT_RD_MSR_FN(IntelEblCrPowerOn);
6002	CPUM_ASSERT_RD_MSR_FN(IntelI7CoreThreadCount);
6003	CPUM_ASSERT_RD_MSR_FN(IntelP4EbcHardPowerOn);
6004	CPUM_ASSERT_RD_MSR_FN(IntelP4EbcSoftPowerOn);
6005	CPUM_ASSERT_RD_MSR_FN(IntelP4EbcFrequencyId);
6006	CPUM_ASSERT_RD_MSR_FN(IntelP6FsbFrequency);
6007	CPUM_ASSERT_RD_MSR_FN(IntelPlatformInfo);
6008	CPUM_ASSERT_RD_MSR_FN(IntelFlexRatio);
6009	CPUM_ASSERT_RD_MSR_FN(IntelPkgCStConfigControl);
6010	CPUM_ASSERT_RD_MSR_FN(IntelPmgIoCaptureBase);
6011	CPUM_ASSERT_RD_MSR_FN(IntelLastBranchFromToN);
6012	CPUM_ASSERT_RD_MSR_FN(IntelLastBranchFromN);
6013	CPUM_ASSERT_RD_MSR_FN(IntelLastBranchToN);
6014	CPUM_ASSERT_RD_MSR_FN(IntelLastBranchTos);
6015	CPUM_ASSERT_RD_MSR_FN(IntelBblCrCtl);
6016	CPUM_ASSERT_RD_MSR_FN(IntelBblCrCtl3);
6017	CPUM_ASSERT_RD_MSR_FN(IntelI7TemperatureTarget);
6018	CPUM_ASSERT_RD_MSR_FN(IntelI7MsrOffCoreResponseN);
6019	CPUM_ASSERT_RD_MSR_FN(IntelI7MiscPwrMgmt);
6020	CPUM_ASSERT_RD_MSR_FN(IntelP6CrN);
6021	CPUM_ASSERT_RD_MSR_FN(IntelCpuId1FeatureMaskEcdx);
6022	CPUM_ASSERT_RD_MSR_FN(IntelCpuId1FeatureMaskEax);
6023	CPUM_ASSERT_RD_MSR_FN(IntelCpuId80000001FeatureMaskEcdx);
6024	CPUM_ASSERT_RD_MSR_FN(IntelI7SandyAesNiCtl);
6025	CPUM_ASSERT_RD_MSR_FN(IntelI7TurboRatioLimit);
6026	CPUM_ASSERT_RD_MSR_FN(IntelI7LbrSelect);
6027	CPUM_ASSERT_RD_MSR_FN(IntelI7SandyErrorControl);
6028	CPUM_ASSERT_RD_MSR_FN(IntelI7VirtualLegacyWireCap);
6029	CPUM_ASSERT_RD_MSR_FN(IntelI7PowerCtl);
6030	CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPebsNumAlt);
6031	CPUM_ASSERT_RD_MSR_FN(IntelI7PebsLdLat);
6032	CPUM_ASSERT_RD_MSR_FN(IntelI7PkgCnResidencyN);
6033	CPUM_ASSERT_RD_MSR_FN(IntelI7CoreCnResidencyN);
6034	CPUM_ASSERT_RD_MSR_FN(IntelI7SandyVrCurrentConfig);
6035	CPUM_ASSERT_RD_MSR_FN(IntelI7SandyVrMiscConfig);
6036	CPUM_ASSERT_RD_MSR_FN(IntelI7SandyRaplPowerUnit);
6037	CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPkgCnIrtlN);
6038	CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPkgC2Residency);
6039	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPowerLimit);
6040	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgEnergyStatus);
6041	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPerfStatus);
6042	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPowerInfo);
6043	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPowerLimit);
6044	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramEnergyStatus);
6045	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPerfStatus);
6046	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPowerInfo);
6047	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0PowerLimit);
6048	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0EnergyStatus);
6049	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0Policy);
6050	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0PerfStatus);
6051	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1PowerLimit);
6052	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1EnergyStatus);
6053	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1Policy);
6054	CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpNominal);
6055	CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpLevel1);
6056	CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpLevel2);
6057	CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpControl);
6058	CPUM_ASSERT_RD_MSR_FN(IntelI7IvyTurboActivationRatio);
6059	CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalCtrl);
6060	CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalStatus);
6061	CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalOvfCtrl);
6062	CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfFixedCtrCtrl);
6063	CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfFixedCtr);
6064	CPUM_ASSERT_RD_MSR_FN(IntelI7UncCBoxConfig);
6065	CPUM_ASSERT_RD_MSR_FN(IntelI7UncArbPerfCtrN);
6066	CPUM_ASSERT_RD_MSR_FN(IntelI7UncArbPerfEvtSelN);
6067	CPUM_ASSERT_RD_MSR_FN(IntelI7SmiCount);
6068	CPUM_ASSERT_RD_MSR_FN(IntelCore2EmttmCrTablesN);
6069	CPUM_ASSERT_RD_MSR_FN(IntelCore2SmmCStMiscInfo);
6070	CPUM_ASSERT_RD_MSR_FN(IntelCore1ExtConfig);
6071	CPUM_ASSERT_RD_MSR_FN(IntelCore1DtsCalControl);
6072	CPUM_ASSERT_RD_MSR_FN(IntelCore2PeciControl);
6073	CPUM_ASSERT_RD_MSR_FN(IntelAtSilvCoreC1Recidency);
6074
6075	CPUM_ASSERT_RD_MSR_FN(P6LastBranchFromIp);
6076	CPUM_ASSERT_RD_MSR_FN(P6LastBranchToIp);
6077	CPUM_ASSERT_RD_MSR_FN(P6LastIntFromIp);
6078	CPUM_ASSERT_RD_MSR_FN(P6LastIntToIp);
6079
6080	CPUM_ASSERT_RD_MSR_FN(AmdFam15hTscRate);
6081	CPUM_ASSERT_RD_MSR_FN(AmdFam15hLwpCfg);
6082	CPUM_ASSERT_RD_MSR_FN(AmdFam15hLwpCbAddr);
6083	CPUM_ASSERT_RD_MSR_FN(AmdFam10hMc4MiscN);
6084	CPUM_ASSERT_RD_MSR_FN(AmdK8PerfCtlN);
6085	CPUM_ASSERT_RD_MSR_FN(AmdK8PerfCtrN);
6086	CPUM_ASSERT_RD_MSR_FN(AmdK8SysCfg);
6087	CPUM_ASSERT_RD_MSR_FN(AmdK8HwCr);
6088	CPUM_ASSERT_RD_MSR_FN(AmdK8IorrBaseN);
6089	CPUM_ASSERT_RD_MSR_FN(AmdK8IorrMaskN);
6090	CPUM_ASSERT_RD_MSR_FN(AmdK8TopOfMemN);
6091	CPUM_ASSERT_RD_MSR_FN(AmdK8NbCfg1);
6092	CPUM_ASSERT_RD_MSR_FN(AmdK8McXcptRedir);
6093	CPUM_ASSERT_RD_MSR_FN(AmdK8CpuNameN);
6094	CPUM_ASSERT_RD_MSR_FN(AmdK8HwThermalCtrl);
6095	CPUM_ASSERT_RD_MSR_FN(AmdK8SwThermalCtrl);
6096	CPUM_ASSERT_RD_MSR_FN(AmdK8FidVidControl);
6097	CPUM_ASSERT_RD_MSR_FN(AmdK8FidVidStatus);
6098	CPUM_ASSERT_RD_MSR_FN(AmdK8McCtlMaskN);
6099	CPUM_ASSERT_RD_MSR_FN(AmdK8SmiOnIoTrapN);
6100	CPUM_ASSERT_RD_MSR_FN(AmdK8SmiOnIoTrapCtlSts);
6101	CPUM_ASSERT_RD_MSR_FN(AmdK8IntPendingMessage);
6102	CPUM_ASSERT_RD_MSR_FN(AmdK8SmiTriggerIoCycle);
6103	CPUM_ASSERT_RD_MSR_FN(AmdFam10hMmioCfgBaseAddr);
6104	CPUM_ASSERT_RD_MSR_FN(AmdFam10hTrapCtlMaybe);
6105	CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateCurLimit);
6106	CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateControl);
6107	CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateStatus);
6108	CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateN);
6109	CPUM_ASSERT_RD_MSR_FN(AmdFam10hCofVidControl);
6110	CPUM_ASSERT_RD_MSR_FN(AmdFam10hCofVidStatus);
6111	CPUM_ASSERT_RD_MSR_FN(AmdFam10hCStateIoBaseAddr);
6112	CPUM_ASSERT_RD_MSR_FN(AmdFam10hCpuWatchdogTimer);
6113	CPUM_ASSERT_RD_MSR_FN(AmdK8SmmBase);
6114	CPUM_ASSERT_RD_MSR_FN(AmdK8SmmAddr);
6115	CPUM_ASSERT_RD_MSR_FN(AmdK8SmmMask);
6116	CPUM_ASSERT_RD_MSR_FN(AmdK8VmCr);
6117	CPUM_ASSERT_RD_MSR_FN(AmdK8IgnNe);
6118	CPUM_ASSERT_RD_MSR_FN(AmdK8SmmCtl);
6119	CPUM_ASSERT_RD_MSR_FN(AmdK8VmHSavePa);
6120	CPUM_ASSERT_RD_MSR_FN(AmdFam10hVmLockKey);
6121	CPUM_ASSERT_RD_MSR_FN(AmdFam10hSmmLockKey);
6122	CPUM_ASSERT_RD_MSR_FN(AmdFam10hLocalSmiStatus);
6123	CPUM_ASSERT_RD_MSR_FN(AmdFam10hOsVisWrkIdLength);
6124	CPUM_ASSERT_RD_MSR_FN(AmdFam10hOsVisWrkStatus);
6125	CPUM_ASSERT_RD_MSR_FN(AmdFam16hL2IPerfCtlN);
6126	CPUM_ASSERT_RD_MSR_FN(AmdFam16hL2IPerfCtrN);
6127	CPUM_ASSERT_RD_MSR_FN(AmdFam15hNorthbridgePerfCtlN);
6128	CPUM_ASSERT_RD_MSR_FN(AmdFam15hNorthbridgePerfCtrN);
6129	CPUM_ASSERT_RD_MSR_FN(AmdK7MicrocodeCtl);
6130	CPUM_ASSERT_RD_MSR_FN(AmdK7ClusterIdMaybe);
6131	CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd07hEbax);
6132	CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd06hEcx);
6133	CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd01hEdcx);
6134	CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlExt01hEdcx);
6135	CPUM_ASSERT_RD_MSR_FN(AmdK8PatchLevel);
6136	CPUM_ASSERT_RD_MSR_FN(AmdK7DebugStatusMaybe);
6137	CPUM_ASSERT_RD_MSR_FN(AmdK7BHTraceBaseMaybe);
6138	CPUM_ASSERT_RD_MSR_FN(AmdK7BHTracePtrMaybe);
6139	CPUM_ASSERT_RD_MSR_FN(AmdK7BHTraceLimitMaybe);
6140	CPUM_ASSERT_RD_MSR_FN(AmdK7HardwareDebugToolCfgMaybe);
6141	CPUM_ASSERT_RD_MSR_FN(AmdK7FastFlushCountMaybe);
6142	CPUM_ASSERT_RD_MSR_FN(AmdK7NodeId);
6143	CPUM_ASSERT_RD_MSR_FN(AmdK7DrXAddrMaskN);
6144	CPUM_ASSERT_RD_MSR_FN(AmdK7Dr0DataMatchMaybe);
6145	CPUM_ASSERT_RD_MSR_FN(AmdK7Dr0DataMaskMaybe);
6146	CPUM_ASSERT_RD_MSR_FN(AmdK7LoadStoreCfg);
6147	CPUM_ASSERT_RD_MSR_FN(AmdK7InstrCacheCfg);
6148	CPUM_ASSERT_RD_MSR_FN(AmdK7DataCacheCfg);
6149	CPUM_ASSERT_RD_MSR_FN(AmdK7BusUnitCfg);
6150	CPUM_ASSERT_RD_MSR_FN(AmdK7DebugCtl2Maybe);
6151	CPUM_ASSERT_RD_MSR_FN(AmdFam15hFpuCfg);
6152	CPUM_ASSERT_RD_MSR_FN(AmdFam15hDecoderCfg);
6153	CPUM_ASSERT_RD_MSR_FN(AmdFam10hBusUnitCfg2);
6154	CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg);
6155	CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg2);
6156	CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg3);
6157	CPUM_ASSERT_RD_MSR_FN(AmdFam15hExecUnitCfg);
6158	CPUM_ASSERT_RD_MSR_FN(AmdFam15hLoadStoreCfg2);
6159	CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchCtl);
6160	CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchLinAddr);
6161	CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchPhysAddr);
6162	CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpExecCtl);
6163	CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpRip);
6164	CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData);
6165	CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData2);
6166	CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData3);
6167	CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsDcLinAddr);
6168	CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsDcPhysAddr);
6169	CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsCtl);
6170	CPUM_ASSERT_RD_MSR_FN(AmdFam14hIbsBrTarget);
6171
6172	CPUM_ASSERT_RD_MSR_FN(Gim)
6173
6174	AssertReturn(g_aCpumWrMsrFns[kCpumMsrWrFn_Invalid].pfnWrMsr == NULL, VERR_CPUM_IPE_2);
6175	CPUM_ASSERT_WR_MSR_FN(Ia32P5McAddr);
6176	CPUM_ASSERT_WR_MSR_FN(Ia32P5McType);
6177	CPUM_ASSERT_WR_MSR_FN(Ia32TimestampCounter);
6178	CPUM_ASSERT_WR_MSR_FN(Ia32ApicBase);
6179	CPUM_ASSERT_WR_MSR_FN(Ia32FeatureControl);
6180	CPUM_ASSERT_WR_MSR_FN(Ia32BiosSignId);
6181	CPUM_ASSERT_WR_MSR_FN(Ia32BiosUpdateTrigger);
6182	CPUM_ASSERT_WR_MSR_FN(Ia32SmmMonitorCtl);
6183	CPUM_ASSERT_WR_MSR_FN(Ia32PmcN);
6184	CPUM_ASSERT_WR_MSR_FN(Ia32MonitorFilterLineSize);
6185	CPUM_ASSERT_WR_MSR_FN(Ia32MPerf);
6186	CPUM_ASSERT_WR_MSR_FN(Ia32APerf);
6187	CPUM_ASSERT_WR_MSR_FN(Ia32MtrrPhysBaseN);
6188	CPUM_ASSERT_WR_MSR_FN(Ia32MtrrPhysMaskN);
6189	CPUM_ASSERT_WR_MSR_FN(Ia32MtrrFixed);
6190	CPUM_ASSERT_WR_MSR_FN(Ia32MtrrDefType);
6191	CPUM_ASSERT_WR_MSR_FN(Ia32Pat);
6192	CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterCs);
6193	CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterEsp);
6194	CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterEip);
6195	CPUM_ASSERT_WR_MSR_FN(Ia32McgStatus);
6196	CPUM_ASSERT_WR_MSR_FN(Ia32McgCtl);
6197	CPUM_ASSERT_WR_MSR_FN(Ia32DebugCtl);
6198	CPUM_ASSERT_WR_MSR_FN(Ia32SmrrPhysBase);
6199	CPUM_ASSERT_WR_MSR_FN(Ia32SmrrPhysMask);
6200	CPUM_ASSERT_WR_MSR_FN(Ia32PlatformDcaCap);
6201	CPUM_ASSERT_WR_MSR_FN(Ia32Dca0Cap);
6202	CPUM_ASSERT_WR_MSR_FN(Ia32PerfEvtSelN);
6203	CPUM_ASSERT_WR_MSR_FN(Ia32PerfStatus);
6204	CPUM_ASSERT_WR_MSR_FN(Ia32PerfCtl);
6205	CPUM_ASSERT_WR_MSR_FN(Ia32FixedCtrN);
6206	CPUM_ASSERT_WR_MSR_FN(Ia32PerfCapabilities);
6207	CPUM_ASSERT_WR_MSR_FN(Ia32FixedCtrCtrl);
6208	CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalStatus);
6209	CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalCtrl);
6210	CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalOvfCtrl);
6211	CPUM_ASSERT_WR_MSR_FN(Ia32PebsEnable);
6212	CPUM_ASSERT_WR_MSR_FN(Ia32ClockModulation);
6213	CPUM_ASSERT_WR_MSR_FN(Ia32ThermInterrupt);
6214	CPUM_ASSERT_WR_MSR_FN(Ia32ThermStatus);
6215	CPUM_ASSERT_WR_MSR_FN(Ia32MiscEnable);
6216	CPUM_ASSERT_WR_MSR_FN(Ia32McCtlStatusAddrMiscN);
6217	CPUM_ASSERT_WR_MSR_FN(Ia32McNCtl2);
6218	CPUM_ASSERT_WR_MSR_FN(Ia32DsArea);
6219	CPUM_ASSERT_WR_MSR_FN(Ia32TscDeadline);
6220	CPUM_ASSERT_WR_MSR_FN(Ia32X2ApicN);
6221	CPUM_ASSERT_WR_MSR_FN(Ia32DebugInterface);
6222	CPUM_ASSERT_WR_MSR_FN(Ia32SpecCtrl);
6223	CPUM_ASSERT_WR_MSR_FN(Ia32PredCmd);
6224	CPUM_ASSERT_WR_MSR_FN(Ia32FlushCmd);
6225
6226	CPUM_ASSERT_WR_MSR_FN(Amd64Efer);
6227	CPUM_ASSERT_WR_MSR_FN(Amd64SyscallTarget);
6228	CPUM_ASSERT_WR_MSR_FN(Amd64LongSyscallTarget);
6229	CPUM_ASSERT_WR_MSR_FN(Amd64CompSyscallTarget);
6230	CPUM_ASSERT_WR_MSR_FN(Amd64SyscallFlagMask);
6231	CPUM_ASSERT_WR_MSR_FN(Amd64FsBase);
6232	CPUM_ASSERT_WR_MSR_FN(Amd64GsBase);
6233	CPUM_ASSERT_WR_MSR_FN(Amd64KernelGsBase);
6234	CPUM_ASSERT_WR_MSR_FN(Amd64TscAux);
6235
6236	CPUM_ASSERT_WR_MSR_FN(IntelEblCrPowerOn);
6237	CPUM_ASSERT_WR_MSR_FN(IntelP4EbcHardPowerOn);
6238	CPUM_ASSERT_WR_MSR_FN(IntelP4EbcSoftPowerOn);
6239	CPUM_ASSERT_WR_MSR_FN(IntelP4EbcFrequencyId);
6240	CPUM_ASSERT_WR_MSR_FN(IntelFlexRatio);
6241	CPUM_ASSERT_WR_MSR_FN(IntelPkgCStConfigControl);
6242	CPUM_ASSERT_WR_MSR_FN(IntelPmgIoCaptureBase);
6243	CPUM_ASSERT_WR_MSR_FN(IntelLastBranchFromToN);
6244	CPUM_ASSERT_WR_MSR_FN(IntelLastBranchFromN);
6245	CPUM_ASSERT_WR_MSR_FN(IntelLastBranchToN);
6246	CPUM_ASSERT_WR_MSR_FN(IntelLastBranchTos);
6247	CPUM_ASSERT_WR_MSR_FN(IntelBblCrCtl);
6248	CPUM_ASSERT_WR_MSR_FN(IntelBblCrCtl3);
6249	CPUM_ASSERT_WR_MSR_FN(IntelI7TemperatureTarget);
6250	CPUM_ASSERT_WR_MSR_FN(IntelI7MsrOffCoreResponseN);
6251	CPUM_ASSERT_WR_MSR_FN(IntelI7MiscPwrMgmt);
6252	CPUM_ASSERT_WR_MSR_FN(IntelP6CrN);
6253	CPUM_ASSERT_WR_MSR_FN(IntelCpuId1FeatureMaskEcdx);
6254	CPUM_ASSERT_WR_MSR_FN(IntelCpuId1FeatureMaskEax);
6255	CPUM_ASSERT_WR_MSR_FN(IntelCpuId80000001FeatureMaskEcdx);
6256	CPUM_ASSERT_WR_MSR_FN(IntelI7SandyAesNiCtl);
6257	CPUM_ASSERT_WR_MSR_FN(IntelI7TurboRatioLimit);
6258	CPUM_ASSERT_WR_MSR_FN(IntelI7LbrSelect);
6259	CPUM_ASSERT_WR_MSR_FN(IntelI7SandyErrorControl);
6260	CPUM_ASSERT_WR_MSR_FN(IntelI7PowerCtl);
6261	CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPebsNumAlt);
6262	CPUM_ASSERT_WR_MSR_FN(IntelI7PebsLdLat);
6263	CPUM_ASSERT_WR_MSR_FN(IntelI7SandyVrCurrentConfig);
6264	CPUM_ASSERT_WR_MSR_FN(IntelI7SandyVrMiscConfig);
6265	CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPkgCnIrtlN);
6266	CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPkgC2Residency);
6267	CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPkgPowerLimit);
6268	CPUM_ASSERT_WR_MSR_FN(IntelI7RaplDramPowerLimit);
6269	CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp0PowerLimit);
6270	CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp0Policy);
6271	CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp1PowerLimit);
6272	CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp1Policy);
6273	CPUM_ASSERT_WR_MSR_FN(IntelI7IvyConfigTdpControl);
6274	CPUM_ASSERT_WR_MSR_FN(IntelI7IvyTurboActivationRatio);
6275	CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalCtrl);
6276	CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalStatus);
6277	CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalOvfCtrl);
6278	CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfFixedCtrCtrl);
6279	CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfFixedCtr);
6280	CPUM_ASSERT_WR_MSR_FN(IntelI7UncArbPerfCtrN);
6281	CPUM_ASSERT_WR_MSR_FN(IntelI7UncArbPerfEvtSelN);
6282	CPUM_ASSERT_WR_MSR_FN(IntelCore2EmttmCrTablesN);
6283	CPUM_ASSERT_WR_MSR_FN(IntelCore2SmmCStMiscInfo);
6284	CPUM_ASSERT_WR_MSR_FN(IntelCore1ExtConfig);
6285	CPUM_ASSERT_WR_MSR_FN(IntelCore1DtsCalControl);
6286	CPUM_ASSERT_WR_MSR_FN(IntelCore2PeciControl);
6287
6288	CPUM_ASSERT_WR_MSR_FN(P6LastIntFromIp);
6289	CPUM_ASSERT_WR_MSR_FN(P6LastIntToIp);
6290
6291	CPUM_ASSERT_WR_MSR_FN(AmdFam15hTscRate);
6292	CPUM_ASSERT_WR_MSR_FN(AmdFam15hLwpCfg);
6293	CPUM_ASSERT_WR_MSR_FN(AmdFam15hLwpCbAddr);
6294	CPUM_ASSERT_WR_MSR_FN(AmdFam10hMc4MiscN);
6295	CPUM_ASSERT_WR_MSR_FN(AmdK8PerfCtlN);
6296	CPUM_ASSERT_WR_MSR_FN(AmdK8PerfCtrN);
6297	CPUM_ASSERT_WR_MSR_FN(AmdK8SysCfg);
6298	CPUM_ASSERT_WR_MSR_FN(AmdK8HwCr);
6299	CPUM_ASSERT_WR_MSR_FN(AmdK8IorrBaseN);
6300	CPUM_ASSERT_WR_MSR_FN(AmdK8IorrMaskN);
6301	CPUM_ASSERT_WR_MSR_FN(AmdK8TopOfMemN);
6302	CPUM_ASSERT_WR_MSR_FN(AmdK8NbCfg1);
6303	CPUM_ASSERT_WR_MSR_FN(AmdK8McXcptRedir);
6304	CPUM_ASSERT_WR_MSR_FN(AmdK8CpuNameN);
6305	CPUM_ASSERT_WR_MSR_FN(AmdK8HwThermalCtrl);
6306	CPUM_ASSERT_WR_MSR_FN(AmdK8SwThermalCtrl);
6307	CPUM_ASSERT_WR_MSR_FN(AmdK8FidVidControl);
6308	CPUM_ASSERT_WR_MSR_FN(AmdK8McCtlMaskN);
6309	CPUM_ASSERT_WR_MSR_FN(AmdK8SmiOnIoTrapN);
6310	CPUM_ASSERT_WR_MSR_FN(AmdK8SmiOnIoTrapCtlSts);
6311	CPUM_ASSERT_WR_MSR_FN(AmdK8IntPendingMessage);
6312	CPUM_ASSERT_WR_MSR_FN(AmdK8SmiTriggerIoCycle);
6313	CPUM_ASSERT_WR_MSR_FN(AmdFam10hMmioCfgBaseAddr);
6314	CPUM_ASSERT_WR_MSR_FN(AmdFam10hTrapCtlMaybe);
6315	CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateControl);
6316	CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateStatus);
6317	CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateN);
6318	CPUM_ASSERT_WR_MSR_FN(AmdFam10hCofVidControl);
6319	CPUM_ASSERT_WR_MSR_FN(AmdFam10hCofVidStatus);
6320	CPUM_ASSERT_WR_MSR_FN(AmdFam10hCStateIoBaseAddr);
6321	CPUM_ASSERT_WR_MSR_FN(AmdFam10hCpuWatchdogTimer);
6322	CPUM_ASSERT_WR_MSR_FN(AmdK8SmmBase);
6323	CPUM_ASSERT_WR_MSR_FN(AmdK8SmmAddr);
6324	CPUM_ASSERT_WR_MSR_FN(AmdK8SmmMask);
6325	CPUM_ASSERT_WR_MSR_FN(AmdK8VmCr);
6326	CPUM_ASSERT_WR_MSR_FN(AmdK8IgnNe);
6327	CPUM_ASSERT_WR_MSR_FN(AmdK8SmmCtl);
6328	CPUM_ASSERT_WR_MSR_FN(AmdK8VmHSavePa);
6329	CPUM_ASSERT_WR_MSR_FN(AmdFam10hVmLockKey);
6330	CPUM_ASSERT_WR_MSR_FN(AmdFam10hSmmLockKey);
6331	CPUM_ASSERT_WR_MSR_FN(AmdFam10hLocalSmiStatus);
6332	CPUM_ASSERT_WR_MSR_FN(AmdFam10hOsVisWrkIdLength);
6333	CPUM_ASSERT_WR_MSR_FN(AmdFam10hOsVisWrkStatus);
6334	CPUM_ASSERT_WR_MSR_FN(AmdFam16hL2IPerfCtlN);
6335	CPUM_ASSERT_WR_MSR_FN(AmdFam16hL2IPerfCtrN);
6336	CPUM_ASSERT_WR_MSR_FN(AmdFam15hNorthbridgePerfCtlN);
6337	CPUM_ASSERT_WR_MSR_FN(AmdFam15hNorthbridgePerfCtrN);
6338	CPUM_ASSERT_WR_MSR_FN(AmdK7MicrocodeCtl);
6339	CPUM_ASSERT_WR_MSR_FN(AmdK7ClusterIdMaybe);
6340	CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd07hEbax);
6341	CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd06hEcx);
6342	CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd01hEdcx);
6343	CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlExt01hEdcx);
6344	CPUM_ASSERT_WR_MSR_FN(AmdK8PatchLoader);
6345	CPUM_ASSERT_WR_MSR_FN(AmdK7DebugStatusMaybe);
6346	CPUM_ASSERT_WR_MSR_FN(AmdK7BHTraceBaseMaybe);
6347	CPUM_ASSERT_WR_MSR_FN(AmdK7BHTracePtrMaybe);
6348	CPUM_ASSERT_WR_MSR_FN(AmdK7BHTraceLimitMaybe);
6349	CPUM_ASSERT_WR_MSR_FN(AmdK7HardwareDebugToolCfgMaybe);
6350	CPUM_ASSERT_WR_MSR_FN(AmdK7FastFlushCountMaybe);
6351	CPUM_ASSERT_WR_MSR_FN(AmdK7NodeId);
6352	CPUM_ASSERT_WR_MSR_FN(AmdK7DrXAddrMaskN);
6353	CPUM_ASSERT_WR_MSR_FN(AmdK7Dr0DataMatchMaybe);
6354	CPUM_ASSERT_WR_MSR_FN(AmdK7Dr0DataMaskMaybe);
6355	CPUM_ASSERT_WR_MSR_FN(AmdK7LoadStoreCfg);
6356	CPUM_ASSERT_WR_MSR_FN(AmdK7InstrCacheCfg);
6357	CPUM_ASSERT_WR_MSR_FN(AmdK7DataCacheCfg);
6358	CPUM_ASSERT_WR_MSR_FN(AmdK7BusUnitCfg);
6359	CPUM_ASSERT_WR_MSR_FN(AmdK7DebugCtl2Maybe);
6360	CPUM_ASSERT_WR_MSR_FN(AmdFam15hFpuCfg);
6361	CPUM_ASSERT_WR_MSR_FN(AmdFam15hDecoderCfg);
6362	CPUM_ASSERT_WR_MSR_FN(AmdFam10hBusUnitCfg2);
6363	CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg);
6364	CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg2);
6365	CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg3);
6366	CPUM_ASSERT_WR_MSR_FN(AmdFam15hExecUnitCfg);
6367	CPUM_ASSERT_WR_MSR_FN(AmdFam15hLoadStoreCfg2);
6368	CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchCtl);
6369	CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchLinAddr);
6370	CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchPhysAddr);
6371	CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpExecCtl);
6372	CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpRip);
6373	CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData);
6374	CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData2);
6375	CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData3);
6376	CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsDcLinAddr);
6377	CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsDcPhysAddr);
6378	CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsCtl);
6379	CPUM_ASSERT_WR_MSR_FN(AmdFam14hIbsBrTarget);
6380
6381	CPUM_ASSERT_WR_MSR_FN(Gim);
6382
6383	return VINF_SUCCESS;
6384	}
6385	#endif /* VBOX_STRICT && IN_RING3 */
6386
6387
6388	/**
6389	* Gets the scalable bus frequency.
6390	*
6391	* The bus frequency is used as a base in several MSRs that gives the CPU and
6392	* other frequency ratios.
6393	*
6394	* @returns Scalable bus frequency in Hz. Will not return CPUM_SBUSFREQ_UNKNOWN.
6395	* @param pVM The cross context VM structure.
6396	*/
6397	VMMDECL(uint64_t) CPUMGetGuestScalableBusFrequency(PVM pVM)
6398	{
6399	uint64_t uFreq = pVM->cpum.s.GuestInfo.uScalableBusFreq;
6400	if (uFreq == CPUM_SBUSFREQ_UNKNOWN)
6401	uFreq = CPUM_SBUSFREQ_100MHZ;
6402	return uFreq;
6403	}
6404
6405
6406	/**
6407	* Sets the guest EFER MSR without performing any additional checks.
6408	*
6409	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
6410	* @param uOldEfer The previous EFER MSR value.
6411	* @param uValidEfer The new, validated EFER MSR value.
6412	*
6413	* @remarks One would normally call CPUMIsGuestEferMsrWriteValid() before calling
6414	* this function to change the EFER in order to perform an EFER transition.
6415	*/
6416	VMMDECL(void) CPUMSetGuestEferMsrNoChecks(PVMCPUCC pVCpu, uint64_t uOldEfer, uint64_t uValidEfer)
6417	{
6418	pVCpu->cpum.s.Guest.msrEFER = uValidEfer;
6419
6420	/* AMD64 Architecture Programmer's Manual: 15.15 TLB Control; flush the TLB
6421	if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
6422	if ( (uOldEfer & (MSR_K6_EFER_NXE \| MSR_K6_EFER_LME \| MSR_K6_EFER_LMA))
6423	!= (pVCpu->cpum.s.Guest.msrEFER & (MSR_K6_EFER_NXE \| MSR_K6_EFER_LME \| MSR_K6_EFER_LMA)))
6424	{
6425	/// @todo PGMFlushTLB(pVCpu, cr3, true /fGlobal/);
6426	HMFlushTlb(pVCpu);
6427
6428	/* Notify PGM about NXE changes. */
6429	if ( (uOldEfer & MSR_K6_EFER_NXE)
6430	!= (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE))
6431	PGMNotifyNxeChanged(pVCpu, !(uOldEfer & MSR_K6_EFER_NXE));
6432	}
6433	}
6434
6435
6436	/**
6437	* Checks if a guest PAT MSR write is valid.
6438	*
6439	* @returns @c true if the PAT bit combination is valid, @c false otherwise.
6440	* @param uValue The PAT MSR value.
6441	*/
6442	VMMDECL(bool) CPUMIsPatMsrValid(uint64_t uValue)
6443	{
6444	for (uint32_t cShift = 0; cShift < 63; cShift += 8)
6445	{
6446	/* Check all eight bits because the top 5 bits of each byte are reserved. */
6447	uint8_t uType = (uint8_t)(uValue >> cShift);
6448	if ((uType >= 8) \|\| (uType == 2) \|\| (uType == 3))
6449	{
6450	Log(("CPUM: Invalid PAT type at %u:%u in IA32_PAT: %#llx (%#llx)\n", cShift + 7, cShift, uValue, uType));
6451	return false;
6452	}
6453	}
6454	return true;
6455	}
6456
6457
6458	/**
6459	* Validates an EFER MSR write and provides the new, validated EFER MSR.
6460	*
6461	* @returns VBox status code.
6462	* @param pVM The cross context VM structure.
6463	* @param uCr0 The CR0 of the CPU corresponding to the EFER MSR.
6464	* @param uOldEfer Value of the previous EFER MSR on the CPU if any.
6465	* @param uNewEfer The new EFER MSR value being written.
6466	* @param puValidEfer Where to store the validated EFER (only updated if
6467	* this function returns VINF_SUCCESS).
6468	*/
6469	VMMDECL(int) CPUMIsGuestEferMsrWriteValid(PVM pVM, uint64_t uCr0, uint64_t uOldEfer, uint64_t uNewEfer, uint64_t *puValidEfer)
6470	{
6471	/* #GP(0) If anything outside the allowed bits is set. */
6472	uint64_t fMask = CPUMGetGuestEferMsrValidMask(pVM);
6473	if (uNewEfer & ~fMask)
6474	{
6475	Log(("CPUM: Settings disallowed EFER bit. uNewEfer=%#RX64 fAllowed=%#RX64 -> #GP(0)\n", uNewEfer, fMask));
6476	return VERR_CPUM_RAISE_GP_0;
6477	}
6478
6479	/* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if
6480	paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
6481	if ( (uOldEfer & MSR_K6_EFER_LME) != (uNewEfer & MSR_K6_EFER_LME)
6482	&& (uCr0 & X86_CR0_PG))
6483	{
6484	Log(("CPUM: Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
6485	return VERR_CPUM_RAISE_GP_0;
6486	}
6487
6488	/* There are a few more: e.g. MSR_K6_EFER_LMSLE. */
6489	AssertMsg(!(uNewEfer & ~( MSR_K6_EFER_NXE
6490	\| MSR_K6_EFER_LME
6491	\| MSR_K6_EFER_LMA /* ignored anyway */
6492	\| MSR_K6_EFER_SCE
6493	\| MSR_K6_EFER_FFXSR
6494	\| MSR_K6_EFER_SVME)),
6495	("Unexpected value %#RX64\n", uNewEfer));
6496
6497	/* Ignore EFER.LMA, it's updated when setting CR0. */
6498	fMask &= ~MSR_K6_EFER_LMA;
6499
6500	*puValidEfer = (uOldEfer & ~fMask) \| (uNewEfer & fMask);
6501	return VINF_SUCCESS;
6502	}
6503
6504
6505	/**
6506	* Gets the mask of valid EFER bits depending on supported guest-CPU features.
6507	*
6508	* @returns Mask of valid EFER bits.
6509	* @param pVM The cross context VM structure.
6510	*
6511	* @remarks EFER.LMA is included as part of the valid mask. It's not invalid but
6512	* rather a read-only bit.
6513	*/
6514	VMMDECL(uint64_t) CPUMGetGuestEferMsrValidMask(PVM pVM)
6515	{
6516	uint32_t const fExtFeatures = pVM->cpum.s.aGuestCpuIdPatmExt[0].uEax >= 0x80000001
6517	? pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx
6518	: 0;
6519	uint64_t fMask = 0;
6520	uint64_t const fIgnoreMask = MSR_K6_EFER_LMA;
6521
6522	/* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
6523	if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_NX)
6524	fMask \|= MSR_K6_EFER_NXE;
6525	if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
6526	fMask \|= MSR_K6_EFER_LME;
6527	if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
6528	fMask \|= MSR_K6_EFER_SCE;
6529	if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
6530	fMask \|= MSR_K6_EFER_FFXSR;
6531	if (pVM->cpum.s.GuestFeatures.fSvm)
6532	fMask \|= MSR_K6_EFER_SVME;
6533
6534	return (fIgnoreMask \| fMask);
6535	}
6536
6537
6538	/**
6539	* Fast way for HM to access the MSR_K8_TSC_AUX register.
6540	*
6541	* @returns The register value.
6542	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
6543	* @thread EMT(pVCpu)
6544	*/
6545	VMM_INT_DECL(uint64_t) CPUMGetGuestTscAux(PVMCPUCC pVCpu)
6546	{
6547	Assert(!(pVCpu->cpum.s.Guest.fExtrn & CPUMCTX_EXTRN_TSC_AUX));
6548	return pVCpu->cpum.s.GuestMsrs.msr.TscAux;
6549	}
6550
6551
6552	/**
6553	* Fast way for HM to access the MSR_K8_TSC_AUX register.
6554	*
6555	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
6556	* @param uValue The new value.
6557	* @thread EMT(pVCpu)
6558	*/
6559	VMM_INT_DECL(void) CPUMSetGuestTscAux(PVMCPUCC pVCpu, uint64_t uValue)
6560	{
6561	pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_TSC_AUX;
6562	pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
6563	}
6564
6565
6566	/**
6567	* Fast way for HM to access the IA32_SPEC_CTRL register.
6568	*
6569	* @returns The register value.
6570	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
6571	* @thread EMT(pVCpu)
6572	*/
6573	VMM_INT_DECL(uint64_t) CPUMGetGuestSpecCtrl(PVMCPUCC pVCpu)
6574	{
6575	return pVCpu->cpum.s.GuestMsrs.msr.SpecCtrl;
6576	}
6577
6578
6579	/**
6580	* Fast way for HM to access the IA32_SPEC_CTRL register.
6581	*
6582	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
6583	* @param uValue The new value.
6584	* @thread EMT(pVCpu)
6585	*/
6586	VMM_INT_DECL(void) CPUMSetGuestSpecCtrl(PVMCPUCC pVCpu, uint64_t uValue)
6587	{
6588	pVCpu->cpum.s.GuestMsrs.msr.SpecCtrl = uValue;
6589	}
6590

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source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllMsrs.cpp@ 107817

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