VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllMsrs.cpp@ 50509

Last change on this file since 50509 was 50158, checked in by vboxsync, 11 years ago

cpumMsrWr_Ia32BiosSignId should ignore writes, not GP. Only used on P4.
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1/* $Id: CPUMAllMsrs.cpp 50158 2014-01-22 02:57:23Z vboxsync $ */
2/** @file
3 * CPUM - CPU MSR Registers.
4 */
5
6/*
7 * Copyright (C) 2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_CPUM
22#include <VBox/vmm/cpum.h>
23#include <VBox/vmm/pdmapi.h>
24#include <VBox/vmm/hm.h>
25#include <VBox/vmm/tm.h>
26#include "CPUMInternal.h"
27#include <VBox/vmm/vm.h>
28#include <VBox/err.h>
29
30
31/*******************************************************************************
32* Defined Constants And Macros *
33*******************************************************************************/
34/**
35 * Validates the CPUMMSRRANGE::offCpumCpu value and declares a local variable
36 * pointing to it.
37 *
38 * ASSUMES sizeof(a_Type) is a power of two and that the member is aligned
39 * correctly.
40 */
41#define CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(a_pVCpu, a_pRange, a_Type, a_VarName) \
42 AssertMsgReturn( (a_pRange)->offCpumCpu >= 8 \
43 && (a_pRange)->offCpumCpu < sizeof(CPUMCPU) \
44 && !((a_pRange)->offCpumCpu & (RT_MIN(sizeof(a_Type), 8) - 1)) \
45 , ("offCpumCpu=%#x %s\n", (a_pRange)->offCpumCpu, (a_pRange)->szName), \
46 VERR_CPUM_MSR_BAD_CPUMCPU_OFFSET); \
47 a_Type *a_VarName = (a_Type *)((uintptr_t)&(a_pVCpu)->cpum.s + (a_pRange)->offCpumCpu)
48
49
50/*******************************************************************************
51* Structures and Typedefs *
52*******************************************************************************/
53
54/**
55 * Implements reading one or more MSRs.
56 *
57 * @returns VBox status code.
58 * @retval VINF_SUCCESS on success.
59 * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR).
60 *
61 * @param pVCpu Pointer to the VMCPU.
62 * @param idMsr The MSR we're reading.
63 * @param pRange The MSR range descriptor.
64 * @param puValue Where to return the value.
65 */
66typedef DECLCALLBACK(int) FNCPUMRDMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue);
67/** Pointer to a RDMSR worker for a specific MSR or range of MSRs. */
68typedef FNCPUMRDMSR *PFNCPUMRDMSR;
69
70
71/**
72 * Implements writing one or more MSRs.
73 *
74 * @retval VINF_SUCCESS on success.
75 * @retval VERR_CPUM_RAISE_GP_0 on failure.
76 *
77 * @param pVCpu Pointer to the VMCPU.
78 * @param idMsr The MSR we're writing.
79 * @param pRange The MSR range descriptor.
80 * @param uValue The value to set, ignored bits masked.
81 * @param uRawValue The raw value with the ignored bits not masked.
82 */
83typedef DECLCALLBACK(int) FNCPUMWRMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue);
84/** Pointer to a WRMSR worker for a specific MSR or range of MSRs. */
85typedef FNCPUMWRMSR *PFNCPUMWRMSR;
86
87
88
89/*
90 * Generic functions.
91 * Generic functions.
92 * Generic functions.
93 */
94
95
96/** @callback_method_impl{FNCPUMRDMSR} */
97static DECLCALLBACK(int) cpumMsrRd_FixedValue(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
98{
99 *puValue = pRange->uValue;
100 return VINF_SUCCESS;
101}
102
103
104/** @callback_method_impl{FNCPUMWRMSR} */
105static DECLCALLBACK(int) cpumMsrWr_IgnoreWrite(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
106{
107 Log(("CPUM: Ignoring WRMSR %#x (%s), %#llx\n", idMsr, pRange->szName, uValue));
108 return VINF_SUCCESS;
109}
110
111
112/** @callback_method_impl{FNCPUMRDMSR} */
113static DECLCALLBACK(int) cpumMsrRd_WriteOnly(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
114{
115 return VERR_CPUM_RAISE_GP_0;
116}
117
118
119/** @callback_method_impl{FNCPUMWRMSR} */
120static DECLCALLBACK(int) cpumMsrWr_ReadOnly(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
121{
122 Assert(pRange->fWrGpMask == UINT64_MAX);
123 return VERR_CPUM_RAISE_GP_0;
124}
125
126
127
128
129/*
130 * IA32
131 * IA32
132 * IA32
133 */
134
135/** @callback_method_impl{FNCPUMRDMSR} */
136static DECLCALLBACK(int) cpumMsrRd_Ia32P5McAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
137{
138 *puValue = 0; /** @todo implement machine check injection. */
139 return VINF_SUCCESS;
140}
141
142
143/** @callback_method_impl{FNCPUMWRMSR} */
144static DECLCALLBACK(int) cpumMsrWr_Ia32P5McAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
145{
146 /** @todo implement machine check injection. */
147 return VINF_SUCCESS;
148}
149
150
151/** @callback_method_impl{FNCPUMRDMSR} */
152static DECLCALLBACK(int) cpumMsrRd_Ia32P5McType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
153{
154 *puValue = 0; /** @todo implement machine check injection. */
155 return VINF_SUCCESS;
156}
157
158
159/** @callback_method_impl{FNCPUMWRMSR} */
160static DECLCALLBACK(int) cpumMsrWr_Ia32P5McType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
161{
162 /** @todo implement machine check injection. */
163 return VINF_SUCCESS;
164}
165
166
167/** @callback_method_impl{FNCPUMRDMSR} */
168static DECLCALLBACK(int) cpumMsrRd_Ia32TimestampCounter(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
169{
170 *puValue = TMCpuTickGet(pVCpu);
171 return VINF_SUCCESS;
172}
173
174
175/** @callback_method_impl{FNCPUMWRMSR} */
176static DECLCALLBACK(int) cpumMsrWr_Ia32TimestampCounter(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
177{
178 TMCpuTickSet(pVCpu->CTX_SUFF(pVM), pVCpu, uValue);
179 return VINF_SUCCESS;
180}
181
182
183/** @callback_method_impl{FNCPUMRDMSR} */
184static DECLCALLBACK(int) cpumMsrRd_Ia32ApicBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
185{
186 PVM pVM = pVCpu->CTX_SUFF(pVM);
187 if ( !pVM->cpum.s.GuestFeatures.fApic
188 && !pVM->cpum.s.GuestFeatures.fX2Apic)
189 {
190 Log(("CPUM: %s, apic not present -> GP\n", pRange->szName));
191 return VERR_CPUM_RAISE_GP_0;
192 }
193
194 *puValue = pVCpu->cpum.s.Guest.msrApicBase;
195 return VINF_SUCCESS;
196}
197
198
199/** @callback_method_impl{FNCPUMWRMSR} */
200static DECLCALLBACK(int) cpumMsrWr_Ia32ApicBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
201{
202 int rc = PDMApicSetBase(pVCpu, uValue);
203 if (rc != VINF_SUCCESS)
204 rc = VERR_CPUM_RAISE_GP_0;
205 return VINF_SUCCESS;
206}
207
208
209/** @callback_method_impl{FNCPUMRDMSR} */
210static DECLCALLBACK(int) cpumMsrRd_Ia32FeatureControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
211{
212 *puValue = 1; /* Locked, no VT-X, no SYSENTER micromanagement. */
213 return VINF_SUCCESS;
214}
215
216
217/** @callback_method_impl{FNCPUMWRMSR} */
218static DECLCALLBACK(int) cpumMsrWr_Ia32FeatureControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
219{
220 return VERR_CPUM_RAISE_GP_0;
221}
222
223
224/** @callback_method_impl{FNCPUMRDMSR} */
225static DECLCALLBACK(int) cpumMsrRd_Ia32BiosSignId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
226{
227 /** @todo fake microcode update. */
228 *puValue = pRange->uValue;
229 return VINF_SUCCESS;
230}
231
232
233/** @callback_method_impl{FNCPUMWRMSR} */
234static DECLCALLBACK(int) cpumMsrWr_Ia32BiosSignId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
235{
236 /* Normally, zero is written to Ia32BiosSignId before reading it in order
237 to select the signature instead of the BBL_CR_D3 behaviour. The GP mask
238 of the database entry should take care of most illegal writes for now, so
239 just ignore all writes atm. */
240 return VINF_SUCCESS;
241}
242
243
244/** @callback_method_impl{FNCPUMWRMSR} */
245static DECLCALLBACK(int) cpumMsrWr_Ia32BiosUpdateTrigger(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
246{
247 /** @todo Fake bios update trigger better. The value is the address to an
248 * update package, I think. We should probably GP if it's invalid. */
249 return VINF_SUCCESS;
250}
251
252
253/** @callback_method_impl{FNCPUMRDMSR} */
254static DECLCALLBACK(int) cpumMsrRd_Ia32SmmMonitorCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
255{
256 /** @todo SMM. */
257 *puValue = 0;
258 return VINF_SUCCESS;
259}
260
261
262/** @callback_method_impl{FNCPUMWRMSR} */
263static DECLCALLBACK(int) cpumMsrWr_Ia32SmmMonitorCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
264{
265 /** @todo SMM. */
266 return VINF_SUCCESS;
267}
268
269
270/** @callback_method_impl{FNCPUMRDMSR} */
271static DECLCALLBACK(int) cpumMsrRd_Ia32PmcN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
272{
273 /** @todo check CPUID leaf 0ah. */
274 *puValue = 0;
275 return VINF_SUCCESS;
276}
277
278
279/** @callback_method_impl{FNCPUMWRMSR} */
280static DECLCALLBACK(int) cpumMsrWr_Ia32PmcN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
281{
282 /** @todo check CPUID leaf 0ah. */
283 return VINF_SUCCESS;
284}
285
286
287/** @callback_method_impl{FNCPUMRDMSR} */
288static DECLCALLBACK(int) cpumMsrRd_Ia32MonitorFilterLineSize(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
289{
290 /** @todo return 0x1000 if we try emulate mwait 100% correctly. */
291 *puValue = 0x40; /** @todo Change to CPU cache line size. */
292 return VINF_SUCCESS;
293}
294
295
296/** @callback_method_impl{FNCPUMWRMSR} */
297static DECLCALLBACK(int) cpumMsrWr_Ia32MonitorFilterLineSize(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
298{
299 /** @todo should remember writes, though it's supposedly something only a BIOS
300 * would write so, it's not extremely important. */
301 return VINF_SUCCESS;
302}
303
304/** @callback_method_impl{FNCPUMRDMSR} */
305static DECLCALLBACK(int) cpumMsrRd_Ia32MPerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
306{
307 /** @todo Read MPERF: Adjust against previously written MPERF value. Is TSC
308 * what we want? */
309 *puValue = TMCpuTickGet(pVCpu);
310 return VINF_SUCCESS;
311}
312
313
314/** @callback_method_impl{FNCPUMWRMSR} */
315static DECLCALLBACK(int) cpumMsrWr_Ia32MPerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
316{
317 /** @todo Write MPERF: Calc adjustment. */
318 return VINF_SUCCESS;
319}
320
321
322/** @callback_method_impl{FNCPUMRDMSR} */
323static DECLCALLBACK(int) cpumMsrRd_Ia32APerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
324{
325 /** @todo Read APERF: Adjust against previously written MPERF value. Is TSC
326 * what we want? */
327 *puValue = TMCpuTickGet(pVCpu);
328 return VINF_SUCCESS;
329}
330
331
332/** @callback_method_impl{FNCPUMWRMSR} */
333static DECLCALLBACK(int) cpumMsrWr_Ia32APerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
334{
335 /** @todo Write APERF: Calc adjustment. */
336 return VINF_SUCCESS;
337}
338
339
340/** @callback_method_impl{FNCPUMWRMSR} */
341static DECLCALLBACK(int) cpumMsrRd_Ia32MtrrCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
342{
343 /* This is currently a bit weird. :-) */
344 uint8_t const cVariableRangeRegs = 0;
345 bool const fSystemManagementRangeRegisters = false;
346 bool const fFixedRangeRegisters = false;
347 bool const fWriteCombiningType = false;
348 *puValue = cVariableRangeRegs
349 | (fFixedRangeRegisters ? RT_BIT_64(8) : 0)
350 | (fWriteCombiningType ? RT_BIT_64(10) : 0)
351 | (fSystemManagementRangeRegisters ? RT_BIT_64(11) : 0);
352 return VINF_SUCCESS;
353}
354
355
356/** @callback_method_impl{FNCPUMRDMSR} */
357static DECLCALLBACK(int) cpumMsrRd_Ia32MtrrPhysBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
358{
359 /** @todo Implement variable MTRR storage. */
360 Assert(pRange->uValue == (idMsr - 0x200) / 2);
361 *puValue = 0;
362 return VINF_SUCCESS;
363}
364
365
366/** @callback_method_impl{FNCPUMWRMSR} */
367static DECLCALLBACK(int) cpumMsrWr_Ia32MtrrPhysBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
368{
369 /*
370 * Validate the value.
371 */
372 Assert(pRange->uValue == (idMsr - 0x200) / 2);
373
374 if ((uValue & 0xff) >= 7)
375 {
376 Log(("CPUM: Invalid type set writing MTRR PhysBase MSR %#x: %#llx (%#llx)\n", idMsr, uValue, uValue & 0xff));
377 return VERR_CPUM_RAISE_GP_0;
378 }
379
380 uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
381 if (fInvPhysMask & uValue)
382 {
383 Log(("CPUM: Invalid physical address bits set writing MTRR PhysBase MSR %#x: %#llx (%#llx)\n",
384 idMsr, uValue, uValue & fInvPhysMask));
385 return VERR_CPUM_RAISE_GP_0;
386 }
387
388 /*
389 * Store it.
390 */
391 /** @todo Implement variable MTRR storage. */
392 return VINF_SUCCESS;
393}
394
395
396/** @callback_method_impl{FNCPUMRDMSR} */
397static DECLCALLBACK(int) cpumMsrRd_Ia32MtrrPhysMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
398{
399 /** @todo Implement variable MTRR storage. */
400 Assert(pRange->uValue == (idMsr - 0x200) / 2);
401 *puValue = 0;
402 return VINF_SUCCESS;
403}
404
405
406/** @callback_method_impl{FNCPUMWRMSR} */
407static DECLCALLBACK(int) cpumMsrWr_Ia32MtrrPhysMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
408{
409 /*
410 * Validate the value.
411 */
412 Assert(pRange->uValue == (idMsr - 0x200) / 2);
413
414 uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
415 if (fInvPhysMask & uValue)
416 {
417 Log(("CPUM: Invalid physical address bits set writing MTRR PhysMask MSR %#x: %#llx (%#llx)\n",
418 idMsr, uValue, uValue & fInvPhysMask));
419 return VERR_CPUM_RAISE_GP_0;
420 }
421
422 /*
423 * Store it.
424 */
425 /** @todo Implement variable MTRR storage. */
426 return VINF_SUCCESS;
427}
428
429
430/** @callback_method_impl{FNCPUMRDMSR} */
431static DECLCALLBACK(int) cpumMsrRd_Ia32MtrrFixed(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
432{
433 CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(pVCpu, pRange, uint64_t, puFixedMtrr);
434 *puValue = *puFixedMtrr;
435 return VINF_SUCCESS;
436}
437
438
439/** @callback_method_impl{FNCPUMWRMSR} */
440static DECLCALLBACK(int) cpumMsrWr_Ia32MtrrFixed(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
441{
442 CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(pVCpu, pRange, uint64_t, puFixedMtrr);
443 for (uint32_t cShift = 0; cShift < 63; cShift += 8)
444 {
445 uint8_t uType = (uint8_t)(uValue >> cShift);
446 if (uType >= 7)
447 {
448 Log(("CPUM: Invalid MTRR type at %u:%u in fixed range (%#x/%s): %#llx (%#llx)\n",
449 cShift + 7, cShift, idMsr, pRange->szName, uValue, uType));
450 return VERR_CPUM_RAISE_GP_0;
451 }
452 }
453 *puFixedMtrr = uValue;
454 return VINF_SUCCESS;
455}
456
457
458/** @callback_method_impl{FNCPUMRDMSR} */
459static DECLCALLBACK(int) cpumMsrRd_Ia32MtrrDefType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
460{
461 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType;
462 return VINF_SUCCESS;
463}
464
465
466/** @callback_method_impl{FNCPUMWRMSR} */
467static DECLCALLBACK(int) cpumMsrWr_Ia32MtrrDefType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
468{
469 if ((uValue & 0xff) >= 7)
470 {
471 Log(("CPUM: Invalid MTRR default type value: %#llx (%#llx)\n", pRange->szName, uValue, uValue & 0xff));
472 return VERR_CPUM_RAISE_GP_0;
473 }
474
475 pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType = uValue;
476 return VINF_SUCCESS;
477}
478
479
480/** @callback_method_impl{FNCPUMRDMSR} */
481static DECLCALLBACK(int) cpumMsrRd_Ia32Pat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
482{
483 *puValue = pVCpu->cpum.s.Guest.msrPAT;
484 return VINF_SUCCESS;
485}
486
487
488/** @callback_method_impl{FNCPUMWRMSR} */
489static DECLCALLBACK(int) cpumMsrWr_Ia32Pat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
490{
491 pVCpu->cpum.s.Guest.msrPAT = uValue;
492 return VINF_SUCCESS;
493}
494
495
496/** @callback_method_impl{FNCPUMRDMSR} */
497static DECLCALLBACK(int) cpumMsrRd_Ia32SysEnterCs(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
498{
499 *puValue = pVCpu->cpum.s.Guest.SysEnter.cs;
500 return VINF_SUCCESS;
501}
502
503
504/** @callback_method_impl{FNCPUMWRMSR} */
505static DECLCALLBACK(int) cpumMsrWr_Ia32SysEnterCs(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
506{
507 /* Note! We used to mask this by 0xffff, but turns out real HW doesn't and
508 there are generally 32-bit working bits backing this register. */
509 pVCpu->cpum.s.Guest.SysEnter.cs = uValue;
510 return VINF_SUCCESS;
511}
512
513
514/** @callback_method_impl{FNCPUMRDMSR} */
515static DECLCALLBACK(int) cpumMsrRd_Ia32SysEnterEsp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
516{
517 *puValue = pVCpu->cpum.s.Guest.SysEnter.esp;
518 return VINF_SUCCESS;
519}
520
521
522/** @callback_method_impl{FNCPUMWRMSR} */
523static DECLCALLBACK(int) cpumMsrWr_Ia32SysEnterEsp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
524{
525 if (X86_IS_CANONICAL(uValue))
526 {
527 pVCpu->cpum.s.Guest.SysEnter.esp = uValue;
528 return VINF_SUCCESS;
529 }
530 Log(("CPUM: IA32_SYSENTER_ESP not canonical! %#llx\n", uValue));
531 return VERR_CPUM_RAISE_GP_0;
532}
533
534
535/** @callback_method_impl{FNCPUMRDMSR} */
536static DECLCALLBACK(int) cpumMsrRd_Ia32SysEnterEip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
537{
538 *puValue = pVCpu->cpum.s.Guest.SysEnter.eip;
539 return VINF_SUCCESS;
540}
541
542
543/** @callback_method_impl{FNCPUMWRMSR} */
544static DECLCALLBACK(int) cpumMsrWr_Ia32SysEnterEip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
545{
546 if (X86_IS_CANONICAL(uValue))
547 {
548 pVCpu->cpum.s.Guest.SysEnter.eip = uValue;
549 return VINF_SUCCESS;
550 }
551 Log(("CPUM: IA32_SYSENTER_EIP not canonical! %#llx\n", uValue));
552 return VERR_CPUM_RAISE_GP_0;
553}
554
555
556/** @callback_method_impl{FNCPUMRDMSR} */
557static DECLCALLBACK(int) cpumMsrRd_Ia32McgCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
558{
559#if 0 /** @todo implement machine checks. */
560 *puValue = pRange->uValue & (RT_BIT_64(8) | 0);
561#else
562 *puValue = 0;
563#endif
564 return VINF_SUCCESS;
565}
566
567
568/** @callback_method_impl{FNCPUMRDMSR} */
569static DECLCALLBACK(int) cpumMsrRd_Ia32McgStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
570{
571 /** @todo implement machine checks. */
572 *puValue = 0;
573 return VINF_SUCCESS;
574}
575
576
577/** @callback_method_impl{FNCPUMWRMSR} */
578static DECLCALLBACK(int) cpumMsrWr_Ia32McgStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
579{
580 /** @todo implement machine checks. */
581 return VINF_SUCCESS;
582}
583
584
585/** @callback_method_impl{FNCPUMRDMSR} */
586static DECLCALLBACK(int) cpumMsrRd_Ia32McgCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
587{
588 /** @todo implement machine checks. */
589 *puValue = 0;
590 return VINF_SUCCESS;
591}
592
593
594/** @callback_method_impl{FNCPUMWRMSR} */
595static DECLCALLBACK(int) cpumMsrWr_Ia32McgCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
596{
597 /** @todo implement machine checks. */
598 return VINF_SUCCESS;
599}
600
601
602/** @callback_method_impl{FNCPUMRDMSR} */
603static DECLCALLBACK(int) cpumMsrRd_Ia32DebugCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
604{
605 /** @todo implement IA32_DEBUGCTL. */
606 *puValue = 0;
607 return VINF_SUCCESS;
608}
609
610
611/** @callback_method_impl{FNCPUMWRMSR} */
612static DECLCALLBACK(int) cpumMsrWr_Ia32DebugCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
613{
614 /** @todo implement IA32_DEBUGCTL. */
615 return VINF_SUCCESS;
616}
617
618
619/** @callback_method_impl{FNCPUMRDMSR} */
620static DECLCALLBACK(int) cpumMsrRd_Ia32SmrrPhysBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
621{
622 /** @todo implement intel SMM. */
623 *puValue = 0;
624 return VINF_SUCCESS;
625}
626
627
628/** @callback_method_impl{FNCPUMWRMSR} */
629static DECLCALLBACK(int) cpumMsrWr_Ia32SmrrPhysBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
630{
631 /** @todo implement intel SMM. */
632 return VERR_CPUM_RAISE_GP_0;
633}
634
635
636/** @callback_method_impl{FNCPUMRDMSR} */
637static DECLCALLBACK(int) cpumMsrRd_Ia32SmrrPhysMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
638{
639 /** @todo implement intel SMM. */
640 *puValue = 0;
641 return VINF_SUCCESS;
642}
643
644
645/** @callback_method_impl{FNCPUMWRMSR} */
646static DECLCALLBACK(int) cpumMsrWr_Ia32SmrrPhysMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
647{
648 /** @todo implement intel SMM. */
649 return VERR_CPUM_RAISE_GP_0;
650}
651
652
653/** @callback_method_impl{FNCPUMRDMSR} */
654static DECLCALLBACK(int) cpumMsrRd_Ia32PlatformDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
655{
656 /** @todo implement intel direct cache access (DCA)?? */
657 *puValue = 0;
658 return VINF_SUCCESS;
659}
660
661
662/** @callback_method_impl{FNCPUMWRMSR} */
663static DECLCALLBACK(int) cpumMsrWr_Ia32PlatformDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
664{
665 /** @todo implement intel direct cache access (DCA)?? */
666 return VINF_SUCCESS;
667}
668
669
670/** @callback_method_impl{FNCPUMRDMSR} */
671static DECLCALLBACK(int) cpumMsrRd_Ia32CpuDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
672{
673 /** @todo implement intel direct cache access (DCA)?? */
674 *puValue = 0;
675 return VINF_SUCCESS;
676}
677
678
679/** @callback_method_impl{FNCPUMRDMSR} */
680static DECLCALLBACK(int) cpumMsrRd_Ia32Dca0Cap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
681{
682 /** @todo implement intel direct cache access (DCA)?? */
683 *puValue = 0;
684 return VINF_SUCCESS;
685}
686
687
688/** @callback_method_impl{FNCPUMWRMSR} */
689static DECLCALLBACK(int) cpumMsrWr_Ia32Dca0Cap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
690{
691 /** @todo implement intel direct cache access (DCA)?? */
692 return VINF_SUCCESS;
693}
694
695
696/** @callback_method_impl{FNCPUMRDMSR} */
697static DECLCALLBACK(int) cpumMsrRd_Ia32PerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
698{
699 /** @todo implement IA32_PERFEVTSEL0+. */
700 *puValue = 0;
701 return VINF_SUCCESS;
702}
703
704
705/** @callback_method_impl{FNCPUMWRMSR} */
706static DECLCALLBACK(int) cpumMsrWr_Ia32PerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
707{
708 /** @todo implement IA32_PERFEVTSEL0+. */
709 return VINF_SUCCESS;
710}
711
712
713/** @callback_method_impl{FNCPUMRDMSR} */
714static DECLCALLBACK(int) cpumMsrRd_Ia32PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
715{
716 /** @todo implement IA32_PERFSTATUS. */
717 *puValue = pRange->uValue;
718 return VINF_SUCCESS;
719}
720
721
722/** @callback_method_impl{FNCPUMWRMSR} */
723static DECLCALLBACK(int) cpumMsrWr_Ia32PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
724{
725 /* Pentium4 allows writing, but all bits are ignored. */
726 return VINF_SUCCESS;
727}
728
729
730/** @callback_method_impl{FNCPUMRDMSR} */
731static DECLCALLBACK(int) cpumMsrRd_Ia32PerfCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
732{
733 /** @todo implement IA32_PERFCTL. */
734 *puValue = 0;
735 return VINF_SUCCESS;
736}
737
738
739/** @callback_method_impl{FNCPUMWRMSR} */
740static DECLCALLBACK(int) cpumMsrWr_Ia32PerfCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
741{
742 /** @todo implement IA32_PERFCTL. */
743 return VINF_SUCCESS;
744}
745
746
747/** @callback_method_impl{FNCPUMRDMSR} */
748static DECLCALLBACK(int) cpumMsrRd_Ia32FixedCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
749{
750 /** @todo implement IA32_FIXED_CTRn (fixed performance counters). */
751 *puValue = 0;
752 return VINF_SUCCESS;
753}
754
755
756/** @callback_method_impl{FNCPUMWRMSR} */
757static DECLCALLBACK(int) cpumMsrWr_Ia32FixedCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
758{
759 /** @todo implement IA32_FIXED_CTRn (fixed performance counters). */
760 return VINF_SUCCESS;
761}
762
763
764/** @callback_method_impl{FNCPUMRDMSR} */
765static DECLCALLBACK(int) cpumMsrRd_Ia32PerfCapabilities(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
766{
767 /** @todo implement performance counters. */
768 *puValue = 0;
769 return VINF_SUCCESS;
770}
771
772
773/** @callback_method_impl{FNCPUMWRMSR} */
774static DECLCALLBACK(int) cpumMsrWr_Ia32PerfCapabilities(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
775{
776 /** @todo implement performance counters. */
777 return VINF_SUCCESS;
778}
779
780
781/** @callback_method_impl{FNCPUMRDMSR} */
782static DECLCALLBACK(int) cpumMsrRd_Ia32FixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
783{
784 /** @todo implement performance counters. */
785 *puValue = 0;
786 return VINF_SUCCESS;
787}
788
789
790/** @callback_method_impl{FNCPUMWRMSR} */
791static DECLCALLBACK(int) cpumMsrWr_Ia32FixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
792{
793 /** @todo implement performance counters. */
794 return VINF_SUCCESS;
795}
796
797
798/** @callback_method_impl{FNCPUMRDMSR} */
799static DECLCALLBACK(int) cpumMsrRd_Ia32PerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
800{
801 /** @todo implement performance counters. */
802 *puValue = 0;
803 return VINF_SUCCESS;
804}
805
806
807/** @callback_method_impl{FNCPUMWRMSR} */
808static DECLCALLBACK(int) cpumMsrWr_Ia32PerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
809{
810 /** @todo implement performance counters. */
811 return VINF_SUCCESS;
812}
813
814
815/** @callback_method_impl{FNCPUMRDMSR} */
816static DECLCALLBACK(int) cpumMsrRd_Ia32PerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
817{
818 /** @todo implement performance counters. */
819 *puValue = 0;
820 return VINF_SUCCESS;
821}
822
823
824/** @callback_method_impl{FNCPUMWRMSR} */
825static DECLCALLBACK(int) cpumMsrWr_Ia32PerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
826{
827 /** @todo implement performance counters. */
828 return VINF_SUCCESS;
829}
830
831
832/** @callback_method_impl{FNCPUMRDMSR} */
833static DECLCALLBACK(int) cpumMsrRd_Ia32PerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
834{
835 /** @todo implement performance counters. */
836 *puValue = 0;
837 return VINF_SUCCESS;
838}
839
840
841/** @callback_method_impl{FNCPUMWRMSR} */
842static DECLCALLBACK(int) cpumMsrWr_Ia32PerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
843{
844 /** @todo implement performance counters. */
845 return VINF_SUCCESS;
846}
847
848
849/** @callback_method_impl{FNCPUMRDMSR} */
850static DECLCALLBACK(int) cpumMsrRd_Ia32PebsEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
851{
852 /** @todo implement performance counters. */
853 *puValue = 0;
854 return VINF_SUCCESS;
855}
856
857
858/** @callback_method_impl{FNCPUMWRMSR} */
859static DECLCALLBACK(int) cpumMsrWr_Ia32PebsEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
860{
861 /** @todo implement performance counters. */
862 return VINF_SUCCESS;
863}
864
865
866/** @callback_method_impl{FNCPUMRDMSR} */
867static DECLCALLBACK(int) cpumMsrRd_Ia32ClockModulation(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
868{
869 /** @todo implement IA32_CLOCK_MODULATION. */
870 *puValue = 0;
871 return VINF_SUCCESS;
872}
873
874
875/** @callback_method_impl{FNCPUMWRMSR} */
876static DECLCALLBACK(int) cpumMsrWr_Ia32ClockModulation(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
877{
878 /** @todo implement IA32_CLOCK_MODULATION. */
879 return VINF_SUCCESS;
880}
881
882
883/** @callback_method_impl{FNCPUMRDMSR} */
884static DECLCALLBACK(int) cpumMsrRd_Ia32ThermInterrupt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
885{
886 /** @todo implement IA32_THERM_INTERRUPT. */
887 *puValue = 0;
888 return VINF_SUCCESS;
889}
890
891
892/** @callback_method_impl{FNCPUMWRMSR} */
893static DECLCALLBACK(int) cpumMsrWr_Ia32ThermInterrupt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
894{
895 /** @todo implement IA32_THERM_STATUS. */
896 return VINF_SUCCESS;
897}
898
899
900/** @callback_method_impl{FNCPUMRDMSR} */
901static DECLCALLBACK(int) cpumMsrRd_Ia32ThermStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
902{
903 /** @todo implement IA32_THERM_STATUS. */
904 *puValue = 0;
905 return VINF_SUCCESS;
906}
907
908
909/** @callback_method_impl{FNCPUMWRMSR} */
910static DECLCALLBACK(int) cpumMsrWr_Ia32ThermStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
911{
912 /** @todo implement IA32_THERM_INTERRUPT. */
913 return VINF_SUCCESS;
914}
915
916
917/** @callback_method_impl{FNCPUMRDMSR} */
918static DECLCALLBACK(int) cpumMsrRd_Ia32Therm2Ctl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
919{
920 /** @todo implement IA32_THERM2_CTL. */
921 *puValue = 0;
922 return VINF_SUCCESS;
923}
924
925
926/** @callback_method_impl{FNCPUMWRMSR} */
927static DECLCALLBACK(int) cpumMsrWr_Ia32Therm2Ctl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
928{
929 /** @todo implement IA32_THERM2_CTL. */
930 return VINF_SUCCESS;
931}
932
933
934/** @callback_method_impl{FNCPUMRDMSR} */
935static DECLCALLBACK(int) cpumMsrRd_Ia32MiscEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
936{
937 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
938 return VINF_SUCCESS;
939}
940
941
942/** @callback_method_impl{FNCPUMWRMSR} */
943static DECLCALLBACK(int) cpumMsrWr_Ia32MiscEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
944{
945#ifdef LOG_ENABLED
946 uint64_t const uOld = pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
947#endif
948
949 /* Unsupported bits are generally ignored and stripped by the MSR range
950 entry that got us here. So, we just need to preserve fixed bits. */
951 pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = uValue
952 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
953 | MSR_IA32_MISC_ENABLE_BTS_UNAVAIL;
954
955 Log(("CPUM: IA32_MISC_ENABLE; old=%#llx written=%#llx => %#llx\n",
956 uOld, uValue, pVCpu->cpum.s.GuestMsrs.msr.MiscEnable));
957
958 /** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
959 /** @todo Wire up MSR_IA32_MISC_ENABLE_XD_DISABLE. */
960 return VINF_SUCCESS;
961}
962
963
964/** @callback_method_impl{FNCPUMRDMSR} */
965static DECLCALLBACK(int) cpumMsrRd_Ia32McCtlStatusAddrMiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
966{
967 /** @todo Implement machine check exception injection. */
968 switch (idMsr & 3)
969 {
970 case 0:
971 case 1:
972 *puValue = 0;
973 break;
974
975 /* The ADDR and MISC registers aren't accessible since the
976 corresponding STATUS bits are zero. */
977 case 2:
978 Log(("CPUM: Reading IA32_MCi_ADDR %#x -> #GP\n", idMsr));
979 return VERR_CPUM_RAISE_GP_0;
980 case 3:
981 Log(("CPUM: Reading IA32_MCi_MISC %#x -> #GP\n", idMsr));
982 return VERR_CPUM_RAISE_GP_0;
983 }
984 return VINF_SUCCESS;
985}
986
987
988/** @callback_method_impl{FNCPUMWRMSR} */
989static DECLCALLBACK(int) cpumMsrWr_Ia32McCtlStatusAddrMiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
990{
991 switch (idMsr & 3)
992 {
993 case 0:
994 /* Ignore writes to the CTL register. */
995 break;
996
997 case 1:
998 /* According to specs, the STATUS register can only be written to
999 with the value 0. VBoxCpuReport thinks different for a
1000 Pentium M Dothan, but implementing according to specs now. */
1001 if (uValue != 0)
1002 {
1003 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_STATUS %#x -> #GP\n", uValue, idMsr));
1004 return VERR_CPUM_RAISE_GP_0;
1005 }
1006 break;
1007
1008 /* Specs states that ADDR and MISC can be cleared by writing zeros.
1009 Writing 1s will GP. Need to figure out how this relates to the
1010 ADDRV and MISCV status flags. If writing is independent of those
1011 bits, we need to know whether the CPU really implements them since
1012 that is exposed by writing 0 to them.
1013 Implementing the solution with the fewer GPs for now. */
1014 case 2:
1015 if (uValue != 0)
1016 {
1017 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_ADDR %#x -> #GP\n", uValue, idMsr));
1018 return VERR_CPUM_RAISE_GP_0;
1019 }
1020 break;
1021 case 3:
1022 if (uValue != 0)
1023 {
1024 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_MISC %#x -> #GP\n", uValue, idMsr));
1025 return VERR_CPUM_RAISE_GP_0;
1026 }
1027 break;
1028 }
1029 return VINF_SUCCESS;
1030}
1031
1032
1033/** @callback_method_impl{FNCPUMRDMSR} */
1034static DECLCALLBACK(int) cpumMsrRd_Ia32McNCtl2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1035{
1036 /** @todo Implement machine check exception injection. */
1037 *puValue = 0;
1038 return VINF_SUCCESS;
1039}
1040
1041
1042/** @callback_method_impl{FNCPUMWRMSR} */
1043static DECLCALLBACK(int) cpumMsrWr_Ia32McNCtl2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1044{
1045 /** @todo Implement machine check exception injection. */
1046 return VINF_SUCCESS;
1047}
1048
1049
1050/** @callback_method_impl{FNCPUMRDMSR} */
1051static DECLCALLBACK(int) cpumMsrRd_Ia32DsArea(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1052{
1053 /** @todo implement IA32_DS_AREA. */
1054 *puValue = 0;
1055 return VINF_SUCCESS;
1056}
1057
1058
1059/** @callback_method_impl{FNCPUMWRMSR} */
1060static DECLCALLBACK(int) cpumMsrWr_Ia32DsArea(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1061{
1062 return VINF_SUCCESS;
1063}
1064
1065
1066/** @callback_method_impl{FNCPUMRDMSR} */
1067static DECLCALLBACK(int) cpumMsrRd_Ia32TscDeadline(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1068{
1069 /** @todo implement TSC deadline timer. */
1070 *puValue = 0;
1071 return VINF_SUCCESS;
1072}
1073
1074
1075/** @callback_method_impl{FNCPUMWRMSR} */
1076static DECLCALLBACK(int) cpumMsrWr_Ia32TscDeadline(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1077{
1078 /** @todo implement TSC deadline timer. */
1079 return VINF_SUCCESS;
1080}
1081
1082
1083/** @callback_method_impl{FNCPUMRDMSR} */
1084static DECLCALLBACK(int) cpumMsrRd_Ia32X2ApicN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1085{
1086 int rc = PDMApicReadMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, puValue);
1087 if (rc != VINF_SUCCESS)
1088 {
1089 Log(("CPUM: X2APIC %#x read => %Rrc => #GP\n", idMsr, rc));
1090 return VERR_CPUM_RAISE_GP_0;
1091 }
1092 return VINF_SUCCESS;
1093}
1094
1095
1096/** @callback_method_impl{FNCPUMWRMSR} */
1097static DECLCALLBACK(int) cpumMsrWr_Ia32X2ApicN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1098{
1099 int rc = PDMApicWriteMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, uValue);
1100 if (rc != VINF_SUCCESS)
1101 {
1102 Log(("CPUM: X2APIC %#x write %#llx => %Rrc => #GP\n", idMsr, rc, uValue));
1103 return VERR_CPUM_RAISE_GP_0;
1104 }
1105 return VINF_SUCCESS;
1106}
1107
1108
1109/** @callback_method_impl{FNCPUMRDMSR} */
1110static DECLCALLBACK(int) cpumMsrRd_Ia32DebugInterface(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1111{
1112 /** @todo IA32_DEBUG_INTERFACE (no docs) */
1113 *puValue = 0;
1114 return VINF_SUCCESS;
1115}
1116
1117
1118/** @callback_method_impl{FNCPUMWRMSR} */
1119static DECLCALLBACK(int) cpumMsrWr_Ia32DebugInterface(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1120{
1121 /** @todo IA32_DEBUG_INTERFACE (no docs) */
1122 return VINF_SUCCESS;
1123}
1124
1125
1126/** @callback_method_impl{FNCPUMRDMSR} */
1127static DECLCALLBACK(int) cpumMsrRd_Ia32VmxBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1128{
1129 *puValue = 0;
1130 return VINF_SUCCESS;
1131}
1132
1133
1134/** @callback_method_impl{FNCPUMRDMSR} */
1135static DECLCALLBACK(int) cpumMsrRd_Ia32VmxPinbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1136{
1137 *puValue = 0;
1138 return VINF_SUCCESS;
1139}
1140
1141
1142/** @callback_method_impl{FNCPUMRDMSR} */
1143static DECLCALLBACK(int) cpumMsrRd_Ia32VmxProcbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1144{
1145 *puValue = 0;
1146 return VINF_SUCCESS;
1147}
1148
1149
1150/** @callback_method_impl{FNCPUMRDMSR} */
1151static DECLCALLBACK(int) cpumMsrRd_Ia32VmxExitCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1152{
1153 *puValue = 0;
1154 return VINF_SUCCESS;
1155}
1156
1157
1158/** @callback_method_impl{FNCPUMRDMSR} */
1159static DECLCALLBACK(int) cpumMsrRd_Ia32VmxEntryCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1160{
1161 *puValue = 0;
1162 return VINF_SUCCESS;
1163}
1164
1165
1166/** @callback_method_impl{FNCPUMRDMSR} */
1167static DECLCALLBACK(int) cpumMsrRd_Ia32VmxMisc(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1168{
1169 *puValue = 0;
1170 return VINF_SUCCESS;
1171}
1172
1173
1174/** @callback_method_impl{FNCPUMRDMSR} */
1175static DECLCALLBACK(int) cpumMsrRd_Ia32VmxCr0Fixed0(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1176{
1177 *puValue = 0;
1178 return VINF_SUCCESS;
1179}
1180
1181
1182/** @callback_method_impl{FNCPUMRDMSR} */
1183static DECLCALLBACK(int) cpumMsrRd_Ia32VmxCr0Fixed1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1184{
1185 *puValue = 0;
1186 return VINF_SUCCESS;
1187}
1188
1189
1190/** @callback_method_impl{FNCPUMRDMSR} */
1191static DECLCALLBACK(int) cpumMsrRd_Ia32VmxCr4Fixed0(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1192{
1193 *puValue = 0;
1194 return VINF_SUCCESS;
1195}
1196
1197
1198/** @callback_method_impl{FNCPUMRDMSR} */
1199static DECLCALLBACK(int) cpumMsrRd_Ia32VmxCr4Fixed1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1200{
1201 *puValue = 0;
1202 return VINF_SUCCESS;
1203}
1204
1205
1206/** @callback_method_impl{FNCPUMRDMSR} */
1207static DECLCALLBACK(int) cpumMsrRd_Ia32VmxVmcsEnum(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1208{
1209 *puValue = 0;
1210 return VINF_SUCCESS;
1211}
1212
1213
1214/** @callback_method_impl{FNCPUMRDMSR} */
1215static DECLCALLBACK(int) cpumMsrRd_Ia32VmxProcBasedCtls2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1216{
1217 *puValue = 0;
1218 return VINF_SUCCESS;
1219}
1220
1221
1222/** @callback_method_impl{FNCPUMRDMSR} */
1223static DECLCALLBACK(int) cpumMsrRd_Ia32VmxEptVpidCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1224{
1225 *puValue = 0;
1226 return VINF_SUCCESS;
1227}
1228
1229
1230/** @callback_method_impl{FNCPUMRDMSR} */
1231static DECLCALLBACK(int) cpumMsrRd_Ia32VmxTruePinbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1232{
1233 *puValue = 0;
1234 return VINF_SUCCESS;
1235}
1236
1237
1238/** @callback_method_impl{FNCPUMRDMSR} */
1239static DECLCALLBACK(int) cpumMsrRd_Ia32VmxTrueProcbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1240{
1241 *puValue = 0;
1242 return VINF_SUCCESS;
1243}
1244
1245
1246/** @callback_method_impl{FNCPUMRDMSR} */
1247static DECLCALLBACK(int) cpumMsrRd_Ia32VmxTrueExitCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1248{
1249 *puValue = 0;
1250 return VINF_SUCCESS;
1251}
1252
1253
1254/** @callback_method_impl{FNCPUMRDMSR} */
1255static DECLCALLBACK(int) cpumMsrRd_Ia32VmxTrueEntryCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1256{
1257 *puValue = 0;
1258 return VINF_SUCCESS;
1259}
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270/*
1271 * AMD64
1272 * AMD64
1273 * AMD64
1274 */
1275
1276
1277/** @callback_method_impl{FNCPUMRDMSR} */
1278static DECLCALLBACK(int) cpumMsrRd_Amd64Efer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1279{
1280 *puValue = pVCpu->cpum.s.Guest.msrEFER;
1281 return VINF_SUCCESS;
1282}
1283
1284
1285/** @callback_method_impl{FNCPUMWRMSR} */
1286static DECLCALLBACK(int) cpumMsrWr_Amd64Efer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1287{
1288 PVM pVM = pVCpu->CTX_SUFF(pVM);
1289 uint64_t const uOldEfer = pVCpu->cpum.s.Guest.msrEFER;
1290 uint32_t const fExtFeatures = pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1291 ? pVM->cpum.s.aGuestCpuIdExt[1].edx
1292 : 0;
1293 uint64_t fMask = 0;
1294
1295 /* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
1296 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_NX)
1297 fMask |= MSR_K6_EFER_NXE;
1298 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
1299 fMask |= MSR_K6_EFER_LME;
1300 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
1301 fMask |= MSR_K6_EFER_SCE;
1302 if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1303 fMask |= MSR_K6_EFER_FFXSR;
1304
1305 /* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if
1306 paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1307 if ( (uOldEfer & MSR_K6_EFER_LME) != (uValue & fMask & MSR_K6_EFER_LME)
1308 && (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG))
1309 {
1310 Log(("CPUM: Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
1311 return VERR_CPUM_RAISE_GP_0;
1312 }
1313
1314 /* There are a few more: e.g. MSR_K6_EFER_LMSLE */
1315 AssertMsg(!(uValue & ~(MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA /* ignored anyway */ | MSR_K6_EFER_SCE | MSR_K6_EFER_FFXSR)),
1316 ("Unexpected value %RX64\n", uValue));
1317 pVCpu->cpum.s.Guest.msrEFER = (uOldEfer & ~fMask) | (uValue & fMask);
1318
1319 /* AMD64 Architecture Programmer's Manual: 15.15 TLB Control; flush the TLB
1320 if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
1321 if ( (uOldEfer & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA))
1322 != (pVCpu->cpum.s.Guest.msrEFER & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA)))
1323 {
1324 /// @todo PGMFlushTLB(pVCpu, cr3, true /*fGlobal*/);
1325 HMFlushTLB(pVCpu);
1326
1327 /* Notify PGM about NXE changes. */
1328 if ( (uOldEfer & MSR_K6_EFER_NXE)
1329 != (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE))
1330 PGMNotifyNxeChanged(pVCpu, !(uOldEfer & MSR_K6_EFER_NXE));
1331 }
1332 return VINF_SUCCESS;
1333}
1334
1335
1336/** @callback_method_impl{FNCPUMRDMSR} */
1337static DECLCALLBACK(int) cpumMsrRd_Amd64SyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1338{
1339 *puValue = pVCpu->cpum.s.Guest.msrSTAR;
1340 return VINF_SUCCESS;
1341}
1342
1343
1344/** @callback_method_impl{FNCPUMWRMSR} */
1345static DECLCALLBACK(int) cpumMsrWr_Amd64SyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1346{
1347 pVCpu->cpum.s.Guest.msrSTAR = uValue;
1348 return VINF_SUCCESS;
1349}
1350
1351
1352/** @callback_method_impl{FNCPUMRDMSR} */
1353static DECLCALLBACK(int) cpumMsrRd_Amd64LongSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1354{
1355 *puValue = pVCpu->cpum.s.Guest.msrLSTAR;
1356 return VINF_SUCCESS;
1357}
1358
1359
1360/** @callback_method_impl{FNCPUMWRMSR} */
1361static DECLCALLBACK(int) cpumMsrWr_Amd64LongSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1362{
1363 if (!X86_IS_CANONICAL(uValue))
1364 {
1365 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
1366 return VERR_CPUM_RAISE_GP_0;
1367 }
1368 pVCpu->cpum.s.Guest.msrLSTAR = uValue;
1369 return VINF_SUCCESS;
1370}
1371
1372
1373/** @callback_method_impl{FNCPUMRDMSR} */
1374static DECLCALLBACK(int) cpumMsrRd_Amd64CompSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1375{
1376 *puValue = pVCpu->cpum.s.Guest.msrCSTAR;
1377 return VINF_SUCCESS;
1378}
1379
1380
1381/** @callback_method_impl{FNCPUMWRMSR} */
1382static DECLCALLBACK(int) cpumMsrWr_Amd64CompSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1383{
1384 if (!X86_IS_CANONICAL(uValue))
1385 {
1386 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
1387 return VERR_CPUM_RAISE_GP_0;
1388 }
1389 pVCpu->cpum.s.Guest.msrCSTAR = uValue;
1390 return VINF_SUCCESS;
1391}
1392
1393
1394/** @callback_method_impl{FNCPUMRDMSR} */
1395static DECLCALLBACK(int) cpumMsrRd_Amd64SyscallFlagMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1396{
1397 *puValue = pVCpu->cpum.s.Guest.msrSFMASK;
1398 return VINF_SUCCESS;
1399}
1400
1401
1402/** @callback_method_impl{FNCPUMWRMSR} */
1403static DECLCALLBACK(int) cpumMsrWr_Amd64SyscallFlagMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1404{
1405 pVCpu->cpum.s.Guest.msrSFMASK = uValue;
1406 return VINF_SUCCESS;
1407}
1408
1409
1410/** @callback_method_impl{FNCPUMRDMSR} */
1411static DECLCALLBACK(int) cpumMsrRd_Amd64FsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1412{
1413 *puValue = pVCpu->cpum.s.Guest.fs.u64Base;
1414 return VINF_SUCCESS;
1415}
1416
1417
1418/** @callback_method_impl{FNCPUMWRMSR} */
1419static DECLCALLBACK(int) cpumMsrWr_Amd64FsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1420{
1421 pVCpu->cpum.s.Guest.fs.u64Base = uValue;
1422 return VINF_SUCCESS;
1423}
1424
1425
1426/** @callback_method_impl{FNCPUMRDMSR} */
1427static DECLCALLBACK(int) cpumMsrRd_Amd64GsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1428{
1429 *puValue = pVCpu->cpum.s.Guest.gs.u64Base;
1430 return VINF_SUCCESS;
1431}
1432
1433/** @callback_method_impl{FNCPUMWRMSR} */
1434static DECLCALLBACK(int) cpumMsrWr_Amd64GsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1435{
1436 pVCpu->cpum.s.Guest.gs.u64Base = uValue;
1437 return VINF_SUCCESS;
1438}
1439
1440
1441
1442/** @callback_method_impl{FNCPUMRDMSR} */
1443static DECLCALLBACK(int) cpumMsrRd_Amd64KernelGsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1444{
1445 *puValue = pVCpu->cpum.s.Guest.msrKERNELGSBASE;
1446 return VINF_SUCCESS;
1447}
1448
1449/** @callback_method_impl{FNCPUMWRMSR} */
1450static DECLCALLBACK(int) cpumMsrWr_Amd64KernelGsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1451{
1452 pVCpu->cpum.s.Guest.msrKERNELGSBASE = uValue;
1453 return VINF_SUCCESS;
1454}
1455
1456
1457/** @callback_method_impl{FNCPUMRDMSR} */
1458static DECLCALLBACK(int) cpumMsrRd_Amd64TscAux(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1459{
1460 *puValue = pVCpu->cpum.s.GuestMsrs.msr.TscAux;
1461 return VINF_SUCCESS;
1462}
1463
1464/** @callback_method_impl{FNCPUMWRMSR} */
1465static DECLCALLBACK(int) cpumMsrWr_Amd64TscAux(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1466{
1467 pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
1468 return VINF_SUCCESS;
1469}
1470
1471
1472/*
1473 * Intel specific
1474 * Intel specific
1475 * Intel specific
1476 */
1477
1478/** @callback_method_impl{FNCPUMRDMSR} */
1479static DECLCALLBACK(int) cpumMsrRd_IntelEblCrPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1480{
1481 /** @todo recalc clock frequency ratio? */
1482 *puValue = pRange->uValue;
1483 return VINF_SUCCESS;
1484}
1485
1486
1487/** @callback_method_impl{FNCPUMWRMSR} */
1488static DECLCALLBACK(int) cpumMsrWr_IntelEblCrPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1489{
1490 /** @todo Write EBL_CR_POWERON: Remember written bits. */
1491 return VINF_SUCCESS;
1492}
1493
1494
1495/** @callback_method_impl{FNCPUMRDMSR} */
1496static DECLCALLBACK(int) cpumMsrRd_IntelP4EbcHardPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1497{
1498 /** @todo P4 hard power on config */
1499 *puValue = pRange->uValue;
1500 return VINF_SUCCESS;
1501}
1502
1503
1504/** @callback_method_impl{FNCPUMWRMSR} */
1505static DECLCALLBACK(int) cpumMsrWr_IntelP4EbcHardPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1506{
1507 /** @todo P4 hard power on config */
1508 return VINF_SUCCESS;
1509}
1510
1511
1512/** @callback_method_impl{FNCPUMRDMSR} */
1513static DECLCALLBACK(int) cpumMsrRd_IntelP4EbcSoftPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1514{
1515 /** @todo P4 soft power on config */
1516 *puValue = pRange->uValue;
1517 return VINF_SUCCESS;
1518}
1519
1520
1521/** @callback_method_impl{FNCPUMWRMSR} */
1522static DECLCALLBACK(int) cpumMsrWr_IntelP4EbcSoftPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1523{
1524 /** @todo P4 soft power on config */
1525 return VINF_SUCCESS;
1526}
1527
1528
1529/** @callback_method_impl{FNCPUMRDMSR} */
1530static DECLCALLBACK(int) cpumMsrRd_IntelP4EbcFrequencyId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1531{
1532 /** @todo P4 bus frequency config */
1533 *puValue = pRange->uValue;
1534 return VINF_SUCCESS;
1535}
1536
1537
1538/** @callback_method_impl{FNCPUMWRMSR} */
1539static DECLCALLBACK(int) cpumMsrWr_IntelP4EbcFrequencyId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1540{
1541 /** @todo P4 bus frequency config */
1542 return VINF_SUCCESS;
1543}
1544
1545
1546/** @callback_method_impl{FNCPUMRDMSR} */
1547static DECLCALLBACK(int) cpumMsrRd_IntelPlatformInfo100MHz(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1548{
1549 PVM pVM = pVCpu->CTX_SUFF(pVM);
1550
1551 /* Just indicate a fixed TSC, no turbo boost, no programmable anything. */
1552 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
1553 uint8_t uTsc100MHz = (uint8_t)(uTscHz / UINT32_C(100000000));
1554 *puValue = ((uint32_t)uTsc100MHz << 8) /* TSC invariant frequency. */
1555 | ((uint64_t)uTsc100MHz << 40); /* The max turbo frequency. */
1556
1557 /* Ivy bridge has a minimum operating ratio as well. */
1558 if (true) /** @todo detect sandy bridge. */
1559 *puValue |= (uint64_t)uTsc100MHz << 48;
1560
1561 return VINF_SUCCESS;
1562}
1563
1564
1565/** @callback_method_impl{FNCPUMRDMSR} */
1566static DECLCALLBACK(int) cpumMsrRd_IntelPlatformInfo133MHz(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1567{
1568 /* Just indicate a fixed TSC, no turbo boost, no programmable anything. */
1569 uint64_t uTscHz = TMCpuTicksPerSecond(pVCpu->CTX_SUFF(pVM));
1570 uint8_t uTsc133MHz = (uint8_t)(uTscHz / UINT32_C(133333333));
1571 *puValue = ((uint32_t)uTsc133MHz << 8) /* TSC invariant frequency. */
1572 | ((uint64_t)uTsc133MHz << 40); /* The max turbo frequency. */
1573 return VINF_SUCCESS;
1574}
1575
1576
1577/** @callback_method_impl{FNCPUMRDMSR} */
1578static DECLCALLBACK(int) cpumMsrRd_IntelPkgCStConfigControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1579{
1580 *puValue = pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl;
1581 return VINF_SUCCESS;
1582}
1583
1584
1585/** @callback_method_impl{FNCPUMWRMSR} */
1586static DECLCALLBACK(int) cpumMsrWr_IntelPkgCStConfigControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1587{
1588 if (pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl & RT_BIT_64(15))
1589 {
1590 Log(("CPUM: WRMDR %#x (%s), %#llx: Write protected -> #GP\n", idMsr, pRange->szName, uValue));
1591 return VERR_CPUM_RAISE_GP_0;
1592 }
1593#if 0 /** @todo check what real (old) hardware does. */
1594 if ((uValue & 7) >= 5)
1595 {
1596 Log(("CPUM: WRMDR %#x (%s), %#llx: Invalid limit (%d) -> #GP\n", idMsr, pRange->szName, uValue, (uint32_t)(uValue & 7)));
1597 return VERR_CPUM_RAISE_GP_0;
1598 }
1599#endif
1600 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = uValue;
1601 return VINF_SUCCESS;
1602}
1603
1604
1605/** @callback_method_impl{FNCPUMRDMSR} */
1606static DECLCALLBACK(int) cpumMsrRd_IntelPmgIoCaptureBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1607{
1608 /** @todo implement I/O mwait wakeup. */
1609 *puValue = 0;
1610 return VINF_SUCCESS;
1611}
1612
1613
1614/** @callback_method_impl{FNCPUMWRMSR} */
1615static DECLCALLBACK(int) cpumMsrWr_IntelPmgIoCaptureBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1616{
1617 /** @todo implement I/O mwait wakeup. */
1618 return VINF_SUCCESS;
1619}
1620
1621
1622/** @callback_method_impl{FNCPUMRDMSR} */
1623static DECLCALLBACK(int) cpumMsrRd_IntelLastBranchFromToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1624{
1625 /** @todo implement last branch records. */
1626 *puValue = 0;
1627 return VINF_SUCCESS;
1628}
1629
1630
1631/** @callback_method_impl{FNCPUMWRMSR} */
1632static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchFromToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1633{
1634 /** @todo implement last branch records. */
1635 return VINF_SUCCESS;
1636}
1637
1638
1639/** @callback_method_impl{FNCPUMRDMSR} */
1640static DECLCALLBACK(int) cpumMsrRd_IntelLastBranchFromN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1641{
1642 /** @todo implement last branch records. */
1643 *puValue = 0;
1644 return VINF_SUCCESS;
1645}
1646
1647
1648/** @callback_method_impl{FNCPUMWRMSR} */
1649static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchFromN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1650{
1651 /** @todo implement last branch records. */
1652 /** @todo Probing indicates that bit 63 is settable on SandyBridge, at least
1653 * if the rest of the bits are zero. Automatic sign extending?
1654 * Investigate! */
1655 if (!X86_IS_CANONICAL(uValue))
1656 {
1657 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
1658 return VERR_CPUM_RAISE_GP_0;
1659 }
1660 return VINF_SUCCESS;
1661}
1662
1663
1664/** @callback_method_impl{FNCPUMRDMSR} */
1665static DECLCALLBACK(int) cpumMsrRd_IntelLastBranchToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1666{
1667 /** @todo implement last branch records. */
1668 *puValue = 0;
1669 return VINF_SUCCESS;
1670}
1671
1672
1673/** @callback_method_impl{FNCPUMWRMSR} */
1674static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1675{
1676 /** @todo implement last branch records. */
1677 /** @todo Probing indicates that bit 63 is settable on SandyBridge, at least
1678 * if the rest of the bits are zero. Automatic sign extending?
1679 * Investigate! */
1680 if (!X86_IS_CANONICAL(uValue))
1681 {
1682 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
1683 return VERR_CPUM_RAISE_GP_0;
1684 }
1685 return VINF_SUCCESS;
1686}
1687
1688
1689/** @callback_method_impl{FNCPUMRDMSR} */
1690static DECLCALLBACK(int) cpumMsrRd_IntelLastBranchTos(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1691{
1692 /** @todo implement last branch records. */
1693 *puValue = 0;
1694 return VINF_SUCCESS;
1695}
1696
1697
1698/** @callback_method_impl{FNCPUMWRMSR} */
1699static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchTos(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1700{
1701 /** @todo implement last branch records. */
1702 return VINF_SUCCESS;
1703}
1704
1705
1706/** @callback_method_impl{FNCPUMRDMSR} */
1707static DECLCALLBACK(int) cpumMsrRd_IntelBblCrCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1708{
1709 *puValue = pRange->uValue;
1710 return VINF_SUCCESS;
1711}
1712
1713
1714/** @callback_method_impl{FNCPUMWRMSR} */
1715static DECLCALLBACK(int) cpumMsrWr_IntelBblCrCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1716{
1717 return VINF_SUCCESS;
1718}
1719
1720
1721/** @callback_method_impl{FNCPUMRDMSR} */
1722static DECLCALLBACK(int) cpumMsrRd_IntelBblCrCtl3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1723{
1724 *puValue = pRange->uValue;
1725 return VINF_SUCCESS;
1726}
1727
1728
1729/** @callback_method_impl{FNCPUMWRMSR} */
1730static DECLCALLBACK(int) cpumMsrWr_IntelBblCrCtl3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1731{
1732 return VINF_SUCCESS;
1733}
1734
1735
1736/** @callback_method_impl{FNCPUMRDMSR} */
1737static DECLCALLBACK(int) cpumMsrRd_IntelI7TemperatureTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1738{
1739 *puValue = pRange->uValue;
1740 return VINF_SUCCESS;
1741}
1742
1743
1744/** @callback_method_impl{FNCPUMWRMSR} */
1745static DECLCALLBACK(int) cpumMsrWr_IntelI7TemperatureTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1746{
1747 return VINF_SUCCESS;
1748}
1749
1750
1751/** @callback_method_impl{FNCPUMRDMSR} */
1752static DECLCALLBACK(int) cpumMsrRd_IntelI7MsrOffCoreResponseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1753{
1754 /** @todo machine check. */
1755 *puValue = pRange->uValue;
1756 return VINF_SUCCESS;
1757}
1758
1759
1760/** @callback_method_impl{FNCPUMWRMSR} */
1761static DECLCALLBACK(int) cpumMsrWr_IntelI7MsrOffCoreResponseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1762{
1763 /** @todo machine check. */
1764 return VINF_SUCCESS;
1765}
1766
1767
1768/** @callback_method_impl{FNCPUMRDMSR} */
1769static DECLCALLBACK(int) cpumMsrRd_IntelI7MiscPwrMgmt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1770{
1771 *puValue = 0;
1772 return VINF_SUCCESS;
1773}
1774
1775
1776/** @callback_method_impl{FNCPUMWRMSR} */
1777static DECLCALLBACK(int) cpumMsrWr_IntelI7MiscPwrMgmt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1778{
1779 return VINF_SUCCESS;
1780}
1781
1782
1783/** @callback_method_impl{FNCPUMRDMSR} */
1784static DECLCALLBACK(int) cpumMsrRd_IntelP6CrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1785{
1786 int rc = CPUMGetGuestCRx(pVCpu, pRange->uValue, puValue);
1787 AssertRC(rc);
1788 return VINF_SUCCESS;
1789}
1790
1791
1792/** @callback_method_impl{FNCPUMWRMSR} */
1793static DECLCALLBACK(int) cpumMsrWr_IntelP6CrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1794{
1795 /* This CRx interface differs from the MOV CRx, GReg interface in that
1796 #GP(0) isn't raised if unsupported bits are written to. Instead they
1797 are simply ignored and masked off. (Pentium M Dothan) */
1798 /** @todo Implement MSR_P6_CRx writing. Too much effort for very little, if
1799 * any, gain. */
1800 return VINF_SUCCESS;
1801}
1802
1803
1804/** @callback_method_impl{FNCPUMRDMSR} */
1805static DECLCALLBACK(int) cpumMsrRd_IntelCpuId1FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1806{
1807 /** @todo implement CPUID masking. */
1808 *puValue = UINT64_MAX;
1809 return VINF_SUCCESS;
1810}
1811
1812
1813/** @callback_method_impl{FNCPUMWRMSR} */
1814static DECLCALLBACK(int) cpumMsrWr_IntelCpuId1FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1815{
1816 /** @todo implement CPUID masking. */
1817 return VINF_SUCCESS;
1818}
1819
1820
1821/** @callback_method_impl{FNCPUMRDMSR} */
1822static DECLCALLBACK(int) cpumMsrRd_IntelCpuId1FeatureMaskEax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1823{
1824 /** @todo implement CPUID masking. */
1825 return VINF_SUCCESS;
1826}
1827
1828
1829/** @callback_method_impl{FNCPUMWRMSR} */
1830static DECLCALLBACK(int) cpumMsrWr_IntelCpuId1FeatureMaskEax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1831{
1832 /** @todo implement CPUID masking. */
1833 return VINF_SUCCESS;
1834}
1835
1836
1837
1838/** @callback_method_impl{FNCPUMRDMSR} */
1839static DECLCALLBACK(int) cpumMsrRd_IntelCpuId80000001FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1840{
1841 /** @todo implement CPUID masking. */
1842 *puValue = UINT64_MAX;
1843 return VINF_SUCCESS;
1844}
1845
1846
1847/** @callback_method_impl{FNCPUMWRMSR} */
1848static DECLCALLBACK(int) cpumMsrWr_IntelCpuId80000001FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1849{
1850 /** @todo implement CPUID masking. */
1851 return VINF_SUCCESS;
1852}
1853
1854
1855
1856/** @callback_method_impl{FNCPUMRDMSR} */
1857static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyAesNiCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1858{
1859 /** @todo implement AES-NI. */
1860 *puValue = 3; /* Bit 0 is lock bit, bit 1 disables AES-NI. That's what they say. */
1861 return VINF_SUCCESS;
1862}
1863
1864
1865/** @callback_method_impl{FNCPUMWRMSR} */
1866static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyAesNiCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1867{
1868 /** @todo implement AES-NI. */
1869 return VERR_CPUM_RAISE_GP_0;
1870}
1871
1872
1873/** @callback_method_impl{FNCPUMRDMSR} */
1874static DECLCALLBACK(int) cpumMsrRd_IntelI7TurboRatioLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1875{
1876 /** @todo implement intel C states. */
1877 *puValue = pRange->uValue;
1878 return VINF_SUCCESS;
1879}
1880
1881
1882/** @callback_method_impl{FNCPUMWRMSR} */
1883static DECLCALLBACK(int) cpumMsrWr_IntelI7TurboRatioLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1884{
1885 /** @todo implement intel C states. */
1886 return VINF_SUCCESS;
1887}
1888
1889
1890/** @callback_method_impl{FNCPUMRDMSR} */
1891static DECLCALLBACK(int) cpumMsrRd_IntelI7LbrSelect(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1892{
1893 /** @todo implement last-branch-records. */
1894 *puValue = 0;
1895 return VINF_SUCCESS;
1896}
1897
1898
1899/** @callback_method_impl{FNCPUMWRMSR} */
1900static DECLCALLBACK(int) cpumMsrWr_IntelI7LbrSelect(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1901{
1902 /** @todo implement last-branch-records. */
1903 return VINF_SUCCESS;
1904}
1905
1906
1907/** @callback_method_impl{FNCPUMRDMSR} */
1908static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyErrorControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1909{
1910 /** @todo implement memory error injection (MSR_ERROR_CONTROL). */
1911 *puValue = 0;
1912 return VINF_SUCCESS;
1913}
1914
1915
1916/** @callback_method_impl{FNCPUMWRMSR} */
1917static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyErrorControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1918{
1919 /** @todo implement memory error injection (MSR_ERROR_CONTROL). */
1920 return VINF_SUCCESS;
1921}
1922
1923
1924/** @callback_method_impl{FNCPUMRDMSR} */
1925static DECLCALLBACK(int) cpumMsrRd_IntelI7VirtualLegacyWireCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1926{
1927 /** @todo implement memory VLW? */
1928 *puValue = pRange->uValue;
1929 /* Note: A20M is known to be bit 1 as this was disclosed in spec update
1930 AAJ49/AAK51/????, which documents the inversion of this bit. The
1931 Sandy bridge CPU here has value 0x74, so it probably doesn't have a BIOS
1932 that correct things. Some guesses at the other bits:
1933 bit 2 = INTR
1934 bit 4 = SMI
1935 bit 5 = INIT
1936 bit 6 = NMI */
1937 return VINF_SUCCESS;
1938}
1939
1940
1941/** @callback_method_impl{FNCPUMRDMSR} */
1942static DECLCALLBACK(int) cpumMsrRd_IntelI7PowerCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1943{
1944 /** @todo intel power management */
1945 *puValue = 0;
1946 return VINF_SUCCESS;
1947}
1948
1949
1950/** @callback_method_impl{FNCPUMWRMSR} */
1951static DECLCALLBACK(int) cpumMsrWr_IntelI7PowerCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1952{
1953 /** @todo intel power management */
1954 return VINF_SUCCESS;
1955}
1956
1957
1958/** @callback_method_impl{FNCPUMRDMSR} */
1959static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyPebsNumAlt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1960{
1961 /** @todo intel performance counters. */
1962 *puValue = 0;
1963 return VINF_SUCCESS;
1964}
1965
1966
1967/** @callback_method_impl{FNCPUMWRMSR} */
1968static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyPebsNumAlt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1969{
1970 /** @todo intel performance counters. */
1971 return VINF_SUCCESS;
1972}
1973
1974
1975/** @callback_method_impl{FNCPUMRDMSR} */
1976static DECLCALLBACK(int) cpumMsrRd_IntelI7PebsLdLat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1977{
1978 /** @todo intel performance counters. */
1979 *puValue = 0;
1980 return VINF_SUCCESS;
1981}
1982
1983
1984/** @callback_method_impl{FNCPUMWRMSR} */
1985static DECLCALLBACK(int) cpumMsrWr_IntelI7PebsLdLat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1986{
1987 /** @todo intel performance counters. */
1988 return VINF_SUCCESS;
1989}
1990
1991
1992/** @callback_method_impl{FNCPUMRDMSR} */
1993static DECLCALLBACK(int) cpumMsrRd_IntelI7PkgCnResidencyN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1994{
1995 /** @todo intel power management. */
1996 *puValue = 0;
1997 return VINF_SUCCESS;
1998}
1999
2000
2001/** @callback_method_impl{FNCPUMRDMSR} */
2002static DECLCALLBACK(int) cpumMsrRd_IntelI7CoreCnResidencyN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2003{
2004 /** @todo intel power management. */
2005 *puValue = 0;
2006 return VINF_SUCCESS;
2007}
2008
2009
2010/** @callback_method_impl{FNCPUMRDMSR} */
2011static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyVrCurrentConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2012{
2013 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2014 *puValue = 0;
2015 return VINF_SUCCESS;
2016}
2017
2018
2019/** @callback_method_impl{FNCPUMWRMSR} */
2020static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyVrCurrentConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2021{
2022 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2023 return VINF_SUCCESS;
2024}
2025
2026
2027/** @callback_method_impl{FNCPUMRDMSR} */
2028static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyVrMiscConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2029{
2030 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2031 *puValue = 0;
2032 return VINF_SUCCESS;
2033}
2034
2035
2036/** @callback_method_impl{FNCPUMWRMSR} */
2037static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyVrMiscConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2038{
2039 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2040 return VINF_SUCCESS;
2041}
2042
2043
2044/** @callback_method_impl{FNCPUMRDMSR} */
2045static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyRaplPowerUnit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2046{
2047 /** @todo intel RAPL. */
2048 *puValue = pRange->uValue;
2049 return VINF_SUCCESS;
2050}
2051
2052
2053/** @callback_method_impl{FNCPUMRDMSR} */
2054static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyPkgCnIrtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2055{
2056 /** @todo intel power management. */
2057 *puValue = 0;
2058 return VINF_SUCCESS;
2059}
2060
2061
2062/** @callback_method_impl{FNCPUMWRMSR} */
2063static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyPkgCnIrtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2064{
2065 /** @todo intel power management. */
2066 return VINF_SUCCESS;
2067}
2068
2069
2070/** @callback_method_impl{FNCPUMRDMSR} */
2071static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyPkgC2Residency(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2072{
2073 /** @todo intel power management. */
2074 *puValue = 0;
2075 return VINF_SUCCESS;
2076}
2077
2078
2079/** @callback_method_impl{FNCPUMRDMSR} */
2080static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPkgPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2081{
2082 /** @todo intel RAPL. */
2083 *puValue = 0;
2084 return VINF_SUCCESS;
2085}
2086
2087
2088/** @callback_method_impl{FNCPUMWRMSR} */
2089static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPkgPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2090{
2091 /** @todo intel RAPL. */
2092 return VINF_SUCCESS;
2093}
2094
2095
2096/** @callback_method_impl{FNCPUMRDMSR} */
2097static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPkgEnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2098{
2099 /** @todo intel power management. */
2100 *puValue = 0;
2101 return VINF_SUCCESS;
2102}
2103
2104
2105/** @callback_method_impl{FNCPUMRDMSR} */
2106static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPkgPerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2107{
2108 /** @todo intel power management. */
2109 *puValue = 0;
2110 return VINF_SUCCESS;
2111}
2112
2113
2114/** @callback_method_impl{FNCPUMRDMSR} */
2115static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPkgPowerInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2116{
2117 /** @todo intel power management. */
2118 *puValue = 0;
2119 return VINF_SUCCESS;
2120}
2121
2122
2123/** @callback_method_impl{FNCPUMRDMSR} */
2124static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplDramPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2125{
2126 /** @todo intel RAPL. */
2127 *puValue = 0;
2128 return VINF_SUCCESS;
2129}
2130
2131
2132/** @callback_method_impl{FNCPUMWRMSR} */
2133static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplDramPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2134{
2135 /** @todo intel RAPL. */
2136 return VINF_SUCCESS;
2137}
2138
2139
2140/** @callback_method_impl{FNCPUMRDMSR} */
2141static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplDramEnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2142{
2143 /** @todo intel power management. */
2144 *puValue = 0;
2145 return VINF_SUCCESS;
2146}
2147
2148
2149/** @callback_method_impl{FNCPUMRDMSR} */
2150static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplDramPerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2151{
2152 /** @todo intel power management. */
2153 *puValue = 0;
2154 return VINF_SUCCESS;
2155}
2156
2157
2158/** @callback_method_impl{FNCPUMRDMSR} */
2159static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplDramPowerInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2160{
2161 /** @todo intel power management. */
2162 *puValue = 0;
2163 return VINF_SUCCESS;
2164}
2165
2166
2167/** @callback_method_impl{FNCPUMRDMSR} */
2168static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp0PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2169{
2170 /** @todo intel RAPL. */
2171 *puValue = 0;
2172 return VINF_SUCCESS;
2173}
2174
2175
2176/** @callback_method_impl{FNCPUMWRMSR} */
2177static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp0PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2178{
2179 /** @todo intel RAPL. */
2180 return VINF_SUCCESS;
2181}
2182
2183
2184/** @callback_method_impl{FNCPUMRDMSR} */
2185static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp0EnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2186{
2187 /** @todo intel power management. */
2188 *puValue = 0;
2189 return VINF_SUCCESS;
2190}
2191
2192
2193/** @callback_method_impl{FNCPUMRDMSR} */
2194static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp0Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2195{
2196 /** @todo intel RAPL. */
2197 *puValue = 0;
2198 return VINF_SUCCESS;
2199}
2200
2201
2202/** @callback_method_impl{FNCPUMWRMSR} */
2203static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp0Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2204{
2205 /** @todo intel RAPL. */
2206 return VINF_SUCCESS;
2207}
2208
2209
2210/** @callback_method_impl{FNCPUMRDMSR} */
2211static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp0PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2212{
2213 /** @todo intel power management. */
2214 *puValue = 0;
2215 return VINF_SUCCESS;
2216}
2217
2218
2219/** @callback_method_impl{FNCPUMRDMSR} */
2220static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp1PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2221{
2222 /** @todo intel RAPL. */
2223 *puValue = 0;
2224 return VINF_SUCCESS;
2225}
2226
2227
2228/** @callback_method_impl{FNCPUMWRMSR} */
2229static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp1PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2230{
2231 /** @todo intel RAPL. */
2232 return VINF_SUCCESS;
2233}
2234
2235
2236/** @callback_method_impl{FNCPUMRDMSR} */
2237static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp1EnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2238{
2239 /** @todo intel power management. */
2240 *puValue = 0;
2241 return VINF_SUCCESS;
2242}
2243
2244
2245/** @callback_method_impl{FNCPUMRDMSR} */
2246static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp1Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2247{
2248 /** @todo intel RAPL. */
2249 *puValue = 0;
2250 return VINF_SUCCESS;
2251}
2252
2253
2254/** @callback_method_impl{FNCPUMWRMSR} */
2255static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp1Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2256{
2257 /** @todo intel RAPL. */
2258 return VINF_SUCCESS;
2259}
2260
2261
2262/** @callback_method_impl{FNCPUMRDMSR} */
2263static DECLCALLBACK(int) cpumMsrRd_IntelI7IvyConfigTdpNominal(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2264{
2265 /** @todo intel power management. */
2266 *puValue = pRange->uValue;
2267 return VINF_SUCCESS;
2268}
2269
2270
2271/** @callback_method_impl{FNCPUMRDMSR} */
2272static DECLCALLBACK(int) cpumMsrRd_IntelI7IvyConfigTdpLevel1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2273{
2274 /** @todo intel power management. */
2275 *puValue = pRange->uValue;
2276 return VINF_SUCCESS;
2277}
2278
2279
2280/** @callback_method_impl{FNCPUMRDMSR} */
2281static DECLCALLBACK(int) cpumMsrRd_IntelI7IvyConfigTdpLevel2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2282{
2283 /** @todo intel power management. */
2284 *puValue = pRange->uValue;
2285 return VINF_SUCCESS;
2286}
2287
2288
2289/** @callback_method_impl{FNCPUMRDMSR} */
2290static DECLCALLBACK(int) cpumMsrRd_IntelI7IvyConfigTdpControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2291{
2292 /** @todo intel power management. */
2293 *puValue = 0;
2294 return VINF_SUCCESS;
2295}
2296
2297
2298/** @callback_method_impl{FNCPUMWRMSR} */
2299static DECLCALLBACK(int) cpumMsrWr_IntelI7IvyConfigTdpControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2300{
2301 /** @todo intel power management. */
2302 return VINF_SUCCESS;
2303}
2304
2305
2306/** @callback_method_impl{FNCPUMRDMSR} */
2307static DECLCALLBACK(int) cpumMsrRd_IntelI7IvyTurboActivationRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2308{
2309 /** @todo intel power management. */
2310 *puValue = 0;
2311 return VINF_SUCCESS;
2312}
2313
2314
2315/** @callback_method_impl{FNCPUMWRMSR} */
2316static DECLCALLBACK(int) cpumMsrWr_IntelI7IvyTurboActivationRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2317{
2318 /** @todo intel power management. */
2319 return VINF_SUCCESS;
2320}
2321
2322
2323/** @callback_method_impl{FNCPUMRDMSR} */
2324static DECLCALLBACK(int) cpumMsrRd_IntelI7UncPerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2325{
2326 /** @todo uncore msrs. */
2327 *puValue = 0;
2328 return VINF_SUCCESS;
2329}
2330
2331
2332/** @callback_method_impl{FNCPUMWRMSR} */
2333static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2334{
2335 /** @todo uncore msrs. */
2336 return VINF_SUCCESS;
2337}
2338
2339
2340/** @callback_method_impl{FNCPUMRDMSR} */
2341static DECLCALLBACK(int) cpumMsrRd_IntelI7UncPerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2342{
2343 /** @todo uncore msrs. */
2344 *puValue = 0;
2345 return VINF_SUCCESS;
2346}
2347
2348
2349/** @callback_method_impl{FNCPUMWRMSR} */
2350static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2351{
2352 /** @todo uncore msrs. */
2353 return VINF_SUCCESS;
2354}
2355
2356
2357/** @callback_method_impl{FNCPUMRDMSR} */
2358static DECLCALLBACK(int) cpumMsrRd_IntelI7UncPerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2359{
2360 /** @todo uncore msrs. */
2361 *puValue = 0;
2362 return VINF_SUCCESS;
2363}
2364
2365
2366/** @callback_method_impl{FNCPUMWRMSR} */
2367static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2368{
2369 /** @todo uncore msrs. */
2370 return VINF_SUCCESS;
2371}
2372
2373
2374/** @callback_method_impl{FNCPUMRDMSR} */
2375static DECLCALLBACK(int) cpumMsrRd_IntelI7UncPerfFixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2376{
2377 /** @todo uncore msrs. */
2378 *puValue = 0;
2379 return VINF_SUCCESS;
2380}
2381
2382
2383/** @callback_method_impl{FNCPUMWRMSR} */
2384static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfFixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2385{
2386 /** @todo uncore msrs. */
2387 return VINF_SUCCESS;
2388}
2389
2390
2391/** @callback_method_impl{FNCPUMRDMSR} */
2392static DECLCALLBACK(int) cpumMsrRd_IntelI7UncPerfFixedCtr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2393{
2394 /** @todo uncore msrs. */
2395 *puValue = 0;
2396 return VINF_SUCCESS;
2397}
2398
2399
2400/** @callback_method_impl{FNCPUMWRMSR} */
2401static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfFixedCtr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2402{
2403 /** @todo uncore msrs. */
2404 return VINF_SUCCESS;
2405}
2406
2407
2408/** @callback_method_impl{FNCPUMRDMSR} */
2409static DECLCALLBACK(int) cpumMsrRd_IntelI7UncCBoxConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2410{
2411 /** @todo uncore msrs. */
2412 *puValue = 0;
2413 return VINF_SUCCESS;
2414}
2415
2416
2417/** @callback_method_impl{FNCPUMRDMSR} */
2418static DECLCALLBACK(int) cpumMsrRd_IntelI7UncArbPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2419{
2420 /** @todo uncore msrs. */
2421 *puValue = 0;
2422 return VINF_SUCCESS;
2423}
2424
2425
2426/** @callback_method_impl{FNCPUMWRMSR} */
2427static DECLCALLBACK(int) cpumMsrWr_IntelI7UncArbPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2428{
2429 /** @todo uncore msrs. */
2430 return VINF_SUCCESS;
2431}
2432
2433
2434/** @callback_method_impl{FNCPUMRDMSR} */
2435static DECLCALLBACK(int) cpumMsrRd_IntelI7UncArbPerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2436{
2437 /** @todo uncore msrs. */
2438 *puValue = 0;
2439 return VINF_SUCCESS;
2440}
2441
2442
2443/** @callback_method_impl{FNCPUMWRMSR} */
2444static DECLCALLBACK(int) cpumMsrWr_IntelI7UncArbPerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2445{
2446 /** @todo uncore msrs. */
2447 return VINF_SUCCESS;
2448}
2449
2450
2451/** @callback_method_impl{FNCPUMRDMSR} */
2452static DECLCALLBACK(int) cpumMsrRd_IntelCore2EmttmCrTablesN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2453{
2454 /** @todo implement enhanced multi thread termal monitoring? */
2455 *puValue = pRange->uValue;
2456 return VINF_SUCCESS;
2457}
2458
2459
2460/** @callback_method_impl{FNCPUMWRMSR} */
2461static DECLCALLBACK(int) cpumMsrWr_IntelCore2EmttmCrTablesN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2462{
2463 /** @todo implement enhanced multi thread termal monitoring? */
2464 return VINF_SUCCESS;
2465}
2466
2467
2468/** @callback_method_impl{FNCPUMRDMSR} */
2469static DECLCALLBACK(int) cpumMsrRd_IntelCore2SmmCStMiscInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2470{
2471 /** @todo SMM & C-states? */
2472 *puValue = 0;
2473 return VINF_SUCCESS;
2474}
2475
2476
2477/** @callback_method_impl{FNCPUMWRMSR} */
2478static DECLCALLBACK(int) cpumMsrWr_IntelCore2SmmCStMiscInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2479{
2480 /** @todo SMM & C-states? */
2481 return VINF_SUCCESS;
2482}
2483
2484
2485/** @callback_method_impl{FNCPUMRDMSR} */
2486static DECLCALLBACK(int) cpumMsrRd_IntelCore1ExtConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2487{
2488 /** @todo Core1&2 EXT_CONFIG (whatever that is)? */
2489 *puValue = 0;
2490 return VINF_SUCCESS;
2491}
2492
2493
2494/** @callback_method_impl{FNCPUMWRMSR} */
2495static DECLCALLBACK(int) cpumMsrWr_IntelCore1ExtConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2496{
2497 /** @todo Core1&2 EXT_CONFIG (whatever that is)? */
2498 return VINF_SUCCESS;
2499}
2500
2501
2502/** @callback_method_impl{FNCPUMRDMSR} */
2503static DECLCALLBACK(int) cpumMsrRd_IntelCore1DtsCalControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2504{
2505 /** @todo Core1&2(?) DTS_CAL_CTRL (whatever that is)? */
2506 *puValue = 0;
2507 return VINF_SUCCESS;
2508}
2509
2510
2511/** @callback_method_impl{FNCPUMWRMSR} */
2512static DECLCALLBACK(int) cpumMsrWr_IntelCore1DtsCalControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2513{
2514 /** @todo Core1&2(?) DTS_CAL_CTRL (whatever that is)? */
2515 return VINF_SUCCESS;
2516}
2517
2518
2519/** @callback_method_impl{FNCPUMRDMSR} */
2520static DECLCALLBACK(int) cpumMsrRd_IntelCore2PeciControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2521{
2522 /** @todo Core2+ platform environment control interface control register? */
2523 *puValue = 0;
2524 return VINF_SUCCESS;
2525}
2526
2527
2528/** @callback_method_impl{FNCPUMWRMSR} */
2529static DECLCALLBACK(int) cpumMsrWr_IntelCore2PeciControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2530{
2531 /** @todo Core2+ platform environment control interface control register? */
2532 return VINF_SUCCESS;
2533}
2534
2535
2536
2537/*
2538 * Multiple vendor P6 MSRs.
2539 * Multiple vendor P6 MSRs.
2540 * Multiple vendor P6 MSRs.
2541 *
2542 * These MSRs were introduced with the P6 but not elevated to architectural
2543 * MSRs, despite other vendors implementing them.
2544 */
2545
2546
2547/** @callback_method_impl{FNCPUMRDMSR} */
2548static DECLCALLBACK(int) cpumMsrRd_P6LastBranchFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2549{
2550 /* AMD seems to just record RIP, while intel claims to record RIP+CS.BASE
2551 if I read the docs correctly, thus the need for separate functions. */
2552 /** @todo implement last branch records. */
2553 *puValue = 0;
2554 return VINF_SUCCESS;
2555}
2556
2557
2558/** @callback_method_impl{FNCPUMRDMSR} */
2559static DECLCALLBACK(int) cpumMsrRd_P6LastBranchToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2560{
2561 /** @todo implement last branch records. */
2562 *puValue = 0;
2563 return VINF_SUCCESS;
2564}
2565
2566
2567/** @callback_method_impl{FNCPUMRDMSR} */
2568static DECLCALLBACK(int) cpumMsrRd_P6LastIntFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2569{
2570 /** @todo implement last exception records. */
2571 *puValue = 0;
2572 return VINF_SUCCESS;
2573}
2574
2575
2576/** @callback_method_impl{FNCPUMWRMSR} */
2577static DECLCALLBACK(int) cpumMsrWr_P6LastIntFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2578{
2579 /** @todo implement last exception records. */
2580 return VINF_SUCCESS;
2581}
2582
2583
2584/** @callback_method_impl{FNCPUMRDMSR} */
2585static DECLCALLBACK(int) cpumMsrRd_P6LastIntToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2586{
2587 /** @todo implement last exception records. */
2588 *puValue = 0;
2589 return VINF_SUCCESS;
2590}
2591
2592
2593/** @callback_method_impl{FNCPUMWRMSR} */
2594static DECLCALLBACK(int) cpumMsrWr_P6LastIntToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2595{
2596 /** @todo implement last exception records. */
2597 return VINF_SUCCESS;
2598}
2599
2600
2601
2602/*
2603 * AMD specific
2604 * AMD specific
2605 * AMD specific
2606 */
2607
2608
2609/** @callback_method_impl{FNCPUMRDMSR} */
2610static DECLCALLBACK(int) cpumMsrRd_AmdFam15hTscRate(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2611{
2612 /** @todo Implement TscRateMsr */
2613 *puValue = RT_MAKE_U64(0, 1); /* 1.0 = reset value. */
2614 return VINF_SUCCESS;
2615}
2616
2617
2618/** @callback_method_impl{FNCPUMWRMSR} */
2619static DECLCALLBACK(int) cpumMsrWr_AmdFam15hTscRate(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2620{
2621 /** @todo Implement TscRateMsr */
2622 return VINF_SUCCESS;
2623}
2624
2625
2626/** @callback_method_impl{FNCPUMRDMSR} */
2627static DECLCALLBACK(int) cpumMsrRd_AmdFam15hLwpCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2628{
2629 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2630 /* Note: Only listes in BKDG for Family 15H. */
2631 *puValue = 0;
2632 return VINF_SUCCESS;
2633}
2634
2635
2636/** @callback_method_impl{FNCPUMWRMSR} */
2637static DECLCALLBACK(int) cpumMsrWr_AmdFam15hLwpCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2638{
2639 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2640 return VINF_SUCCESS;
2641}
2642
2643
2644/** @callback_method_impl{FNCPUMRDMSR} */
2645static DECLCALLBACK(int) cpumMsrRd_AmdFam15hLwpCbAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2646{
2647 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2648 /* Note: Only listes in BKDG for Family 15H. */
2649 *puValue = 0;
2650 return VINF_SUCCESS;
2651}
2652
2653
2654/** @callback_method_impl{FNCPUMWRMSR} */
2655static DECLCALLBACK(int) cpumMsrWr_AmdFam15hLwpCbAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2656{
2657 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2658 return VINF_SUCCESS;
2659}
2660
2661
2662/** @callback_method_impl{FNCPUMRDMSR} */
2663static DECLCALLBACK(int) cpumMsrRd_AmdFam10hMc4MiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2664{
2665 /** @todo machine check. */
2666 *puValue = 0;
2667 return VINF_SUCCESS;
2668}
2669
2670
2671/** @callback_method_impl{FNCPUMWRMSR} */
2672static DECLCALLBACK(int) cpumMsrWr_AmdFam10hMc4MiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2673{
2674 /** @todo machine check. */
2675 return VINF_SUCCESS;
2676}
2677
2678
2679/** @callback_method_impl{FNCPUMRDMSR} */
2680static DECLCALLBACK(int) cpumMsrRd_AmdK8PerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2681{
2682 /** @todo AMD performance events. */
2683 *puValue = 0;
2684 return VINF_SUCCESS;
2685}
2686
2687
2688/** @callback_method_impl{FNCPUMWRMSR} */
2689static DECLCALLBACK(int) cpumMsrWr_AmdK8PerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2690{
2691 /** @todo AMD performance events. */
2692 return VINF_SUCCESS;
2693}
2694
2695
2696/** @callback_method_impl{FNCPUMRDMSR} */
2697static DECLCALLBACK(int) cpumMsrRd_AmdK8PerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2698{
2699 /** @todo AMD performance events. */
2700 *puValue = 0;
2701 return VINF_SUCCESS;
2702}
2703
2704
2705/** @callback_method_impl{FNCPUMWRMSR} */
2706static DECLCALLBACK(int) cpumMsrWr_AmdK8PerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2707{
2708 /** @todo AMD performance events. */
2709 return VINF_SUCCESS;
2710}
2711
2712
2713/** @callback_method_impl{FNCPUMRDMSR} */
2714static DECLCALLBACK(int) cpumMsrRd_AmdK8SysCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2715{
2716 /** @todo AMD SYS_CFG */
2717 *puValue = pRange->uValue;
2718 return VINF_SUCCESS;
2719}
2720
2721
2722/** @callback_method_impl{FNCPUMWRMSR} */
2723static DECLCALLBACK(int) cpumMsrWr_AmdK8SysCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2724{
2725 /** @todo AMD SYS_CFG */
2726 return VINF_SUCCESS;
2727}
2728
2729
2730/** @callback_method_impl{FNCPUMRDMSR} */
2731static DECLCALLBACK(int) cpumMsrRd_AmdK8HwCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2732{
2733 /** @todo AMD HW_CFG */
2734 *puValue = 0;
2735 return VINF_SUCCESS;
2736}
2737
2738
2739/** @callback_method_impl{FNCPUMWRMSR} */
2740static DECLCALLBACK(int) cpumMsrWr_AmdK8HwCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2741{
2742 /** @todo AMD HW_CFG */
2743 return VINF_SUCCESS;
2744}
2745
2746
2747/** @callback_method_impl{FNCPUMRDMSR} */
2748static DECLCALLBACK(int) cpumMsrRd_AmdK8IorrBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2749{
2750 /** @todo AMD IorrMask/IorrBase */
2751 *puValue = 0;
2752 return VINF_SUCCESS;
2753}
2754
2755
2756/** @callback_method_impl{FNCPUMWRMSR} */
2757static DECLCALLBACK(int) cpumMsrWr_AmdK8IorrBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2758{
2759 /** @todo AMD IorrMask/IorrBase */
2760 return VINF_SUCCESS;
2761}
2762
2763
2764/** @callback_method_impl{FNCPUMRDMSR} */
2765static DECLCALLBACK(int) cpumMsrRd_AmdK8IorrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2766{
2767 /** @todo AMD IorrMask/IorrBase */
2768 *puValue = 0;
2769 return VINF_SUCCESS;
2770}
2771
2772
2773/** @callback_method_impl{FNCPUMWRMSR} */
2774static DECLCALLBACK(int) cpumMsrWr_AmdK8IorrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2775{
2776 /** @todo AMD IorrMask/IorrBase */
2777 return VINF_SUCCESS;
2778}
2779
2780
2781/** @callback_method_impl{FNCPUMRDMSR} */
2782static DECLCALLBACK(int) cpumMsrRd_AmdK8TopOfMemN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2783{
2784 *puValue = 0;
2785 /** @todo return 4GB - RamHoleSize here for TOPMEM. Figure out what to return
2786 * for TOPMEM2. */
2787 //if (pRange->uValue == 0)
2788 // *puValue = _4G - RamHoleSize;
2789 return VINF_SUCCESS;
2790}
2791
2792
2793/** @callback_method_impl{FNCPUMWRMSR} */
2794static DECLCALLBACK(int) cpumMsrWr_AmdK8TopOfMemN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2795{
2796 /** @todo AMD TOPMEM and TOPMEM2/TOM2. */
2797 return VINF_SUCCESS;
2798}
2799
2800
2801/** @callback_method_impl{FNCPUMRDMSR} */
2802static DECLCALLBACK(int) cpumMsrRd_AmdK8NbCfg1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2803{
2804 /** @todo AMD NB_CFG1 */
2805 *puValue = 0;
2806 return VINF_SUCCESS;
2807}
2808
2809
2810/** @callback_method_impl{FNCPUMWRMSR} */
2811static DECLCALLBACK(int) cpumMsrWr_AmdK8NbCfg1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2812{
2813 /** @todo AMD NB_CFG1 */
2814 return VINF_SUCCESS;
2815}
2816
2817
2818/** @callback_method_impl{FNCPUMRDMSR} */
2819static DECLCALLBACK(int) cpumMsrRd_AmdK8McXcptRedir(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2820{
2821 /** @todo machine check. */
2822 *puValue = 0;
2823 return VINF_SUCCESS;
2824}
2825
2826
2827/** @callback_method_impl{FNCPUMWRMSR} */
2828static DECLCALLBACK(int) cpumMsrWr_AmdK8McXcptRedir(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2829{
2830 /** @todo machine check. */
2831 return VINF_SUCCESS;
2832}
2833
2834
2835/** @callback_method_impl{FNCPUMRDMSR} */
2836static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuNameN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2837{
2838 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), pRange->uValue / 2 + 0x80000001, 0);
2839 if (pLeaf)
2840 {
2841 if (!(pRange->uValue & 1))
2842 *puValue = RT_MAKE_U64(pLeaf->uEax, pLeaf->uEbx);
2843 else
2844 *puValue = RT_MAKE_U64(pLeaf->uEcx, pLeaf->uEdx);
2845 }
2846 else
2847 *puValue = 0;
2848 return VINF_SUCCESS;
2849}
2850
2851
2852/** @callback_method_impl{FNCPUMWRMSR} */
2853static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuNameN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2854{
2855 /** @todo Remember guest programmed CPU name. */
2856 return VINF_SUCCESS;
2857}
2858
2859
2860/** @callback_method_impl{FNCPUMRDMSR} */
2861static DECLCALLBACK(int) cpumMsrRd_AmdK8HwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2862{
2863 /** @todo AMD HTC. */
2864 *puValue = pRange->uValue;
2865 return VINF_SUCCESS;
2866}
2867
2868
2869/** @callback_method_impl{FNCPUMWRMSR} */
2870static DECLCALLBACK(int) cpumMsrWr_AmdK8HwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2871{
2872 /** @todo AMD HTC. */
2873 return VINF_SUCCESS;
2874}
2875
2876
2877/** @callback_method_impl{FNCPUMRDMSR} */
2878static DECLCALLBACK(int) cpumMsrRd_AmdK8SwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2879{
2880 /** @todo AMD STC. */
2881 *puValue = 0;
2882 return VINF_SUCCESS;
2883}
2884
2885
2886/** @callback_method_impl{FNCPUMWRMSR} */
2887static DECLCALLBACK(int) cpumMsrWr_AmdK8SwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2888{
2889 /** @todo AMD STC. */
2890 return VINF_SUCCESS;
2891}
2892
2893
2894/** @callback_method_impl{FNCPUMRDMSR} */
2895static DECLCALLBACK(int) cpumMsrRd_AmdK8FidVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2896{
2897 /** @todo AMD FIDVID_CTL. */
2898 *puValue = pRange->uValue;
2899 return VINF_SUCCESS;
2900}
2901
2902
2903/** @callback_method_impl{FNCPUMWRMSR} */
2904static DECLCALLBACK(int) cpumMsrWr_AmdK8FidVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2905{
2906 /** @todo AMD FIDVID_CTL. */
2907 return VINF_SUCCESS;
2908}
2909
2910
2911/** @callback_method_impl{FNCPUMRDMSR} */
2912static DECLCALLBACK(int) cpumMsrRd_AmdK8FidVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2913{
2914 /** @todo AMD FIDVID_STATUS. */
2915 *puValue = pRange->uValue;
2916 return VINF_SUCCESS;
2917}
2918
2919
2920/** @callback_method_impl{FNCPUMRDMSR} */
2921static DECLCALLBACK(int) cpumMsrRd_AmdK8McCtlMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2922{
2923 /** @todo AMD MC. */
2924 *puValue = 0;
2925 return VINF_SUCCESS;
2926}
2927
2928
2929/** @callback_method_impl{FNCPUMWRMSR} */
2930static DECLCALLBACK(int) cpumMsrWr_AmdK8McCtlMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2931{
2932 /** @todo AMD MC. */
2933 return VINF_SUCCESS;
2934}
2935
2936
2937/** @callback_method_impl{FNCPUMRDMSR} */
2938static DECLCALLBACK(int) cpumMsrRd_AmdK8SmiOnIoTrapN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2939{
2940 /** @todo AMD SMM/SMI and I/O trap. */
2941 *puValue = 0;
2942 return VINF_SUCCESS;
2943}
2944
2945
2946/** @callback_method_impl{FNCPUMWRMSR} */
2947static DECLCALLBACK(int) cpumMsrWr_AmdK8SmiOnIoTrapN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2948{
2949 /** @todo AMD SMM/SMI and I/O trap. */
2950 return VINF_SUCCESS;
2951}
2952
2953
2954/** @callback_method_impl{FNCPUMRDMSR} */
2955static DECLCALLBACK(int) cpumMsrRd_AmdK8SmiOnIoTrapCtlSts(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2956{
2957 /** @todo AMD SMM/SMI and I/O trap. */
2958 *puValue = 0;
2959 return VINF_SUCCESS;
2960}
2961
2962
2963/** @callback_method_impl{FNCPUMWRMSR} */
2964static DECLCALLBACK(int) cpumMsrWr_AmdK8SmiOnIoTrapCtlSts(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2965{
2966 /** @todo AMD SMM/SMI and I/O trap. */
2967 return VINF_SUCCESS;
2968}
2969
2970
2971/** @callback_method_impl{FNCPUMRDMSR} */
2972static DECLCALLBACK(int) cpumMsrRd_AmdK8IntPendingMessage(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2973{
2974 /** @todo Interrupt pending message. */
2975 *puValue = 0;
2976 return VINF_SUCCESS;
2977}
2978
2979
2980/** @callback_method_impl{FNCPUMWRMSR} */
2981static DECLCALLBACK(int) cpumMsrWr_AmdK8IntPendingMessage(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2982{
2983 /** @todo Interrupt pending message. */
2984 return VINF_SUCCESS;
2985}
2986
2987
2988/** @callback_method_impl{FNCPUMRDMSR} */
2989static DECLCALLBACK(int) cpumMsrRd_AmdK8SmiTriggerIoCycle(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2990{
2991 /** @todo AMD SMM/SMI and trigger I/O cycle. */
2992 *puValue = 0;
2993 return VINF_SUCCESS;
2994}
2995
2996
2997/** @callback_method_impl{FNCPUMWRMSR} */
2998static DECLCALLBACK(int) cpumMsrWr_AmdK8SmiTriggerIoCycle(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2999{
3000 /** @todo AMD SMM/SMI and trigger I/O cycle. */
3001 return VINF_SUCCESS;
3002}
3003
3004
3005/** @callback_method_impl{FNCPUMRDMSR} */
3006static DECLCALLBACK(int) cpumMsrRd_AmdFam10hMmioCfgBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3007{
3008 /** @todo AMD MMIO Configuration base address. */
3009 *puValue = 0;
3010 return VINF_SUCCESS;
3011}
3012
3013
3014/** @callback_method_impl{FNCPUMWRMSR} */
3015static DECLCALLBACK(int) cpumMsrWr_AmdFam10hMmioCfgBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3016{
3017 /** @todo AMD MMIO Configuration base address. */
3018 return VINF_SUCCESS;
3019}
3020
3021
3022/** @callback_method_impl{FNCPUMRDMSR} */
3023static DECLCALLBACK(int) cpumMsrRd_AmdFam10hTrapCtlMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3024{
3025 /** @todo AMD 0xc0010059. */
3026 *puValue = 0;
3027 return VINF_SUCCESS;
3028}
3029
3030
3031/** @callback_method_impl{FNCPUMWRMSR} */
3032static DECLCALLBACK(int) cpumMsrWr_AmdFam10hTrapCtlMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3033{
3034 /** @todo AMD 0xc0010059. */
3035 return VINF_SUCCESS;
3036}
3037
3038
3039/** @callback_method_impl{FNCPUMRDMSR} */
3040static DECLCALLBACK(int) cpumMsrRd_AmdFam10hPStateCurLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3041{
3042 /** @todo AMD P-states. */
3043 *puValue = pRange->uValue;
3044 return VINF_SUCCESS;
3045}
3046
3047
3048/** @callback_method_impl{FNCPUMRDMSR} */
3049static DECLCALLBACK(int) cpumMsrRd_AmdFam10hPStateControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3050{
3051 /** @todo AMD P-states. */
3052 *puValue = pRange->uValue;
3053 return VINF_SUCCESS;
3054}
3055
3056
3057/** @callback_method_impl{FNCPUMWRMSR} */
3058static DECLCALLBACK(int) cpumMsrWr_AmdFam10hPStateControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3059{
3060 /** @todo AMD P-states. */
3061 return VINF_SUCCESS;
3062}
3063
3064
3065/** @callback_method_impl{FNCPUMRDMSR} */
3066static DECLCALLBACK(int) cpumMsrRd_AmdFam10hPStateStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3067{
3068 /** @todo AMD P-states. */
3069 *puValue = pRange->uValue;
3070 return VINF_SUCCESS;
3071}
3072
3073
3074/** @callback_method_impl{FNCPUMWRMSR} */
3075static DECLCALLBACK(int) cpumMsrWr_AmdFam10hPStateStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3076{
3077 /** @todo AMD P-states. */
3078 return VINF_SUCCESS;
3079}
3080
3081
3082/** @callback_method_impl{FNCPUMRDMSR} */
3083static DECLCALLBACK(int) cpumMsrRd_AmdFam10hPStateN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3084{
3085 /** @todo AMD P-states. */
3086 *puValue = pRange->uValue;
3087 return VINF_SUCCESS;
3088}
3089
3090
3091/** @callback_method_impl{FNCPUMWRMSR} */
3092static DECLCALLBACK(int) cpumMsrWr_AmdFam10hPStateN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3093{
3094 /** @todo AMD P-states. */
3095 return VINF_SUCCESS;
3096}
3097
3098
3099/** @callback_method_impl{FNCPUMRDMSR} */
3100static DECLCALLBACK(int) cpumMsrRd_AmdFam10hCofVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3101{
3102 /** @todo AMD P-states. */
3103 *puValue = pRange->uValue;
3104 return VINF_SUCCESS;
3105}
3106
3107
3108/** @callback_method_impl{FNCPUMWRMSR} */
3109static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCofVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3110{
3111 /** @todo AMD P-states. */
3112 return VINF_SUCCESS;
3113}
3114
3115
3116/** @callback_method_impl{FNCPUMRDMSR} */
3117static DECLCALLBACK(int) cpumMsrRd_AmdFam10hCofVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3118{
3119 /** @todo AMD P-states. */
3120 *puValue = pRange->uValue;
3121 return VINF_SUCCESS;
3122}
3123
3124
3125/** @callback_method_impl{FNCPUMWRMSR} */
3126static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCofVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3127{
3128 /* Note! Writing 0 seems to not GP, not sure if it does anything to the value... */
3129 /** @todo AMD P-states. */
3130 return VINF_SUCCESS;
3131}
3132
3133
3134/** @callback_method_impl{FNCPUMRDMSR} */
3135static DECLCALLBACK(int) cpumMsrRd_AmdFam10hCStateIoBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3136{
3137 /** @todo AMD C-states. */
3138 *puValue = 0;
3139 return VINF_SUCCESS;
3140}
3141
3142
3143/** @callback_method_impl{FNCPUMWRMSR} */
3144static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCStateIoBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3145{
3146 /** @todo AMD C-states. */
3147 return VINF_SUCCESS;
3148}
3149
3150
3151/** @callback_method_impl{FNCPUMRDMSR} */
3152static DECLCALLBACK(int) cpumMsrRd_AmdFam10hCpuWatchdogTimer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3153{
3154 /** @todo AMD machine checks. */
3155 *puValue = 0;
3156 return VINF_SUCCESS;
3157}
3158
3159
3160/** @callback_method_impl{FNCPUMWRMSR} */
3161static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCpuWatchdogTimer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3162{
3163 /** @todo AMD machine checks. */
3164 return VINF_SUCCESS;
3165}
3166
3167
3168/** @callback_method_impl{FNCPUMRDMSR} */
3169static DECLCALLBACK(int) cpumMsrRd_AmdK8SmmBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3170{
3171 /** @todo AMD SMM. */
3172 *puValue = 0;
3173 return VINF_SUCCESS;
3174}
3175
3176
3177/** @callback_method_impl{FNCPUMWRMSR} */
3178static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3179{
3180 /** @todo AMD SMM. */
3181 return VINF_SUCCESS;
3182}
3183
3184
3185/** @callback_method_impl{FNCPUMRDMSR} */
3186static DECLCALLBACK(int) cpumMsrRd_AmdK8SmmAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3187{
3188 /** @todo AMD SMM. */
3189 *puValue = 0;
3190 return VINF_SUCCESS;
3191}
3192
3193
3194/** @callback_method_impl{FNCPUMWRMSR} */
3195static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3196{
3197 /** @todo AMD SMM. */
3198 return VINF_SUCCESS;
3199}
3200
3201
3202
3203/** @callback_method_impl{FNCPUMRDMSR} */
3204static DECLCALLBACK(int) cpumMsrRd_AmdK8SmmMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3205{
3206 /** @todo AMD SMM. */
3207 *puValue = 0;
3208 return VINF_SUCCESS;
3209}
3210
3211
3212/** @callback_method_impl{FNCPUMWRMSR} */
3213static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3214{
3215 /** @todo AMD SMM. */
3216 return VINF_SUCCESS;
3217}
3218
3219
3220/** @callback_method_impl{FNCPUMRDMSR} */
3221static DECLCALLBACK(int) cpumMsrRd_AmdK8VmCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3222{
3223 /** @todo AMD SVM. */
3224 *puValue = 0;
3225 return VINF_SUCCESS;
3226}
3227
3228
3229/** @callback_method_impl{FNCPUMWRMSR} */
3230static DECLCALLBACK(int) cpumMsrWr_AmdK8VmCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3231{
3232 /** @todo AMD SVM. */
3233 return VINF_SUCCESS;
3234}
3235
3236
3237/** @callback_method_impl{FNCPUMRDMSR} */
3238static DECLCALLBACK(int) cpumMsrRd_AmdK8IgnNe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3239{
3240 /** @todo AMD IGNNE\# control. */
3241 *puValue = 0;
3242 return VINF_SUCCESS;
3243}
3244
3245
3246/** @callback_method_impl{FNCPUMWRMSR} */
3247static DECLCALLBACK(int) cpumMsrWr_AmdK8IgnNe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3248{
3249 /** @todo AMD IGNNE\# control. */
3250 return VINF_SUCCESS;
3251}
3252
3253
3254/** @callback_method_impl{FNCPUMRDMSR} */
3255static DECLCALLBACK(int) cpumMsrRd_AmdK8SmmCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3256{
3257 /** @todo AMD SMM. */
3258 *puValue = 0;
3259 return VINF_SUCCESS;
3260}
3261
3262
3263/** @callback_method_impl{FNCPUMWRMSR} */
3264static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3265{
3266 /** @todo AMD SMM. */
3267 return VINF_SUCCESS;
3268}
3269
3270
3271/** @callback_method_impl{FNCPUMRDMSR} */
3272static DECLCALLBACK(int) cpumMsrRd_AmdK8VmHSavePa(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3273{
3274 /** @todo AMD SVM. */
3275 *puValue = 0;
3276 return VINF_SUCCESS;
3277}
3278
3279
3280/** @callback_method_impl{FNCPUMWRMSR} */
3281static DECLCALLBACK(int) cpumMsrWr_AmdK8VmHSavePa(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3282{
3283 /** @todo AMD SVM. */
3284 return VINF_SUCCESS;
3285}
3286
3287
3288/** @callback_method_impl{FNCPUMRDMSR} */
3289static DECLCALLBACK(int) cpumMsrRd_AmdFam10hVmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3290{
3291 /** @todo AMD SVM. */
3292 *puValue = 0; /* RAZ */
3293 return VINF_SUCCESS;
3294}
3295
3296
3297/** @callback_method_impl{FNCPUMWRMSR} */
3298static DECLCALLBACK(int) cpumMsrWr_AmdFam10hVmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3299{
3300 /** @todo AMD SVM. */
3301 return VINF_SUCCESS;
3302}
3303
3304
3305/** @callback_method_impl{FNCPUMRDMSR} */
3306static DECLCALLBACK(int) cpumMsrRd_AmdFam10hSmmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3307{
3308 /** @todo AMD SMM. */
3309 *puValue = 0; /* RAZ */
3310 return VINF_SUCCESS;
3311}
3312
3313
3314/** @callback_method_impl{FNCPUMWRMSR} */
3315static DECLCALLBACK(int) cpumMsrWr_AmdFam10hSmmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3316{
3317 /** @todo AMD SMM. */
3318 return VINF_SUCCESS;
3319}
3320
3321
3322/** @callback_method_impl{FNCPUMRDMSR} */
3323static DECLCALLBACK(int) cpumMsrRd_AmdFam10hLocalSmiStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3324{
3325 /** @todo AMD SMM/SMI. */
3326 *puValue = 0;
3327 return VINF_SUCCESS;
3328}
3329
3330
3331/** @callback_method_impl{FNCPUMWRMSR} */
3332static DECLCALLBACK(int) cpumMsrWr_AmdFam10hLocalSmiStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3333{
3334 /** @todo AMD SMM/SMI. */
3335 return VINF_SUCCESS;
3336}
3337
3338
3339/** @callback_method_impl{FNCPUMRDMSR} */
3340static DECLCALLBACK(int) cpumMsrRd_AmdFam10hOsVisWrkIdLength(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3341{
3342 /** @todo AMD OS visible workaround. */
3343 *puValue = pRange->uValue;
3344 return VINF_SUCCESS;
3345}
3346
3347
3348/** @callback_method_impl{FNCPUMWRMSR} */
3349static DECLCALLBACK(int) cpumMsrWr_AmdFam10hOsVisWrkIdLength(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3350{
3351 /** @todo AMD OS visible workaround. */
3352 return VINF_SUCCESS;
3353}
3354
3355
3356/** @callback_method_impl{FNCPUMRDMSR} */
3357static DECLCALLBACK(int) cpumMsrRd_AmdFam10hOsVisWrkStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3358{
3359 /** @todo AMD OS visible workaround. */
3360 *puValue = 0;
3361 return VINF_SUCCESS;
3362}
3363
3364
3365/** @callback_method_impl{FNCPUMWRMSR} */
3366static DECLCALLBACK(int) cpumMsrWr_AmdFam10hOsVisWrkStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3367{
3368 /** @todo AMD OS visible workaround. */
3369 return VINF_SUCCESS;
3370}
3371
3372
3373/** @callback_method_impl{FNCPUMRDMSR} */
3374static DECLCALLBACK(int) cpumMsrRd_AmdFam16hL2IPerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3375{
3376 /** @todo AMD L2I performance counters. */
3377 *puValue = 0;
3378 return VINF_SUCCESS;
3379}
3380
3381
3382/** @callback_method_impl{FNCPUMWRMSR} */
3383static DECLCALLBACK(int) cpumMsrWr_AmdFam16hL2IPerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3384{
3385 /** @todo AMD L2I performance counters. */
3386 return VINF_SUCCESS;
3387}
3388
3389
3390/** @callback_method_impl{FNCPUMRDMSR} */
3391static DECLCALLBACK(int) cpumMsrRd_AmdFam16hL2IPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3392{
3393 /** @todo AMD L2I performance counters. */
3394 *puValue = 0;
3395 return VINF_SUCCESS;
3396}
3397
3398
3399/** @callback_method_impl{FNCPUMWRMSR} */
3400static DECLCALLBACK(int) cpumMsrWr_AmdFam16hL2IPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3401{
3402 /** @todo AMD L2I performance counters. */
3403 return VINF_SUCCESS;
3404}
3405
3406
3407/** @callback_method_impl{FNCPUMRDMSR} */
3408static DECLCALLBACK(int) cpumMsrRd_AmdFam15hNorthbridgePerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3409{
3410 /** @todo AMD Northbridge performance counters. */
3411 *puValue = 0;
3412 return VINF_SUCCESS;
3413}
3414
3415
3416/** @callback_method_impl{FNCPUMWRMSR} */
3417static DECLCALLBACK(int) cpumMsrWr_AmdFam15hNorthbridgePerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3418{
3419 /** @todo AMD Northbridge performance counters. */
3420 return VINF_SUCCESS;
3421}
3422
3423
3424/** @callback_method_impl{FNCPUMRDMSR} */
3425static DECLCALLBACK(int) cpumMsrRd_AmdFam15hNorthbridgePerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3426{
3427 /** @todo AMD Northbridge performance counters. */
3428 *puValue = 0;
3429 return VINF_SUCCESS;
3430}
3431
3432
3433/** @callback_method_impl{FNCPUMWRMSR} */
3434static DECLCALLBACK(int) cpumMsrWr_AmdFam15hNorthbridgePerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3435{
3436 /** @todo AMD Northbridge performance counters. */
3437 return VINF_SUCCESS;
3438}
3439
3440
3441/** @callback_method_impl{FNCPUMRDMSR} */
3442static DECLCALLBACK(int) cpumMsrRd_AmdK7MicrocodeCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3443{
3444 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3445 * cpus. Need to be explored and verify K7 presence. */
3446 /** @todo Undocumented register only seen mentioned in fam15h erratum \#608. */
3447 *puValue = pRange->uValue;
3448 return VINF_SUCCESS;
3449}
3450
3451
3452/** @callback_method_impl{FNCPUMWRMSR} */
3453static DECLCALLBACK(int) cpumMsrWr_AmdK7MicrocodeCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3454{
3455 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3456 * cpus. Need to be explored and verify K7 presence. */
3457 /** @todo Undocumented register only seen mentioned in fam15h erratum \#608. */
3458 return VINF_SUCCESS;
3459}
3460
3461
3462/** @callback_method_impl{FNCPUMRDMSR} */
3463static DECLCALLBACK(int) cpumMsrRd_AmdK7ClusterIdMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3464{
3465 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3466 * cpus. Need to be explored and verify K7 presence. */
3467 /** @todo Undocumented register only seen mentioned in fam16h BKDG r3.00 when
3468 * describing EBL_CR_POWERON. */
3469 *puValue = pRange->uValue;
3470 return VINF_SUCCESS;
3471}
3472
3473
3474/** @callback_method_impl{FNCPUMWRMSR} */
3475static DECLCALLBACK(int) cpumMsrWr_AmdK7ClusterIdMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3476{
3477 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3478 * cpus. Need to be explored and verify K7 presence. */
3479 /** @todo Undocumented register only seen mentioned in fam16h BKDG r3.00 when
3480 * describing EBL_CR_POWERON. */
3481 return VINF_SUCCESS;
3482}
3483
3484
3485/** @callback_method_impl{FNCPUMRDMSR} */
3486static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuIdCtlStd07hEbax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3487{
3488 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000007, 0);
3489 if (pLeaf)
3490 *puValue = RT_MAKE_U64(pLeaf->uEbx, pLeaf->uEax);
3491 else
3492 *puValue = 0;
3493 return VINF_SUCCESS;
3494}
3495
3496
3497/** @callback_method_impl{FNCPUMWRMSR} */
3498static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlStd07hEbax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3499{
3500 /** @todo Changing CPUID leaf 7/0. */
3501 return VINF_SUCCESS;
3502}
3503
3504
3505/** @callback_method_impl{FNCPUMRDMSR} */
3506static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuIdCtlStd06hEcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3507{
3508 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000006, 0);
3509 if (pLeaf)
3510 *puValue = pLeaf->uEcx;
3511 else
3512 *puValue = 0;
3513 return VINF_SUCCESS;
3514}
3515
3516
3517/** @callback_method_impl{FNCPUMWRMSR} */
3518static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlStd06hEcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3519{
3520 /** @todo Changing CPUID leaf 6. */
3521 return VINF_SUCCESS;
3522}
3523
3524
3525/** @callback_method_impl{FNCPUMRDMSR} */
3526static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuIdCtlStd01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3527{
3528 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000001, 0);
3529 if (pLeaf)
3530 *puValue = RT_MAKE_U64(pLeaf->uEdx, pLeaf->uEcx);
3531 else
3532 *puValue = 0;
3533 return VINF_SUCCESS;
3534}
3535
3536
3537/** @callback_method_impl{FNCPUMWRMSR} */
3538static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlStd01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3539{
3540 /** @todo Changing CPUID leaf 0x80000001. */
3541 return VINF_SUCCESS;
3542}
3543
3544
3545/** @callback_method_impl{FNCPUMRDMSR} */
3546static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuIdCtlExt01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3547{
3548 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x80000001, 0);
3549 if (pLeaf)
3550 *puValue = RT_MAKE_U64(pLeaf->uEdx, pLeaf->uEcx);
3551 else
3552 *puValue = 0;
3553 return VINF_SUCCESS;
3554}
3555
3556
3557/** @callback_method_impl{FNCPUMWRMSR} */
3558static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlExt01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3559{
3560 /** @todo Changing CPUID leaf 0x80000001. */
3561 return VINF_SUCCESS;
3562}
3563
3564
3565/** @callback_method_impl{FNCPUMRDMSR} */
3566static DECLCALLBACK(int) cpumMsrRd_AmdK8PatchLevel(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3567{
3568 /** @todo Fake AMD microcode patching. */
3569 *puValue = pRange->uValue;
3570 return VINF_SUCCESS;
3571}
3572
3573
3574/** @callback_method_impl{FNCPUMWRMSR} */
3575static DECLCALLBACK(int) cpumMsrWr_AmdK8PatchLoader(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3576{
3577 /** @todo Fake AMD microcode patching. */
3578 return VINF_SUCCESS;
3579}
3580
3581
3582/** @callback_method_impl{FNCPUMRDMSR} */
3583static DECLCALLBACK(int) cpumMsrRd_AmdK7DebugStatusMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3584{
3585 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3586 * cpus. Need to be explored and verify K7 presence. */
3587 /** @todo undocumented */
3588 *puValue = 0;
3589 return VINF_SUCCESS;
3590}
3591
3592
3593/** @callback_method_impl{FNCPUMWRMSR} */
3594static DECLCALLBACK(int) cpumMsrWr_AmdK7DebugStatusMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3595{
3596 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3597 * cpus. Need to be explored and verify K7 presence. */
3598 /** @todo undocumented */
3599 return VINF_SUCCESS;
3600}
3601
3602
3603/** @callback_method_impl{FNCPUMRDMSR} */
3604static DECLCALLBACK(int) cpumMsrRd_AmdK7BHTraceBaseMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3605{
3606 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3607 * cpus. Need to be explored and verify K7 presence. */
3608 /** @todo undocumented */
3609 *puValue = 0;
3610 return VINF_SUCCESS;
3611}
3612
3613
3614/** @callback_method_impl{FNCPUMWRMSR} */
3615static DECLCALLBACK(int) cpumMsrWr_AmdK7BHTraceBaseMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3616{
3617 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3618 * cpus. Need to be explored and verify K7 presence. */
3619 /** @todo undocumented */
3620 return VINF_SUCCESS;
3621}
3622
3623
3624/** @callback_method_impl{FNCPUMRDMSR} */
3625static DECLCALLBACK(int) cpumMsrRd_AmdK7BHTracePtrMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3626{
3627 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3628 * cpus. Need to be explored and verify K7 presence. */
3629 /** @todo undocumented */
3630 *puValue = 0;
3631 return VINF_SUCCESS;
3632}
3633
3634
3635/** @callback_method_impl{FNCPUMWRMSR} */
3636static DECLCALLBACK(int) cpumMsrWr_AmdK7BHTracePtrMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3637{
3638 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3639 * cpus. Need to be explored and verify K7 presence. */
3640 /** @todo undocumented */
3641 return VINF_SUCCESS;
3642}
3643
3644
3645/** @callback_method_impl{FNCPUMRDMSR} */
3646static DECLCALLBACK(int) cpumMsrRd_AmdK7BHTraceLimitMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3647{
3648 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3649 * cpus. Need to be explored and verify K7 presence. */
3650 /** @todo undocumented */
3651 *puValue = 0;
3652 return VINF_SUCCESS;
3653}
3654
3655
3656/** @callback_method_impl{FNCPUMWRMSR} */
3657static DECLCALLBACK(int) cpumMsrWr_AmdK7BHTraceLimitMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3658{
3659 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3660 * cpus. Need to be explored and verify K7 presence. */
3661 /** @todo undocumented */
3662 return VINF_SUCCESS;
3663}
3664
3665
3666/** @callback_method_impl{FNCPUMRDMSR} */
3667static DECLCALLBACK(int) cpumMsrRd_AmdK7HardwareDebugToolCfgMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3668{
3669 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3670 * cpus. Need to be explored and verify K7 presence. */
3671 /** @todo undocumented */
3672 *puValue = 0;
3673 return VINF_SUCCESS;
3674}
3675
3676
3677/** @callback_method_impl{FNCPUMWRMSR} */
3678static DECLCALLBACK(int) cpumMsrWr_AmdK7HardwareDebugToolCfgMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3679{
3680 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3681 * cpus. Need to be explored and verify K7 presence. */
3682 /** @todo undocumented */
3683 return VINF_SUCCESS;
3684}
3685
3686
3687/** @callback_method_impl{FNCPUMRDMSR} */
3688static DECLCALLBACK(int) cpumMsrRd_AmdK7FastFlushCountMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3689{
3690 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3691 * cpus. Need to be explored and verify K7 presence. */
3692 /** @todo undocumented */
3693 *puValue = 0;
3694 return VINF_SUCCESS;
3695}
3696
3697
3698/** @callback_method_impl{FNCPUMWRMSR} */
3699static DECLCALLBACK(int) cpumMsrWr_AmdK7FastFlushCountMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3700{
3701 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3702 * cpus. Need to be explored and verify K7 presence. */
3703 /** @todo undocumented */
3704 return VINF_SUCCESS;
3705}
3706
3707
3708/** @callback_method_impl{FNCPUMRDMSR} */
3709static DECLCALLBACK(int) cpumMsrRd_AmdK7NodeId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3710{
3711 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3712 * cpus. Need to be explored and verify K7 presence. */
3713 /** @todo AMD node ID and bios scratch. */
3714 *puValue = 0; /* nodeid = 0; nodes-per-cpu = 1 */
3715 return VINF_SUCCESS;
3716}
3717
3718
3719/** @callback_method_impl{FNCPUMWRMSR} */
3720static DECLCALLBACK(int) cpumMsrWr_AmdK7NodeId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3721{
3722 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3723 * cpus. Need to be explored and verify K7 presence. */
3724 /** @todo AMD node ID and bios scratch. */
3725 return VINF_SUCCESS;
3726}
3727
3728
3729/** @callback_method_impl{FNCPUMRDMSR} */
3730static DECLCALLBACK(int) cpumMsrRd_AmdK7DrXAddrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3731{
3732 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3733 * cpus. Need to be explored and verify K7 presence. */
3734 /** @todo AMD DRx address masking (range breakpoints). */
3735 *puValue = 0;
3736 return VINF_SUCCESS;
3737}
3738
3739
3740/** @callback_method_impl{FNCPUMWRMSR} */
3741static DECLCALLBACK(int) cpumMsrWr_AmdK7DrXAddrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3742{
3743 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3744 * cpus. Need to be explored and verify K7 presence. */
3745 /** @todo AMD DRx address masking (range breakpoints). */
3746 return VINF_SUCCESS;
3747}
3748
3749
3750/** @callback_method_impl{FNCPUMRDMSR} */
3751static DECLCALLBACK(int) cpumMsrRd_AmdK7Dr0DataMatchMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3752{
3753 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3754 * cpus. Need to be explored and verify K7 presence. */
3755 /** @todo AMD undocument debugging features. */
3756 *puValue = 0;
3757 return VINF_SUCCESS;
3758}
3759
3760
3761/** @callback_method_impl{FNCPUMWRMSR} */
3762static DECLCALLBACK(int) cpumMsrWr_AmdK7Dr0DataMatchMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3763{
3764 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3765 * cpus. Need to be explored and verify K7 presence. */
3766 /** @todo AMD undocument debugging features. */
3767 return VINF_SUCCESS;
3768}
3769
3770
3771/** @callback_method_impl{FNCPUMRDMSR} */
3772static DECLCALLBACK(int) cpumMsrRd_AmdK7Dr0DataMaskMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3773{
3774 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3775 * cpus. Need to be explored and verify K7 presence. */
3776 /** @todo AMD undocument debugging features. */
3777 *puValue = 0;
3778 return VINF_SUCCESS;
3779}
3780
3781
3782/** @callback_method_impl{FNCPUMWRMSR} */
3783static DECLCALLBACK(int) cpumMsrWr_AmdK7Dr0DataMaskMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3784{
3785 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3786 * cpus. Need to be explored and verify K7 presence. */
3787 /** @todo AMD undocument debugging features. */
3788 return VINF_SUCCESS;
3789}
3790
3791
3792/** @callback_method_impl{FNCPUMRDMSR} */
3793static DECLCALLBACK(int) cpumMsrRd_AmdK7LoadStoreCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3794{
3795 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3796 * cpus. Need to be explored and verify K7 presence. */
3797 /** @todo AMD load-store config. */
3798 *puValue = 0;
3799 return VINF_SUCCESS;
3800}
3801
3802
3803/** @callback_method_impl{FNCPUMWRMSR} */
3804static DECLCALLBACK(int) cpumMsrWr_AmdK7LoadStoreCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3805{
3806 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3807 * cpus. Need to be explored and verify K7 presence. */
3808 /** @todo AMD load-store config. */
3809 return VINF_SUCCESS;
3810}
3811
3812
3813/** @callback_method_impl{FNCPUMRDMSR} */
3814static DECLCALLBACK(int) cpumMsrRd_AmdK7InstrCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3815{
3816 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3817 * cpus. Need to be explored and verify K7 presence. */
3818 /** @todo AMD instruction cache config. */
3819 *puValue = 0;
3820 return VINF_SUCCESS;
3821}
3822
3823
3824/** @callback_method_impl{FNCPUMWRMSR} */
3825static DECLCALLBACK(int) cpumMsrWr_AmdK7InstrCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3826{
3827 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3828 * cpus. Need to be explored and verify K7 presence. */
3829 /** @todo AMD instruction cache config. */
3830 return VINF_SUCCESS;
3831}
3832
3833
3834/** @callback_method_impl{FNCPUMRDMSR} */
3835static DECLCALLBACK(int) cpumMsrRd_AmdK7DataCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3836{
3837 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3838 * cpus. Need to be explored and verify K7 presence. */
3839 /** @todo AMD data cache config. */
3840 *puValue = 0;
3841 return VINF_SUCCESS;
3842}
3843
3844
3845/** @callback_method_impl{FNCPUMWRMSR} */
3846static DECLCALLBACK(int) cpumMsrWr_AmdK7DataCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3847{
3848 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3849 * cpus. Need to be explored and verify K7 presence. */
3850 /** @todo AMD data cache config. */
3851 return VINF_SUCCESS;
3852}
3853
3854
3855/** @callback_method_impl{FNCPUMRDMSR} */
3856static DECLCALLBACK(int) cpumMsrRd_AmdK7BusUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3857{
3858 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3859 * cpus. Need to be explored and verify K7 presence. */
3860 /** @todo AMD bus unit config. */
3861 *puValue = 0;
3862 return VINF_SUCCESS;
3863}
3864
3865
3866/** @callback_method_impl{FNCPUMWRMSR} */
3867static DECLCALLBACK(int) cpumMsrWr_AmdK7BusUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3868{
3869 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3870 * cpus. Need to be explored and verify K7 presence. */
3871 /** @todo AMD bus unit config. */
3872 return VINF_SUCCESS;
3873}
3874
3875
3876/** @callback_method_impl{FNCPUMRDMSR} */
3877static DECLCALLBACK(int) cpumMsrRd_AmdK7DebugCtl2Maybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3878{
3879 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3880 * cpus. Need to be explored and verify K7 presence. */
3881 /** @todo Undocument AMD debug control register \#2. */
3882 *puValue = 0;
3883 return VINF_SUCCESS;
3884}
3885
3886
3887/** @callback_method_impl{FNCPUMWRMSR} */
3888static DECLCALLBACK(int) cpumMsrWr_AmdK7DebugCtl2Maybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3889{
3890 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3891 * cpus. Need to be explored and verify K7 presence. */
3892 /** @todo Undocument AMD debug control register \#2. */
3893 return VINF_SUCCESS;
3894}
3895
3896
3897/** @callback_method_impl{FNCPUMRDMSR} */
3898static DECLCALLBACK(int) cpumMsrRd_AmdFam15hFpuCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3899{
3900 /** @todo AMD FPU config. */
3901 *puValue = 0;
3902 return VINF_SUCCESS;
3903}
3904
3905
3906/** @callback_method_impl{FNCPUMWRMSR} */
3907static DECLCALLBACK(int) cpumMsrWr_AmdFam15hFpuCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3908{
3909 /** @todo AMD FPU config. */
3910 return VINF_SUCCESS;
3911}
3912
3913
3914/** @callback_method_impl{FNCPUMRDMSR} */
3915static DECLCALLBACK(int) cpumMsrRd_AmdFam15hDecoderCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3916{
3917 /** @todo AMD decoder config. */
3918 *puValue = 0;
3919 return VINF_SUCCESS;
3920}
3921
3922
3923/** @callback_method_impl{FNCPUMWRMSR} */
3924static DECLCALLBACK(int) cpumMsrWr_AmdFam15hDecoderCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3925{
3926 /** @todo AMD decoder config. */
3927 return VINF_SUCCESS;
3928}
3929
3930
3931/** @callback_method_impl{FNCPUMRDMSR} */
3932static DECLCALLBACK(int) cpumMsrRd_AmdFam10hBusUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3933{
3934 /* Note! 10h and 16h */
3935 /** @todo AMD bus unit config. */
3936 *puValue = 0;
3937 return VINF_SUCCESS;
3938}
3939
3940
3941/** @callback_method_impl{FNCPUMWRMSR} */
3942static DECLCALLBACK(int) cpumMsrWr_AmdFam10hBusUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3943{
3944 /* Note! 10h and 16h */
3945 /** @todo AMD bus unit config. */
3946 return VINF_SUCCESS;
3947}
3948
3949
3950/** @callback_method_impl{FNCPUMRDMSR} */
3951static DECLCALLBACK(int) cpumMsrRd_AmdFam15hCombUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3952{
3953 /** @todo AMD unit config. */
3954 *puValue = 0;
3955 return VINF_SUCCESS;
3956}
3957
3958
3959/** @callback_method_impl{FNCPUMWRMSR} */
3960static DECLCALLBACK(int) cpumMsrWr_AmdFam15hCombUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3961{
3962 /** @todo AMD unit config. */
3963 return VINF_SUCCESS;
3964}
3965
3966
3967/** @callback_method_impl{FNCPUMRDMSR} */
3968static DECLCALLBACK(int) cpumMsrRd_AmdFam15hCombUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3969{
3970 /** @todo AMD unit config 2. */
3971 *puValue = 0;
3972 return VINF_SUCCESS;
3973}
3974
3975
3976/** @callback_method_impl{FNCPUMWRMSR} */
3977static DECLCALLBACK(int) cpumMsrWr_AmdFam15hCombUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3978{
3979 /** @todo AMD unit config 2. */
3980 return VINF_SUCCESS;
3981}
3982
3983
3984/** @callback_method_impl{FNCPUMRDMSR} */
3985static DECLCALLBACK(int) cpumMsrRd_AmdFam15hCombUnitCfg3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3986{
3987 /** @todo AMD combined unit config 3. */
3988 *puValue = 0;
3989 return VINF_SUCCESS;
3990}
3991
3992
3993/** @callback_method_impl{FNCPUMWRMSR} */
3994static DECLCALLBACK(int) cpumMsrWr_AmdFam15hCombUnitCfg3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3995{
3996 /** @todo AMD combined unit config 3. */
3997 return VINF_SUCCESS;
3998}
3999
4000
4001/** @callback_method_impl{FNCPUMRDMSR} */
4002static DECLCALLBACK(int) cpumMsrRd_AmdFam15hExecUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4003{
4004 /** @todo AMD execution unit config. */
4005 *puValue = 0;
4006 return VINF_SUCCESS;
4007}
4008
4009
4010/** @callback_method_impl{FNCPUMWRMSR} */
4011static DECLCALLBACK(int) cpumMsrWr_AmdFam15hExecUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4012{
4013 /** @todo AMD execution unit config. */
4014 return VINF_SUCCESS;
4015}
4016
4017
4018/** @callback_method_impl{FNCPUMRDMSR} */
4019static DECLCALLBACK(int) cpumMsrRd_AmdFam15hLoadStoreCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4020{
4021 /** @todo AMD load-store config 2. */
4022 *puValue = 0;
4023 return VINF_SUCCESS;
4024}
4025
4026
4027/** @callback_method_impl{FNCPUMWRMSR} */
4028static DECLCALLBACK(int) cpumMsrWr_AmdFam15hLoadStoreCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4029{
4030 /** @todo AMD load-store config 2. */
4031 return VINF_SUCCESS;
4032}
4033
4034
4035/** @callback_method_impl{FNCPUMRDMSR} */
4036static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsFetchCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4037{
4038 /** @todo AMD IBS. */
4039 *puValue = 0;
4040 return VINF_SUCCESS;
4041}
4042
4043
4044/** @callback_method_impl{FNCPUMWRMSR} */
4045static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsFetchCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4046{
4047 /** @todo AMD IBS. */
4048 return VINF_SUCCESS;
4049}
4050
4051
4052/** @callback_method_impl{FNCPUMRDMSR} */
4053static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsFetchLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4054{
4055 /** @todo AMD IBS. */
4056 *puValue = 0;
4057 return VINF_SUCCESS;
4058}
4059
4060
4061/** @callback_method_impl{FNCPUMWRMSR} */
4062static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsFetchLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4063{
4064 /** @todo AMD IBS. */
4065 return VINF_SUCCESS;
4066}
4067
4068
4069/** @callback_method_impl{FNCPUMRDMSR} */
4070static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsFetchPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4071{
4072 /** @todo AMD IBS. */
4073 *puValue = 0;
4074 return VINF_SUCCESS;
4075}
4076
4077
4078/** @callback_method_impl{FNCPUMWRMSR} */
4079static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsFetchPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4080{
4081 /** @todo AMD IBS. */
4082 return VINF_SUCCESS;
4083}
4084
4085
4086/** @callback_method_impl{FNCPUMRDMSR} */
4087static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpExecCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4088{
4089 /** @todo AMD IBS. */
4090 *puValue = 0;
4091 return VINF_SUCCESS;
4092}
4093
4094
4095/** @callback_method_impl{FNCPUMWRMSR} */
4096static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpExecCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4097{
4098 /** @todo AMD IBS. */
4099 return VINF_SUCCESS;
4100}
4101
4102
4103/** @callback_method_impl{FNCPUMRDMSR} */
4104static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpRip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4105{
4106 /** @todo AMD IBS. */
4107 *puValue = 0;
4108 return VINF_SUCCESS;
4109}
4110
4111
4112/** @callback_method_impl{FNCPUMWRMSR} */
4113static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpRip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4114{
4115 /** @todo AMD IBS. */
4116 if (!X86_IS_CANONICAL(uValue))
4117 {
4118 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
4119 return VERR_CPUM_RAISE_GP_0;
4120 }
4121 return VINF_SUCCESS;
4122}
4123
4124
4125/** @callback_method_impl{FNCPUMRDMSR} */
4126static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpData(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4127{
4128 /** @todo AMD IBS. */
4129 *puValue = 0;
4130 return VINF_SUCCESS;
4131}
4132
4133
4134/** @callback_method_impl{FNCPUMWRMSR} */
4135static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpData(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4136{
4137 /** @todo AMD IBS. */
4138 return VINF_SUCCESS;
4139}
4140
4141
4142/** @callback_method_impl{FNCPUMRDMSR} */
4143static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpData2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4144{
4145 /** @todo AMD IBS. */
4146 *puValue = 0;
4147 return VINF_SUCCESS;
4148}
4149
4150
4151/** @callback_method_impl{FNCPUMWRMSR} */
4152static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpData2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4153{
4154 /** @todo AMD IBS. */
4155 return VINF_SUCCESS;
4156}
4157
4158
4159/** @callback_method_impl{FNCPUMRDMSR} */
4160static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpData3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4161{
4162 /** @todo AMD IBS. */
4163 *puValue = 0;
4164 return VINF_SUCCESS;
4165}
4166
4167
4168/** @callback_method_impl{FNCPUMWRMSR} */
4169static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpData3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4170{
4171 /** @todo AMD IBS. */
4172 return VINF_SUCCESS;
4173}
4174
4175
4176/** @callback_method_impl{FNCPUMRDMSR} */
4177static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsDcLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4178{
4179 /** @todo AMD IBS. */
4180 *puValue = 0;
4181 return VINF_SUCCESS;
4182}
4183
4184
4185/** @callback_method_impl{FNCPUMWRMSR} */
4186static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsDcLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4187{
4188 /** @todo AMD IBS. */
4189 if (!X86_IS_CANONICAL(uValue))
4190 {
4191 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
4192 return VERR_CPUM_RAISE_GP_0;
4193 }
4194 return VINF_SUCCESS;
4195}
4196
4197
4198/** @callback_method_impl{FNCPUMRDMSR} */
4199static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsDcPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4200{
4201 /** @todo AMD IBS. */
4202 *puValue = 0;
4203 return VINF_SUCCESS;
4204}
4205
4206
4207/** @callback_method_impl{FNCPUMWRMSR} */
4208static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsDcPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4209{
4210 /** @todo AMD IBS. */
4211 return VINF_SUCCESS;
4212}
4213
4214
4215/** @callback_method_impl{FNCPUMRDMSR} */
4216static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4217{
4218 /** @todo AMD IBS. */
4219 *puValue = 0;
4220 return VINF_SUCCESS;
4221}
4222
4223
4224/** @callback_method_impl{FNCPUMWRMSR} */
4225static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4226{
4227 /** @todo AMD IBS. */
4228 return VINF_SUCCESS;
4229}
4230
4231
4232/** @callback_method_impl{FNCPUMRDMSR} */
4233static DECLCALLBACK(int) cpumMsrRd_AmdFam14hIbsBrTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4234{
4235 /** @todo AMD IBS. */
4236 *puValue = 0;
4237 return VINF_SUCCESS;
4238}
4239
4240
4241/** @callback_method_impl{FNCPUMWRMSR} */
4242static DECLCALLBACK(int) cpumMsrWr_AmdFam14hIbsBrTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4243{
4244 /** @todo AMD IBS. */
4245 if (!X86_IS_CANONICAL(uValue))
4246 {
4247 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
4248 return VERR_CPUM_RAISE_GP_0;
4249 }
4250 return VINF_SUCCESS;
4251}
4252
4253
4254
4255/**
4256 * MSR read function table.
4257 */
4258static const PFNCPUMRDMSR g_aCpumRdMsrFns[kCpumMsrRdFn_End] =
4259{
4260 NULL, /* Invalid */
4261 cpumMsrRd_FixedValue,
4262 NULL, /* Alias */
4263 cpumMsrRd_WriteOnly,
4264 cpumMsrRd_Ia32P5McAddr,
4265 cpumMsrRd_Ia32P5McType,
4266 cpumMsrRd_Ia32TimestampCounter,
4267 cpumMsrRd_Ia32ApicBase,
4268 cpumMsrRd_Ia32FeatureControl,
4269 cpumMsrRd_Ia32BiosSignId,
4270 cpumMsrRd_Ia32SmmMonitorCtl,
4271 cpumMsrRd_Ia32PmcN,
4272 cpumMsrRd_Ia32MonitorFilterLineSize,
4273 cpumMsrRd_Ia32MPerf,
4274 cpumMsrRd_Ia32APerf,
4275 cpumMsrRd_Ia32MtrrCap,
4276 cpumMsrRd_Ia32MtrrPhysBaseN,
4277 cpumMsrRd_Ia32MtrrPhysMaskN,
4278 cpumMsrRd_Ia32MtrrFixed,
4279 cpumMsrRd_Ia32MtrrDefType,
4280 cpumMsrRd_Ia32Pat,
4281 cpumMsrRd_Ia32SysEnterCs,
4282 cpumMsrRd_Ia32SysEnterEsp,
4283 cpumMsrRd_Ia32SysEnterEip,
4284 cpumMsrRd_Ia32McgCap,
4285 cpumMsrRd_Ia32McgStatus,
4286 cpumMsrRd_Ia32McgCtl,
4287 cpumMsrRd_Ia32DebugCtl,
4288 cpumMsrRd_Ia32SmrrPhysBase,
4289 cpumMsrRd_Ia32SmrrPhysMask,
4290 cpumMsrRd_Ia32PlatformDcaCap,
4291 cpumMsrRd_Ia32CpuDcaCap,
4292 cpumMsrRd_Ia32Dca0Cap,
4293 cpumMsrRd_Ia32PerfEvtSelN,
4294 cpumMsrRd_Ia32PerfStatus,
4295 cpumMsrRd_Ia32PerfCtl,
4296 cpumMsrRd_Ia32FixedCtrN,
4297 cpumMsrRd_Ia32PerfCapabilities,
4298 cpumMsrRd_Ia32FixedCtrCtrl,
4299 cpumMsrRd_Ia32PerfGlobalStatus,
4300 cpumMsrRd_Ia32PerfGlobalCtrl,
4301 cpumMsrRd_Ia32PerfGlobalOvfCtrl,
4302 cpumMsrRd_Ia32PebsEnable,
4303 cpumMsrRd_Ia32ClockModulation,
4304 cpumMsrRd_Ia32ThermInterrupt,
4305 cpumMsrRd_Ia32ThermStatus,
4306 cpumMsrRd_Ia32Therm2Ctl,
4307 cpumMsrRd_Ia32MiscEnable,
4308 cpumMsrRd_Ia32McCtlStatusAddrMiscN,
4309 cpumMsrRd_Ia32McNCtl2,
4310 cpumMsrRd_Ia32DsArea,
4311 cpumMsrRd_Ia32TscDeadline,
4312 cpumMsrRd_Ia32X2ApicN,
4313 cpumMsrRd_Ia32DebugInterface,
4314 cpumMsrRd_Ia32VmxBase,
4315 cpumMsrRd_Ia32VmxPinbasedCtls,
4316 cpumMsrRd_Ia32VmxProcbasedCtls,
4317 cpumMsrRd_Ia32VmxExitCtls,
4318 cpumMsrRd_Ia32VmxEntryCtls,
4319 cpumMsrRd_Ia32VmxMisc,
4320 cpumMsrRd_Ia32VmxCr0Fixed0,
4321 cpumMsrRd_Ia32VmxCr0Fixed1,
4322 cpumMsrRd_Ia32VmxCr4Fixed0,
4323 cpumMsrRd_Ia32VmxCr4Fixed1,
4324 cpumMsrRd_Ia32VmxVmcsEnum,
4325 cpumMsrRd_Ia32VmxProcBasedCtls2,
4326 cpumMsrRd_Ia32VmxEptVpidCap,
4327 cpumMsrRd_Ia32VmxTruePinbasedCtls,
4328 cpumMsrRd_Ia32VmxTrueProcbasedCtls,
4329 cpumMsrRd_Ia32VmxTrueExitCtls,
4330 cpumMsrRd_Ia32VmxTrueEntryCtls,
4331
4332 cpumMsrRd_Amd64Efer,
4333 cpumMsrRd_Amd64SyscallTarget,
4334 cpumMsrRd_Amd64LongSyscallTarget,
4335 cpumMsrRd_Amd64CompSyscallTarget,
4336 cpumMsrRd_Amd64SyscallFlagMask,
4337 cpumMsrRd_Amd64FsBase,
4338 cpumMsrRd_Amd64GsBase,
4339 cpumMsrRd_Amd64KernelGsBase,
4340 cpumMsrRd_Amd64TscAux,
4341
4342 cpumMsrRd_IntelEblCrPowerOn,
4343 cpumMsrRd_IntelP4EbcHardPowerOn,
4344 cpumMsrRd_IntelP4EbcSoftPowerOn,
4345 cpumMsrRd_IntelP4EbcFrequencyId,
4346 cpumMsrRd_IntelPlatformInfo100MHz,
4347 cpumMsrRd_IntelPlatformInfo133MHz,
4348 cpumMsrRd_IntelPkgCStConfigControl,
4349 cpumMsrRd_IntelPmgIoCaptureBase,
4350 cpumMsrRd_IntelLastBranchFromToN,
4351 cpumMsrRd_IntelLastBranchFromN,
4352 cpumMsrRd_IntelLastBranchToN,
4353 cpumMsrRd_IntelLastBranchTos,
4354 cpumMsrRd_IntelBblCrCtl,
4355 cpumMsrRd_IntelBblCrCtl3,
4356 cpumMsrRd_IntelI7TemperatureTarget,
4357 cpumMsrRd_IntelI7MsrOffCoreResponseN,
4358 cpumMsrRd_IntelI7MiscPwrMgmt,
4359 cpumMsrRd_IntelP6CrN,
4360 cpumMsrRd_IntelCpuId1FeatureMaskEcdx,
4361 cpumMsrRd_IntelCpuId1FeatureMaskEax,
4362 cpumMsrRd_IntelCpuId80000001FeatureMaskEcdx,
4363 cpumMsrRd_IntelI7SandyAesNiCtl,
4364 cpumMsrRd_IntelI7TurboRatioLimit,
4365 cpumMsrRd_IntelI7LbrSelect,
4366 cpumMsrRd_IntelI7SandyErrorControl,
4367 cpumMsrRd_IntelI7VirtualLegacyWireCap,
4368 cpumMsrRd_IntelI7PowerCtl,
4369 cpumMsrRd_IntelI7SandyPebsNumAlt,
4370 cpumMsrRd_IntelI7PebsLdLat,
4371 cpumMsrRd_IntelI7PkgCnResidencyN,
4372 cpumMsrRd_IntelI7CoreCnResidencyN,
4373 cpumMsrRd_IntelI7SandyVrCurrentConfig,
4374 cpumMsrRd_IntelI7SandyVrMiscConfig,
4375 cpumMsrRd_IntelI7SandyRaplPowerUnit,
4376 cpumMsrRd_IntelI7SandyPkgCnIrtlN,
4377 cpumMsrRd_IntelI7SandyPkgC2Residency,
4378 cpumMsrRd_IntelI7RaplPkgPowerLimit,
4379 cpumMsrRd_IntelI7RaplPkgEnergyStatus,
4380 cpumMsrRd_IntelI7RaplPkgPerfStatus,
4381 cpumMsrRd_IntelI7RaplPkgPowerInfo,
4382 cpumMsrRd_IntelI7RaplDramPowerLimit,
4383 cpumMsrRd_IntelI7RaplDramEnergyStatus,
4384 cpumMsrRd_IntelI7RaplDramPerfStatus,
4385 cpumMsrRd_IntelI7RaplDramPowerInfo,
4386 cpumMsrRd_IntelI7RaplPp0PowerLimit,
4387 cpumMsrRd_IntelI7RaplPp0EnergyStatus,
4388 cpumMsrRd_IntelI7RaplPp0Policy,
4389 cpumMsrRd_IntelI7RaplPp0PerfStatus,
4390 cpumMsrRd_IntelI7RaplPp1PowerLimit,
4391 cpumMsrRd_IntelI7RaplPp1EnergyStatus,
4392 cpumMsrRd_IntelI7RaplPp1Policy,
4393 cpumMsrRd_IntelI7IvyConfigTdpNominal,
4394 cpumMsrRd_IntelI7IvyConfigTdpLevel1,
4395 cpumMsrRd_IntelI7IvyConfigTdpLevel2,
4396 cpumMsrRd_IntelI7IvyConfigTdpControl,
4397 cpumMsrRd_IntelI7IvyTurboActivationRatio,
4398 cpumMsrRd_IntelI7UncPerfGlobalCtrl,
4399 cpumMsrRd_IntelI7UncPerfGlobalStatus,
4400 cpumMsrRd_IntelI7UncPerfGlobalOvfCtrl,
4401 cpumMsrRd_IntelI7UncPerfFixedCtrCtrl,
4402 cpumMsrRd_IntelI7UncPerfFixedCtr,
4403 cpumMsrRd_IntelI7UncCBoxConfig,
4404 cpumMsrRd_IntelI7UncArbPerfCtrN,
4405 cpumMsrRd_IntelI7UncArbPerfEvtSelN,
4406 cpumMsrRd_IntelCore2EmttmCrTablesN,
4407 cpumMsrRd_IntelCore2SmmCStMiscInfo,
4408 cpumMsrRd_IntelCore1ExtConfig,
4409 cpumMsrRd_IntelCore1DtsCalControl,
4410 cpumMsrRd_IntelCore2PeciControl,
4411
4412 cpumMsrRd_P6LastBranchFromIp,
4413 cpumMsrRd_P6LastBranchToIp,
4414 cpumMsrRd_P6LastIntFromIp,
4415 cpumMsrRd_P6LastIntToIp,
4416
4417 cpumMsrRd_AmdFam15hTscRate,
4418 cpumMsrRd_AmdFam15hLwpCfg,
4419 cpumMsrRd_AmdFam15hLwpCbAddr,
4420 cpumMsrRd_AmdFam10hMc4MiscN,
4421 cpumMsrRd_AmdK8PerfCtlN,
4422 cpumMsrRd_AmdK8PerfCtrN,
4423 cpumMsrRd_AmdK8SysCfg,
4424 cpumMsrRd_AmdK8HwCr,
4425 cpumMsrRd_AmdK8IorrBaseN,
4426 cpumMsrRd_AmdK8IorrMaskN,
4427 cpumMsrRd_AmdK8TopOfMemN,
4428 cpumMsrRd_AmdK8NbCfg1,
4429 cpumMsrRd_AmdK8McXcptRedir,
4430 cpumMsrRd_AmdK8CpuNameN,
4431 cpumMsrRd_AmdK8HwThermalCtrl,
4432 cpumMsrRd_AmdK8SwThermalCtrl,
4433 cpumMsrRd_AmdK8FidVidControl,
4434 cpumMsrRd_AmdK8FidVidStatus,
4435 cpumMsrRd_AmdK8McCtlMaskN,
4436 cpumMsrRd_AmdK8SmiOnIoTrapN,
4437 cpumMsrRd_AmdK8SmiOnIoTrapCtlSts,
4438 cpumMsrRd_AmdK8IntPendingMessage,
4439 cpumMsrRd_AmdK8SmiTriggerIoCycle,
4440 cpumMsrRd_AmdFam10hMmioCfgBaseAddr,
4441 cpumMsrRd_AmdFam10hTrapCtlMaybe,
4442 cpumMsrRd_AmdFam10hPStateCurLimit,
4443 cpumMsrRd_AmdFam10hPStateControl,
4444 cpumMsrRd_AmdFam10hPStateStatus,
4445 cpumMsrRd_AmdFam10hPStateN,
4446 cpumMsrRd_AmdFam10hCofVidControl,
4447 cpumMsrRd_AmdFam10hCofVidStatus,
4448 cpumMsrRd_AmdFam10hCStateIoBaseAddr,
4449 cpumMsrRd_AmdFam10hCpuWatchdogTimer,
4450 cpumMsrRd_AmdK8SmmBase,
4451 cpumMsrRd_AmdK8SmmAddr,
4452 cpumMsrRd_AmdK8SmmMask,
4453 cpumMsrRd_AmdK8VmCr,
4454 cpumMsrRd_AmdK8IgnNe,
4455 cpumMsrRd_AmdK8SmmCtl,
4456 cpumMsrRd_AmdK8VmHSavePa,
4457 cpumMsrRd_AmdFam10hVmLockKey,
4458 cpumMsrRd_AmdFam10hSmmLockKey,
4459 cpumMsrRd_AmdFam10hLocalSmiStatus,
4460 cpumMsrRd_AmdFam10hOsVisWrkIdLength,
4461 cpumMsrRd_AmdFam10hOsVisWrkStatus,
4462 cpumMsrRd_AmdFam16hL2IPerfCtlN,
4463 cpumMsrRd_AmdFam16hL2IPerfCtrN,
4464 cpumMsrRd_AmdFam15hNorthbridgePerfCtlN,
4465 cpumMsrRd_AmdFam15hNorthbridgePerfCtrN,
4466 cpumMsrRd_AmdK7MicrocodeCtl,
4467 cpumMsrRd_AmdK7ClusterIdMaybe,
4468 cpumMsrRd_AmdK8CpuIdCtlStd07hEbax,
4469 cpumMsrRd_AmdK8CpuIdCtlStd06hEcx,
4470 cpumMsrRd_AmdK8CpuIdCtlStd01hEdcx,
4471 cpumMsrRd_AmdK8CpuIdCtlExt01hEdcx,
4472 cpumMsrRd_AmdK8PatchLevel,
4473 cpumMsrRd_AmdK7DebugStatusMaybe,
4474 cpumMsrRd_AmdK7BHTraceBaseMaybe,
4475 cpumMsrRd_AmdK7BHTracePtrMaybe,
4476 cpumMsrRd_AmdK7BHTraceLimitMaybe,
4477 cpumMsrRd_AmdK7HardwareDebugToolCfgMaybe,
4478 cpumMsrRd_AmdK7FastFlushCountMaybe,
4479 cpumMsrRd_AmdK7NodeId,
4480 cpumMsrRd_AmdK7DrXAddrMaskN,
4481 cpumMsrRd_AmdK7Dr0DataMatchMaybe,
4482 cpumMsrRd_AmdK7Dr0DataMaskMaybe,
4483 cpumMsrRd_AmdK7LoadStoreCfg,
4484 cpumMsrRd_AmdK7InstrCacheCfg,
4485 cpumMsrRd_AmdK7DataCacheCfg,
4486 cpumMsrRd_AmdK7BusUnitCfg,
4487 cpumMsrRd_AmdK7DebugCtl2Maybe,
4488 cpumMsrRd_AmdFam15hFpuCfg,
4489 cpumMsrRd_AmdFam15hDecoderCfg,
4490 cpumMsrRd_AmdFam10hBusUnitCfg2,
4491 cpumMsrRd_AmdFam15hCombUnitCfg,
4492 cpumMsrRd_AmdFam15hCombUnitCfg2,
4493 cpumMsrRd_AmdFam15hCombUnitCfg3,
4494 cpumMsrRd_AmdFam15hExecUnitCfg,
4495 cpumMsrRd_AmdFam15hLoadStoreCfg2,
4496 cpumMsrRd_AmdFam10hIbsFetchCtl,
4497 cpumMsrRd_AmdFam10hIbsFetchLinAddr,
4498 cpumMsrRd_AmdFam10hIbsFetchPhysAddr,
4499 cpumMsrRd_AmdFam10hIbsOpExecCtl,
4500 cpumMsrRd_AmdFam10hIbsOpRip,
4501 cpumMsrRd_AmdFam10hIbsOpData,
4502 cpumMsrRd_AmdFam10hIbsOpData2,
4503 cpumMsrRd_AmdFam10hIbsOpData3,
4504 cpumMsrRd_AmdFam10hIbsDcLinAddr,
4505 cpumMsrRd_AmdFam10hIbsDcPhysAddr,
4506 cpumMsrRd_AmdFam10hIbsCtl,
4507 cpumMsrRd_AmdFam14hIbsBrTarget,
4508};
4509
4510
4511/**
4512 * MSR write function table.
4513 */
4514static const PFNCPUMWRMSR g_aCpumWrMsrFns[kCpumMsrWrFn_End] =
4515{
4516 NULL, /* Invalid */
4517 cpumMsrWr_IgnoreWrite,
4518 cpumMsrWr_ReadOnly,
4519 NULL, /* Alias */
4520 cpumMsrWr_Ia32P5McAddr,
4521 cpumMsrWr_Ia32P5McType,
4522 cpumMsrWr_Ia32TimestampCounter,
4523 cpumMsrWr_Ia32ApicBase,
4524 cpumMsrWr_Ia32FeatureControl,
4525 cpumMsrWr_Ia32BiosSignId,
4526 cpumMsrWr_Ia32BiosUpdateTrigger,
4527 cpumMsrWr_Ia32SmmMonitorCtl,
4528 cpumMsrWr_Ia32PmcN,
4529 cpumMsrWr_Ia32MonitorFilterLineSize,
4530 cpumMsrWr_Ia32MPerf,
4531 cpumMsrWr_Ia32APerf,
4532 cpumMsrWr_Ia32MtrrPhysBaseN,
4533 cpumMsrWr_Ia32MtrrPhysMaskN,
4534 cpumMsrWr_Ia32MtrrFixed,
4535 cpumMsrWr_Ia32MtrrDefType,
4536 cpumMsrWr_Ia32Pat,
4537 cpumMsrWr_Ia32SysEnterCs,
4538 cpumMsrWr_Ia32SysEnterEsp,
4539 cpumMsrWr_Ia32SysEnterEip,
4540 cpumMsrWr_Ia32McgStatus,
4541 cpumMsrWr_Ia32McgCtl,
4542 cpumMsrWr_Ia32DebugCtl,
4543 cpumMsrWr_Ia32SmrrPhysBase,
4544 cpumMsrWr_Ia32SmrrPhysMask,
4545 cpumMsrWr_Ia32PlatformDcaCap,
4546 cpumMsrWr_Ia32Dca0Cap,
4547 cpumMsrWr_Ia32PerfEvtSelN,
4548 cpumMsrWr_Ia32PerfStatus,
4549 cpumMsrWr_Ia32PerfCtl,
4550 cpumMsrWr_Ia32FixedCtrN,
4551 cpumMsrWr_Ia32PerfCapabilities,
4552 cpumMsrWr_Ia32FixedCtrCtrl,
4553 cpumMsrWr_Ia32PerfGlobalStatus,
4554 cpumMsrWr_Ia32PerfGlobalCtrl,
4555 cpumMsrWr_Ia32PerfGlobalOvfCtrl,
4556 cpumMsrWr_Ia32PebsEnable,
4557 cpumMsrWr_Ia32ClockModulation,
4558 cpumMsrWr_Ia32ThermInterrupt,
4559 cpumMsrWr_Ia32ThermStatus,
4560 cpumMsrWr_Ia32Therm2Ctl,
4561 cpumMsrWr_Ia32MiscEnable,
4562 cpumMsrWr_Ia32McCtlStatusAddrMiscN,
4563 cpumMsrWr_Ia32McNCtl2,
4564 cpumMsrWr_Ia32DsArea,
4565 cpumMsrWr_Ia32TscDeadline,
4566 cpumMsrWr_Ia32X2ApicN,
4567 cpumMsrWr_Ia32DebugInterface,
4568
4569 cpumMsrWr_Amd64Efer,
4570 cpumMsrWr_Amd64SyscallTarget,
4571 cpumMsrWr_Amd64LongSyscallTarget,
4572 cpumMsrWr_Amd64CompSyscallTarget,
4573 cpumMsrWr_Amd64SyscallFlagMask,
4574 cpumMsrWr_Amd64FsBase,
4575 cpumMsrWr_Amd64GsBase,
4576 cpumMsrWr_Amd64KernelGsBase,
4577 cpumMsrWr_Amd64TscAux,
4578
4579 cpumMsrWr_IntelEblCrPowerOn,
4580 cpumMsrWr_IntelP4EbcHardPowerOn,
4581 cpumMsrWr_IntelP4EbcSoftPowerOn,
4582 cpumMsrWr_IntelP4EbcFrequencyId,
4583 cpumMsrWr_IntelPkgCStConfigControl,
4584 cpumMsrWr_IntelPmgIoCaptureBase,
4585 cpumMsrWr_IntelLastBranchFromToN,
4586 cpumMsrWr_IntelLastBranchFromN,
4587 cpumMsrWr_IntelLastBranchToN,
4588 cpumMsrWr_IntelLastBranchTos,
4589 cpumMsrWr_IntelBblCrCtl,
4590 cpumMsrWr_IntelBblCrCtl3,
4591 cpumMsrWr_IntelI7TemperatureTarget,
4592 cpumMsrWr_IntelI7MsrOffCoreResponseN,
4593 cpumMsrWr_IntelI7MiscPwrMgmt,
4594 cpumMsrWr_IntelP6CrN,
4595 cpumMsrWr_IntelCpuId1FeatureMaskEcdx,
4596 cpumMsrWr_IntelCpuId1FeatureMaskEax,
4597 cpumMsrWr_IntelCpuId80000001FeatureMaskEcdx,
4598 cpumMsrWr_IntelI7SandyAesNiCtl,
4599 cpumMsrWr_IntelI7TurboRatioLimit,
4600 cpumMsrWr_IntelI7LbrSelect,
4601 cpumMsrWr_IntelI7SandyErrorControl,
4602 cpumMsrWr_IntelI7PowerCtl,
4603 cpumMsrWr_IntelI7SandyPebsNumAlt,
4604 cpumMsrWr_IntelI7PebsLdLat,
4605 cpumMsrWr_IntelI7SandyVrCurrentConfig,
4606 cpumMsrWr_IntelI7SandyVrMiscConfig,
4607 cpumMsrWr_IntelI7SandyPkgCnIrtlN,
4608 cpumMsrWr_IntelI7RaplPkgPowerLimit,
4609 cpumMsrWr_IntelI7RaplDramPowerLimit,
4610 cpumMsrWr_IntelI7RaplPp0PowerLimit,
4611 cpumMsrWr_IntelI7RaplPp0Policy,
4612 cpumMsrWr_IntelI7RaplPp1PowerLimit,
4613 cpumMsrWr_IntelI7RaplPp1Policy,
4614 cpumMsrWr_IntelI7IvyConfigTdpControl,
4615 cpumMsrWr_IntelI7IvyTurboActivationRatio,
4616 cpumMsrWr_IntelI7UncPerfGlobalCtrl,
4617 cpumMsrWr_IntelI7UncPerfGlobalStatus,
4618 cpumMsrWr_IntelI7UncPerfGlobalOvfCtrl,
4619 cpumMsrWr_IntelI7UncPerfFixedCtrCtrl,
4620 cpumMsrWr_IntelI7UncPerfFixedCtr,
4621 cpumMsrWr_IntelI7UncArbPerfCtrN,
4622 cpumMsrWr_IntelI7UncArbPerfEvtSelN,
4623 cpumMsrWr_IntelCore2EmttmCrTablesN,
4624 cpumMsrWr_IntelCore2SmmCStMiscInfo,
4625 cpumMsrWr_IntelCore1ExtConfig,
4626 cpumMsrWr_IntelCore1DtsCalControl,
4627 cpumMsrWr_IntelCore2PeciControl,
4628
4629 cpumMsrWr_P6LastIntFromIp,
4630 cpumMsrWr_P6LastIntToIp,
4631
4632 cpumMsrWr_AmdFam15hTscRate,
4633 cpumMsrWr_AmdFam15hLwpCfg,
4634 cpumMsrWr_AmdFam15hLwpCbAddr,
4635 cpumMsrWr_AmdFam10hMc4MiscN,
4636 cpumMsrWr_AmdK8PerfCtlN,
4637 cpumMsrWr_AmdK8PerfCtrN,
4638 cpumMsrWr_AmdK8SysCfg,
4639 cpumMsrWr_AmdK8HwCr,
4640 cpumMsrWr_AmdK8IorrBaseN,
4641 cpumMsrWr_AmdK8IorrMaskN,
4642 cpumMsrWr_AmdK8TopOfMemN,
4643 cpumMsrWr_AmdK8NbCfg1,
4644 cpumMsrWr_AmdK8McXcptRedir,
4645 cpumMsrWr_AmdK8CpuNameN,
4646 cpumMsrWr_AmdK8HwThermalCtrl,
4647 cpumMsrWr_AmdK8SwThermalCtrl,
4648 cpumMsrWr_AmdK8FidVidControl,
4649 cpumMsrWr_AmdK8McCtlMaskN,
4650 cpumMsrWr_AmdK8SmiOnIoTrapN,
4651 cpumMsrWr_AmdK8SmiOnIoTrapCtlSts,
4652 cpumMsrWr_AmdK8IntPendingMessage,
4653 cpumMsrWr_AmdK8SmiTriggerIoCycle,
4654 cpumMsrWr_AmdFam10hMmioCfgBaseAddr,
4655 cpumMsrWr_AmdFam10hTrapCtlMaybe,
4656 cpumMsrWr_AmdFam10hPStateControl,
4657 cpumMsrWr_AmdFam10hPStateStatus,
4658 cpumMsrWr_AmdFam10hPStateN,
4659 cpumMsrWr_AmdFam10hCofVidControl,
4660 cpumMsrWr_AmdFam10hCofVidStatus,
4661 cpumMsrWr_AmdFam10hCStateIoBaseAddr,
4662 cpumMsrWr_AmdFam10hCpuWatchdogTimer,
4663 cpumMsrWr_AmdK8SmmBase,
4664 cpumMsrWr_AmdK8SmmAddr,
4665 cpumMsrWr_AmdK8SmmMask,
4666 cpumMsrWr_AmdK8VmCr,
4667 cpumMsrWr_AmdK8IgnNe,
4668 cpumMsrWr_AmdK8SmmCtl,
4669 cpumMsrWr_AmdK8VmHSavePa,
4670 cpumMsrWr_AmdFam10hVmLockKey,
4671 cpumMsrWr_AmdFam10hSmmLockKey,
4672 cpumMsrWr_AmdFam10hLocalSmiStatus,
4673 cpumMsrWr_AmdFam10hOsVisWrkIdLength,
4674 cpumMsrWr_AmdFam10hOsVisWrkStatus,
4675 cpumMsrWr_AmdFam16hL2IPerfCtlN,
4676 cpumMsrWr_AmdFam16hL2IPerfCtrN,
4677 cpumMsrWr_AmdFam15hNorthbridgePerfCtlN,
4678 cpumMsrWr_AmdFam15hNorthbridgePerfCtrN,
4679 cpumMsrWr_AmdK7MicrocodeCtl,
4680 cpumMsrWr_AmdK7ClusterIdMaybe,
4681 cpumMsrWr_AmdK8CpuIdCtlStd07hEbax,
4682 cpumMsrWr_AmdK8CpuIdCtlStd06hEcx,
4683 cpumMsrWr_AmdK8CpuIdCtlStd01hEdcx,
4684 cpumMsrWr_AmdK8CpuIdCtlExt01hEdcx,
4685 cpumMsrWr_AmdK8PatchLoader,
4686 cpumMsrWr_AmdK7DebugStatusMaybe,
4687 cpumMsrWr_AmdK7BHTraceBaseMaybe,
4688 cpumMsrWr_AmdK7BHTracePtrMaybe,
4689 cpumMsrWr_AmdK7BHTraceLimitMaybe,
4690 cpumMsrWr_AmdK7HardwareDebugToolCfgMaybe,
4691 cpumMsrWr_AmdK7FastFlushCountMaybe,
4692 cpumMsrWr_AmdK7NodeId,
4693 cpumMsrWr_AmdK7DrXAddrMaskN,
4694 cpumMsrWr_AmdK7Dr0DataMatchMaybe,
4695 cpumMsrWr_AmdK7Dr0DataMaskMaybe,
4696 cpumMsrWr_AmdK7LoadStoreCfg,
4697 cpumMsrWr_AmdK7InstrCacheCfg,
4698 cpumMsrWr_AmdK7DataCacheCfg,
4699 cpumMsrWr_AmdK7BusUnitCfg,
4700 cpumMsrWr_AmdK7DebugCtl2Maybe,
4701 cpumMsrWr_AmdFam15hFpuCfg,
4702 cpumMsrWr_AmdFam15hDecoderCfg,
4703 cpumMsrWr_AmdFam10hBusUnitCfg2,
4704 cpumMsrWr_AmdFam15hCombUnitCfg,
4705 cpumMsrWr_AmdFam15hCombUnitCfg2,
4706 cpumMsrWr_AmdFam15hCombUnitCfg3,
4707 cpumMsrWr_AmdFam15hExecUnitCfg,
4708 cpumMsrWr_AmdFam15hLoadStoreCfg2,
4709 cpumMsrWr_AmdFam10hIbsFetchCtl,
4710 cpumMsrWr_AmdFam10hIbsFetchLinAddr,
4711 cpumMsrWr_AmdFam10hIbsFetchPhysAddr,
4712 cpumMsrWr_AmdFam10hIbsOpExecCtl,
4713 cpumMsrWr_AmdFam10hIbsOpRip,
4714 cpumMsrWr_AmdFam10hIbsOpData,
4715 cpumMsrWr_AmdFam10hIbsOpData2,
4716 cpumMsrWr_AmdFam10hIbsOpData3,
4717 cpumMsrWr_AmdFam10hIbsDcLinAddr,
4718 cpumMsrWr_AmdFam10hIbsDcPhysAddr,
4719 cpumMsrWr_AmdFam10hIbsCtl,
4720 cpumMsrWr_AmdFam14hIbsBrTarget,
4721};
4722
4723
4724/**
4725 * Looks up the range for the given MSR.
4726 *
4727 * @returns Pointer to the range if found, NULL if not.
4728 * @param pVM The cross context VM structure.
4729 * @param idMsr The MSR to look up.
4730 */
4731# ifndef IN_RING3
4732static
4733# endif
4734PCPUMMSRRANGE cpumLookupMsrRange(PVM pVM, uint32_t idMsr)
4735{
4736 /*
4737 * Binary lookup.
4738 */
4739 uint32_t cRanges = pVM->cpum.s.GuestInfo.cMsrRanges;
4740 if (!cRanges)
4741 return NULL;
4742 PCPUMMSRRANGE paRanges = pVM->cpum.s.GuestInfo.CTX_SUFF(paMsrRanges);
4743 for (;;)
4744 {
4745 uint32_t i = cRanges / 2;
4746 if (idMsr < paRanges[i].uFirst)
4747 {
4748 if (i == 0)
4749 break;
4750 cRanges = i;
4751 }
4752 else if (idMsr > paRanges[i].uLast)
4753 {
4754 i++;
4755 if (i >= cRanges)
4756 break;
4757 cRanges -= i;
4758 paRanges = &paRanges[i];
4759 }
4760 else
4761 {
4762 if (paRanges[i].enmRdFn == kCpumMsrRdFn_MsrAlias)
4763 return cpumLookupMsrRange(pVM, paRanges[i].uValue);
4764 return &paRanges[i];
4765 }
4766 }
4767
4768# ifdef VBOX_STRICT
4769 /*
4770 * Linear lookup to verify the above binary search.
4771 */
4772 uint32_t cLeft = pVM->cpum.s.GuestInfo.cMsrRanges;
4773 PCPUMMSRRANGE pCur = pVM->cpum.s.GuestInfo.CTX_SUFF(paMsrRanges);
4774 while (cLeft-- > 0)
4775 {
4776 if (idMsr >= pCur->uFirst && idMsr <= pCur->uLast)
4777 {
4778 AssertFailed();
4779 if (pCur->enmRdFn == kCpumMsrRdFn_MsrAlias)
4780 return cpumLookupMsrRange(pVM, pCur->uValue);
4781 return pCur;
4782 }
4783 pCur++;
4784 }
4785# endif
4786 return NULL;
4787}
4788
4789#ifdef VBOX_WITH_NEW_MSR_CODE
4790
4791/**
4792 * Query a guest MSR.
4793 *
4794 * The caller is responsible for checking privilege if the call is the result of
4795 * a RDMSR instruction. We'll do the rest.
4796 *
4797 * @retval VINF_SUCCESS on success.
4798 * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR), the caller is
4799 * expected to take the appropriate actions. @a *puValue is set to 0.
4800 * @param pVCpu Pointer to the VMCPU.
4801 * @param idMsr The MSR.
4802 * @param puValue Where to return the value.
4803 *
4804 * @remarks This will always return the right values, even when we're in the
4805 * recompiler.
4806 */
4807VMMDECL(int) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue)
4808{
4809 *puValue = 0;
4810
4811 int rc;
4812 PVM pVM = pVCpu->CTX_SUFF(pVM);
4813 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, idMsr);
4814 if (pRange)
4815 {
4816 CPUMMSRRDFN enmRdFn = (CPUMMSRRDFN)pRange->enmRdFn;
4817 AssertReturn(enmRdFn > kCpumMsrRdFn_Invalid && enmRdFn < kCpumMsrRdFn_End, VERR_CPUM_IPE_1);
4818
4819 PFNCPUMRDMSR pfnRdMsr = g_aCpumRdMsrFns[enmRdFn];
4820 AssertReturn(pfnRdMsr, VERR_CPUM_IPE_2);
4821
4822 STAM_COUNTER_INC(&pRange->cReads);
4823 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReads);
4824
4825 rc = pfnRdMsr(pVCpu, idMsr, pRange, puValue);
4826 if (RT_SUCCESS(rc))
4827 {
4828 Log2(("CPUM: RDMSR %#x (%s) -> %#llx\n", idMsr, pRange->szName, *puValue));
4829 AssertMsg(rc == VINF_SUCCESS, ("%Rrc idMsr=%#x\n", rc, idMsr));
4830 }
4831 else if (rc == VERR_CPUM_RAISE_GP_0)
4832 {
4833 Log(("CPUM: RDMSR %#x (%s) -> #GP(0)\n", idMsr, pRange->szName));
4834 STAM_COUNTER_INC(&pRange->cGps);
4835 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReadsRaiseGp);
4836 }
4837 else
4838 Log(("CPUM: RDMSR %#x (%s) -> rc=%Rrc\n", idMsr, pRange->szName, rc));
4839 }
4840 else
4841 {
4842 Log(("CPUM: Unknown RDMSR %#x -> #GP(0)\n", idMsr));
4843 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReads);
4844 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReadsUnknown);
4845 rc = VERR_CPUM_RAISE_GP_0;
4846 }
4847 return rc;
4848}
4849
4850
4851/**
4852 * Writes to a guest MSR.
4853 *
4854 * The caller is responsible for checking privilege if the call is the result of
4855 * a WRMSR instruction. We'll do the rest.
4856 *
4857 * @retval VINF_SUCCESS on success.
4858 * @retval VERR_CPUM_RAISE_GP_0 on failure, the caller is expected to take the
4859 * appropriate actions.
4860 *
4861 * @param pVCpu Pointer to the VMCPU.
4862 * @param idMsr The MSR id.
4863 * @param uValue The value to set.
4864 *
4865 * @remarks Everyone changing MSR values, including the recompiler, shall do it
4866 * by calling this method. This makes sure we have current values and
4867 * that we trigger all the right actions when something changes.
4868 *
4869 * For performance reasons, this actually isn't entirely true for some
4870 * MSRs when in HM mode. The code here and in HM must be aware of
4871 * this.
4872 */
4873VMMDECL(int) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue)
4874{
4875 int rc;
4876 PVM pVM = pVCpu->CTX_SUFF(pVM);
4877 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, idMsr);
4878 if (pRange)
4879 {
4880 STAM_COUNTER_INC(&pRange->cWrites);
4881 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWrites);
4882
4883 if (!(uValue & pRange->fWrGpMask))
4884 {
4885 CPUMMSRWRFN enmWrFn = (CPUMMSRWRFN)pRange->enmWrFn;
4886 AssertReturn(enmWrFn > kCpumMsrWrFn_Invalid && enmWrFn < kCpumMsrWrFn_End, VERR_CPUM_IPE_1);
4887
4888 PFNCPUMWRMSR pfnWrMsr = g_aCpumWrMsrFns[enmWrFn];
4889 AssertReturn(pfnWrMsr, VERR_CPUM_IPE_2);
4890
4891 uint64_t uValueAdjusted = uValue & ~pRange->fWrIgnMask;
4892 if (uValueAdjusted != uValue)
4893 {
4894 STAM_COUNTER_INC(&pRange->cIgnoredBits);
4895 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesToIgnoredBits);
4896 }
4897
4898 rc = pfnWrMsr(pVCpu, idMsr, pRange, uValueAdjusted, uValue);
4899 if (RT_SUCCESS(rc))
4900 {
4901 Log2(("CPUM: WRMSR %#x (%s), %#llx [%#llx]\n", idMsr, pRange->szName, uValueAdjusted, uValue));
4902 AssertMsg(rc == VINF_SUCCESS, ("%Rrc idMsr=%#x\n", rc, idMsr));
4903 }
4904 else if (rc == VERR_CPUM_RAISE_GP_0)
4905 {
4906 Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> #GP(0)\n", idMsr, pRange->szName, uValueAdjusted, uValue));
4907 STAM_COUNTER_INC(&pRange->cGps);
4908 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesRaiseGp);
4909 }
4910 else
4911 Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> rc=%Rrc\n", idMsr, pRange->szName, uValueAdjusted, uValue, rc));
4912 }
4913 else
4914 {
4915 Log(("CPUM: WRMSR %#x (%s), %#llx -> #GP(0) - invalid bits %#llx\n",
4916 idMsr, pRange->szName, uValue, uValue & pRange->fWrGpMask));
4917 STAM_COUNTER_INC(&pRange->cGps);
4918 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesRaiseGp);
4919 rc = VERR_CPUM_RAISE_GP_0;
4920 }
4921 }
4922 else
4923 {
4924 Log(("CPUM: Unknown WRMSR %#x, %#llx -> #GP(0)\n", idMsr, uValue));
4925 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWrites);
4926 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesUnknown);
4927 rc = VERR_CPUM_RAISE_GP_0;
4928 }
4929 return rc;
4930}
4931
4932#endif /* VBOX_WITH_NEW_MSR_CODE */
4933
4934
4935#if defined(VBOX_STRICT) && defined(IN_RING3)
4936/**
4937 * Performs some checks on the static data related to MSRs.
4938 *
4939 * @returns VINF_SUCCESS on success, error on failure.
4940 */
4941int cpumR3MsrStrictInitChecks(void)
4942{
4943#define CPUM_ASSERT_RD_MSR_FN(a_Register) \
4944 AssertReturn(g_aCpumRdMsrFns[kCpumMsrRdFn_##a_Register] == cpumMsrRd_##a_Register, VERR_CPUM_IPE_2);
4945#define CPUM_ASSERT_WR_MSR_FN(a_Register) \
4946 AssertReturn(g_aCpumWrMsrFns[kCpumMsrWrFn_##a_Register] == cpumMsrWr_##a_Register, VERR_CPUM_IPE_2);
4947
4948 AssertReturn(g_aCpumRdMsrFns[kCpumMsrRdFn_Invalid] == NULL, VERR_CPUM_IPE_2);
4949 CPUM_ASSERT_RD_MSR_FN(FixedValue);
4950 CPUM_ASSERT_RD_MSR_FN(WriteOnly);
4951 CPUM_ASSERT_RD_MSR_FN(Ia32P5McAddr);
4952 CPUM_ASSERT_RD_MSR_FN(Ia32P5McType);
4953 CPUM_ASSERT_RD_MSR_FN(Ia32TimestampCounter);
4954 CPUM_ASSERT_RD_MSR_FN(Ia32ApicBase);
4955 CPUM_ASSERT_RD_MSR_FN(Ia32FeatureControl);
4956 CPUM_ASSERT_RD_MSR_FN(Ia32BiosSignId);
4957 CPUM_ASSERT_RD_MSR_FN(Ia32SmmMonitorCtl);
4958 CPUM_ASSERT_RD_MSR_FN(Ia32PmcN);
4959 CPUM_ASSERT_RD_MSR_FN(Ia32MonitorFilterLineSize);
4960 CPUM_ASSERT_RD_MSR_FN(Ia32MPerf);
4961 CPUM_ASSERT_RD_MSR_FN(Ia32APerf);
4962 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrCap);
4963 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrPhysBaseN);
4964 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrPhysMaskN);
4965 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrFixed);
4966 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrDefType);
4967 CPUM_ASSERT_RD_MSR_FN(Ia32Pat);
4968 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterCs);
4969 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterEsp);
4970 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterEip);
4971 CPUM_ASSERT_RD_MSR_FN(Ia32McgCap);
4972 CPUM_ASSERT_RD_MSR_FN(Ia32McgStatus);
4973 CPUM_ASSERT_RD_MSR_FN(Ia32McgCtl);
4974 CPUM_ASSERT_RD_MSR_FN(Ia32DebugCtl);
4975 CPUM_ASSERT_RD_MSR_FN(Ia32SmrrPhysBase);
4976 CPUM_ASSERT_RD_MSR_FN(Ia32SmrrPhysMask);
4977 CPUM_ASSERT_RD_MSR_FN(Ia32PlatformDcaCap);
4978 CPUM_ASSERT_RD_MSR_FN(Ia32CpuDcaCap);
4979 CPUM_ASSERT_RD_MSR_FN(Ia32Dca0Cap);
4980 CPUM_ASSERT_RD_MSR_FN(Ia32PerfEvtSelN);
4981 CPUM_ASSERT_RD_MSR_FN(Ia32PerfStatus);
4982 CPUM_ASSERT_RD_MSR_FN(Ia32PerfCtl);
4983 CPUM_ASSERT_RD_MSR_FN(Ia32FixedCtrN);
4984 CPUM_ASSERT_RD_MSR_FN(Ia32PerfCapabilities);
4985 CPUM_ASSERT_RD_MSR_FN(Ia32FixedCtrCtrl);
4986 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalStatus);
4987 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalCtrl);
4988 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalOvfCtrl);
4989 CPUM_ASSERT_RD_MSR_FN(Ia32PebsEnable);
4990 CPUM_ASSERT_RD_MSR_FN(Ia32ClockModulation);
4991 CPUM_ASSERT_RD_MSR_FN(Ia32ThermInterrupt);
4992 CPUM_ASSERT_RD_MSR_FN(Ia32ThermStatus);
4993 CPUM_ASSERT_RD_MSR_FN(Ia32MiscEnable);
4994 CPUM_ASSERT_RD_MSR_FN(Ia32McCtlStatusAddrMiscN);
4995 CPUM_ASSERT_RD_MSR_FN(Ia32McNCtl2);
4996 CPUM_ASSERT_RD_MSR_FN(Ia32DsArea);
4997 CPUM_ASSERT_RD_MSR_FN(Ia32TscDeadline);
4998 CPUM_ASSERT_RD_MSR_FN(Ia32X2ApicN);
4999 CPUM_ASSERT_RD_MSR_FN(Ia32DebugInterface);
5000 CPUM_ASSERT_RD_MSR_FN(Ia32VmxBase);
5001 CPUM_ASSERT_RD_MSR_FN(Ia32VmxPinbasedCtls);
5002 CPUM_ASSERT_RD_MSR_FN(Ia32VmxProcbasedCtls);
5003 CPUM_ASSERT_RD_MSR_FN(Ia32VmxExitCtls);
5004 CPUM_ASSERT_RD_MSR_FN(Ia32VmxEntryCtls);
5005 CPUM_ASSERT_RD_MSR_FN(Ia32VmxMisc);
5006 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr0Fixed0);
5007 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr0Fixed1);
5008 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr4Fixed0);
5009 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr4Fixed1);
5010 CPUM_ASSERT_RD_MSR_FN(Ia32VmxVmcsEnum);
5011 CPUM_ASSERT_RD_MSR_FN(Ia32VmxProcBasedCtls2);
5012 CPUM_ASSERT_RD_MSR_FN(Ia32VmxEptVpidCap);
5013 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTruePinbasedCtls);
5014 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueProcbasedCtls);
5015 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueExitCtls);
5016 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueEntryCtls);
5017
5018 CPUM_ASSERT_RD_MSR_FN(Amd64Efer);
5019 CPUM_ASSERT_RD_MSR_FN(Amd64SyscallTarget);
5020 CPUM_ASSERT_RD_MSR_FN(Amd64LongSyscallTarget);
5021 CPUM_ASSERT_RD_MSR_FN(Amd64CompSyscallTarget);
5022 CPUM_ASSERT_RD_MSR_FN(Amd64SyscallFlagMask);
5023 CPUM_ASSERT_RD_MSR_FN(Amd64FsBase);
5024 CPUM_ASSERT_RD_MSR_FN(Amd64GsBase);
5025 CPUM_ASSERT_RD_MSR_FN(Amd64KernelGsBase);
5026 CPUM_ASSERT_RD_MSR_FN(Amd64TscAux);
5027
5028 CPUM_ASSERT_RD_MSR_FN(IntelEblCrPowerOn);
5029 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcHardPowerOn);
5030 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcSoftPowerOn);
5031 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcFrequencyId);
5032 CPUM_ASSERT_RD_MSR_FN(IntelPlatformInfo100MHz);
5033 CPUM_ASSERT_RD_MSR_FN(IntelPlatformInfo133MHz);
5034 CPUM_ASSERT_RD_MSR_FN(IntelPkgCStConfigControl);
5035 CPUM_ASSERT_RD_MSR_FN(IntelPmgIoCaptureBase);
5036 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchFromToN);
5037 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchFromN);
5038 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchToN);
5039 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchTos);
5040 CPUM_ASSERT_RD_MSR_FN(IntelBblCrCtl);
5041 CPUM_ASSERT_RD_MSR_FN(IntelBblCrCtl3);
5042 CPUM_ASSERT_RD_MSR_FN(IntelI7TemperatureTarget);
5043 CPUM_ASSERT_RD_MSR_FN(IntelI7MsrOffCoreResponseN);
5044 CPUM_ASSERT_RD_MSR_FN(IntelI7MiscPwrMgmt);
5045 CPUM_ASSERT_RD_MSR_FN(IntelP6CrN);
5046 CPUM_ASSERT_RD_MSR_FN(IntelCpuId1FeatureMaskEcdx);
5047 CPUM_ASSERT_RD_MSR_FN(IntelCpuId1FeatureMaskEax);
5048 CPUM_ASSERT_RD_MSR_FN(IntelCpuId80000001FeatureMaskEcdx);
5049 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyAesNiCtl);
5050 CPUM_ASSERT_RD_MSR_FN(IntelI7TurboRatioLimit);
5051 CPUM_ASSERT_RD_MSR_FN(IntelI7LbrSelect);
5052 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyErrorControl);
5053 CPUM_ASSERT_RD_MSR_FN(IntelI7VirtualLegacyWireCap);
5054 CPUM_ASSERT_RD_MSR_FN(IntelI7PowerCtl);
5055 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPebsNumAlt);
5056 CPUM_ASSERT_RD_MSR_FN(IntelI7PebsLdLat);
5057 CPUM_ASSERT_RD_MSR_FN(IntelI7PkgCnResidencyN);
5058 CPUM_ASSERT_RD_MSR_FN(IntelI7CoreCnResidencyN);
5059 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyVrCurrentConfig);
5060 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyVrMiscConfig);
5061 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyRaplPowerUnit);
5062 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPkgCnIrtlN);
5063 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPkgC2Residency);
5064 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPowerLimit);
5065 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgEnergyStatus);
5066 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPerfStatus);
5067 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPowerInfo);
5068 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPowerLimit);
5069 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramEnergyStatus);
5070 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPerfStatus);
5071 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPowerInfo);
5072 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0PowerLimit);
5073 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0EnergyStatus);
5074 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0Policy);
5075 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0PerfStatus);
5076 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1PowerLimit);
5077 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1EnergyStatus);
5078 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1Policy);
5079 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpNominal);
5080 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpLevel1);
5081 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpLevel2);
5082 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpControl);
5083 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyTurboActivationRatio);
5084 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalCtrl);
5085 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalStatus);
5086 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalOvfCtrl);
5087 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfFixedCtrCtrl);
5088 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfFixedCtr);
5089 CPUM_ASSERT_RD_MSR_FN(IntelI7UncCBoxConfig);
5090 CPUM_ASSERT_RD_MSR_FN(IntelI7UncArbPerfCtrN);
5091 CPUM_ASSERT_RD_MSR_FN(IntelI7UncArbPerfEvtSelN);
5092 CPUM_ASSERT_RD_MSR_FN(IntelCore2EmttmCrTablesN);
5093 CPUM_ASSERT_RD_MSR_FN(IntelCore2SmmCStMiscInfo);
5094 CPUM_ASSERT_RD_MSR_FN(IntelCore1ExtConfig);
5095 CPUM_ASSERT_RD_MSR_FN(IntelCore1DtsCalControl);
5096 CPUM_ASSERT_RD_MSR_FN(IntelCore2PeciControl);
5097
5098 CPUM_ASSERT_RD_MSR_FN(P6LastBranchFromIp);
5099 CPUM_ASSERT_RD_MSR_FN(P6LastBranchToIp);
5100 CPUM_ASSERT_RD_MSR_FN(P6LastIntFromIp);
5101 CPUM_ASSERT_RD_MSR_FN(P6LastIntToIp);
5102
5103 CPUM_ASSERT_RD_MSR_FN(AmdFam15hTscRate);
5104 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLwpCfg);
5105 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLwpCbAddr);
5106 CPUM_ASSERT_RD_MSR_FN(AmdFam10hMc4MiscN);
5107 CPUM_ASSERT_RD_MSR_FN(AmdK8PerfCtlN);
5108 CPUM_ASSERT_RD_MSR_FN(AmdK8PerfCtrN);
5109 CPUM_ASSERT_RD_MSR_FN(AmdK8SysCfg);
5110 CPUM_ASSERT_RD_MSR_FN(AmdK8HwCr);
5111 CPUM_ASSERT_RD_MSR_FN(AmdK8IorrBaseN);
5112 CPUM_ASSERT_RD_MSR_FN(AmdK8IorrMaskN);
5113 CPUM_ASSERT_RD_MSR_FN(AmdK8TopOfMemN);
5114 CPUM_ASSERT_RD_MSR_FN(AmdK8NbCfg1);
5115 CPUM_ASSERT_RD_MSR_FN(AmdK8McXcptRedir);
5116 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuNameN);
5117 CPUM_ASSERT_RD_MSR_FN(AmdK8HwThermalCtrl);
5118 CPUM_ASSERT_RD_MSR_FN(AmdK8SwThermalCtrl);
5119 CPUM_ASSERT_RD_MSR_FN(AmdK8FidVidControl);
5120 CPUM_ASSERT_RD_MSR_FN(AmdK8FidVidStatus);
5121 CPUM_ASSERT_RD_MSR_FN(AmdK8McCtlMaskN);
5122 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiOnIoTrapN);
5123 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiOnIoTrapCtlSts);
5124 CPUM_ASSERT_RD_MSR_FN(AmdK8IntPendingMessage);
5125 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiTriggerIoCycle);
5126 CPUM_ASSERT_RD_MSR_FN(AmdFam10hMmioCfgBaseAddr);
5127 CPUM_ASSERT_RD_MSR_FN(AmdFam10hTrapCtlMaybe);
5128 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateCurLimit);
5129 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateControl);
5130 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateStatus);
5131 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateN);
5132 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCofVidControl);
5133 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCofVidStatus);
5134 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCStateIoBaseAddr);
5135 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCpuWatchdogTimer);
5136 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmBase);
5137 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmAddr);
5138 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmMask);
5139 CPUM_ASSERT_RD_MSR_FN(AmdK8VmCr);
5140 CPUM_ASSERT_RD_MSR_FN(AmdK8IgnNe);
5141 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmCtl);
5142 CPUM_ASSERT_RD_MSR_FN(AmdK8VmHSavePa);
5143 CPUM_ASSERT_RD_MSR_FN(AmdFam10hVmLockKey);
5144 CPUM_ASSERT_RD_MSR_FN(AmdFam10hSmmLockKey);
5145 CPUM_ASSERT_RD_MSR_FN(AmdFam10hLocalSmiStatus);
5146 CPUM_ASSERT_RD_MSR_FN(AmdFam10hOsVisWrkIdLength);
5147 CPUM_ASSERT_RD_MSR_FN(AmdFam10hOsVisWrkStatus);
5148 CPUM_ASSERT_RD_MSR_FN(AmdFam16hL2IPerfCtlN);
5149 CPUM_ASSERT_RD_MSR_FN(AmdFam16hL2IPerfCtrN);
5150 CPUM_ASSERT_RD_MSR_FN(AmdFam15hNorthbridgePerfCtlN);
5151 CPUM_ASSERT_RD_MSR_FN(AmdFam15hNorthbridgePerfCtrN);
5152 CPUM_ASSERT_RD_MSR_FN(AmdK7MicrocodeCtl);
5153 CPUM_ASSERT_RD_MSR_FN(AmdK7ClusterIdMaybe);
5154 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd07hEbax);
5155 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd06hEcx);
5156 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd01hEdcx);
5157 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlExt01hEdcx);
5158 CPUM_ASSERT_RD_MSR_FN(AmdK8PatchLevel);
5159 CPUM_ASSERT_RD_MSR_FN(AmdK7DebugStatusMaybe);
5160 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTraceBaseMaybe);
5161 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTracePtrMaybe);
5162 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTraceLimitMaybe);
5163 CPUM_ASSERT_RD_MSR_FN(AmdK7HardwareDebugToolCfgMaybe);
5164 CPUM_ASSERT_RD_MSR_FN(AmdK7FastFlushCountMaybe);
5165 CPUM_ASSERT_RD_MSR_FN(AmdK7NodeId);
5166 CPUM_ASSERT_RD_MSR_FN(AmdK7DrXAddrMaskN);
5167 CPUM_ASSERT_RD_MSR_FN(AmdK7Dr0DataMatchMaybe);
5168 CPUM_ASSERT_RD_MSR_FN(AmdK7Dr0DataMaskMaybe);
5169 CPUM_ASSERT_RD_MSR_FN(AmdK7LoadStoreCfg);
5170 CPUM_ASSERT_RD_MSR_FN(AmdK7InstrCacheCfg);
5171 CPUM_ASSERT_RD_MSR_FN(AmdK7DataCacheCfg);
5172 CPUM_ASSERT_RD_MSR_FN(AmdK7BusUnitCfg);
5173 CPUM_ASSERT_RD_MSR_FN(AmdK7DebugCtl2Maybe);
5174 CPUM_ASSERT_RD_MSR_FN(AmdFam15hFpuCfg);
5175 CPUM_ASSERT_RD_MSR_FN(AmdFam15hDecoderCfg);
5176 CPUM_ASSERT_RD_MSR_FN(AmdFam10hBusUnitCfg2);
5177 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg);
5178 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg2);
5179 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg3);
5180 CPUM_ASSERT_RD_MSR_FN(AmdFam15hExecUnitCfg);
5181 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLoadStoreCfg2);
5182 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchCtl);
5183 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchLinAddr);
5184 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchPhysAddr);
5185 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpExecCtl);
5186 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpRip);
5187 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData);
5188 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData2);
5189 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData3);
5190 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsDcLinAddr);
5191 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsDcPhysAddr);
5192 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsCtl);
5193 CPUM_ASSERT_RD_MSR_FN(AmdFam14hIbsBrTarget);
5194
5195 AssertReturn(g_aCpumWrMsrFns[kCpumMsrWrFn_Invalid] == NULL, VERR_CPUM_IPE_2);
5196 CPUM_ASSERT_WR_MSR_FN(Ia32P5McAddr);
5197 CPUM_ASSERT_WR_MSR_FN(Ia32P5McType);
5198 CPUM_ASSERT_WR_MSR_FN(Ia32TimestampCounter);
5199 CPUM_ASSERT_WR_MSR_FN(Ia32ApicBase);
5200 CPUM_ASSERT_WR_MSR_FN(Ia32FeatureControl);
5201 CPUM_ASSERT_WR_MSR_FN(Ia32BiosSignId);
5202 CPUM_ASSERT_WR_MSR_FN(Ia32BiosUpdateTrigger);
5203 CPUM_ASSERT_WR_MSR_FN(Ia32SmmMonitorCtl);
5204 CPUM_ASSERT_WR_MSR_FN(Ia32PmcN);
5205 CPUM_ASSERT_WR_MSR_FN(Ia32MonitorFilterLineSize);
5206 CPUM_ASSERT_WR_MSR_FN(Ia32MPerf);
5207 CPUM_ASSERT_WR_MSR_FN(Ia32APerf);
5208 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrPhysBaseN);
5209 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrPhysMaskN);
5210 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrFixed);
5211 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrDefType);
5212 CPUM_ASSERT_WR_MSR_FN(Ia32Pat);
5213 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterCs);
5214 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterEsp);
5215 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterEip);
5216 CPUM_ASSERT_WR_MSR_FN(Ia32McgStatus);
5217 CPUM_ASSERT_WR_MSR_FN(Ia32McgCtl);
5218 CPUM_ASSERT_WR_MSR_FN(Ia32DebugCtl);
5219 CPUM_ASSERT_WR_MSR_FN(Ia32SmrrPhysBase);
5220 CPUM_ASSERT_WR_MSR_FN(Ia32SmrrPhysMask);
5221 CPUM_ASSERT_WR_MSR_FN(Ia32PlatformDcaCap);
5222 CPUM_ASSERT_WR_MSR_FN(Ia32Dca0Cap);
5223 CPUM_ASSERT_WR_MSR_FN(Ia32PerfEvtSelN);
5224 CPUM_ASSERT_WR_MSR_FN(Ia32PerfStatus);
5225 CPUM_ASSERT_WR_MSR_FN(Ia32PerfCtl);
5226 CPUM_ASSERT_WR_MSR_FN(Ia32FixedCtrN);
5227 CPUM_ASSERT_WR_MSR_FN(Ia32PerfCapabilities);
5228 CPUM_ASSERT_WR_MSR_FN(Ia32FixedCtrCtrl);
5229 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalStatus);
5230 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalCtrl);
5231 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalOvfCtrl);
5232 CPUM_ASSERT_WR_MSR_FN(Ia32PebsEnable);
5233 CPUM_ASSERT_WR_MSR_FN(Ia32ClockModulation);
5234 CPUM_ASSERT_WR_MSR_FN(Ia32ThermInterrupt);
5235 CPUM_ASSERT_WR_MSR_FN(Ia32ThermStatus);
5236 CPUM_ASSERT_WR_MSR_FN(Ia32MiscEnable);
5237 CPUM_ASSERT_WR_MSR_FN(Ia32McCtlStatusAddrMiscN);
5238 CPUM_ASSERT_WR_MSR_FN(Ia32McNCtl2);
5239 CPUM_ASSERT_WR_MSR_FN(Ia32DsArea);
5240 CPUM_ASSERT_WR_MSR_FN(Ia32TscDeadline);
5241 CPUM_ASSERT_WR_MSR_FN(Ia32X2ApicN);
5242 CPUM_ASSERT_WR_MSR_FN(Ia32DebugInterface);
5243
5244 CPUM_ASSERT_WR_MSR_FN(Amd64Efer);
5245 CPUM_ASSERT_WR_MSR_FN(Amd64SyscallTarget);
5246 CPUM_ASSERT_WR_MSR_FN(Amd64LongSyscallTarget);
5247 CPUM_ASSERT_WR_MSR_FN(Amd64CompSyscallTarget);
5248 CPUM_ASSERT_WR_MSR_FN(Amd64SyscallFlagMask);
5249 CPUM_ASSERT_WR_MSR_FN(Amd64FsBase);
5250 CPUM_ASSERT_WR_MSR_FN(Amd64GsBase);
5251 CPUM_ASSERT_WR_MSR_FN(Amd64KernelGsBase);
5252 CPUM_ASSERT_WR_MSR_FN(Amd64TscAux);
5253
5254 CPUM_ASSERT_WR_MSR_FN(IntelEblCrPowerOn);
5255 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcHardPowerOn);
5256 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcSoftPowerOn);
5257 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcFrequencyId);
5258 CPUM_ASSERT_WR_MSR_FN(IntelPkgCStConfigControl);
5259 CPUM_ASSERT_WR_MSR_FN(IntelPmgIoCaptureBase);
5260 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchFromToN);
5261 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchFromN);
5262 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchToN);
5263 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchTos);
5264 CPUM_ASSERT_WR_MSR_FN(IntelBblCrCtl);
5265 CPUM_ASSERT_WR_MSR_FN(IntelBblCrCtl3);
5266 CPUM_ASSERT_WR_MSR_FN(IntelI7TemperatureTarget);
5267 CPUM_ASSERT_WR_MSR_FN(IntelI7MsrOffCoreResponseN);
5268 CPUM_ASSERT_WR_MSR_FN(IntelI7MiscPwrMgmt);
5269 CPUM_ASSERT_WR_MSR_FN(IntelP6CrN);
5270 CPUM_ASSERT_WR_MSR_FN(IntelCpuId1FeatureMaskEcdx);
5271 CPUM_ASSERT_WR_MSR_FN(IntelCpuId1FeatureMaskEax);
5272 CPUM_ASSERT_WR_MSR_FN(IntelCpuId80000001FeatureMaskEcdx);
5273 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyAesNiCtl);
5274 CPUM_ASSERT_WR_MSR_FN(IntelI7TurboRatioLimit);
5275 CPUM_ASSERT_WR_MSR_FN(IntelI7LbrSelect);
5276 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyErrorControl);
5277 CPUM_ASSERT_WR_MSR_FN(IntelI7PowerCtl);
5278 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPebsNumAlt);
5279 CPUM_ASSERT_WR_MSR_FN(IntelI7PebsLdLat);
5280 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyVrCurrentConfig);
5281 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyVrMiscConfig);
5282 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPkgCnIrtlN);
5283 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPkgPowerLimit);
5284 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplDramPowerLimit);
5285 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp0PowerLimit);
5286 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp0Policy);
5287 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp1PowerLimit);
5288 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp1Policy);
5289 CPUM_ASSERT_WR_MSR_FN(IntelI7IvyConfigTdpControl);
5290 CPUM_ASSERT_WR_MSR_FN(IntelI7IvyTurboActivationRatio);
5291 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalCtrl);
5292 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalStatus);
5293 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalOvfCtrl);
5294 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfFixedCtrCtrl);
5295 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfFixedCtr);
5296 CPUM_ASSERT_WR_MSR_FN(IntelI7UncArbPerfCtrN);
5297 CPUM_ASSERT_WR_MSR_FN(IntelI7UncArbPerfEvtSelN);
5298 CPUM_ASSERT_WR_MSR_FN(IntelCore2EmttmCrTablesN);
5299 CPUM_ASSERT_WR_MSR_FN(IntelCore2SmmCStMiscInfo);
5300 CPUM_ASSERT_WR_MSR_FN(IntelCore1ExtConfig);
5301 CPUM_ASSERT_WR_MSR_FN(IntelCore1DtsCalControl);
5302 CPUM_ASSERT_WR_MSR_FN(IntelCore2PeciControl);
5303
5304 CPUM_ASSERT_WR_MSR_FN(P6LastIntFromIp);
5305 CPUM_ASSERT_WR_MSR_FN(P6LastIntToIp);
5306
5307 CPUM_ASSERT_WR_MSR_FN(AmdFam15hTscRate);
5308 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLwpCfg);
5309 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLwpCbAddr);
5310 CPUM_ASSERT_WR_MSR_FN(AmdFam10hMc4MiscN);
5311 CPUM_ASSERT_WR_MSR_FN(AmdK8PerfCtlN);
5312 CPUM_ASSERT_WR_MSR_FN(AmdK8PerfCtrN);
5313 CPUM_ASSERT_WR_MSR_FN(AmdK8SysCfg);
5314 CPUM_ASSERT_WR_MSR_FN(AmdK8HwCr);
5315 CPUM_ASSERT_WR_MSR_FN(AmdK8IorrBaseN);
5316 CPUM_ASSERT_WR_MSR_FN(AmdK8IorrMaskN);
5317 CPUM_ASSERT_WR_MSR_FN(AmdK8TopOfMemN);
5318 CPUM_ASSERT_WR_MSR_FN(AmdK8NbCfg1);
5319 CPUM_ASSERT_WR_MSR_FN(AmdK8McXcptRedir);
5320 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuNameN);
5321 CPUM_ASSERT_WR_MSR_FN(AmdK8HwThermalCtrl);
5322 CPUM_ASSERT_WR_MSR_FN(AmdK8SwThermalCtrl);
5323 CPUM_ASSERT_WR_MSR_FN(AmdK8FidVidControl);
5324 CPUM_ASSERT_WR_MSR_FN(AmdK8McCtlMaskN);
5325 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiOnIoTrapN);
5326 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiOnIoTrapCtlSts);
5327 CPUM_ASSERT_WR_MSR_FN(AmdK8IntPendingMessage);
5328 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiTriggerIoCycle);
5329 CPUM_ASSERT_WR_MSR_FN(AmdFam10hMmioCfgBaseAddr);
5330 CPUM_ASSERT_WR_MSR_FN(AmdFam10hTrapCtlMaybe);
5331 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateControl);
5332 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateStatus);
5333 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateN);
5334 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCofVidControl);
5335 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCofVidStatus);
5336 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCStateIoBaseAddr);
5337 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCpuWatchdogTimer);
5338 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmBase);
5339 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmAddr);
5340 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmMask);
5341 CPUM_ASSERT_WR_MSR_FN(AmdK8VmCr);
5342 CPUM_ASSERT_WR_MSR_FN(AmdK8IgnNe);
5343 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmCtl);
5344 CPUM_ASSERT_WR_MSR_FN(AmdK8VmHSavePa);
5345 CPUM_ASSERT_WR_MSR_FN(AmdFam10hVmLockKey);
5346 CPUM_ASSERT_WR_MSR_FN(AmdFam10hSmmLockKey);
5347 CPUM_ASSERT_WR_MSR_FN(AmdFam10hLocalSmiStatus);
5348 CPUM_ASSERT_WR_MSR_FN(AmdFam10hOsVisWrkIdLength);
5349 CPUM_ASSERT_WR_MSR_FN(AmdFam10hOsVisWrkStatus);
5350 CPUM_ASSERT_WR_MSR_FN(AmdFam16hL2IPerfCtlN);
5351 CPUM_ASSERT_WR_MSR_FN(AmdFam16hL2IPerfCtrN);
5352 CPUM_ASSERT_WR_MSR_FN(AmdFam15hNorthbridgePerfCtlN);
5353 CPUM_ASSERT_WR_MSR_FN(AmdFam15hNorthbridgePerfCtrN);
5354 CPUM_ASSERT_WR_MSR_FN(AmdK7MicrocodeCtl);
5355 CPUM_ASSERT_WR_MSR_FN(AmdK7ClusterIdMaybe);
5356 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd07hEbax);
5357 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd06hEcx);
5358 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd01hEdcx);
5359 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlExt01hEdcx);
5360 CPUM_ASSERT_WR_MSR_FN(AmdK8PatchLoader);
5361 CPUM_ASSERT_WR_MSR_FN(AmdK7DebugStatusMaybe);
5362 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTraceBaseMaybe);
5363 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTracePtrMaybe);
5364 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTraceLimitMaybe);
5365 CPUM_ASSERT_WR_MSR_FN(AmdK7HardwareDebugToolCfgMaybe);
5366 CPUM_ASSERT_WR_MSR_FN(AmdK7FastFlushCountMaybe);
5367 CPUM_ASSERT_WR_MSR_FN(AmdK7NodeId);
5368 CPUM_ASSERT_WR_MSR_FN(AmdK7DrXAddrMaskN);
5369 CPUM_ASSERT_WR_MSR_FN(AmdK7Dr0DataMatchMaybe);
5370 CPUM_ASSERT_WR_MSR_FN(AmdK7Dr0DataMaskMaybe);
5371 CPUM_ASSERT_WR_MSR_FN(AmdK7LoadStoreCfg);
5372 CPUM_ASSERT_WR_MSR_FN(AmdK7InstrCacheCfg);
5373 CPUM_ASSERT_WR_MSR_FN(AmdK7DataCacheCfg);
5374 CPUM_ASSERT_WR_MSR_FN(AmdK7BusUnitCfg);
5375 CPUM_ASSERT_WR_MSR_FN(AmdK7DebugCtl2Maybe);
5376 CPUM_ASSERT_WR_MSR_FN(AmdFam15hFpuCfg);
5377 CPUM_ASSERT_WR_MSR_FN(AmdFam15hDecoderCfg);
5378 CPUM_ASSERT_WR_MSR_FN(AmdFam10hBusUnitCfg2);
5379 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg);
5380 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg2);
5381 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg3);
5382 CPUM_ASSERT_WR_MSR_FN(AmdFam15hExecUnitCfg);
5383 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLoadStoreCfg2);
5384 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchCtl);
5385 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchLinAddr);
5386 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchPhysAddr);
5387 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpExecCtl);
5388 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpRip);
5389 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData);
5390 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData2);
5391 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData3);
5392 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsDcLinAddr);
5393 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsDcPhysAddr);
5394 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsCtl);
5395 CPUM_ASSERT_WR_MSR_FN(AmdFam14hIbsBrTarget);
5396
5397 return VINF_SUCCESS;
5398}
5399#endif /* VBOX_STRICT && IN_RING3 */
5400
5401
5402#ifdef IN_RING0
5403
5404/**
5405 * Fast way for HM to access the MSR_K8_TSC_AUX register.
5406 *
5407 * @returns The register value.
5408 * @param pVCpu Pointer to the cross context CPU structure for
5409 * the calling EMT.
5410 * @thread EMT(pVCpu)
5411 */
5412VMMR0_INT_DECL(uint64_t) CPUMR0GetGuestTscAux(PVMCPU pVCpu)
5413{
5414 return pVCpu->cpum.s.GuestMsrs.msr.TscAux;
5415}
5416
5417
5418/**
5419 * Fast way for HM to access the MSR_K8_TSC_AUX register.
5420 *
5421 * @param pVCpu Pointer to the cross context CPU structure for
5422 * the calling EMT.
5423 * @param uValue The new value.
5424 * @thread EMT(pVCpu)
5425 */
5426VMMR0_INT_DECL(void) CPUMR0SetGuestTscAux(PVMCPU pVCpu, uint64_t uValue)
5427{
5428 pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
5429}
5430
5431#endif /* IN_RING0 */
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