VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllMsrs.cpp@ 53627

Last change on this file since 53627 was 53467, checked in by vboxsync, 10 years ago

VMM: Removed VBOX_WITH_NEW_MSR_CODE and the code marked ifndef VBOX_WITH_NEW_MSR_CODE.
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File size: 189.3 KB
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1/* $Id: CPUMAllMsrs.cpp 53467 2014-12-05 16:10:20Z vboxsync $ */
2/** @file
3 * CPUM - CPU MSR Registers.
4 */
5
6/*
7 * Copyright (C) 2013-2014 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_CPUM
22#include <VBox/vmm/cpum.h>
23#include <VBox/vmm/pdmapi.h>
24#include <VBox/vmm/hm.h>
25#include <VBox/vmm/tm.h>
26#include <VBox/vmm/gim.h>
27#include "CPUMInternal.h"
28#include <VBox/vmm/vm.h>
29#include <VBox/err.h>
30
31
32/*******************************************************************************
33* Defined Constants And Macros *
34*******************************************************************************/
35/**
36 * Validates the CPUMMSRRANGE::offCpumCpu value and declares a local variable
37 * pointing to it.
38 *
39 * ASSUMES sizeof(a_Type) is a power of two and that the member is aligned
40 * correctly.
41 */
42#define CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(a_pVCpu, a_pRange, a_Type, a_VarName) \
43 AssertMsgReturn( (a_pRange)->offCpumCpu >= 8 \
44 && (a_pRange)->offCpumCpu < sizeof(CPUMCPU) \
45 && !((a_pRange)->offCpumCpu & (RT_MIN(sizeof(a_Type), 8) - 1)) \
46 , ("offCpumCpu=%#x %s\n", (a_pRange)->offCpumCpu, (a_pRange)->szName), \
47 VERR_CPUM_MSR_BAD_CPUMCPU_OFFSET); \
48 a_Type *a_VarName = (a_Type *)((uintptr_t)&(a_pVCpu)->cpum.s + (a_pRange)->offCpumCpu)
49
50
51/*******************************************************************************
52* Structures and Typedefs *
53*******************************************************************************/
54
55/**
56 * Implements reading one or more MSRs.
57 *
58 * @returns VBox status code.
59 * @retval VINF_SUCCESS on success.
60 * @retval VINF_CPUM_R3_MSR_READ if the MSR read could not be serviced in the
61 * current context (raw-mode or ring-0).
62 * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR).
63 *
64 * @param pVCpu Pointer to the VMCPU.
65 * @param idMsr The MSR we're reading.
66 * @param pRange The MSR range descriptor.
67 * @param puValue Where to return the value.
68 */
69typedef DECLCALLBACK(VBOXSTRICTRC) FNCPUMRDMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue);
70/** Pointer to a RDMSR worker for a specific MSR or range of MSRs. */
71typedef FNCPUMRDMSR *PFNCPUMRDMSR;
72
73
74/**
75 * Implements writing one or more MSRs.
76 *
77 * @retval VINF_SUCCESS on success.
78 * @retval VINF_CPUM_R3_MSR_WRITE if the MSR write could not be serviced in the
79 * current context (raw-mode or ring-0).
80 * @retval VERR_CPUM_RAISE_GP_0 on failure.
81 *
82 * @param pVCpu Pointer to the VMCPU.
83 * @param idMsr The MSR we're writing.
84 * @param pRange The MSR range descriptor.
85 * @param uValue The value to set, ignored bits masked.
86 * @param uRawValue The raw value with the ignored bits not masked.
87 */
88typedef DECLCALLBACK(VBOXSTRICTRC) FNCPUMWRMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue);
89/** Pointer to a WRMSR worker for a specific MSR or range of MSRs. */
90typedef FNCPUMWRMSR *PFNCPUMWRMSR;
91
92
93
94/*
95 * Generic functions.
96 * Generic functions.
97 * Generic functions.
98 */
99
100
101/** @callback_method_impl{FNCPUMRDMSR} */
102static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_FixedValue(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
103{
104 *puValue = pRange->uValue;
105 return VINF_SUCCESS;
106}
107
108
109/** @callback_method_impl{FNCPUMWRMSR} */
110static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IgnoreWrite(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
111{
112 Log(("CPUM: Ignoring WRMSR %#x (%s), %#llx\n", idMsr, pRange->szName, uValue));
113 return VINF_SUCCESS;
114}
115
116
117/** @callback_method_impl{FNCPUMRDMSR} */
118static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_WriteOnly(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
119{
120 return VERR_CPUM_RAISE_GP_0;
121}
122
123
124/** @callback_method_impl{FNCPUMWRMSR} */
125static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_ReadOnly(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
126{
127 Assert(pRange->fWrGpMask == UINT64_MAX);
128 return VERR_CPUM_RAISE_GP_0;
129}
130
131
132
133
134/*
135 * IA32
136 * IA32
137 * IA32
138 */
139
140/** @callback_method_impl{FNCPUMRDMSR} */
141static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32P5McAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
142{
143 *puValue = 0; /** @todo implement machine check injection. */
144 return VINF_SUCCESS;
145}
146
147
148/** @callback_method_impl{FNCPUMWRMSR} */
149static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32P5McAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
150{
151 /** @todo implement machine check injection. */
152 return VINF_SUCCESS;
153}
154
155
156/** @callback_method_impl{FNCPUMRDMSR} */
157static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32P5McType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
158{
159 *puValue = 0; /** @todo implement machine check injection. */
160 return VINF_SUCCESS;
161}
162
163
164/** @callback_method_impl{FNCPUMWRMSR} */
165static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32P5McType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
166{
167 /** @todo implement machine check injection. */
168 return VINF_SUCCESS;
169}
170
171
172/** @callback_method_impl{FNCPUMRDMSR} */
173static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32TimestampCounter(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
174{
175 *puValue = TMCpuTickGet(pVCpu);
176 return VINF_SUCCESS;
177}
178
179
180/** @callback_method_impl{FNCPUMWRMSR} */
181static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32TimestampCounter(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
182{
183 TMCpuTickSet(pVCpu->CTX_SUFF(pVM), pVCpu, uValue);
184 return VINF_SUCCESS;
185}
186
187
188/** @callback_method_impl{FNCPUMRDMSR} */
189static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PlatformId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
190{
191 uint64_t uValue = pRange->uValue;
192 if (uValue & 0x1f00)
193 {
194 /* Max allowed bus ratio present. */
195 /** @todo Implement scaled BUS frequency. */
196 }
197
198 *puValue = uValue;
199 return VINF_SUCCESS;
200}
201
202
203/** @callback_method_impl{FNCPUMRDMSR} */
204static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ApicBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
205{
206 PVM pVM = pVCpu->CTX_SUFF(pVM);
207#if 0 /** @todo Sort this one out properly. Evidence from ticks 12240 and 12875 suggest the apic base is still readable even
208 * after the apic has been diabled. That makes common sense too. What we need to do here, though, is check whether
209 * there is an APIC device associated with the VM, and GP if there isn't. But that's for later. */
210 if ( !pVM->cpum.s.GuestFeatures.fApic
211 && !pVM->cpum.s.GuestFeatures.fX2Apic)
212 {
213 Log(("CPUM: %s, apic not present -> GP\n", pRange->szName));
214 return VERR_CPUM_RAISE_GP_0;
215 }
216#endif
217
218 *puValue = pVCpu->cpum.s.Guest.msrApicBase;
219 return VINF_SUCCESS;
220}
221
222
223/** @callback_method_impl{FNCPUMWRMSR} */
224static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ApicBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
225{
226 int rc = PDMApicSetBase(pVCpu, uValue);
227 if (rc != VINF_SUCCESS)
228 rc = VERR_CPUM_RAISE_GP_0;
229 return VINF_SUCCESS;
230}
231
232
233/** @callback_method_impl{FNCPUMRDMSR} */
234static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32FeatureControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
235{
236 *puValue = 1; /* Locked, no VT-X, no SYSENTER micromanagement. */
237 return VINF_SUCCESS;
238}
239
240
241/** @callback_method_impl{FNCPUMWRMSR} */
242static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32FeatureControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
243{
244 return VERR_CPUM_RAISE_GP_0;
245}
246
247
248/** @callback_method_impl{FNCPUMRDMSR} */
249static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32BiosSignId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
250{
251 /** @todo fake microcode update. */
252 *puValue = pRange->uValue;
253 return VINF_SUCCESS;
254}
255
256
257/** @callback_method_impl{FNCPUMWRMSR} */
258static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32BiosSignId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
259{
260 /* Normally, zero is written to Ia32BiosSignId before reading it in order
261 to select the signature instead of the BBL_CR_D3 behaviour. The GP mask
262 of the database entry should take care of most illegal writes for now, so
263 just ignore all writes atm. */
264 return VINF_SUCCESS;
265}
266
267
268/** @callback_method_impl{FNCPUMWRMSR} */
269static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32BiosUpdateTrigger(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
270{
271 /** @todo Fake bios update trigger better. The value is the address to an
272 * update package, I think. We should probably GP if it's invalid. */
273 return VINF_SUCCESS;
274}
275
276
277/** @callback_method_impl{FNCPUMRDMSR} */
278static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SmmMonitorCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
279{
280 /** @todo SMM. */
281 *puValue = 0;
282 return VINF_SUCCESS;
283}
284
285
286/** @callback_method_impl{FNCPUMWRMSR} */
287static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SmmMonitorCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
288{
289 /** @todo SMM. */
290 return VINF_SUCCESS;
291}
292
293
294/** @callback_method_impl{FNCPUMRDMSR} */
295static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PmcN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
296{
297 /** @todo check CPUID leaf 0ah. */
298 *puValue = 0;
299 return VINF_SUCCESS;
300}
301
302
303/** @callback_method_impl{FNCPUMWRMSR} */
304static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PmcN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
305{
306 /** @todo check CPUID leaf 0ah. */
307 return VINF_SUCCESS;
308}
309
310
311/** @callback_method_impl{FNCPUMRDMSR} */
312static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MonitorFilterLineSize(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
313{
314 /** @todo return 0x1000 if we try emulate mwait 100% correctly. */
315 *puValue = 0x40; /** @todo Change to CPU cache line size. */
316 return VINF_SUCCESS;
317}
318
319
320/** @callback_method_impl{FNCPUMWRMSR} */
321static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MonitorFilterLineSize(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
322{
323 /** @todo should remember writes, though it's supposedly something only a BIOS
324 * would write so, it's not extremely important. */
325 return VINF_SUCCESS;
326}
327
328/** @callback_method_impl{FNCPUMRDMSR} */
329static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MPerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
330{
331 /** @todo Read MPERF: Adjust against previously written MPERF value. Is TSC
332 * what we want? */
333 *puValue = TMCpuTickGet(pVCpu);
334 return VINF_SUCCESS;
335}
336
337
338/** @callback_method_impl{FNCPUMWRMSR} */
339static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MPerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
340{
341 /** @todo Write MPERF: Calc adjustment. */
342 return VINF_SUCCESS;
343}
344
345
346/** @callback_method_impl{FNCPUMRDMSR} */
347static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32APerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
348{
349 /** @todo Read APERF: Adjust against previously written MPERF value. Is TSC
350 * what we want? */
351 *puValue = TMCpuTickGet(pVCpu);
352 return VINF_SUCCESS;
353}
354
355
356/** @callback_method_impl{FNCPUMWRMSR} */
357static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32APerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
358{
359 /** @todo Write APERF: Calc adjustment. */
360 return VINF_SUCCESS;
361}
362
363
364/** @callback_method_impl{FNCPUMWRMSR} */
365static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
366{
367 /* This is currently a bit weird. :-) */
368 uint8_t const cVariableRangeRegs = 0;
369 bool const fSystemManagementRangeRegisters = false;
370 bool const fFixedRangeRegisters = false;
371 bool const fWriteCombiningType = false;
372 *puValue = cVariableRangeRegs
373 | (fFixedRangeRegisters ? RT_BIT_64(8) : 0)
374 | (fWriteCombiningType ? RT_BIT_64(10) : 0)
375 | (fSystemManagementRangeRegisters ? RT_BIT_64(11) : 0);
376 return VINF_SUCCESS;
377}
378
379
380/** @callback_method_impl{FNCPUMRDMSR} */
381static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrPhysBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
382{
383 /** @todo Implement variable MTRR storage. */
384 Assert(pRange->uValue == (idMsr - 0x200) / 2);
385 *puValue = 0;
386 return VINF_SUCCESS;
387}
388
389
390/** @callback_method_impl{FNCPUMWRMSR} */
391static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrPhysBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
392{
393 /*
394 * Validate the value.
395 */
396 Assert(pRange->uValue == (idMsr - 0x200) / 2);
397
398 if ((uValue & 0xff) >= 7)
399 {
400 Log(("CPUM: Invalid type set writing MTRR PhysBase MSR %#x: %#llx (%#llx)\n", idMsr, uValue, uValue & 0xff));
401 return VERR_CPUM_RAISE_GP_0;
402 }
403
404 uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
405 if (fInvPhysMask & uValue)
406 {
407 Log(("CPUM: Invalid physical address bits set writing MTRR PhysBase MSR %#x: %#llx (%#llx)\n",
408 idMsr, uValue, uValue & fInvPhysMask));
409 return VERR_CPUM_RAISE_GP_0;
410 }
411
412 /*
413 * Store it.
414 */
415 /** @todo Implement variable MTRR storage. */
416 return VINF_SUCCESS;
417}
418
419
420/** @callback_method_impl{FNCPUMRDMSR} */
421static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrPhysMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
422{
423 /** @todo Implement variable MTRR storage. */
424 Assert(pRange->uValue == (idMsr - 0x200) / 2);
425 *puValue = 0;
426 return VINF_SUCCESS;
427}
428
429
430/** @callback_method_impl{FNCPUMWRMSR} */
431static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrPhysMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
432{
433 /*
434 * Validate the value.
435 */
436 Assert(pRange->uValue == (idMsr - 0x200) / 2);
437
438 uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
439 if (fInvPhysMask & uValue)
440 {
441 Log(("CPUM: Invalid physical address bits set writing MTRR PhysMask MSR %#x: %#llx (%#llx)\n",
442 idMsr, uValue, uValue & fInvPhysMask));
443 return VERR_CPUM_RAISE_GP_0;
444 }
445
446 /*
447 * Store it.
448 */
449 /** @todo Implement variable MTRR storage. */
450 return VINF_SUCCESS;
451}
452
453
454/** @callback_method_impl{FNCPUMRDMSR} */
455static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrFixed(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
456{
457 CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(pVCpu, pRange, uint64_t, puFixedMtrr);
458 *puValue = *puFixedMtrr;
459 return VINF_SUCCESS;
460}
461
462
463/** @callback_method_impl{FNCPUMWRMSR} */
464static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrFixed(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
465{
466 CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(pVCpu, pRange, uint64_t, puFixedMtrr);
467 for (uint32_t cShift = 0; cShift < 63; cShift += 8)
468 {
469 uint8_t uType = (uint8_t)(uValue >> cShift);
470 if (uType >= 7)
471 {
472 Log(("CPUM: Invalid MTRR type at %u:%u in fixed range (%#x/%s): %#llx (%#llx)\n",
473 cShift + 7, cShift, idMsr, pRange->szName, uValue, uType));
474 return VERR_CPUM_RAISE_GP_0;
475 }
476 }
477 *puFixedMtrr = uValue;
478 return VINF_SUCCESS;
479}
480
481
482/** @callback_method_impl{FNCPUMRDMSR} */
483static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrDefType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
484{
485 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType;
486 return VINF_SUCCESS;
487}
488
489
490/** @callback_method_impl{FNCPUMWRMSR} */
491static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrDefType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
492{
493 if ((uValue & 0xff) >= 7)
494 {
495 Log(("CPUM: Invalid MTRR default type value: %#llx (%#llx)\n", pRange->szName, uValue, uValue & 0xff));
496 return VERR_CPUM_RAISE_GP_0;
497 }
498
499 pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType = uValue;
500 return VINF_SUCCESS;
501}
502
503
504/** @callback_method_impl{FNCPUMRDMSR} */
505static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32Pat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
506{
507 *puValue = pVCpu->cpum.s.Guest.msrPAT;
508 return VINF_SUCCESS;
509}
510
511
512/** @callback_method_impl{FNCPUMWRMSR} */
513static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32Pat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
514{
515 pVCpu->cpum.s.Guest.msrPAT = uValue;
516 return VINF_SUCCESS;
517}
518
519
520/** @callback_method_impl{FNCPUMRDMSR} */
521static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SysEnterCs(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
522{
523 *puValue = pVCpu->cpum.s.Guest.SysEnter.cs;
524 return VINF_SUCCESS;
525}
526
527
528/** @callback_method_impl{FNCPUMWRMSR} */
529static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SysEnterCs(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
530{
531 /* Note! We used to mask this by 0xffff, but turns out real HW doesn't and
532 there are generally 32-bit working bits backing this register. */
533 pVCpu->cpum.s.Guest.SysEnter.cs = uValue;
534 return VINF_SUCCESS;
535}
536
537
538/** @callback_method_impl{FNCPUMRDMSR} */
539static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SysEnterEsp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
540{
541 *puValue = pVCpu->cpum.s.Guest.SysEnter.esp;
542 return VINF_SUCCESS;
543}
544
545
546/** @callback_method_impl{FNCPUMWRMSR} */
547static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SysEnterEsp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
548{
549 if (X86_IS_CANONICAL(uValue))
550 {
551 pVCpu->cpum.s.Guest.SysEnter.esp = uValue;
552 return VINF_SUCCESS;
553 }
554 Log(("CPUM: IA32_SYSENTER_ESP not canonical! %#llx\n", uValue));
555 return VERR_CPUM_RAISE_GP_0;
556}
557
558
559/** @callback_method_impl{FNCPUMRDMSR} */
560static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SysEnterEip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
561{
562 *puValue = pVCpu->cpum.s.Guest.SysEnter.eip;
563 return VINF_SUCCESS;
564}
565
566
567/** @callback_method_impl{FNCPUMWRMSR} */
568static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SysEnterEip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
569{
570 if (X86_IS_CANONICAL(uValue))
571 {
572 pVCpu->cpum.s.Guest.SysEnter.eip = uValue;
573 return VINF_SUCCESS;
574 }
575#ifdef IN_RING3
576 LogRel(("CPUM: IA32_SYSENTER_EIP not canonical! %#llx\n", uValue));
577#else
578 Log(("CPUM: IA32_SYSENTER_EIP not canonical! %#llx\n", uValue));
579#endif
580 return VERR_CPUM_RAISE_GP_0;
581}
582
583
584/** @callback_method_impl{FNCPUMRDMSR} */
585static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McgCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
586{
587#if 0 /** @todo implement machine checks. */
588 *puValue = pRange->uValue & (RT_BIT_64(8) | 0);
589#else
590 *puValue = 0;
591#endif
592 return VINF_SUCCESS;
593}
594
595
596/** @callback_method_impl{FNCPUMRDMSR} */
597static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McgStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
598{
599 /** @todo implement machine checks. */
600 *puValue = 0;
601 return VINF_SUCCESS;
602}
603
604
605/** @callback_method_impl{FNCPUMWRMSR} */
606static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McgStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
607{
608 /** @todo implement machine checks. */
609 return VINF_SUCCESS;
610}
611
612
613/** @callback_method_impl{FNCPUMRDMSR} */
614static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McgCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
615{
616 /** @todo implement machine checks. */
617 *puValue = 0;
618 return VINF_SUCCESS;
619}
620
621
622/** @callback_method_impl{FNCPUMWRMSR} */
623static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McgCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
624{
625 /** @todo implement machine checks. */
626 return VINF_SUCCESS;
627}
628
629
630/** @callback_method_impl{FNCPUMRDMSR} */
631static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32DebugCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
632{
633 /** @todo implement IA32_DEBUGCTL. */
634 *puValue = 0;
635 return VINF_SUCCESS;
636}
637
638
639/** @callback_method_impl{FNCPUMWRMSR} */
640static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32DebugCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
641{
642 /** @todo implement IA32_DEBUGCTL. */
643 return VINF_SUCCESS;
644}
645
646
647/** @callback_method_impl{FNCPUMRDMSR} */
648static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SmrrPhysBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
649{
650 /** @todo implement intel SMM. */
651 *puValue = 0;
652 return VINF_SUCCESS;
653}
654
655
656/** @callback_method_impl{FNCPUMWRMSR} */
657static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SmrrPhysBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
658{
659 /** @todo implement intel SMM. */
660 return VERR_CPUM_RAISE_GP_0;
661}
662
663
664/** @callback_method_impl{FNCPUMRDMSR} */
665static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SmrrPhysMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
666{
667 /** @todo implement intel SMM. */
668 *puValue = 0;
669 return VINF_SUCCESS;
670}
671
672
673/** @callback_method_impl{FNCPUMWRMSR} */
674static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SmrrPhysMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
675{
676 /** @todo implement intel SMM. */
677 return VERR_CPUM_RAISE_GP_0;
678}
679
680
681/** @callback_method_impl{FNCPUMRDMSR} */
682static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PlatformDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
683{
684 /** @todo implement intel direct cache access (DCA)?? */
685 *puValue = 0;
686 return VINF_SUCCESS;
687}
688
689
690/** @callback_method_impl{FNCPUMWRMSR} */
691static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PlatformDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
692{
693 /** @todo implement intel direct cache access (DCA)?? */
694 return VINF_SUCCESS;
695}
696
697
698/** @callback_method_impl{FNCPUMRDMSR} */
699static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32CpuDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
700{
701 /** @todo implement intel direct cache access (DCA)?? */
702 *puValue = 0;
703 return VINF_SUCCESS;
704}
705
706
707/** @callback_method_impl{FNCPUMRDMSR} */
708static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32Dca0Cap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
709{
710 /** @todo implement intel direct cache access (DCA)?? */
711 *puValue = 0;
712 return VINF_SUCCESS;
713}
714
715
716/** @callback_method_impl{FNCPUMWRMSR} */
717static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32Dca0Cap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
718{
719 /** @todo implement intel direct cache access (DCA)?? */
720 return VINF_SUCCESS;
721}
722
723
724/** @callback_method_impl{FNCPUMRDMSR} */
725static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
726{
727 /** @todo implement IA32_PERFEVTSEL0+. */
728 *puValue = 0;
729 return VINF_SUCCESS;
730}
731
732
733/** @callback_method_impl{FNCPUMWRMSR} */
734static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
735{
736 /** @todo implement IA32_PERFEVTSEL0+. */
737 return VINF_SUCCESS;
738}
739
740
741/** @callback_method_impl{FNCPUMRDMSR} */
742static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
743{
744 uint64_t uValue = pRange->uValue;
745
746 /* Always provide the max bus ratio for now. XNU expects it. */
747 uValue &= ~((UINT64_C(0x1f) << 40) | RT_BIT_64(46));
748
749 PVM pVM = pVCpu->CTX_SUFF(pVM);
750 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
751 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
752 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
753 if (uTscRatio > 0x1f)
754 uTscRatio = 0x1f;
755 uValue |= (uint64_t)uTscRatio << 40;
756
757 *puValue = uValue;
758 return VINF_SUCCESS;
759}
760
761
762/** @callback_method_impl{FNCPUMWRMSR} */
763static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
764{
765 /* Pentium4 allows writing, but all bits are ignored. */
766 return VINF_SUCCESS;
767}
768
769
770/** @callback_method_impl{FNCPUMRDMSR} */
771static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
772{
773 /** @todo implement IA32_PERFCTL. */
774 *puValue = 0;
775 return VINF_SUCCESS;
776}
777
778
779/** @callback_method_impl{FNCPUMWRMSR} */
780static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
781{
782 /** @todo implement IA32_PERFCTL. */
783 return VINF_SUCCESS;
784}
785
786
787/** @callback_method_impl{FNCPUMRDMSR} */
788static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32FixedCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
789{
790 /** @todo implement IA32_FIXED_CTRn (fixed performance counters). */
791 *puValue = 0;
792 return VINF_SUCCESS;
793}
794
795
796/** @callback_method_impl{FNCPUMWRMSR} */
797static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32FixedCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
798{
799 /** @todo implement IA32_FIXED_CTRn (fixed performance counters). */
800 return VINF_SUCCESS;
801}
802
803
804/** @callback_method_impl{FNCPUMRDMSR} */
805static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfCapabilities(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
806{
807 /** @todo implement performance counters. */
808 *puValue = 0;
809 return VINF_SUCCESS;
810}
811
812
813/** @callback_method_impl{FNCPUMWRMSR} */
814static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfCapabilities(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
815{
816 /** @todo implement performance counters. */
817 return VINF_SUCCESS;
818}
819
820
821/** @callback_method_impl{FNCPUMRDMSR} */
822static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32FixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
823{
824 /** @todo implement performance counters. */
825 *puValue = 0;
826 return VINF_SUCCESS;
827}
828
829
830/** @callback_method_impl{FNCPUMWRMSR} */
831static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32FixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
832{
833 /** @todo implement performance counters. */
834 return VINF_SUCCESS;
835}
836
837
838/** @callback_method_impl{FNCPUMRDMSR} */
839static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
840{
841 /** @todo implement performance counters. */
842 *puValue = 0;
843 return VINF_SUCCESS;
844}
845
846
847/** @callback_method_impl{FNCPUMWRMSR} */
848static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
849{
850 /** @todo implement performance counters. */
851 return VINF_SUCCESS;
852}
853
854
855/** @callback_method_impl{FNCPUMRDMSR} */
856static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
857{
858 /** @todo implement performance counters. */
859 *puValue = 0;
860 return VINF_SUCCESS;
861}
862
863
864/** @callback_method_impl{FNCPUMWRMSR} */
865static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
866{
867 /** @todo implement performance counters. */
868 return VINF_SUCCESS;
869}
870
871
872/** @callback_method_impl{FNCPUMRDMSR} */
873static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
874{
875 /** @todo implement performance counters. */
876 *puValue = 0;
877 return VINF_SUCCESS;
878}
879
880
881/** @callback_method_impl{FNCPUMWRMSR} */
882static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
883{
884 /** @todo implement performance counters. */
885 return VINF_SUCCESS;
886}
887
888
889/** @callback_method_impl{FNCPUMRDMSR} */
890static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PebsEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
891{
892 /** @todo implement performance counters. */
893 *puValue = 0;
894 return VINF_SUCCESS;
895}
896
897
898/** @callback_method_impl{FNCPUMWRMSR} */
899static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PebsEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
900{
901 /** @todo implement performance counters. */
902 return VINF_SUCCESS;
903}
904
905
906/** @callback_method_impl{FNCPUMRDMSR} */
907static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ClockModulation(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
908{
909 /** @todo implement IA32_CLOCK_MODULATION. */
910 *puValue = 0;
911 return VINF_SUCCESS;
912}
913
914
915/** @callback_method_impl{FNCPUMWRMSR} */
916static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ClockModulation(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
917{
918 /** @todo implement IA32_CLOCK_MODULATION. */
919 return VINF_SUCCESS;
920}
921
922
923/** @callback_method_impl{FNCPUMRDMSR} */
924static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ThermInterrupt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
925{
926 /** @todo implement IA32_THERM_INTERRUPT. */
927 *puValue = 0;
928 return VINF_SUCCESS;
929}
930
931
932/** @callback_method_impl{FNCPUMWRMSR} */
933static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ThermInterrupt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
934{
935 /** @todo implement IA32_THERM_STATUS. */
936 return VINF_SUCCESS;
937}
938
939
940/** @callback_method_impl{FNCPUMRDMSR} */
941static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ThermStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
942{
943 /** @todo implement IA32_THERM_STATUS. */
944 *puValue = 0;
945 return VINF_SUCCESS;
946}
947
948
949/** @callback_method_impl{FNCPUMWRMSR} */
950static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ThermStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
951{
952 /** @todo implement IA32_THERM_INTERRUPT. */
953 return VINF_SUCCESS;
954}
955
956
957/** @callback_method_impl{FNCPUMRDMSR} */
958static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32Therm2Ctl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
959{
960 /** @todo implement IA32_THERM2_CTL. */
961 *puValue = 0;
962 return VINF_SUCCESS;
963}
964
965
966/** @callback_method_impl{FNCPUMWRMSR} */
967static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32Therm2Ctl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
968{
969 /** @todo implement IA32_THERM2_CTL. */
970 return VINF_SUCCESS;
971}
972
973
974/** @callback_method_impl{FNCPUMRDMSR} */
975static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MiscEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
976{
977 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
978 return VINF_SUCCESS;
979}
980
981
982/** @callback_method_impl{FNCPUMWRMSR} */
983static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MiscEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
984{
985#ifdef LOG_ENABLED
986 uint64_t const uOld = pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
987#endif
988
989 /* Unsupported bits are generally ignored and stripped by the MSR range
990 entry that got us here. So, we just need to preserve fixed bits. */
991 pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = uValue
992 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
993 | MSR_IA32_MISC_ENABLE_BTS_UNAVAIL;
994
995 Log(("CPUM: IA32_MISC_ENABLE; old=%#llx written=%#llx => %#llx\n",
996 uOld, uValue, pVCpu->cpum.s.GuestMsrs.msr.MiscEnable));
997
998 /** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
999 /** @todo Wire up MSR_IA32_MISC_ENABLE_XD_DISABLE. */
1000 return VINF_SUCCESS;
1001}
1002
1003
1004/** @callback_method_impl{FNCPUMRDMSR} */
1005static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McCtlStatusAddrMiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1006{
1007 /** @todo Implement machine check exception injection. */
1008 switch (idMsr & 3)
1009 {
1010 case 0:
1011 case 1:
1012 *puValue = 0;
1013 break;
1014
1015 /* The ADDR and MISC registers aren't accessible since the
1016 corresponding STATUS bits are zero. */
1017 case 2:
1018 Log(("CPUM: Reading IA32_MCi_ADDR %#x -> #GP\n", idMsr));
1019 return VERR_CPUM_RAISE_GP_0;
1020 case 3:
1021 Log(("CPUM: Reading IA32_MCi_MISC %#x -> #GP\n", idMsr));
1022 return VERR_CPUM_RAISE_GP_0;
1023 }
1024 return VINF_SUCCESS;
1025}
1026
1027
1028/** @callback_method_impl{FNCPUMWRMSR} */
1029static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McCtlStatusAddrMiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1030{
1031 switch (idMsr & 3)
1032 {
1033 case 0:
1034 /* Ignore writes to the CTL register. */
1035 break;
1036
1037 case 1:
1038 /* According to specs, the STATUS register can only be written to
1039 with the value 0. VBoxCpuReport thinks different for a
1040 Pentium M Dothan, but implementing according to specs now. */
1041 if (uValue != 0)
1042 {
1043 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_STATUS %#x -> #GP\n", uValue, idMsr));
1044 return VERR_CPUM_RAISE_GP_0;
1045 }
1046 break;
1047
1048 /* Specs states that ADDR and MISC can be cleared by writing zeros.
1049 Writing 1s will GP. Need to figure out how this relates to the
1050 ADDRV and MISCV status flags. If writing is independent of those
1051 bits, we need to know whether the CPU really implements them since
1052 that is exposed by writing 0 to them.
1053 Implementing the solution with the fewer GPs for now. */
1054 case 2:
1055 if (uValue != 0)
1056 {
1057 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_ADDR %#x -> #GP\n", uValue, idMsr));
1058 return VERR_CPUM_RAISE_GP_0;
1059 }
1060 break;
1061 case 3:
1062 if (uValue != 0)
1063 {
1064 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_MISC %#x -> #GP\n", uValue, idMsr));
1065 return VERR_CPUM_RAISE_GP_0;
1066 }
1067 break;
1068 }
1069 return VINF_SUCCESS;
1070}
1071
1072
1073/** @callback_method_impl{FNCPUMRDMSR} */
1074static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McNCtl2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1075{
1076 /** @todo Implement machine check exception injection. */
1077 *puValue = 0;
1078 return VINF_SUCCESS;
1079}
1080
1081
1082/** @callback_method_impl{FNCPUMWRMSR} */
1083static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McNCtl2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1084{
1085 /** @todo Implement machine check exception injection. */
1086 return VINF_SUCCESS;
1087}
1088
1089
1090/** @callback_method_impl{FNCPUMRDMSR} */
1091static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32DsArea(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1092{
1093 /** @todo implement IA32_DS_AREA. */
1094 *puValue = 0;
1095 return VINF_SUCCESS;
1096}
1097
1098
1099/** @callback_method_impl{FNCPUMWRMSR} */
1100static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32DsArea(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1101{
1102 return VINF_SUCCESS;
1103}
1104
1105
1106/** @callback_method_impl{FNCPUMRDMSR} */
1107static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32TscDeadline(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1108{
1109 /** @todo implement TSC deadline timer. */
1110 *puValue = 0;
1111 return VINF_SUCCESS;
1112}
1113
1114
1115/** @callback_method_impl{FNCPUMWRMSR} */
1116static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32TscDeadline(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1117{
1118 /** @todo implement TSC deadline timer. */
1119 return VINF_SUCCESS;
1120}
1121
1122
1123/** @callback_method_impl{FNCPUMRDMSR} */
1124static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32X2ApicN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1125{
1126 int rc = PDMApicReadMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, puValue);
1127 if (rc != VINF_SUCCESS)
1128 {
1129 Log(("CPUM: X2APIC %#x read => %Rrc => #GP\n", idMsr, rc));
1130 return VERR_CPUM_RAISE_GP_0;
1131 }
1132 return VINF_SUCCESS;
1133}
1134
1135
1136/** @callback_method_impl{FNCPUMWRMSR} */
1137static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32X2ApicN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1138{
1139 int rc = PDMApicWriteMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, uValue);
1140 if (rc != VINF_SUCCESS)
1141 {
1142 Log(("CPUM: X2APIC %#x write %#llx => %Rrc => #GP\n", idMsr, rc, uValue));
1143 return VERR_CPUM_RAISE_GP_0;
1144 }
1145 return VINF_SUCCESS;
1146}
1147
1148
1149/** @callback_method_impl{FNCPUMRDMSR} */
1150static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32DebugInterface(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1151{
1152 /** @todo IA32_DEBUG_INTERFACE (no docs) */
1153 *puValue = 0;
1154 return VINF_SUCCESS;
1155}
1156
1157
1158/** @callback_method_impl{FNCPUMWRMSR} */
1159static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32DebugInterface(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1160{
1161 /** @todo IA32_DEBUG_INTERFACE (no docs) */
1162 return VINF_SUCCESS;
1163}
1164
1165
1166/** @callback_method_impl{FNCPUMRDMSR} */
1167static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1168{
1169 *puValue = 0;
1170 return VINF_SUCCESS;
1171}
1172
1173
1174/** @callback_method_impl{FNCPUMRDMSR} */
1175static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxPinbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1176{
1177 *puValue = 0;
1178 return VINF_SUCCESS;
1179}
1180
1181
1182/** @callback_method_impl{FNCPUMRDMSR} */
1183static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxProcbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1184{
1185 *puValue = 0;
1186 return VINF_SUCCESS;
1187}
1188
1189
1190/** @callback_method_impl{FNCPUMRDMSR} */
1191static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxExitCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1192{
1193 *puValue = 0;
1194 return VINF_SUCCESS;
1195}
1196
1197
1198/** @callback_method_impl{FNCPUMRDMSR} */
1199static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxEntryCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1200{
1201 *puValue = 0;
1202 return VINF_SUCCESS;
1203}
1204
1205
1206/** @callback_method_impl{FNCPUMRDMSR} */
1207static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxMisc(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1208{
1209 *puValue = 0;
1210 return VINF_SUCCESS;
1211}
1212
1213
1214/** @callback_method_impl{FNCPUMRDMSR} */
1215static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr0Fixed0(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1216{
1217 *puValue = 0;
1218 return VINF_SUCCESS;
1219}
1220
1221
1222/** @callback_method_impl{FNCPUMRDMSR} */
1223static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr0Fixed1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1224{
1225 *puValue = 0;
1226 return VINF_SUCCESS;
1227}
1228
1229
1230/** @callback_method_impl{FNCPUMRDMSR} */
1231static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr4Fixed0(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1232{
1233 *puValue = 0;
1234 return VINF_SUCCESS;
1235}
1236
1237
1238/** @callback_method_impl{FNCPUMRDMSR} */
1239static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr4Fixed1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1240{
1241 *puValue = 0;
1242 return VINF_SUCCESS;
1243}
1244
1245
1246/** @callback_method_impl{FNCPUMRDMSR} */
1247static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxVmcsEnum(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1248{
1249 *puValue = 0;
1250 return VINF_SUCCESS;
1251}
1252
1253
1254/** @callback_method_impl{FNCPUMRDMSR} */
1255static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxProcBasedCtls2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1256{
1257 *puValue = 0;
1258 return VINF_SUCCESS;
1259}
1260
1261
1262/** @callback_method_impl{FNCPUMRDMSR} */
1263static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxEptVpidCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1264{
1265 *puValue = 0;
1266 return VINF_SUCCESS;
1267}
1268
1269
1270/** @callback_method_impl{FNCPUMRDMSR} */
1271static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTruePinbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1272{
1273 *puValue = 0;
1274 return VINF_SUCCESS;
1275}
1276
1277
1278/** @callback_method_impl{FNCPUMRDMSR} */
1279static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTrueProcbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1280{
1281 *puValue = 0;
1282 return VINF_SUCCESS;
1283}
1284
1285
1286/** @callback_method_impl{FNCPUMRDMSR} */
1287static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTrueExitCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1288{
1289 *puValue = 0;
1290 return VINF_SUCCESS;
1291}
1292
1293
1294/** @callback_method_impl{FNCPUMRDMSR} */
1295static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTrueEntryCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1296{
1297 *puValue = 0;
1298 return VINF_SUCCESS;
1299}
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310/*
1311 * AMD64
1312 * AMD64
1313 * AMD64
1314 */
1315
1316
1317/** @callback_method_impl{FNCPUMRDMSR} */
1318static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64Efer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1319{
1320 *puValue = pVCpu->cpum.s.Guest.msrEFER;
1321 return VINF_SUCCESS;
1322}
1323
1324
1325/** @callback_method_impl{FNCPUMWRMSR} */
1326static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64Efer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1327{
1328 PVM pVM = pVCpu->CTX_SUFF(pVM);
1329 uint64_t const uOldEfer = pVCpu->cpum.s.Guest.msrEFER;
1330 uint32_t const fExtFeatures = pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1331 ? pVM->cpum.s.aGuestCpuIdExt[1].edx
1332 : 0;
1333 uint64_t fMask = 0;
1334 uint64_t fIgnoreMask = MSR_K6_EFER_LMA;
1335
1336 /* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
1337 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_NX)
1338 fMask |= MSR_K6_EFER_NXE;
1339 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
1340 fMask |= MSR_K6_EFER_LME;
1341 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
1342 fMask |= MSR_K6_EFER_SCE;
1343 if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1344 fMask |= MSR_K6_EFER_FFXSR;
1345
1346 /* #GP(0) If anything outside the allowed bits is set. */
1347 if (uValue & ~(fIgnoreMask | fMask))
1348 {
1349 Log(("CPUM: Settings disallowed EFER bit. uValue=%#RX64 fAllowed=%#RX64 -> #GP(0)\n", uValue, fMask));
1350 return VERR_CPUM_RAISE_GP_0;
1351 }
1352
1353 /* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if
1354 paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1355 if ( (uOldEfer & MSR_K6_EFER_LME) != (uValue & fMask & MSR_K6_EFER_LME)
1356 && (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG))
1357 {
1358 Log(("CPUM: Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
1359 return VERR_CPUM_RAISE_GP_0;
1360 }
1361
1362 /* There are a few more: e.g. MSR_K6_EFER_LMSLE */
1363 AssertMsg(!(uValue & ~(MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA /* ignored anyway */ | MSR_K6_EFER_SCE | MSR_K6_EFER_FFXSR)),
1364 ("Unexpected value %RX64\n", uValue));
1365 pVCpu->cpum.s.Guest.msrEFER = (uOldEfer & ~fMask) | (uValue & fMask);
1366
1367 /* AMD64 Architecture Programmer's Manual: 15.15 TLB Control; flush the TLB
1368 if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
1369 if ( (uOldEfer & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA))
1370 != (pVCpu->cpum.s.Guest.msrEFER & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA)))
1371 {
1372 /// @todo PGMFlushTLB(pVCpu, cr3, true /*fGlobal*/);
1373 HMFlushTLB(pVCpu);
1374
1375 /* Notify PGM about NXE changes. */
1376 if ( (uOldEfer & MSR_K6_EFER_NXE)
1377 != (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE))
1378 PGMNotifyNxeChanged(pVCpu, !(uOldEfer & MSR_K6_EFER_NXE));
1379 }
1380 return VINF_SUCCESS;
1381}
1382
1383
1384/** @callback_method_impl{FNCPUMRDMSR} */
1385static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64SyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1386{
1387 *puValue = pVCpu->cpum.s.Guest.msrSTAR;
1388 return VINF_SUCCESS;
1389}
1390
1391
1392/** @callback_method_impl{FNCPUMWRMSR} */
1393static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64SyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1394{
1395 pVCpu->cpum.s.Guest.msrSTAR = uValue;
1396 return VINF_SUCCESS;
1397}
1398
1399
1400/** @callback_method_impl{FNCPUMRDMSR} */
1401static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64LongSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1402{
1403 *puValue = pVCpu->cpum.s.Guest.msrLSTAR;
1404 return VINF_SUCCESS;
1405}
1406
1407
1408/** @callback_method_impl{FNCPUMWRMSR} */
1409static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64LongSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1410{
1411 if (!X86_IS_CANONICAL(uValue))
1412 {
1413 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
1414 return VERR_CPUM_RAISE_GP_0;
1415 }
1416 pVCpu->cpum.s.Guest.msrLSTAR = uValue;
1417 return VINF_SUCCESS;
1418}
1419
1420
1421/** @callback_method_impl{FNCPUMRDMSR} */
1422static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64CompSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1423{
1424 *puValue = pVCpu->cpum.s.Guest.msrCSTAR;
1425 return VINF_SUCCESS;
1426}
1427
1428
1429/** @callback_method_impl{FNCPUMWRMSR} */
1430static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64CompSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1431{
1432 if (!X86_IS_CANONICAL(uValue))
1433 {
1434 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
1435 return VERR_CPUM_RAISE_GP_0;
1436 }
1437 pVCpu->cpum.s.Guest.msrCSTAR = uValue;
1438 return VINF_SUCCESS;
1439}
1440
1441
1442/** @callback_method_impl{FNCPUMRDMSR} */
1443static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64SyscallFlagMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1444{
1445 *puValue = pVCpu->cpum.s.Guest.msrSFMASK;
1446 return VINF_SUCCESS;
1447}
1448
1449
1450/** @callback_method_impl{FNCPUMWRMSR} */
1451static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64SyscallFlagMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1452{
1453 pVCpu->cpum.s.Guest.msrSFMASK = uValue;
1454 return VINF_SUCCESS;
1455}
1456
1457
1458/** @callback_method_impl{FNCPUMRDMSR} */
1459static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64FsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1460{
1461 *puValue = pVCpu->cpum.s.Guest.fs.u64Base;
1462 return VINF_SUCCESS;
1463}
1464
1465
1466/** @callback_method_impl{FNCPUMWRMSR} */
1467static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64FsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1468{
1469 pVCpu->cpum.s.Guest.fs.u64Base = uValue;
1470 return VINF_SUCCESS;
1471}
1472
1473
1474/** @callback_method_impl{FNCPUMRDMSR} */
1475static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64GsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1476{
1477 *puValue = pVCpu->cpum.s.Guest.gs.u64Base;
1478 return VINF_SUCCESS;
1479}
1480
1481/** @callback_method_impl{FNCPUMWRMSR} */
1482static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64GsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1483{
1484 pVCpu->cpum.s.Guest.gs.u64Base = uValue;
1485 return VINF_SUCCESS;
1486}
1487
1488
1489
1490/** @callback_method_impl{FNCPUMRDMSR} */
1491static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64KernelGsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1492{
1493 *puValue = pVCpu->cpum.s.Guest.msrKERNELGSBASE;
1494 return VINF_SUCCESS;
1495}
1496
1497/** @callback_method_impl{FNCPUMWRMSR} */
1498static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64KernelGsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1499{
1500 pVCpu->cpum.s.Guest.msrKERNELGSBASE = uValue;
1501 return VINF_SUCCESS;
1502}
1503
1504
1505/** @callback_method_impl{FNCPUMRDMSR} */
1506static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64TscAux(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1507{
1508 *puValue = pVCpu->cpum.s.GuestMsrs.msr.TscAux;
1509 return VINF_SUCCESS;
1510}
1511
1512/** @callback_method_impl{FNCPUMWRMSR} */
1513static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64TscAux(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1514{
1515 pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
1516 return VINF_SUCCESS;
1517}
1518
1519
1520/*
1521 * Intel specific
1522 * Intel specific
1523 * Intel specific
1524 */
1525
1526/** @callback_method_impl{FNCPUMRDMSR} */
1527static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelEblCrPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1528{
1529 /** @todo recalc clock frequency ratio? */
1530 *puValue = pRange->uValue;
1531 return VINF_SUCCESS;
1532}
1533
1534
1535/** @callback_method_impl{FNCPUMWRMSR} */
1536static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelEblCrPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1537{
1538 /** @todo Write EBL_CR_POWERON: Remember written bits. */
1539 return VINF_SUCCESS;
1540}
1541
1542
1543/** @callback_method_impl{FNCPUMRDMSR} */
1544static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7CoreThreadCount(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1545{
1546 /* Note! According to cpuid_set_info in XNU (10.7.0), Westmere CPU only
1547 have a 4-bit core count. */
1548 uint16_t cCores = pVCpu->CTX_SUFF(pVM)->cCpus;
1549 uint16_t cThreads = cCores; /** @todo hyper-threading. */
1550 *puValue = RT_MAKE_U32(cThreads, cCores);
1551 return VINF_SUCCESS;
1552}
1553
1554
1555/** @callback_method_impl{FNCPUMRDMSR} */
1556static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP4EbcHardPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1557{
1558 /** @todo P4 hard power on config */
1559 *puValue = pRange->uValue;
1560 return VINF_SUCCESS;
1561}
1562
1563
1564/** @callback_method_impl{FNCPUMWRMSR} */
1565static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP4EbcHardPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1566{
1567 /** @todo P4 hard power on config */
1568 return VINF_SUCCESS;
1569}
1570
1571
1572/** @callback_method_impl{FNCPUMRDMSR} */
1573static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP4EbcSoftPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1574{
1575 /** @todo P4 soft power on config */
1576 *puValue = pRange->uValue;
1577 return VINF_SUCCESS;
1578}
1579
1580
1581/** @callback_method_impl{FNCPUMWRMSR} */
1582static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP4EbcSoftPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1583{
1584 /** @todo P4 soft power on config */
1585 return VINF_SUCCESS;
1586}
1587
1588
1589/** @callback_method_impl{FNCPUMRDMSR} */
1590static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP4EbcFrequencyId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1591{
1592 uint64_t uValue;
1593 PVM pVM = pVCpu->CTX_SUFF(pVM);
1594 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
1595 if (pVM->cpum.s.GuestFeatures.uModel >= 2)
1596 {
1597 if (uScalableBusHz <= CPUM_SBUSFREQ_100MHZ && pVM->cpum.s.GuestFeatures.uModel <= 2)
1598 {
1599 uScalableBusHz = CPUM_SBUSFREQ_100MHZ;
1600 uValue = 0;
1601 }
1602 else if (uScalableBusHz <= CPUM_SBUSFREQ_133MHZ)
1603 {
1604 uScalableBusHz = CPUM_SBUSFREQ_133MHZ;
1605 uValue = 1;
1606 }
1607 else if (uScalableBusHz <= CPUM_SBUSFREQ_167MHZ)
1608 {
1609 uScalableBusHz = CPUM_SBUSFREQ_167MHZ;
1610 uValue = 3;
1611 }
1612 else if (uScalableBusHz <= CPUM_SBUSFREQ_200MHZ)
1613 {
1614 uScalableBusHz = CPUM_SBUSFREQ_200MHZ;
1615 uValue = 2;
1616 }
1617 else if (uScalableBusHz <= CPUM_SBUSFREQ_267MHZ && pVM->cpum.s.GuestFeatures.uModel > 2)
1618 {
1619 uScalableBusHz = CPUM_SBUSFREQ_267MHZ;
1620 uValue = 0;
1621 }
1622 else
1623 {
1624 uScalableBusHz = CPUM_SBUSFREQ_333MHZ;
1625 uValue = 6;
1626 }
1627 uValue <<= 16;
1628
1629 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
1630 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
1631 uValue |= (uint32_t)uTscRatio << 24;
1632
1633 uValue |= pRange->uValue & ~UINT64_C(0xff0f0000);
1634 }
1635 else
1636 {
1637 /* Probably more stuff here, but intel doesn't want to tell us. */
1638 uValue = pRange->uValue;
1639 uValue &= ~(RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23)); /* 100 MHz is only documented value */
1640 }
1641
1642 *puValue = uValue;
1643 return VINF_SUCCESS;
1644}
1645
1646
1647/** @callback_method_impl{FNCPUMWRMSR} */
1648static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP4EbcFrequencyId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1649{
1650 /** @todo P4 bus frequency config */
1651 return VINF_SUCCESS;
1652}
1653
1654
1655/** @callback_method_impl{FNCPUMRDMSR} */
1656static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP6FsbFrequency(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1657{
1658 /* Convert the scalable bus frequency to the encoding in the intel manual (for core+). */
1659 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVCpu->CTX_SUFF(pVM));
1660 if (uScalableBusHz <= CPUM_SBUSFREQ_100MHZ)
1661 *puValue = 5;
1662 else if (uScalableBusHz <= CPUM_SBUSFREQ_133MHZ)
1663 *puValue = 1;
1664 else if (uScalableBusHz <= CPUM_SBUSFREQ_167MHZ)
1665 *puValue = 3;
1666 else if (uScalableBusHz <= CPUM_SBUSFREQ_200MHZ)
1667 *puValue = 2;
1668 else if (uScalableBusHz <= CPUM_SBUSFREQ_267MHZ)
1669 *puValue = 0;
1670 else if (uScalableBusHz <= CPUM_SBUSFREQ_333MHZ)
1671 *puValue = 4;
1672 else /*if (uScalableBusHz <= CPUM_SBUSFREQ_400MHZ)*/
1673 *puValue = 6;
1674
1675 *puValue |= pRange->uValue & ~UINT64_C(0x7);
1676
1677 return VINF_SUCCESS;
1678}
1679
1680
1681/** @callback_method_impl{FNCPUMRDMSR} */
1682static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelPlatformInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1683{
1684 /* Just indicate a fixed TSC, no turbo boost, no programmable anything. */
1685 PVM pVM = pVCpu->CTX_SUFF(pVM);
1686 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
1687 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
1688 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
1689 uint64_t uValue = ((uint32_t)uTscRatio << 8) /* TSC invariant frequency. */
1690 | ((uint64_t)uTscRatio << 40); /* The max turbo frequency. */
1691
1692 /* Ivy bridge has a minimum operating ratio as well. */
1693 if (true) /** @todo detect sandy bridge. */
1694 uValue |= (uint64_t)uTscRatio << 48;
1695
1696 *puValue = uValue;
1697 return VINF_SUCCESS;
1698}
1699
1700
1701/** @callback_method_impl{FNCPUMRDMSR} */
1702static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelFlexRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1703{
1704 uint64_t uValue = pRange->uValue & ~UINT64_C(0x1ff00);
1705
1706 PVM pVM = pVCpu->CTX_SUFF(pVM);
1707 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
1708 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
1709 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
1710 uValue |= (uint32_t)uTscRatio << 8;
1711
1712 *puValue = uValue;
1713 return VINF_SUCCESS;
1714}
1715
1716
1717/** @callback_method_impl{FNCPUMWRMSR} */
1718static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelFlexRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1719{
1720 /** @todo implement writing MSR_FLEX_RATIO. */
1721 return VINF_SUCCESS;
1722}
1723
1724
1725/** @callback_method_impl{FNCPUMRDMSR} */
1726static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelPkgCStConfigControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1727{
1728 *puValue = pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl;
1729 return VINF_SUCCESS;
1730}
1731
1732
1733/** @callback_method_impl{FNCPUMWRMSR} */
1734static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelPkgCStConfigControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1735{
1736 if (pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl & RT_BIT_64(15))
1737 {
1738 Log(("CPUM: WRMDR %#x (%s), %#llx: Write protected -> #GP\n", idMsr, pRange->szName, uValue));
1739 return VERR_CPUM_RAISE_GP_0;
1740 }
1741#if 0 /** @todo check what real (old) hardware does. */
1742 if ((uValue & 7) >= 5)
1743 {
1744 Log(("CPUM: WRMDR %#x (%s), %#llx: Invalid limit (%d) -> #GP\n", idMsr, pRange->szName, uValue, (uint32_t)(uValue & 7)));
1745 return VERR_CPUM_RAISE_GP_0;
1746 }
1747#endif
1748 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = uValue;
1749 return VINF_SUCCESS;
1750}
1751
1752
1753/** @callback_method_impl{FNCPUMRDMSR} */
1754static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelPmgIoCaptureBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1755{
1756 /** @todo implement I/O mwait wakeup. */
1757 *puValue = 0;
1758 return VINF_SUCCESS;
1759}
1760
1761
1762/** @callback_method_impl{FNCPUMWRMSR} */
1763static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelPmgIoCaptureBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1764{
1765 /** @todo implement I/O mwait wakeup. */
1766 return VINF_SUCCESS;
1767}
1768
1769
1770/** @callback_method_impl{FNCPUMRDMSR} */
1771static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchFromToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1772{
1773 /** @todo implement last branch records. */
1774 *puValue = 0;
1775 return VINF_SUCCESS;
1776}
1777
1778
1779/** @callback_method_impl{FNCPUMWRMSR} */
1780static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchFromToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1781{
1782 /** @todo implement last branch records. */
1783 return VINF_SUCCESS;
1784}
1785
1786
1787/** @callback_method_impl{FNCPUMRDMSR} */
1788static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchFromN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1789{
1790 /** @todo implement last branch records. */
1791 *puValue = 0;
1792 return VINF_SUCCESS;
1793}
1794
1795
1796/** @callback_method_impl{FNCPUMWRMSR} */
1797static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchFromN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1798{
1799 /** @todo implement last branch records. */
1800 /** @todo Probing indicates that bit 63 is settable on SandyBridge, at least
1801 * if the rest of the bits are zero. Automatic sign extending?
1802 * Investigate! */
1803 if (!X86_IS_CANONICAL(uValue))
1804 {
1805 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
1806 return VERR_CPUM_RAISE_GP_0;
1807 }
1808 return VINF_SUCCESS;
1809}
1810
1811
1812/** @callback_method_impl{FNCPUMRDMSR} */
1813static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1814{
1815 /** @todo implement last branch records. */
1816 *puValue = 0;
1817 return VINF_SUCCESS;
1818}
1819
1820
1821/** @callback_method_impl{FNCPUMWRMSR} */
1822static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1823{
1824 /** @todo implement last branch records. */
1825 /** @todo Probing indicates that bit 63 is settable on SandyBridge, at least
1826 * if the rest of the bits are zero. Automatic sign extending?
1827 * Investigate! */
1828 if (!X86_IS_CANONICAL(uValue))
1829 {
1830 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
1831 return VERR_CPUM_RAISE_GP_0;
1832 }
1833 return VINF_SUCCESS;
1834}
1835
1836
1837/** @callback_method_impl{FNCPUMRDMSR} */
1838static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchTos(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1839{
1840 /** @todo implement last branch records. */
1841 *puValue = 0;
1842 return VINF_SUCCESS;
1843}
1844
1845
1846/** @callback_method_impl{FNCPUMWRMSR} */
1847static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchTos(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1848{
1849 /** @todo implement last branch records. */
1850 return VINF_SUCCESS;
1851}
1852
1853
1854/** @callback_method_impl{FNCPUMRDMSR} */
1855static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelBblCrCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1856{
1857 *puValue = pRange->uValue;
1858 return VINF_SUCCESS;
1859}
1860
1861
1862/** @callback_method_impl{FNCPUMWRMSR} */
1863static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelBblCrCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1864{
1865 return VINF_SUCCESS;
1866}
1867
1868
1869/** @callback_method_impl{FNCPUMRDMSR} */
1870static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelBblCrCtl3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1871{
1872 *puValue = pRange->uValue;
1873 return VINF_SUCCESS;
1874}
1875
1876
1877/** @callback_method_impl{FNCPUMWRMSR} */
1878static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelBblCrCtl3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1879{
1880 return VINF_SUCCESS;
1881}
1882
1883
1884/** @callback_method_impl{FNCPUMRDMSR} */
1885static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7TemperatureTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1886{
1887 *puValue = pRange->uValue;
1888 return VINF_SUCCESS;
1889}
1890
1891
1892/** @callback_method_impl{FNCPUMWRMSR} */
1893static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7TemperatureTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1894{
1895 return VINF_SUCCESS;
1896}
1897
1898
1899/** @callback_method_impl{FNCPUMRDMSR} */
1900static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7MsrOffCoreResponseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1901{
1902 /** @todo machine check. */
1903 *puValue = pRange->uValue;
1904 return VINF_SUCCESS;
1905}
1906
1907
1908/** @callback_method_impl{FNCPUMWRMSR} */
1909static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7MsrOffCoreResponseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1910{
1911 /** @todo machine check. */
1912 return VINF_SUCCESS;
1913}
1914
1915
1916/** @callback_method_impl{FNCPUMRDMSR} */
1917static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7MiscPwrMgmt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1918{
1919 *puValue = 0;
1920 return VINF_SUCCESS;
1921}
1922
1923
1924/** @callback_method_impl{FNCPUMWRMSR} */
1925static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7MiscPwrMgmt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1926{
1927 return VINF_SUCCESS;
1928}
1929
1930
1931/** @callback_method_impl{FNCPUMRDMSR} */
1932static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP6CrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1933{
1934 int rc = CPUMGetGuestCRx(pVCpu, pRange->uValue, puValue);
1935 AssertRC(rc);
1936 return VINF_SUCCESS;
1937}
1938
1939
1940/** @callback_method_impl{FNCPUMWRMSR} */
1941static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP6CrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1942{
1943 /* This CRx interface differs from the MOV CRx, GReg interface in that
1944 #GP(0) isn't raised if unsupported bits are written to. Instead they
1945 are simply ignored and masked off. (Pentium M Dothan) */
1946 /** @todo Implement MSR_P6_CRx writing. Too much effort for very little, if
1947 * any, gain. */
1948 return VINF_SUCCESS;
1949}
1950
1951
1952/** @callback_method_impl{FNCPUMRDMSR} */
1953static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCpuId1FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1954{
1955 /** @todo implement CPUID masking. */
1956 *puValue = UINT64_MAX;
1957 return VINF_SUCCESS;
1958}
1959
1960
1961/** @callback_method_impl{FNCPUMWRMSR} */
1962static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCpuId1FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1963{
1964 /** @todo implement CPUID masking. */
1965 return VINF_SUCCESS;
1966}
1967
1968
1969/** @callback_method_impl{FNCPUMRDMSR} */
1970static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCpuId1FeatureMaskEax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1971{
1972 /** @todo implement CPUID masking. */
1973 return VINF_SUCCESS;
1974}
1975
1976
1977/** @callback_method_impl{FNCPUMWRMSR} */
1978static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCpuId1FeatureMaskEax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1979{
1980 /** @todo implement CPUID masking. */
1981 return VINF_SUCCESS;
1982}
1983
1984
1985
1986/** @callback_method_impl{FNCPUMRDMSR} */
1987static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCpuId80000001FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1988{
1989 /** @todo implement CPUID masking. */
1990 *puValue = UINT64_MAX;
1991 return VINF_SUCCESS;
1992}
1993
1994
1995/** @callback_method_impl{FNCPUMWRMSR} */
1996static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCpuId80000001FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1997{
1998 /** @todo implement CPUID masking. */
1999 return VINF_SUCCESS;
2000}
2001
2002
2003
2004/** @callback_method_impl{FNCPUMRDMSR} */
2005static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyAesNiCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2006{
2007 /** @todo implement AES-NI. */
2008 *puValue = 3; /* Bit 0 is lock bit, bit 1 disables AES-NI. That's what they say. */
2009 return VINF_SUCCESS;
2010}
2011
2012
2013/** @callback_method_impl{FNCPUMWRMSR} */
2014static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyAesNiCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2015{
2016 /** @todo implement AES-NI. */
2017 return VERR_CPUM_RAISE_GP_0;
2018}
2019
2020
2021/** @callback_method_impl{FNCPUMRDMSR} */
2022static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7TurboRatioLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2023{
2024 /** @todo implement intel C states. */
2025 *puValue = pRange->uValue;
2026 return VINF_SUCCESS;
2027}
2028
2029
2030/** @callback_method_impl{FNCPUMWRMSR} */
2031static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7TurboRatioLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2032{
2033 /** @todo implement intel C states. */
2034 return VINF_SUCCESS;
2035}
2036
2037
2038/** @callback_method_impl{FNCPUMRDMSR} */
2039static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7LbrSelect(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2040{
2041 /** @todo implement last-branch-records. */
2042 *puValue = 0;
2043 return VINF_SUCCESS;
2044}
2045
2046
2047/** @callback_method_impl{FNCPUMWRMSR} */
2048static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7LbrSelect(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2049{
2050 /** @todo implement last-branch-records. */
2051 return VINF_SUCCESS;
2052}
2053
2054
2055/** @callback_method_impl{FNCPUMRDMSR} */
2056static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyErrorControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2057{
2058 /** @todo implement memory error injection (MSR_ERROR_CONTROL). */
2059 *puValue = 0;
2060 return VINF_SUCCESS;
2061}
2062
2063
2064/** @callback_method_impl{FNCPUMWRMSR} */
2065static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyErrorControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2066{
2067 /** @todo implement memory error injection (MSR_ERROR_CONTROL). */
2068 return VINF_SUCCESS;
2069}
2070
2071
2072/** @callback_method_impl{FNCPUMRDMSR} */
2073static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7VirtualLegacyWireCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2074{
2075 /** @todo implement memory VLW? */
2076 *puValue = pRange->uValue;
2077 /* Note: A20M is known to be bit 1 as this was disclosed in spec update
2078 AAJ49/AAK51/????, which documents the inversion of this bit. The
2079 Sandy bridge CPU here has value 0x74, so it probably doesn't have a BIOS
2080 that correct things. Some guesses at the other bits:
2081 bit 2 = INTR
2082 bit 4 = SMI
2083 bit 5 = INIT
2084 bit 6 = NMI */
2085 return VINF_SUCCESS;
2086}
2087
2088
2089/** @callback_method_impl{FNCPUMRDMSR} */
2090static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7PowerCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2091{
2092 /** @todo intel power management */
2093 *puValue = 0;
2094 return VINF_SUCCESS;
2095}
2096
2097
2098/** @callback_method_impl{FNCPUMWRMSR} */
2099static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7PowerCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2100{
2101 /** @todo intel power management */
2102 return VINF_SUCCESS;
2103}
2104
2105
2106/** @callback_method_impl{FNCPUMRDMSR} */
2107static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyPebsNumAlt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2108{
2109 /** @todo intel performance counters. */
2110 *puValue = 0;
2111 return VINF_SUCCESS;
2112}
2113
2114
2115/** @callback_method_impl{FNCPUMWRMSR} */
2116static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyPebsNumAlt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2117{
2118 /** @todo intel performance counters. */
2119 return VINF_SUCCESS;
2120}
2121
2122
2123/** @callback_method_impl{FNCPUMRDMSR} */
2124static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7PebsLdLat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2125{
2126 /** @todo intel performance counters. */
2127 *puValue = 0;
2128 return VINF_SUCCESS;
2129}
2130
2131
2132/** @callback_method_impl{FNCPUMWRMSR} */
2133static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7PebsLdLat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2134{
2135 /** @todo intel performance counters. */
2136 return VINF_SUCCESS;
2137}
2138
2139
2140/** @callback_method_impl{FNCPUMRDMSR} */
2141static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7PkgCnResidencyN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2142{
2143 /** @todo intel power management. */
2144 *puValue = 0;
2145 return VINF_SUCCESS;
2146}
2147
2148
2149/** @callback_method_impl{FNCPUMRDMSR} */
2150static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7CoreCnResidencyN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2151{
2152 /** @todo intel power management. */
2153 *puValue = 0;
2154 return VINF_SUCCESS;
2155}
2156
2157
2158/** @callback_method_impl{FNCPUMRDMSR} */
2159static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyVrCurrentConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2160{
2161 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2162 *puValue = 0;
2163 return VINF_SUCCESS;
2164}
2165
2166
2167/** @callback_method_impl{FNCPUMWRMSR} */
2168static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyVrCurrentConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2169{
2170 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2171 return VINF_SUCCESS;
2172}
2173
2174
2175/** @callback_method_impl{FNCPUMRDMSR} */
2176static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyVrMiscConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2177{
2178 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2179 *puValue = 0;
2180 return VINF_SUCCESS;
2181}
2182
2183
2184/** @callback_method_impl{FNCPUMWRMSR} */
2185static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyVrMiscConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2186{
2187 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2188 return VINF_SUCCESS;
2189}
2190
2191
2192/** @callback_method_impl{FNCPUMRDMSR} */
2193static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyRaplPowerUnit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2194{
2195 /** @todo intel RAPL. */
2196 *puValue = pRange->uValue;
2197 return VINF_SUCCESS;
2198}
2199
2200
2201/** @callback_method_impl{FNCPUMRDMSR} */
2202static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyPkgCnIrtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2203{
2204 /** @todo intel power management. */
2205 *puValue = 0;
2206 return VINF_SUCCESS;
2207}
2208
2209
2210/** @callback_method_impl{FNCPUMWRMSR} */
2211static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyPkgCnIrtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2212{
2213 /** @todo intel power management. */
2214 return VINF_SUCCESS;
2215}
2216
2217
2218/** @callback_method_impl{FNCPUMRDMSR} */
2219static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyPkgC2Residency(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2220{
2221 /** @todo intel power management. */
2222 *puValue = 0;
2223 return VINF_SUCCESS;
2224}
2225
2226
2227/** @callback_method_impl{FNCPUMRDMSR} */
2228static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2229{
2230 /** @todo intel RAPL. */
2231 *puValue = 0;
2232 return VINF_SUCCESS;
2233}
2234
2235
2236/** @callback_method_impl{FNCPUMWRMSR} */
2237static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPkgPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2238{
2239 /** @todo intel RAPL. */
2240 return VINF_SUCCESS;
2241}
2242
2243
2244/** @callback_method_impl{FNCPUMRDMSR} */
2245static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgEnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2246{
2247 /** @todo intel power management. */
2248 *puValue = 0;
2249 return VINF_SUCCESS;
2250}
2251
2252
2253/** @callback_method_impl{FNCPUMRDMSR} */
2254static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgPerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2255{
2256 /** @todo intel power management. */
2257 *puValue = 0;
2258 return VINF_SUCCESS;
2259}
2260
2261
2262/** @callback_method_impl{FNCPUMRDMSR} */
2263static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgPowerInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2264{
2265 /** @todo intel power management. */
2266 *puValue = 0;
2267 return VINF_SUCCESS;
2268}
2269
2270
2271/** @callback_method_impl{FNCPUMRDMSR} */
2272static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2273{
2274 /** @todo intel RAPL. */
2275 *puValue = 0;
2276 return VINF_SUCCESS;
2277}
2278
2279
2280/** @callback_method_impl{FNCPUMWRMSR} */
2281static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplDramPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2282{
2283 /** @todo intel RAPL. */
2284 return VINF_SUCCESS;
2285}
2286
2287
2288/** @callback_method_impl{FNCPUMRDMSR} */
2289static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramEnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2290{
2291 /** @todo intel power management. */
2292 *puValue = 0;
2293 return VINF_SUCCESS;
2294}
2295
2296
2297/** @callback_method_impl{FNCPUMRDMSR} */
2298static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramPerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2299{
2300 /** @todo intel power management. */
2301 *puValue = 0;
2302 return VINF_SUCCESS;
2303}
2304
2305
2306/** @callback_method_impl{FNCPUMRDMSR} */
2307static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramPowerInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2308{
2309 /** @todo intel power management. */
2310 *puValue = 0;
2311 return VINF_SUCCESS;
2312}
2313
2314
2315/** @callback_method_impl{FNCPUMRDMSR} */
2316static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2317{
2318 /** @todo intel RAPL. */
2319 *puValue = 0;
2320 return VINF_SUCCESS;
2321}
2322
2323
2324/** @callback_method_impl{FNCPUMWRMSR} */
2325static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp0PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2326{
2327 /** @todo intel RAPL. */
2328 return VINF_SUCCESS;
2329}
2330
2331
2332/** @callback_method_impl{FNCPUMRDMSR} */
2333static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0EnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2334{
2335 /** @todo intel power management. */
2336 *puValue = 0;
2337 return VINF_SUCCESS;
2338}
2339
2340
2341/** @callback_method_impl{FNCPUMRDMSR} */
2342static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2343{
2344 /** @todo intel RAPL. */
2345 *puValue = 0;
2346 return VINF_SUCCESS;
2347}
2348
2349
2350/** @callback_method_impl{FNCPUMWRMSR} */
2351static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp0Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2352{
2353 /** @todo intel RAPL. */
2354 return VINF_SUCCESS;
2355}
2356
2357
2358/** @callback_method_impl{FNCPUMRDMSR} */
2359static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2360{
2361 /** @todo intel power management. */
2362 *puValue = 0;
2363 return VINF_SUCCESS;
2364}
2365
2366
2367/** @callback_method_impl{FNCPUMRDMSR} */
2368static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp1PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2369{
2370 /** @todo intel RAPL. */
2371 *puValue = 0;
2372 return VINF_SUCCESS;
2373}
2374
2375
2376/** @callback_method_impl{FNCPUMWRMSR} */
2377static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp1PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2378{
2379 /** @todo intel RAPL. */
2380 return VINF_SUCCESS;
2381}
2382
2383
2384/** @callback_method_impl{FNCPUMRDMSR} */
2385static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp1EnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2386{
2387 /** @todo intel power management. */
2388 *puValue = 0;
2389 return VINF_SUCCESS;
2390}
2391
2392
2393/** @callback_method_impl{FNCPUMRDMSR} */
2394static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp1Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2395{
2396 /** @todo intel RAPL. */
2397 *puValue = 0;
2398 return VINF_SUCCESS;
2399}
2400
2401
2402/** @callback_method_impl{FNCPUMWRMSR} */
2403static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp1Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2404{
2405 /** @todo intel RAPL. */
2406 return VINF_SUCCESS;
2407}
2408
2409
2410/** @callback_method_impl{FNCPUMRDMSR} */
2411static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpNominal(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2412{
2413 /** @todo intel power management. */
2414 *puValue = pRange->uValue;
2415 return VINF_SUCCESS;
2416}
2417
2418
2419/** @callback_method_impl{FNCPUMRDMSR} */
2420static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpLevel1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2421{
2422 /** @todo intel power management. */
2423 *puValue = pRange->uValue;
2424 return VINF_SUCCESS;
2425}
2426
2427
2428/** @callback_method_impl{FNCPUMRDMSR} */
2429static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpLevel2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2430{
2431 /** @todo intel power management. */
2432 *puValue = pRange->uValue;
2433 return VINF_SUCCESS;
2434}
2435
2436
2437/** @callback_method_impl{FNCPUMRDMSR} */
2438static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2439{
2440 /** @todo intel power management. */
2441 *puValue = 0;
2442 return VINF_SUCCESS;
2443}
2444
2445
2446/** @callback_method_impl{FNCPUMWRMSR} */
2447static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7IvyConfigTdpControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2448{
2449 /** @todo intel power management. */
2450 return VINF_SUCCESS;
2451}
2452
2453
2454/** @callback_method_impl{FNCPUMRDMSR} */
2455static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyTurboActivationRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2456{
2457 /** @todo intel power management. */
2458 *puValue = 0;
2459 return VINF_SUCCESS;
2460}
2461
2462
2463/** @callback_method_impl{FNCPUMWRMSR} */
2464static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7IvyTurboActivationRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2465{
2466 /** @todo intel power management. */
2467 return VINF_SUCCESS;
2468}
2469
2470
2471/** @callback_method_impl{FNCPUMRDMSR} */
2472static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2473{
2474 /** @todo uncore msrs. */
2475 *puValue = 0;
2476 return VINF_SUCCESS;
2477}
2478
2479
2480/** @callback_method_impl{FNCPUMWRMSR} */
2481static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2482{
2483 /** @todo uncore msrs. */
2484 return VINF_SUCCESS;
2485}
2486
2487
2488/** @callback_method_impl{FNCPUMRDMSR} */
2489static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2490{
2491 /** @todo uncore msrs. */
2492 *puValue = 0;
2493 return VINF_SUCCESS;
2494}
2495
2496
2497/** @callback_method_impl{FNCPUMWRMSR} */
2498static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2499{
2500 /** @todo uncore msrs. */
2501 return VINF_SUCCESS;
2502}
2503
2504
2505/** @callback_method_impl{FNCPUMRDMSR} */
2506static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2507{
2508 /** @todo uncore msrs. */
2509 *puValue = 0;
2510 return VINF_SUCCESS;
2511}
2512
2513
2514/** @callback_method_impl{FNCPUMWRMSR} */
2515static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2516{
2517 /** @todo uncore msrs. */
2518 return VINF_SUCCESS;
2519}
2520
2521
2522/** @callback_method_impl{FNCPUMRDMSR} */
2523static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfFixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2524{
2525 /** @todo uncore msrs. */
2526 *puValue = 0;
2527 return VINF_SUCCESS;
2528}
2529
2530
2531/** @callback_method_impl{FNCPUMWRMSR} */
2532static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfFixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2533{
2534 /** @todo uncore msrs. */
2535 return VINF_SUCCESS;
2536}
2537
2538
2539/** @callback_method_impl{FNCPUMRDMSR} */
2540static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfFixedCtr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2541{
2542 /** @todo uncore msrs. */
2543 *puValue = 0;
2544 return VINF_SUCCESS;
2545}
2546
2547
2548/** @callback_method_impl{FNCPUMWRMSR} */
2549static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfFixedCtr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2550{
2551 /** @todo uncore msrs. */
2552 return VINF_SUCCESS;
2553}
2554
2555
2556/** @callback_method_impl{FNCPUMRDMSR} */
2557static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncCBoxConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2558{
2559 /** @todo uncore msrs. */
2560 *puValue = 0;
2561 return VINF_SUCCESS;
2562}
2563
2564
2565/** @callback_method_impl{FNCPUMRDMSR} */
2566static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncArbPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2567{
2568 /** @todo uncore msrs. */
2569 *puValue = 0;
2570 return VINF_SUCCESS;
2571}
2572
2573
2574/** @callback_method_impl{FNCPUMWRMSR} */
2575static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncArbPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2576{
2577 /** @todo uncore msrs. */
2578 return VINF_SUCCESS;
2579}
2580
2581
2582/** @callback_method_impl{FNCPUMRDMSR} */
2583static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncArbPerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2584{
2585 /** @todo uncore msrs. */
2586 *puValue = 0;
2587 return VINF_SUCCESS;
2588}
2589
2590
2591/** @callback_method_impl{FNCPUMWRMSR} */
2592static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncArbPerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2593{
2594 /** @todo uncore msrs. */
2595 return VINF_SUCCESS;
2596}
2597
2598
2599/** @callback_method_impl{FNCPUMRDMSR} */
2600static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore2EmttmCrTablesN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2601{
2602 /** @todo implement enhanced multi thread termal monitoring? */
2603 *puValue = pRange->uValue;
2604 return VINF_SUCCESS;
2605}
2606
2607
2608/** @callback_method_impl{FNCPUMWRMSR} */
2609static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore2EmttmCrTablesN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2610{
2611 /** @todo implement enhanced multi thread termal monitoring? */
2612 return VINF_SUCCESS;
2613}
2614
2615
2616/** @callback_method_impl{FNCPUMRDMSR} */
2617static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore2SmmCStMiscInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2618{
2619 /** @todo SMM & C-states? */
2620 *puValue = 0;
2621 return VINF_SUCCESS;
2622}
2623
2624
2625/** @callback_method_impl{FNCPUMWRMSR} */
2626static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore2SmmCStMiscInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2627{
2628 /** @todo SMM & C-states? */
2629 return VINF_SUCCESS;
2630}
2631
2632
2633/** @callback_method_impl{FNCPUMRDMSR} */
2634static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore1ExtConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2635{
2636 /** @todo Core1&2 EXT_CONFIG (whatever that is)? */
2637 *puValue = 0;
2638 return VINF_SUCCESS;
2639}
2640
2641
2642/** @callback_method_impl{FNCPUMWRMSR} */
2643static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore1ExtConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2644{
2645 /** @todo Core1&2 EXT_CONFIG (whatever that is)? */
2646 return VINF_SUCCESS;
2647}
2648
2649
2650/** @callback_method_impl{FNCPUMRDMSR} */
2651static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore1DtsCalControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2652{
2653 /** @todo Core1&2(?) DTS_CAL_CTRL (whatever that is)? */
2654 *puValue = 0;
2655 return VINF_SUCCESS;
2656}
2657
2658
2659/** @callback_method_impl{FNCPUMWRMSR} */
2660static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore1DtsCalControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2661{
2662 /** @todo Core1&2(?) DTS_CAL_CTRL (whatever that is)? */
2663 return VINF_SUCCESS;
2664}
2665
2666
2667/** @callback_method_impl{FNCPUMRDMSR} */
2668static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore2PeciControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2669{
2670 /** @todo Core2+ platform environment control interface control register? */
2671 *puValue = 0;
2672 return VINF_SUCCESS;
2673}
2674
2675
2676/** @callback_method_impl{FNCPUMWRMSR} */
2677static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore2PeciControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2678{
2679 /** @todo Core2+ platform environment control interface control register? */
2680 return VINF_SUCCESS;
2681}
2682
2683
2684
2685/*
2686 * Multiple vendor P6 MSRs.
2687 * Multiple vendor P6 MSRs.
2688 * Multiple vendor P6 MSRs.
2689 *
2690 * These MSRs were introduced with the P6 but not elevated to architectural
2691 * MSRs, despite other vendors implementing them.
2692 */
2693
2694
2695/** @callback_method_impl{FNCPUMRDMSR} */
2696static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastBranchFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2697{
2698 /* AMD seems to just record RIP, while intel claims to record RIP+CS.BASE
2699 if I read the docs correctly, thus the need for separate functions. */
2700 /** @todo implement last branch records. */
2701 *puValue = 0;
2702 return VINF_SUCCESS;
2703}
2704
2705
2706/** @callback_method_impl{FNCPUMRDMSR} */
2707static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastBranchToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2708{
2709 /** @todo implement last branch records. */
2710 *puValue = 0;
2711 return VINF_SUCCESS;
2712}
2713
2714
2715/** @callback_method_impl{FNCPUMRDMSR} */
2716static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastIntFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2717{
2718 /** @todo implement last exception records. */
2719 *puValue = 0;
2720 return VINF_SUCCESS;
2721}
2722
2723
2724/** @callback_method_impl{FNCPUMWRMSR} */
2725static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_P6LastIntFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2726{
2727 /** @todo implement last exception records. */
2728 /* Note! On many CPUs, the high bit of the 0x000001dd register is always writable, even when the result is
2729 a non-cannonical address. */
2730 return VINF_SUCCESS;
2731}
2732
2733
2734/** @callback_method_impl{FNCPUMRDMSR} */
2735static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastIntToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2736{
2737 /** @todo implement last exception records. */
2738 *puValue = 0;
2739 return VINF_SUCCESS;
2740}
2741
2742
2743/** @callback_method_impl{FNCPUMWRMSR} */
2744static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_P6LastIntToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2745{
2746 /** @todo implement last exception records. */
2747 return VINF_SUCCESS;
2748}
2749
2750
2751
2752/*
2753 * AMD specific
2754 * AMD specific
2755 * AMD specific
2756 */
2757
2758
2759/** @callback_method_impl{FNCPUMRDMSR} */
2760static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hTscRate(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2761{
2762 /** @todo Implement TscRateMsr */
2763 *puValue = RT_MAKE_U64(0, 1); /* 1.0 = reset value. */
2764 return VINF_SUCCESS;
2765}
2766
2767
2768/** @callback_method_impl{FNCPUMWRMSR} */
2769static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hTscRate(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2770{
2771 /** @todo Implement TscRateMsr */
2772 return VINF_SUCCESS;
2773}
2774
2775
2776/** @callback_method_impl{FNCPUMRDMSR} */
2777static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hLwpCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2778{
2779 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2780 /* Note: Only listes in BKDG for Family 15H. */
2781 *puValue = 0;
2782 return VINF_SUCCESS;
2783}
2784
2785
2786/** @callback_method_impl{FNCPUMWRMSR} */
2787static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hLwpCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2788{
2789 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2790 return VINF_SUCCESS;
2791}
2792
2793
2794/** @callback_method_impl{FNCPUMRDMSR} */
2795static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hLwpCbAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2796{
2797 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2798 /* Note: Only listes in BKDG for Family 15H. */
2799 *puValue = 0;
2800 return VINF_SUCCESS;
2801}
2802
2803
2804/** @callback_method_impl{FNCPUMWRMSR} */
2805static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hLwpCbAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2806{
2807 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2808 return VINF_SUCCESS;
2809}
2810
2811
2812/** @callback_method_impl{FNCPUMRDMSR} */
2813static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hMc4MiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2814{
2815 /** @todo machine check. */
2816 *puValue = 0;
2817 return VINF_SUCCESS;
2818}
2819
2820
2821/** @callback_method_impl{FNCPUMWRMSR} */
2822static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hMc4MiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2823{
2824 /** @todo machine check. */
2825 return VINF_SUCCESS;
2826}
2827
2828
2829/** @callback_method_impl{FNCPUMRDMSR} */
2830static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8PerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2831{
2832 /** @todo AMD performance events. */
2833 *puValue = 0;
2834 return VINF_SUCCESS;
2835}
2836
2837
2838/** @callback_method_impl{FNCPUMWRMSR} */
2839static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8PerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2840{
2841 /** @todo AMD performance events. */
2842 return VINF_SUCCESS;
2843}
2844
2845
2846/** @callback_method_impl{FNCPUMRDMSR} */
2847static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8PerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2848{
2849 /** @todo AMD performance events. */
2850 *puValue = 0;
2851 return VINF_SUCCESS;
2852}
2853
2854
2855/** @callback_method_impl{FNCPUMWRMSR} */
2856static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8PerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2857{
2858 /** @todo AMD performance events. */
2859 return VINF_SUCCESS;
2860}
2861
2862
2863/** @callback_method_impl{FNCPUMRDMSR} */
2864static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SysCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2865{
2866 /** @todo AMD SYS_CFG */
2867 *puValue = pRange->uValue;
2868 return VINF_SUCCESS;
2869}
2870
2871
2872/** @callback_method_impl{FNCPUMWRMSR} */
2873static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SysCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2874{
2875 /** @todo AMD SYS_CFG */
2876 return VINF_SUCCESS;
2877}
2878
2879
2880/** @callback_method_impl{FNCPUMRDMSR} */
2881static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8HwCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2882{
2883 /** @todo AMD HW_CFG */
2884 *puValue = 0;
2885 return VINF_SUCCESS;
2886}
2887
2888
2889/** @callback_method_impl{FNCPUMWRMSR} */
2890static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8HwCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2891{
2892 /** @todo AMD HW_CFG */
2893 return VINF_SUCCESS;
2894}
2895
2896
2897/** @callback_method_impl{FNCPUMRDMSR} */
2898static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IorrBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2899{
2900 /** @todo AMD IorrMask/IorrBase */
2901 *puValue = 0;
2902 return VINF_SUCCESS;
2903}
2904
2905
2906/** @callback_method_impl{FNCPUMWRMSR} */
2907static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IorrBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2908{
2909 /** @todo AMD IorrMask/IorrBase */
2910 return VINF_SUCCESS;
2911}
2912
2913
2914/** @callback_method_impl{FNCPUMRDMSR} */
2915static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IorrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2916{
2917 /** @todo AMD IorrMask/IorrBase */
2918 *puValue = 0;
2919 return VINF_SUCCESS;
2920}
2921
2922
2923/** @callback_method_impl{FNCPUMWRMSR} */
2924static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IorrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2925{
2926 /** @todo AMD IorrMask/IorrBase */
2927 return VINF_SUCCESS;
2928}
2929
2930
2931/** @callback_method_impl{FNCPUMRDMSR} */
2932static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8TopOfMemN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2933{
2934 *puValue = 0;
2935 /** @todo return 4GB - RamHoleSize here for TOPMEM. Figure out what to return
2936 * for TOPMEM2. */
2937 //if (pRange->uValue == 0)
2938 // *puValue = _4G - RamHoleSize;
2939 return VINF_SUCCESS;
2940}
2941
2942
2943/** @callback_method_impl{FNCPUMWRMSR} */
2944static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8TopOfMemN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2945{
2946 /** @todo AMD TOPMEM and TOPMEM2/TOM2. */
2947 return VINF_SUCCESS;
2948}
2949
2950
2951/** @callback_method_impl{FNCPUMRDMSR} */
2952static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8NbCfg1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2953{
2954 /** @todo AMD NB_CFG1 */
2955 *puValue = 0;
2956 return VINF_SUCCESS;
2957}
2958
2959
2960/** @callback_method_impl{FNCPUMWRMSR} */
2961static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8NbCfg1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2962{
2963 /** @todo AMD NB_CFG1 */
2964 return VINF_SUCCESS;
2965}
2966
2967
2968/** @callback_method_impl{FNCPUMRDMSR} */
2969static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8McXcptRedir(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2970{
2971 /** @todo machine check. */
2972 *puValue = 0;
2973 return VINF_SUCCESS;
2974}
2975
2976
2977/** @callback_method_impl{FNCPUMWRMSR} */
2978static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8McXcptRedir(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2979{
2980 /** @todo machine check. */
2981 return VINF_SUCCESS;
2982}
2983
2984
2985/** @callback_method_impl{FNCPUMRDMSR} */
2986static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuNameN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2987{
2988 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), pRange->uValue / 2 + 0x80000001, 0);
2989 if (pLeaf)
2990 {
2991 if (!(pRange->uValue & 1))
2992 *puValue = RT_MAKE_U64(pLeaf->uEax, pLeaf->uEbx);
2993 else
2994 *puValue = RT_MAKE_U64(pLeaf->uEcx, pLeaf->uEdx);
2995 }
2996 else
2997 *puValue = 0;
2998 return VINF_SUCCESS;
2999}
3000
3001
3002/** @callback_method_impl{FNCPUMWRMSR} */
3003static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuNameN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3004{
3005 /** @todo Remember guest programmed CPU name. */
3006 return VINF_SUCCESS;
3007}
3008
3009
3010/** @callback_method_impl{FNCPUMRDMSR} */
3011static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8HwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3012{
3013 /** @todo AMD HTC. */
3014 *puValue = pRange->uValue;
3015 return VINF_SUCCESS;
3016}
3017
3018
3019/** @callback_method_impl{FNCPUMWRMSR} */
3020static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8HwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3021{
3022 /** @todo AMD HTC. */
3023 return VINF_SUCCESS;
3024}
3025
3026
3027/** @callback_method_impl{FNCPUMRDMSR} */
3028static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3029{
3030 /** @todo AMD STC. */
3031 *puValue = 0;
3032 return VINF_SUCCESS;
3033}
3034
3035
3036/** @callback_method_impl{FNCPUMWRMSR} */
3037static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3038{
3039 /** @todo AMD STC. */
3040 return VINF_SUCCESS;
3041}
3042
3043
3044/** @callback_method_impl{FNCPUMRDMSR} */
3045static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8FidVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3046{
3047 /** @todo AMD FIDVID_CTL. */
3048 *puValue = pRange->uValue;
3049 return VINF_SUCCESS;
3050}
3051
3052
3053/** @callback_method_impl{FNCPUMWRMSR} */
3054static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8FidVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3055{
3056 /** @todo AMD FIDVID_CTL. */
3057 return VINF_SUCCESS;
3058}
3059
3060
3061/** @callback_method_impl{FNCPUMRDMSR} */
3062static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8FidVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3063{
3064 /** @todo AMD FIDVID_STATUS. */
3065 *puValue = pRange->uValue;
3066 return VINF_SUCCESS;
3067}
3068
3069
3070/** @callback_method_impl{FNCPUMRDMSR} */
3071static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8McCtlMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3072{
3073 /** @todo AMD MC. */
3074 *puValue = 0;
3075 return VINF_SUCCESS;
3076}
3077
3078
3079/** @callback_method_impl{FNCPUMWRMSR} */
3080static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8McCtlMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3081{
3082 /** @todo AMD MC. */
3083 return VINF_SUCCESS;
3084}
3085
3086
3087/** @callback_method_impl{FNCPUMRDMSR} */
3088static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmiOnIoTrapN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3089{
3090 /** @todo AMD SMM/SMI and I/O trap. */
3091 *puValue = 0;
3092 return VINF_SUCCESS;
3093}
3094
3095
3096/** @callback_method_impl{FNCPUMWRMSR} */
3097static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmiOnIoTrapN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3098{
3099 /** @todo AMD SMM/SMI and I/O trap. */
3100 return VINF_SUCCESS;
3101}
3102
3103
3104/** @callback_method_impl{FNCPUMRDMSR} */
3105static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmiOnIoTrapCtlSts(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3106{
3107 /** @todo AMD SMM/SMI and I/O trap. */
3108 *puValue = 0;
3109 return VINF_SUCCESS;
3110}
3111
3112
3113/** @callback_method_impl{FNCPUMWRMSR} */
3114static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmiOnIoTrapCtlSts(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3115{
3116 /** @todo AMD SMM/SMI and I/O trap. */
3117 return VINF_SUCCESS;
3118}
3119
3120
3121/** @callback_method_impl{FNCPUMRDMSR} */
3122static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IntPendingMessage(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3123{
3124 /** @todo Interrupt pending message. */
3125 *puValue = 0;
3126 return VINF_SUCCESS;
3127}
3128
3129
3130/** @callback_method_impl{FNCPUMWRMSR} */
3131static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IntPendingMessage(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3132{
3133 /** @todo Interrupt pending message. */
3134 return VINF_SUCCESS;
3135}
3136
3137
3138/** @callback_method_impl{FNCPUMRDMSR} */
3139static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmiTriggerIoCycle(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3140{
3141 /** @todo AMD SMM/SMI and trigger I/O cycle. */
3142 *puValue = 0;
3143 return VINF_SUCCESS;
3144}
3145
3146
3147/** @callback_method_impl{FNCPUMWRMSR} */
3148static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmiTriggerIoCycle(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3149{
3150 /** @todo AMD SMM/SMI and trigger I/O cycle. */
3151 return VINF_SUCCESS;
3152}
3153
3154
3155/** @callback_method_impl{FNCPUMRDMSR} */
3156static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hMmioCfgBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3157{
3158 /** @todo AMD MMIO Configuration base address. */
3159 *puValue = 0;
3160 return VINF_SUCCESS;
3161}
3162
3163
3164/** @callback_method_impl{FNCPUMWRMSR} */
3165static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hMmioCfgBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3166{
3167 /** @todo AMD MMIO Configuration base address. */
3168 return VINF_SUCCESS;
3169}
3170
3171
3172/** @callback_method_impl{FNCPUMRDMSR} */
3173static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hTrapCtlMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3174{
3175 /** @todo AMD 0xc0010059. */
3176 *puValue = 0;
3177 return VINF_SUCCESS;
3178}
3179
3180
3181/** @callback_method_impl{FNCPUMWRMSR} */
3182static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hTrapCtlMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3183{
3184 /** @todo AMD 0xc0010059. */
3185 return VINF_SUCCESS;
3186}
3187
3188
3189/** @callback_method_impl{FNCPUMRDMSR} */
3190static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateCurLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3191{
3192 /** @todo AMD P-states. */
3193 *puValue = pRange->uValue;
3194 return VINF_SUCCESS;
3195}
3196
3197
3198/** @callback_method_impl{FNCPUMRDMSR} */
3199static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3200{
3201 /** @todo AMD P-states. */
3202 *puValue = pRange->uValue;
3203 return VINF_SUCCESS;
3204}
3205
3206
3207/** @callback_method_impl{FNCPUMWRMSR} */
3208static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hPStateControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3209{
3210 /** @todo AMD P-states. */
3211 return VINF_SUCCESS;
3212}
3213
3214
3215/** @callback_method_impl{FNCPUMRDMSR} */
3216static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3217{
3218 /** @todo AMD P-states. */
3219 *puValue = pRange->uValue;
3220 return VINF_SUCCESS;
3221}
3222
3223
3224/** @callback_method_impl{FNCPUMWRMSR} */
3225static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hPStateStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3226{
3227 /** @todo AMD P-states. */
3228 return VINF_SUCCESS;
3229}
3230
3231
3232/** @callback_method_impl{FNCPUMRDMSR} */
3233static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3234{
3235 /** @todo AMD P-states. */
3236 *puValue = pRange->uValue;
3237 return VINF_SUCCESS;
3238}
3239
3240
3241/** @callback_method_impl{FNCPUMWRMSR} */
3242static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hPStateN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3243{
3244 /** @todo AMD P-states. */
3245 return VINF_SUCCESS;
3246}
3247
3248
3249/** @callback_method_impl{FNCPUMRDMSR} */
3250static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCofVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3251{
3252 /** @todo AMD P-states. */
3253 *puValue = pRange->uValue;
3254 return VINF_SUCCESS;
3255}
3256
3257
3258/** @callback_method_impl{FNCPUMWRMSR} */
3259static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCofVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3260{
3261 /** @todo AMD P-states. */
3262 return VINF_SUCCESS;
3263}
3264
3265
3266/** @callback_method_impl{FNCPUMRDMSR} */
3267static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCofVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3268{
3269 /** @todo AMD P-states. */
3270 *puValue = pRange->uValue;
3271 return VINF_SUCCESS;
3272}
3273
3274
3275/** @callback_method_impl{FNCPUMWRMSR} */
3276static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCofVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3277{
3278 /* Note! Writing 0 seems to not GP, not sure if it does anything to the value... */
3279 /** @todo AMD P-states. */
3280 return VINF_SUCCESS;
3281}
3282
3283
3284/** @callback_method_impl{FNCPUMRDMSR} */
3285static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCStateIoBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3286{
3287 /** @todo AMD C-states. */
3288 *puValue = 0;
3289 return VINF_SUCCESS;
3290}
3291
3292
3293/** @callback_method_impl{FNCPUMWRMSR} */
3294static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCStateIoBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3295{
3296 /** @todo AMD C-states. */
3297 return VINF_SUCCESS;
3298}
3299
3300
3301/** @callback_method_impl{FNCPUMRDMSR} */
3302static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCpuWatchdogTimer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3303{
3304 /** @todo AMD machine checks. */
3305 *puValue = 0;
3306 return VINF_SUCCESS;
3307}
3308
3309
3310/** @callback_method_impl{FNCPUMWRMSR} */
3311static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCpuWatchdogTimer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3312{
3313 /** @todo AMD machine checks. */
3314 return VINF_SUCCESS;
3315}
3316
3317
3318/** @callback_method_impl{FNCPUMRDMSR} */
3319static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3320{
3321 /** @todo AMD SMM. */
3322 *puValue = 0;
3323 return VINF_SUCCESS;
3324}
3325
3326
3327/** @callback_method_impl{FNCPUMWRMSR} */
3328static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3329{
3330 /** @todo AMD SMM. */
3331 return VINF_SUCCESS;
3332}
3333
3334
3335/** @callback_method_impl{FNCPUMRDMSR} */
3336static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3337{
3338 /** @todo AMD SMM. */
3339 *puValue = 0;
3340 return VINF_SUCCESS;
3341}
3342
3343
3344/** @callback_method_impl{FNCPUMWRMSR} */
3345static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3346{
3347 /** @todo AMD SMM. */
3348 return VINF_SUCCESS;
3349}
3350
3351
3352
3353/** @callback_method_impl{FNCPUMRDMSR} */
3354static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3355{
3356 /** @todo AMD SMM. */
3357 *puValue = 0;
3358 return VINF_SUCCESS;
3359}
3360
3361
3362/** @callback_method_impl{FNCPUMWRMSR} */
3363static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3364{
3365 /** @todo AMD SMM. */
3366 return VINF_SUCCESS;
3367}
3368
3369
3370/** @callback_method_impl{FNCPUMRDMSR} */
3371static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8VmCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3372{
3373 /** @todo AMD SVM. */
3374 *puValue = 0;
3375 return VINF_SUCCESS;
3376}
3377
3378
3379/** @callback_method_impl{FNCPUMWRMSR} */
3380static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8VmCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3381{
3382 /** @todo AMD SVM. */
3383 return VINF_SUCCESS;
3384}
3385
3386
3387/** @callback_method_impl{FNCPUMRDMSR} */
3388static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IgnNe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3389{
3390 /** @todo AMD IGNNE\# control. */
3391 *puValue = 0;
3392 return VINF_SUCCESS;
3393}
3394
3395
3396/** @callback_method_impl{FNCPUMWRMSR} */
3397static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IgnNe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3398{
3399 /** @todo AMD IGNNE\# control. */
3400 return VINF_SUCCESS;
3401}
3402
3403
3404/** @callback_method_impl{FNCPUMRDMSR} */
3405static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3406{
3407 /** @todo AMD SMM. */
3408 *puValue = 0;
3409 return VINF_SUCCESS;
3410}
3411
3412
3413/** @callback_method_impl{FNCPUMWRMSR} */
3414static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3415{
3416 /** @todo AMD SMM. */
3417 return VINF_SUCCESS;
3418}
3419
3420
3421/** @callback_method_impl{FNCPUMRDMSR} */
3422static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8VmHSavePa(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3423{
3424 /** @todo AMD SVM. */
3425 *puValue = 0;
3426 return VINF_SUCCESS;
3427}
3428
3429
3430/** @callback_method_impl{FNCPUMWRMSR} */
3431static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8VmHSavePa(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3432{
3433 /** @todo AMD SVM. */
3434 return VINF_SUCCESS;
3435}
3436
3437
3438/** @callback_method_impl{FNCPUMRDMSR} */
3439static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hVmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3440{
3441 /** @todo AMD SVM. */
3442 *puValue = 0; /* RAZ */
3443 return VINF_SUCCESS;
3444}
3445
3446
3447/** @callback_method_impl{FNCPUMWRMSR} */
3448static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hVmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3449{
3450 /** @todo AMD SVM. */
3451 return VINF_SUCCESS;
3452}
3453
3454
3455/** @callback_method_impl{FNCPUMRDMSR} */
3456static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hSmmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3457{
3458 /** @todo AMD SMM. */
3459 *puValue = 0; /* RAZ */
3460 return VINF_SUCCESS;
3461}
3462
3463
3464/** @callback_method_impl{FNCPUMWRMSR} */
3465static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hSmmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3466{
3467 /** @todo AMD SMM. */
3468 return VINF_SUCCESS;
3469}
3470
3471
3472/** @callback_method_impl{FNCPUMRDMSR} */
3473static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hLocalSmiStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3474{
3475 /** @todo AMD SMM/SMI. */
3476 *puValue = 0;
3477 return VINF_SUCCESS;
3478}
3479
3480
3481/** @callback_method_impl{FNCPUMWRMSR} */
3482static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hLocalSmiStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3483{
3484 /** @todo AMD SMM/SMI. */
3485 return VINF_SUCCESS;
3486}
3487
3488
3489/** @callback_method_impl{FNCPUMRDMSR} */
3490static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hOsVisWrkIdLength(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3491{
3492 /** @todo AMD OS visible workaround. */
3493 *puValue = pRange->uValue;
3494 return VINF_SUCCESS;
3495}
3496
3497
3498/** @callback_method_impl{FNCPUMWRMSR} */
3499static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hOsVisWrkIdLength(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3500{
3501 /** @todo AMD OS visible workaround. */
3502 return VINF_SUCCESS;
3503}
3504
3505
3506/** @callback_method_impl{FNCPUMRDMSR} */
3507static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hOsVisWrkStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3508{
3509 /** @todo AMD OS visible workaround. */
3510 *puValue = 0;
3511 return VINF_SUCCESS;
3512}
3513
3514
3515/** @callback_method_impl{FNCPUMWRMSR} */
3516static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hOsVisWrkStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3517{
3518 /** @todo AMD OS visible workaround. */
3519 return VINF_SUCCESS;
3520}
3521
3522
3523/** @callback_method_impl{FNCPUMRDMSR} */
3524static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam16hL2IPerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3525{
3526 /** @todo AMD L2I performance counters. */
3527 *puValue = 0;
3528 return VINF_SUCCESS;
3529}
3530
3531
3532/** @callback_method_impl{FNCPUMWRMSR} */
3533static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam16hL2IPerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3534{
3535 /** @todo AMD L2I performance counters. */
3536 return VINF_SUCCESS;
3537}
3538
3539
3540/** @callback_method_impl{FNCPUMRDMSR} */
3541static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam16hL2IPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3542{
3543 /** @todo AMD L2I performance counters. */
3544 *puValue = 0;
3545 return VINF_SUCCESS;
3546}
3547
3548
3549/** @callback_method_impl{FNCPUMWRMSR} */
3550static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam16hL2IPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3551{
3552 /** @todo AMD L2I performance counters. */
3553 return VINF_SUCCESS;
3554}
3555
3556
3557/** @callback_method_impl{FNCPUMRDMSR} */
3558static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hNorthbridgePerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3559{
3560 /** @todo AMD Northbridge performance counters. */
3561 *puValue = 0;
3562 return VINF_SUCCESS;
3563}
3564
3565
3566/** @callback_method_impl{FNCPUMWRMSR} */
3567static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hNorthbridgePerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3568{
3569 /** @todo AMD Northbridge performance counters. */
3570 return VINF_SUCCESS;
3571}
3572
3573
3574/** @callback_method_impl{FNCPUMRDMSR} */
3575static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hNorthbridgePerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3576{
3577 /** @todo AMD Northbridge performance counters. */
3578 *puValue = 0;
3579 return VINF_SUCCESS;
3580}
3581
3582
3583/** @callback_method_impl{FNCPUMWRMSR} */
3584static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hNorthbridgePerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3585{
3586 /** @todo AMD Northbridge performance counters. */
3587 return VINF_SUCCESS;
3588}
3589
3590
3591/** @callback_method_impl{FNCPUMRDMSR} */
3592static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7MicrocodeCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3593{
3594 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3595 * cpus. Need to be explored and verify K7 presence. */
3596 /** @todo Undocumented register only seen mentioned in fam15h erratum \#608. */
3597 *puValue = pRange->uValue;
3598 return VINF_SUCCESS;
3599}
3600
3601
3602/** @callback_method_impl{FNCPUMWRMSR} */
3603static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7MicrocodeCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3604{
3605 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3606 * cpus. Need to be explored and verify K7 presence. */
3607 /** @todo Undocumented register only seen mentioned in fam15h erratum \#608. */
3608 return VINF_SUCCESS;
3609}
3610
3611
3612/** @callback_method_impl{FNCPUMRDMSR} */
3613static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7ClusterIdMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3614{
3615 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3616 * cpus. Need to be explored and verify K7 presence. */
3617 /** @todo Undocumented register only seen mentioned in fam16h BKDG r3.00 when
3618 * describing EBL_CR_POWERON. */
3619 *puValue = pRange->uValue;
3620 return VINF_SUCCESS;
3621}
3622
3623
3624/** @callback_method_impl{FNCPUMWRMSR} */
3625static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7ClusterIdMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3626{
3627 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3628 * cpus. Need to be explored and verify K7 presence. */
3629 /** @todo Undocumented register only seen mentioned in fam16h BKDG r3.00 when
3630 * describing EBL_CR_POWERON. */
3631 return VINF_SUCCESS;
3632}
3633
3634
3635/** @callback_method_impl{FNCPUMRDMSR} */
3636static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlStd07hEbax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3637{
3638 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000007, 0);
3639 if (pLeaf)
3640 *puValue = RT_MAKE_U64(pLeaf->uEbx, pLeaf->uEax);
3641 else
3642 *puValue = 0;
3643 return VINF_SUCCESS;
3644}
3645
3646
3647/** @callback_method_impl{FNCPUMWRMSR} */
3648static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlStd07hEbax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3649{
3650 /** @todo Changing CPUID leaf 7/0. */
3651 return VINF_SUCCESS;
3652}
3653
3654
3655/** @callback_method_impl{FNCPUMRDMSR} */
3656static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlStd06hEcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3657{
3658 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000006, 0);
3659 if (pLeaf)
3660 *puValue = pLeaf->uEcx;
3661 else
3662 *puValue = 0;
3663 return VINF_SUCCESS;
3664}
3665
3666
3667/** @callback_method_impl{FNCPUMWRMSR} */
3668static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlStd06hEcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3669{
3670 /** @todo Changing CPUID leaf 6. */
3671 return VINF_SUCCESS;
3672}
3673
3674
3675/** @callback_method_impl{FNCPUMRDMSR} */
3676static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlStd01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3677{
3678 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000001, 0);
3679 if (pLeaf)
3680 *puValue = RT_MAKE_U64(pLeaf->uEdx, pLeaf->uEcx);
3681 else
3682 *puValue = 0;
3683 return VINF_SUCCESS;
3684}
3685
3686
3687/** @callback_method_impl{FNCPUMWRMSR} */
3688static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlStd01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3689{
3690 /** @todo Changing CPUID leaf 0x80000001. */
3691 return VINF_SUCCESS;
3692}
3693
3694
3695/** @callback_method_impl{FNCPUMRDMSR} */
3696static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlExt01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3697{
3698 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x80000001, 0);
3699 if (pLeaf)
3700 *puValue = RT_MAKE_U64(pLeaf->uEdx, pLeaf->uEcx);
3701 else
3702 *puValue = 0;
3703 return VINF_SUCCESS;
3704}
3705
3706
3707/** @callback_method_impl{FNCPUMWRMSR} */
3708static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlExt01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3709{
3710 /** @todo Changing CPUID leaf 0x80000001. */
3711 return VINF_SUCCESS;
3712}
3713
3714
3715/** @callback_method_impl{FNCPUMRDMSR} */
3716static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8PatchLevel(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3717{
3718 /** @todo Fake AMD microcode patching. */
3719 *puValue = pRange->uValue;
3720 return VINF_SUCCESS;
3721}
3722
3723
3724/** @callback_method_impl{FNCPUMWRMSR} */
3725static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8PatchLoader(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3726{
3727 /** @todo Fake AMD microcode patching. */
3728 return VINF_SUCCESS;
3729}
3730
3731
3732/** @callback_method_impl{FNCPUMRDMSR} */
3733static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DebugStatusMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3734{
3735 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3736 * cpus. Need to be explored and verify K7 presence. */
3737 /** @todo undocumented */
3738 *puValue = 0;
3739 return VINF_SUCCESS;
3740}
3741
3742
3743/** @callback_method_impl{FNCPUMWRMSR} */
3744static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DebugStatusMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3745{
3746 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3747 * cpus. Need to be explored and verify K7 presence. */
3748 /** @todo undocumented */
3749 return VINF_SUCCESS;
3750}
3751
3752
3753/** @callback_method_impl{FNCPUMRDMSR} */
3754static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BHTraceBaseMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3755{
3756 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3757 * cpus. Need to be explored and verify K7 presence. */
3758 /** @todo undocumented */
3759 *puValue = 0;
3760 return VINF_SUCCESS;
3761}
3762
3763
3764/** @callback_method_impl{FNCPUMWRMSR} */
3765static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BHTraceBaseMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3766{
3767 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3768 * cpus. Need to be explored and verify K7 presence. */
3769 /** @todo undocumented */
3770 return VINF_SUCCESS;
3771}
3772
3773
3774/** @callback_method_impl{FNCPUMRDMSR} */
3775static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BHTracePtrMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3776{
3777 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3778 * cpus. Need to be explored and verify K7 presence. */
3779 /** @todo undocumented */
3780 *puValue = 0;
3781 return VINF_SUCCESS;
3782}
3783
3784
3785/** @callback_method_impl{FNCPUMWRMSR} */
3786static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BHTracePtrMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3787{
3788 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3789 * cpus. Need to be explored and verify K7 presence. */
3790 /** @todo undocumented */
3791 return VINF_SUCCESS;
3792}
3793
3794
3795/** @callback_method_impl{FNCPUMRDMSR} */
3796static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BHTraceLimitMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3797{
3798 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3799 * cpus. Need to be explored and verify K7 presence. */
3800 /** @todo undocumented */
3801 *puValue = 0;
3802 return VINF_SUCCESS;
3803}
3804
3805
3806/** @callback_method_impl{FNCPUMWRMSR} */
3807static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BHTraceLimitMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3808{
3809 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3810 * cpus. Need to be explored and verify K7 presence. */
3811 /** @todo undocumented */
3812 return VINF_SUCCESS;
3813}
3814
3815
3816/** @callback_method_impl{FNCPUMRDMSR} */
3817static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7HardwareDebugToolCfgMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3818{
3819 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3820 * cpus. Need to be explored and verify K7 presence. */
3821 /** @todo undocumented */
3822 *puValue = 0;
3823 return VINF_SUCCESS;
3824}
3825
3826
3827/** @callback_method_impl{FNCPUMWRMSR} */
3828static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7HardwareDebugToolCfgMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3829{
3830 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3831 * cpus. Need to be explored and verify K7 presence. */
3832 /** @todo undocumented */
3833 return VINF_SUCCESS;
3834}
3835
3836
3837/** @callback_method_impl{FNCPUMRDMSR} */
3838static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7FastFlushCountMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3839{
3840 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3841 * cpus. Need to be explored and verify K7 presence. */
3842 /** @todo undocumented */
3843 *puValue = 0;
3844 return VINF_SUCCESS;
3845}
3846
3847
3848/** @callback_method_impl{FNCPUMWRMSR} */
3849static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7FastFlushCountMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3850{
3851 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3852 * cpus. Need to be explored and verify K7 presence. */
3853 /** @todo undocumented */
3854 return VINF_SUCCESS;
3855}
3856
3857
3858/** @callback_method_impl{FNCPUMRDMSR} */
3859static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7NodeId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3860{
3861 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3862 * cpus. Need to be explored and verify K7 presence. */
3863 /** @todo AMD node ID and bios scratch. */
3864 *puValue = 0; /* nodeid = 0; nodes-per-cpu = 1 */
3865 return VINF_SUCCESS;
3866}
3867
3868
3869/** @callback_method_impl{FNCPUMWRMSR} */
3870static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7NodeId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3871{
3872 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3873 * cpus. Need to be explored and verify K7 presence. */
3874 /** @todo AMD node ID and bios scratch. */
3875 return VINF_SUCCESS;
3876}
3877
3878
3879/** @callback_method_impl{FNCPUMRDMSR} */
3880static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DrXAddrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3881{
3882 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3883 * cpus. Need to be explored and verify K7 presence. */
3884 /** @todo AMD DRx address masking (range breakpoints). */
3885 *puValue = 0;
3886 return VINF_SUCCESS;
3887}
3888
3889
3890/** @callback_method_impl{FNCPUMWRMSR} */
3891static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DrXAddrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3892{
3893 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3894 * cpus. Need to be explored and verify K7 presence. */
3895 /** @todo AMD DRx address masking (range breakpoints). */
3896 return VINF_SUCCESS;
3897}
3898
3899
3900/** @callback_method_impl{FNCPUMRDMSR} */
3901static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7Dr0DataMatchMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3902{
3903 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3904 * cpus. Need to be explored and verify K7 presence. */
3905 /** @todo AMD undocument debugging features. */
3906 *puValue = 0;
3907 return VINF_SUCCESS;
3908}
3909
3910
3911/** @callback_method_impl{FNCPUMWRMSR} */
3912static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7Dr0DataMatchMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3913{
3914 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3915 * cpus. Need to be explored and verify K7 presence. */
3916 /** @todo AMD undocument debugging features. */
3917 return VINF_SUCCESS;
3918}
3919
3920
3921/** @callback_method_impl{FNCPUMRDMSR} */
3922static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7Dr0DataMaskMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3923{
3924 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3925 * cpus. Need to be explored and verify K7 presence. */
3926 /** @todo AMD undocument debugging features. */
3927 *puValue = 0;
3928 return VINF_SUCCESS;
3929}
3930
3931
3932/** @callback_method_impl{FNCPUMWRMSR} */
3933static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7Dr0DataMaskMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3934{
3935 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3936 * cpus. Need to be explored and verify K7 presence. */
3937 /** @todo AMD undocument debugging features. */
3938 return VINF_SUCCESS;
3939}
3940
3941
3942/** @callback_method_impl{FNCPUMRDMSR} */
3943static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7LoadStoreCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3944{
3945 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3946 * cpus. Need to be explored and verify K7 presence. */
3947 /** @todo AMD load-store config. */
3948 *puValue = 0;
3949 return VINF_SUCCESS;
3950}
3951
3952
3953/** @callback_method_impl{FNCPUMWRMSR} */
3954static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7LoadStoreCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3955{
3956 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3957 * cpus. Need to be explored and verify K7 presence. */
3958 /** @todo AMD load-store config. */
3959 return VINF_SUCCESS;
3960}
3961
3962
3963/** @callback_method_impl{FNCPUMRDMSR} */
3964static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7InstrCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3965{
3966 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3967 * cpus. Need to be explored and verify K7 presence. */
3968 /** @todo AMD instruction cache config. */
3969 *puValue = 0;
3970 return VINF_SUCCESS;
3971}
3972
3973
3974/** @callback_method_impl{FNCPUMWRMSR} */
3975static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7InstrCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3976{
3977 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3978 * cpus. Need to be explored and verify K7 presence. */
3979 /** @todo AMD instruction cache config. */
3980 return VINF_SUCCESS;
3981}
3982
3983
3984/** @callback_method_impl{FNCPUMRDMSR} */
3985static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DataCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3986{
3987 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3988 * cpus. Need to be explored and verify K7 presence. */
3989 /** @todo AMD data cache config. */
3990 *puValue = 0;
3991 return VINF_SUCCESS;
3992}
3993
3994
3995/** @callback_method_impl{FNCPUMWRMSR} */
3996static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DataCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3997{
3998 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3999 * cpus. Need to be explored and verify K7 presence. */
4000 /** @todo AMD data cache config. */
4001 return VINF_SUCCESS;
4002}
4003
4004
4005/** @callback_method_impl{FNCPUMRDMSR} */
4006static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BusUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4007{
4008 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4009 * cpus. Need to be explored and verify K7 presence. */
4010 /** @todo AMD bus unit config. */
4011 *puValue = 0;
4012 return VINF_SUCCESS;
4013}
4014
4015
4016/** @callback_method_impl{FNCPUMWRMSR} */
4017static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BusUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4018{
4019 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4020 * cpus. Need to be explored and verify K7 presence. */
4021 /** @todo AMD bus unit config. */
4022 return VINF_SUCCESS;
4023}
4024
4025
4026/** @callback_method_impl{FNCPUMRDMSR} */
4027static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DebugCtl2Maybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4028{
4029 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4030 * cpus. Need to be explored and verify K7 presence. */
4031 /** @todo Undocument AMD debug control register \#2. */
4032 *puValue = 0;
4033 return VINF_SUCCESS;
4034}
4035
4036
4037/** @callback_method_impl{FNCPUMWRMSR} */
4038static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DebugCtl2Maybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4039{
4040 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4041 * cpus. Need to be explored and verify K7 presence. */
4042 /** @todo Undocument AMD debug control register \#2. */
4043 return VINF_SUCCESS;
4044}
4045
4046
4047/** @callback_method_impl{FNCPUMRDMSR} */
4048static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hFpuCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4049{
4050 /** @todo AMD FPU config. */
4051 *puValue = 0;
4052 return VINF_SUCCESS;
4053}
4054
4055
4056/** @callback_method_impl{FNCPUMWRMSR} */
4057static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hFpuCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4058{
4059 /** @todo AMD FPU config. */
4060 return VINF_SUCCESS;
4061}
4062
4063
4064/** @callback_method_impl{FNCPUMRDMSR} */
4065static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hDecoderCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4066{
4067 /** @todo AMD decoder config. */
4068 *puValue = 0;
4069 return VINF_SUCCESS;
4070}
4071
4072
4073/** @callback_method_impl{FNCPUMWRMSR} */
4074static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hDecoderCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4075{
4076 /** @todo AMD decoder config. */
4077 return VINF_SUCCESS;
4078}
4079
4080
4081/** @callback_method_impl{FNCPUMRDMSR} */
4082static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hBusUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4083{
4084 /* Note! 10h and 16h */
4085 /** @todo AMD bus unit config. */
4086 *puValue = 0;
4087 return VINF_SUCCESS;
4088}
4089
4090
4091/** @callback_method_impl{FNCPUMWRMSR} */
4092static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hBusUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4093{
4094 /* Note! 10h and 16h */
4095 /** @todo AMD bus unit config. */
4096 return VINF_SUCCESS;
4097}
4098
4099
4100/** @callback_method_impl{FNCPUMRDMSR} */
4101static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hCombUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4102{
4103 /** @todo AMD unit config. */
4104 *puValue = 0;
4105 return VINF_SUCCESS;
4106}
4107
4108
4109/** @callback_method_impl{FNCPUMWRMSR} */
4110static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hCombUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4111{
4112 /** @todo AMD unit config. */
4113 return VINF_SUCCESS;
4114}
4115
4116
4117/** @callback_method_impl{FNCPUMRDMSR} */
4118static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hCombUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4119{
4120 /** @todo AMD unit config 2. */
4121 *puValue = 0;
4122 return VINF_SUCCESS;
4123}
4124
4125
4126/** @callback_method_impl{FNCPUMWRMSR} */
4127static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hCombUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4128{
4129 /** @todo AMD unit config 2. */
4130 return VINF_SUCCESS;
4131}
4132
4133
4134/** @callback_method_impl{FNCPUMRDMSR} */
4135static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hCombUnitCfg3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4136{
4137 /** @todo AMD combined unit config 3. */
4138 *puValue = 0;
4139 return VINF_SUCCESS;
4140}
4141
4142
4143/** @callback_method_impl{FNCPUMWRMSR} */
4144static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hCombUnitCfg3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4145{
4146 /** @todo AMD combined unit config 3. */
4147 return VINF_SUCCESS;
4148}
4149
4150
4151/** @callback_method_impl{FNCPUMRDMSR} */
4152static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hExecUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4153{
4154 /** @todo AMD execution unit config. */
4155 *puValue = 0;
4156 return VINF_SUCCESS;
4157}
4158
4159
4160/** @callback_method_impl{FNCPUMWRMSR} */
4161static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hExecUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4162{
4163 /** @todo AMD execution unit config. */
4164 return VINF_SUCCESS;
4165}
4166
4167
4168/** @callback_method_impl{FNCPUMRDMSR} */
4169static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hLoadStoreCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4170{
4171 /** @todo AMD load-store config 2. */
4172 *puValue = 0;
4173 return VINF_SUCCESS;
4174}
4175
4176
4177/** @callback_method_impl{FNCPUMWRMSR} */
4178static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hLoadStoreCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4179{
4180 /** @todo AMD load-store config 2. */
4181 return VINF_SUCCESS;
4182}
4183
4184
4185/** @callback_method_impl{FNCPUMRDMSR} */
4186static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsFetchCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4187{
4188 /** @todo AMD IBS. */
4189 *puValue = 0;
4190 return VINF_SUCCESS;
4191}
4192
4193
4194/** @callback_method_impl{FNCPUMWRMSR} */
4195static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsFetchCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4196{
4197 /** @todo AMD IBS. */
4198 return VINF_SUCCESS;
4199}
4200
4201
4202/** @callback_method_impl{FNCPUMRDMSR} */
4203static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsFetchLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4204{
4205 /** @todo AMD IBS. */
4206 *puValue = 0;
4207 return VINF_SUCCESS;
4208}
4209
4210
4211/** @callback_method_impl{FNCPUMWRMSR} */
4212static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsFetchLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4213{
4214 /** @todo AMD IBS. */
4215 return VINF_SUCCESS;
4216}
4217
4218
4219/** @callback_method_impl{FNCPUMRDMSR} */
4220static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsFetchPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4221{
4222 /** @todo AMD IBS. */
4223 *puValue = 0;
4224 return VINF_SUCCESS;
4225}
4226
4227
4228/** @callback_method_impl{FNCPUMWRMSR} */
4229static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsFetchPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4230{
4231 /** @todo AMD IBS. */
4232 return VINF_SUCCESS;
4233}
4234
4235
4236/** @callback_method_impl{FNCPUMRDMSR} */
4237static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpExecCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4238{
4239 /** @todo AMD IBS. */
4240 *puValue = 0;
4241 return VINF_SUCCESS;
4242}
4243
4244
4245/** @callback_method_impl{FNCPUMWRMSR} */
4246static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpExecCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4247{
4248 /** @todo AMD IBS. */
4249 return VINF_SUCCESS;
4250}
4251
4252
4253/** @callback_method_impl{FNCPUMRDMSR} */
4254static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpRip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4255{
4256 /** @todo AMD IBS. */
4257 *puValue = 0;
4258 return VINF_SUCCESS;
4259}
4260
4261
4262/** @callback_method_impl{FNCPUMWRMSR} */
4263static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpRip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4264{
4265 /** @todo AMD IBS. */
4266 if (!X86_IS_CANONICAL(uValue))
4267 {
4268 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
4269 return VERR_CPUM_RAISE_GP_0;
4270 }
4271 return VINF_SUCCESS;
4272}
4273
4274
4275/** @callback_method_impl{FNCPUMRDMSR} */
4276static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpData(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4277{
4278 /** @todo AMD IBS. */
4279 *puValue = 0;
4280 return VINF_SUCCESS;
4281}
4282
4283
4284/** @callback_method_impl{FNCPUMWRMSR} */
4285static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpData(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4286{
4287 /** @todo AMD IBS. */
4288 return VINF_SUCCESS;
4289}
4290
4291
4292/** @callback_method_impl{FNCPUMRDMSR} */
4293static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpData2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4294{
4295 /** @todo AMD IBS. */
4296 *puValue = 0;
4297 return VINF_SUCCESS;
4298}
4299
4300
4301/** @callback_method_impl{FNCPUMWRMSR} */
4302static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpData2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4303{
4304 /** @todo AMD IBS. */
4305 return VINF_SUCCESS;
4306}
4307
4308
4309/** @callback_method_impl{FNCPUMRDMSR} */
4310static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpData3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4311{
4312 /** @todo AMD IBS. */
4313 *puValue = 0;
4314 return VINF_SUCCESS;
4315}
4316
4317
4318/** @callback_method_impl{FNCPUMWRMSR} */
4319static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpData3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4320{
4321 /** @todo AMD IBS. */
4322 return VINF_SUCCESS;
4323}
4324
4325
4326/** @callback_method_impl{FNCPUMRDMSR} */
4327static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsDcLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4328{
4329 /** @todo AMD IBS. */
4330 *puValue = 0;
4331 return VINF_SUCCESS;
4332}
4333
4334
4335/** @callback_method_impl{FNCPUMWRMSR} */
4336static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsDcLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4337{
4338 /** @todo AMD IBS. */
4339 if (!X86_IS_CANONICAL(uValue))
4340 {
4341 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
4342 return VERR_CPUM_RAISE_GP_0;
4343 }
4344 return VINF_SUCCESS;
4345}
4346
4347
4348/** @callback_method_impl{FNCPUMRDMSR} */
4349static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsDcPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4350{
4351 /** @todo AMD IBS. */
4352 *puValue = 0;
4353 return VINF_SUCCESS;
4354}
4355
4356
4357/** @callback_method_impl{FNCPUMWRMSR} */
4358static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsDcPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4359{
4360 /** @todo AMD IBS. */
4361 return VINF_SUCCESS;
4362}
4363
4364
4365/** @callback_method_impl{FNCPUMRDMSR} */
4366static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4367{
4368 /** @todo AMD IBS. */
4369 *puValue = 0;
4370 return VINF_SUCCESS;
4371}
4372
4373
4374/** @callback_method_impl{FNCPUMWRMSR} */
4375static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4376{
4377 /** @todo AMD IBS. */
4378 return VINF_SUCCESS;
4379}
4380
4381
4382/** @callback_method_impl{FNCPUMRDMSR} */
4383static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam14hIbsBrTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4384{
4385 /** @todo AMD IBS. */
4386 *puValue = 0;
4387 return VINF_SUCCESS;
4388}
4389
4390
4391/** @callback_method_impl{FNCPUMWRMSR} */
4392static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam14hIbsBrTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4393{
4394 /** @todo AMD IBS. */
4395 if (!X86_IS_CANONICAL(uValue))
4396 {
4397 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
4398 return VERR_CPUM_RAISE_GP_0;
4399 }
4400 return VINF_SUCCESS;
4401}
4402
4403
4404
4405/*
4406 * GIM MSRs.
4407 * GIM MSRs.
4408 * GIM MSRs.
4409 */
4410
4411
4412/** @callback_method_impl{FNCPUMRDMSR} */
4413static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Gim(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4414{
4415 return GIMReadMsr(pVCpu, idMsr, pRange, puValue);
4416}
4417
4418
4419/** @callback_method_impl{FNCPUMWRMSR} */
4420static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Gim(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4421{
4422 return GIMWriteMsr(pVCpu, idMsr, pRange, uValue, uRawValue);
4423}
4424
4425
4426/**
4427 * MSR read function table.
4428 */
4429static const PFNCPUMRDMSR g_aCpumRdMsrFns[kCpumMsrRdFn_End] =
4430{
4431 NULL, /* Invalid */
4432 cpumMsrRd_FixedValue,
4433 NULL, /* Alias */
4434 cpumMsrRd_WriteOnly,
4435 cpumMsrRd_Ia32P5McAddr,
4436 cpumMsrRd_Ia32P5McType,
4437 cpumMsrRd_Ia32TimestampCounter,
4438 cpumMsrRd_Ia32PlatformId,
4439 cpumMsrRd_Ia32ApicBase,
4440 cpumMsrRd_Ia32FeatureControl,
4441 cpumMsrRd_Ia32BiosSignId,
4442 cpumMsrRd_Ia32SmmMonitorCtl,
4443 cpumMsrRd_Ia32PmcN,
4444 cpumMsrRd_Ia32MonitorFilterLineSize,
4445 cpumMsrRd_Ia32MPerf,
4446 cpumMsrRd_Ia32APerf,
4447 cpumMsrRd_Ia32MtrrCap,
4448 cpumMsrRd_Ia32MtrrPhysBaseN,
4449 cpumMsrRd_Ia32MtrrPhysMaskN,
4450 cpumMsrRd_Ia32MtrrFixed,
4451 cpumMsrRd_Ia32MtrrDefType,
4452 cpumMsrRd_Ia32Pat,
4453 cpumMsrRd_Ia32SysEnterCs,
4454 cpumMsrRd_Ia32SysEnterEsp,
4455 cpumMsrRd_Ia32SysEnterEip,
4456 cpumMsrRd_Ia32McgCap,
4457 cpumMsrRd_Ia32McgStatus,
4458 cpumMsrRd_Ia32McgCtl,
4459 cpumMsrRd_Ia32DebugCtl,
4460 cpumMsrRd_Ia32SmrrPhysBase,
4461 cpumMsrRd_Ia32SmrrPhysMask,
4462 cpumMsrRd_Ia32PlatformDcaCap,
4463 cpumMsrRd_Ia32CpuDcaCap,
4464 cpumMsrRd_Ia32Dca0Cap,
4465 cpumMsrRd_Ia32PerfEvtSelN,
4466 cpumMsrRd_Ia32PerfStatus,
4467 cpumMsrRd_Ia32PerfCtl,
4468 cpumMsrRd_Ia32FixedCtrN,
4469 cpumMsrRd_Ia32PerfCapabilities,
4470 cpumMsrRd_Ia32FixedCtrCtrl,
4471 cpumMsrRd_Ia32PerfGlobalStatus,
4472 cpumMsrRd_Ia32PerfGlobalCtrl,
4473 cpumMsrRd_Ia32PerfGlobalOvfCtrl,
4474 cpumMsrRd_Ia32PebsEnable,
4475 cpumMsrRd_Ia32ClockModulation,
4476 cpumMsrRd_Ia32ThermInterrupt,
4477 cpumMsrRd_Ia32ThermStatus,
4478 cpumMsrRd_Ia32Therm2Ctl,
4479 cpumMsrRd_Ia32MiscEnable,
4480 cpumMsrRd_Ia32McCtlStatusAddrMiscN,
4481 cpumMsrRd_Ia32McNCtl2,
4482 cpumMsrRd_Ia32DsArea,
4483 cpumMsrRd_Ia32TscDeadline,
4484 cpumMsrRd_Ia32X2ApicN,
4485 cpumMsrRd_Ia32DebugInterface,
4486 cpumMsrRd_Ia32VmxBase,
4487 cpumMsrRd_Ia32VmxPinbasedCtls,
4488 cpumMsrRd_Ia32VmxProcbasedCtls,
4489 cpumMsrRd_Ia32VmxExitCtls,
4490 cpumMsrRd_Ia32VmxEntryCtls,
4491 cpumMsrRd_Ia32VmxMisc,
4492 cpumMsrRd_Ia32VmxCr0Fixed0,
4493 cpumMsrRd_Ia32VmxCr0Fixed1,
4494 cpumMsrRd_Ia32VmxCr4Fixed0,
4495 cpumMsrRd_Ia32VmxCr4Fixed1,
4496 cpumMsrRd_Ia32VmxVmcsEnum,
4497 cpumMsrRd_Ia32VmxProcBasedCtls2,
4498 cpumMsrRd_Ia32VmxEptVpidCap,
4499 cpumMsrRd_Ia32VmxTruePinbasedCtls,
4500 cpumMsrRd_Ia32VmxTrueProcbasedCtls,
4501 cpumMsrRd_Ia32VmxTrueExitCtls,
4502 cpumMsrRd_Ia32VmxTrueEntryCtls,
4503
4504 cpumMsrRd_Amd64Efer,
4505 cpumMsrRd_Amd64SyscallTarget,
4506 cpumMsrRd_Amd64LongSyscallTarget,
4507 cpumMsrRd_Amd64CompSyscallTarget,
4508 cpumMsrRd_Amd64SyscallFlagMask,
4509 cpumMsrRd_Amd64FsBase,
4510 cpumMsrRd_Amd64GsBase,
4511 cpumMsrRd_Amd64KernelGsBase,
4512 cpumMsrRd_Amd64TscAux,
4513
4514 cpumMsrRd_IntelEblCrPowerOn,
4515 cpumMsrRd_IntelI7CoreThreadCount,
4516 cpumMsrRd_IntelP4EbcHardPowerOn,
4517 cpumMsrRd_IntelP4EbcSoftPowerOn,
4518 cpumMsrRd_IntelP4EbcFrequencyId,
4519 cpumMsrRd_IntelP6FsbFrequency,
4520 cpumMsrRd_IntelPlatformInfo,
4521 cpumMsrRd_IntelFlexRatio,
4522 cpumMsrRd_IntelPkgCStConfigControl,
4523 cpumMsrRd_IntelPmgIoCaptureBase,
4524 cpumMsrRd_IntelLastBranchFromToN,
4525 cpumMsrRd_IntelLastBranchFromN,
4526 cpumMsrRd_IntelLastBranchToN,
4527 cpumMsrRd_IntelLastBranchTos,
4528 cpumMsrRd_IntelBblCrCtl,
4529 cpumMsrRd_IntelBblCrCtl3,
4530 cpumMsrRd_IntelI7TemperatureTarget,
4531 cpumMsrRd_IntelI7MsrOffCoreResponseN,
4532 cpumMsrRd_IntelI7MiscPwrMgmt,
4533 cpumMsrRd_IntelP6CrN,
4534 cpumMsrRd_IntelCpuId1FeatureMaskEcdx,
4535 cpumMsrRd_IntelCpuId1FeatureMaskEax,
4536 cpumMsrRd_IntelCpuId80000001FeatureMaskEcdx,
4537 cpumMsrRd_IntelI7SandyAesNiCtl,
4538 cpumMsrRd_IntelI7TurboRatioLimit,
4539 cpumMsrRd_IntelI7LbrSelect,
4540 cpumMsrRd_IntelI7SandyErrorControl,
4541 cpumMsrRd_IntelI7VirtualLegacyWireCap,
4542 cpumMsrRd_IntelI7PowerCtl,
4543 cpumMsrRd_IntelI7SandyPebsNumAlt,
4544 cpumMsrRd_IntelI7PebsLdLat,
4545 cpumMsrRd_IntelI7PkgCnResidencyN,
4546 cpumMsrRd_IntelI7CoreCnResidencyN,
4547 cpumMsrRd_IntelI7SandyVrCurrentConfig,
4548 cpumMsrRd_IntelI7SandyVrMiscConfig,
4549 cpumMsrRd_IntelI7SandyRaplPowerUnit,
4550 cpumMsrRd_IntelI7SandyPkgCnIrtlN,
4551 cpumMsrRd_IntelI7SandyPkgC2Residency,
4552 cpumMsrRd_IntelI7RaplPkgPowerLimit,
4553 cpumMsrRd_IntelI7RaplPkgEnergyStatus,
4554 cpumMsrRd_IntelI7RaplPkgPerfStatus,
4555 cpumMsrRd_IntelI7RaplPkgPowerInfo,
4556 cpumMsrRd_IntelI7RaplDramPowerLimit,
4557 cpumMsrRd_IntelI7RaplDramEnergyStatus,
4558 cpumMsrRd_IntelI7RaplDramPerfStatus,
4559 cpumMsrRd_IntelI7RaplDramPowerInfo,
4560 cpumMsrRd_IntelI7RaplPp0PowerLimit,
4561 cpumMsrRd_IntelI7RaplPp0EnergyStatus,
4562 cpumMsrRd_IntelI7RaplPp0Policy,
4563 cpumMsrRd_IntelI7RaplPp0PerfStatus,
4564 cpumMsrRd_IntelI7RaplPp1PowerLimit,
4565 cpumMsrRd_IntelI7RaplPp1EnergyStatus,
4566 cpumMsrRd_IntelI7RaplPp1Policy,
4567 cpumMsrRd_IntelI7IvyConfigTdpNominal,
4568 cpumMsrRd_IntelI7IvyConfigTdpLevel1,
4569 cpumMsrRd_IntelI7IvyConfigTdpLevel2,
4570 cpumMsrRd_IntelI7IvyConfigTdpControl,
4571 cpumMsrRd_IntelI7IvyTurboActivationRatio,
4572 cpumMsrRd_IntelI7UncPerfGlobalCtrl,
4573 cpumMsrRd_IntelI7UncPerfGlobalStatus,
4574 cpumMsrRd_IntelI7UncPerfGlobalOvfCtrl,
4575 cpumMsrRd_IntelI7UncPerfFixedCtrCtrl,
4576 cpumMsrRd_IntelI7UncPerfFixedCtr,
4577 cpumMsrRd_IntelI7UncCBoxConfig,
4578 cpumMsrRd_IntelI7UncArbPerfCtrN,
4579 cpumMsrRd_IntelI7UncArbPerfEvtSelN,
4580 cpumMsrRd_IntelCore2EmttmCrTablesN,
4581 cpumMsrRd_IntelCore2SmmCStMiscInfo,
4582 cpumMsrRd_IntelCore1ExtConfig,
4583 cpumMsrRd_IntelCore1DtsCalControl,
4584 cpumMsrRd_IntelCore2PeciControl,
4585
4586 cpumMsrRd_P6LastBranchFromIp,
4587 cpumMsrRd_P6LastBranchToIp,
4588 cpumMsrRd_P6LastIntFromIp,
4589 cpumMsrRd_P6LastIntToIp,
4590
4591 cpumMsrRd_AmdFam15hTscRate,
4592 cpumMsrRd_AmdFam15hLwpCfg,
4593 cpumMsrRd_AmdFam15hLwpCbAddr,
4594 cpumMsrRd_AmdFam10hMc4MiscN,
4595 cpumMsrRd_AmdK8PerfCtlN,
4596 cpumMsrRd_AmdK8PerfCtrN,
4597 cpumMsrRd_AmdK8SysCfg,
4598 cpumMsrRd_AmdK8HwCr,
4599 cpumMsrRd_AmdK8IorrBaseN,
4600 cpumMsrRd_AmdK8IorrMaskN,
4601 cpumMsrRd_AmdK8TopOfMemN,
4602 cpumMsrRd_AmdK8NbCfg1,
4603 cpumMsrRd_AmdK8McXcptRedir,
4604 cpumMsrRd_AmdK8CpuNameN,
4605 cpumMsrRd_AmdK8HwThermalCtrl,
4606 cpumMsrRd_AmdK8SwThermalCtrl,
4607 cpumMsrRd_AmdK8FidVidControl,
4608 cpumMsrRd_AmdK8FidVidStatus,
4609 cpumMsrRd_AmdK8McCtlMaskN,
4610 cpumMsrRd_AmdK8SmiOnIoTrapN,
4611 cpumMsrRd_AmdK8SmiOnIoTrapCtlSts,
4612 cpumMsrRd_AmdK8IntPendingMessage,
4613 cpumMsrRd_AmdK8SmiTriggerIoCycle,
4614 cpumMsrRd_AmdFam10hMmioCfgBaseAddr,
4615 cpumMsrRd_AmdFam10hTrapCtlMaybe,
4616 cpumMsrRd_AmdFam10hPStateCurLimit,
4617 cpumMsrRd_AmdFam10hPStateControl,
4618 cpumMsrRd_AmdFam10hPStateStatus,
4619 cpumMsrRd_AmdFam10hPStateN,
4620 cpumMsrRd_AmdFam10hCofVidControl,
4621 cpumMsrRd_AmdFam10hCofVidStatus,
4622 cpumMsrRd_AmdFam10hCStateIoBaseAddr,
4623 cpumMsrRd_AmdFam10hCpuWatchdogTimer,
4624 cpumMsrRd_AmdK8SmmBase,
4625 cpumMsrRd_AmdK8SmmAddr,
4626 cpumMsrRd_AmdK8SmmMask,
4627 cpumMsrRd_AmdK8VmCr,
4628 cpumMsrRd_AmdK8IgnNe,
4629 cpumMsrRd_AmdK8SmmCtl,
4630 cpumMsrRd_AmdK8VmHSavePa,
4631 cpumMsrRd_AmdFam10hVmLockKey,
4632 cpumMsrRd_AmdFam10hSmmLockKey,
4633 cpumMsrRd_AmdFam10hLocalSmiStatus,
4634 cpumMsrRd_AmdFam10hOsVisWrkIdLength,
4635 cpumMsrRd_AmdFam10hOsVisWrkStatus,
4636 cpumMsrRd_AmdFam16hL2IPerfCtlN,
4637 cpumMsrRd_AmdFam16hL2IPerfCtrN,
4638 cpumMsrRd_AmdFam15hNorthbridgePerfCtlN,
4639 cpumMsrRd_AmdFam15hNorthbridgePerfCtrN,
4640 cpumMsrRd_AmdK7MicrocodeCtl,
4641 cpumMsrRd_AmdK7ClusterIdMaybe,
4642 cpumMsrRd_AmdK8CpuIdCtlStd07hEbax,
4643 cpumMsrRd_AmdK8CpuIdCtlStd06hEcx,
4644 cpumMsrRd_AmdK8CpuIdCtlStd01hEdcx,
4645 cpumMsrRd_AmdK8CpuIdCtlExt01hEdcx,
4646 cpumMsrRd_AmdK8PatchLevel,
4647 cpumMsrRd_AmdK7DebugStatusMaybe,
4648 cpumMsrRd_AmdK7BHTraceBaseMaybe,
4649 cpumMsrRd_AmdK7BHTracePtrMaybe,
4650 cpumMsrRd_AmdK7BHTraceLimitMaybe,
4651 cpumMsrRd_AmdK7HardwareDebugToolCfgMaybe,
4652 cpumMsrRd_AmdK7FastFlushCountMaybe,
4653 cpumMsrRd_AmdK7NodeId,
4654 cpumMsrRd_AmdK7DrXAddrMaskN,
4655 cpumMsrRd_AmdK7Dr0DataMatchMaybe,
4656 cpumMsrRd_AmdK7Dr0DataMaskMaybe,
4657 cpumMsrRd_AmdK7LoadStoreCfg,
4658 cpumMsrRd_AmdK7InstrCacheCfg,
4659 cpumMsrRd_AmdK7DataCacheCfg,
4660 cpumMsrRd_AmdK7BusUnitCfg,
4661 cpumMsrRd_AmdK7DebugCtl2Maybe,
4662 cpumMsrRd_AmdFam15hFpuCfg,
4663 cpumMsrRd_AmdFam15hDecoderCfg,
4664 cpumMsrRd_AmdFam10hBusUnitCfg2,
4665 cpumMsrRd_AmdFam15hCombUnitCfg,
4666 cpumMsrRd_AmdFam15hCombUnitCfg2,
4667 cpumMsrRd_AmdFam15hCombUnitCfg3,
4668 cpumMsrRd_AmdFam15hExecUnitCfg,
4669 cpumMsrRd_AmdFam15hLoadStoreCfg2,
4670 cpumMsrRd_AmdFam10hIbsFetchCtl,
4671 cpumMsrRd_AmdFam10hIbsFetchLinAddr,
4672 cpumMsrRd_AmdFam10hIbsFetchPhysAddr,
4673 cpumMsrRd_AmdFam10hIbsOpExecCtl,
4674 cpumMsrRd_AmdFam10hIbsOpRip,
4675 cpumMsrRd_AmdFam10hIbsOpData,
4676 cpumMsrRd_AmdFam10hIbsOpData2,
4677 cpumMsrRd_AmdFam10hIbsOpData3,
4678 cpumMsrRd_AmdFam10hIbsDcLinAddr,
4679 cpumMsrRd_AmdFam10hIbsDcPhysAddr,
4680 cpumMsrRd_AmdFam10hIbsCtl,
4681 cpumMsrRd_AmdFam14hIbsBrTarget,
4682
4683 cpumMsrRd_Gim
4684};
4685
4686
4687/**
4688 * MSR write function table.
4689 */
4690static const PFNCPUMWRMSR g_aCpumWrMsrFns[kCpumMsrWrFn_End] =
4691{
4692 NULL, /* Invalid */
4693 cpumMsrWr_IgnoreWrite,
4694 cpumMsrWr_ReadOnly,
4695 NULL, /* Alias */
4696 cpumMsrWr_Ia32P5McAddr,
4697 cpumMsrWr_Ia32P5McType,
4698 cpumMsrWr_Ia32TimestampCounter,
4699 cpumMsrWr_Ia32ApicBase,
4700 cpumMsrWr_Ia32FeatureControl,
4701 cpumMsrWr_Ia32BiosSignId,
4702 cpumMsrWr_Ia32BiosUpdateTrigger,
4703 cpumMsrWr_Ia32SmmMonitorCtl,
4704 cpumMsrWr_Ia32PmcN,
4705 cpumMsrWr_Ia32MonitorFilterLineSize,
4706 cpumMsrWr_Ia32MPerf,
4707 cpumMsrWr_Ia32APerf,
4708 cpumMsrWr_Ia32MtrrPhysBaseN,
4709 cpumMsrWr_Ia32MtrrPhysMaskN,
4710 cpumMsrWr_Ia32MtrrFixed,
4711 cpumMsrWr_Ia32MtrrDefType,
4712 cpumMsrWr_Ia32Pat,
4713 cpumMsrWr_Ia32SysEnterCs,
4714 cpumMsrWr_Ia32SysEnterEsp,
4715 cpumMsrWr_Ia32SysEnterEip,
4716 cpumMsrWr_Ia32McgStatus,
4717 cpumMsrWr_Ia32McgCtl,
4718 cpumMsrWr_Ia32DebugCtl,
4719 cpumMsrWr_Ia32SmrrPhysBase,
4720 cpumMsrWr_Ia32SmrrPhysMask,
4721 cpumMsrWr_Ia32PlatformDcaCap,
4722 cpumMsrWr_Ia32Dca0Cap,
4723 cpumMsrWr_Ia32PerfEvtSelN,
4724 cpumMsrWr_Ia32PerfStatus,
4725 cpumMsrWr_Ia32PerfCtl,
4726 cpumMsrWr_Ia32FixedCtrN,
4727 cpumMsrWr_Ia32PerfCapabilities,
4728 cpumMsrWr_Ia32FixedCtrCtrl,
4729 cpumMsrWr_Ia32PerfGlobalStatus,
4730 cpumMsrWr_Ia32PerfGlobalCtrl,
4731 cpumMsrWr_Ia32PerfGlobalOvfCtrl,
4732 cpumMsrWr_Ia32PebsEnable,
4733 cpumMsrWr_Ia32ClockModulation,
4734 cpumMsrWr_Ia32ThermInterrupt,
4735 cpumMsrWr_Ia32ThermStatus,
4736 cpumMsrWr_Ia32Therm2Ctl,
4737 cpumMsrWr_Ia32MiscEnable,
4738 cpumMsrWr_Ia32McCtlStatusAddrMiscN,
4739 cpumMsrWr_Ia32McNCtl2,
4740 cpumMsrWr_Ia32DsArea,
4741 cpumMsrWr_Ia32TscDeadline,
4742 cpumMsrWr_Ia32X2ApicN,
4743 cpumMsrWr_Ia32DebugInterface,
4744
4745 cpumMsrWr_Amd64Efer,
4746 cpumMsrWr_Amd64SyscallTarget,
4747 cpumMsrWr_Amd64LongSyscallTarget,
4748 cpumMsrWr_Amd64CompSyscallTarget,
4749 cpumMsrWr_Amd64SyscallFlagMask,
4750 cpumMsrWr_Amd64FsBase,
4751 cpumMsrWr_Amd64GsBase,
4752 cpumMsrWr_Amd64KernelGsBase,
4753 cpumMsrWr_Amd64TscAux,
4754
4755 cpumMsrWr_IntelEblCrPowerOn,
4756 cpumMsrWr_IntelP4EbcHardPowerOn,
4757 cpumMsrWr_IntelP4EbcSoftPowerOn,
4758 cpumMsrWr_IntelP4EbcFrequencyId,
4759 cpumMsrWr_IntelFlexRatio,
4760 cpumMsrWr_IntelPkgCStConfigControl,
4761 cpumMsrWr_IntelPmgIoCaptureBase,
4762 cpumMsrWr_IntelLastBranchFromToN,
4763 cpumMsrWr_IntelLastBranchFromN,
4764 cpumMsrWr_IntelLastBranchToN,
4765 cpumMsrWr_IntelLastBranchTos,
4766 cpumMsrWr_IntelBblCrCtl,
4767 cpumMsrWr_IntelBblCrCtl3,
4768 cpumMsrWr_IntelI7TemperatureTarget,
4769 cpumMsrWr_IntelI7MsrOffCoreResponseN,
4770 cpumMsrWr_IntelI7MiscPwrMgmt,
4771 cpumMsrWr_IntelP6CrN,
4772 cpumMsrWr_IntelCpuId1FeatureMaskEcdx,
4773 cpumMsrWr_IntelCpuId1FeatureMaskEax,
4774 cpumMsrWr_IntelCpuId80000001FeatureMaskEcdx,
4775 cpumMsrWr_IntelI7SandyAesNiCtl,
4776 cpumMsrWr_IntelI7TurboRatioLimit,
4777 cpumMsrWr_IntelI7LbrSelect,
4778 cpumMsrWr_IntelI7SandyErrorControl,
4779 cpumMsrWr_IntelI7PowerCtl,
4780 cpumMsrWr_IntelI7SandyPebsNumAlt,
4781 cpumMsrWr_IntelI7PebsLdLat,
4782 cpumMsrWr_IntelI7SandyVrCurrentConfig,
4783 cpumMsrWr_IntelI7SandyVrMiscConfig,
4784 cpumMsrWr_IntelI7SandyPkgCnIrtlN,
4785 cpumMsrWr_IntelI7RaplPkgPowerLimit,
4786 cpumMsrWr_IntelI7RaplDramPowerLimit,
4787 cpumMsrWr_IntelI7RaplPp0PowerLimit,
4788 cpumMsrWr_IntelI7RaplPp0Policy,
4789 cpumMsrWr_IntelI7RaplPp1PowerLimit,
4790 cpumMsrWr_IntelI7RaplPp1Policy,
4791 cpumMsrWr_IntelI7IvyConfigTdpControl,
4792 cpumMsrWr_IntelI7IvyTurboActivationRatio,
4793 cpumMsrWr_IntelI7UncPerfGlobalCtrl,
4794 cpumMsrWr_IntelI7UncPerfGlobalStatus,
4795 cpumMsrWr_IntelI7UncPerfGlobalOvfCtrl,
4796 cpumMsrWr_IntelI7UncPerfFixedCtrCtrl,
4797 cpumMsrWr_IntelI7UncPerfFixedCtr,
4798 cpumMsrWr_IntelI7UncArbPerfCtrN,
4799 cpumMsrWr_IntelI7UncArbPerfEvtSelN,
4800 cpumMsrWr_IntelCore2EmttmCrTablesN,
4801 cpumMsrWr_IntelCore2SmmCStMiscInfo,
4802 cpumMsrWr_IntelCore1ExtConfig,
4803 cpumMsrWr_IntelCore1DtsCalControl,
4804 cpumMsrWr_IntelCore2PeciControl,
4805
4806 cpumMsrWr_P6LastIntFromIp,
4807 cpumMsrWr_P6LastIntToIp,
4808
4809 cpumMsrWr_AmdFam15hTscRate,
4810 cpumMsrWr_AmdFam15hLwpCfg,
4811 cpumMsrWr_AmdFam15hLwpCbAddr,
4812 cpumMsrWr_AmdFam10hMc4MiscN,
4813 cpumMsrWr_AmdK8PerfCtlN,
4814 cpumMsrWr_AmdK8PerfCtrN,
4815 cpumMsrWr_AmdK8SysCfg,
4816 cpumMsrWr_AmdK8HwCr,
4817 cpumMsrWr_AmdK8IorrBaseN,
4818 cpumMsrWr_AmdK8IorrMaskN,
4819 cpumMsrWr_AmdK8TopOfMemN,
4820 cpumMsrWr_AmdK8NbCfg1,
4821 cpumMsrWr_AmdK8McXcptRedir,
4822 cpumMsrWr_AmdK8CpuNameN,
4823 cpumMsrWr_AmdK8HwThermalCtrl,
4824 cpumMsrWr_AmdK8SwThermalCtrl,
4825 cpumMsrWr_AmdK8FidVidControl,
4826 cpumMsrWr_AmdK8McCtlMaskN,
4827 cpumMsrWr_AmdK8SmiOnIoTrapN,
4828 cpumMsrWr_AmdK8SmiOnIoTrapCtlSts,
4829 cpumMsrWr_AmdK8IntPendingMessage,
4830 cpumMsrWr_AmdK8SmiTriggerIoCycle,
4831 cpumMsrWr_AmdFam10hMmioCfgBaseAddr,
4832 cpumMsrWr_AmdFam10hTrapCtlMaybe,
4833 cpumMsrWr_AmdFam10hPStateControl,
4834 cpumMsrWr_AmdFam10hPStateStatus,
4835 cpumMsrWr_AmdFam10hPStateN,
4836 cpumMsrWr_AmdFam10hCofVidControl,
4837 cpumMsrWr_AmdFam10hCofVidStatus,
4838 cpumMsrWr_AmdFam10hCStateIoBaseAddr,
4839 cpumMsrWr_AmdFam10hCpuWatchdogTimer,
4840 cpumMsrWr_AmdK8SmmBase,
4841 cpumMsrWr_AmdK8SmmAddr,
4842 cpumMsrWr_AmdK8SmmMask,
4843 cpumMsrWr_AmdK8VmCr,
4844 cpumMsrWr_AmdK8IgnNe,
4845 cpumMsrWr_AmdK8SmmCtl,
4846 cpumMsrWr_AmdK8VmHSavePa,
4847 cpumMsrWr_AmdFam10hVmLockKey,
4848 cpumMsrWr_AmdFam10hSmmLockKey,
4849 cpumMsrWr_AmdFam10hLocalSmiStatus,
4850 cpumMsrWr_AmdFam10hOsVisWrkIdLength,
4851 cpumMsrWr_AmdFam10hOsVisWrkStatus,
4852 cpumMsrWr_AmdFam16hL2IPerfCtlN,
4853 cpumMsrWr_AmdFam16hL2IPerfCtrN,
4854 cpumMsrWr_AmdFam15hNorthbridgePerfCtlN,
4855 cpumMsrWr_AmdFam15hNorthbridgePerfCtrN,
4856 cpumMsrWr_AmdK7MicrocodeCtl,
4857 cpumMsrWr_AmdK7ClusterIdMaybe,
4858 cpumMsrWr_AmdK8CpuIdCtlStd07hEbax,
4859 cpumMsrWr_AmdK8CpuIdCtlStd06hEcx,
4860 cpumMsrWr_AmdK8CpuIdCtlStd01hEdcx,
4861 cpumMsrWr_AmdK8CpuIdCtlExt01hEdcx,
4862 cpumMsrWr_AmdK8PatchLoader,
4863 cpumMsrWr_AmdK7DebugStatusMaybe,
4864 cpumMsrWr_AmdK7BHTraceBaseMaybe,
4865 cpumMsrWr_AmdK7BHTracePtrMaybe,
4866 cpumMsrWr_AmdK7BHTraceLimitMaybe,
4867 cpumMsrWr_AmdK7HardwareDebugToolCfgMaybe,
4868 cpumMsrWr_AmdK7FastFlushCountMaybe,
4869 cpumMsrWr_AmdK7NodeId,
4870 cpumMsrWr_AmdK7DrXAddrMaskN,
4871 cpumMsrWr_AmdK7Dr0DataMatchMaybe,
4872 cpumMsrWr_AmdK7Dr0DataMaskMaybe,
4873 cpumMsrWr_AmdK7LoadStoreCfg,
4874 cpumMsrWr_AmdK7InstrCacheCfg,
4875 cpumMsrWr_AmdK7DataCacheCfg,
4876 cpumMsrWr_AmdK7BusUnitCfg,
4877 cpumMsrWr_AmdK7DebugCtl2Maybe,
4878 cpumMsrWr_AmdFam15hFpuCfg,
4879 cpumMsrWr_AmdFam15hDecoderCfg,
4880 cpumMsrWr_AmdFam10hBusUnitCfg2,
4881 cpumMsrWr_AmdFam15hCombUnitCfg,
4882 cpumMsrWr_AmdFam15hCombUnitCfg2,
4883 cpumMsrWr_AmdFam15hCombUnitCfg3,
4884 cpumMsrWr_AmdFam15hExecUnitCfg,
4885 cpumMsrWr_AmdFam15hLoadStoreCfg2,
4886 cpumMsrWr_AmdFam10hIbsFetchCtl,
4887 cpumMsrWr_AmdFam10hIbsFetchLinAddr,
4888 cpumMsrWr_AmdFam10hIbsFetchPhysAddr,
4889 cpumMsrWr_AmdFam10hIbsOpExecCtl,
4890 cpumMsrWr_AmdFam10hIbsOpRip,
4891 cpumMsrWr_AmdFam10hIbsOpData,
4892 cpumMsrWr_AmdFam10hIbsOpData2,
4893 cpumMsrWr_AmdFam10hIbsOpData3,
4894 cpumMsrWr_AmdFam10hIbsDcLinAddr,
4895 cpumMsrWr_AmdFam10hIbsDcPhysAddr,
4896 cpumMsrWr_AmdFam10hIbsCtl,
4897 cpumMsrWr_AmdFam14hIbsBrTarget,
4898
4899 cpumMsrWr_Gim
4900};
4901
4902
4903/**
4904 * Looks up the range for the given MSR.
4905 *
4906 * @returns Pointer to the range if found, NULL if not.
4907 * @param pVM The cross context VM structure.
4908 * @param idMsr The MSR to look up.
4909 */
4910# ifndef IN_RING3
4911static
4912# endif
4913PCPUMMSRRANGE cpumLookupMsrRange(PVM pVM, uint32_t idMsr)
4914{
4915 /*
4916 * Binary lookup.
4917 */
4918 uint32_t cRanges = pVM->cpum.s.GuestInfo.cMsrRanges;
4919 if (!cRanges)
4920 return NULL;
4921 PCPUMMSRRANGE paRanges = pVM->cpum.s.GuestInfo.CTX_SUFF(paMsrRanges);
4922 for (;;)
4923 {
4924 uint32_t i = cRanges / 2;
4925 if (idMsr < paRanges[i].uFirst)
4926 {
4927 if (i == 0)
4928 break;
4929 cRanges = i;
4930 }
4931 else if (idMsr > paRanges[i].uLast)
4932 {
4933 i++;
4934 if (i >= cRanges)
4935 break;
4936 cRanges -= i;
4937 paRanges = &paRanges[i];
4938 }
4939 else
4940 {
4941 if (paRanges[i].enmRdFn == kCpumMsrRdFn_MsrAlias)
4942 return cpumLookupMsrRange(pVM, paRanges[i].uValue);
4943 return &paRanges[i];
4944 }
4945 }
4946
4947# ifdef VBOX_STRICT
4948 /*
4949 * Linear lookup to verify the above binary search.
4950 */
4951 uint32_t cLeft = pVM->cpum.s.GuestInfo.cMsrRanges;
4952 PCPUMMSRRANGE pCur = pVM->cpum.s.GuestInfo.CTX_SUFF(paMsrRanges);
4953 while (cLeft-- > 0)
4954 {
4955 if (idMsr >= pCur->uFirst && idMsr <= pCur->uLast)
4956 {
4957 AssertFailed();
4958 if (pCur->enmRdFn == kCpumMsrRdFn_MsrAlias)
4959 return cpumLookupMsrRange(pVM, pCur->uValue);
4960 return pCur;
4961 }
4962 pCur++;
4963 }
4964# endif
4965 return NULL;
4966}
4967
4968
4969/**
4970 * Query a guest MSR.
4971 *
4972 * The caller is responsible for checking privilege if the call is the result of
4973 * a RDMSR instruction. We'll do the rest.
4974 *
4975 * @retval VINF_SUCCESS on success.
4976 * @retval VINF_CPUM_R3_MSR_READ if the MSR read could not be serviced in the
4977 * current context (raw-mode or ring-0).
4978 * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR), the caller is
4979 * expected to take the appropriate actions. @a *puValue is set to 0.
4980 * @param pVCpu Pointer to the VMCPU.
4981 * @param idMsr The MSR.
4982 * @param puValue Where to return the value.
4983 *
4984 * @remarks This will always return the right values, even when we're in the
4985 * recompiler.
4986 */
4987VMMDECL(VBOXSTRICTRC) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue)
4988{
4989 *puValue = 0;
4990
4991 VBOXSTRICTRC rcStrict;
4992 PVM pVM = pVCpu->CTX_SUFF(pVM);
4993 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, idMsr);
4994 if (pRange)
4995 {
4996 CPUMMSRRDFN enmRdFn = (CPUMMSRRDFN)pRange->enmRdFn;
4997 AssertReturn(enmRdFn > kCpumMsrRdFn_Invalid && enmRdFn < kCpumMsrRdFn_End, VERR_CPUM_IPE_1);
4998
4999 PFNCPUMRDMSR pfnRdMsr = g_aCpumRdMsrFns[enmRdFn];
5000 AssertReturn(pfnRdMsr, VERR_CPUM_IPE_2);
5001
5002 STAM_COUNTER_INC(&pRange->cReads);
5003 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReads);
5004
5005 rcStrict = pfnRdMsr(pVCpu, idMsr, pRange, puValue);
5006 if (rcStrict == VINF_SUCCESS)
5007 Log2(("CPUM: RDMSR %#x (%s) -> %#llx\n", idMsr, pRange->szName, *puValue));
5008 else if (rcStrict == VERR_CPUM_RAISE_GP_0)
5009 {
5010 Log(("CPUM: RDMSR %#x (%s) -> #GP(0)\n", idMsr, pRange->szName));
5011 STAM_COUNTER_INC(&pRange->cGps);
5012 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReadsRaiseGp);
5013 }
5014#ifndef IN_RING3
5015 else if (rcStrict == VINF_CPUM_R3_MSR_READ)
5016 Log(("CPUM: RDMSR %#x (%s) -> ring-3\n", idMsr, pRange->szName));
5017#endif
5018 else
5019 {
5020 Log(("CPUM: RDMSR %#x (%s) -> rcStrict=%Rrc\n", idMsr, pRange->szName, VBOXSTRICTRC_VAL(rcStrict)));
5021 AssertMsgStmt(RT_FAILURE_NP(rcStrict), ("%Rrc idMsr=%#x\n", VBOXSTRICTRC_VAL(rcStrict), idMsr),
5022 rcStrict = VERR_IPE_UNEXPECTED_INFO_STATUS);
5023 Assert(rcStrict != VERR_EM_INTERPRETER);
5024 }
5025 }
5026 else
5027 {
5028 Log(("CPUM: Unknown RDMSR %#x -> #GP(0)\n", idMsr));
5029 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReads);
5030 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReadsUnknown);
5031 rcStrict = VERR_CPUM_RAISE_GP_0;
5032 }
5033 return rcStrict;
5034}
5035
5036
5037/**
5038 * Writes to a guest MSR.
5039 *
5040 * The caller is responsible for checking privilege if the call is the result of
5041 * a WRMSR instruction. We'll do the rest.
5042 *
5043 * @retval VINF_SUCCESS on success.
5044 * @retval VINF_CPUM_R3_MSR_WRITE if the MSR write could not be serviced in the
5045 * current context (raw-mode or ring-0).
5046 * @retval VERR_CPUM_RAISE_GP_0 on failure, the caller is expected to take the
5047 * appropriate actions.
5048 *
5049 * @param pVCpu Pointer to the VMCPU.
5050 * @param idMsr The MSR id.
5051 * @param uValue The value to set.
5052 *
5053 * @remarks Everyone changing MSR values, including the recompiler, shall do it
5054 * by calling this method. This makes sure we have current values and
5055 * that we trigger all the right actions when something changes.
5056 *
5057 * For performance reasons, this actually isn't entirely true for some
5058 * MSRs when in HM mode. The code here and in HM must be aware of
5059 * this.
5060 */
5061VMMDECL(VBOXSTRICTRC) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue)
5062{
5063 VBOXSTRICTRC rcStrict;
5064 PVM pVM = pVCpu->CTX_SUFF(pVM);
5065 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, idMsr);
5066 if (pRange)
5067 {
5068 STAM_COUNTER_INC(&pRange->cWrites);
5069 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWrites);
5070
5071 if (!(uValue & pRange->fWrGpMask))
5072 {
5073 CPUMMSRWRFN enmWrFn = (CPUMMSRWRFN)pRange->enmWrFn;
5074 AssertReturn(enmWrFn > kCpumMsrWrFn_Invalid && enmWrFn < kCpumMsrWrFn_End, VERR_CPUM_IPE_1);
5075
5076 PFNCPUMWRMSR pfnWrMsr = g_aCpumWrMsrFns[enmWrFn];
5077 AssertReturn(pfnWrMsr, VERR_CPUM_IPE_2);
5078
5079 uint64_t uValueAdjusted = uValue & ~pRange->fWrIgnMask;
5080 if (uValueAdjusted != uValue)
5081 {
5082 STAM_COUNTER_INC(&pRange->cIgnoredBits);
5083 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesToIgnoredBits);
5084 }
5085
5086 rcStrict = pfnWrMsr(pVCpu, idMsr, pRange, uValueAdjusted, uValue);
5087 if (rcStrict == VINF_SUCCESS)
5088 Log2(("CPUM: WRMSR %#x (%s), %#llx [%#llx]\n", idMsr, pRange->szName, uValueAdjusted, uValue));
5089 else if (rcStrict == VERR_CPUM_RAISE_GP_0)
5090 {
5091 Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> #GP(0)\n", idMsr, pRange->szName, uValueAdjusted, uValue));
5092 STAM_COUNTER_INC(&pRange->cGps);
5093 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesRaiseGp);
5094 }
5095#ifndef IN_RING3
5096 else if (rcStrict == VINF_CPUM_R3_MSR_WRITE)
5097 Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> ring-3\n", idMsr, pRange->szName, uValueAdjusted, uValue));
5098#endif
5099 else
5100 {
5101 Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> rcStrict=%Rrc\n",
5102 idMsr, pRange->szName, uValueAdjusted, uValue, VBOXSTRICTRC_VAL(rcStrict)));
5103 AssertMsgStmt(RT_FAILURE_NP(rcStrict), ("%Rrc idMsr=%#x\n", VBOXSTRICTRC_VAL(rcStrict), idMsr),
5104 rcStrict = VERR_IPE_UNEXPECTED_INFO_STATUS);
5105 Assert(rcStrict != VERR_EM_INTERPRETER);
5106 }
5107 }
5108 else
5109 {
5110 Log(("CPUM: WRMSR %#x (%s), %#llx -> #GP(0) - invalid bits %#llx\n",
5111 idMsr, pRange->szName, uValue, uValue & pRange->fWrGpMask));
5112 STAM_COUNTER_INC(&pRange->cGps);
5113 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesRaiseGp);
5114 rcStrict = VERR_CPUM_RAISE_GP_0;
5115 }
5116 }
5117 else
5118 {
5119 Log(("CPUM: Unknown WRMSR %#x, %#llx -> #GP(0)\n", idMsr, uValue));
5120 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWrites);
5121 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesUnknown);
5122 rcStrict = VERR_CPUM_RAISE_GP_0;
5123 }
5124 return rcStrict;
5125}
5126
5127
5128#if defined(VBOX_STRICT) && defined(IN_RING3)
5129/**
5130 * Performs some checks on the static data related to MSRs.
5131 *
5132 * @returns VINF_SUCCESS on success, error on failure.
5133 */
5134int cpumR3MsrStrictInitChecks(void)
5135{
5136#define CPUM_ASSERT_RD_MSR_FN(a_Register) \
5137 AssertReturn(g_aCpumRdMsrFns[kCpumMsrRdFn_##a_Register] == cpumMsrRd_##a_Register, VERR_CPUM_IPE_2);
5138#define CPUM_ASSERT_WR_MSR_FN(a_Register) \
5139 AssertReturn(g_aCpumWrMsrFns[kCpumMsrWrFn_##a_Register] == cpumMsrWr_##a_Register, VERR_CPUM_IPE_2);
5140
5141 AssertReturn(g_aCpumRdMsrFns[kCpumMsrRdFn_Invalid] == NULL, VERR_CPUM_IPE_2);
5142 CPUM_ASSERT_RD_MSR_FN(FixedValue);
5143 CPUM_ASSERT_RD_MSR_FN(WriteOnly);
5144 CPUM_ASSERT_RD_MSR_FN(Ia32P5McAddr);
5145 CPUM_ASSERT_RD_MSR_FN(Ia32P5McType);
5146 CPUM_ASSERT_RD_MSR_FN(Ia32TimestampCounter);
5147 CPUM_ASSERT_RD_MSR_FN(Ia32PlatformId);
5148 CPUM_ASSERT_RD_MSR_FN(Ia32ApicBase);
5149 CPUM_ASSERT_RD_MSR_FN(Ia32FeatureControl);
5150 CPUM_ASSERT_RD_MSR_FN(Ia32BiosSignId);
5151 CPUM_ASSERT_RD_MSR_FN(Ia32SmmMonitorCtl);
5152 CPUM_ASSERT_RD_MSR_FN(Ia32PmcN);
5153 CPUM_ASSERT_RD_MSR_FN(Ia32MonitorFilterLineSize);
5154 CPUM_ASSERT_RD_MSR_FN(Ia32MPerf);
5155 CPUM_ASSERT_RD_MSR_FN(Ia32APerf);
5156 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrCap);
5157 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrPhysBaseN);
5158 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrPhysMaskN);
5159 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrFixed);
5160 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrDefType);
5161 CPUM_ASSERT_RD_MSR_FN(Ia32Pat);
5162 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterCs);
5163 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterEsp);
5164 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterEip);
5165 CPUM_ASSERT_RD_MSR_FN(Ia32McgCap);
5166 CPUM_ASSERT_RD_MSR_FN(Ia32McgStatus);
5167 CPUM_ASSERT_RD_MSR_FN(Ia32McgCtl);
5168 CPUM_ASSERT_RD_MSR_FN(Ia32DebugCtl);
5169 CPUM_ASSERT_RD_MSR_FN(Ia32SmrrPhysBase);
5170 CPUM_ASSERT_RD_MSR_FN(Ia32SmrrPhysMask);
5171 CPUM_ASSERT_RD_MSR_FN(Ia32PlatformDcaCap);
5172 CPUM_ASSERT_RD_MSR_FN(Ia32CpuDcaCap);
5173 CPUM_ASSERT_RD_MSR_FN(Ia32Dca0Cap);
5174 CPUM_ASSERT_RD_MSR_FN(Ia32PerfEvtSelN);
5175 CPUM_ASSERT_RD_MSR_FN(Ia32PerfStatus);
5176 CPUM_ASSERT_RD_MSR_FN(Ia32PerfCtl);
5177 CPUM_ASSERT_RD_MSR_FN(Ia32FixedCtrN);
5178 CPUM_ASSERT_RD_MSR_FN(Ia32PerfCapabilities);
5179 CPUM_ASSERT_RD_MSR_FN(Ia32FixedCtrCtrl);
5180 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalStatus);
5181 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalCtrl);
5182 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalOvfCtrl);
5183 CPUM_ASSERT_RD_MSR_FN(Ia32PebsEnable);
5184 CPUM_ASSERT_RD_MSR_FN(Ia32ClockModulation);
5185 CPUM_ASSERT_RD_MSR_FN(Ia32ThermInterrupt);
5186 CPUM_ASSERT_RD_MSR_FN(Ia32ThermStatus);
5187 CPUM_ASSERT_RD_MSR_FN(Ia32MiscEnable);
5188 CPUM_ASSERT_RD_MSR_FN(Ia32McCtlStatusAddrMiscN);
5189 CPUM_ASSERT_RD_MSR_FN(Ia32McNCtl2);
5190 CPUM_ASSERT_RD_MSR_FN(Ia32DsArea);
5191 CPUM_ASSERT_RD_MSR_FN(Ia32TscDeadline);
5192 CPUM_ASSERT_RD_MSR_FN(Ia32X2ApicN);
5193 CPUM_ASSERT_RD_MSR_FN(Ia32DebugInterface);
5194 CPUM_ASSERT_RD_MSR_FN(Ia32VmxBase);
5195 CPUM_ASSERT_RD_MSR_FN(Ia32VmxPinbasedCtls);
5196 CPUM_ASSERT_RD_MSR_FN(Ia32VmxProcbasedCtls);
5197 CPUM_ASSERT_RD_MSR_FN(Ia32VmxExitCtls);
5198 CPUM_ASSERT_RD_MSR_FN(Ia32VmxEntryCtls);
5199 CPUM_ASSERT_RD_MSR_FN(Ia32VmxMisc);
5200 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr0Fixed0);
5201 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr0Fixed1);
5202 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr4Fixed0);
5203 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr4Fixed1);
5204 CPUM_ASSERT_RD_MSR_FN(Ia32VmxVmcsEnum);
5205 CPUM_ASSERT_RD_MSR_FN(Ia32VmxProcBasedCtls2);
5206 CPUM_ASSERT_RD_MSR_FN(Ia32VmxEptVpidCap);
5207 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTruePinbasedCtls);
5208 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueProcbasedCtls);
5209 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueExitCtls);
5210 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueEntryCtls);
5211
5212 CPUM_ASSERT_RD_MSR_FN(Amd64Efer);
5213 CPUM_ASSERT_RD_MSR_FN(Amd64SyscallTarget);
5214 CPUM_ASSERT_RD_MSR_FN(Amd64LongSyscallTarget);
5215 CPUM_ASSERT_RD_MSR_FN(Amd64CompSyscallTarget);
5216 CPUM_ASSERT_RD_MSR_FN(Amd64SyscallFlagMask);
5217 CPUM_ASSERT_RD_MSR_FN(Amd64FsBase);
5218 CPUM_ASSERT_RD_MSR_FN(Amd64GsBase);
5219 CPUM_ASSERT_RD_MSR_FN(Amd64KernelGsBase);
5220 CPUM_ASSERT_RD_MSR_FN(Amd64TscAux);
5221
5222 CPUM_ASSERT_RD_MSR_FN(IntelEblCrPowerOn);
5223 CPUM_ASSERT_RD_MSR_FN(IntelI7CoreThreadCount);
5224 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcHardPowerOn);
5225 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcSoftPowerOn);
5226 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcFrequencyId);
5227 CPUM_ASSERT_RD_MSR_FN(IntelP6FsbFrequency);
5228 CPUM_ASSERT_RD_MSR_FN(IntelPlatformInfo);
5229 CPUM_ASSERT_RD_MSR_FN(IntelFlexRatio);
5230 CPUM_ASSERT_RD_MSR_FN(IntelPkgCStConfigControl);
5231 CPUM_ASSERT_RD_MSR_FN(IntelPmgIoCaptureBase);
5232 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchFromToN);
5233 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchFromN);
5234 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchToN);
5235 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchTos);
5236 CPUM_ASSERT_RD_MSR_FN(IntelBblCrCtl);
5237 CPUM_ASSERT_RD_MSR_FN(IntelBblCrCtl3);
5238 CPUM_ASSERT_RD_MSR_FN(IntelI7TemperatureTarget);
5239 CPUM_ASSERT_RD_MSR_FN(IntelI7MsrOffCoreResponseN);
5240 CPUM_ASSERT_RD_MSR_FN(IntelI7MiscPwrMgmt);
5241 CPUM_ASSERT_RD_MSR_FN(IntelP6CrN);
5242 CPUM_ASSERT_RD_MSR_FN(IntelCpuId1FeatureMaskEcdx);
5243 CPUM_ASSERT_RD_MSR_FN(IntelCpuId1FeatureMaskEax);
5244 CPUM_ASSERT_RD_MSR_FN(IntelCpuId80000001FeatureMaskEcdx);
5245 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyAesNiCtl);
5246 CPUM_ASSERT_RD_MSR_FN(IntelI7TurboRatioLimit);
5247 CPUM_ASSERT_RD_MSR_FN(IntelI7LbrSelect);
5248 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyErrorControl);
5249 CPUM_ASSERT_RD_MSR_FN(IntelI7VirtualLegacyWireCap);
5250 CPUM_ASSERT_RD_MSR_FN(IntelI7PowerCtl);
5251 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPebsNumAlt);
5252 CPUM_ASSERT_RD_MSR_FN(IntelI7PebsLdLat);
5253 CPUM_ASSERT_RD_MSR_FN(IntelI7PkgCnResidencyN);
5254 CPUM_ASSERT_RD_MSR_FN(IntelI7CoreCnResidencyN);
5255 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyVrCurrentConfig);
5256 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyVrMiscConfig);
5257 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyRaplPowerUnit);
5258 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPkgCnIrtlN);
5259 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPkgC2Residency);
5260 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPowerLimit);
5261 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgEnergyStatus);
5262 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPerfStatus);
5263 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPowerInfo);
5264 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPowerLimit);
5265 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramEnergyStatus);
5266 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPerfStatus);
5267 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPowerInfo);
5268 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0PowerLimit);
5269 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0EnergyStatus);
5270 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0Policy);
5271 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0PerfStatus);
5272 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1PowerLimit);
5273 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1EnergyStatus);
5274 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1Policy);
5275 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpNominal);
5276 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpLevel1);
5277 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpLevel2);
5278 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpControl);
5279 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyTurboActivationRatio);
5280 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalCtrl);
5281 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalStatus);
5282 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalOvfCtrl);
5283 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfFixedCtrCtrl);
5284 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfFixedCtr);
5285 CPUM_ASSERT_RD_MSR_FN(IntelI7UncCBoxConfig);
5286 CPUM_ASSERT_RD_MSR_FN(IntelI7UncArbPerfCtrN);
5287 CPUM_ASSERT_RD_MSR_FN(IntelI7UncArbPerfEvtSelN);
5288 CPUM_ASSERT_RD_MSR_FN(IntelCore2EmttmCrTablesN);
5289 CPUM_ASSERT_RD_MSR_FN(IntelCore2SmmCStMiscInfo);
5290 CPUM_ASSERT_RD_MSR_FN(IntelCore1ExtConfig);
5291 CPUM_ASSERT_RD_MSR_FN(IntelCore1DtsCalControl);
5292 CPUM_ASSERT_RD_MSR_FN(IntelCore2PeciControl);
5293
5294 CPUM_ASSERT_RD_MSR_FN(P6LastBranchFromIp);
5295 CPUM_ASSERT_RD_MSR_FN(P6LastBranchToIp);
5296 CPUM_ASSERT_RD_MSR_FN(P6LastIntFromIp);
5297 CPUM_ASSERT_RD_MSR_FN(P6LastIntToIp);
5298
5299 CPUM_ASSERT_RD_MSR_FN(AmdFam15hTscRate);
5300 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLwpCfg);
5301 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLwpCbAddr);
5302 CPUM_ASSERT_RD_MSR_FN(AmdFam10hMc4MiscN);
5303 CPUM_ASSERT_RD_MSR_FN(AmdK8PerfCtlN);
5304 CPUM_ASSERT_RD_MSR_FN(AmdK8PerfCtrN);
5305 CPUM_ASSERT_RD_MSR_FN(AmdK8SysCfg);
5306 CPUM_ASSERT_RD_MSR_FN(AmdK8HwCr);
5307 CPUM_ASSERT_RD_MSR_FN(AmdK8IorrBaseN);
5308 CPUM_ASSERT_RD_MSR_FN(AmdK8IorrMaskN);
5309 CPUM_ASSERT_RD_MSR_FN(AmdK8TopOfMemN);
5310 CPUM_ASSERT_RD_MSR_FN(AmdK8NbCfg1);
5311 CPUM_ASSERT_RD_MSR_FN(AmdK8McXcptRedir);
5312 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuNameN);
5313 CPUM_ASSERT_RD_MSR_FN(AmdK8HwThermalCtrl);
5314 CPUM_ASSERT_RD_MSR_FN(AmdK8SwThermalCtrl);
5315 CPUM_ASSERT_RD_MSR_FN(AmdK8FidVidControl);
5316 CPUM_ASSERT_RD_MSR_FN(AmdK8FidVidStatus);
5317 CPUM_ASSERT_RD_MSR_FN(AmdK8McCtlMaskN);
5318 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiOnIoTrapN);
5319 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiOnIoTrapCtlSts);
5320 CPUM_ASSERT_RD_MSR_FN(AmdK8IntPendingMessage);
5321 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiTriggerIoCycle);
5322 CPUM_ASSERT_RD_MSR_FN(AmdFam10hMmioCfgBaseAddr);
5323 CPUM_ASSERT_RD_MSR_FN(AmdFam10hTrapCtlMaybe);
5324 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateCurLimit);
5325 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateControl);
5326 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateStatus);
5327 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateN);
5328 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCofVidControl);
5329 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCofVidStatus);
5330 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCStateIoBaseAddr);
5331 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCpuWatchdogTimer);
5332 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmBase);
5333 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmAddr);
5334 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmMask);
5335 CPUM_ASSERT_RD_MSR_FN(AmdK8VmCr);
5336 CPUM_ASSERT_RD_MSR_FN(AmdK8IgnNe);
5337 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmCtl);
5338 CPUM_ASSERT_RD_MSR_FN(AmdK8VmHSavePa);
5339 CPUM_ASSERT_RD_MSR_FN(AmdFam10hVmLockKey);
5340 CPUM_ASSERT_RD_MSR_FN(AmdFam10hSmmLockKey);
5341 CPUM_ASSERT_RD_MSR_FN(AmdFam10hLocalSmiStatus);
5342 CPUM_ASSERT_RD_MSR_FN(AmdFam10hOsVisWrkIdLength);
5343 CPUM_ASSERT_RD_MSR_FN(AmdFam10hOsVisWrkStatus);
5344 CPUM_ASSERT_RD_MSR_FN(AmdFam16hL2IPerfCtlN);
5345 CPUM_ASSERT_RD_MSR_FN(AmdFam16hL2IPerfCtrN);
5346 CPUM_ASSERT_RD_MSR_FN(AmdFam15hNorthbridgePerfCtlN);
5347 CPUM_ASSERT_RD_MSR_FN(AmdFam15hNorthbridgePerfCtrN);
5348 CPUM_ASSERT_RD_MSR_FN(AmdK7MicrocodeCtl);
5349 CPUM_ASSERT_RD_MSR_FN(AmdK7ClusterIdMaybe);
5350 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd07hEbax);
5351 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd06hEcx);
5352 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd01hEdcx);
5353 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlExt01hEdcx);
5354 CPUM_ASSERT_RD_MSR_FN(AmdK8PatchLevel);
5355 CPUM_ASSERT_RD_MSR_FN(AmdK7DebugStatusMaybe);
5356 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTraceBaseMaybe);
5357 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTracePtrMaybe);
5358 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTraceLimitMaybe);
5359 CPUM_ASSERT_RD_MSR_FN(AmdK7HardwareDebugToolCfgMaybe);
5360 CPUM_ASSERT_RD_MSR_FN(AmdK7FastFlushCountMaybe);
5361 CPUM_ASSERT_RD_MSR_FN(AmdK7NodeId);
5362 CPUM_ASSERT_RD_MSR_FN(AmdK7DrXAddrMaskN);
5363 CPUM_ASSERT_RD_MSR_FN(AmdK7Dr0DataMatchMaybe);
5364 CPUM_ASSERT_RD_MSR_FN(AmdK7Dr0DataMaskMaybe);
5365 CPUM_ASSERT_RD_MSR_FN(AmdK7LoadStoreCfg);
5366 CPUM_ASSERT_RD_MSR_FN(AmdK7InstrCacheCfg);
5367 CPUM_ASSERT_RD_MSR_FN(AmdK7DataCacheCfg);
5368 CPUM_ASSERT_RD_MSR_FN(AmdK7BusUnitCfg);
5369 CPUM_ASSERT_RD_MSR_FN(AmdK7DebugCtl2Maybe);
5370 CPUM_ASSERT_RD_MSR_FN(AmdFam15hFpuCfg);
5371 CPUM_ASSERT_RD_MSR_FN(AmdFam15hDecoderCfg);
5372 CPUM_ASSERT_RD_MSR_FN(AmdFam10hBusUnitCfg2);
5373 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg);
5374 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg2);
5375 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg3);
5376 CPUM_ASSERT_RD_MSR_FN(AmdFam15hExecUnitCfg);
5377 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLoadStoreCfg2);
5378 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchCtl);
5379 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchLinAddr);
5380 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchPhysAddr);
5381 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpExecCtl);
5382 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpRip);
5383 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData);
5384 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData2);
5385 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData3);
5386 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsDcLinAddr);
5387 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsDcPhysAddr);
5388 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsCtl);
5389 CPUM_ASSERT_RD_MSR_FN(AmdFam14hIbsBrTarget);
5390
5391 CPUM_ASSERT_RD_MSR_FN(Gim)
5392
5393 AssertReturn(g_aCpumWrMsrFns[kCpumMsrWrFn_Invalid] == NULL, VERR_CPUM_IPE_2);
5394 CPUM_ASSERT_WR_MSR_FN(Ia32P5McAddr);
5395 CPUM_ASSERT_WR_MSR_FN(Ia32P5McType);
5396 CPUM_ASSERT_WR_MSR_FN(Ia32TimestampCounter);
5397 CPUM_ASSERT_WR_MSR_FN(Ia32ApicBase);
5398 CPUM_ASSERT_WR_MSR_FN(Ia32FeatureControl);
5399 CPUM_ASSERT_WR_MSR_FN(Ia32BiosSignId);
5400 CPUM_ASSERT_WR_MSR_FN(Ia32BiosUpdateTrigger);
5401 CPUM_ASSERT_WR_MSR_FN(Ia32SmmMonitorCtl);
5402 CPUM_ASSERT_WR_MSR_FN(Ia32PmcN);
5403 CPUM_ASSERT_WR_MSR_FN(Ia32MonitorFilterLineSize);
5404 CPUM_ASSERT_WR_MSR_FN(Ia32MPerf);
5405 CPUM_ASSERT_WR_MSR_FN(Ia32APerf);
5406 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrPhysBaseN);
5407 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrPhysMaskN);
5408 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrFixed);
5409 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrDefType);
5410 CPUM_ASSERT_WR_MSR_FN(Ia32Pat);
5411 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterCs);
5412 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterEsp);
5413 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterEip);
5414 CPUM_ASSERT_WR_MSR_FN(Ia32McgStatus);
5415 CPUM_ASSERT_WR_MSR_FN(Ia32McgCtl);
5416 CPUM_ASSERT_WR_MSR_FN(Ia32DebugCtl);
5417 CPUM_ASSERT_WR_MSR_FN(Ia32SmrrPhysBase);
5418 CPUM_ASSERT_WR_MSR_FN(Ia32SmrrPhysMask);
5419 CPUM_ASSERT_WR_MSR_FN(Ia32PlatformDcaCap);
5420 CPUM_ASSERT_WR_MSR_FN(Ia32Dca0Cap);
5421 CPUM_ASSERT_WR_MSR_FN(Ia32PerfEvtSelN);
5422 CPUM_ASSERT_WR_MSR_FN(Ia32PerfStatus);
5423 CPUM_ASSERT_WR_MSR_FN(Ia32PerfCtl);
5424 CPUM_ASSERT_WR_MSR_FN(Ia32FixedCtrN);
5425 CPUM_ASSERT_WR_MSR_FN(Ia32PerfCapabilities);
5426 CPUM_ASSERT_WR_MSR_FN(Ia32FixedCtrCtrl);
5427 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalStatus);
5428 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalCtrl);
5429 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalOvfCtrl);
5430 CPUM_ASSERT_WR_MSR_FN(Ia32PebsEnable);
5431 CPUM_ASSERT_WR_MSR_FN(Ia32ClockModulation);
5432 CPUM_ASSERT_WR_MSR_FN(Ia32ThermInterrupt);
5433 CPUM_ASSERT_WR_MSR_FN(Ia32ThermStatus);
5434 CPUM_ASSERT_WR_MSR_FN(Ia32MiscEnable);
5435 CPUM_ASSERT_WR_MSR_FN(Ia32McCtlStatusAddrMiscN);
5436 CPUM_ASSERT_WR_MSR_FN(Ia32McNCtl2);
5437 CPUM_ASSERT_WR_MSR_FN(Ia32DsArea);
5438 CPUM_ASSERT_WR_MSR_FN(Ia32TscDeadline);
5439 CPUM_ASSERT_WR_MSR_FN(Ia32X2ApicN);
5440 CPUM_ASSERT_WR_MSR_FN(Ia32DebugInterface);
5441
5442 CPUM_ASSERT_WR_MSR_FN(Amd64Efer);
5443 CPUM_ASSERT_WR_MSR_FN(Amd64SyscallTarget);
5444 CPUM_ASSERT_WR_MSR_FN(Amd64LongSyscallTarget);
5445 CPUM_ASSERT_WR_MSR_FN(Amd64CompSyscallTarget);
5446 CPUM_ASSERT_WR_MSR_FN(Amd64SyscallFlagMask);
5447 CPUM_ASSERT_WR_MSR_FN(Amd64FsBase);
5448 CPUM_ASSERT_WR_MSR_FN(Amd64GsBase);
5449 CPUM_ASSERT_WR_MSR_FN(Amd64KernelGsBase);
5450 CPUM_ASSERT_WR_MSR_FN(Amd64TscAux);
5451
5452 CPUM_ASSERT_WR_MSR_FN(IntelEblCrPowerOn);
5453 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcHardPowerOn);
5454 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcSoftPowerOn);
5455 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcFrequencyId);
5456 CPUM_ASSERT_WR_MSR_FN(IntelFlexRatio);
5457 CPUM_ASSERT_WR_MSR_FN(IntelPkgCStConfigControl);
5458 CPUM_ASSERT_WR_MSR_FN(IntelPmgIoCaptureBase);
5459 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchFromToN);
5460 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchFromN);
5461 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchToN);
5462 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchTos);
5463 CPUM_ASSERT_WR_MSR_FN(IntelBblCrCtl);
5464 CPUM_ASSERT_WR_MSR_FN(IntelBblCrCtl3);
5465 CPUM_ASSERT_WR_MSR_FN(IntelI7TemperatureTarget);
5466 CPUM_ASSERT_WR_MSR_FN(IntelI7MsrOffCoreResponseN);
5467 CPUM_ASSERT_WR_MSR_FN(IntelI7MiscPwrMgmt);
5468 CPUM_ASSERT_WR_MSR_FN(IntelP6CrN);
5469 CPUM_ASSERT_WR_MSR_FN(IntelCpuId1FeatureMaskEcdx);
5470 CPUM_ASSERT_WR_MSR_FN(IntelCpuId1FeatureMaskEax);
5471 CPUM_ASSERT_WR_MSR_FN(IntelCpuId80000001FeatureMaskEcdx);
5472 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyAesNiCtl);
5473 CPUM_ASSERT_WR_MSR_FN(IntelI7TurboRatioLimit);
5474 CPUM_ASSERT_WR_MSR_FN(IntelI7LbrSelect);
5475 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyErrorControl);
5476 CPUM_ASSERT_WR_MSR_FN(IntelI7PowerCtl);
5477 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPebsNumAlt);
5478 CPUM_ASSERT_WR_MSR_FN(IntelI7PebsLdLat);
5479 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyVrCurrentConfig);
5480 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyVrMiscConfig);
5481 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPkgCnIrtlN);
5482 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPkgPowerLimit);
5483 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplDramPowerLimit);
5484 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp0PowerLimit);
5485 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp0Policy);
5486 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp1PowerLimit);
5487 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp1Policy);
5488 CPUM_ASSERT_WR_MSR_FN(IntelI7IvyConfigTdpControl);
5489 CPUM_ASSERT_WR_MSR_FN(IntelI7IvyTurboActivationRatio);
5490 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalCtrl);
5491 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalStatus);
5492 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalOvfCtrl);
5493 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfFixedCtrCtrl);
5494 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfFixedCtr);
5495 CPUM_ASSERT_WR_MSR_FN(IntelI7UncArbPerfCtrN);
5496 CPUM_ASSERT_WR_MSR_FN(IntelI7UncArbPerfEvtSelN);
5497 CPUM_ASSERT_WR_MSR_FN(IntelCore2EmttmCrTablesN);
5498 CPUM_ASSERT_WR_MSR_FN(IntelCore2SmmCStMiscInfo);
5499 CPUM_ASSERT_WR_MSR_FN(IntelCore1ExtConfig);
5500 CPUM_ASSERT_WR_MSR_FN(IntelCore1DtsCalControl);
5501 CPUM_ASSERT_WR_MSR_FN(IntelCore2PeciControl);
5502
5503 CPUM_ASSERT_WR_MSR_FN(P6LastIntFromIp);
5504 CPUM_ASSERT_WR_MSR_FN(P6LastIntToIp);
5505
5506 CPUM_ASSERT_WR_MSR_FN(AmdFam15hTscRate);
5507 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLwpCfg);
5508 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLwpCbAddr);
5509 CPUM_ASSERT_WR_MSR_FN(AmdFam10hMc4MiscN);
5510 CPUM_ASSERT_WR_MSR_FN(AmdK8PerfCtlN);
5511 CPUM_ASSERT_WR_MSR_FN(AmdK8PerfCtrN);
5512 CPUM_ASSERT_WR_MSR_FN(AmdK8SysCfg);
5513 CPUM_ASSERT_WR_MSR_FN(AmdK8HwCr);
5514 CPUM_ASSERT_WR_MSR_FN(AmdK8IorrBaseN);
5515 CPUM_ASSERT_WR_MSR_FN(AmdK8IorrMaskN);
5516 CPUM_ASSERT_WR_MSR_FN(AmdK8TopOfMemN);
5517 CPUM_ASSERT_WR_MSR_FN(AmdK8NbCfg1);
5518 CPUM_ASSERT_WR_MSR_FN(AmdK8McXcptRedir);
5519 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuNameN);
5520 CPUM_ASSERT_WR_MSR_FN(AmdK8HwThermalCtrl);
5521 CPUM_ASSERT_WR_MSR_FN(AmdK8SwThermalCtrl);
5522 CPUM_ASSERT_WR_MSR_FN(AmdK8FidVidControl);
5523 CPUM_ASSERT_WR_MSR_FN(AmdK8McCtlMaskN);
5524 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiOnIoTrapN);
5525 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiOnIoTrapCtlSts);
5526 CPUM_ASSERT_WR_MSR_FN(AmdK8IntPendingMessage);
5527 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiTriggerIoCycle);
5528 CPUM_ASSERT_WR_MSR_FN(AmdFam10hMmioCfgBaseAddr);
5529 CPUM_ASSERT_WR_MSR_FN(AmdFam10hTrapCtlMaybe);
5530 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateControl);
5531 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateStatus);
5532 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateN);
5533 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCofVidControl);
5534 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCofVidStatus);
5535 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCStateIoBaseAddr);
5536 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCpuWatchdogTimer);
5537 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmBase);
5538 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmAddr);
5539 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmMask);
5540 CPUM_ASSERT_WR_MSR_FN(AmdK8VmCr);
5541 CPUM_ASSERT_WR_MSR_FN(AmdK8IgnNe);
5542 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmCtl);
5543 CPUM_ASSERT_WR_MSR_FN(AmdK8VmHSavePa);
5544 CPUM_ASSERT_WR_MSR_FN(AmdFam10hVmLockKey);
5545 CPUM_ASSERT_WR_MSR_FN(AmdFam10hSmmLockKey);
5546 CPUM_ASSERT_WR_MSR_FN(AmdFam10hLocalSmiStatus);
5547 CPUM_ASSERT_WR_MSR_FN(AmdFam10hOsVisWrkIdLength);
5548 CPUM_ASSERT_WR_MSR_FN(AmdFam10hOsVisWrkStatus);
5549 CPUM_ASSERT_WR_MSR_FN(AmdFam16hL2IPerfCtlN);
5550 CPUM_ASSERT_WR_MSR_FN(AmdFam16hL2IPerfCtrN);
5551 CPUM_ASSERT_WR_MSR_FN(AmdFam15hNorthbridgePerfCtlN);
5552 CPUM_ASSERT_WR_MSR_FN(AmdFam15hNorthbridgePerfCtrN);
5553 CPUM_ASSERT_WR_MSR_FN(AmdK7MicrocodeCtl);
5554 CPUM_ASSERT_WR_MSR_FN(AmdK7ClusterIdMaybe);
5555 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd07hEbax);
5556 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd06hEcx);
5557 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd01hEdcx);
5558 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlExt01hEdcx);
5559 CPUM_ASSERT_WR_MSR_FN(AmdK8PatchLoader);
5560 CPUM_ASSERT_WR_MSR_FN(AmdK7DebugStatusMaybe);
5561 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTraceBaseMaybe);
5562 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTracePtrMaybe);
5563 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTraceLimitMaybe);
5564 CPUM_ASSERT_WR_MSR_FN(AmdK7HardwareDebugToolCfgMaybe);
5565 CPUM_ASSERT_WR_MSR_FN(AmdK7FastFlushCountMaybe);
5566 CPUM_ASSERT_WR_MSR_FN(AmdK7NodeId);
5567 CPUM_ASSERT_WR_MSR_FN(AmdK7DrXAddrMaskN);
5568 CPUM_ASSERT_WR_MSR_FN(AmdK7Dr0DataMatchMaybe);
5569 CPUM_ASSERT_WR_MSR_FN(AmdK7Dr0DataMaskMaybe);
5570 CPUM_ASSERT_WR_MSR_FN(AmdK7LoadStoreCfg);
5571 CPUM_ASSERT_WR_MSR_FN(AmdK7InstrCacheCfg);
5572 CPUM_ASSERT_WR_MSR_FN(AmdK7DataCacheCfg);
5573 CPUM_ASSERT_WR_MSR_FN(AmdK7BusUnitCfg);
5574 CPUM_ASSERT_WR_MSR_FN(AmdK7DebugCtl2Maybe);
5575 CPUM_ASSERT_WR_MSR_FN(AmdFam15hFpuCfg);
5576 CPUM_ASSERT_WR_MSR_FN(AmdFam15hDecoderCfg);
5577 CPUM_ASSERT_WR_MSR_FN(AmdFam10hBusUnitCfg2);
5578 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg);
5579 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg2);
5580 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg3);
5581 CPUM_ASSERT_WR_MSR_FN(AmdFam15hExecUnitCfg);
5582 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLoadStoreCfg2);
5583 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchCtl);
5584 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchLinAddr);
5585 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchPhysAddr);
5586 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpExecCtl);
5587 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpRip);
5588 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData);
5589 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData2);
5590 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData3);
5591 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsDcLinAddr);
5592 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsDcPhysAddr);
5593 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsCtl);
5594 CPUM_ASSERT_WR_MSR_FN(AmdFam14hIbsBrTarget);
5595
5596 CPUM_ASSERT_WR_MSR_FN(Gim);
5597
5598 return VINF_SUCCESS;
5599}
5600#endif /* VBOX_STRICT && IN_RING3 */
5601
5602
5603/**
5604 * Gets the scalable bus frequency.
5605 *
5606 * The bus frequency is used as a base in several MSRs that gives the CPU and
5607 * other frequency ratios.
5608 *
5609 * @returns Scalable bus frequency in Hz. Will not return CPUM_SBUSFREQ_UNKNOWN.
5610 * @param pVM Pointer to the shared VM structure.
5611 */
5612VMMDECL(uint64_t) CPUMGetGuestScalableBusFrequency(PVM pVM)
5613{
5614 uint64_t uFreq = pVM->cpum.s.GuestInfo.uScalableBusFreq;
5615 if (uFreq == CPUM_SBUSFREQ_UNKNOWN)
5616 uFreq = CPUM_SBUSFREQ_100MHZ;
5617 return uFreq;
5618}
5619
5620
5621#ifdef IN_RING0
5622
5623/**
5624 * Fast way for HM to access the MSR_K8_TSC_AUX register.
5625 *
5626 * @returns The register value.
5627 * @param pVCpu Pointer to the cross context CPU structure for
5628 * the calling EMT.
5629 * @thread EMT(pVCpu)
5630 */
5631VMMR0_INT_DECL(uint64_t) CPUMR0GetGuestTscAux(PVMCPU pVCpu)
5632{
5633 return pVCpu->cpum.s.GuestMsrs.msr.TscAux;
5634}
5635
5636
5637/**
5638 * Fast way for HM to access the MSR_K8_TSC_AUX register.
5639 *
5640 * @param pVCpu Pointer to the cross context CPU structure for
5641 * the calling EMT.
5642 * @param uValue The new value.
5643 * @thread EMT(pVCpu)
5644 */
5645VMMR0_INT_DECL(void) CPUMR0SetGuestTscAux(PVMCPU pVCpu, uint64_t uValue)
5646{
5647 pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
5648}
5649
5650#endif /* IN_RING0 */
5651
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