CPUMAllMsrs.cpp@ 85416

Last change on this file since 85416 was 85183, checked in by vboxsync, 4 years ago
VMM/CPUMAllMsrs.cpp: Workaround for Clang 11 nothrow weirdness. bugref:9794
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1	/* $Id: CPUMAllMsrs.cpp 85183 2020-07-10 13:21:26Z vboxsync $ */
2	/** @file
3	* CPUM - CPU MSR Registers.
4	*/
5
6	/*
7	* Copyright (C) 2013-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include <VBox/vmm/apic.h>
25	#include <VBox/vmm/hm.h>
26	#include <VBox/vmm/hm_vmx.h>
27	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
28	# include <VBox/vmm/iem.h>
29	#endif
30	#include <VBox/vmm/tm.h>
31	#include <VBox/vmm/gim.h>
32	#include "CPUMInternal.h"
33	#include <VBox/vmm/vmcc.h>
34	#include <VBox/err.h>
35
36
37	/*********************************************************************************************************************************
38	* Defined Constants And Macros *
39	*********************************************************************************************************************************/
40	/**
41	* Validates the CPUMMSRRANGE::offCpumCpu value and declares a local variable
42	* pointing to it.
43	*
44	* ASSUMES sizeof(a_Type) is a power of two and that the member is aligned
45	* correctly.
46	*/
47	#define CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(a_pVCpu, a_pRange, a_Type, a_VarName) \
48	AssertMsgReturn( (a_pRange)->offCpumCpu >= 8 \
49	&& (a_pRange)->offCpumCpu < sizeof(CPUMCPU) \
50	&& !((a_pRange)->offCpumCpu & (RT_MIN(sizeof(a_Type), 8) - 1)) \
51	, ("offCpumCpu=%#x %s\n", (a_pRange)->offCpumCpu, (a_pRange)->szName), \
52	VERR_CPUM_MSR_BAD_CPUMCPU_OFFSET); \
53	a_Type a_VarName = (a_Type )((uintptr_t)&(a_pVCpu)->cpum.s + (a_pRange)->offCpumCpu)
54
55
56	/*********************************************************************************************************************************
57	* Structures and Typedefs *
58	*********************************************************************************************************************************/
59
60	/**
61	* Implements reading one or more MSRs.
62	*
63	* @returns VBox status code.
64	* @retval VINF_SUCCESS on success.
65	* @retval VINF_CPUM_R3_MSR_READ if the MSR read could not be serviced in the
66	* current context (raw-mode or ring-0).
67	* @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR).
68	*
69	* @param pVCpu The cross context virtual CPU structure.
70	* @param idMsr The MSR we're reading.
71	* @param pRange The MSR range descriptor.
72	* @param puValue Where to return the value.
73	*/
74	typedef DECLCALLBACKTYPE(VBOXSTRICTRC, FNCPUMRDMSR,(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue));
75	/** Pointer to a RDMSR worker for a specific MSR or range of MSRs. */
76	typedef FNCPUMRDMSR *PFNCPUMRDMSR;
77
78
79	/**
80	* Implements writing one or more MSRs.
81	*
82	* @retval VINF_SUCCESS on success.
83	* @retval VINF_CPUM_R3_MSR_WRITE if the MSR write could not be serviced in the
84	* current context (raw-mode or ring-0).
85	* @retval VERR_CPUM_RAISE_GP_0 on failure.
86	*
87	* @param pVCpu The cross context virtual CPU structure.
88	* @param idMsr The MSR we're writing.
89	* @param pRange The MSR range descriptor.
90	* @param uValue The value to set, ignored bits masked.
91	* @param uRawValue The raw value with the ignored bits not masked.
92	*/
93	typedef DECLCALLBACKTYPE(VBOXSTRICTRC, FNCPUMWRMSR,(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange,
94	uint64_t uValue, uint64_t uRawValue));
95	/** Pointer to a WRMSR worker for a specific MSR or range of MSRs. */
96	typedef FNCPUMWRMSR *PFNCPUMWRMSR;
97
98
99
100	/*
101	* Generic functions.
102	* Generic functions.
103	* Generic functions.
104	*/
105
106
107	/** @callback_method_impl{FNCPUMRDMSR} */
108	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_FixedValue(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
109	{
110	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
111	*puValue = pRange->uValue;
112	return VINF_SUCCESS;
113	}
114
115
116	/** @callback_method_impl{FNCPUMWRMSR} */
117	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IgnoreWrite(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
118	{
119	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
120	Log(("CPUM: Ignoring WRMSR %#x (%s), %#llx\n", idMsr, pRange->szName, uValue));
121	return VINF_SUCCESS;
122	}
123
124
125	/** @callback_method_impl{FNCPUMRDMSR} */
126	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_WriteOnly(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
127	{
128	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(puValue);
129	return VERR_CPUM_RAISE_GP_0;
130	}
131
132
133	/** @callback_method_impl{FNCPUMWRMSR} */
134	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_ReadOnly(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
135	{
136	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
137	Assert(pRange->fWrGpMask == UINT64_MAX);
138	return VERR_CPUM_RAISE_GP_0;
139	}
140
141
142
143
144	/*
145	* IA32
146	* IA32
147	* IA32
148	*/
149
150	/** @callback_method_impl{FNCPUMRDMSR} */
151	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32P5McAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
152	{
153	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
154	puValue = 0; /* @todo implement machine check injection. */
155	return VINF_SUCCESS;
156	}
157
158
159	/** @callback_method_impl{FNCPUMWRMSR} */
160	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32P5McAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
161	{
162	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
163	/** @todo implement machine check injection. */
164	return VINF_SUCCESS;
165	}
166
167
168	/** @callback_method_impl{FNCPUMRDMSR} */
169	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32P5McType(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
170	{
171	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
172	puValue = 0; /* @todo implement machine check injection. */
173	return VINF_SUCCESS;
174	}
175
176
177	/** @callback_method_impl{FNCPUMWRMSR} */
178	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32P5McType(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
179	{
180	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
181	/** @todo implement machine check injection. */
182	return VINF_SUCCESS;
183	}
184
185
186	/** @callback_method_impl{FNCPUMRDMSR} */
187	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32TimestampCounter(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
188	{
189	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
190	*puValue = TMCpuTickGet(pVCpu);
191	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
192	puValue = CPUMApplyNestedGuestTscOffset(pVCpu, puValue);
193	#endif
194	return VINF_SUCCESS;
195	}
196
197
198	/** @callback_method_impl{FNCPUMWRMSR} */
199	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32TimestampCounter(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
200	{
201	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
202	TMCpuTickSet(pVCpu->CTX_SUFF(pVM), pVCpu, uValue);
203	return VINF_SUCCESS;
204	}
205
206
207	/** @callback_method_impl{FNCPUMRDMSR} */
208	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PlatformId(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
209	{
210	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
211	uint64_t uValue = pRange->uValue;
212	if (uValue & 0x1f00)
213	{
214	/* Max allowed bus ratio present. */
215	/** @todo Implement scaled BUS frequency. */
216	}
217
218	*puValue = uValue;
219	return VINF_SUCCESS;
220	}
221
222
223	/** @callback_method_impl{FNCPUMRDMSR} */
224	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ApicBase(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
225	{
226	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
227	return APICGetBaseMsr(pVCpu, puValue);
228	}
229
230
231	/** @callback_method_impl{FNCPUMWRMSR} */
232	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ApicBase(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
233	{
234	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
235	return APICSetBaseMsr(pVCpu, uValue);
236	}
237
238
239	/** @callback_method_impl{FNCPUMRDMSR} */
240	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32FeatureControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
241	{
242	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
243	*puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64FeatCtrl;
244	return VINF_SUCCESS;
245	}
246
247
248	/** @callback_method_impl{FNCPUMWRMSR} */
249	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32FeatureControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
250	{
251	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
252	return VERR_CPUM_RAISE_GP_0;
253	}
254
255
256	/** @callback_method_impl{FNCPUMRDMSR} */
257	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32BiosSignId(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
258	{
259	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
260	/** @todo fake microcode update. */
261	*puValue = pRange->uValue;
262	return VINF_SUCCESS;
263	}
264
265
266	/** @callback_method_impl{FNCPUMWRMSR} */
267	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32BiosSignId(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
268	{
269	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
270	/* Normally, zero is written to Ia32BiosSignId before reading it in order
271	to select the signature instead of the BBL_CR_D3 behaviour. The GP mask
272	of the database entry should take care of most illegal writes for now, so
273	just ignore all writes atm. */
274	return VINF_SUCCESS;
275	}
276
277
278	/** @callback_method_impl{FNCPUMWRMSR} */
279	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32BiosUpdateTrigger(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
280	{
281	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
282
283	/* Microcode updates cannot be loaded in VMX non-root mode. */
284	if (CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.s.Guest))
285	return VINF_SUCCESS;
286
287	/** @todo Fake bios update trigger better. The value is the address to an
288	* update package, I think. We should probably GP if it's invalid. */
289	return VINF_SUCCESS;
290	}
291
292
293	/**
294	* Get MSR_IA32_SMM_MONITOR_CTL value for IEM and cpumMsrRd_Ia32SmmMonitorCtl.
295	*
296	* @returns The MSR_IA32_SMM_MONITOR_CTL value.
297	* @param pVCpu The cross context per CPU structure.
298	*/
299	VMM_INT_DECL(uint64_t) CPUMGetGuestIa32SmmMonitorCtl(PCVMCPU pVCpu)
300	{
301	/* We do not support dual-monitor treatment for SMI and SMM. */
302	/** @todo SMM. */
303	RT_NOREF(pVCpu);
304	return 0;
305	}
306
307
308	/** @callback_method_impl{FNCPUMRDMSR} */
309	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SmmMonitorCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
310	{
311	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
312	*puValue = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
313	return VINF_SUCCESS;
314	}
315
316
317	/** @callback_method_impl{FNCPUMWRMSR} */
318	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SmmMonitorCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
319	{
320	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
321	/** @todo SMM. */
322	return VINF_SUCCESS;
323	}
324
325
326	/** @callback_method_impl{FNCPUMRDMSR} */
327	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PmcN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
328	{
329	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
330	/** @todo check CPUID leaf 0ah. */
331	*puValue = 0;
332	return VINF_SUCCESS;
333	}
334
335
336	/** @callback_method_impl{FNCPUMWRMSR} */
337	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PmcN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
338	{
339	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
340	/** @todo check CPUID leaf 0ah. */
341	return VINF_SUCCESS;
342	}
343
344
345	/** @callback_method_impl{FNCPUMRDMSR} */
346	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MonitorFilterLineSize(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
347	{
348	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
349	/** @todo return 0x1000 if we try emulate mwait 100% correctly. */
350	puValue = 0x40; /* @todo Change to CPU cache line size. */
351	return VINF_SUCCESS;
352	}
353
354
355	/** @callback_method_impl{FNCPUMWRMSR} */
356	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MonitorFilterLineSize(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
357	{
358	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
359	/** @todo should remember writes, though it's supposedly something only a BIOS
360	* would write so, it's not extremely important. */
361	return VINF_SUCCESS;
362	}
363
364	/** @callback_method_impl{FNCPUMRDMSR} */
365	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MPerf(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
366	{
367	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
368	/** @todo Read MPERF: Adjust against previously written MPERF value. Is TSC
369	* what we want? */
370	*puValue = TMCpuTickGet(pVCpu);
371	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
372	puValue = CPUMApplyNestedGuestTscOffset(pVCpu, puValue);
373	#endif
374	return VINF_SUCCESS;
375	}
376
377
378	/** @callback_method_impl{FNCPUMWRMSR} */
379	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MPerf(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
380	{
381	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
382	/** @todo Write MPERF: Calc adjustment. */
383	return VINF_SUCCESS;
384	}
385
386
387	/** @callback_method_impl{FNCPUMRDMSR} */
388	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32APerf(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
389	{
390	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
391	/** @todo Read APERF: Adjust against previously written MPERF value. Is TSC
392	* what we want? */
393	*puValue = TMCpuTickGet(pVCpu);
394	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
395	puValue = CPUMApplyNestedGuestTscOffset(pVCpu, puValue);
396	#endif
397	return VINF_SUCCESS;
398	}
399
400
401	/** @callback_method_impl{FNCPUMWRMSR} */
402	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32APerf(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
403	{
404	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
405	/** @todo Write APERF: Calc adjustment. */
406	return VINF_SUCCESS;
407	}
408
409
410	/**
411	* Get fixed IA32_MTRR_CAP value for NEM and cpumMsrRd_Ia32MtrrCap.
412	*
413	* @returns Fixed IA32_MTRR_CAP value.
414	* @param pVCpu The cross context per CPU structure.
415	*/
416	VMM_INT_DECL(uint64_t) CPUMGetGuestIa32MtrrCap(PCVMCPU pVCpu)
417	{
418	RT_NOREF_PV(pVCpu);
419
420	/* This is currently a bit weird. :-) */
421	uint8_t const cVariableRangeRegs = 0;
422	bool const fSystemManagementRangeRegisters = false;
423	bool const fFixedRangeRegisters = false;
424	bool const fWriteCombiningType = false;
425	return cVariableRangeRegs
426	\| (fFixedRangeRegisters ? RT_BIT_64(8) : 0)
427	\| (fWriteCombiningType ? RT_BIT_64(10) : 0)
428	\| (fSystemManagementRangeRegisters ? RT_BIT_64(11) : 0);
429	}
430
431	/** @callback_method_impl{FNCPUMRDMSR} */
432	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrCap(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
433	{
434	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
435	*puValue = CPUMGetGuestIa32MtrrCap(pVCpu);
436	return VINF_SUCCESS;
437	}
438
439
440	/** @callback_method_impl{FNCPUMRDMSR} */
441	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrPhysBaseN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
442	{
443	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
444	/** @todo Implement variable MTRR storage. */
445	Assert(pRange->uValue == (idMsr - 0x200) / 2);
446	*puValue = 0;
447	return VINF_SUCCESS;
448	}
449
450
451	/** @callback_method_impl{FNCPUMWRMSR} */
452	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrPhysBaseN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
453	{
454	/*
455	* Validate the value.
456	*/
457	Assert(pRange->uValue == (idMsr - 0x200) / 2);
458	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(uRawValue); RT_NOREF_PV(pRange);
459
460	uint8_t uType = uValue & 0xff;
461	if ((uType >= 7) \|\| (uType == 2) \|\| (uType == 3))
462	{
463	Log(("CPUM: Invalid type set writing MTRR PhysBase MSR %#x: %#llx (%#llx)\n", idMsr, uValue, uType));
464	return VERR_CPUM_RAISE_GP_0;
465	}
466
467	uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
468	if (fInvPhysMask & uValue)
469	{
470	Log(("CPUM: Invalid physical address bits set writing MTRR PhysBase MSR %#x: %#llx (%#llx)\n",
471	idMsr, uValue, uValue & fInvPhysMask));
472	return VERR_CPUM_RAISE_GP_0;
473	}
474
475	/*
476	* Store it.
477	*/
478	/** @todo Implement variable MTRR storage. */
479	return VINF_SUCCESS;
480	}
481
482
483	/** @callback_method_impl{FNCPUMRDMSR} */
484	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrPhysMaskN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
485	{
486	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
487	/** @todo Implement variable MTRR storage. */
488	Assert(pRange->uValue == (idMsr - 0x200) / 2);
489	*puValue = 0;
490	return VINF_SUCCESS;
491	}
492
493
494	/** @callback_method_impl{FNCPUMWRMSR} */
495	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrPhysMaskN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
496	{
497	/*
498	* Validate the value.
499	*/
500	Assert(pRange->uValue == (idMsr - 0x200) / 2);
501	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(uRawValue); RT_NOREF_PV(pRange);
502
503	uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
504	if (fInvPhysMask & uValue)
505	{
506	Log(("CPUM: Invalid physical address bits set writing MTRR PhysMask MSR %#x: %#llx (%#llx)\n",
507	idMsr, uValue, uValue & fInvPhysMask));
508	return VERR_CPUM_RAISE_GP_0;
509	}
510
511	/*
512	* Store it.
513	*/
514	/** @todo Implement variable MTRR storage. */
515	return VINF_SUCCESS;
516	}
517
518
519	/** @callback_method_impl{FNCPUMRDMSR} */
520	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrFixed(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
521	{
522	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
523	CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(pVCpu, pRange, uint64_t, puFixedMtrr);
524	puValue = puFixedMtrr;
525	return VINF_SUCCESS;
526	}
527
528
529	/** @callback_method_impl{FNCPUMWRMSR} */
530	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrFixed(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
531	{
532	CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(pVCpu, pRange, uint64_t, puFixedMtrr);
533	RT_NOREF_PV(idMsr); RT_NOREF_PV(uRawValue);
534
535	for (uint32_t cShift = 0; cShift < 63; cShift += 8)
536	{
537	uint8_t uType = (uint8_t)(uValue >> cShift);
538	if ((uType >= 7) \|\| (uType == 2) \|\| (uType == 3))
539	{
540	Log(("CPUM: Invalid MTRR type at %u:%u in fixed range (%#x/%s): %#llx (%#llx)\n",
541	cShift + 7, cShift, idMsr, pRange->szName, uValue, uType));
542	return VERR_CPUM_RAISE_GP_0;
543	}
544	}
545	*puFixedMtrr = uValue;
546	return VINF_SUCCESS;
547	}
548
549
550	/** @callback_method_impl{FNCPUMRDMSR} */
551	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrDefType(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
552	{
553	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
554	*puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType;
555	return VINF_SUCCESS;
556	}
557
558
559	/** @callback_method_impl{FNCPUMWRMSR} */
560	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrDefType(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
561	{
562	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
563
564	uint8_t uType = uValue & 0xff;
565	if ((uType >= 7) \|\| (uType == 2) \|\| (uType == 3))
566	{
567	Log(("CPUM: Invalid MTRR default type value on %s: %#llx (%#llx)\n", pRange->szName, uValue, uType));
568	return VERR_CPUM_RAISE_GP_0;
569	}
570
571	pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType = uValue;
572	return VINF_SUCCESS;
573	}
574
575
576	/** @callback_method_impl{FNCPUMRDMSR} */
577	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32Pat(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
578	{
579	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
580	*puValue = pVCpu->cpum.s.Guest.msrPAT;
581	return VINF_SUCCESS;
582	}
583
584
585	/** @callback_method_impl{FNCPUMWRMSR} */
586	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32Pat(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
587	{
588	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
589	if (CPUMIsPatMsrValid(uValue))
590	{
591	pVCpu->cpum.s.Guest.msrPAT = uValue;
592	return VINF_SUCCESS;
593	}
594	return VERR_CPUM_RAISE_GP_0;
595	}
596
597
598	/** @callback_method_impl{FNCPUMRDMSR} */
599	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SysEnterCs(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
600	{
601	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
602	*puValue = pVCpu->cpum.s.Guest.SysEnter.cs;
603	return VINF_SUCCESS;
604	}
605
606
607	/** @callback_method_impl{FNCPUMWRMSR} */
608	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SysEnterCs(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
609	{
610	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
611
612	/* Note! We used to mask this by 0xffff, but turns out real HW doesn't and
613	there are generally 32-bit working bits backing this register. */
614	pVCpu->cpum.s.Guest.SysEnter.cs = uValue;
615	return VINF_SUCCESS;
616	}
617
618
619	/** @callback_method_impl{FNCPUMRDMSR} */
620	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SysEnterEsp(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
621	{
622	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
623	*puValue = pVCpu->cpum.s.Guest.SysEnter.esp;
624	return VINF_SUCCESS;
625	}
626
627
628	/** @callback_method_impl{FNCPUMWRMSR} */
629	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SysEnterEsp(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
630	{
631	if (X86_IS_CANONICAL(uValue))
632	{
633	pVCpu->cpum.s.Guest.SysEnter.esp = uValue;
634	return VINF_SUCCESS;
635	}
636	Log(("CPUM: IA32_SYSENTER_ESP not canonical! %#llx\n", uValue));
637	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
638	return VERR_CPUM_RAISE_GP_0;
639	}
640
641
642	/** @callback_method_impl{FNCPUMRDMSR} */
643	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SysEnterEip(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
644	{
645	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
646	*puValue = pVCpu->cpum.s.Guest.SysEnter.eip;
647	return VINF_SUCCESS;
648	}
649
650
651	/** @callback_method_impl{FNCPUMWRMSR} */
652	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SysEnterEip(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
653	{
654	if (X86_IS_CANONICAL(uValue))
655	{
656	pVCpu->cpum.s.Guest.SysEnter.eip = uValue;
657	return VINF_SUCCESS;
658	}
659	LogRel(("CPUM: IA32_SYSENTER_EIP not canonical! %#llx\n", uValue));
660	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
661	return VERR_CPUM_RAISE_GP_0;
662	}
663
664
665	/** @callback_method_impl{FNCPUMRDMSR} */
666	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McgCap(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
667	{
668	#if 0 /** @todo implement machine checks. */
669	*puValue = pRange->uValue & (RT_BIT_64(8) \| 0);
670	#else
671	*puValue = 0;
672	#endif
673	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
674	return VINF_SUCCESS;
675	}
676
677
678	/** @callback_method_impl{FNCPUMRDMSR} */
679	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McgStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
680	{
681	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
682	/** @todo implement machine checks. */
683	*puValue = 0;
684	return VINF_SUCCESS;
685	}
686
687
688	/** @callback_method_impl{FNCPUMWRMSR} */
689	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McgStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
690	{
691	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
692	/** @todo implement machine checks. */
693	return VINF_SUCCESS;
694	}
695
696
697	/** @callback_method_impl{FNCPUMRDMSR} */
698	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McgCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
699	{
700	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
701	/** @todo implement machine checks. */
702	*puValue = 0;
703	return VINF_SUCCESS;
704	}
705
706
707	/** @callback_method_impl{FNCPUMWRMSR} */
708	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McgCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
709	{
710	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
711	/** @todo implement machine checks. */
712	return VINF_SUCCESS;
713	}
714
715
716	/** @callback_method_impl{FNCPUMRDMSR} */
717	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32DebugCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
718	{
719	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
720	/** @todo implement IA32_DEBUGCTL. */
721	*puValue = 0;
722	return VINF_SUCCESS;
723	}
724
725
726	/** @callback_method_impl{FNCPUMWRMSR} */
727	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32DebugCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
728	{
729	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
730	/** @todo implement IA32_DEBUGCTL. */
731	return VINF_SUCCESS;
732	}
733
734
735	/** @callback_method_impl{FNCPUMRDMSR} */
736	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SmrrPhysBase(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
737	{
738	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
739	/** @todo implement intel SMM. */
740	*puValue = 0;
741	return VINF_SUCCESS;
742	}
743
744
745	/** @callback_method_impl{FNCPUMWRMSR} */
746	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SmrrPhysBase(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
747	{
748	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
749	/** @todo implement intel SMM. */
750	return VERR_CPUM_RAISE_GP_0;
751	}
752
753
754	/** @callback_method_impl{FNCPUMRDMSR} */
755	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SmrrPhysMask(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
756	{
757	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
758	/** @todo implement intel SMM. */
759	*puValue = 0;
760	return VINF_SUCCESS;
761	}
762
763
764	/** @callback_method_impl{FNCPUMWRMSR} */
765	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SmrrPhysMask(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
766	{
767	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
768	/** @todo implement intel SMM. */
769	return VERR_CPUM_RAISE_GP_0;
770	}
771
772
773	/** @callback_method_impl{FNCPUMRDMSR} */
774	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PlatformDcaCap(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
775	{
776	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
777	/** @todo implement intel direct cache access (DCA)?? */
778	*puValue = 0;
779	return VINF_SUCCESS;
780	}
781
782
783	/** @callback_method_impl{FNCPUMWRMSR} */
784	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PlatformDcaCap(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
785	{
786	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
787	/** @todo implement intel direct cache access (DCA)?? */
788	return VINF_SUCCESS;
789	}
790
791
792	/** @callback_method_impl{FNCPUMRDMSR} */
793	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32CpuDcaCap(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
794	{
795	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
796	/** @todo implement intel direct cache access (DCA)?? */
797	*puValue = 0;
798	return VINF_SUCCESS;
799	}
800
801
802	/** @callback_method_impl{FNCPUMRDMSR} */
803	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32Dca0Cap(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
804	{
805	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
806	/** @todo implement intel direct cache access (DCA)?? */
807	*puValue = 0;
808	return VINF_SUCCESS;
809	}
810
811
812	/** @callback_method_impl{FNCPUMWRMSR} */
813	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32Dca0Cap(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
814	{
815	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
816	/** @todo implement intel direct cache access (DCA)?? */
817	return VINF_SUCCESS;
818	}
819
820
821	/** @callback_method_impl{FNCPUMRDMSR} */
822	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfEvtSelN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
823	{
824	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
825	/** @todo implement IA32_PERFEVTSEL0+. */
826	*puValue = 0;
827	return VINF_SUCCESS;
828	}
829
830
831	/** @callback_method_impl{FNCPUMWRMSR} */
832	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfEvtSelN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
833	{
834	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
835	/** @todo implement IA32_PERFEVTSEL0+. */
836	return VINF_SUCCESS;
837	}
838
839
840	/** @callback_method_impl{FNCPUMRDMSR} */
841	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
842	{
843	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
844	uint64_t uValue = pRange->uValue;
845
846	/* Always provide the max bus ratio for now. XNU expects it. */
847	uValue &= ~((UINT64_C(0x1f) << 40) \| RT_BIT_64(46));
848
849	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
850	uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
851	uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
852	uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
853	if (uTscRatio > 0x1f)
854	uTscRatio = 0x1f;
855	uValue \|= (uint64_t)uTscRatio << 40;
856
857	*puValue = uValue;
858	return VINF_SUCCESS;
859	}
860
861
862	/** @callback_method_impl{FNCPUMWRMSR} */
863	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
864	{
865	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
866	/* Pentium4 allows writing, but all bits are ignored. */
867	return VINF_SUCCESS;
868	}
869
870
871	/** @callback_method_impl{FNCPUMRDMSR} */
872	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
873	{
874	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
875	/** @todo implement IA32_PERFCTL. */
876	*puValue = 0;
877	return VINF_SUCCESS;
878	}
879
880
881	/** @callback_method_impl{FNCPUMWRMSR} */
882	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
883	{
884	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
885	/** @todo implement IA32_PERFCTL. */
886	return VINF_SUCCESS;
887	}
888
889
890	/** @callback_method_impl{FNCPUMRDMSR} */
891	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32FixedCtrN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
892	{
893	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
894	/** @todo implement IA32_FIXED_CTRn (fixed performance counters). */
895	*puValue = 0;
896	return VINF_SUCCESS;
897	}
898
899
900	/** @callback_method_impl{FNCPUMWRMSR} */
901	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32FixedCtrN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
902	{
903	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
904	/** @todo implement IA32_FIXED_CTRn (fixed performance counters). */
905	return VINF_SUCCESS;
906	}
907
908
909	/** @callback_method_impl{FNCPUMRDMSR} */
910	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfCapabilities(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
911	{
912	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
913	/** @todo implement performance counters. */
914	*puValue = 0;
915	return VINF_SUCCESS;
916	}
917
918
919	/** @callback_method_impl{FNCPUMWRMSR} */
920	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfCapabilities(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
921	{
922	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
923	/** @todo implement performance counters. */
924	return VINF_SUCCESS;
925	}
926
927
928	/** @callback_method_impl{FNCPUMRDMSR} */
929	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32FixedCtrCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
930	{
931	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
932	/** @todo implement performance counters. */
933	*puValue = 0;
934	return VINF_SUCCESS;
935	}
936
937
938	/** @callback_method_impl{FNCPUMWRMSR} */
939	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32FixedCtrCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
940	{
941	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
942	/** @todo implement performance counters. */
943	return VINF_SUCCESS;
944	}
945
946
947	/** @callback_method_impl{FNCPUMRDMSR} */
948	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfGlobalStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
949	{
950	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
951	/** @todo implement performance counters. */
952	*puValue = 0;
953	return VINF_SUCCESS;
954	}
955
956
957	/** @callback_method_impl{FNCPUMWRMSR} */
958	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfGlobalStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
959	{
960	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
961	/** @todo implement performance counters. */
962	return VINF_SUCCESS;
963	}
964
965
966	/** @callback_method_impl{FNCPUMRDMSR} */
967	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfGlobalCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
968	{
969	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
970	/** @todo implement performance counters. */
971	*puValue = 0;
972	return VINF_SUCCESS;
973	}
974
975
976	/** @callback_method_impl{FNCPUMWRMSR} */
977	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfGlobalCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
978	{
979	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
980	/** @todo implement performance counters. */
981	return VINF_SUCCESS;
982	}
983
984
985	/** @callback_method_impl{FNCPUMRDMSR} */
986	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfGlobalOvfCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
987	{
988	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
989	/** @todo implement performance counters. */
990	*puValue = 0;
991	return VINF_SUCCESS;
992	}
993
994
995	/** @callback_method_impl{FNCPUMWRMSR} */
996	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfGlobalOvfCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
997	{
998	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
999	/** @todo implement performance counters. */
1000	return VINF_SUCCESS;
1001	}
1002
1003
1004	/** @callback_method_impl{FNCPUMRDMSR} */
1005	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PebsEnable(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1006	{
1007	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1008	/** @todo implement performance counters. */
1009	*puValue = 0;
1010	return VINF_SUCCESS;
1011	}
1012
1013
1014	/** @callback_method_impl{FNCPUMWRMSR} */
1015	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PebsEnable(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1016	{
1017	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1018	/** @todo implement performance counters. */
1019	return VINF_SUCCESS;
1020	}
1021
1022
1023	/** @callback_method_impl{FNCPUMRDMSR} */
1024	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ClockModulation(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1025	{
1026	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1027	/** @todo implement IA32_CLOCK_MODULATION. */
1028	*puValue = 0;
1029	return VINF_SUCCESS;
1030	}
1031
1032
1033	/** @callback_method_impl{FNCPUMWRMSR} */
1034	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ClockModulation(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1035	{
1036	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1037	/** @todo implement IA32_CLOCK_MODULATION. */
1038	return VINF_SUCCESS;
1039	}
1040
1041
1042	/** @callback_method_impl{FNCPUMRDMSR} */
1043	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ThermInterrupt(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1044	{
1045	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1046	/** @todo implement IA32_THERM_INTERRUPT. */
1047	*puValue = 0;
1048	return VINF_SUCCESS;
1049	}
1050
1051
1052	/** @callback_method_impl{FNCPUMWRMSR} */
1053	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ThermInterrupt(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1054	{
1055	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1056	/** @todo implement IA32_THERM_STATUS. */
1057	return VINF_SUCCESS;
1058	}
1059
1060
1061	/** @callback_method_impl{FNCPUMRDMSR} */
1062	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ThermStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1063	{
1064	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1065	/** @todo implement IA32_THERM_STATUS. */
1066	*puValue = 0;
1067	return VINF_SUCCESS;
1068	}
1069
1070
1071	/** @callback_method_impl{FNCPUMWRMSR} */
1072	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ThermStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1073	{
1074	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1075	/** @todo implement IA32_THERM_INTERRUPT. */
1076	return VINF_SUCCESS;
1077	}
1078
1079
1080	/** @callback_method_impl{FNCPUMRDMSR} */
1081	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32Therm2Ctl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1082	{
1083	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1084	/** @todo implement IA32_THERM2_CTL. */
1085	*puValue = 0;
1086	return VINF_SUCCESS;
1087	}
1088
1089
1090	/** @callback_method_impl{FNCPUMWRMSR} */
1091	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32Therm2Ctl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1092	{
1093	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1094	/** @todo implement IA32_THERM2_CTL. */
1095	return VINF_SUCCESS;
1096	}
1097
1098
1099	/** @callback_method_impl{FNCPUMRDMSR} */
1100	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MiscEnable(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1101	{
1102	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1103	*puValue = pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
1104	return VINF_SUCCESS;
1105	}
1106
1107
1108	/** @callback_method_impl{FNCPUMWRMSR} */
1109	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MiscEnable(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1110	{
1111	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1112	#ifdef LOG_ENABLED
1113	uint64_t const uOld = pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
1114	#endif
1115
1116	/* Unsupported bits are generally ignored and stripped by the MSR range
1117	entry that got us here. So, we just need to preserve fixed bits. */
1118	pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = uValue
1119	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
1120	\| MSR_IA32_MISC_ENABLE_BTS_UNAVAIL;
1121
1122	Log(("CPUM: IA32_MISC_ENABLE; old=%#llx written=%#llx => %#llx\n",
1123	uOld, uValue, pVCpu->cpum.s.GuestMsrs.msr.MiscEnable));
1124
1125	/** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
1126	/** @todo Wire up MSR_IA32_MISC_ENABLE_XD_DISABLE. */
1127	return VINF_SUCCESS;
1128	}
1129
1130
1131	/** @callback_method_impl{FNCPUMRDMSR} */
1132	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McCtlStatusAddrMiscN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1133	{
1134	RT_NOREF_PV(pVCpu); RT_NOREF_PV(pRange);
1135
1136	/** @todo Implement machine check exception injection. */
1137	switch (idMsr & 3)
1138	{
1139	case 0:
1140	case 1:
1141	*puValue = 0;
1142	break;
1143
1144	/* The ADDR and MISC registers aren't accessible since the
1145	corresponding STATUS bits are zero. */
1146	case 2:
1147	Log(("CPUM: Reading IA32_MCi_ADDR %#x -> #GP\n", idMsr));
1148	return VERR_CPUM_RAISE_GP_0;
1149	case 3:
1150	Log(("CPUM: Reading IA32_MCi_MISC %#x -> #GP\n", idMsr));
1151	return VERR_CPUM_RAISE_GP_0;
1152	}
1153	return VINF_SUCCESS;
1154	}
1155
1156
1157	/** @callback_method_impl{FNCPUMWRMSR} */
1158	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McCtlStatusAddrMiscN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1159	{
1160	RT_NOREF_PV(pVCpu); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1161	switch (idMsr & 3)
1162	{
1163	case 0:
1164	/* Ignore writes to the CTL register. */
1165	break;
1166
1167	case 1:
1168	/* According to specs, the STATUS register can only be written to
1169	with the value 0. VBoxCpuReport thinks different for a
1170	Pentium M Dothan, but implementing according to specs now. */
1171	if (uValue != 0)
1172	{
1173	Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_STATUS %#x -> #GP\n", uValue, idMsr));
1174	return VERR_CPUM_RAISE_GP_0;
1175	}
1176	break;
1177
1178	/* Specs states that ADDR and MISC can be cleared by writing zeros.
1179	Writing 1s will GP. Need to figure out how this relates to the
1180	ADDRV and MISCV status flags. If writing is independent of those
1181	bits, we need to know whether the CPU really implements them since
1182	that is exposed by writing 0 to them.
1183	Implementing the solution with the fewer GPs for now. */
1184	case 2:
1185	if (uValue != 0)
1186	{
1187	Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_ADDR %#x -> #GP\n", uValue, idMsr));
1188	return VERR_CPUM_RAISE_GP_0;
1189	}
1190	break;
1191	case 3:
1192	if (uValue != 0)
1193	{
1194	Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_MISC %#x -> #GP\n", uValue, idMsr));
1195	return VERR_CPUM_RAISE_GP_0;
1196	}
1197	break;
1198	}
1199	return VINF_SUCCESS;
1200	}
1201
1202
1203	/** @callback_method_impl{FNCPUMRDMSR} */
1204	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McNCtl2(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1205	{
1206	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1207	/** @todo Implement machine check exception injection. */
1208	*puValue = 0;
1209	return VINF_SUCCESS;
1210	}
1211
1212
1213	/** @callback_method_impl{FNCPUMWRMSR} */
1214	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McNCtl2(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1215	{
1216	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1217	/** @todo Implement machine check exception injection. */
1218	return VINF_SUCCESS;
1219	}
1220
1221
1222	/** @callback_method_impl{FNCPUMRDMSR} */
1223	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32DsArea(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1224	{
1225	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1226	/** @todo implement IA32_DS_AREA. */
1227	*puValue = 0;
1228	return VINF_SUCCESS;
1229	}
1230
1231
1232	/** @callback_method_impl{FNCPUMWRMSR} */
1233	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32DsArea(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1234	{
1235	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1236	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1237	return VINF_SUCCESS;
1238	}
1239
1240
1241	/** @callback_method_impl{FNCPUMRDMSR} */
1242	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32TscDeadline(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1243	{
1244	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1245	/** @todo implement TSC deadline timer. */
1246	*puValue = 0;
1247	return VINF_SUCCESS;
1248	}
1249
1250
1251	/** @callback_method_impl{FNCPUMWRMSR} */
1252	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32TscDeadline(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1253	{
1254	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1255	/** @todo implement TSC deadline timer. */
1256	return VINF_SUCCESS;
1257	}
1258
1259
1260	/** @callback_method_impl{FNCPUMRDMSR} */
1261	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32X2ApicN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1262	{
1263	RT_NOREF_PV(pRange);
1264	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1265	if ( CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.s.Guest)
1266	&& CPUMIsGuestVmxProcCtls2Set(&pVCpu->cpum.s.Guest, VMX_PROC_CTLS2_VIRT_X2APIC_MODE))
1267	{
1268	VBOXSTRICTRC rcStrict = IEMExecVmxVirtApicAccessMsr(pVCpu, idMsr, puValue, false /* fWrite */);
1269	if (rcStrict == VINF_VMX_MODIFIES_BEHAVIOR)
1270	return VINF_SUCCESS;
1271	if (rcStrict == VERR_OUT_OF_RANGE)
1272	return VERR_CPUM_RAISE_GP_0;
1273	Assert(rcStrict == VINF_VMX_INTERCEPT_NOT_ACTIVE);
1274	}
1275	#endif
1276	return APICReadMsr(pVCpu, idMsr, puValue);
1277	}
1278
1279
1280	/** @callback_method_impl{FNCPUMWRMSR} */
1281	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32X2ApicN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1282	{
1283	RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1284	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1285	if ( CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.s.Guest)
1286	&& CPUMIsGuestVmxProcCtls2Set(&pVCpu->cpum.s.Guest, VMX_PROC_CTLS2_VIRT_X2APIC_MODE))
1287	{
1288	VBOXSTRICTRC rcStrict = IEMExecVmxVirtApicAccessMsr(pVCpu, idMsr, &uValue, true /* fWrite */);
1289	if (rcStrict == VINF_VMX_MODIFIES_BEHAVIOR)
1290	return VINF_SUCCESS;
1291	if (rcStrict == VERR_OUT_OF_RANGE)
1292	return VERR_CPUM_RAISE_GP_0;
1293	Assert(rcStrict == VINF_VMX_INTERCEPT_NOT_ACTIVE);
1294	}
1295	#endif
1296	return APICWriteMsr(pVCpu, idMsr, uValue);
1297	}
1298
1299
1300	/** @callback_method_impl{FNCPUMRDMSR} */
1301	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32DebugInterface(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1302	{
1303	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1304	/** @todo IA32_DEBUG_INTERFACE (no docs) */
1305	*puValue = 0;
1306	return VINF_SUCCESS;
1307	}
1308
1309
1310	/** @callback_method_impl{FNCPUMWRMSR} */
1311	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32DebugInterface(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1312	{
1313	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1314	/** @todo IA32_DEBUG_INTERFACE (no docs) */
1315	return VINF_SUCCESS;
1316	}
1317
1318
1319	/** @callback_method_impl{FNCPUMRDMSR} */
1320	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxBasic(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1321	{
1322	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1323	*puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Basic;
1324	return VINF_SUCCESS;
1325	}
1326
1327
1328	/** @callback_method_impl{FNCPUMRDMSR} */
1329	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxPinbasedCtls(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1330	{
1331	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1332	*puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.PinCtls.u;
1333	return VINF_SUCCESS;
1334	}
1335
1336	/** @callback_method_impl{FNCPUMRDMSR} */
1337	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxProcbasedCtls(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1338	{
1339	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1340	*puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.ProcCtls.u;
1341	return VINF_SUCCESS;
1342	}
1343
1344
1345	/** @callback_method_impl{FNCPUMRDMSR} */
1346	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxExitCtls(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1347	{
1348	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1349	*puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.ExitCtls.u;
1350	return VINF_SUCCESS;
1351	}
1352
1353
1354	/** @callback_method_impl{FNCPUMRDMSR} */
1355	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxEntryCtls(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1356	{
1357	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1358	*puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.EntryCtls.u;
1359	return VINF_SUCCESS;
1360	}
1361
1362
1363
1364	/** @callback_method_impl{FNCPUMRDMSR} */
1365	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxMisc(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1366	{
1367	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1368	*puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Misc;
1369	return VINF_SUCCESS;
1370	}
1371
1372
1373	/** @callback_method_impl{FNCPUMRDMSR} */
1374	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr0Fixed0(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1375	{
1376	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1377	*puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Cr0Fixed0;
1378	return VINF_SUCCESS;
1379	}
1380
1381
1382	/** @callback_method_impl{FNCPUMRDMSR} */
1383	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr0Fixed1(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1384	{
1385	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1386	*puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Cr0Fixed1;
1387	return VINF_SUCCESS;
1388	}
1389
1390
1391	/** @callback_method_impl{FNCPUMRDMSR} */
1392	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr4Fixed0(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1393	{
1394	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1395	*puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Cr4Fixed0;
1396	return VINF_SUCCESS;
1397	}
1398
1399
1400	/** @callback_method_impl{FNCPUMRDMSR} */
1401	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr4Fixed1(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1402	{
1403	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1404	*puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Cr4Fixed1;
1405	return VINF_SUCCESS;
1406	}
1407
1408
1409	/** @callback_method_impl{FNCPUMRDMSR} */
1410	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxVmcsEnum(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1411	{
1412	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1413	*puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64VmcsEnum;
1414	return VINF_SUCCESS;
1415	}
1416
1417
1418	/** @callback_method_impl{FNCPUMRDMSR} */
1419	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxProcBasedCtls2(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1420	{
1421	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1422	*puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.ProcCtls2.u;
1423	return VINF_SUCCESS;
1424	}
1425
1426
1427	/** @callback_method_impl{FNCPUMRDMSR} */
1428	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxEptVpidCap(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1429	{
1430	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1431	*puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64EptVpidCaps;
1432	return VINF_SUCCESS;
1433	}
1434
1435
1436	/** @callback_method_impl{FNCPUMRDMSR} */
1437	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTruePinbasedCtls(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1438	{
1439	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1440	*puValue = 0;
1441	return VINF_SUCCESS;
1442	}
1443
1444
1445	/** @callback_method_impl{FNCPUMRDMSR} */
1446	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTrueProcbasedCtls(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1447	{
1448	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1449	*puValue = 0;
1450	return VINF_SUCCESS;
1451	}
1452
1453
1454	/** @callback_method_impl{FNCPUMRDMSR} */
1455	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTrueExitCtls(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1456	{
1457	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1458	*puValue = 0;
1459	return VINF_SUCCESS;
1460	}
1461
1462
1463	/** @callback_method_impl{FNCPUMRDMSR} */
1464	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTrueEntryCtls(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1465	{
1466	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1467	*puValue = 0;
1468	return VINF_SUCCESS;
1469	}
1470
1471
1472	/** @callback_method_impl{FNCPUMRDMSR} */
1473	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxVmFunc(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1474	{
1475	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1476	*puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64VmFunc;
1477	return VINF_SUCCESS;
1478	}
1479
1480
1481	/** @callback_method_impl{FNCPUMRDMSR} */
1482	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SpecCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1483	{
1484	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1485	*puValue = pVCpu->cpum.s.GuestMsrs.msr.SpecCtrl;
1486	return VINF_SUCCESS;
1487	}
1488
1489
1490	/** @callback_method_impl{FNCPUMWRMSR} */
1491	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SpecCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1492	{
1493	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1494
1495	/* NB: The STIBP bit can be set even when IBRS is present, regardless of whether STIBP is actually implemented. */
1496	if (uValue & ~(MSR_IA32_SPEC_CTRL_F_IBRS \| MSR_IA32_SPEC_CTRL_F_STIBP))
1497	{
1498	Log(("CPUM: Invalid IA32_SPEC_CTRL bits (trying to write %#llx)\n", uValue));
1499	return VERR_CPUM_RAISE_GP_0;
1500	}
1501
1502	pVCpu->cpum.s.GuestMsrs.msr.SpecCtrl = uValue;
1503	return VINF_SUCCESS;
1504	}
1505
1506
1507	/** @callback_method_impl{FNCPUMWRMSR} */
1508	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PredCmd(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1509	{
1510	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1511	return VINF_SUCCESS;
1512	}
1513
1514
1515	/** @callback_method_impl{FNCPUMRDMSR} */
1516	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ArchCapabilities(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1517	{
1518	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1519	*puValue = pVCpu->cpum.s.GuestMsrs.msr.ArchCaps;
1520	return VINF_SUCCESS;
1521	}
1522
1523
1524	/** @callback_method_impl{FNCPUMWRMSR} */
1525	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32FlushCmd(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1526	{
1527	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1528	if ((uValue & ~MSR_IA32_FLUSH_CMD_F_L1D) == 0)
1529	return VINF_SUCCESS;
1530	Log(("CPUM: Invalid MSR_IA32_FLUSH_CMD_ bits (trying to write %#llx)\n", uValue));
1531	return VERR_CPUM_RAISE_GP_0;
1532	}
1533
1534
1535
1536	/*
1537	* AMD64
1538	* AMD64
1539	* AMD64
1540	*/
1541
1542
1543	/** @callback_method_impl{FNCPUMRDMSR} */
1544	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64Efer(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1545	{
1546	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1547	*puValue = pVCpu->cpum.s.Guest.msrEFER;
1548	return VINF_SUCCESS;
1549	}
1550
1551
1552	/** @callback_method_impl{FNCPUMWRMSR} */
1553	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64Efer(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1554	{
1555	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1556	uint64_t uValidatedEfer;
1557	uint64_t const uOldEfer = pVCpu->cpum.s.Guest.msrEFER;
1558	int rc = CPUMIsGuestEferMsrWriteValid(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.s.Guest.cr0, uOldEfer, uValue, &uValidatedEfer);
1559	if (RT_FAILURE(rc))
1560	return VERR_CPUM_RAISE_GP_0;
1561
1562	CPUMSetGuestEferMsrNoChecks(pVCpu, uOldEfer, uValidatedEfer);
1563	return VINF_SUCCESS;
1564	}
1565
1566
1567	/** @callback_method_impl{FNCPUMRDMSR} */
1568	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64SyscallTarget(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1569	{
1570	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1571	*puValue = pVCpu->cpum.s.Guest.msrSTAR;
1572	return VINF_SUCCESS;
1573	}
1574
1575
1576	/** @callback_method_impl{FNCPUMWRMSR} */
1577	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64SyscallTarget(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1578	{
1579	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1580	pVCpu->cpum.s.Guest.msrSTAR = uValue;
1581	return VINF_SUCCESS;
1582	}
1583
1584
1585	/** @callback_method_impl{FNCPUMRDMSR} */
1586	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64LongSyscallTarget(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1587	{
1588	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1589	*puValue = pVCpu->cpum.s.Guest.msrLSTAR;
1590	return VINF_SUCCESS;
1591	}
1592
1593
1594	/** @callback_method_impl{FNCPUMWRMSR} */
1595	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64LongSyscallTarget(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1596	{
1597	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1598	if (!X86_IS_CANONICAL(uValue))
1599	{
1600	Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
1601	return VERR_CPUM_RAISE_GP_0;
1602	}
1603	pVCpu->cpum.s.Guest.msrLSTAR = uValue;
1604	return VINF_SUCCESS;
1605	}
1606
1607
1608	/** @callback_method_impl{FNCPUMRDMSR} */
1609	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64CompSyscallTarget(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1610	{
1611	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1612	*puValue = pVCpu->cpum.s.Guest.msrCSTAR;
1613	return VINF_SUCCESS;
1614	}
1615
1616
1617	/** @callback_method_impl{FNCPUMWRMSR} */
1618	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64CompSyscallTarget(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1619	{
1620	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1621	if (!X86_IS_CANONICAL(uValue))
1622	{
1623	Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
1624	return VERR_CPUM_RAISE_GP_0;
1625	}
1626	pVCpu->cpum.s.Guest.msrCSTAR = uValue;
1627	return VINF_SUCCESS;
1628	}
1629
1630
1631	/** @callback_method_impl{FNCPUMRDMSR} */
1632	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64SyscallFlagMask(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1633	{
1634	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1635	*puValue = pVCpu->cpum.s.Guest.msrSFMASK;
1636	return VINF_SUCCESS;
1637	}
1638
1639
1640	/** @callback_method_impl{FNCPUMWRMSR} */
1641	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64SyscallFlagMask(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1642	{
1643	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1644	pVCpu->cpum.s.Guest.msrSFMASK = uValue;
1645	return VINF_SUCCESS;
1646	}
1647
1648
1649	/** @callback_method_impl{FNCPUMRDMSR} */
1650	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64FsBase(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1651	{
1652	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1653	*puValue = pVCpu->cpum.s.Guest.fs.u64Base;
1654	return VINF_SUCCESS;
1655	}
1656
1657
1658	/** @callback_method_impl{FNCPUMWRMSR} */
1659	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64FsBase(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1660	{
1661	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1662	pVCpu->cpum.s.Guest.fs.u64Base = uValue;
1663	return VINF_SUCCESS;
1664	}
1665
1666
1667	/** @callback_method_impl{FNCPUMRDMSR} */
1668	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64GsBase(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1669	{
1670	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1671	*puValue = pVCpu->cpum.s.Guest.gs.u64Base;
1672	return VINF_SUCCESS;
1673	}
1674
1675	/** @callback_method_impl{FNCPUMWRMSR} */
1676	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64GsBase(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1677	{
1678	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1679	pVCpu->cpum.s.Guest.gs.u64Base = uValue;
1680	return VINF_SUCCESS;
1681	}
1682
1683
1684
1685	/** @callback_method_impl{FNCPUMRDMSR} */
1686	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64KernelGsBase(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1687	{
1688	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1689	*puValue = pVCpu->cpum.s.Guest.msrKERNELGSBASE;
1690	return VINF_SUCCESS;
1691	}
1692
1693	/** @callback_method_impl{FNCPUMWRMSR} */
1694	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64KernelGsBase(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1695	{
1696	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1697	pVCpu->cpum.s.Guest.msrKERNELGSBASE = uValue;
1698	return VINF_SUCCESS;
1699	}
1700
1701
1702	/** @callback_method_impl{FNCPUMRDMSR} */
1703	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64TscAux(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1704	{
1705	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1706	*puValue = pVCpu->cpum.s.GuestMsrs.msr.TscAux;
1707	return VINF_SUCCESS;
1708	}
1709
1710	/** @callback_method_impl{FNCPUMWRMSR} */
1711	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64TscAux(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1712	{
1713	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1714	pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
1715	return VINF_SUCCESS;
1716	}
1717
1718
1719	/*
1720	* Intel specific
1721	* Intel specific
1722	* Intel specific
1723	*/
1724
1725	/** @callback_method_impl{FNCPUMRDMSR} */
1726	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelEblCrPowerOn(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1727	{
1728	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1729	/** @todo recalc clock frequency ratio? */
1730	*puValue = pRange->uValue;
1731	return VINF_SUCCESS;
1732	}
1733
1734
1735	/** @callback_method_impl{FNCPUMWRMSR} */
1736	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelEblCrPowerOn(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1737	{
1738	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1739	/** @todo Write EBL_CR_POWERON: Remember written bits. */
1740	return VINF_SUCCESS;
1741	}
1742
1743
1744	/** @callback_method_impl{FNCPUMRDMSR} */
1745	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7CoreThreadCount(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1746	{
1747	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1748
1749	/* Note! According to cpuid_set_info in XNU (10.7.0), Westmere CPU only
1750	have a 4-bit core count. */
1751	uint16_t cCores = pVCpu->CTX_SUFF(pVM)->cCpus;
1752	uint16_t cThreads = cCores; /** @todo hyper-threading. */
1753	*puValue = RT_MAKE_U32(cThreads, cCores);
1754	return VINF_SUCCESS;
1755	}
1756
1757
1758	/** @callback_method_impl{FNCPUMRDMSR} */
1759	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP4EbcHardPowerOn(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1760	{
1761	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1762	/** @todo P4 hard power on config */
1763	*puValue = pRange->uValue;
1764	return VINF_SUCCESS;
1765	}
1766
1767
1768	/** @callback_method_impl{FNCPUMWRMSR} */
1769	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP4EbcHardPowerOn(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1770	{
1771	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1772	/** @todo P4 hard power on config */
1773	return VINF_SUCCESS;
1774	}
1775
1776
1777	/** @callback_method_impl{FNCPUMRDMSR} */
1778	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP4EbcSoftPowerOn(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1779	{
1780	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1781	/** @todo P4 soft power on config */
1782	*puValue = pRange->uValue;
1783	return VINF_SUCCESS;
1784	}
1785
1786
1787	/** @callback_method_impl{FNCPUMWRMSR} */
1788	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP4EbcSoftPowerOn(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1789	{
1790	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1791	/** @todo P4 soft power on config */
1792	return VINF_SUCCESS;
1793	}
1794
1795
1796	/** @callback_method_impl{FNCPUMRDMSR} */
1797	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP4EbcFrequencyId(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1798	{
1799	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1800
1801	uint64_t uValue;
1802	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1803	uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
1804	if (pVM->cpum.s.GuestFeatures.uModel >= 2)
1805	{
1806	if (uScalableBusHz <= CPUM_SBUSFREQ_100MHZ && pVM->cpum.s.GuestFeatures.uModel <= 2)
1807	{
1808	uScalableBusHz = CPUM_SBUSFREQ_100MHZ;
1809	uValue = 0;
1810	}
1811	else if (uScalableBusHz <= CPUM_SBUSFREQ_133MHZ)
1812	{
1813	uScalableBusHz = CPUM_SBUSFREQ_133MHZ;
1814	uValue = 1;
1815	}
1816	else if (uScalableBusHz <= CPUM_SBUSFREQ_167MHZ)
1817	{
1818	uScalableBusHz = CPUM_SBUSFREQ_167MHZ;
1819	uValue = 3;
1820	}
1821	else if (uScalableBusHz <= CPUM_SBUSFREQ_200MHZ)
1822	{
1823	uScalableBusHz = CPUM_SBUSFREQ_200MHZ;
1824	uValue = 2;
1825	}
1826	else if (uScalableBusHz <= CPUM_SBUSFREQ_267MHZ && pVM->cpum.s.GuestFeatures.uModel > 2)
1827	{
1828	uScalableBusHz = CPUM_SBUSFREQ_267MHZ;
1829	uValue = 0;
1830	}
1831	else
1832	{
1833	uScalableBusHz = CPUM_SBUSFREQ_333MHZ;
1834	uValue = 6;
1835	}
1836	uValue <<= 16;
1837
1838	uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
1839	uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
1840	uValue \|= (uint32_t)uTscRatio << 24;
1841
1842	uValue \|= pRange->uValue & ~UINT64_C(0xff0f0000);
1843	}
1844	else
1845	{
1846	/* Probably more stuff here, but intel doesn't want to tell us. */
1847	uValue = pRange->uValue;
1848	uValue &= ~(RT_BIT_64(21) \| RT_BIT_64(22) \| RT_BIT_64(23)); /* 100 MHz is only documented value */
1849	}
1850
1851	*puValue = uValue;
1852	return VINF_SUCCESS;
1853	}
1854
1855
1856	/** @callback_method_impl{FNCPUMWRMSR} */
1857	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP4EbcFrequencyId(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1858	{
1859	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1860	/** @todo P4 bus frequency config */
1861	return VINF_SUCCESS;
1862	}
1863
1864
1865	/** @callback_method_impl{FNCPUMRDMSR} */
1866	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP6FsbFrequency(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1867	{
1868	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1869
1870	/* Convert the scalable bus frequency to the encoding in the intel manual (for core+). */
1871	uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVCpu->CTX_SUFF(pVM));
1872	if (uScalableBusHz <= CPUM_SBUSFREQ_100MHZ)
1873	*puValue = 5;
1874	else if (uScalableBusHz <= CPUM_SBUSFREQ_133MHZ)
1875	*puValue = 1;
1876	else if (uScalableBusHz <= CPUM_SBUSFREQ_167MHZ)
1877	*puValue = 3;
1878	else if (uScalableBusHz <= CPUM_SBUSFREQ_200MHZ)
1879	*puValue = 2;
1880	else if (uScalableBusHz <= CPUM_SBUSFREQ_267MHZ)
1881	*puValue = 0;
1882	else if (uScalableBusHz <= CPUM_SBUSFREQ_333MHZ)
1883	*puValue = 4;
1884	else /if (uScalableBusHz <= CPUM_SBUSFREQ_400MHZ)/
1885	*puValue = 6;
1886
1887	*puValue \|= pRange->uValue & ~UINT64_C(0x7);
1888
1889	return VINF_SUCCESS;
1890	}
1891
1892
1893	/** @callback_method_impl{FNCPUMRDMSR} */
1894	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelPlatformInfo(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1895	{
1896	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1897
1898	/* Just indicate a fixed TSC, no turbo boost, no programmable anything. */
1899	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1900	uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
1901	uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
1902	uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
1903	uint64_t uValue = ((uint32_t)uTscRatio << 8) /* TSC invariant frequency. */
1904	\| ((uint64_t)uTscRatio << 40); /* The max turbo frequency. */
1905
1906	/* Ivy bridge has a minimum operating ratio as well. */
1907	if (true) /** @todo detect sandy bridge. */
1908	uValue \|= (uint64_t)uTscRatio << 48;
1909
1910	*puValue = uValue;
1911	return VINF_SUCCESS;
1912	}
1913
1914
1915	/** @callback_method_impl{FNCPUMRDMSR} */
1916	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelFlexRatio(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1917	{
1918	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1919
1920	uint64_t uValue = pRange->uValue & ~UINT64_C(0x1ff00);
1921
1922	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1923	uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
1924	uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
1925	uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
1926	uValue \|= (uint32_t)uTscRatio << 8;
1927
1928	*puValue = uValue;
1929	return VINF_SUCCESS;
1930	}
1931
1932
1933	/** @callback_method_impl{FNCPUMWRMSR} */
1934	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelFlexRatio(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1935	{
1936	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1937	/** @todo implement writing MSR_FLEX_RATIO. */
1938	return VINF_SUCCESS;
1939	}
1940
1941
1942	/** @callback_method_impl{FNCPUMRDMSR} */
1943	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelPkgCStConfigControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1944	{
1945	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1946	*puValue = pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl;
1947	return VINF_SUCCESS;
1948	}
1949
1950
1951	/** @callback_method_impl{FNCPUMWRMSR} */
1952	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelPkgCStConfigControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1953	{
1954	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1955
1956	if (pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl & RT_BIT_64(15))
1957	{
1958	Log(("CPUM: WRMSR %#x (%s), %#llx: Write protected -> #GP\n", idMsr, pRange->szName, uValue));
1959	return VERR_CPUM_RAISE_GP_0;
1960	}
1961	#if 0 /** @todo check what real (old) hardware does. */
1962	if ((uValue & 7) >= 5)
1963	{
1964	Log(("CPUM: WRMSR %#x (%s), %#llx: Invalid limit (%d) -> #GP\n", idMsr, pRange->szName, uValue, (uint32_t)(uValue & 7)));
1965	return VERR_CPUM_RAISE_GP_0;
1966	}
1967	#endif
1968	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = uValue;
1969	return VINF_SUCCESS;
1970	}
1971
1972
1973	/** @callback_method_impl{FNCPUMRDMSR} */
1974	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelPmgIoCaptureBase(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1975	{
1976	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1977	/** @todo implement I/O mwait wakeup. */
1978	*puValue = 0;
1979	return VINF_SUCCESS;
1980	}
1981
1982
1983	/** @callback_method_impl{FNCPUMWRMSR} */
1984	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelPmgIoCaptureBase(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1985	{
1986	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1987	/** @todo implement I/O mwait wakeup. */
1988	return VINF_SUCCESS;
1989	}
1990
1991
1992	/** @callback_method_impl{FNCPUMRDMSR} */
1993	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchFromToN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1994	{
1995	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1996	/** @todo implement last branch records. */
1997	*puValue = 0;
1998	return VINF_SUCCESS;
1999	}
2000
2001
2002	/** @callback_method_impl{FNCPUMWRMSR} */
2003	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchFromToN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2004	{
2005	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2006	/** @todo implement last branch records. */
2007	return VINF_SUCCESS;
2008	}
2009
2010
2011	/** @callback_method_impl{FNCPUMRDMSR} */
2012	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchFromN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2013	{
2014	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2015	/** @todo implement last branch records. */
2016	*puValue = 0;
2017	return VINF_SUCCESS;
2018	}
2019
2020
2021	/** @callback_method_impl{FNCPUMWRMSR} */
2022	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchFromN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2023	{
2024	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
2025	/** @todo implement last branch records. */
2026	/** @todo Probing indicates that bit 63 is settable on SandyBridge, at least
2027	* if the rest of the bits are zero. Automatic sign extending?
2028	* Investigate! */
2029	if (!X86_IS_CANONICAL(uValue))
2030	{
2031	Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
2032	return VERR_CPUM_RAISE_GP_0;
2033	}
2034	return VINF_SUCCESS;
2035	}
2036
2037
2038	/** @callback_method_impl{FNCPUMRDMSR} */
2039	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchToN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2040	{
2041	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2042	/** @todo implement last branch records. */
2043	*puValue = 0;
2044	return VINF_SUCCESS;
2045	}
2046
2047
2048	/** @callback_method_impl{FNCPUMWRMSR} */
2049	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchToN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2050	{
2051	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2052	/** @todo implement last branch records. */
2053	/** @todo Probing indicates that bit 63 is settable on SandyBridge, at least
2054	* if the rest of the bits are zero. Automatic sign extending?
2055	* Investigate! */
2056	if (!X86_IS_CANONICAL(uValue))
2057	{
2058	Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
2059	return VERR_CPUM_RAISE_GP_0;
2060	}
2061	return VINF_SUCCESS;
2062	}
2063
2064
2065	/** @callback_method_impl{FNCPUMRDMSR} */
2066	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchTos(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2067	{
2068	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2069	/** @todo implement last branch records. */
2070	*puValue = 0;
2071	return VINF_SUCCESS;
2072	}
2073
2074
2075	/** @callback_method_impl{FNCPUMWRMSR} */
2076	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchTos(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2077	{
2078	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2079	/** @todo implement last branch records. */
2080	return VINF_SUCCESS;
2081	}
2082
2083
2084	/** @callback_method_impl{FNCPUMRDMSR} */
2085	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelBblCrCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2086	{
2087	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2088	*puValue = pRange->uValue;
2089	return VINF_SUCCESS;
2090	}
2091
2092
2093	/** @callback_method_impl{FNCPUMWRMSR} */
2094	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelBblCrCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2095	{
2096	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2097	return VINF_SUCCESS;
2098	}
2099
2100
2101	/** @callback_method_impl{FNCPUMRDMSR} */
2102	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelBblCrCtl3(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2103	{
2104	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2105	*puValue = pRange->uValue;
2106	return VINF_SUCCESS;
2107	}
2108
2109
2110	/** @callback_method_impl{FNCPUMWRMSR} */
2111	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelBblCrCtl3(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2112	{
2113	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2114	return VINF_SUCCESS;
2115	}
2116
2117
2118	/** @callback_method_impl{FNCPUMRDMSR} */
2119	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7TemperatureTarget(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2120	{
2121	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2122	*puValue = pRange->uValue;
2123	return VINF_SUCCESS;
2124	}
2125
2126
2127	/** @callback_method_impl{FNCPUMWRMSR} */
2128	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7TemperatureTarget(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2129	{
2130	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2131	return VINF_SUCCESS;
2132	}
2133
2134
2135	/** @callback_method_impl{FNCPUMRDMSR} */
2136	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7MsrOffCoreResponseN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2137	{
2138	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2139	/** @todo machine check. */
2140	*puValue = pRange->uValue;
2141	return VINF_SUCCESS;
2142	}
2143
2144
2145	/** @callback_method_impl{FNCPUMWRMSR} */
2146	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7MsrOffCoreResponseN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2147	{
2148	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2149	/** @todo machine check. */
2150	return VINF_SUCCESS;
2151	}
2152
2153
2154	/** @callback_method_impl{FNCPUMRDMSR} */
2155	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7MiscPwrMgmt(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2156	{
2157	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2158	*puValue = 0;
2159	return VINF_SUCCESS;
2160	}
2161
2162
2163	/** @callback_method_impl{FNCPUMWRMSR} */
2164	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7MiscPwrMgmt(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2165	{
2166	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2167	return VINF_SUCCESS;
2168	}
2169
2170
2171	/** @callback_method_impl{FNCPUMRDMSR} */
2172	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP6CrN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2173	{
2174	RT_NOREF_PV(idMsr);
2175	int rc = CPUMGetGuestCRx(pVCpu, pRange->uValue, puValue);
2176	AssertRC(rc);
2177	return VINF_SUCCESS;
2178	}
2179
2180
2181	/** @callback_method_impl{FNCPUMWRMSR} */
2182	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP6CrN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2183	{
2184	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2185	/* This CRx interface differs from the MOV CRx, GReg interface in that
2186	#GP(0) isn't raised if unsupported bits are written to. Instead they
2187	are simply ignored and masked off. (Pentium M Dothan) */
2188	/** @todo Implement MSR_P6_CRx writing. Too much effort for very little, if
2189	* any, gain. */
2190	return VINF_SUCCESS;
2191	}
2192
2193
2194	/** @callback_method_impl{FNCPUMRDMSR} */
2195	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCpuId1FeatureMaskEcdx(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2196	{
2197	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2198	/** @todo implement CPUID masking. */
2199	*puValue = UINT64_MAX;
2200	return VINF_SUCCESS;
2201	}
2202
2203
2204	/** @callback_method_impl{FNCPUMWRMSR} */
2205	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCpuId1FeatureMaskEcdx(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2206	{
2207	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2208	/** @todo implement CPUID masking. */
2209	return VINF_SUCCESS;
2210	}
2211
2212
2213	/** @callback_method_impl{FNCPUMRDMSR} */
2214	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCpuId1FeatureMaskEax(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2215	{
2216	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2217	/** @todo implement CPUID masking. */
2218	*puValue = 0;
2219	return VINF_SUCCESS;
2220	}
2221
2222
2223	/** @callback_method_impl{FNCPUMWRMSR} */
2224	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCpuId1FeatureMaskEax(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2225	{
2226	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2227	/** @todo implement CPUID masking. */
2228	return VINF_SUCCESS;
2229	}
2230
2231
2232
2233	/** @callback_method_impl{FNCPUMRDMSR} */
2234	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCpuId80000001FeatureMaskEcdx(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2235	{
2236	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2237	/** @todo implement CPUID masking. */
2238	*puValue = UINT64_MAX;
2239	return VINF_SUCCESS;
2240	}
2241
2242
2243	/** @callback_method_impl{FNCPUMWRMSR} */
2244	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCpuId80000001FeatureMaskEcdx(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2245	{
2246	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2247	/** @todo implement CPUID masking. */
2248	return VINF_SUCCESS;
2249	}
2250
2251
2252
2253	/** @callback_method_impl{FNCPUMRDMSR} */
2254	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyAesNiCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2255	{
2256	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2257	/** @todo implement AES-NI. */
2258	puValue = 3; / Bit 0 is lock bit, bit 1 disables AES-NI. That's what they say. */
2259	return VINF_SUCCESS;
2260	}
2261
2262
2263	/** @callback_method_impl{FNCPUMWRMSR} */
2264	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyAesNiCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2265	{
2266	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2267	/** @todo implement AES-NI. */
2268	return VERR_CPUM_RAISE_GP_0;
2269	}
2270
2271
2272	/** @callback_method_impl{FNCPUMRDMSR} */
2273	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7TurboRatioLimit(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2274	{
2275	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2276	/** @todo implement intel C states. */
2277	*puValue = pRange->uValue;
2278	return VINF_SUCCESS;
2279	}
2280
2281
2282	/** @callback_method_impl{FNCPUMWRMSR} */
2283	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7TurboRatioLimit(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2284	{
2285	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2286	/** @todo implement intel C states. */
2287	return VINF_SUCCESS;
2288	}
2289
2290
2291	/** @callback_method_impl{FNCPUMRDMSR} */
2292	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7LbrSelect(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2293	{
2294	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2295	/** @todo implement last-branch-records. */
2296	*puValue = 0;
2297	return VINF_SUCCESS;
2298	}
2299
2300
2301	/** @callback_method_impl{FNCPUMWRMSR} */
2302	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7LbrSelect(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2303	{
2304	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2305	/** @todo implement last-branch-records. */
2306	return VINF_SUCCESS;
2307	}
2308
2309
2310	/** @callback_method_impl{FNCPUMRDMSR} */
2311	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyErrorControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2312	{
2313	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2314	/** @todo implement memory error injection (MSR_ERROR_CONTROL). */
2315	*puValue = 0;
2316	return VINF_SUCCESS;
2317	}
2318
2319
2320	/** @callback_method_impl{FNCPUMWRMSR} */
2321	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyErrorControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2322	{
2323	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2324	/** @todo implement memory error injection (MSR_ERROR_CONTROL). */
2325	return VINF_SUCCESS;
2326	}
2327
2328
2329	/** @callback_method_impl{FNCPUMRDMSR} */
2330	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7VirtualLegacyWireCap(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2331	{
2332	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2333	/** @todo implement memory VLW? */
2334	*puValue = pRange->uValue;
2335	/* Note: A20M is known to be bit 1 as this was disclosed in spec update
2336	AAJ49/AAK51/????, which documents the inversion of this bit. The
2337	Sandy bridge CPU here has value 0x74, so it probably doesn't have a BIOS
2338	that correct things. Some guesses at the other bits:
2339	bit 2 = INTR
2340	bit 4 = SMI
2341	bit 5 = INIT
2342	bit 6 = NMI */
2343	return VINF_SUCCESS;
2344	}
2345
2346
2347	/** @callback_method_impl{FNCPUMRDMSR} */
2348	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7PowerCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2349	{
2350	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2351	/** @todo intel power management */
2352	*puValue = 0;
2353	return VINF_SUCCESS;
2354	}
2355
2356
2357	/** @callback_method_impl{FNCPUMWRMSR} */
2358	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7PowerCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2359	{
2360	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2361	/** @todo intel power management */
2362	return VINF_SUCCESS;
2363	}
2364
2365
2366	/** @callback_method_impl{FNCPUMRDMSR} */
2367	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyPebsNumAlt(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2368	{
2369	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2370	/** @todo intel performance counters. */
2371	*puValue = 0;
2372	return VINF_SUCCESS;
2373	}
2374
2375
2376	/** @callback_method_impl{FNCPUMWRMSR} */
2377	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyPebsNumAlt(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2378	{
2379	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2380	/** @todo intel performance counters. */
2381	return VINF_SUCCESS;
2382	}
2383
2384
2385	/** @callback_method_impl{FNCPUMRDMSR} */
2386	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7PebsLdLat(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2387	{
2388	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2389	/** @todo intel performance counters. */
2390	*puValue = 0;
2391	return VINF_SUCCESS;
2392	}
2393
2394
2395	/** @callback_method_impl{FNCPUMWRMSR} */
2396	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7PebsLdLat(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2397	{
2398	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2399	/** @todo intel performance counters. */
2400	return VINF_SUCCESS;
2401	}
2402
2403
2404	/** @callback_method_impl{FNCPUMRDMSR} */
2405	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7PkgCnResidencyN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2406	{
2407	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2408	/** @todo intel power management. */
2409	*puValue = 0;
2410	return VINF_SUCCESS;
2411	}
2412
2413
2414	/** @callback_method_impl{FNCPUMRDMSR} */
2415	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7CoreCnResidencyN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2416	{
2417	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2418	/** @todo intel power management. */
2419	*puValue = 0;
2420	return VINF_SUCCESS;
2421	}
2422
2423
2424	/** @callback_method_impl{FNCPUMRDMSR} */
2425	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyVrCurrentConfig(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2426	{
2427	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2428	/** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2429	*puValue = 0;
2430	return VINF_SUCCESS;
2431	}
2432
2433
2434	/** @callback_method_impl{FNCPUMWRMSR} */
2435	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyVrCurrentConfig(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2436	{
2437	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2438	/** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2439	return VINF_SUCCESS;
2440	}
2441
2442
2443	/** @callback_method_impl{FNCPUMRDMSR} */
2444	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyVrMiscConfig(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2445	{
2446	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2447	/** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2448	*puValue = 0;
2449	return VINF_SUCCESS;
2450	}
2451
2452
2453	/** @callback_method_impl{FNCPUMWRMSR} */
2454	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyVrMiscConfig(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2455	{
2456	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2457	/** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2458	return VINF_SUCCESS;
2459	}
2460
2461
2462	/** @callback_method_impl{FNCPUMRDMSR} */
2463	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyRaplPowerUnit(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2464	{
2465	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2466	/** @todo intel RAPL. */
2467	*puValue = pRange->uValue;
2468	return VINF_SUCCESS;
2469	}
2470
2471
2472	/** @callback_method_impl{FNCPUMWRMSR} */
2473	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyRaplPowerUnit(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2474	{
2475	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2476	/* Note! This is documented as read only and except for a Silvermont sample has
2477	always been classified as read only. This is just here to make it compile. */
2478	return VINF_SUCCESS;
2479	}
2480
2481
2482	/** @callback_method_impl{FNCPUMRDMSR} */
2483	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyPkgCnIrtlN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2484	{
2485	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2486	/** @todo intel power management. */
2487	*puValue = 0;
2488	return VINF_SUCCESS;
2489	}
2490
2491
2492	/** @callback_method_impl{FNCPUMWRMSR} */
2493	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyPkgCnIrtlN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2494	{
2495	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2496	/** @todo intel power management. */
2497	return VINF_SUCCESS;
2498	}
2499
2500
2501	/** @callback_method_impl{FNCPUMRDMSR} */
2502	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyPkgC2Residency(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2503	{
2504	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2505	/** @todo intel power management. */
2506	*puValue = 0;
2507	return VINF_SUCCESS;
2508	}
2509
2510
2511	/** @callback_method_impl{FNCPUMWRMSR} */
2512	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyPkgC2Residency(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2513	{
2514	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2515	/* Note! This is documented as read only and except for a Silvermont sample has
2516	always been classified as read only. This is just here to make it compile. */
2517	return VINF_SUCCESS;
2518	}
2519
2520
2521	/** @callback_method_impl{FNCPUMRDMSR} */
2522	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgPowerLimit(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2523	{
2524	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2525	/** @todo intel RAPL. */
2526	*puValue = 0;
2527	return VINF_SUCCESS;
2528	}
2529
2530
2531	/** @callback_method_impl{FNCPUMWRMSR} */
2532	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPkgPowerLimit(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2533	{
2534	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2535	/** @todo intel RAPL. */
2536	return VINF_SUCCESS;
2537	}
2538
2539
2540	/** @callback_method_impl{FNCPUMRDMSR} */
2541	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgEnergyStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2542	{
2543	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2544	/** @todo intel power management. */
2545	*puValue = 0;
2546	return VINF_SUCCESS;
2547	}
2548
2549
2550	/** @callback_method_impl{FNCPUMRDMSR} */
2551	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgPerfStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2552	{
2553	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2554	/** @todo intel power management. */
2555	*puValue = 0;
2556	return VINF_SUCCESS;
2557	}
2558
2559
2560	/** @callback_method_impl{FNCPUMRDMSR} */
2561	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgPowerInfo(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2562	{
2563	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2564	/** @todo intel power management. */
2565	*puValue = 0;
2566	return VINF_SUCCESS;
2567	}
2568
2569
2570	/** @callback_method_impl{FNCPUMRDMSR} */
2571	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramPowerLimit(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2572	{
2573	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2574	/** @todo intel RAPL. */
2575	*puValue = 0;
2576	return VINF_SUCCESS;
2577	}
2578
2579
2580	/** @callback_method_impl{FNCPUMWRMSR} */
2581	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplDramPowerLimit(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2582	{
2583	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2584	/** @todo intel RAPL. */
2585	return VINF_SUCCESS;
2586	}
2587
2588
2589	/** @callback_method_impl{FNCPUMRDMSR} */
2590	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramEnergyStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2591	{
2592	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2593	/** @todo intel power management. */
2594	*puValue = 0;
2595	return VINF_SUCCESS;
2596	}
2597
2598
2599	/** @callback_method_impl{FNCPUMRDMSR} */
2600	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramPerfStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2601	{
2602	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2603	/** @todo intel power management. */
2604	*puValue = 0;
2605	return VINF_SUCCESS;
2606	}
2607
2608
2609	/** @callback_method_impl{FNCPUMRDMSR} */
2610	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramPowerInfo(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2611	{
2612	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2613	/** @todo intel power management. */
2614	*puValue = 0;
2615	return VINF_SUCCESS;
2616	}
2617
2618
2619	/** @callback_method_impl{FNCPUMRDMSR} */
2620	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0PowerLimit(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2621	{
2622	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2623	/** @todo intel RAPL. */
2624	*puValue = 0;
2625	return VINF_SUCCESS;
2626	}
2627
2628
2629	/** @callback_method_impl{FNCPUMWRMSR} */
2630	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp0PowerLimit(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2631	{
2632	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2633	/** @todo intel RAPL. */
2634	return VINF_SUCCESS;
2635	}
2636
2637
2638	/** @callback_method_impl{FNCPUMRDMSR} */
2639	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0EnergyStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2640	{
2641	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2642	/** @todo intel power management. */
2643	*puValue = 0;
2644	return VINF_SUCCESS;
2645	}
2646
2647
2648	/** @callback_method_impl{FNCPUMRDMSR} */
2649	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0Policy(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2650	{
2651	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2652	/** @todo intel RAPL. */
2653	*puValue = 0;
2654	return VINF_SUCCESS;
2655	}
2656
2657
2658	/** @callback_method_impl{FNCPUMWRMSR} */
2659	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp0Policy(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2660	{
2661	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2662	/** @todo intel RAPL. */
2663	return VINF_SUCCESS;
2664	}
2665
2666
2667	/** @callback_method_impl{FNCPUMRDMSR} */
2668	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0PerfStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2669	{
2670	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2671	/** @todo intel power management. */
2672	*puValue = 0;
2673	return VINF_SUCCESS;
2674	}
2675
2676
2677	/** @callback_method_impl{FNCPUMRDMSR} */
2678	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp1PowerLimit(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2679	{
2680	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2681	/** @todo intel RAPL. */
2682	*puValue = 0;
2683	return VINF_SUCCESS;
2684	}
2685
2686
2687	/** @callback_method_impl{FNCPUMWRMSR} */
2688	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp1PowerLimit(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2689	{
2690	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2691	/** @todo intel RAPL. */
2692	return VINF_SUCCESS;
2693	}
2694
2695
2696	/** @callback_method_impl{FNCPUMRDMSR} */
2697	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp1EnergyStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2698	{
2699	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2700	/** @todo intel power management. */
2701	*puValue = 0;
2702	return VINF_SUCCESS;
2703	}
2704
2705
2706	/** @callback_method_impl{FNCPUMRDMSR} */
2707	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp1Policy(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2708	{
2709	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2710	/** @todo intel RAPL. */
2711	*puValue = 0;
2712	return VINF_SUCCESS;
2713	}
2714
2715
2716	/** @callback_method_impl{FNCPUMWRMSR} */
2717	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp1Policy(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2718	{
2719	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2720	/** @todo intel RAPL. */
2721	return VINF_SUCCESS;
2722	}
2723
2724
2725	/** @callback_method_impl{FNCPUMRDMSR} */
2726	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpNominal(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2727	{
2728	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2729	/** @todo intel power management. */
2730	*puValue = pRange->uValue;
2731	return VINF_SUCCESS;
2732	}
2733
2734
2735	/** @callback_method_impl{FNCPUMRDMSR} */
2736	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpLevel1(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2737	{
2738	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2739	/** @todo intel power management. */
2740	*puValue = pRange->uValue;
2741	return VINF_SUCCESS;
2742	}
2743
2744
2745	/** @callback_method_impl{FNCPUMRDMSR} */
2746	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpLevel2(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2747	{
2748	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2749	/** @todo intel power management. */
2750	*puValue = pRange->uValue;
2751	return VINF_SUCCESS;
2752	}
2753
2754
2755	/** @callback_method_impl{FNCPUMRDMSR} */
2756	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2757	{
2758	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2759	/** @todo intel power management. */
2760	*puValue = 0;
2761	return VINF_SUCCESS;
2762	}
2763
2764
2765	/** @callback_method_impl{FNCPUMWRMSR} */
2766	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7IvyConfigTdpControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2767	{
2768	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2769	/** @todo intel power management. */
2770	return VINF_SUCCESS;
2771	}
2772
2773
2774	/** @callback_method_impl{FNCPUMRDMSR} */
2775	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyTurboActivationRatio(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2776	{
2777	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2778	/** @todo intel power management. */
2779	*puValue = 0;
2780	return VINF_SUCCESS;
2781	}
2782
2783
2784	/** @callback_method_impl{FNCPUMWRMSR} */
2785	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7IvyTurboActivationRatio(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2786	{
2787	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2788	/** @todo intel power management. */
2789	return VINF_SUCCESS;
2790	}
2791
2792
2793	/** @callback_method_impl{FNCPUMRDMSR} */
2794	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfGlobalCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2795	{
2796	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2797	/** @todo uncore msrs. */
2798	*puValue = 0;
2799	return VINF_SUCCESS;
2800	}
2801
2802
2803	/** @callback_method_impl{FNCPUMWRMSR} */
2804	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfGlobalCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2805	{
2806	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2807	/** @todo uncore msrs. */
2808	return VINF_SUCCESS;
2809	}
2810
2811
2812	/** @callback_method_impl{FNCPUMRDMSR} */
2813	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfGlobalStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2814	{
2815	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2816	/** @todo uncore msrs. */
2817	*puValue = 0;
2818	return VINF_SUCCESS;
2819	}
2820
2821
2822	/** @callback_method_impl{FNCPUMWRMSR} */
2823	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfGlobalStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2824	{
2825	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2826	/** @todo uncore msrs. */
2827	return VINF_SUCCESS;
2828	}
2829
2830
2831	/** @callback_method_impl{FNCPUMRDMSR} */
2832	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfGlobalOvfCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2833	{
2834	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2835	/** @todo uncore msrs. */
2836	*puValue = 0;
2837	return VINF_SUCCESS;
2838	}
2839
2840
2841	/** @callback_method_impl{FNCPUMWRMSR} */
2842	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfGlobalOvfCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2843	{
2844	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2845	/** @todo uncore msrs. */
2846	return VINF_SUCCESS;
2847	}
2848
2849
2850	/** @callback_method_impl{FNCPUMRDMSR} */
2851	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfFixedCtrCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2852	{
2853	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2854	/** @todo uncore msrs. */
2855	*puValue = 0;
2856	return VINF_SUCCESS;
2857	}
2858
2859
2860	/** @callback_method_impl{FNCPUMWRMSR} */
2861	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfFixedCtrCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2862	{
2863	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2864	/** @todo uncore msrs. */
2865	return VINF_SUCCESS;
2866	}
2867
2868
2869	/** @callback_method_impl{FNCPUMRDMSR} */
2870	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfFixedCtr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2871	{
2872	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2873	/** @todo uncore msrs. */
2874	*puValue = 0;
2875	return VINF_SUCCESS;
2876	}
2877
2878
2879	/** @callback_method_impl{FNCPUMWRMSR} */
2880	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfFixedCtr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2881	{
2882	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2883	/** @todo uncore msrs. */
2884	return VINF_SUCCESS;
2885	}
2886
2887
2888	/** @callback_method_impl{FNCPUMRDMSR} */
2889	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncCBoxConfig(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2890	{
2891	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2892	/** @todo uncore msrs. */
2893	*puValue = 0;
2894	return VINF_SUCCESS;
2895	}
2896
2897
2898	/** @callback_method_impl{FNCPUMRDMSR} */
2899	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncArbPerfCtrN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2900	{
2901	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2902	/** @todo uncore msrs. */
2903	*puValue = 0;
2904	return VINF_SUCCESS;
2905	}
2906
2907
2908	/** @callback_method_impl{FNCPUMWRMSR} */
2909	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncArbPerfCtrN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2910	{
2911	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2912	/** @todo uncore msrs. */
2913	return VINF_SUCCESS;
2914	}
2915
2916
2917	/** @callback_method_impl{FNCPUMRDMSR} */
2918	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncArbPerfEvtSelN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2919	{
2920	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2921	/** @todo uncore msrs. */
2922	*puValue = 0;
2923	return VINF_SUCCESS;
2924	}
2925
2926
2927	/** @callback_method_impl{FNCPUMWRMSR} */
2928	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncArbPerfEvtSelN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2929	{
2930	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2931	/** @todo uncore msrs. */
2932	return VINF_SUCCESS;
2933	}
2934
2935
2936	/** @callback_method_impl{FNCPUMRDMSR} */
2937	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SmiCount(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2938	{
2939	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2940
2941	/*
2942	* 31:0 is SMI count (read only), 63:32 reserved.
2943	* Since we don't do SMI, the count is always zero.
2944	*/
2945	*puValue = 0;
2946	return VINF_SUCCESS;
2947	}
2948
2949
2950	/** @callback_method_impl{FNCPUMRDMSR} */
2951	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore2EmttmCrTablesN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2952	{
2953	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2954	/** @todo implement enhanced multi thread termal monitoring? */
2955	*puValue = pRange->uValue;
2956	return VINF_SUCCESS;
2957	}
2958
2959
2960	/** @callback_method_impl{FNCPUMWRMSR} */
2961	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore2EmttmCrTablesN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2962	{
2963	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2964	/** @todo implement enhanced multi thread termal monitoring? */
2965	return VINF_SUCCESS;
2966	}
2967
2968
2969	/** @callback_method_impl{FNCPUMRDMSR} */
2970	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore2SmmCStMiscInfo(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2971	{
2972	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2973	/** @todo SMM & C-states? */
2974	*puValue = 0;
2975	return VINF_SUCCESS;
2976	}
2977
2978
2979	/** @callback_method_impl{FNCPUMWRMSR} */
2980	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore2SmmCStMiscInfo(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2981	{
2982	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2983	/** @todo SMM & C-states? */
2984	return VINF_SUCCESS;
2985	}
2986
2987
2988	/** @callback_method_impl{FNCPUMRDMSR} */
2989	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore1ExtConfig(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2990	{
2991	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2992	/** @todo Core1&2 EXT_CONFIG (whatever that is)? */
2993	*puValue = 0;
2994	return VINF_SUCCESS;
2995	}
2996
2997
2998	/** @callback_method_impl{FNCPUMWRMSR} */
2999	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore1ExtConfig(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3000	{
3001	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3002	/** @todo Core1&2 EXT_CONFIG (whatever that is)? */
3003	return VINF_SUCCESS;
3004	}
3005
3006
3007	/** @callback_method_impl{FNCPUMRDMSR} */
3008	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore1DtsCalControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3009	{
3010	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3011	/** @todo Core1&2(?) DTS_CAL_CTRL (whatever that is)? */
3012	*puValue = 0;
3013	return VINF_SUCCESS;
3014	}
3015
3016
3017	/** @callback_method_impl{FNCPUMWRMSR} */
3018	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore1DtsCalControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3019	{
3020	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3021	/** @todo Core1&2(?) DTS_CAL_CTRL (whatever that is)? */
3022	return VINF_SUCCESS;
3023	}
3024
3025
3026	/** @callback_method_impl{FNCPUMRDMSR} */
3027	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore2PeciControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3028	{
3029	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3030	/** @todo Core2+ platform environment control interface control register? */
3031	*puValue = 0;
3032	return VINF_SUCCESS;
3033	}
3034
3035
3036	/** @callback_method_impl{FNCPUMWRMSR} */
3037	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore2PeciControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3038	{
3039	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3040	/** @todo Core2+ platform environment control interface control register? */
3041	return VINF_SUCCESS;
3042	}
3043
3044
3045	/** @callback_method_impl{FNCPUMRDMSR} */
3046	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelAtSilvCoreC1Recidency(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3047	{
3048	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3049	*puValue = 0;
3050	return VINF_SUCCESS;
3051	}
3052
3053
3054	/*
3055	* Multiple vendor P6 MSRs.
3056	* Multiple vendor P6 MSRs.
3057	* Multiple vendor P6 MSRs.
3058	*
3059	* These MSRs were introduced with the P6 but not elevated to architectural
3060	* MSRs, despite other vendors implementing them.
3061	*/
3062
3063
3064	/** @callback_method_impl{FNCPUMRDMSR} */
3065	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastBranchFromIp(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3066	{
3067	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3068	/* AMD seems to just record RIP, while intel claims to record RIP+CS.BASE
3069	if I read the docs correctly, thus the need for separate functions. */
3070	/** @todo implement last branch records. */
3071	*puValue = 0;
3072	return VINF_SUCCESS;
3073	}
3074
3075
3076	/** @callback_method_impl{FNCPUMRDMSR} */
3077	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastBranchToIp(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3078	{
3079	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3080	/** @todo implement last branch records. */
3081	*puValue = 0;
3082	return VINF_SUCCESS;
3083	}
3084
3085
3086	/** @callback_method_impl{FNCPUMRDMSR} */
3087	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastIntFromIp(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3088	{
3089	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3090	/** @todo implement last exception records. */
3091	*puValue = 0;
3092	return VINF_SUCCESS;
3093	}
3094
3095
3096	/** @callback_method_impl{FNCPUMWRMSR} */
3097	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_P6LastIntFromIp(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3098	{
3099	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3100	/** @todo implement last exception records. */
3101	/* Note! On many CPUs, the high bit of the 0x000001dd register is always writable, even when the result is
3102	a non-cannonical address. */
3103	return VINF_SUCCESS;
3104	}
3105
3106
3107	/** @callback_method_impl{FNCPUMRDMSR} */
3108	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastIntToIp(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3109	{
3110	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3111	/** @todo implement last exception records. */
3112	*puValue = 0;
3113	return VINF_SUCCESS;
3114	}
3115
3116
3117	/** @callback_method_impl{FNCPUMWRMSR} */
3118	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_P6LastIntToIp(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3119	{
3120	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3121	/** @todo implement last exception records. */
3122	return VINF_SUCCESS;
3123	}
3124
3125
3126
3127	/*
3128	* AMD specific
3129	* AMD specific
3130	* AMD specific
3131	*/
3132
3133
3134	/** @callback_method_impl{FNCPUMRDMSR} */
3135	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hTscRate(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3136	{
3137	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3138	/** @todo Implement TscRateMsr */
3139	puValue = RT_MAKE_U64(0, 1); / 1.0 = reset value. */
3140	return VINF_SUCCESS;
3141	}
3142
3143
3144	/** @callback_method_impl{FNCPUMWRMSR} */
3145	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hTscRate(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3146	{
3147	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3148	/** @todo Implement TscRateMsr */
3149	return VINF_SUCCESS;
3150	}
3151
3152
3153	/** @callback_method_impl{FNCPUMRDMSR} */
3154	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hLwpCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3155	{
3156	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3157	/** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
3158	/* Note: Only listes in BKDG for Family 15H. */
3159	*puValue = 0;
3160	return VINF_SUCCESS;
3161	}
3162
3163
3164	/** @callback_method_impl{FNCPUMWRMSR} */
3165	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hLwpCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3166	{
3167	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3168	/** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
3169	return VINF_SUCCESS;
3170	}
3171
3172
3173	/** @callback_method_impl{FNCPUMRDMSR} */
3174	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hLwpCbAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3175	{
3176	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3177	/** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
3178	/* Note: Only listes in BKDG for Family 15H. */
3179	*puValue = 0;
3180	return VINF_SUCCESS;
3181	}
3182
3183
3184	/** @callback_method_impl{FNCPUMWRMSR} */
3185	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hLwpCbAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3186	{
3187	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3188	/** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
3189	return VINF_SUCCESS;
3190	}
3191
3192
3193	/** @callback_method_impl{FNCPUMRDMSR} */
3194	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hMc4MiscN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3195	{
3196	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3197	/** @todo machine check. */
3198	*puValue = 0;
3199	return VINF_SUCCESS;
3200	}
3201
3202
3203	/** @callback_method_impl{FNCPUMWRMSR} */
3204	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hMc4MiscN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3205	{
3206	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3207	/** @todo machine check. */
3208	return VINF_SUCCESS;
3209	}
3210
3211
3212	/** @callback_method_impl{FNCPUMRDMSR} */
3213	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8PerfCtlN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3214	{
3215	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3216	/** @todo AMD performance events. */
3217	*puValue = 0;
3218	return VINF_SUCCESS;
3219	}
3220
3221
3222	/** @callback_method_impl{FNCPUMWRMSR} */
3223	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8PerfCtlN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3224	{
3225	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3226	/** @todo AMD performance events. */
3227	return VINF_SUCCESS;
3228	}
3229
3230
3231	/** @callback_method_impl{FNCPUMRDMSR} */
3232	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8PerfCtrN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3233	{
3234	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3235	/** @todo AMD performance events. */
3236	*puValue = 0;
3237	return VINF_SUCCESS;
3238	}
3239
3240
3241	/** @callback_method_impl{FNCPUMWRMSR} */
3242	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8PerfCtrN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3243	{
3244	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3245	/** @todo AMD performance events. */
3246	return VINF_SUCCESS;
3247	}
3248
3249
3250	/** @callback_method_impl{FNCPUMRDMSR} */
3251	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SysCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3252	{
3253	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3254	/** @todo AMD SYS_CFG */
3255	*puValue = pRange->uValue;
3256	return VINF_SUCCESS;
3257	}
3258
3259
3260	/** @callback_method_impl{FNCPUMWRMSR} */
3261	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SysCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3262	{
3263	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3264	/** @todo AMD SYS_CFG */
3265	return VINF_SUCCESS;
3266	}
3267
3268
3269	/** @callback_method_impl{FNCPUMRDMSR} */
3270	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8HwCr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3271	{
3272	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3273	/** @todo AMD HW_CFG */
3274	*puValue = 0;
3275	return VINF_SUCCESS;
3276	}
3277
3278
3279	/** @callback_method_impl{FNCPUMWRMSR} */
3280	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8HwCr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3281	{
3282	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3283	/** @todo AMD HW_CFG */
3284	return VINF_SUCCESS;
3285	}
3286
3287
3288	/** @callback_method_impl{FNCPUMRDMSR} */
3289	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IorrBaseN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3290	{
3291	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3292	/** @todo AMD IorrMask/IorrBase */
3293	*puValue = 0;
3294	return VINF_SUCCESS;
3295	}
3296
3297
3298	/** @callback_method_impl{FNCPUMWRMSR} */
3299	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IorrBaseN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3300	{
3301	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3302	/** @todo AMD IorrMask/IorrBase */
3303	return VINF_SUCCESS;
3304	}
3305
3306
3307	/** @callback_method_impl{FNCPUMRDMSR} */
3308	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IorrMaskN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3309	{
3310	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3311	/** @todo AMD IorrMask/IorrBase */
3312	*puValue = 0;
3313	return VINF_SUCCESS;
3314	}
3315
3316
3317	/** @callback_method_impl{FNCPUMWRMSR} */
3318	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IorrMaskN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3319	{
3320	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3321	/** @todo AMD IorrMask/IorrBase */
3322	return VINF_SUCCESS;
3323	}
3324
3325
3326	/** @callback_method_impl{FNCPUMRDMSR} */
3327	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8TopOfMemN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3328	{
3329	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3330	*puValue = 0;
3331	/** @todo return 4GB - RamHoleSize here for TOPMEM. Figure out what to return
3332	* for TOPMEM2. */
3333	//if (pRange->uValue == 0)
3334	// *puValue = _4G - RamHoleSize;
3335	return VINF_SUCCESS;
3336	}
3337
3338
3339	/** @callback_method_impl{FNCPUMWRMSR} */
3340	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8TopOfMemN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3341	{
3342	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3343	/** @todo AMD TOPMEM and TOPMEM2/TOM2. */
3344	return VINF_SUCCESS;
3345	}
3346
3347
3348	/** @callback_method_impl{FNCPUMRDMSR} */
3349	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8NbCfg1(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3350	{
3351	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3352	/** @todo AMD NB_CFG1 */
3353	*puValue = 0;
3354	return VINF_SUCCESS;
3355	}
3356
3357
3358	/** @callback_method_impl{FNCPUMWRMSR} */
3359	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8NbCfg1(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3360	{
3361	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3362	/** @todo AMD NB_CFG1 */
3363	return VINF_SUCCESS;
3364	}
3365
3366
3367	/** @callback_method_impl{FNCPUMRDMSR} */
3368	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8McXcptRedir(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3369	{
3370	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3371	/** @todo machine check. */
3372	*puValue = 0;
3373	return VINF_SUCCESS;
3374	}
3375
3376
3377	/** @callback_method_impl{FNCPUMWRMSR} */
3378	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8McXcptRedir(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3379	{
3380	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3381	/** @todo machine check. */
3382	return VINF_SUCCESS;
3383	}
3384
3385
3386	/** @callback_method_impl{FNCPUMRDMSR} */
3387	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuNameN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3388	{
3389	RT_NOREF_PV(idMsr);
3390	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), pRange->uValue / 2 + 0x80000001);
3391	if (pLeaf)
3392	{
3393	if (!(pRange->uValue & 1))
3394	*puValue = RT_MAKE_U64(pLeaf->uEax, pLeaf->uEbx);
3395	else
3396	*puValue = RT_MAKE_U64(pLeaf->uEcx, pLeaf->uEdx);
3397	}
3398	else
3399	*puValue = 0;
3400	return VINF_SUCCESS;
3401	}
3402
3403
3404	/** @callback_method_impl{FNCPUMWRMSR} */
3405	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuNameN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3406	{
3407	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3408	/** @todo Remember guest programmed CPU name. */
3409	return VINF_SUCCESS;
3410	}
3411
3412
3413	/** @callback_method_impl{FNCPUMRDMSR} */
3414	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8HwThermalCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3415	{
3416	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3417	/** @todo AMD HTC. */
3418	*puValue = pRange->uValue;
3419	return VINF_SUCCESS;
3420	}
3421
3422
3423	/** @callback_method_impl{FNCPUMWRMSR} */
3424	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8HwThermalCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3425	{
3426	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3427	/** @todo AMD HTC. */
3428	return VINF_SUCCESS;
3429	}
3430
3431
3432	/** @callback_method_impl{FNCPUMRDMSR} */
3433	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SwThermalCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3434	{
3435	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3436	/** @todo AMD STC. */
3437	*puValue = 0;
3438	return VINF_SUCCESS;
3439	}
3440
3441
3442	/** @callback_method_impl{FNCPUMWRMSR} */
3443	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SwThermalCtrl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3444	{
3445	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3446	/** @todo AMD STC. */
3447	return VINF_SUCCESS;
3448	}
3449
3450
3451	/** @callback_method_impl{FNCPUMRDMSR} */
3452	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8FidVidControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3453	{
3454	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3455	/** @todo AMD FIDVID_CTL. */
3456	*puValue = pRange->uValue;
3457	return VINF_SUCCESS;
3458	}
3459
3460
3461	/** @callback_method_impl{FNCPUMWRMSR} */
3462	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8FidVidControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3463	{
3464	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3465	/** @todo AMD FIDVID_CTL. */
3466	return VINF_SUCCESS;
3467	}
3468
3469
3470	/** @callback_method_impl{FNCPUMRDMSR} */
3471	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8FidVidStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3472	{
3473	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3474	/** @todo AMD FIDVID_STATUS. */
3475	*puValue = pRange->uValue;
3476	return VINF_SUCCESS;
3477	}
3478
3479
3480	/** @callback_method_impl{FNCPUMRDMSR} */
3481	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8McCtlMaskN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3482	{
3483	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3484	/** @todo AMD MC. */
3485	*puValue = 0;
3486	return VINF_SUCCESS;
3487	}
3488
3489
3490	/** @callback_method_impl{FNCPUMWRMSR} */
3491	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8McCtlMaskN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3492	{
3493	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3494	/** @todo AMD MC. */
3495	return VINF_SUCCESS;
3496	}
3497
3498
3499	/** @callback_method_impl{FNCPUMRDMSR} */
3500	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmiOnIoTrapN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3501	{
3502	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3503	/** @todo AMD SMM/SMI and I/O trap. */
3504	*puValue = 0;
3505	return VINF_SUCCESS;
3506	}
3507
3508
3509	/** @callback_method_impl{FNCPUMWRMSR} */
3510	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmiOnIoTrapN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3511	{
3512	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3513	/** @todo AMD SMM/SMI and I/O trap. */
3514	return VINF_SUCCESS;
3515	}
3516
3517
3518	/** @callback_method_impl{FNCPUMRDMSR} */
3519	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmiOnIoTrapCtlSts(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3520	{
3521	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3522	/** @todo AMD SMM/SMI and I/O trap. */
3523	*puValue = 0;
3524	return VINF_SUCCESS;
3525	}
3526
3527
3528	/** @callback_method_impl{FNCPUMWRMSR} */
3529	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmiOnIoTrapCtlSts(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3530	{
3531	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3532	/** @todo AMD SMM/SMI and I/O trap. */
3533	return VINF_SUCCESS;
3534	}
3535
3536
3537	/** @callback_method_impl{FNCPUMRDMSR} */
3538	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IntPendingMessage(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3539	{
3540	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3541	/** @todo Interrupt pending message. */
3542	*puValue = 0;
3543	return VINF_SUCCESS;
3544	}
3545
3546
3547	/** @callback_method_impl{FNCPUMWRMSR} */
3548	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IntPendingMessage(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3549	{
3550	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3551	/** @todo Interrupt pending message. */
3552	return VINF_SUCCESS;
3553	}
3554
3555
3556	/** @callback_method_impl{FNCPUMRDMSR} */
3557	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmiTriggerIoCycle(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3558	{
3559	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3560	/** @todo AMD SMM/SMI and trigger I/O cycle. */
3561	*puValue = 0;
3562	return VINF_SUCCESS;
3563	}
3564
3565
3566	/** @callback_method_impl{FNCPUMWRMSR} */
3567	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmiTriggerIoCycle(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3568	{
3569	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3570	/** @todo AMD SMM/SMI and trigger I/O cycle. */
3571	return VINF_SUCCESS;
3572	}
3573
3574
3575	/** @callback_method_impl{FNCPUMRDMSR} */
3576	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hMmioCfgBaseAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3577	{
3578	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3579	/** @todo AMD MMIO Configuration base address. */
3580	*puValue = 0;
3581	return VINF_SUCCESS;
3582	}
3583
3584
3585	/** @callback_method_impl{FNCPUMWRMSR} */
3586	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hMmioCfgBaseAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3587	{
3588	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3589	/** @todo AMD MMIO Configuration base address. */
3590	return VINF_SUCCESS;
3591	}
3592
3593
3594	/** @callback_method_impl{FNCPUMRDMSR} */
3595	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hTrapCtlMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3596	{
3597	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3598	/** @todo AMD 0xc0010059. */
3599	*puValue = 0;
3600	return VINF_SUCCESS;
3601	}
3602
3603
3604	/** @callback_method_impl{FNCPUMWRMSR} */
3605	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hTrapCtlMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3606	{
3607	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3608	/** @todo AMD 0xc0010059. */
3609	return VINF_SUCCESS;
3610	}
3611
3612
3613	/** @callback_method_impl{FNCPUMRDMSR} */
3614	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateCurLimit(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3615	{
3616	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3617	/** @todo AMD P-states. */
3618	*puValue = pRange->uValue;
3619	return VINF_SUCCESS;
3620	}
3621
3622
3623	/** @callback_method_impl{FNCPUMRDMSR} */
3624	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3625	{
3626	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3627	/** @todo AMD P-states. */
3628	*puValue = pRange->uValue;
3629	return VINF_SUCCESS;
3630	}
3631
3632
3633	/** @callback_method_impl{FNCPUMWRMSR} */
3634	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hPStateControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3635	{
3636	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3637	/** @todo AMD P-states. */
3638	return VINF_SUCCESS;
3639	}
3640
3641
3642	/** @callback_method_impl{FNCPUMRDMSR} */
3643	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3644	{
3645	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3646	/** @todo AMD P-states. */
3647	*puValue = pRange->uValue;
3648	return VINF_SUCCESS;
3649	}
3650
3651
3652	/** @callback_method_impl{FNCPUMWRMSR} */
3653	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hPStateStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3654	{
3655	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3656	/** @todo AMD P-states. */
3657	return VINF_SUCCESS;
3658	}
3659
3660
3661	/** @callback_method_impl{FNCPUMRDMSR} */
3662	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3663	{
3664	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3665	/** @todo AMD P-states. */
3666	*puValue = pRange->uValue;
3667	return VINF_SUCCESS;
3668	}
3669
3670
3671	/** @callback_method_impl{FNCPUMWRMSR} */
3672	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hPStateN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3673	{
3674	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3675	/** @todo AMD P-states. */
3676	return VINF_SUCCESS;
3677	}
3678
3679
3680	/** @callback_method_impl{FNCPUMRDMSR} */
3681	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCofVidControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3682	{
3683	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3684	/** @todo AMD P-states. */
3685	*puValue = pRange->uValue;
3686	return VINF_SUCCESS;
3687	}
3688
3689
3690	/** @callback_method_impl{FNCPUMWRMSR} */
3691	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCofVidControl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3692	{
3693	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3694	/** @todo AMD P-states. */
3695	return VINF_SUCCESS;
3696	}
3697
3698
3699	/** @callback_method_impl{FNCPUMRDMSR} */
3700	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCofVidStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3701	{
3702	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3703	/** @todo AMD P-states. */
3704	*puValue = pRange->uValue;
3705	return VINF_SUCCESS;
3706	}
3707
3708
3709	/** @callback_method_impl{FNCPUMWRMSR} */
3710	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCofVidStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3711	{
3712	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3713	/* Note! Writing 0 seems to not GP, not sure if it does anything to the value... */
3714	/** @todo AMD P-states. */
3715	return VINF_SUCCESS;
3716	}
3717
3718
3719	/** @callback_method_impl{FNCPUMRDMSR} */
3720	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCStateIoBaseAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3721	{
3722	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3723	/** @todo AMD C-states. */
3724	*puValue = 0;
3725	return VINF_SUCCESS;
3726	}
3727
3728
3729	/** @callback_method_impl{FNCPUMWRMSR} */
3730	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCStateIoBaseAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3731	{
3732	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3733	/** @todo AMD C-states. */
3734	return VINF_SUCCESS;
3735	}
3736
3737
3738	/** @callback_method_impl{FNCPUMRDMSR} */
3739	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCpuWatchdogTimer(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3740	{
3741	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3742	/** @todo AMD machine checks. */
3743	*puValue = 0;
3744	return VINF_SUCCESS;
3745	}
3746
3747
3748	/** @callback_method_impl{FNCPUMWRMSR} */
3749	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCpuWatchdogTimer(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3750	{
3751	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3752	/** @todo AMD machine checks. */
3753	return VINF_SUCCESS;
3754	}
3755
3756
3757	/** @callback_method_impl{FNCPUMRDMSR} */
3758	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmBase(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3759	{
3760	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3761	/** @todo AMD SMM. */
3762	*puValue = 0;
3763	return VINF_SUCCESS;
3764	}
3765
3766
3767	/** @callback_method_impl{FNCPUMWRMSR} */
3768	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmBase(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3769	{
3770	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3771	/** @todo AMD SMM. */
3772	return VINF_SUCCESS;
3773	}
3774
3775
3776	/** @callback_method_impl{FNCPUMRDMSR} */
3777	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3778	{
3779	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3780	/** @todo AMD SMM. */
3781	*puValue = 0;
3782	return VINF_SUCCESS;
3783	}
3784
3785
3786	/** @callback_method_impl{FNCPUMWRMSR} */
3787	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3788	{
3789	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3790	/** @todo AMD SMM. */
3791	return VINF_SUCCESS;
3792	}
3793
3794
3795
3796	/** @callback_method_impl{FNCPUMRDMSR} */
3797	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmMask(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3798	{
3799	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3800	/** @todo AMD SMM. */
3801	*puValue = 0;
3802	return VINF_SUCCESS;
3803	}
3804
3805
3806	/** @callback_method_impl{FNCPUMWRMSR} */
3807	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmMask(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3808	{
3809	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3810	/** @todo AMD SMM. */
3811	return VINF_SUCCESS;
3812	}
3813
3814
3815	/** @callback_method_impl{FNCPUMRDMSR} */
3816	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8VmCr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3817	{
3818	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3819	PVM pVM = pVCpu->CTX_SUFF(pVM);
3820	if (pVM->cpum.s.GuestFeatures.fSvm)
3821	*puValue = MSR_K8_VM_CR_LOCK;
3822	else
3823	*puValue = 0;
3824	return VINF_SUCCESS;
3825	}
3826
3827
3828	/** @callback_method_impl{FNCPUMWRMSR} */
3829	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8VmCr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3830	{
3831	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
3832	PVM pVM = pVCpu->CTX_SUFF(pVM);
3833	if (pVM->cpum.s.GuestFeatures.fSvm)
3834	{
3835	/* Silently ignore writes to LOCK and SVM_DISABLE bit when the LOCK bit is set (see cpumMsrRd_AmdK8VmCr). */
3836	if (uValue & (MSR_K8_VM_CR_DPD \| MSR_K8_VM_CR_R_INIT \| MSR_K8_VM_CR_DIS_A20M))
3837	return VERR_CPUM_RAISE_GP_0;
3838	return VINF_SUCCESS;
3839	}
3840	return VERR_CPUM_RAISE_GP_0;
3841	}
3842
3843
3844	/** @callback_method_impl{FNCPUMRDMSR} */
3845	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IgnNe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3846	{
3847	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3848	/** @todo AMD IGNNE\# control. */
3849	*puValue = 0;
3850	return VINF_SUCCESS;
3851	}
3852
3853
3854	/** @callback_method_impl{FNCPUMWRMSR} */
3855	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IgnNe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3856	{
3857	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3858	/** @todo AMD IGNNE\# control. */
3859	return VINF_SUCCESS;
3860	}
3861
3862
3863	/** @callback_method_impl{FNCPUMRDMSR} */
3864	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3865	{
3866	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3867	/** @todo AMD SMM. */
3868	*puValue = 0;
3869	return VINF_SUCCESS;
3870	}
3871
3872
3873	/** @callback_method_impl{FNCPUMWRMSR} */
3874	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3875	{
3876	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3877	/** @todo AMD SMM. */
3878	return VINF_SUCCESS;
3879	}
3880
3881
3882	/** @callback_method_impl{FNCPUMRDMSR} */
3883	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8VmHSavePa(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3884	{
3885	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3886	*puValue = pVCpu->cpum.s.Guest.hwvirt.svm.uMsrHSavePa;
3887	return VINF_SUCCESS;
3888	}
3889
3890
3891	/** @callback_method_impl{FNCPUMWRMSR} */
3892	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8VmHSavePa(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3893	{
3894	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
3895	if (uValue & UINT64_C(0xfff))
3896	{
3897	Log(("CPUM: Invalid setting of low 12 bits set writing host-state save area MSR %#x: %#llx\n", idMsr, uValue));
3898	return VERR_CPUM_RAISE_GP_0;
3899	}
3900
3901	uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
3902	if (fInvPhysMask & uValue)
3903	{
3904	Log(("CPUM: Invalid physical address bits set writing host-state save area MSR %#x: %#llx (%#llx)\n",
3905	idMsr, uValue, uValue & fInvPhysMask));
3906	return VERR_CPUM_RAISE_GP_0;
3907	}
3908
3909	pVCpu->cpum.s.Guest.hwvirt.svm.uMsrHSavePa = uValue;
3910	return VINF_SUCCESS;
3911	}
3912
3913
3914	/** @callback_method_impl{FNCPUMRDMSR} */
3915	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hVmLockKey(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3916	{
3917	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3918	/** @todo AMD SVM. */
3919	puValue = 0; / RAZ */
3920	return VINF_SUCCESS;
3921	}
3922
3923
3924	/** @callback_method_impl{FNCPUMWRMSR} */
3925	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hVmLockKey(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3926	{
3927	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3928	/** @todo AMD SVM. */
3929	return VINF_SUCCESS;
3930	}
3931
3932
3933	/** @callback_method_impl{FNCPUMRDMSR} */
3934	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hSmmLockKey(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3935	{
3936	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3937	/** @todo AMD SMM. */
3938	puValue = 0; / RAZ */
3939	return VINF_SUCCESS;
3940	}
3941
3942
3943	/** @callback_method_impl{FNCPUMWRMSR} */
3944	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hSmmLockKey(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3945	{
3946	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3947	/** @todo AMD SMM. */
3948	return VINF_SUCCESS;
3949	}
3950
3951
3952	/** @callback_method_impl{FNCPUMRDMSR} */
3953	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hLocalSmiStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3954	{
3955	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3956	/** @todo AMD SMM/SMI. */
3957	*puValue = 0;
3958	return VINF_SUCCESS;
3959	}
3960
3961
3962	/** @callback_method_impl{FNCPUMWRMSR} */
3963	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hLocalSmiStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3964	{
3965	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3966	/** @todo AMD SMM/SMI. */
3967	return VINF_SUCCESS;
3968	}
3969
3970
3971	/** @callback_method_impl{FNCPUMRDMSR} */
3972	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hOsVisWrkIdLength(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3973	{
3974	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
3975	/** @todo AMD OS visible workaround. */
3976	*puValue = pRange->uValue;
3977	return VINF_SUCCESS;
3978	}
3979
3980
3981	/** @callback_method_impl{FNCPUMWRMSR} */
3982	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hOsVisWrkIdLength(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3983	{
3984	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3985	/** @todo AMD OS visible workaround. */
3986	return VINF_SUCCESS;
3987	}
3988
3989
3990	/** @callback_method_impl{FNCPUMRDMSR} */
3991	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hOsVisWrkStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3992	{
3993	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3994	/** @todo AMD OS visible workaround. */
3995	*puValue = 0;
3996	return VINF_SUCCESS;
3997	}
3998
3999
4000	/** @callback_method_impl{FNCPUMWRMSR} */
4001	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hOsVisWrkStatus(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4002	{
4003	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4004	/** @todo AMD OS visible workaround. */
4005	return VINF_SUCCESS;
4006	}
4007
4008
4009	/** @callback_method_impl{FNCPUMRDMSR} */
4010	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam16hL2IPerfCtlN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4011	{
4012	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4013	/** @todo AMD L2I performance counters. */
4014	*puValue = 0;
4015	return VINF_SUCCESS;
4016	}
4017
4018
4019	/** @callback_method_impl{FNCPUMWRMSR} */
4020	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam16hL2IPerfCtlN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4021	{
4022	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4023	/** @todo AMD L2I performance counters. */
4024	return VINF_SUCCESS;
4025	}
4026
4027
4028	/** @callback_method_impl{FNCPUMRDMSR} */
4029	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam16hL2IPerfCtrN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4030	{
4031	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4032	/** @todo AMD L2I performance counters. */
4033	*puValue = 0;
4034	return VINF_SUCCESS;
4035	}
4036
4037
4038	/** @callback_method_impl{FNCPUMWRMSR} */
4039	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam16hL2IPerfCtrN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4040	{
4041	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4042	/** @todo AMD L2I performance counters. */
4043	return VINF_SUCCESS;
4044	}
4045
4046
4047	/** @callback_method_impl{FNCPUMRDMSR} */
4048	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hNorthbridgePerfCtlN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4049	{
4050	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4051	/** @todo AMD Northbridge performance counters. */
4052	*puValue = 0;
4053	return VINF_SUCCESS;
4054	}
4055
4056
4057	/** @callback_method_impl{FNCPUMWRMSR} */
4058	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hNorthbridgePerfCtlN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4059	{
4060	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4061	/** @todo AMD Northbridge performance counters. */
4062	return VINF_SUCCESS;
4063	}
4064
4065
4066	/** @callback_method_impl{FNCPUMRDMSR} */
4067	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hNorthbridgePerfCtrN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4068	{
4069	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4070	/** @todo AMD Northbridge performance counters. */
4071	*puValue = 0;
4072	return VINF_SUCCESS;
4073	}
4074
4075
4076	/** @callback_method_impl{FNCPUMWRMSR} */
4077	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hNorthbridgePerfCtrN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4078	{
4079	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4080	/** @todo AMD Northbridge performance counters. */
4081	return VINF_SUCCESS;
4082	}
4083
4084
4085	/** @callback_method_impl{FNCPUMRDMSR} */
4086	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7MicrocodeCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4087	{
4088	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4089	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4090	* cpus. Need to be explored and verify K7 presence. */
4091	/** @todo Undocumented register only seen mentioned in fam15h erratum \#608. */
4092	*puValue = pRange->uValue;
4093	return VINF_SUCCESS;
4094	}
4095
4096
4097	/** @callback_method_impl{FNCPUMWRMSR} */
4098	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7MicrocodeCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4099	{
4100	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4101	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4102	* cpus. Need to be explored and verify K7 presence. */
4103	/** @todo Undocumented register only seen mentioned in fam15h erratum \#608. */
4104	return VINF_SUCCESS;
4105	}
4106
4107
4108	/** @callback_method_impl{FNCPUMRDMSR} */
4109	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7ClusterIdMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4110	{
4111	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4112	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4113	* cpus. Need to be explored and verify K7 presence. */
4114	/** @todo Undocumented register only seen mentioned in fam16h BKDG r3.00 when
4115	* describing EBL_CR_POWERON. */
4116	*puValue = pRange->uValue;
4117	return VINF_SUCCESS;
4118	}
4119
4120
4121	/** @callback_method_impl{FNCPUMWRMSR} */
4122	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7ClusterIdMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4123	{
4124	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4125	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4126	* cpus. Need to be explored and verify K7 presence. */
4127	/** @todo Undocumented register only seen mentioned in fam16h BKDG r3.00 when
4128	* describing EBL_CR_POWERON. */
4129	return VINF_SUCCESS;
4130	}
4131
4132
4133	/** @callback_method_impl{FNCPUMRDMSR} */
4134	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlStd07hEbax(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4135	{
4136	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4137	bool fIgnored;
4138	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafEx(pVCpu->CTX_SUFF(pVM), 0x00000007, 0, &fIgnored);
4139	if (pLeaf)
4140	*puValue = RT_MAKE_U64(pLeaf->uEbx, pLeaf->uEax);
4141	else
4142	*puValue = 0;
4143	return VINF_SUCCESS;
4144	}
4145
4146
4147	/** @callback_method_impl{FNCPUMWRMSR} */
4148	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlStd07hEbax(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4149	{
4150	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4151	/** @todo Changing CPUID leaf 7/0. */
4152	return VINF_SUCCESS;
4153	}
4154
4155
4156	/** @callback_method_impl{FNCPUMRDMSR} */
4157	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlStd06hEcx(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4158	{
4159	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4160	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000006);
4161	if (pLeaf)
4162	*puValue = pLeaf->uEcx;
4163	else
4164	*puValue = 0;
4165	return VINF_SUCCESS;
4166	}
4167
4168
4169	/** @callback_method_impl{FNCPUMWRMSR} */
4170	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlStd06hEcx(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4171	{
4172	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4173	/** @todo Changing CPUID leaf 6. */
4174	return VINF_SUCCESS;
4175	}
4176
4177
4178	/** @callback_method_impl{FNCPUMRDMSR} */
4179	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlStd01hEdcx(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4180	{
4181	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4182	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000001);
4183	if (pLeaf)
4184	*puValue = RT_MAKE_U64(pLeaf->uEdx, pLeaf->uEcx);
4185	else
4186	*puValue = 0;
4187	return VINF_SUCCESS;
4188	}
4189
4190
4191	/** @callback_method_impl{FNCPUMWRMSR} */
4192	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlStd01hEdcx(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4193	{
4194	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4195	/** @todo Changing CPUID leaf 0x80000001. */
4196	return VINF_SUCCESS;
4197	}
4198
4199
4200	/** @callback_method_impl{FNCPUMRDMSR} */
4201	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlExt01hEdcx(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4202	{
4203	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4204	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x80000001);
4205	if (pLeaf)
4206	*puValue = RT_MAKE_U64(pLeaf->uEdx, pLeaf->uEcx);
4207	else
4208	*puValue = 0;
4209	return VINF_SUCCESS;
4210	}
4211
4212
4213	/** @callback_method_impl{FNCPUMWRMSR} */
4214	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlExt01hEdcx(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4215	{
4216	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4217	/** @todo Changing CPUID leaf 0x80000001. */
4218	return VINF_SUCCESS;
4219	}
4220
4221
4222	/** @callback_method_impl{FNCPUMRDMSR} */
4223	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8PatchLevel(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4224	{
4225	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4226	/** @todo Fake AMD microcode patching. */
4227	*puValue = pRange->uValue;
4228	return VINF_SUCCESS;
4229	}
4230
4231
4232	/** @callback_method_impl{FNCPUMWRMSR} */
4233	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8PatchLoader(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4234	{
4235	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4236	/** @todo Fake AMD microcode patching. */
4237	return VINF_SUCCESS;
4238	}
4239
4240
4241	/** @callback_method_impl{FNCPUMRDMSR} */
4242	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DebugStatusMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4243	{
4244	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4245	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4246	* cpus. Need to be explored and verify K7 presence. */
4247	/** @todo undocumented */
4248	*puValue = 0;
4249	return VINF_SUCCESS;
4250	}
4251
4252
4253	/** @callback_method_impl{FNCPUMWRMSR} */
4254	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DebugStatusMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4255	{
4256	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4257	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4258	* cpus. Need to be explored and verify K7 presence. */
4259	/** @todo undocumented */
4260	return VINF_SUCCESS;
4261	}
4262
4263
4264	/** @callback_method_impl{FNCPUMRDMSR} */
4265	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BHTraceBaseMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4266	{
4267	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4268	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4269	* cpus. Need to be explored and verify K7 presence. */
4270	/** @todo undocumented */
4271	*puValue = 0;
4272	return VINF_SUCCESS;
4273	}
4274
4275
4276	/** @callback_method_impl{FNCPUMWRMSR} */
4277	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BHTraceBaseMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4278	{
4279	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4280	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4281	* cpus. Need to be explored and verify K7 presence. */
4282	/** @todo undocumented */
4283	return VINF_SUCCESS;
4284	}
4285
4286
4287	/** @callback_method_impl{FNCPUMRDMSR} */
4288	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BHTracePtrMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4289	{
4290	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4291	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4292	* cpus. Need to be explored and verify K7 presence. */
4293	/** @todo undocumented */
4294	*puValue = 0;
4295	return VINF_SUCCESS;
4296	}
4297
4298
4299	/** @callback_method_impl{FNCPUMWRMSR} */
4300	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BHTracePtrMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4301	{
4302	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4303	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4304	* cpus. Need to be explored and verify K7 presence. */
4305	/** @todo undocumented */
4306	return VINF_SUCCESS;
4307	}
4308
4309
4310	/** @callback_method_impl{FNCPUMRDMSR} */
4311	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BHTraceLimitMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4312	{
4313	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4314	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4315	* cpus. Need to be explored and verify K7 presence. */
4316	/** @todo undocumented */
4317	*puValue = 0;
4318	return VINF_SUCCESS;
4319	}
4320
4321
4322	/** @callback_method_impl{FNCPUMWRMSR} */
4323	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BHTraceLimitMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4324	{
4325	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4326	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4327	* cpus. Need to be explored and verify K7 presence. */
4328	/** @todo undocumented */
4329	return VINF_SUCCESS;
4330	}
4331
4332
4333	/** @callback_method_impl{FNCPUMRDMSR} */
4334	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7HardwareDebugToolCfgMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4335	{
4336	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4337	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4338	* cpus. Need to be explored and verify K7 presence. */
4339	/** @todo undocumented */
4340	*puValue = 0;
4341	return VINF_SUCCESS;
4342	}
4343
4344
4345	/** @callback_method_impl{FNCPUMWRMSR} */
4346	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7HardwareDebugToolCfgMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4347	{
4348	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4349	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4350	* cpus. Need to be explored and verify K7 presence. */
4351	/** @todo undocumented */
4352	return VINF_SUCCESS;
4353	}
4354
4355
4356	/** @callback_method_impl{FNCPUMRDMSR} */
4357	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7FastFlushCountMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4358	{
4359	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4360	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4361	* cpus. Need to be explored and verify K7 presence. */
4362	/** @todo undocumented */
4363	*puValue = 0;
4364	return VINF_SUCCESS;
4365	}
4366
4367
4368	/** @callback_method_impl{FNCPUMWRMSR} */
4369	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7FastFlushCountMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4370	{
4371	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4372	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4373	* cpus. Need to be explored and verify K7 presence. */
4374	/** @todo undocumented */
4375	return VINF_SUCCESS;
4376	}
4377
4378
4379	/** @callback_method_impl{FNCPUMRDMSR} */
4380	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7NodeId(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4381	{
4382	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4383	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4384	* cpus. Need to be explored and verify K7 presence. */
4385	/** @todo AMD node ID and bios scratch. */
4386	puValue = 0; / nodeid = 0; nodes-per-cpu = 1 */
4387	return VINF_SUCCESS;
4388	}
4389
4390
4391	/** @callback_method_impl{FNCPUMWRMSR} */
4392	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7NodeId(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4393	{
4394	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4395	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4396	* cpus. Need to be explored and verify K7 presence. */
4397	/** @todo AMD node ID and bios scratch. */
4398	return VINF_SUCCESS;
4399	}
4400
4401
4402	/** @callback_method_impl{FNCPUMRDMSR} */
4403	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DrXAddrMaskN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4404	{
4405	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4406	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4407	* cpus. Need to be explored and verify K7 presence. */
4408	/** @todo AMD DRx address masking (range breakpoints). */
4409	*puValue = 0;
4410	return VINF_SUCCESS;
4411	}
4412
4413
4414	/** @callback_method_impl{FNCPUMWRMSR} */
4415	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DrXAddrMaskN(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4416	{
4417	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4418	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4419	* cpus. Need to be explored and verify K7 presence. */
4420	/** @todo AMD DRx address masking (range breakpoints). */
4421	return VINF_SUCCESS;
4422	}
4423
4424
4425	/** @callback_method_impl{FNCPUMRDMSR} */
4426	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7Dr0DataMatchMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4427	{
4428	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4429	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4430	* cpus. Need to be explored and verify K7 presence. */
4431	/** @todo AMD undocument debugging features. */
4432	*puValue = 0;
4433	return VINF_SUCCESS;
4434	}
4435
4436
4437	/** @callback_method_impl{FNCPUMWRMSR} */
4438	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7Dr0DataMatchMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4439	{
4440	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4441	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4442	* cpus. Need to be explored and verify K7 presence. */
4443	/** @todo AMD undocument debugging features. */
4444	return VINF_SUCCESS;
4445	}
4446
4447
4448	/** @callback_method_impl{FNCPUMRDMSR} */
4449	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7Dr0DataMaskMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4450	{
4451	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4452	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4453	* cpus. Need to be explored and verify K7 presence. */
4454	/** @todo AMD undocument debugging features. */
4455	*puValue = 0;
4456	return VINF_SUCCESS;
4457	}
4458
4459
4460	/** @callback_method_impl{FNCPUMWRMSR} */
4461	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7Dr0DataMaskMaybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4462	{
4463	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4464	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4465	* cpus. Need to be explored and verify K7 presence. */
4466	/** @todo AMD undocument debugging features. */
4467	return VINF_SUCCESS;
4468	}
4469
4470
4471	/** @callback_method_impl{FNCPUMRDMSR} */
4472	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7LoadStoreCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4473	{
4474	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4475	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4476	* cpus. Need to be explored and verify K7 presence. */
4477	/** @todo AMD load-store config. */
4478	*puValue = 0;
4479	return VINF_SUCCESS;
4480	}
4481
4482
4483	/** @callback_method_impl{FNCPUMWRMSR} */
4484	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7LoadStoreCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4485	{
4486	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4487	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4488	* cpus. Need to be explored and verify K7 presence. */
4489	/** @todo AMD load-store config. */
4490	return VINF_SUCCESS;
4491	}
4492
4493
4494	/** @callback_method_impl{FNCPUMRDMSR} */
4495	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7InstrCacheCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4496	{
4497	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4498	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4499	* cpus. Need to be explored and verify K7 presence. */
4500	/** @todo AMD instruction cache config. */
4501	*puValue = 0;
4502	return VINF_SUCCESS;
4503	}
4504
4505
4506	/** @callback_method_impl{FNCPUMWRMSR} */
4507	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7InstrCacheCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4508	{
4509	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4510	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4511	* cpus. Need to be explored and verify K7 presence. */
4512	/** @todo AMD instruction cache config. */
4513	return VINF_SUCCESS;
4514	}
4515
4516
4517	/** @callback_method_impl{FNCPUMRDMSR} */
4518	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DataCacheCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4519	{
4520	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4521	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4522	* cpus. Need to be explored and verify K7 presence. */
4523	/** @todo AMD data cache config. */
4524	*puValue = 0;
4525	return VINF_SUCCESS;
4526	}
4527
4528
4529	/** @callback_method_impl{FNCPUMWRMSR} */
4530	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DataCacheCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4531	{
4532	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4533	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4534	* cpus. Need to be explored and verify K7 presence. */
4535	/** @todo AMD data cache config. */
4536	return VINF_SUCCESS;
4537	}
4538
4539
4540	/** @callback_method_impl{FNCPUMRDMSR} */
4541	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BusUnitCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4542	{
4543	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4544	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4545	* cpus. Need to be explored and verify K7 presence. */
4546	/** @todo AMD bus unit config. */
4547	*puValue = 0;
4548	return VINF_SUCCESS;
4549	}
4550
4551
4552	/** @callback_method_impl{FNCPUMWRMSR} */
4553	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BusUnitCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4554	{
4555	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4556	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4557	* cpus. Need to be explored and verify K7 presence. */
4558	/** @todo AMD bus unit config. */
4559	return VINF_SUCCESS;
4560	}
4561
4562
4563	/** @callback_method_impl{FNCPUMRDMSR} */
4564	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DebugCtl2Maybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4565	{
4566	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4567	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4568	* cpus. Need to be explored and verify K7 presence. */
4569	/** @todo Undocument AMD debug control register \#2. */
4570	*puValue = 0;
4571	return VINF_SUCCESS;
4572	}
4573
4574
4575	/** @callback_method_impl{FNCPUMWRMSR} */
4576	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DebugCtl2Maybe(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4577	{
4578	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4579	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4580	* cpus. Need to be explored and verify K7 presence. */
4581	/** @todo Undocument AMD debug control register \#2. */
4582	return VINF_SUCCESS;
4583	}
4584
4585
4586	/** @callback_method_impl{FNCPUMRDMSR} */
4587	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hFpuCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4588	{
4589	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4590	/** @todo AMD FPU config. */
4591	*puValue = 0;
4592	return VINF_SUCCESS;
4593	}
4594
4595
4596	/** @callback_method_impl{FNCPUMWRMSR} */
4597	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hFpuCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4598	{
4599	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4600	/** @todo AMD FPU config. */
4601	return VINF_SUCCESS;
4602	}
4603
4604
4605	/** @callback_method_impl{FNCPUMRDMSR} */
4606	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hDecoderCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4607	{
4608	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4609	/** @todo AMD decoder config. */
4610	*puValue = 0;
4611	return VINF_SUCCESS;
4612	}
4613
4614
4615	/** @callback_method_impl{FNCPUMWRMSR} */
4616	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hDecoderCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4617	{
4618	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4619	/** @todo AMD decoder config. */
4620	return VINF_SUCCESS;
4621	}
4622
4623
4624	/** @callback_method_impl{FNCPUMRDMSR} */
4625	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hBusUnitCfg2(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4626	{
4627	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4628	/* Note! 10h and 16h */
4629	/** @todo AMD bus unit config. */
4630	*puValue = 0;
4631	return VINF_SUCCESS;
4632	}
4633
4634
4635	/** @callback_method_impl{FNCPUMWRMSR} */
4636	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hBusUnitCfg2(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4637	{
4638	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4639	/* Note! 10h and 16h */
4640	/** @todo AMD bus unit config. */
4641	return VINF_SUCCESS;
4642	}
4643
4644
4645	/** @callback_method_impl{FNCPUMRDMSR} */
4646	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hCombUnitCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4647	{
4648	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4649	/** @todo AMD unit config. */
4650	*puValue = 0;
4651	return VINF_SUCCESS;
4652	}
4653
4654
4655	/** @callback_method_impl{FNCPUMWRMSR} */
4656	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hCombUnitCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4657	{
4658	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4659	/** @todo AMD unit config. */
4660	return VINF_SUCCESS;
4661	}
4662
4663
4664	/** @callback_method_impl{FNCPUMRDMSR} */
4665	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hCombUnitCfg2(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4666	{
4667	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4668	/** @todo AMD unit config 2. */
4669	*puValue = 0;
4670	return VINF_SUCCESS;
4671	}
4672
4673
4674	/** @callback_method_impl{FNCPUMWRMSR} */
4675	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hCombUnitCfg2(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4676	{
4677	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4678	/** @todo AMD unit config 2. */
4679	return VINF_SUCCESS;
4680	}
4681
4682
4683	/** @callback_method_impl{FNCPUMRDMSR} */
4684	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hCombUnitCfg3(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4685	{
4686	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4687	/** @todo AMD combined unit config 3. */
4688	*puValue = 0;
4689	return VINF_SUCCESS;
4690	}
4691
4692
4693	/** @callback_method_impl{FNCPUMWRMSR} */
4694	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hCombUnitCfg3(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4695	{
4696	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4697	/** @todo AMD combined unit config 3. */
4698	return VINF_SUCCESS;
4699	}
4700
4701
4702	/** @callback_method_impl{FNCPUMRDMSR} */
4703	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hExecUnitCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4704	{
4705	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4706	/** @todo AMD execution unit config. */
4707	*puValue = 0;
4708	return VINF_SUCCESS;
4709	}
4710
4711
4712	/** @callback_method_impl{FNCPUMWRMSR} */
4713	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hExecUnitCfg(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4714	{
4715	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4716	/** @todo AMD execution unit config. */
4717	return VINF_SUCCESS;
4718	}
4719
4720
4721	/** @callback_method_impl{FNCPUMRDMSR} */
4722	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hLoadStoreCfg2(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4723	{
4724	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4725	/** @todo AMD load-store config 2. */
4726	*puValue = 0;
4727	return VINF_SUCCESS;
4728	}
4729
4730
4731	/** @callback_method_impl{FNCPUMWRMSR} */
4732	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hLoadStoreCfg2(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4733	{
4734	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4735	/** @todo AMD load-store config 2. */
4736	return VINF_SUCCESS;
4737	}
4738
4739
4740	/** @callback_method_impl{FNCPUMRDMSR} */
4741	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsFetchCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4742	{
4743	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4744	/** @todo AMD IBS. */
4745	*puValue = 0;
4746	return VINF_SUCCESS;
4747	}
4748
4749
4750	/** @callback_method_impl{FNCPUMWRMSR} */
4751	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsFetchCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4752	{
4753	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4754	/** @todo AMD IBS. */
4755	return VINF_SUCCESS;
4756	}
4757
4758
4759	/** @callback_method_impl{FNCPUMRDMSR} */
4760	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsFetchLinAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4761	{
4762	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4763	/** @todo AMD IBS. */
4764	*puValue = 0;
4765	return VINF_SUCCESS;
4766	}
4767
4768
4769	/** @callback_method_impl{FNCPUMWRMSR} */
4770	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsFetchLinAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4771	{
4772	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4773	/** @todo AMD IBS. */
4774	return VINF_SUCCESS;
4775	}
4776
4777
4778	/** @callback_method_impl{FNCPUMRDMSR} */
4779	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsFetchPhysAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4780	{
4781	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4782	/** @todo AMD IBS. */
4783	*puValue = 0;
4784	return VINF_SUCCESS;
4785	}
4786
4787
4788	/** @callback_method_impl{FNCPUMWRMSR} */
4789	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsFetchPhysAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4790	{
4791	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4792	/** @todo AMD IBS. */
4793	return VINF_SUCCESS;
4794	}
4795
4796
4797	/** @callback_method_impl{FNCPUMRDMSR} */
4798	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpExecCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4799	{
4800	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4801	/** @todo AMD IBS. */
4802	*puValue = 0;
4803	return VINF_SUCCESS;
4804	}
4805
4806
4807	/** @callback_method_impl{FNCPUMWRMSR} */
4808	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpExecCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4809	{
4810	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4811	/** @todo AMD IBS. */
4812	return VINF_SUCCESS;
4813	}
4814
4815
4816	/** @callback_method_impl{FNCPUMRDMSR} */
4817	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpRip(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4818	{
4819	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4820	/** @todo AMD IBS. */
4821	*puValue = 0;
4822	return VINF_SUCCESS;
4823	}
4824
4825
4826	/** @callback_method_impl{FNCPUMWRMSR} */
4827	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpRip(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4828	{
4829	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4830	/** @todo AMD IBS. */
4831	if (!X86_IS_CANONICAL(uValue))
4832	{
4833	Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
4834	return VERR_CPUM_RAISE_GP_0;
4835	}
4836	return VINF_SUCCESS;
4837	}
4838
4839
4840	/** @callback_method_impl{FNCPUMRDMSR} */
4841	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpData(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4842	{
4843	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4844	/** @todo AMD IBS. */
4845	*puValue = 0;
4846	return VINF_SUCCESS;
4847	}
4848
4849
4850	/** @callback_method_impl{FNCPUMWRMSR} */
4851	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpData(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4852	{
4853	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4854	/** @todo AMD IBS. */
4855	return VINF_SUCCESS;
4856	}
4857
4858
4859	/** @callback_method_impl{FNCPUMRDMSR} */
4860	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpData2(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4861	{
4862	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4863	/** @todo AMD IBS. */
4864	*puValue = 0;
4865	return VINF_SUCCESS;
4866	}
4867
4868
4869	/** @callback_method_impl{FNCPUMWRMSR} */
4870	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpData2(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4871	{
4872	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4873	/** @todo AMD IBS. */
4874	return VINF_SUCCESS;
4875	}
4876
4877
4878	/** @callback_method_impl{FNCPUMRDMSR} */
4879	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpData3(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4880	{
4881	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4882	/** @todo AMD IBS. */
4883	*puValue = 0;
4884	return VINF_SUCCESS;
4885	}
4886
4887
4888	/** @callback_method_impl{FNCPUMWRMSR} */
4889	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpData3(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4890	{
4891	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4892	/** @todo AMD IBS. */
4893	return VINF_SUCCESS;
4894	}
4895
4896
4897	/** @callback_method_impl{FNCPUMRDMSR} */
4898	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsDcLinAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4899	{
4900	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4901	/** @todo AMD IBS. */
4902	*puValue = 0;
4903	return VINF_SUCCESS;
4904	}
4905
4906
4907	/** @callback_method_impl{FNCPUMWRMSR} */
4908	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsDcLinAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4909	{
4910	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4911	/** @todo AMD IBS. */
4912	if (!X86_IS_CANONICAL(uValue))
4913	{
4914	Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
4915	return VERR_CPUM_RAISE_GP_0;
4916	}
4917	return VINF_SUCCESS;
4918	}
4919
4920
4921	/** @callback_method_impl{FNCPUMRDMSR} */
4922	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsDcPhysAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4923	{
4924	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4925	/** @todo AMD IBS. */
4926	*puValue = 0;
4927	return VINF_SUCCESS;
4928	}
4929
4930
4931	/** @callback_method_impl{FNCPUMWRMSR} */
4932	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsDcPhysAddr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4933	{
4934	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4935	/** @todo AMD IBS. */
4936	return VINF_SUCCESS;
4937	}
4938
4939
4940	/** @callback_method_impl{FNCPUMRDMSR} */
4941	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4942	{
4943	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4944	/** @todo AMD IBS. */
4945	*puValue = 0;
4946	return VINF_SUCCESS;
4947	}
4948
4949
4950	/** @callback_method_impl{FNCPUMWRMSR} */
4951	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsCtl(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4952	{
4953	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4954	/** @todo AMD IBS. */
4955	return VINF_SUCCESS;
4956	}
4957
4958
4959	/** @callback_method_impl{FNCPUMRDMSR} */
4960	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam14hIbsBrTarget(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4961	{
4962	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4963	/** @todo AMD IBS. */
4964	*puValue = 0;
4965	return VINF_SUCCESS;
4966	}
4967
4968
4969	/** @callback_method_impl{FNCPUMWRMSR} */
4970	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam14hIbsBrTarget(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4971	{
4972	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4973	/** @todo AMD IBS. */
4974	if (!X86_IS_CANONICAL(uValue))
4975	{
4976	Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
4977	return VERR_CPUM_RAISE_GP_0;
4978	}
4979	return VINF_SUCCESS;
4980	}
4981
4982
4983
4984	/*
4985	* GIM MSRs.
4986	* GIM MSRs.
4987	* GIM MSRs.
4988	*/
4989
4990
4991	/** @callback_method_impl{FNCPUMRDMSR} */
4992	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Gim(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4993	{
4994	#if defined(VBOX_WITH_NESTED_HWVIRT_SVM) \|\| defined(VBOX_WITH_NESTED_HWVIRT_VMX)
4995	/* Raise #GP(0) like a physical CPU would since the nested-hypervisor hasn't intercept these MSRs. */
4996	if ( CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.s.Guest)
4997	\|\| CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.s.Guest))
4998	return VERR_CPUM_RAISE_GP_0;
4999	#endif
5000	return GIMReadMsr(pVCpu, idMsr, pRange, puValue);
5001	}
5002
5003
5004	/** @callback_method_impl{FNCPUMWRMSR} */
5005	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Gim(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
5006	{
5007	#if defined(VBOX_WITH_NESTED_HWVIRT_SVM) \|\| defined(VBOX_WITH_NESTED_HWVIRT_VMX)
5008	/* Raise #GP(0) like a physical CPU would since the nested-hypervisor hasn't intercept these MSRs. */
5009	if ( CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.s.Guest)
5010	\|\| CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.s.Guest))
5011	return VERR_CPUM_RAISE_GP_0;
5012	#endif
5013	return GIMWriteMsr(pVCpu, idMsr, pRange, uValue, uRawValue);
5014	}
5015
5016
5017	/**
5018	* MSR read function table.
5019	*/
5020	static const struct READMSRCLANG11WEIRDNOTHROW { PFNCPUMRDMSR pfnRdMsr; } g_aCpumRdMsrFns[kCpumMsrRdFn_End] =
5021	{
5022	{ NULL }, /* Invalid */
5023	{ cpumMsrRd_FixedValue },
5024	{ NULL }, /* Alias */
5025	{ cpumMsrRd_WriteOnly },
5026	{ cpumMsrRd_Ia32P5McAddr },
5027	{ cpumMsrRd_Ia32P5McType },
5028	{ cpumMsrRd_Ia32TimestampCounter },
5029	{ cpumMsrRd_Ia32PlatformId },
5030	{ cpumMsrRd_Ia32ApicBase },
5031	{ cpumMsrRd_Ia32FeatureControl },
5032	{ cpumMsrRd_Ia32BiosSignId },
5033	{ cpumMsrRd_Ia32SmmMonitorCtl },
5034	{ cpumMsrRd_Ia32PmcN },
5035	{ cpumMsrRd_Ia32MonitorFilterLineSize },
5036	{ cpumMsrRd_Ia32MPerf },
5037	{ cpumMsrRd_Ia32APerf },
5038	{ cpumMsrRd_Ia32MtrrCap },
5039	{ cpumMsrRd_Ia32MtrrPhysBaseN },
5040	{ cpumMsrRd_Ia32MtrrPhysMaskN },
5041	{ cpumMsrRd_Ia32MtrrFixed },
5042	{ cpumMsrRd_Ia32MtrrDefType },
5043	{ cpumMsrRd_Ia32Pat },
5044	{ cpumMsrRd_Ia32SysEnterCs },
5045	{ cpumMsrRd_Ia32SysEnterEsp },
5046	{ cpumMsrRd_Ia32SysEnterEip },
5047	{ cpumMsrRd_Ia32McgCap },
5048	{ cpumMsrRd_Ia32McgStatus },
5049	{ cpumMsrRd_Ia32McgCtl },
5050	{ cpumMsrRd_Ia32DebugCtl },
5051	{ cpumMsrRd_Ia32SmrrPhysBase },
5052	{ cpumMsrRd_Ia32SmrrPhysMask },
5053	{ cpumMsrRd_Ia32PlatformDcaCap },
5054	{ cpumMsrRd_Ia32CpuDcaCap },
5055	{ cpumMsrRd_Ia32Dca0Cap },
5056	{ cpumMsrRd_Ia32PerfEvtSelN },
5057	{ cpumMsrRd_Ia32PerfStatus },
5058	{ cpumMsrRd_Ia32PerfCtl },
5059	{ cpumMsrRd_Ia32FixedCtrN },
5060	{ cpumMsrRd_Ia32PerfCapabilities },
5061	{ cpumMsrRd_Ia32FixedCtrCtrl },
5062	{ cpumMsrRd_Ia32PerfGlobalStatus },
5063	{ cpumMsrRd_Ia32PerfGlobalCtrl },
5064	{ cpumMsrRd_Ia32PerfGlobalOvfCtrl },
5065	{ cpumMsrRd_Ia32PebsEnable },
5066	{ cpumMsrRd_Ia32ClockModulation },
5067	{ cpumMsrRd_Ia32ThermInterrupt },
5068	{ cpumMsrRd_Ia32ThermStatus },
5069	{ cpumMsrRd_Ia32Therm2Ctl },
5070	{ cpumMsrRd_Ia32MiscEnable },
5071	{ cpumMsrRd_Ia32McCtlStatusAddrMiscN },
5072	{ cpumMsrRd_Ia32McNCtl2 },
5073	{ cpumMsrRd_Ia32DsArea },
5074	{ cpumMsrRd_Ia32TscDeadline },
5075	{ cpumMsrRd_Ia32X2ApicN },
5076	{ cpumMsrRd_Ia32DebugInterface },
5077	{ cpumMsrRd_Ia32VmxBasic },
5078	{ cpumMsrRd_Ia32VmxPinbasedCtls },
5079	{ cpumMsrRd_Ia32VmxProcbasedCtls },
5080	{ cpumMsrRd_Ia32VmxExitCtls },
5081	{ cpumMsrRd_Ia32VmxEntryCtls },
5082	{ cpumMsrRd_Ia32VmxMisc },
5083	{ cpumMsrRd_Ia32VmxCr0Fixed0 },
5084	{ cpumMsrRd_Ia32VmxCr0Fixed1 },
5085	{ cpumMsrRd_Ia32VmxCr4Fixed0 },
5086	{ cpumMsrRd_Ia32VmxCr4Fixed1 },
5087	{ cpumMsrRd_Ia32VmxVmcsEnum },
5088	{ cpumMsrRd_Ia32VmxProcBasedCtls2 },
5089	{ cpumMsrRd_Ia32VmxEptVpidCap },
5090	{ cpumMsrRd_Ia32VmxTruePinbasedCtls },
5091	{ cpumMsrRd_Ia32VmxTrueProcbasedCtls },
5092	{ cpumMsrRd_Ia32VmxTrueExitCtls },
5093	{ cpumMsrRd_Ia32VmxTrueEntryCtls },
5094	{ cpumMsrRd_Ia32VmxVmFunc },
5095	{ cpumMsrRd_Ia32SpecCtrl },
5096	{ cpumMsrRd_Ia32ArchCapabilities },
5097
5098	{ cpumMsrRd_Amd64Efer },
5099	{ cpumMsrRd_Amd64SyscallTarget },
5100	{ cpumMsrRd_Amd64LongSyscallTarget },
5101	{ cpumMsrRd_Amd64CompSyscallTarget },
5102	{ cpumMsrRd_Amd64SyscallFlagMask },
5103	{ cpumMsrRd_Amd64FsBase },
5104	{ cpumMsrRd_Amd64GsBase },
5105	{ cpumMsrRd_Amd64KernelGsBase },
5106	{ cpumMsrRd_Amd64TscAux },
5107
5108	{ cpumMsrRd_IntelEblCrPowerOn },
5109	{ cpumMsrRd_IntelI7CoreThreadCount },
5110	{ cpumMsrRd_IntelP4EbcHardPowerOn },
5111	{ cpumMsrRd_IntelP4EbcSoftPowerOn },
5112	{ cpumMsrRd_IntelP4EbcFrequencyId },
5113	{ cpumMsrRd_IntelP6FsbFrequency },
5114	{ cpumMsrRd_IntelPlatformInfo },
5115	{ cpumMsrRd_IntelFlexRatio },
5116	{ cpumMsrRd_IntelPkgCStConfigControl },
5117	{ cpumMsrRd_IntelPmgIoCaptureBase },
5118	{ cpumMsrRd_IntelLastBranchFromToN },
5119	{ cpumMsrRd_IntelLastBranchFromN },
5120	{ cpumMsrRd_IntelLastBranchToN },
5121	{ cpumMsrRd_IntelLastBranchTos },
5122	{ cpumMsrRd_IntelBblCrCtl },
5123	{ cpumMsrRd_IntelBblCrCtl3 },
5124	{ cpumMsrRd_IntelI7TemperatureTarget },
5125	{ cpumMsrRd_IntelI7MsrOffCoreResponseN },
5126	{ cpumMsrRd_IntelI7MiscPwrMgmt },
5127	{ cpumMsrRd_IntelP6CrN },
5128	{ cpumMsrRd_IntelCpuId1FeatureMaskEcdx },
5129	{ cpumMsrRd_IntelCpuId1FeatureMaskEax },
5130	{ cpumMsrRd_IntelCpuId80000001FeatureMaskEcdx },
5131	{ cpumMsrRd_IntelI7SandyAesNiCtl },
5132	{ cpumMsrRd_IntelI7TurboRatioLimit },
5133	{ cpumMsrRd_IntelI7LbrSelect },
5134	{ cpumMsrRd_IntelI7SandyErrorControl },
5135	{ cpumMsrRd_IntelI7VirtualLegacyWireCap },
5136	{ cpumMsrRd_IntelI7PowerCtl },
5137	{ cpumMsrRd_IntelI7SandyPebsNumAlt },
5138	{ cpumMsrRd_IntelI7PebsLdLat },
5139	{ cpumMsrRd_IntelI7PkgCnResidencyN },
5140	{ cpumMsrRd_IntelI7CoreCnResidencyN },
5141	{ cpumMsrRd_IntelI7SandyVrCurrentConfig },
5142	{ cpumMsrRd_IntelI7SandyVrMiscConfig },
5143	{ cpumMsrRd_IntelI7SandyRaplPowerUnit },
5144	{ cpumMsrRd_IntelI7SandyPkgCnIrtlN },
5145	{ cpumMsrRd_IntelI7SandyPkgC2Residency },
5146	{ cpumMsrRd_IntelI7RaplPkgPowerLimit },
5147	{ cpumMsrRd_IntelI7RaplPkgEnergyStatus },
5148	{ cpumMsrRd_IntelI7RaplPkgPerfStatus },
5149	{ cpumMsrRd_IntelI7RaplPkgPowerInfo },
5150	{ cpumMsrRd_IntelI7RaplDramPowerLimit },
5151	{ cpumMsrRd_IntelI7RaplDramEnergyStatus },
5152	{ cpumMsrRd_IntelI7RaplDramPerfStatus },
5153	{ cpumMsrRd_IntelI7RaplDramPowerInfo },
5154	{ cpumMsrRd_IntelI7RaplPp0PowerLimit },
5155	{ cpumMsrRd_IntelI7RaplPp0EnergyStatus },
5156	{ cpumMsrRd_IntelI7RaplPp0Policy },
5157	{ cpumMsrRd_IntelI7RaplPp0PerfStatus },
5158	{ cpumMsrRd_IntelI7RaplPp1PowerLimit },
5159	{ cpumMsrRd_IntelI7RaplPp1EnergyStatus },
5160	{ cpumMsrRd_IntelI7RaplPp1Policy },
5161	{ cpumMsrRd_IntelI7IvyConfigTdpNominal },
5162	{ cpumMsrRd_IntelI7IvyConfigTdpLevel1 },
5163	{ cpumMsrRd_IntelI7IvyConfigTdpLevel2 },
5164	{ cpumMsrRd_IntelI7IvyConfigTdpControl },
5165	{ cpumMsrRd_IntelI7IvyTurboActivationRatio },
5166	{ cpumMsrRd_IntelI7UncPerfGlobalCtrl },
5167	{ cpumMsrRd_IntelI7UncPerfGlobalStatus },
5168	{ cpumMsrRd_IntelI7UncPerfGlobalOvfCtrl },
5169	{ cpumMsrRd_IntelI7UncPerfFixedCtrCtrl },
5170	{ cpumMsrRd_IntelI7UncPerfFixedCtr },
5171	{ cpumMsrRd_IntelI7UncCBoxConfig },
5172	{ cpumMsrRd_IntelI7UncArbPerfCtrN },
5173	{ cpumMsrRd_IntelI7UncArbPerfEvtSelN },
5174	{ cpumMsrRd_IntelI7SmiCount },
5175	{ cpumMsrRd_IntelCore2EmttmCrTablesN },
5176	{ cpumMsrRd_IntelCore2SmmCStMiscInfo },
5177	{ cpumMsrRd_IntelCore1ExtConfig },
5178	{ cpumMsrRd_IntelCore1DtsCalControl },
5179	{ cpumMsrRd_IntelCore2PeciControl },
5180	{ cpumMsrRd_IntelAtSilvCoreC1Recidency },
5181
5182	{ cpumMsrRd_P6LastBranchFromIp },
5183	{ cpumMsrRd_P6LastBranchToIp },
5184	{ cpumMsrRd_P6LastIntFromIp },
5185	{ cpumMsrRd_P6LastIntToIp },
5186
5187	{ cpumMsrRd_AmdFam15hTscRate },
5188	{ cpumMsrRd_AmdFam15hLwpCfg },
5189	{ cpumMsrRd_AmdFam15hLwpCbAddr },
5190	{ cpumMsrRd_AmdFam10hMc4MiscN },
5191	{ cpumMsrRd_AmdK8PerfCtlN },
5192	{ cpumMsrRd_AmdK8PerfCtrN },
5193	{ cpumMsrRd_AmdK8SysCfg },
5194	{ cpumMsrRd_AmdK8HwCr },
5195	{ cpumMsrRd_AmdK8IorrBaseN },
5196	{ cpumMsrRd_AmdK8IorrMaskN },
5197	{ cpumMsrRd_AmdK8TopOfMemN },
5198	{ cpumMsrRd_AmdK8NbCfg1 },
5199	{ cpumMsrRd_AmdK8McXcptRedir },
5200	{ cpumMsrRd_AmdK8CpuNameN },
5201	{ cpumMsrRd_AmdK8HwThermalCtrl },
5202	{ cpumMsrRd_AmdK8SwThermalCtrl },
5203	{ cpumMsrRd_AmdK8FidVidControl },
5204	{ cpumMsrRd_AmdK8FidVidStatus },
5205	{ cpumMsrRd_AmdK8McCtlMaskN },
5206	{ cpumMsrRd_AmdK8SmiOnIoTrapN },
5207	{ cpumMsrRd_AmdK8SmiOnIoTrapCtlSts },
5208	{ cpumMsrRd_AmdK8IntPendingMessage },
5209	{ cpumMsrRd_AmdK8SmiTriggerIoCycle },
5210	{ cpumMsrRd_AmdFam10hMmioCfgBaseAddr },
5211	{ cpumMsrRd_AmdFam10hTrapCtlMaybe },
5212	{ cpumMsrRd_AmdFam10hPStateCurLimit },
5213	{ cpumMsrRd_AmdFam10hPStateControl },
5214	{ cpumMsrRd_AmdFam10hPStateStatus },
5215	{ cpumMsrRd_AmdFam10hPStateN },
5216	{ cpumMsrRd_AmdFam10hCofVidControl },
5217	{ cpumMsrRd_AmdFam10hCofVidStatus },
5218	{ cpumMsrRd_AmdFam10hCStateIoBaseAddr },
5219	{ cpumMsrRd_AmdFam10hCpuWatchdogTimer },
5220	{ cpumMsrRd_AmdK8SmmBase },
5221	{ cpumMsrRd_AmdK8SmmAddr },
5222	{ cpumMsrRd_AmdK8SmmMask },
5223	{ cpumMsrRd_AmdK8VmCr },
5224	{ cpumMsrRd_AmdK8IgnNe },
5225	{ cpumMsrRd_AmdK8SmmCtl },
5226	{ cpumMsrRd_AmdK8VmHSavePa },
5227	{ cpumMsrRd_AmdFam10hVmLockKey },
5228	{ cpumMsrRd_AmdFam10hSmmLockKey },
5229	{ cpumMsrRd_AmdFam10hLocalSmiStatus },
5230	{ cpumMsrRd_AmdFam10hOsVisWrkIdLength },
5231	{ cpumMsrRd_AmdFam10hOsVisWrkStatus },
5232	{ cpumMsrRd_AmdFam16hL2IPerfCtlN },
5233	{ cpumMsrRd_AmdFam16hL2IPerfCtrN },
5234	{ cpumMsrRd_AmdFam15hNorthbridgePerfCtlN },
5235	{ cpumMsrRd_AmdFam15hNorthbridgePerfCtrN },
5236	{ cpumMsrRd_AmdK7MicrocodeCtl },
5237	{ cpumMsrRd_AmdK7ClusterIdMaybe },
5238	{ cpumMsrRd_AmdK8CpuIdCtlStd07hEbax },
5239	{ cpumMsrRd_AmdK8CpuIdCtlStd06hEcx },
5240	{ cpumMsrRd_AmdK8CpuIdCtlStd01hEdcx },
5241	{ cpumMsrRd_AmdK8CpuIdCtlExt01hEdcx },
5242	{ cpumMsrRd_AmdK8PatchLevel },
5243	{ cpumMsrRd_AmdK7DebugStatusMaybe },
5244	{ cpumMsrRd_AmdK7BHTraceBaseMaybe },
5245	{ cpumMsrRd_AmdK7BHTracePtrMaybe },
5246	{ cpumMsrRd_AmdK7BHTraceLimitMaybe },
5247	{ cpumMsrRd_AmdK7HardwareDebugToolCfgMaybe },
5248	{ cpumMsrRd_AmdK7FastFlushCountMaybe },
5249	{ cpumMsrRd_AmdK7NodeId },
5250	{ cpumMsrRd_AmdK7DrXAddrMaskN },
5251	{ cpumMsrRd_AmdK7Dr0DataMatchMaybe },
5252	{ cpumMsrRd_AmdK7Dr0DataMaskMaybe },
5253	{ cpumMsrRd_AmdK7LoadStoreCfg },
5254	{ cpumMsrRd_AmdK7InstrCacheCfg },
5255	{ cpumMsrRd_AmdK7DataCacheCfg },
5256	{ cpumMsrRd_AmdK7BusUnitCfg },
5257	{ cpumMsrRd_AmdK7DebugCtl2Maybe },
5258	{ cpumMsrRd_AmdFam15hFpuCfg },
5259	{ cpumMsrRd_AmdFam15hDecoderCfg },
5260	{ cpumMsrRd_AmdFam10hBusUnitCfg2 },
5261	{ cpumMsrRd_AmdFam15hCombUnitCfg },
5262	{ cpumMsrRd_AmdFam15hCombUnitCfg2 },
5263	{ cpumMsrRd_AmdFam15hCombUnitCfg3 },
5264	{ cpumMsrRd_AmdFam15hExecUnitCfg },
5265	{ cpumMsrRd_AmdFam15hLoadStoreCfg2 },
5266	{ cpumMsrRd_AmdFam10hIbsFetchCtl },
5267	{ cpumMsrRd_AmdFam10hIbsFetchLinAddr },
5268	{ cpumMsrRd_AmdFam10hIbsFetchPhysAddr },
5269	{ cpumMsrRd_AmdFam10hIbsOpExecCtl },
5270	{ cpumMsrRd_AmdFam10hIbsOpRip },
5271	{ cpumMsrRd_AmdFam10hIbsOpData },
5272	{ cpumMsrRd_AmdFam10hIbsOpData2 },
5273	{ cpumMsrRd_AmdFam10hIbsOpData3 },
5274	{ cpumMsrRd_AmdFam10hIbsDcLinAddr },
5275	{ cpumMsrRd_AmdFam10hIbsDcPhysAddr },
5276	{ cpumMsrRd_AmdFam10hIbsCtl },
5277	{ cpumMsrRd_AmdFam14hIbsBrTarget },
5278
5279	{ cpumMsrRd_Gim },
5280	};
5281
5282
5283	/**
5284	* MSR write function table.
5285	*/
5286	static const struct WRITEMSRCLANG11WEIRDNOTHROW { PFNCPUMWRMSR pfnWrMsr; } g_aCpumWrMsrFns[kCpumMsrWrFn_End] =
5287	{
5288	{ NULL }, /* Invalid */
5289	{ cpumMsrWr_IgnoreWrite },
5290	{ cpumMsrWr_ReadOnly },
5291	{ NULL }, /* Alias */
5292	{ cpumMsrWr_Ia32P5McAddr },
5293	{ cpumMsrWr_Ia32P5McType },
5294	{ cpumMsrWr_Ia32TimestampCounter },
5295	{ cpumMsrWr_Ia32ApicBase },
5296	{ cpumMsrWr_Ia32FeatureControl },
5297	{ cpumMsrWr_Ia32BiosSignId },
5298	{ cpumMsrWr_Ia32BiosUpdateTrigger },
5299	{ cpumMsrWr_Ia32SmmMonitorCtl },
5300	{ cpumMsrWr_Ia32PmcN },
5301	{ cpumMsrWr_Ia32MonitorFilterLineSize },
5302	{ cpumMsrWr_Ia32MPerf },
5303	{ cpumMsrWr_Ia32APerf },
5304	{ cpumMsrWr_Ia32MtrrPhysBaseN },
5305	{ cpumMsrWr_Ia32MtrrPhysMaskN },
5306	{ cpumMsrWr_Ia32MtrrFixed },
5307	{ cpumMsrWr_Ia32MtrrDefType },
5308	{ cpumMsrWr_Ia32Pat },
5309	{ cpumMsrWr_Ia32SysEnterCs },
5310	{ cpumMsrWr_Ia32SysEnterEsp },
5311	{ cpumMsrWr_Ia32SysEnterEip },
5312	{ cpumMsrWr_Ia32McgStatus },
5313	{ cpumMsrWr_Ia32McgCtl },
5314	{ cpumMsrWr_Ia32DebugCtl },
5315	{ cpumMsrWr_Ia32SmrrPhysBase },
5316	{ cpumMsrWr_Ia32SmrrPhysMask },
5317	{ cpumMsrWr_Ia32PlatformDcaCap },
5318	{ cpumMsrWr_Ia32Dca0Cap },
5319	{ cpumMsrWr_Ia32PerfEvtSelN },
5320	{ cpumMsrWr_Ia32PerfStatus },
5321	{ cpumMsrWr_Ia32PerfCtl },
5322	{ cpumMsrWr_Ia32FixedCtrN },
5323	{ cpumMsrWr_Ia32PerfCapabilities },
5324	{ cpumMsrWr_Ia32FixedCtrCtrl },
5325	{ cpumMsrWr_Ia32PerfGlobalStatus },
5326	{ cpumMsrWr_Ia32PerfGlobalCtrl },
5327	{ cpumMsrWr_Ia32PerfGlobalOvfCtrl },
5328	{ cpumMsrWr_Ia32PebsEnable },
5329	{ cpumMsrWr_Ia32ClockModulation },
5330	{ cpumMsrWr_Ia32ThermInterrupt },
5331	{ cpumMsrWr_Ia32ThermStatus },
5332	{ cpumMsrWr_Ia32Therm2Ctl },
5333	{ cpumMsrWr_Ia32MiscEnable },
5334	{ cpumMsrWr_Ia32McCtlStatusAddrMiscN },
5335	{ cpumMsrWr_Ia32McNCtl2 },
5336	{ cpumMsrWr_Ia32DsArea },
5337	{ cpumMsrWr_Ia32TscDeadline },
5338	{ cpumMsrWr_Ia32X2ApicN },
5339	{ cpumMsrWr_Ia32DebugInterface },
5340	{ cpumMsrWr_Ia32SpecCtrl },
5341	{ cpumMsrWr_Ia32PredCmd },
5342	{ cpumMsrWr_Ia32FlushCmd },
5343
5344	{ cpumMsrWr_Amd64Efer },
5345	{ cpumMsrWr_Amd64SyscallTarget },
5346	{ cpumMsrWr_Amd64LongSyscallTarget },
5347	{ cpumMsrWr_Amd64CompSyscallTarget },
5348	{ cpumMsrWr_Amd64SyscallFlagMask },
5349	{ cpumMsrWr_Amd64FsBase },
5350	{ cpumMsrWr_Amd64GsBase },
5351	{ cpumMsrWr_Amd64KernelGsBase },
5352	{ cpumMsrWr_Amd64TscAux },
5353
5354	{ cpumMsrWr_IntelEblCrPowerOn },
5355	{ cpumMsrWr_IntelP4EbcHardPowerOn },
5356	{ cpumMsrWr_IntelP4EbcSoftPowerOn },
5357	{ cpumMsrWr_IntelP4EbcFrequencyId },
5358	{ cpumMsrWr_IntelFlexRatio },
5359	{ cpumMsrWr_IntelPkgCStConfigControl },
5360	{ cpumMsrWr_IntelPmgIoCaptureBase },
5361	{ cpumMsrWr_IntelLastBranchFromToN },
5362	{ cpumMsrWr_IntelLastBranchFromN },
5363	{ cpumMsrWr_IntelLastBranchToN },
5364	{ cpumMsrWr_IntelLastBranchTos },
5365	{ cpumMsrWr_IntelBblCrCtl },
5366	{ cpumMsrWr_IntelBblCrCtl3 },
5367	{ cpumMsrWr_IntelI7TemperatureTarget },
5368	{ cpumMsrWr_IntelI7MsrOffCoreResponseN },
5369	{ cpumMsrWr_IntelI7MiscPwrMgmt },
5370	{ cpumMsrWr_IntelP6CrN },
5371	{ cpumMsrWr_IntelCpuId1FeatureMaskEcdx },
5372	{ cpumMsrWr_IntelCpuId1FeatureMaskEax },
5373	{ cpumMsrWr_IntelCpuId80000001FeatureMaskEcdx },
5374	{ cpumMsrWr_IntelI7SandyAesNiCtl },
5375	{ cpumMsrWr_IntelI7TurboRatioLimit },
5376	{ cpumMsrWr_IntelI7LbrSelect },
5377	{ cpumMsrWr_IntelI7SandyErrorControl },
5378	{ cpumMsrWr_IntelI7PowerCtl },
5379	{ cpumMsrWr_IntelI7SandyPebsNumAlt },
5380	{ cpumMsrWr_IntelI7PebsLdLat },
5381	{ cpumMsrWr_IntelI7SandyVrCurrentConfig },
5382	{ cpumMsrWr_IntelI7SandyVrMiscConfig },
5383	{ cpumMsrWr_IntelI7SandyRaplPowerUnit },
5384	{ cpumMsrWr_IntelI7SandyPkgCnIrtlN },
5385	{ cpumMsrWr_IntelI7SandyPkgC2Residency },
5386	{ cpumMsrWr_IntelI7RaplPkgPowerLimit },
5387	{ cpumMsrWr_IntelI7RaplDramPowerLimit },
5388	{ cpumMsrWr_IntelI7RaplPp0PowerLimit },
5389	{ cpumMsrWr_IntelI7RaplPp0Policy },
5390	{ cpumMsrWr_IntelI7RaplPp1PowerLimit },
5391	{ cpumMsrWr_IntelI7RaplPp1Policy },
5392	{ cpumMsrWr_IntelI7IvyConfigTdpControl },
5393	{ cpumMsrWr_IntelI7IvyTurboActivationRatio },
5394	{ cpumMsrWr_IntelI7UncPerfGlobalCtrl },
5395	{ cpumMsrWr_IntelI7UncPerfGlobalStatus },
5396	{ cpumMsrWr_IntelI7UncPerfGlobalOvfCtrl },
5397	{ cpumMsrWr_IntelI7UncPerfFixedCtrCtrl },
5398	{ cpumMsrWr_IntelI7UncPerfFixedCtr },
5399	{ cpumMsrWr_IntelI7UncArbPerfCtrN },
5400	{ cpumMsrWr_IntelI7UncArbPerfEvtSelN },
5401	{ cpumMsrWr_IntelCore2EmttmCrTablesN },
5402	{ cpumMsrWr_IntelCore2SmmCStMiscInfo },
5403	{ cpumMsrWr_IntelCore1ExtConfig },
5404	{ cpumMsrWr_IntelCore1DtsCalControl },
5405	{ cpumMsrWr_IntelCore2PeciControl },
5406
5407	{ cpumMsrWr_P6LastIntFromIp },
5408	{ cpumMsrWr_P6LastIntToIp },
5409
5410	{ cpumMsrWr_AmdFam15hTscRate },
5411	{ cpumMsrWr_AmdFam15hLwpCfg },
5412	{ cpumMsrWr_AmdFam15hLwpCbAddr },
5413	{ cpumMsrWr_AmdFam10hMc4MiscN },
5414	{ cpumMsrWr_AmdK8PerfCtlN },
5415	{ cpumMsrWr_AmdK8PerfCtrN },
5416	{ cpumMsrWr_AmdK8SysCfg },
5417	{ cpumMsrWr_AmdK8HwCr },
5418	{ cpumMsrWr_AmdK8IorrBaseN },
5419	{ cpumMsrWr_AmdK8IorrMaskN },
5420	{ cpumMsrWr_AmdK8TopOfMemN },
5421	{ cpumMsrWr_AmdK8NbCfg1 },
5422	{ cpumMsrWr_AmdK8McXcptRedir },
5423	{ cpumMsrWr_AmdK8CpuNameN },
5424	{ cpumMsrWr_AmdK8HwThermalCtrl },
5425	{ cpumMsrWr_AmdK8SwThermalCtrl },
5426	{ cpumMsrWr_AmdK8FidVidControl },
5427	{ cpumMsrWr_AmdK8McCtlMaskN },
5428	{ cpumMsrWr_AmdK8SmiOnIoTrapN },
5429	{ cpumMsrWr_AmdK8SmiOnIoTrapCtlSts },
5430	{ cpumMsrWr_AmdK8IntPendingMessage },
5431	{ cpumMsrWr_AmdK8SmiTriggerIoCycle },
5432	{ cpumMsrWr_AmdFam10hMmioCfgBaseAddr },
5433	{ cpumMsrWr_AmdFam10hTrapCtlMaybe },
5434	{ cpumMsrWr_AmdFam10hPStateControl },
5435	{ cpumMsrWr_AmdFam10hPStateStatus },
5436	{ cpumMsrWr_AmdFam10hPStateN },
5437	{ cpumMsrWr_AmdFam10hCofVidControl },
5438	{ cpumMsrWr_AmdFam10hCofVidStatus },
5439	{ cpumMsrWr_AmdFam10hCStateIoBaseAddr },
5440	{ cpumMsrWr_AmdFam10hCpuWatchdogTimer },
5441	{ cpumMsrWr_AmdK8SmmBase },
5442	{ cpumMsrWr_AmdK8SmmAddr },
5443	{ cpumMsrWr_AmdK8SmmMask },
5444	{ cpumMsrWr_AmdK8VmCr },
5445	{ cpumMsrWr_AmdK8IgnNe },
5446	{ cpumMsrWr_AmdK8SmmCtl },
5447	{ cpumMsrWr_AmdK8VmHSavePa },
5448	{ cpumMsrWr_AmdFam10hVmLockKey },
5449	{ cpumMsrWr_AmdFam10hSmmLockKey },
5450	{ cpumMsrWr_AmdFam10hLocalSmiStatus },
5451	{ cpumMsrWr_AmdFam10hOsVisWrkIdLength },
5452	{ cpumMsrWr_AmdFam10hOsVisWrkStatus },
5453	{ cpumMsrWr_AmdFam16hL2IPerfCtlN },
5454	{ cpumMsrWr_AmdFam16hL2IPerfCtrN },
5455	{ cpumMsrWr_AmdFam15hNorthbridgePerfCtlN },
5456	{ cpumMsrWr_AmdFam15hNorthbridgePerfCtrN },
5457	{ cpumMsrWr_AmdK7MicrocodeCtl },
5458	{ cpumMsrWr_AmdK7ClusterIdMaybe },
5459	{ cpumMsrWr_AmdK8CpuIdCtlStd07hEbax },
5460	{ cpumMsrWr_AmdK8CpuIdCtlStd06hEcx },
5461	{ cpumMsrWr_AmdK8CpuIdCtlStd01hEdcx },
5462	{ cpumMsrWr_AmdK8CpuIdCtlExt01hEdcx },
5463	{ cpumMsrWr_AmdK8PatchLoader },
5464	{ cpumMsrWr_AmdK7DebugStatusMaybe },
5465	{ cpumMsrWr_AmdK7BHTraceBaseMaybe },
5466	{ cpumMsrWr_AmdK7BHTracePtrMaybe },
5467	{ cpumMsrWr_AmdK7BHTraceLimitMaybe },
5468	{ cpumMsrWr_AmdK7HardwareDebugToolCfgMaybe },
5469	{ cpumMsrWr_AmdK7FastFlushCountMaybe },
5470	{ cpumMsrWr_AmdK7NodeId },
5471	{ cpumMsrWr_AmdK7DrXAddrMaskN },
5472	{ cpumMsrWr_AmdK7Dr0DataMatchMaybe },
5473	{ cpumMsrWr_AmdK7Dr0DataMaskMaybe },
5474	{ cpumMsrWr_AmdK7LoadStoreCfg },
5475	{ cpumMsrWr_AmdK7InstrCacheCfg },
5476	{ cpumMsrWr_AmdK7DataCacheCfg },
5477	{ cpumMsrWr_AmdK7BusUnitCfg },
5478	{ cpumMsrWr_AmdK7DebugCtl2Maybe },
5479	{ cpumMsrWr_AmdFam15hFpuCfg },
5480	{ cpumMsrWr_AmdFam15hDecoderCfg },
5481	{ cpumMsrWr_AmdFam10hBusUnitCfg2 },
5482	{ cpumMsrWr_AmdFam15hCombUnitCfg },
5483	{ cpumMsrWr_AmdFam15hCombUnitCfg2 },
5484	{ cpumMsrWr_AmdFam15hCombUnitCfg3 },
5485	{ cpumMsrWr_AmdFam15hExecUnitCfg },
5486	{ cpumMsrWr_AmdFam15hLoadStoreCfg2 },
5487	{ cpumMsrWr_AmdFam10hIbsFetchCtl },
5488	{ cpumMsrWr_AmdFam10hIbsFetchLinAddr },
5489	{ cpumMsrWr_AmdFam10hIbsFetchPhysAddr },
5490	{ cpumMsrWr_AmdFam10hIbsOpExecCtl },
5491	{ cpumMsrWr_AmdFam10hIbsOpRip },
5492	{ cpumMsrWr_AmdFam10hIbsOpData },
5493	{ cpumMsrWr_AmdFam10hIbsOpData2 },
5494	{ cpumMsrWr_AmdFam10hIbsOpData3 },
5495	{ cpumMsrWr_AmdFam10hIbsDcLinAddr },
5496	{ cpumMsrWr_AmdFam10hIbsDcPhysAddr },
5497	{ cpumMsrWr_AmdFam10hIbsCtl },
5498	{ cpumMsrWr_AmdFam14hIbsBrTarget },
5499
5500	{ cpumMsrWr_Gim },
5501	};
5502
5503
5504	/**
5505	* Looks up the range for the given MSR.
5506	*
5507	* @returns Pointer to the range if found, NULL if not.
5508	* @param pVM The cross context VM structure.
5509	* @param idMsr The MSR to look up.
5510	*/
5511	# ifndef IN_RING3
5512	static
5513	# endif
5514	PCPUMMSRRANGE cpumLookupMsrRange(PVM pVM, uint32_t idMsr)
5515	{
5516	/*
5517	* Binary lookup.
5518	*/
5519	uint32_t cRanges = pVM->cpum.s.GuestInfo.cMsrRanges;
5520	if (!cRanges)
5521	return NULL;
5522	PCPUMMSRRANGE paRanges = pVM->cpum.s.GuestInfo.CTX_SUFF(paMsrRanges);
5523	for (;;)
5524	{
5525	uint32_t i = cRanges / 2;
5526	if (idMsr < paRanges[i].uFirst)
5527	{
5528	if (i == 0)
5529	break;
5530	cRanges = i;
5531	}
5532	else if (idMsr > paRanges[i].uLast)
5533	{
5534	i++;
5535	if (i >= cRanges)
5536	break;
5537	cRanges -= i;
5538	paRanges = &paRanges[i];
5539	}
5540	else
5541	{
5542	if (paRanges[i].enmRdFn == kCpumMsrRdFn_MsrAlias)
5543	return cpumLookupMsrRange(pVM, paRanges[i].uValue);
5544	return &paRanges[i];
5545	}
5546	}
5547
5548	# ifdef VBOX_STRICT
5549	/*
5550	* Linear lookup to verify the above binary search.
5551	*/
5552	uint32_t cLeft = pVM->cpum.s.GuestInfo.cMsrRanges;
5553	PCPUMMSRRANGE pCur = pVM->cpum.s.GuestInfo.CTX_SUFF(paMsrRanges);
5554	while (cLeft-- > 0)
5555	{
5556	if (idMsr >= pCur->uFirst && idMsr <= pCur->uLast)
5557	{
5558	AssertFailed();
5559	if (pCur->enmRdFn == kCpumMsrRdFn_MsrAlias)
5560	return cpumLookupMsrRange(pVM, pCur->uValue);
5561	return pCur;
5562	}
5563	pCur++;
5564	}
5565	# endif
5566	return NULL;
5567	}
5568
5569
5570	/**
5571	* Query a guest MSR.
5572	*
5573	* The caller is responsible for checking privilege if the call is the result of
5574	* a RDMSR instruction. We'll do the rest.
5575	*
5576	* @retval VINF_SUCCESS on success.
5577	* @retval VINF_CPUM_R3_MSR_READ if the MSR read could not be serviced in the
5578	* current context (raw-mode or ring-0).
5579	* @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR), the caller is
5580	* expected to take the appropriate actions. @a *puValue is set to 0.
5581	* @param pVCpu The cross context virtual CPU structure.
5582	* @param idMsr The MSR.
5583	* @param puValue Where to return the value.
5584	*
5585	* @remarks This will always return the right values, even when we're in the
5586	* recompiler.
5587	*/
5588	VMMDECL(VBOXSTRICTRC) CPUMQueryGuestMsr(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *puValue)
5589	{
5590	*puValue = 0;
5591
5592	VBOXSTRICTRC rcStrict;
5593	PVM pVM = pVCpu->CTX_SUFF(pVM);
5594	PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, idMsr);
5595	if (pRange)
5596	{
5597	CPUMMSRRDFN enmRdFn = (CPUMMSRRDFN)pRange->enmRdFn;
5598	AssertReturn(enmRdFn > kCpumMsrRdFn_Invalid && enmRdFn < kCpumMsrRdFn_End, VERR_CPUM_IPE_1);
5599
5600	PFNCPUMRDMSR pfnRdMsr = g_aCpumRdMsrFns[enmRdFn].pfnRdMsr;
5601	AssertReturn(pfnRdMsr, VERR_CPUM_IPE_2);
5602
5603	STAM_COUNTER_INC(&pRange->cReads);
5604	STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReads);
5605
5606	rcStrict = pfnRdMsr(pVCpu, idMsr, pRange, puValue);
5607	if (rcStrict == VINF_SUCCESS)
5608	Log2(("CPUM: RDMSR %#x (%s) -> %#llx\n", idMsr, pRange->szName, *puValue));
5609	else if (rcStrict == VERR_CPUM_RAISE_GP_0)
5610	{
5611	Log(("CPUM: RDMSR %#x (%s) -> #GP(0)\n", idMsr, pRange->szName));
5612	STAM_COUNTER_INC(&pRange->cGps);
5613	STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReadsRaiseGp);
5614	}
5615	#ifndef IN_RING3
5616	else if (rcStrict == VINF_CPUM_R3_MSR_READ)
5617	Log(("CPUM: RDMSR %#x (%s) -> ring-3\n", idMsr, pRange->szName));
5618	#endif
5619	else
5620	{
5621	Log(("CPUM: RDMSR %#x (%s) -> rcStrict=%Rrc\n", idMsr, pRange->szName, VBOXSTRICTRC_VAL(rcStrict)));
5622	AssertMsgStmt(RT_FAILURE_NP(rcStrict), ("%Rrc idMsr=%#x\n", VBOXSTRICTRC_VAL(rcStrict), idMsr),
5623	rcStrict = VERR_IPE_UNEXPECTED_INFO_STATUS);
5624	Assert(rcStrict != VERR_EM_INTERPRETER);
5625	}
5626	}
5627	else
5628	{
5629	Log(("CPUM: Unknown RDMSR %#x -> #GP(0)\n", idMsr));
5630	STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReads);
5631	STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReadsUnknown);
5632	rcStrict = VERR_CPUM_RAISE_GP_0;
5633	}
5634	return rcStrict;
5635	}
5636
5637
5638	/**
5639	* Writes to a guest MSR.
5640	*
5641	* The caller is responsible for checking privilege if the call is the result of
5642	* a WRMSR instruction. We'll do the rest.
5643	*
5644	* @retval VINF_SUCCESS on success.
5645	* @retval VINF_CPUM_R3_MSR_WRITE if the MSR write could not be serviced in the
5646	* current context (raw-mode or ring-0).
5647	* @retval VERR_CPUM_RAISE_GP_0 on failure, the caller is expected to take the
5648	* appropriate actions.
5649	*
5650	* @param pVCpu The cross context virtual CPU structure.
5651	* @param idMsr The MSR id.
5652	* @param uValue The value to set.
5653	*
5654	* @remarks Everyone changing MSR values, including the recompiler, shall do it
5655	* by calling this method. This makes sure we have current values and
5656	* that we trigger all the right actions when something changes.
5657	*
5658	* For performance reasons, this actually isn't entirely true for some
5659	* MSRs when in HM mode. The code here and in HM must be aware of
5660	* this.
5661	*/
5662	VMMDECL(VBOXSTRICTRC) CPUMSetGuestMsr(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t uValue)
5663	{
5664	VBOXSTRICTRC rcStrict;
5665	PVM pVM = pVCpu->CTX_SUFF(pVM);
5666	PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, idMsr);
5667	if (pRange)
5668	{
5669	STAM_COUNTER_INC(&pRange->cWrites);
5670	STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWrites);
5671
5672	if (!(uValue & pRange->fWrGpMask))
5673	{
5674	CPUMMSRWRFN enmWrFn = (CPUMMSRWRFN)pRange->enmWrFn;
5675	AssertReturn(enmWrFn > kCpumMsrWrFn_Invalid && enmWrFn < kCpumMsrWrFn_End, VERR_CPUM_IPE_1);
5676
5677	PFNCPUMWRMSR pfnWrMsr = g_aCpumWrMsrFns[enmWrFn].pfnWrMsr;
5678	AssertReturn(pfnWrMsr, VERR_CPUM_IPE_2);
5679
5680	uint64_t uValueAdjusted = uValue & ~pRange->fWrIgnMask;
5681	if (uValueAdjusted != uValue)
5682	{
5683	STAM_COUNTER_INC(&pRange->cIgnoredBits);
5684	STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesToIgnoredBits);
5685	}
5686
5687	rcStrict = pfnWrMsr(pVCpu, idMsr, pRange, uValueAdjusted, uValue);
5688	if (rcStrict == VINF_SUCCESS)
5689	Log2(("CPUM: WRMSR %#x (%s), %#llx [%#llx]\n", idMsr, pRange->szName, uValueAdjusted, uValue));
5690	else if (rcStrict == VERR_CPUM_RAISE_GP_0)
5691	{
5692	Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> #GP(0)\n", idMsr, pRange->szName, uValueAdjusted, uValue));
5693	STAM_COUNTER_INC(&pRange->cGps);
5694	STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesRaiseGp);
5695	}
5696	#ifndef IN_RING3
5697	else if (rcStrict == VINF_CPUM_R3_MSR_WRITE)
5698	Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> ring-3\n", idMsr, pRange->szName, uValueAdjusted, uValue));
5699	#endif
5700	else
5701	{
5702	Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> rcStrict=%Rrc\n",
5703	idMsr, pRange->szName, uValueAdjusted, uValue, VBOXSTRICTRC_VAL(rcStrict)));
5704	AssertMsgStmt(RT_FAILURE_NP(rcStrict), ("%Rrc idMsr=%#x\n", VBOXSTRICTRC_VAL(rcStrict), idMsr),
5705	rcStrict = VERR_IPE_UNEXPECTED_INFO_STATUS);
5706	Assert(rcStrict != VERR_EM_INTERPRETER);
5707	}
5708	}
5709	else
5710	{
5711	Log(("CPUM: WRMSR %#x (%s), %#llx -> #GP(0) - invalid bits %#llx\n",
5712	idMsr, pRange->szName, uValue, uValue & pRange->fWrGpMask));
5713	STAM_COUNTER_INC(&pRange->cGps);
5714	STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesRaiseGp);
5715	rcStrict = VERR_CPUM_RAISE_GP_0;
5716	}
5717	}
5718	else
5719	{
5720	Log(("CPUM: Unknown WRMSR %#x, %#llx -> #GP(0)\n", idMsr, uValue));
5721	STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWrites);
5722	STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesUnknown);
5723	rcStrict = VERR_CPUM_RAISE_GP_0;
5724	}
5725	return rcStrict;
5726	}
5727
5728
5729	#if defined(VBOX_STRICT) && defined(IN_RING3)
5730	/**
5731	* Performs some checks on the static data related to MSRs.
5732	*
5733	* @returns VINF_SUCCESS on success, error on failure.
5734	*/
5735	int cpumR3MsrStrictInitChecks(void)
5736	{
5737	#define CPUM_ASSERT_RD_MSR_FN(a_Register) \
5738	AssertReturn(g_aCpumRdMsrFns[kCpumMsrRdFn_##a_Register].pfnRdMsr == cpumMsrRd_##a_Register, VERR_CPUM_IPE_2);
5739	#define CPUM_ASSERT_WR_MSR_FN(a_Register) \
5740	AssertReturn(g_aCpumWrMsrFns[kCpumMsrWrFn_##a_Register].pfnWrMsr == cpumMsrWr_##a_Register, VERR_CPUM_IPE_2);
5741
5742	AssertReturn(g_aCpumRdMsrFns[kCpumMsrRdFn_Invalid].pfnRdMsr == NULL, VERR_CPUM_IPE_2);
5743	CPUM_ASSERT_RD_MSR_FN(FixedValue);
5744	CPUM_ASSERT_RD_MSR_FN(WriteOnly);
5745	CPUM_ASSERT_RD_MSR_FN(Ia32P5McAddr);
5746	CPUM_ASSERT_RD_MSR_FN(Ia32P5McType);
5747	CPUM_ASSERT_RD_MSR_FN(Ia32TimestampCounter);
5748	CPUM_ASSERT_RD_MSR_FN(Ia32PlatformId);
5749	CPUM_ASSERT_RD_MSR_FN(Ia32ApicBase);
5750	CPUM_ASSERT_RD_MSR_FN(Ia32FeatureControl);
5751	CPUM_ASSERT_RD_MSR_FN(Ia32BiosSignId);
5752	CPUM_ASSERT_RD_MSR_FN(Ia32SmmMonitorCtl);
5753	CPUM_ASSERT_RD_MSR_FN(Ia32PmcN);
5754	CPUM_ASSERT_RD_MSR_FN(Ia32MonitorFilterLineSize);
5755	CPUM_ASSERT_RD_MSR_FN(Ia32MPerf);
5756	CPUM_ASSERT_RD_MSR_FN(Ia32APerf);
5757	CPUM_ASSERT_RD_MSR_FN(Ia32MtrrCap);
5758	CPUM_ASSERT_RD_MSR_FN(Ia32MtrrPhysBaseN);
5759	CPUM_ASSERT_RD_MSR_FN(Ia32MtrrPhysMaskN);
5760	CPUM_ASSERT_RD_MSR_FN(Ia32MtrrFixed);
5761	CPUM_ASSERT_RD_MSR_FN(Ia32MtrrDefType);
5762	CPUM_ASSERT_RD_MSR_FN(Ia32Pat);
5763	CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterCs);
5764	CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterEsp);
5765	CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterEip);
5766	CPUM_ASSERT_RD_MSR_FN(Ia32McgCap);
5767	CPUM_ASSERT_RD_MSR_FN(Ia32McgStatus);
5768	CPUM_ASSERT_RD_MSR_FN(Ia32McgCtl);
5769	CPUM_ASSERT_RD_MSR_FN(Ia32DebugCtl);
5770	CPUM_ASSERT_RD_MSR_FN(Ia32SmrrPhysBase);
5771	CPUM_ASSERT_RD_MSR_FN(Ia32SmrrPhysMask);
5772	CPUM_ASSERT_RD_MSR_FN(Ia32PlatformDcaCap);
5773	CPUM_ASSERT_RD_MSR_FN(Ia32CpuDcaCap);
5774	CPUM_ASSERT_RD_MSR_FN(Ia32Dca0Cap);
5775	CPUM_ASSERT_RD_MSR_FN(Ia32PerfEvtSelN);
5776	CPUM_ASSERT_RD_MSR_FN(Ia32PerfStatus);
5777	CPUM_ASSERT_RD_MSR_FN(Ia32PerfCtl);
5778	CPUM_ASSERT_RD_MSR_FN(Ia32FixedCtrN);
5779	CPUM_ASSERT_RD_MSR_FN(Ia32PerfCapabilities);
5780	CPUM_ASSERT_RD_MSR_FN(Ia32FixedCtrCtrl);
5781	CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalStatus);
5782	CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalCtrl);
5783	CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalOvfCtrl);
5784	CPUM_ASSERT_RD_MSR_FN(Ia32PebsEnable);
5785	CPUM_ASSERT_RD_MSR_FN(Ia32ClockModulation);
5786	CPUM_ASSERT_RD_MSR_FN(Ia32ThermInterrupt);
5787	CPUM_ASSERT_RD_MSR_FN(Ia32ThermStatus);
5788	CPUM_ASSERT_RD_MSR_FN(Ia32MiscEnable);
5789	CPUM_ASSERT_RD_MSR_FN(Ia32McCtlStatusAddrMiscN);
5790	CPUM_ASSERT_RD_MSR_FN(Ia32McNCtl2);
5791	CPUM_ASSERT_RD_MSR_FN(Ia32DsArea);
5792	CPUM_ASSERT_RD_MSR_FN(Ia32TscDeadline);
5793	CPUM_ASSERT_RD_MSR_FN(Ia32X2ApicN);
5794	CPUM_ASSERT_RD_MSR_FN(Ia32DebugInterface);
5795	CPUM_ASSERT_RD_MSR_FN(Ia32VmxBasic);
5796	CPUM_ASSERT_RD_MSR_FN(Ia32VmxPinbasedCtls);
5797	CPUM_ASSERT_RD_MSR_FN(Ia32VmxProcbasedCtls);
5798	CPUM_ASSERT_RD_MSR_FN(Ia32VmxExitCtls);
5799	CPUM_ASSERT_RD_MSR_FN(Ia32VmxEntryCtls);
5800	CPUM_ASSERT_RD_MSR_FN(Ia32VmxMisc);
5801	CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr0Fixed0);
5802	CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr0Fixed1);
5803	CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr4Fixed0);
5804	CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr4Fixed1);
5805	CPUM_ASSERT_RD_MSR_FN(Ia32VmxVmcsEnum);
5806	CPUM_ASSERT_RD_MSR_FN(Ia32VmxProcBasedCtls2);
5807	CPUM_ASSERT_RD_MSR_FN(Ia32VmxEptVpidCap);
5808	CPUM_ASSERT_RD_MSR_FN(Ia32VmxTruePinbasedCtls);
5809	CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueProcbasedCtls);
5810	CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueExitCtls);
5811	CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueEntryCtls);
5812	CPUM_ASSERT_RD_MSR_FN(Ia32VmxVmFunc);
5813	CPUM_ASSERT_RD_MSR_FN(Ia32SpecCtrl);
5814	CPUM_ASSERT_RD_MSR_FN(Ia32ArchCapabilities);
5815
5816	CPUM_ASSERT_RD_MSR_FN(Amd64Efer);
5817	CPUM_ASSERT_RD_MSR_FN(Amd64SyscallTarget);
5818	CPUM_ASSERT_RD_MSR_FN(Amd64LongSyscallTarget);
5819	CPUM_ASSERT_RD_MSR_FN(Amd64CompSyscallTarget);
5820	CPUM_ASSERT_RD_MSR_FN(Amd64SyscallFlagMask);
5821	CPUM_ASSERT_RD_MSR_FN(Amd64FsBase);
5822	CPUM_ASSERT_RD_MSR_FN(Amd64GsBase);
5823	CPUM_ASSERT_RD_MSR_FN(Amd64KernelGsBase);
5824	CPUM_ASSERT_RD_MSR_FN(Amd64TscAux);
5825
5826	CPUM_ASSERT_RD_MSR_FN(IntelEblCrPowerOn);
5827	CPUM_ASSERT_RD_MSR_FN(IntelI7CoreThreadCount);
5828	CPUM_ASSERT_RD_MSR_FN(IntelP4EbcHardPowerOn);
5829	CPUM_ASSERT_RD_MSR_FN(IntelP4EbcSoftPowerOn);
5830	CPUM_ASSERT_RD_MSR_FN(IntelP4EbcFrequencyId);
5831	CPUM_ASSERT_RD_MSR_FN(IntelP6FsbFrequency);
5832	CPUM_ASSERT_RD_MSR_FN(IntelPlatformInfo);
5833	CPUM_ASSERT_RD_MSR_FN(IntelFlexRatio);
5834	CPUM_ASSERT_RD_MSR_FN(IntelPkgCStConfigControl);
5835	CPUM_ASSERT_RD_MSR_FN(IntelPmgIoCaptureBase);
5836	CPUM_ASSERT_RD_MSR_FN(IntelLastBranchFromToN);
5837	CPUM_ASSERT_RD_MSR_FN(IntelLastBranchFromN);
5838	CPUM_ASSERT_RD_MSR_FN(IntelLastBranchToN);
5839	CPUM_ASSERT_RD_MSR_FN(IntelLastBranchTos);
5840	CPUM_ASSERT_RD_MSR_FN(IntelBblCrCtl);
5841	CPUM_ASSERT_RD_MSR_FN(IntelBblCrCtl3);
5842	CPUM_ASSERT_RD_MSR_FN(IntelI7TemperatureTarget);
5843	CPUM_ASSERT_RD_MSR_FN(IntelI7MsrOffCoreResponseN);
5844	CPUM_ASSERT_RD_MSR_FN(IntelI7MiscPwrMgmt);
5845	CPUM_ASSERT_RD_MSR_FN(IntelP6CrN);
5846	CPUM_ASSERT_RD_MSR_FN(IntelCpuId1FeatureMaskEcdx);
5847	CPUM_ASSERT_RD_MSR_FN(IntelCpuId1FeatureMaskEax);
5848	CPUM_ASSERT_RD_MSR_FN(IntelCpuId80000001FeatureMaskEcdx);
5849	CPUM_ASSERT_RD_MSR_FN(IntelI7SandyAesNiCtl);
5850	CPUM_ASSERT_RD_MSR_FN(IntelI7TurboRatioLimit);
5851	CPUM_ASSERT_RD_MSR_FN(IntelI7LbrSelect);
5852	CPUM_ASSERT_RD_MSR_FN(IntelI7SandyErrorControl);
5853	CPUM_ASSERT_RD_MSR_FN(IntelI7VirtualLegacyWireCap);
5854	CPUM_ASSERT_RD_MSR_FN(IntelI7PowerCtl);
5855	CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPebsNumAlt);
5856	CPUM_ASSERT_RD_MSR_FN(IntelI7PebsLdLat);
5857	CPUM_ASSERT_RD_MSR_FN(IntelI7PkgCnResidencyN);
5858	CPUM_ASSERT_RD_MSR_FN(IntelI7CoreCnResidencyN);
5859	CPUM_ASSERT_RD_MSR_FN(IntelI7SandyVrCurrentConfig);
5860	CPUM_ASSERT_RD_MSR_FN(IntelI7SandyVrMiscConfig);
5861	CPUM_ASSERT_RD_MSR_FN(IntelI7SandyRaplPowerUnit);
5862	CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPkgCnIrtlN);
5863	CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPkgC2Residency);
5864	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPowerLimit);
5865	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgEnergyStatus);
5866	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPerfStatus);
5867	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPowerInfo);
5868	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPowerLimit);
5869	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramEnergyStatus);
5870	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPerfStatus);
5871	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPowerInfo);
5872	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0PowerLimit);
5873	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0EnergyStatus);
5874	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0Policy);
5875	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0PerfStatus);
5876	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1PowerLimit);
5877	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1EnergyStatus);
5878	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1Policy);
5879	CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpNominal);
5880	CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpLevel1);
5881	CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpLevel2);
5882	CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpControl);
5883	CPUM_ASSERT_RD_MSR_FN(IntelI7IvyTurboActivationRatio);
5884	CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalCtrl);
5885	CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalStatus);
5886	CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalOvfCtrl);
5887	CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfFixedCtrCtrl);
5888	CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfFixedCtr);
5889	CPUM_ASSERT_RD_MSR_FN(IntelI7UncCBoxConfig);
5890	CPUM_ASSERT_RD_MSR_FN(IntelI7UncArbPerfCtrN);
5891	CPUM_ASSERT_RD_MSR_FN(IntelI7UncArbPerfEvtSelN);
5892	CPUM_ASSERT_RD_MSR_FN(IntelI7SmiCount);
5893	CPUM_ASSERT_RD_MSR_FN(IntelCore2EmttmCrTablesN);
5894	CPUM_ASSERT_RD_MSR_FN(IntelCore2SmmCStMiscInfo);
5895	CPUM_ASSERT_RD_MSR_FN(IntelCore1ExtConfig);
5896	CPUM_ASSERT_RD_MSR_FN(IntelCore1DtsCalControl);
5897	CPUM_ASSERT_RD_MSR_FN(IntelCore2PeciControl);
5898	CPUM_ASSERT_RD_MSR_FN(IntelAtSilvCoreC1Recidency);
5899
5900	CPUM_ASSERT_RD_MSR_FN(P6LastBranchFromIp);
5901	CPUM_ASSERT_RD_MSR_FN(P6LastBranchToIp);
5902	CPUM_ASSERT_RD_MSR_FN(P6LastIntFromIp);
5903	CPUM_ASSERT_RD_MSR_FN(P6LastIntToIp);
5904
5905	CPUM_ASSERT_RD_MSR_FN(AmdFam15hTscRate);
5906	CPUM_ASSERT_RD_MSR_FN(AmdFam15hLwpCfg);
5907	CPUM_ASSERT_RD_MSR_FN(AmdFam15hLwpCbAddr);
5908	CPUM_ASSERT_RD_MSR_FN(AmdFam10hMc4MiscN);
5909	CPUM_ASSERT_RD_MSR_FN(AmdK8PerfCtlN);
5910	CPUM_ASSERT_RD_MSR_FN(AmdK8PerfCtrN);
5911	CPUM_ASSERT_RD_MSR_FN(AmdK8SysCfg);
5912	CPUM_ASSERT_RD_MSR_FN(AmdK8HwCr);
5913	CPUM_ASSERT_RD_MSR_FN(AmdK8IorrBaseN);
5914	CPUM_ASSERT_RD_MSR_FN(AmdK8IorrMaskN);
5915	CPUM_ASSERT_RD_MSR_FN(AmdK8TopOfMemN);
5916	CPUM_ASSERT_RD_MSR_FN(AmdK8NbCfg1);
5917	CPUM_ASSERT_RD_MSR_FN(AmdK8McXcptRedir);
5918	CPUM_ASSERT_RD_MSR_FN(AmdK8CpuNameN);
5919	CPUM_ASSERT_RD_MSR_FN(AmdK8HwThermalCtrl);
5920	CPUM_ASSERT_RD_MSR_FN(AmdK8SwThermalCtrl);
5921	CPUM_ASSERT_RD_MSR_FN(AmdK8FidVidControl);
5922	CPUM_ASSERT_RD_MSR_FN(AmdK8FidVidStatus);
5923	CPUM_ASSERT_RD_MSR_FN(AmdK8McCtlMaskN);
5924	CPUM_ASSERT_RD_MSR_FN(AmdK8SmiOnIoTrapN);
5925	CPUM_ASSERT_RD_MSR_FN(AmdK8SmiOnIoTrapCtlSts);
5926	CPUM_ASSERT_RD_MSR_FN(AmdK8IntPendingMessage);
5927	CPUM_ASSERT_RD_MSR_FN(AmdK8SmiTriggerIoCycle);
5928	CPUM_ASSERT_RD_MSR_FN(AmdFam10hMmioCfgBaseAddr);
5929	CPUM_ASSERT_RD_MSR_FN(AmdFam10hTrapCtlMaybe);
5930	CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateCurLimit);
5931	CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateControl);
5932	CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateStatus);
5933	CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateN);
5934	CPUM_ASSERT_RD_MSR_FN(AmdFam10hCofVidControl);
5935	CPUM_ASSERT_RD_MSR_FN(AmdFam10hCofVidStatus);
5936	CPUM_ASSERT_RD_MSR_FN(AmdFam10hCStateIoBaseAddr);
5937	CPUM_ASSERT_RD_MSR_FN(AmdFam10hCpuWatchdogTimer);
5938	CPUM_ASSERT_RD_MSR_FN(AmdK8SmmBase);
5939	CPUM_ASSERT_RD_MSR_FN(AmdK8SmmAddr);
5940	CPUM_ASSERT_RD_MSR_FN(AmdK8SmmMask);
5941	CPUM_ASSERT_RD_MSR_FN(AmdK8VmCr);
5942	CPUM_ASSERT_RD_MSR_FN(AmdK8IgnNe);
5943	CPUM_ASSERT_RD_MSR_FN(AmdK8SmmCtl);
5944	CPUM_ASSERT_RD_MSR_FN(AmdK8VmHSavePa);
5945	CPUM_ASSERT_RD_MSR_FN(AmdFam10hVmLockKey);
5946	CPUM_ASSERT_RD_MSR_FN(AmdFam10hSmmLockKey);
5947	CPUM_ASSERT_RD_MSR_FN(AmdFam10hLocalSmiStatus);
5948	CPUM_ASSERT_RD_MSR_FN(AmdFam10hOsVisWrkIdLength);
5949	CPUM_ASSERT_RD_MSR_FN(AmdFam10hOsVisWrkStatus);
5950	CPUM_ASSERT_RD_MSR_FN(AmdFam16hL2IPerfCtlN);
5951	CPUM_ASSERT_RD_MSR_FN(AmdFam16hL2IPerfCtrN);
5952	CPUM_ASSERT_RD_MSR_FN(AmdFam15hNorthbridgePerfCtlN);
5953	CPUM_ASSERT_RD_MSR_FN(AmdFam15hNorthbridgePerfCtrN);
5954	CPUM_ASSERT_RD_MSR_FN(AmdK7MicrocodeCtl);
5955	CPUM_ASSERT_RD_MSR_FN(AmdK7ClusterIdMaybe);
5956	CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd07hEbax);
5957	CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd06hEcx);
5958	CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd01hEdcx);
5959	CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlExt01hEdcx);
5960	CPUM_ASSERT_RD_MSR_FN(AmdK8PatchLevel);
5961	CPUM_ASSERT_RD_MSR_FN(AmdK7DebugStatusMaybe);
5962	CPUM_ASSERT_RD_MSR_FN(AmdK7BHTraceBaseMaybe);
5963	CPUM_ASSERT_RD_MSR_FN(AmdK7BHTracePtrMaybe);
5964	CPUM_ASSERT_RD_MSR_FN(AmdK7BHTraceLimitMaybe);
5965	CPUM_ASSERT_RD_MSR_FN(AmdK7HardwareDebugToolCfgMaybe);
5966	CPUM_ASSERT_RD_MSR_FN(AmdK7FastFlushCountMaybe);
5967	CPUM_ASSERT_RD_MSR_FN(AmdK7NodeId);
5968	CPUM_ASSERT_RD_MSR_FN(AmdK7DrXAddrMaskN);
5969	CPUM_ASSERT_RD_MSR_FN(AmdK7Dr0DataMatchMaybe);
5970	CPUM_ASSERT_RD_MSR_FN(AmdK7Dr0DataMaskMaybe);
5971	CPUM_ASSERT_RD_MSR_FN(AmdK7LoadStoreCfg);
5972	CPUM_ASSERT_RD_MSR_FN(AmdK7InstrCacheCfg);
5973	CPUM_ASSERT_RD_MSR_FN(AmdK7DataCacheCfg);
5974	CPUM_ASSERT_RD_MSR_FN(AmdK7BusUnitCfg);
5975	CPUM_ASSERT_RD_MSR_FN(AmdK7DebugCtl2Maybe);
5976	CPUM_ASSERT_RD_MSR_FN(AmdFam15hFpuCfg);
5977	CPUM_ASSERT_RD_MSR_FN(AmdFam15hDecoderCfg);
5978	CPUM_ASSERT_RD_MSR_FN(AmdFam10hBusUnitCfg2);
5979	CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg);
5980	CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg2);
5981	CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg3);
5982	CPUM_ASSERT_RD_MSR_FN(AmdFam15hExecUnitCfg);
5983	CPUM_ASSERT_RD_MSR_FN(AmdFam15hLoadStoreCfg2);
5984	CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchCtl);
5985	CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchLinAddr);
5986	CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchPhysAddr);
5987	CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpExecCtl);
5988	CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpRip);
5989	CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData);
5990	CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData2);
5991	CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData3);
5992	CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsDcLinAddr);
5993	CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsDcPhysAddr);
5994	CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsCtl);
5995	CPUM_ASSERT_RD_MSR_FN(AmdFam14hIbsBrTarget);
5996
5997	CPUM_ASSERT_RD_MSR_FN(Gim)
5998
5999	AssertReturn(g_aCpumWrMsrFns[kCpumMsrWrFn_Invalid].pfnWrMsr == NULL, VERR_CPUM_IPE_2);
6000	CPUM_ASSERT_WR_MSR_FN(Ia32P5McAddr);
6001	CPUM_ASSERT_WR_MSR_FN(Ia32P5McType);
6002	CPUM_ASSERT_WR_MSR_FN(Ia32TimestampCounter);
6003	CPUM_ASSERT_WR_MSR_FN(Ia32ApicBase);
6004	CPUM_ASSERT_WR_MSR_FN(Ia32FeatureControl);
6005	CPUM_ASSERT_WR_MSR_FN(Ia32BiosSignId);
6006	CPUM_ASSERT_WR_MSR_FN(Ia32BiosUpdateTrigger);
6007	CPUM_ASSERT_WR_MSR_FN(Ia32SmmMonitorCtl);
6008	CPUM_ASSERT_WR_MSR_FN(Ia32PmcN);
6009	CPUM_ASSERT_WR_MSR_FN(Ia32MonitorFilterLineSize);
6010	CPUM_ASSERT_WR_MSR_FN(Ia32MPerf);
6011	CPUM_ASSERT_WR_MSR_FN(Ia32APerf);
6012	CPUM_ASSERT_WR_MSR_FN(Ia32MtrrPhysBaseN);
6013	CPUM_ASSERT_WR_MSR_FN(Ia32MtrrPhysMaskN);
6014	CPUM_ASSERT_WR_MSR_FN(Ia32MtrrFixed);
6015	CPUM_ASSERT_WR_MSR_FN(Ia32MtrrDefType);
6016	CPUM_ASSERT_WR_MSR_FN(Ia32Pat);
6017	CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterCs);
6018	CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterEsp);
6019	CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterEip);
6020	CPUM_ASSERT_WR_MSR_FN(Ia32McgStatus);
6021	CPUM_ASSERT_WR_MSR_FN(Ia32McgCtl);
6022	CPUM_ASSERT_WR_MSR_FN(Ia32DebugCtl);
6023	CPUM_ASSERT_WR_MSR_FN(Ia32SmrrPhysBase);
6024	CPUM_ASSERT_WR_MSR_FN(Ia32SmrrPhysMask);
6025	CPUM_ASSERT_WR_MSR_FN(Ia32PlatformDcaCap);
6026	CPUM_ASSERT_WR_MSR_FN(Ia32Dca0Cap);
6027	CPUM_ASSERT_WR_MSR_FN(Ia32PerfEvtSelN);
6028	CPUM_ASSERT_WR_MSR_FN(Ia32PerfStatus);
6029	CPUM_ASSERT_WR_MSR_FN(Ia32PerfCtl);
6030	CPUM_ASSERT_WR_MSR_FN(Ia32FixedCtrN);
6031	CPUM_ASSERT_WR_MSR_FN(Ia32PerfCapabilities);
6032	CPUM_ASSERT_WR_MSR_FN(Ia32FixedCtrCtrl);
6033	CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalStatus);
6034	CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalCtrl);
6035	CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalOvfCtrl);
6036	CPUM_ASSERT_WR_MSR_FN(Ia32PebsEnable);
6037	CPUM_ASSERT_WR_MSR_FN(Ia32ClockModulation);
6038	CPUM_ASSERT_WR_MSR_FN(Ia32ThermInterrupt);
6039	CPUM_ASSERT_WR_MSR_FN(Ia32ThermStatus);
6040	CPUM_ASSERT_WR_MSR_FN(Ia32MiscEnable);
6041	CPUM_ASSERT_WR_MSR_FN(Ia32McCtlStatusAddrMiscN);
6042	CPUM_ASSERT_WR_MSR_FN(Ia32McNCtl2);
6043	CPUM_ASSERT_WR_MSR_FN(Ia32DsArea);
6044	CPUM_ASSERT_WR_MSR_FN(Ia32TscDeadline);
6045	CPUM_ASSERT_WR_MSR_FN(Ia32X2ApicN);
6046	CPUM_ASSERT_WR_MSR_FN(Ia32DebugInterface);
6047	CPUM_ASSERT_WR_MSR_FN(Ia32SpecCtrl);
6048	CPUM_ASSERT_WR_MSR_FN(Ia32PredCmd);
6049	CPUM_ASSERT_WR_MSR_FN(Ia32FlushCmd);
6050
6051	CPUM_ASSERT_WR_MSR_FN(Amd64Efer);
6052	CPUM_ASSERT_WR_MSR_FN(Amd64SyscallTarget);
6053	CPUM_ASSERT_WR_MSR_FN(Amd64LongSyscallTarget);
6054	CPUM_ASSERT_WR_MSR_FN(Amd64CompSyscallTarget);
6055	CPUM_ASSERT_WR_MSR_FN(Amd64SyscallFlagMask);
6056	CPUM_ASSERT_WR_MSR_FN(Amd64FsBase);
6057	CPUM_ASSERT_WR_MSR_FN(Amd64GsBase);
6058	CPUM_ASSERT_WR_MSR_FN(Amd64KernelGsBase);
6059	CPUM_ASSERT_WR_MSR_FN(Amd64TscAux);
6060
6061	CPUM_ASSERT_WR_MSR_FN(IntelEblCrPowerOn);
6062	CPUM_ASSERT_WR_MSR_FN(IntelP4EbcHardPowerOn);
6063	CPUM_ASSERT_WR_MSR_FN(IntelP4EbcSoftPowerOn);
6064	CPUM_ASSERT_WR_MSR_FN(IntelP4EbcFrequencyId);
6065	CPUM_ASSERT_WR_MSR_FN(IntelFlexRatio);
6066	CPUM_ASSERT_WR_MSR_FN(IntelPkgCStConfigControl);
6067	CPUM_ASSERT_WR_MSR_FN(IntelPmgIoCaptureBase);
6068	CPUM_ASSERT_WR_MSR_FN(IntelLastBranchFromToN);
6069	CPUM_ASSERT_WR_MSR_FN(IntelLastBranchFromN);
6070	CPUM_ASSERT_WR_MSR_FN(IntelLastBranchToN);
6071	CPUM_ASSERT_WR_MSR_FN(IntelLastBranchTos);
6072	CPUM_ASSERT_WR_MSR_FN(IntelBblCrCtl);
6073	CPUM_ASSERT_WR_MSR_FN(IntelBblCrCtl3);
6074	CPUM_ASSERT_WR_MSR_FN(IntelI7TemperatureTarget);
6075	CPUM_ASSERT_WR_MSR_FN(IntelI7MsrOffCoreResponseN);
6076	CPUM_ASSERT_WR_MSR_FN(IntelI7MiscPwrMgmt);
6077	CPUM_ASSERT_WR_MSR_FN(IntelP6CrN);
6078	CPUM_ASSERT_WR_MSR_FN(IntelCpuId1FeatureMaskEcdx);
6079	CPUM_ASSERT_WR_MSR_FN(IntelCpuId1FeatureMaskEax);
6080	CPUM_ASSERT_WR_MSR_FN(IntelCpuId80000001FeatureMaskEcdx);
6081	CPUM_ASSERT_WR_MSR_FN(IntelI7SandyAesNiCtl);
6082	CPUM_ASSERT_WR_MSR_FN(IntelI7TurboRatioLimit);
6083	CPUM_ASSERT_WR_MSR_FN(IntelI7LbrSelect);
6084	CPUM_ASSERT_WR_MSR_FN(IntelI7SandyErrorControl);
6085	CPUM_ASSERT_WR_MSR_FN(IntelI7PowerCtl);
6086	CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPebsNumAlt);
6087	CPUM_ASSERT_WR_MSR_FN(IntelI7PebsLdLat);
6088	CPUM_ASSERT_WR_MSR_FN(IntelI7SandyVrCurrentConfig);
6089	CPUM_ASSERT_WR_MSR_FN(IntelI7SandyVrMiscConfig);
6090	CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPkgCnIrtlN);
6091	CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPkgC2Residency);
6092	CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPkgPowerLimit);
6093	CPUM_ASSERT_WR_MSR_FN(IntelI7RaplDramPowerLimit);
6094	CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp0PowerLimit);
6095	CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp0Policy);
6096	CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp1PowerLimit);
6097	CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp1Policy);
6098	CPUM_ASSERT_WR_MSR_FN(IntelI7IvyConfigTdpControl);
6099	CPUM_ASSERT_WR_MSR_FN(IntelI7IvyTurboActivationRatio);
6100	CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalCtrl);
6101	CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalStatus);
6102	CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalOvfCtrl);
6103	CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfFixedCtrCtrl);
6104	CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfFixedCtr);
6105	CPUM_ASSERT_WR_MSR_FN(IntelI7UncArbPerfCtrN);
6106	CPUM_ASSERT_WR_MSR_FN(IntelI7UncArbPerfEvtSelN);
6107	CPUM_ASSERT_WR_MSR_FN(IntelCore2EmttmCrTablesN);
6108	CPUM_ASSERT_WR_MSR_FN(IntelCore2SmmCStMiscInfo);
6109	CPUM_ASSERT_WR_MSR_FN(IntelCore1ExtConfig);
6110	CPUM_ASSERT_WR_MSR_FN(IntelCore1DtsCalControl);
6111	CPUM_ASSERT_WR_MSR_FN(IntelCore2PeciControl);
6112
6113	CPUM_ASSERT_WR_MSR_FN(P6LastIntFromIp);
6114	CPUM_ASSERT_WR_MSR_FN(P6LastIntToIp);
6115
6116	CPUM_ASSERT_WR_MSR_FN(AmdFam15hTscRate);
6117	CPUM_ASSERT_WR_MSR_FN(AmdFam15hLwpCfg);
6118	CPUM_ASSERT_WR_MSR_FN(AmdFam15hLwpCbAddr);
6119	CPUM_ASSERT_WR_MSR_FN(AmdFam10hMc4MiscN);
6120	CPUM_ASSERT_WR_MSR_FN(AmdK8PerfCtlN);
6121	CPUM_ASSERT_WR_MSR_FN(AmdK8PerfCtrN);
6122	CPUM_ASSERT_WR_MSR_FN(AmdK8SysCfg);
6123	CPUM_ASSERT_WR_MSR_FN(AmdK8HwCr);
6124	CPUM_ASSERT_WR_MSR_FN(AmdK8IorrBaseN);
6125	CPUM_ASSERT_WR_MSR_FN(AmdK8IorrMaskN);
6126	CPUM_ASSERT_WR_MSR_FN(AmdK8TopOfMemN);
6127	CPUM_ASSERT_WR_MSR_FN(AmdK8NbCfg1);
6128	CPUM_ASSERT_WR_MSR_FN(AmdK8McXcptRedir);
6129	CPUM_ASSERT_WR_MSR_FN(AmdK8CpuNameN);
6130	CPUM_ASSERT_WR_MSR_FN(AmdK8HwThermalCtrl);
6131	CPUM_ASSERT_WR_MSR_FN(AmdK8SwThermalCtrl);
6132	CPUM_ASSERT_WR_MSR_FN(AmdK8FidVidControl);
6133	CPUM_ASSERT_WR_MSR_FN(AmdK8McCtlMaskN);
6134	CPUM_ASSERT_WR_MSR_FN(AmdK8SmiOnIoTrapN);
6135	CPUM_ASSERT_WR_MSR_FN(AmdK8SmiOnIoTrapCtlSts);
6136	CPUM_ASSERT_WR_MSR_FN(AmdK8IntPendingMessage);
6137	CPUM_ASSERT_WR_MSR_FN(AmdK8SmiTriggerIoCycle);
6138	CPUM_ASSERT_WR_MSR_FN(AmdFam10hMmioCfgBaseAddr);
6139	CPUM_ASSERT_WR_MSR_FN(AmdFam10hTrapCtlMaybe);
6140	CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateControl);
6141	CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateStatus);
6142	CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateN);
6143	CPUM_ASSERT_WR_MSR_FN(AmdFam10hCofVidControl);
6144	CPUM_ASSERT_WR_MSR_FN(AmdFam10hCofVidStatus);
6145	CPUM_ASSERT_WR_MSR_FN(AmdFam10hCStateIoBaseAddr);
6146	CPUM_ASSERT_WR_MSR_FN(AmdFam10hCpuWatchdogTimer);
6147	CPUM_ASSERT_WR_MSR_FN(AmdK8SmmBase);
6148	CPUM_ASSERT_WR_MSR_FN(AmdK8SmmAddr);
6149	CPUM_ASSERT_WR_MSR_FN(AmdK8SmmMask);
6150	CPUM_ASSERT_WR_MSR_FN(AmdK8VmCr);
6151	CPUM_ASSERT_WR_MSR_FN(AmdK8IgnNe);
6152	CPUM_ASSERT_WR_MSR_FN(AmdK8SmmCtl);
6153	CPUM_ASSERT_WR_MSR_FN(AmdK8VmHSavePa);
6154	CPUM_ASSERT_WR_MSR_FN(AmdFam10hVmLockKey);
6155	CPUM_ASSERT_WR_MSR_FN(AmdFam10hSmmLockKey);
6156	CPUM_ASSERT_WR_MSR_FN(AmdFam10hLocalSmiStatus);
6157	CPUM_ASSERT_WR_MSR_FN(AmdFam10hOsVisWrkIdLength);
6158	CPUM_ASSERT_WR_MSR_FN(AmdFam10hOsVisWrkStatus);
6159	CPUM_ASSERT_WR_MSR_FN(AmdFam16hL2IPerfCtlN);
6160	CPUM_ASSERT_WR_MSR_FN(AmdFam16hL2IPerfCtrN);
6161	CPUM_ASSERT_WR_MSR_FN(AmdFam15hNorthbridgePerfCtlN);
6162	CPUM_ASSERT_WR_MSR_FN(AmdFam15hNorthbridgePerfCtrN);
6163	CPUM_ASSERT_WR_MSR_FN(AmdK7MicrocodeCtl);
6164	CPUM_ASSERT_WR_MSR_FN(AmdK7ClusterIdMaybe);
6165	CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd07hEbax);
6166	CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd06hEcx);
6167	CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd01hEdcx);
6168	CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlExt01hEdcx);
6169	CPUM_ASSERT_WR_MSR_FN(AmdK8PatchLoader);
6170	CPUM_ASSERT_WR_MSR_FN(AmdK7DebugStatusMaybe);
6171	CPUM_ASSERT_WR_MSR_FN(AmdK7BHTraceBaseMaybe);
6172	CPUM_ASSERT_WR_MSR_FN(AmdK7BHTracePtrMaybe);
6173	CPUM_ASSERT_WR_MSR_FN(AmdK7BHTraceLimitMaybe);
6174	CPUM_ASSERT_WR_MSR_FN(AmdK7HardwareDebugToolCfgMaybe);
6175	CPUM_ASSERT_WR_MSR_FN(AmdK7FastFlushCountMaybe);
6176	CPUM_ASSERT_WR_MSR_FN(AmdK7NodeId);
6177	CPUM_ASSERT_WR_MSR_FN(AmdK7DrXAddrMaskN);
6178	CPUM_ASSERT_WR_MSR_FN(AmdK7Dr0DataMatchMaybe);
6179	CPUM_ASSERT_WR_MSR_FN(AmdK7Dr0DataMaskMaybe);
6180	CPUM_ASSERT_WR_MSR_FN(AmdK7LoadStoreCfg);
6181	CPUM_ASSERT_WR_MSR_FN(AmdK7InstrCacheCfg);
6182	CPUM_ASSERT_WR_MSR_FN(AmdK7DataCacheCfg);
6183	CPUM_ASSERT_WR_MSR_FN(AmdK7BusUnitCfg);
6184	CPUM_ASSERT_WR_MSR_FN(AmdK7DebugCtl2Maybe);
6185	CPUM_ASSERT_WR_MSR_FN(AmdFam15hFpuCfg);
6186	CPUM_ASSERT_WR_MSR_FN(AmdFam15hDecoderCfg);
6187	CPUM_ASSERT_WR_MSR_FN(AmdFam10hBusUnitCfg2);
6188	CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg);
6189	CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg2);
6190	CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg3);
6191	CPUM_ASSERT_WR_MSR_FN(AmdFam15hExecUnitCfg);
6192	CPUM_ASSERT_WR_MSR_FN(AmdFam15hLoadStoreCfg2);
6193	CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchCtl);
6194	CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchLinAddr);
6195	CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchPhysAddr);
6196	CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpExecCtl);
6197	CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpRip);
6198	CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData);
6199	CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData2);
6200	CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData3);
6201	CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsDcLinAddr);
6202	CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsDcPhysAddr);
6203	CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsCtl);
6204	CPUM_ASSERT_WR_MSR_FN(AmdFam14hIbsBrTarget);
6205
6206	CPUM_ASSERT_WR_MSR_FN(Gim);
6207
6208	return VINF_SUCCESS;
6209	}
6210	#endif /* VBOX_STRICT && IN_RING3 */
6211
6212
6213	/**
6214	* Gets the scalable bus frequency.
6215	*
6216	* The bus frequency is used as a base in several MSRs that gives the CPU and
6217	* other frequency ratios.
6218	*
6219	* @returns Scalable bus frequency in Hz. Will not return CPUM_SBUSFREQ_UNKNOWN.
6220	* @param pVM The cross context VM structure.
6221	*/
6222	VMMDECL(uint64_t) CPUMGetGuestScalableBusFrequency(PVM pVM)
6223	{
6224	uint64_t uFreq = pVM->cpum.s.GuestInfo.uScalableBusFreq;
6225	if (uFreq == CPUM_SBUSFREQ_UNKNOWN)
6226	uFreq = CPUM_SBUSFREQ_100MHZ;
6227	return uFreq;
6228	}
6229
6230
6231	/**
6232	* Sets the guest EFER MSR without performing any additional checks.
6233	*
6234	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
6235	* @param uOldEfer The previous EFER MSR value.
6236	* @param uValidEfer The new, validated EFER MSR value.
6237	*
6238	* @remarks One would normally call CPUMIsGuestEferMsrWriteValid() before calling
6239	* this function to change the EFER in order to perform an EFER transition.
6240	*/
6241	VMMDECL(void) CPUMSetGuestEferMsrNoChecks(PVMCPUCC pVCpu, uint64_t uOldEfer, uint64_t uValidEfer)
6242	{
6243	pVCpu->cpum.s.Guest.msrEFER = uValidEfer;
6244
6245	/* AMD64 Architecture Programmer's Manual: 15.15 TLB Control; flush the TLB
6246	if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
6247	if ( (uOldEfer & (MSR_K6_EFER_NXE \| MSR_K6_EFER_LME \| MSR_K6_EFER_LMA))
6248	!= (pVCpu->cpum.s.Guest.msrEFER & (MSR_K6_EFER_NXE \| MSR_K6_EFER_LME \| MSR_K6_EFER_LMA)))
6249	{
6250	/// @todo PGMFlushTLB(pVCpu, cr3, true /fGlobal/);
6251	HMFlushTlb(pVCpu);
6252
6253	/* Notify PGM about NXE changes. */
6254	if ( (uOldEfer & MSR_K6_EFER_NXE)
6255	!= (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE))
6256	PGMNotifyNxeChanged(pVCpu, !(uOldEfer & MSR_K6_EFER_NXE));
6257	}
6258	}
6259
6260
6261	/**
6262	* Checks if a guest PAT MSR write is valid.
6263	*
6264	* @returns @c true if the PAT bit combination is valid, @c false otherwise.
6265	* @param uValue The PAT MSR value.
6266	*/
6267	VMMDECL(bool) CPUMIsPatMsrValid(uint64_t uValue)
6268	{
6269	for (uint32_t cShift = 0; cShift < 63; cShift += 8)
6270	{
6271	/* Check all eight bits because the top 5 bits of each byte are reserved. */
6272	uint8_t uType = (uint8_t)(uValue >> cShift);
6273	if ((uType >= 8) \|\| (uType == 2) \|\| (uType == 3))
6274	{
6275	Log(("CPUM: Invalid PAT type at %u:%u in IA32_PAT: %#llx (%#llx)\n", cShift + 7, cShift, uValue, uType));
6276	return false;
6277	}
6278	}
6279	return true;
6280	}
6281
6282
6283	/**
6284	* Validates an EFER MSR write and provides the new, validated EFER MSR.
6285	*
6286	* @returns VBox status code.
6287	* @param pVM The cross context VM structure.
6288	* @param uCr0 The CR0 of the CPU corresponding to the EFER MSR.
6289	* @param uOldEfer Value of the previous EFER MSR on the CPU if any.
6290	* @param uNewEfer The new EFER MSR value being written.
6291	* @param puValidEfer Where to store the validated EFER (only updated if
6292	* this function returns VINF_SUCCESS).
6293	*/
6294	VMMDECL(int) CPUMIsGuestEferMsrWriteValid(PVM pVM, uint64_t uCr0, uint64_t uOldEfer, uint64_t uNewEfer, uint64_t *puValidEfer)
6295	{
6296	/* #GP(0) If anything outside the allowed bits is set. */
6297	uint64_t fMask = CPUMGetGuestEferMsrValidMask(pVM);
6298	if (uNewEfer & ~fMask)
6299	{
6300	Log(("CPUM: Settings disallowed EFER bit. uNewEfer=%#RX64 fAllowed=%#RX64 -> #GP(0)\n", uNewEfer, fMask));
6301	return VERR_CPUM_RAISE_GP_0;
6302	}
6303
6304	/* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if
6305	paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
6306	if ( (uOldEfer & MSR_K6_EFER_LME) != (uNewEfer & MSR_K6_EFER_LME)
6307	&& (uCr0 & X86_CR0_PG))
6308	{
6309	Log(("CPUM: Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
6310	return VERR_CPUM_RAISE_GP_0;
6311	}
6312
6313	/* There are a few more: e.g. MSR_K6_EFER_LMSLE. */
6314	AssertMsg(!(uNewEfer & ~( MSR_K6_EFER_NXE
6315	\| MSR_K6_EFER_LME
6316	\| MSR_K6_EFER_LMA /* ignored anyway */
6317	\| MSR_K6_EFER_SCE
6318	\| MSR_K6_EFER_FFXSR
6319	\| MSR_K6_EFER_SVME)),
6320	("Unexpected value %#RX64\n", uNewEfer));
6321
6322	/* Ignore EFER.LMA, it's updated when setting CR0. */
6323	fMask &= ~MSR_K6_EFER_LMA;
6324
6325	*puValidEfer = (uOldEfer & ~fMask) \| (uNewEfer & fMask);
6326	return VINF_SUCCESS;
6327	}
6328
6329
6330	/**
6331	* Gets the mask of valid EFER bits depending on supported guest-CPU features.
6332	*
6333	* @returns Mask of valid EFER bits.
6334	* @param pVM The cross context VM structure.
6335	*
6336	* @remarks EFER.LMA is included as part of the valid mask. It's not invalid but
6337	* rather a read-only bit.
6338	*/
6339	VMMDECL(uint64_t) CPUMGetGuestEferMsrValidMask(PVM pVM)
6340	{
6341	uint32_t const fExtFeatures = pVM->cpum.s.aGuestCpuIdPatmExt[0].uEax >= 0x80000001
6342	? pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx
6343	: 0;
6344	uint64_t fMask = 0;
6345	uint64_t const fIgnoreMask = MSR_K6_EFER_LMA;
6346
6347	/* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
6348	if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_NX)
6349	fMask \|= MSR_K6_EFER_NXE;
6350	if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
6351	fMask \|= MSR_K6_EFER_LME;
6352	if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
6353	fMask \|= MSR_K6_EFER_SCE;
6354	if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
6355	fMask \|= MSR_K6_EFER_FFXSR;
6356	if (pVM->cpum.s.GuestFeatures.fSvm)
6357	fMask \|= MSR_K6_EFER_SVME;
6358
6359	return (fIgnoreMask \| fMask);
6360	}
6361
6362
6363	/**
6364	* Fast way for HM to access the MSR_K8_TSC_AUX register.
6365	*
6366	* @returns The register value.
6367	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
6368	* @thread EMT(pVCpu)
6369	*/
6370	VMM_INT_DECL(uint64_t) CPUMGetGuestTscAux(PVMCPUCC pVCpu)
6371	{
6372	Assert(!(pVCpu->cpum.s.Guest.fExtrn & CPUMCTX_EXTRN_TSC_AUX));
6373	return pVCpu->cpum.s.GuestMsrs.msr.TscAux;
6374	}
6375
6376
6377	/**
6378	* Fast way for HM to access the MSR_K8_TSC_AUX register.
6379	*
6380	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
6381	* @param uValue The new value.
6382	* @thread EMT(pVCpu)
6383	*/
6384	VMM_INT_DECL(void) CPUMSetGuestTscAux(PVMCPUCC pVCpu, uint64_t uValue)
6385	{
6386	pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_TSC_AUX;
6387	pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
6388	}
6389
6390
6391	/**
6392	* Fast way for HM to access the IA32_SPEC_CTRL register.
6393	*
6394	* @returns The register value.
6395	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
6396	* @thread EMT(pVCpu)
6397	*/
6398	VMM_INT_DECL(uint64_t) CPUMGetGuestSpecCtrl(PVMCPUCC pVCpu)
6399	{
6400	return pVCpu->cpum.s.GuestMsrs.msr.SpecCtrl;
6401	}
6402
6403
6404	/**
6405	* Fast way for HM to access the IA32_SPEC_CTRL register.
6406	*
6407	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
6408	* @param uValue The new value.
6409	* @thread EMT(pVCpu)
6410	*/
6411	VMM_INT_DECL(void) CPUMSetGuestSpecCtrl(PVMCPUCC pVCpu, uint64_t uValue)
6412	{
6413	pVCpu->cpum.s.GuestMsrs.msr.SpecCtrl = uValue;
6414	}
6415

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source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllMsrs.cpp@ 85416

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