CPUMAllMsrs.cpp@ 73400

Last change on this file since 73400 was 73395, checked in by vboxsync, 7 years ago
VMM, CPUM: Nested VMX: bugref:9180 Implement Cr0Fixed[0\|1] and Cr4Fixed[0\|1] MSRs, nits.
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1	/* $Id: CPUMAllMsrs.cpp 73395 2018-07-30 15:19:54Z vboxsync $ */
2	/** @file
3	* CPUM - CPU MSR Registers.
4	*/
5
6	/*
7	* Copyright (C) 2013-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include <VBox/vmm/apic.h>
25	#include <VBox/vmm/hm.h>
26	#include <VBox/vmm/hm_vmx.h>
27	#include <VBox/vmm/tm.h>
28	#include <VBox/vmm/gim.h>
29	#include "CPUMInternal.h"
30	#include <VBox/vmm/vm.h>
31	#include <VBox/err.h>
32
33
34	/*********************************************************************************************************************************
35	* Defined Constants And Macros *
36	*********************************************************************************************************************************/
37	/**
38	* Validates the CPUMMSRRANGE::offCpumCpu value and declares a local variable
39	* pointing to it.
40	*
41	* ASSUMES sizeof(a_Type) is a power of two and that the member is aligned
42	* correctly.
43	*/
44	#define CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(a_pVCpu, a_pRange, a_Type, a_VarName) \
45	AssertMsgReturn( (a_pRange)->offCpumCpu >= 8 \
46	&& (a_pRange)->offCpumCpu < sizeof(CPUMCPU) \
47	&& !((a_pRange)->offCpumCpu & (RT_MIN(sizeof(a_Type), 8) - 1)) \
48	, ("offCpumCpu=%#x %s\n", (a_pRange)->offCpumCpu, (a_pRange)->szName), \
49	VERR_CPUM_MSR_BAD_CPUMCPU_OFFSET); \
50	a_Type a_VarName = (a_Type )((uintptr_t)&(a_pVCpu)->cpum.s + (a_pRange)->offCpumCpu)
51
52
53	/*********************************************************************************************************************************
54	* Structures and Typedefs *
55	*********************************************************************************************************************************/
56
57	/**
58	* Implements reading one or more MSRs.
59	*
60	* @returns VBox status code.
61	* @retval VINF_SUCCESS on success.
62	* @retval VINF_CPUM_R3_MSR_READ if the MSR read could not be serviced in the
63	* current context (raw-mode or ring-0).
64	* @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR).
65	*
66	* @param pVCpu The cross context virtual CPU structure.
67	* @param idMsr The MSR we're reading.
68	* @param pRange The MSR range descriptor.
69	* @param puValue Where to return the value.
70	*/
71	typedef DECLCALLBACK(VBOXSTRICTRC) FNCPUMRDMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue);
72	/** Pointer to a RDMSR worker for a specific MSR or range of MSRs. */
73	typedef FNCPUMRDMSR *PFNCPUMRDMSR;
74
75
76	/**
77	* Implements writing one or more MSRs.
78	*
79	* @retval VINF_SUCCESS on success.
80	* @retval VINF_CPUM_R3_MSR_WRITE if the MSR write could not be serviced in the
81	* current context (raw-mode or ring-0).
82	* @retval VERR_CPUM_RAISE_GP_0 on failure.
83	*
84	* @param pVCpu The cross context virtual CPU structure.
85	* @param idMsr The MSR we're writing.
86	* @param pRange The MSR range descriptor.
87	* @param uValue The value to set, ignored bits masked.
88	* @param uRawValue The raw value with the ignored bits not masked.
89	*/
90	typedef DECLCALLBACK(VBOXSTRICTRC) FNCPUMWRMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue);
91	/** Pointer to a WRMSR worker for a specific MSR or range of MSRs. */
92	typedef FNCPUMWRMSR *PFNCPUMWRMSR;
93
94
95
96	/*
97	* Generic functions.
98	* Generic functions.
99	* Generic functions.
100	*/
101
102
103	/** @callback_method_impl{FNCPUMRDMSR} */
104	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_FixedValue(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
105	{
106	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
107	*puValue = pRange->uValue;
108	return VINF_SUCCESS;
109	}
110
111
112	/** @callback_method_impl{FNCPUMWRMSR} */
113	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IgnoreWrite(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
114	{
115	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
116	Log(("CPUM: Ignoring WRMSR %#x (%s), %#llx\n", idMsr, pRange->szName, uValue));
117	return VINF_SUCCESS;
118	}
119
120
121	/** @callback_method_impl{FNCPUMRDMSR} */
122	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_WriteOnly(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
123	{
124	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(puValue);
125	return VERR_CPUM_RAISE_GP_0;
126	}
127
128
129	/** @callback_method_impl{FNCPUMWRMSR} */
130	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_ReadOnly(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
131	{
132	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
133	Assert(pRange->fWrGpMask == UINT64_MAX);
134	return VERR_CPUM_RAISE_GP_0;
135	}
136
137
138
139
140	/*
141	* IA32
142	* IA32
143	* IA32
144	*/
145
146	/** @callback_method_impl{FNCPUMRDMSR} */
147	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32P5McAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
148	{
149	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
150	puValue = 0; /* @todo implement machine check injection. */
151	return VINF_SUCCESS;
152	}
153
154
155	/** @callback_method_impl{FNCPUMWRMSR} */
156	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32P5McAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
157	{
158	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
159	/** @todo implement machine check injection. */
160	return VINF_SUCCESS;
161	}
162
163
164	/** @callback_method_impl{FNCPUMRDMSR} */
165	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32P5McType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
166	{
167	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
168	puValue = 0; /* @todo implement machine check injection. */
169	return VINF_SUCCESS;
170	}
171
172
173	/** @callback_method_impl{FNCPUMWRMSR} */
174	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32P5McType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
175	{
176	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
177	/** @todo implement machine check injection. */
178	return VINF_SUCCESS;
179	}
180
181
182	/** @callback_method_impl{FNCPUMRDMSR} */
183	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32TimestampCounter(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
184	{
185	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
186	*puValue = TMCpuTickGet(pVCpu);
187	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
188	puValue = CPUMApplyNestedGuestTscOffset(pVCpu, puValue);
189	#endif
190	return VINF_SUCCESS;
191	}
192
193
194	/** @callback_method_impl{FNCPUMWRMSR} */
195	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32TimestampCounter(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
196	{
197	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
198	TMCpuTickSet(pVCpu->CTX_SUFF(pVM), pVCpu, uValue);
199	return VINF_SUCCESS;
200	}
201
202
203	/** @callback_method_impl{FNCPUMRDMSR} */
204	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PlatformId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
205	{
206	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
207	uint64_t uValue = pRange->uValue;
208	if (uValue & 0x1f00)
209	{
210	/* Max allowed bus ratio present. */
211	/** @todo Implement scaled BUS frequency. */
212	}
213
214	*puValue = uValue;
215	return VINF_SUCCESS;
216	}
217
218
219	/** @callback_method_impl{FNCPUMRDMSR} */
220	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ApicBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
221	{
222	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
223	return APICGetBaseMsr(pVCpu, puValue);
224	}
225
226
227	/** @callback_method_impl{FNCPUMWRMSR} */
228	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ApicBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
229	{
230	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
231	return APICSetBaseMsr(pVCpu, uValue);
232	}
233
234
235	/**
236	* Get fixed IA32_FEATURE_CONTROL value for NEM and cpumMsrRd_Ia32FeatureControl.
237	*
238	* @returns Fixed IA32_FEATURE_CONTROL value.
239	* @param pVCpu The cross context per CPU structure.
240	*/
241	VMM_INT_DECL(uint64_t) CPUMGetGuestIa32FeatureControl(PVMCPU pVCpu)
242	{
243	/* Always report the MSR lock bit as set, in order to prevent guests from modifiying this MSR. */
244	uint64_t fFeatCtl = MSR_IA32_FEATURE_CONTROL_LOCK;
245
246	/* Report VMX features. */
247	if (pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fVmx)
248	fFeatCtl \|= MSR_IA32_FEATURE_CONTROL_VMXON;
249
250	return fFeatCtl;
251	}
252
253	/** @callback_method_impl{FNCPUMRDMSR} */
254	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32FeatureControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
255	{
256	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
257	*puValue = CPUMGetGuestIa32FeatureControl(pVCpu);
258	return VINF_SUCCESS;
259	}
260
261
262	/** @callback_method_impl{FNCPUMWRMSR} */
263	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32FeatureControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
264	{
265	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
266	return VERR_CPUM_RAISE_GP_0;
267	}
268
269
270	/** @callback_method_impl{FNCPUMRDMSR} */
271	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32BiosSignId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
272	{
273	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
274	/** @todo fake microcode update. */
275	*puValue = pRange->uValue;
276	return VINF_SUCCESS;
277	}
278
279
280	/** @callback_method_impl{FNCPUMWRMSR} */
281	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32BiosSignId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
282	{
283	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
284	/* Normally, zero is written to Ia32BiosSignId before reading it in order
285	to select the signature instead of the BBL_CR_D3 behaviour. The GP mask
286	of the database entry should take care of most illegal writes for now, so
287	just ignore all writes atm. */
288	return VINF_SUCCESS;
289	}
290
291
292	/** @callback_method_impl{FNCPUMWRMSR} */
293	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32BiosUpdateTrigger(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
294	{
295	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
296	/** @todo Fake bios update trigger better. The value is the address to an
297	* update package, I think. We should probably GP if it's invalid. */
298	return VINF_SUCCESS;
299	}
300
301
302	/** @callback_method_impl{FNCPUMRDMSR} */
303	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SmmMonitorCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
304	{
305	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
306	/** @todo SMM. */
307	*puValue = 0;
308	return VINF_SUCCESS;
309	}
310
311
312	/** @callback_method_impl{FNCPUMWRMSR} */
313	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SmmMonitorCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
314	{
315	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
316	/** @todo SMM. */
317	return VINF_SUCCESS;
318	}
319
320
321	/** @callback_method_impl{FNCPUMRDMSR} */
322	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PmcN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
323	{
324	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
325	/** @todo check CPUID leaf 0ah. */
326	*puValue = 0;
327	return VINF_SUCCESS;
328	}
329
330
331	/** @callback_method_impl{FNCPUMWRMSR} */
332	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PmcN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
333	{
334	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
335	/** @todo check CPUID leaf 0ah. */
336	return VINF_SUCCESS;
337	}
338
339
340	/** @callback_method_impl{FNCPUMRDMSR} */
341	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MonitorFilterLineSize(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
342	{
343	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
344	/** @todo return 0x1000 if we try emulate mwait 100% correctly. */
345	puValue = 0x40; /* @todo Change to CPU cache line size. */
346	return VINF_SUCCESS;
347	}
348
349
350	/** @callback_method_impl{FNCPUMWRMSR} */
351	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MonitorFilterLineSize(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
352	{
353	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
354	/** @todo should remember writes, though it's supposedly something only a BIOS
355	* would write so, it's not extremely important. */
356	return VINF_SUCCESS;
357	}
358
359	/** @callback_method_impl{FNCPUMRDMSR} */
360	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MPerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
361	{
362	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
363	/** @todo Read MPERF: Adjust against previously written MPERF value. Is TSC
364	* what we want? */
365	*puValue = TMCpuTickGet(pVCpu);
366	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
367	puValue = CPUMApplyNestedGuestTscOffset(pVCpu, puValue);
368	#endif
369	return VINF_SUCCESS;
370	}
371
372
373	/** @callback_method_impl{FNCPUMWRMSR} */
374	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MPerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
375	{
376	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
377	/** @todo Write MPERF: Calc adjustment. */
378	return VINF_SUCCESS;
379	}
380
381
382	/** @callback_method_impl{FNCPUMRDMSR} */
383	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32APerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
384	{
385	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
386	/** @todo Read APERF: Adjust against previously written MPERF value. Is TSC
387	* what we want? */
388	*puValue = TMCpuTickGet(pVCpu);
389	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
390	puValue = CPUMApplyNestedGuestTscOffset(pVCpu, puValue);
391	#endif
392	return VINF_SUCCESS;
393	}
394
395
396	/** @callback_method_impl{FNCPUMWRMSR} */
397	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32APerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
398	{
399	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
400	/** @todo Write APERF: Calc adjustment. */
401	return VINF_SUCCESS;
402	}
403
404
405	/**
406	* Get fixed IA32_MTRR_CAP value for NEM and cpumMsrRd_Ia32MtrrCap.
407	*
408	* @returns Fixed IA32_MTRR_CAP value.
409	* @param pVCpu The cross context per CPU structure.
410	*/
411	VMM_INT_DECL(uint64_t) CPUMGetGuestIa32MtrrCap(PVMCPU pVCpu)
412	{
413	RT_NOREF_PV(pVCpu);
414
415	/* This is currently a bit weird. :-) */
416	uint8_t const cVariableRangeRegs = 0;
417	bool const fSystemManagementRangeRegisters = false;
418	bool const fFixedRangeRegisters = false;
419	bool const fWriteCombiningType = false;
420	return cVariableRangeRegs
421	\| (fFixedRangeRegisters ? RT_BIT_64(8) : 0)
422	\| (fWriteCombiningType ? RT_BIT_64(10) : 0)
423	\| (fSystemManagementRangeRegisters ? RT_BIT_64(11) : 0);
424	}
425
426	/** @callback_method_impl{FNCPUMRDMSR} */
427	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
428	{
429	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
430	*puValue = CPUMGetGuestIa32MtrrCap(pVCpu);
431	return VINF_SUCCESS;
432	}
433
434
435	/** @callback_method_impl{FNCPUMRDMSR} */
436	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrPhysBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
437	{
438	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
439	/** @todo Implement variable MTRR storage. */
440	Assert(pRange->uValue == (idMsr - 0x200) / 2);
441	*puValue = 0;
442	return VINF_SUCCESS;
443	}
444
445
446	/** @callback_method_impl{FNCPUMWRMSR} */
447	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrPhysBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
448	{
449	/*
450	* Validate the value.
451	*/
452	Assert(pRange->uValue == (idMsr - 0x200) / 2);
453	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(uRawValue); RT_NOREF_PV(pRange);
454
455	uint8_t uType = uValue & 0xff;
456	if ((uType >= 7) \|\| (uType == 2) \|\| (uType == 3))
457	{
458	Log(("CPUM: Invalid type set writing MTRR PhysBase MSR %#x: %#llx (%#llx)\n", idMsr, uValue, uType));
459	return VERR_CPUM_RAISE_GP_0;
460	}
461
462	uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
463	if (fInvPhysMask & uValue)
464	{
465	Log(("CPUM: Invalid physical address bits set writing MTRR PhysBase MSR %#x: %#llx (%#llx)\n",
466	idMsr, uValue, uValue & fInvPhysMask));
467	return VERR_CPUM_RAISE_GP_0;
468	}
469
470	/*
471	* Store it.
472	*/
473	/** @todo Implement variable MTRR storage. */
474	return VINF_SUCCESS;
475	}
476
477
478	/** @callback_method_impl{FNCPUMRDMSR} */
479	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrPhysMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
480	{
481	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
482	/** @todo Implement variable MTRR storage. */
483	Assert(pRange->uValue == (idMsr - 0x200) / 2);
484	*puValue = 0;
485	return VINF_SUCCESS;
486	}
487
488
489	/** @callback_method_impl{FNCPUMWRMSR} */
490	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrPhysMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
491	{
492	/*
493	* Validate the value.
494	*/
495	Assert(pRange->uValue == (idMsr - 0x200) / 2);
496	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(uRawValue); RT_NOREF_PV(pRange);
497
498	uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
499	if (fInvPhysMask & uValue)
500	{
501	Log(("CPUM: Invalid physical address bits set writing MTRR PhysMask MSR %#x: %#llx (%#llx)\n",
502	idMsr, uValue, uValue & fInvPhysMask));
503	return VERR_CPUM_RAISE_GP_0;
504	}
505
506	/*
507	* Store it.
508	*/
509	/** @todo Implement variable MTRR storage. */
510	return VINF_SUCCESS;
511	}
512
513
514	/** @callback_method_impl{FNCPUMRDMSR} */
515	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrFixed(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
516	{
517	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
518	CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(pVCpu, pRange, uint64_t, puFixedMtrr);
519	puValue = puFixedMtrr;
520	return VINF_SUCCESS;
521	}
522
523
524	/** @callback_method_impl{FNCPUMWRMSR} */
525	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrFixed(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
526	{
527	CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(pVCpu, pRange, uint64_t, puFixedMtrr);
528	RT_NOREF_PV(idMsr); RT_NOREF_PV(uRawValue);
529
530	for (uint32_t cShift = 0; cShift < 63; cShift += 8)
531	{
532	uint8_t uType = (uint8_t)(uValue >> cShift);
533	if ((uType >= 7) \|\| (uType == 2) \|\| (uType == 3))
534	{
535	Log(("CPUM: Invalid MTRR type at %u:%u in fixed range (%#x/%s): %#llx (%#llx)\n",
536	cShift + 7, cShift, idMsr, pRange->szName, uValue, uType));
537	return VERR_CPUM_RAISE_GP_0;
538	}
539	}
540	*puFixedMtrr = uValue;
541	return VINF_SUCCESS;
542	}
543
544
545	/** @callback_method_impl{FNCPUMRDMSR} */
546	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrDefType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
547	{
548	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
549	*puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType;
550	return VINF_SUCCESS;
551	}
552
553
554	/** @callback_method_impl{FNCPUMWRMSR} */
555	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrDefType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
556	{
557	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
558
559	uint8_t uType = uValue & 0xff;
560	if ((uType >= 7) \|\| (uType == 2) \|\| (uType == 3))
561	{
562	Log(("CPUM: Invalid MTRR default type value on %s: %#llx (%#llx)\n", pRange->szName, uValue, uType));
563	return VERR_CPUM_RAISE_GP_0;
564	}
565
566	pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType = uValue;
567	return VINF_SUCCESS;
568	}
569
570
571	/** @callback_method_impl{FNCPUMRDMSR} */
572	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32Pat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
573	{
574	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
575	*puValue = pVCpu->cpum.s.Guest.msrPAT;
576	return VINF_SUCCESS;
577	}
578
579
580	/** @callback_method_impl{FNCPUMWRMSR} */
581	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32Pat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
582	{
583	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
584	if (CPUMIsPatMsrValid(uValue))
585	{
586	pVCpu->cpum.s.Guest.msrPAT = uValue;
587	return VINF_SUCCESS;
588	}
589	return VERR_CPUM_RAISE_GP_0;
590	}
591
592
593	/** @callback_method_impl{FNCPUMRDMSR} */
594	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SysEnterCs(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
595	{
596	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
597	*puValue = pVCpu->cpum.s.Guest.SysEnter.cs;
598	return VINF_SUCCESS;
599	}
600
601
602	/** @callback_method_impl{FNCPUMWRMSR} */
603	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SysEnterCs(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
604	{
605	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
606
607	/* Note! We used to mask this by 0xffff, but turns out real HW doesn't and
608	there are generally 32-bit working bits backing this register. */
609	pVCpu->cpum.s.Guest.SysEnter.cs = uValue;
610	return VINF_SUCCESS;
611	}
612
613
614	/** @callback_method_impl{FNCPUMRDMSR} */
615	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SysEnterEsp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
616	{
617	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
618	*puValue = pVCpu->cpum.s.Guest.SysEnter.esp;
619	return VINF_SUCCESS;
620	}
621
622
623	/** @callback_method_impl{FNCPUMWRMSR} */
624	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SysEnterEsp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
625	{
626	if (X86_IS_CANONICAL(uValue))
627	{
628	pVCpu->cpum.s.Guest.SysEnter.esp = uValue;
629	return VINF_SUCCESS;
630	}
631	Log(("CPUM: IA32_SYSENTER_ESP not canonical! %#llx\n", uValue));
632	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
633	return VERR_CPUM_RAISE_GP_0;
634	}
635
636
637	/** @callback_method_impl{FNCPUMRDMSR} */
638	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SysEnterEip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
639	{
640	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
641	*puValue = pVCpu->cpum.s.Guest.SysEnter.eip;
642	return VINF_SUCCESS;
643	}
644
645
646	/** @callback_method_impl{FNCPUMWRMSR} */
647	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SysEnterEip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
648	{
649	if (X86_IS_CANONICAL(uValue))
650	{
651	pVCpu->cpum.s.Guest.SysEnter.eip = uValue;
652	return VINF_SUCCESS;
653	}
654	LogRel(("CPUM: IA32_SYSENTER_EIP not canonical! %#llx\n", uValue));
655	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
656	return VERR_CPUM_RAISE_GP_0;
657	}
658
659
660	/** @callback_method_impl{FNCPUMRDMSR} */
661	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McgCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
662	{
663	#if 0 /** @todo implement machine checks. */
664	*puValue = pRange->uValue & (RT_BIT_64(8) \| 0);
665	#else
666	*puValue = 0;
667	#endif
668	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
669	return VINF_SUCCESS;
670	}
671
672
673	/** @callback_method_impl{FNCPUMRDMSR} */
674	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McgStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
675	{
676	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
677	/** @todo implement machine checks. */
678	*puValue = 0;
679	return VINF_SUCCESS;
680	}
681
682
683	/** @callback_method_impl{FNCPUMWRMSR} */
684	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McgStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
685	{
686	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
687	/** @todo implement machine checks. */
688	return VINF_SUCCESS;
689	}
690
691
692	/** @callback_method_impl{FNCPUMRDMSR} */
693	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McgCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
694	{
695	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
696	/** @todo implement machine checks. */
697	*puValue = 0;
698	return VINF_SUCCESS;
699	}
700
701
702	/** @callback_method_impl{FNCPUMWRMSR} */
703	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McgCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
704	{
705	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
706	/** @todo implement machine checks. */
707	return VINF_SUCCESS;
708	}
709
710
711	/** @callback_method_impl{FNCPUMRDMSR} */
712	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32DebugCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
713	{
714	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
715	/** @todo implement IA32_DEBUGCTL. */
716	*puValue = 0;
717	return VINF_SUCCESS;
718	}
719
720
721	/** @callback_method_impl{FNCPUMWRMSR} */
722	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32DebugCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
723	{
724	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
725	/** @todo implement IA32_DEBUGCTL. */
726	return VINF_SUCCESS;
727	}
728
729
730	/** @callback_method_impl{FNCPUMRDMSR} */
731	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SmrrPhysBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
732	{
733	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
734	/** @todo implement intel SMM. */
735	*puValue = 0;
736	return VINF_SUCCESS;
737	}
738
739
740	/** @callback_method_impl{FNCPUMWRMSR} */
741	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SmrrPhysBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
742	{
743	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
744	/** @todo implement intel SMM. */
745	return VERR_CPUM_RAISE_GP_0;
746	}
747
748
749	/** @callback_method_impl{FNCPUMRDMSR} */
750	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SmrrPhysMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
751	{
752	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
753	/** @todo implement intel SMM. */
754	*puValue = 0;
755	return VINF_SUCCESS;
756	}
757
758
759	/** @callback_method_impl{FNCPUMWRMSR} */
760	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SmrrPhysMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
761	{
762	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
763	/** @todo implement intel SMM. */
764	return VERR_CPUM_RAISE_GP_0;
765	}
766
767
768	/** @callback_method_impl{FNCPUMRDMSR} */
769	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PlatformDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
770	{
771	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
772	/** @todo implement intel direct cache access (DCA)?? */
773	*puValue = 0;
774	return VINF_SUCCESS;
775	}
776
777
778	/** @callback_method_impl{FNCPUMWRMSR} */
779	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PlatformDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
780	{
781	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
782	/** @todo implement intel direct cache access (DCA)?? */
783	return VINF_SUCCESS;
784	}
785
786
787	/** @callback_method_impl{FNCPUMRDMSR} */
788	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32CpuDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
789	{
790	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
791	/** @todo implement intel direct cache access (DCA)?? */
792	*puValue = 0;
793	return VINF_SUCCESS;
794	}
795
796
797	/** @callback_method_impl{FNCPUMRDMSR} */
798	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32Dca0Cap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
799	{
800	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
801	/** @todo implement intel direct cache access (DCA)?? */
802	*puValue = 0;
803	return VINF_SUCCESS;
804	}
805
806
807	/** @callback_method_impl{FNCPUMWRMSR} */
808	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32Dca0Cap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
809	{
810	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
811	/** @todo implement intel direct cache access (DCA)?? */
812	return VINF_SUCCESS;
813	}
814
815
816	/** @callback_method_impl{FNCPUMRDMSR} */
817	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
818	{
819	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
820	/** @todo implement IA32_PERFEVTSEL0+. */
821	*puValue = 0;
822	return VINF_SUCCESS;
823	}
824
825
826	/** @callback_method_impl{FNCPUMWRMSR} */
827	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
828	{
829	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
830	/** @todo implement IA32_PERFEVTSEL0+. */
831	return VINF_SUCCESS;
832	}
833
834
835	/** @callback_method_impl{FNCPUMRDMSR} */
836	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
837	{
838	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
839	uint64_t uValue = pRange->uValue;
840
841	/* Always provide the max bus ratio for now. XNU expects it. */
842	uValue &= ~((UINT64_C(0x1f) << 40) \| RT_BIT_64(46));
843
844	PVM pVM = pVCpu->CTX_SUFF(pVM);
845	uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
846	uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
847	uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
848	if (uTscRatio > 0x1f)
849	uTscRatio = 0x1f;
850	uValue \|= (uint64_t)uTscRatio << 40;
851
852	*puValue = uValue;
853	return VINF_SUCCESS;
854	}
855
856
857	/** @callback_method_impl{FNCPUMWRMSR} */
858	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
859	{
860	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
861	/* Pentium4 allows writing, but all bits are ignored. */
862	return VINF_SUCCESS;
863	}
864
865
866	/** @callback_method_impl{FNCPUMRDMSR} */
867	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
868	{
869	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
870	/** @todo implement IA32_PERFCTL. */
871	*puValue = 0;
872	return VINF_SUCCESS;
873	}
874
875
876	/** @callback_method_impl{FNCPUMWRMSR} */
877	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
878	{
879	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
880	/** @todo implement IA32_PERFCTL. */
881	return VINF_SUCCESS;
882	}
883
884
885	/** @callback_method_impl{FNCPUMRDMSR} */
886	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32FixedCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
887	{
888	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
889	/** @todo implement IA32_FIXED_CTRn (fixed performance counters). */
890	*puValue = 0;
891	return VINF_SUCCESS;
892	}
893
894
895	/** @callback_method_impl{FNCPUMWRMSR} */
896	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32FixedCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
897	{
898	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
899	/** @todo implement IA32_FIXED_CTRn (fixed performance counters). */
900	return VINF_SUCCESS;
901	}
902
903
904	/** @callback_method_impl{FNCPUMRDMSR} */
905	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfCapabilities(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
906	{
907	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
908	/** @todo implement performance counters. */
909	*puValue = 0;
910	return VINF_SUCCESS;
911	}
912
913
914	/** @callback_method_impl{FNCPUMWRMSR} */
915	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfCapabilities(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
916	{
917	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
918	/** @todo implement performance counters. */
919	return VINF_SUCCESS;
920	}
921
922
923	/** @callback_method_impl{FNCPUMRDMSR} */
924	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32FixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
925	{
926	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
927	/** @todo implement performance counters. */
928	*puValue = 0;
929	return VINF_SUCCESS;
930	}
931
932
933	/** @callback_method_impl{FNCPUMWRMSR} */
934	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32FixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
935	{
936	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
937	/** @todo implement performance counters. */
938	return VINF_SUCCESS;
939	}
940
941
942	/** @callback_method_impl{FNCPUMRDMSR} */
943	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
944	{
945	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
946	/** @todo implement performance counters. */
947	*puValue = 0;
948	return VINF_SUCCESS;
949	}
950
951
952	/** @callback_method_impl{FNCPUMWRMSR} */
953	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
954	{
955	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
956	/** @todo implement performance counters. */
957	return VINF_SUCCESS;
958	}
959
960
961	/** @callback_method_impl{FNCPUMRDMSR} */
962	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
963	{
964	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
965	/** @todo implement performance counters. */
966	*puValue = 0;
967	return VINF_SUCCESS;
968	}
969
970
971	/** @callback_method_impl{FNCPUMWRMSR} */
972	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
973	{
974	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
975	/** @todo implement performance counters. */
976	return VINF_SUCCESS;
977	}
978
979
980	/** @callback_method_impl{FNCPUMRDMSR} */
981	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
982	{
983	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
984	/** @todo implement performance counters. */
985	*puValue = 0;
986	return VINF_SUCCESS;
987	}
988
989
990	/** @callback_method_impl{FNCPUMWRMSR} */
991	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
992	{
993	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
994	/** @todo implement performance counters. */
995	return VINF_SUCCESS;
996	}
997
998
999	/** @callback_method_impl{FNCPUMRDMSR} */
1000	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PebsEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1001	{
1002	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1003	/** @todo implement performance counters. */
1004	*puValue = 0;
1005	return VINF_SUCCESS;
1006	}
1007
1008
1009	/** @callback_method_impl{FNCPUMWRMSR} */
1010	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PebsEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1011	{
1012	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1013	/** @todo implement performance counters. */
1014	return VINF_SUCCESS;
1015	}
1016
1017
1018	/** @callback_method_impl{FNCPUMRDMSR} */
1019	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ClockModulation(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1020	{
1021	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1022	/** @todo implement IA32_CLOCK_MODULATION. */
1023	*puValue = 0;
1024	return VINF_SUCCESS;
1025	}
1026
1027
1028	/** @callback_method_impl{FNCPUMWRMSR} */
1029	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ClockModulation(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1030	{
1031	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1032	/** @todo implement IA32_CLOCK_MODULATION. */
1033	return VINF_SUCCESS;
1034	}
1035
1036
1037	/** @callback_method_impl{FNCPUMRDMSR} */
1038	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ThermInterrupt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1039	{
1040	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1041	/** @todo implement IA32_THERM_INTERRUPT. */
1042	*puValue = 0;
1043	return VINF_SUCCESS;
1044	}
1045
1046
1047	/** @callback_method_impl{FNCPUMWRMSR} */
1048	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ThermInterrupt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1049	{
1050	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1051	/** @todo implement IA32_THERM_STATUS. */
1052	return VINF_SUCCESS;
1053	}
1054
1055
1056	/** @callback_method_impl{FNCPUMRDMSR} */
1057	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ThermStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1058	{
1059	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1060	/** @todo implement IA32_THERM_STATUS. */
1061	*puValue = 0;
1062	return VINF_SUCCESS;
1063	}
1064
1065
1066	/** @callback_method_impl{FNCPUMWRMSR} */
1067	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ThermStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1068	{
1069	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1070	/** @todo implement IA32_THERM_INTERRUPT. */
1071	return VINF_SUCCESS;
1072	}
1073
1074
1075	/** @callback_method_impl{FNCPUMRDMSR} */
1076	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32Therm2Ctl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1077	{
1078	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1079	/** @todo implement IA32_THERM2_CTL. */
1080	*puValue = 0;
1081	return VINF_SUCCESS;
1082	}
1083
1084
1085	/** @callback_method_impl{FNCPUMWRMSR} */
1086	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32Therm2Ctl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1087	{
1088	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1089	/** @todo implement IA32_THERM2_CTL. */
1090	return VINF_SUCCESS;
1091	}
1092
1093
1094	/** @callback_method_impl{FNCPUMRDMSR} */
1095	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MiscEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1096	{
1097	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1098	*puValue = pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
1099	return VINF_SUCCESS;
1100	}
1101
1102
1103	/** @callback_method_impl{FNCPUMWRMSR} */
1104	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MiscEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1105	{
1106	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1107	#ifdef LOG_ENABLED
1108	uint64_t const uOld = pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
1109	#endif
1110
1111	/* Unsupported bits are generally ignored and stripped by the MSR range
1112	entry that got us here. So, we just need to preserve fixed bits. */
1113	pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = uValue
1114	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
1115	\| MSR_IA32_MISC_ENABLE_BTS_UNAVAIL;
1116
1117	Log(("CPUM: IA32_MISC_ENABLE; old=%#llx written=%#llx => %#llx\n",
1118	uOld, uValue, pVCpu->cpum.s.GuestMsrs.msr.MiscEnable));
1119
1120	/** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
1121	/** @todo Wire up MSR_IA32_MISC_ENABLE_XD_DISABLE. */
1122	return VINF_SUCCESS;
1123	}
1124
1125
1126	/** @callback_method_impl{FNCPUMRDMSR} */
1127	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McCtlStatusAddrMiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1128	{
1129	RT_NOREF_PV(pVCpu); RT_NOREF_PV(pRange);
1130
1131	/** @todo Implement machine check exception injection. */
1132	switch (idMsr & 3)
1133	{
1134	case 0:
1135	case 1:
1136	*puValue = 0;
1137	break;
1138
1139	/* The ADDR and MISC registers aren't accessible since the
1140	corresponding STATUS bits are zero. */
1141	case 2:
1142	Log(("CPUM: Reading IA32_MCi_ADDR %#x -> #GP\n", idMsr));
1143	return VERR_CPUM_RAISE_GP_0;
1144	case 3:
1145	Log(("CPUM: Reading IA32_MCi_MISC %#x -> #GP\n", idMsr));
1146	return VERR_CPUM_RAISE_GP_0;
1147	}
1148	return VINF_SUCCESS;
1149	}
1150
1151
1152	/** @callback_method_impl{FNCPUMWRMSR} */
1153	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McCtlStatusAddrMiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1154	{
1155	RT_NOREF_PV(pVCpu); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1156	switch (idMsr & 3)
1157	{
1158	case 0:
1159	/* Ignore writes to the CTL register. */
1160	break;
1161
1162	case 1:
1163	/* According to specs, the STATUS register can only be written to
1164	with the value 0. VBoxCpuReport thinks different for a
1165	Pentium M Dothan, but implementing according to specs now. */
1166	if (uValue != 0)
1167	{
1168	Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_STATUS %#x -> #GP\n", uValue, idMsr));
1169	return VERR_CPUM_RAISE_GP_0;
1170	}
1171	break;
1172
1173	/* Specs states that ADDR and MISC can be cleared by writing zeros.
1174	Writing 1s will GP. Need to figure out how this relates to the
1175	ADDRV and MISCV status flags. If writing is independent of those
1176	bits, we need to know whether the CPU really implements them since
1177	that is exposed by writing 0 to them.
1178	Implementing the solution with the fewer GPs for now. */
1179	case 2:
1180	if (uValue != 0)
1181	{
1182	Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_ADDR %#x -> #GP\n", uValue, idMsr));
1183	return VERR_CPUM_RAISE_GP_0;
1184	}
1185	break;
1186	case 3:
1187	if (uValue != 0)
1188	{
1189	Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_MISC %#x -> #GP\n", uValue, idMsr));
1190	return VERR_CPUM_RAISE_GP_0;
1191	}
1192	break;
1193	}
1194	return VINF_SUCCESS;
1195	}
1196
1197
1198	/** @callback_method_impl{FNCPUMRDMSR} */
1199	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McNCtl2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1200	{
1201	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1202	/** @todo Implement machine check exception injection. */
1203	*puValue = 0;
1204	return VINF_SUCCESS;
1205	}
1206
1207
1208	/** @callback_method_impl{FNCPUMWRMSR} */
1209	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McNCtl2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1210	{
1211	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1212	/** @todo Implement machine check exception injection. */
1213	return VINF_SUCCESS;
1214	}
1215
1216
1217	/** @callback_method_impl{FNCPUMRDMSR} */
1218	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32DsArea(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1219	{
1220	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1221	/** @todo implement IA32_DS_AREA. */
1222	*puValue = 0;
1223	return VINF_SUCCESS;
1224	}
1225
1226
1227	/** @callback_method_impl{FNCPUMWRMSR} */
1228	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32DsArea(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1229	{
1230	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1231	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1232	return VINF_SUCCESS;
1233	}
1234
1235
1236	/** @callback_method_impl{FNCPUMRDMSR} */
1237	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32TscDeadline(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1238	{
1239	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1240	/** @todo implement TSC deadline timer. */
1241	*puValue = 0;
1242	return VINF_SUCCESS;
1243	}
1244
1245
1246	/** @callback_method_impl{FNCPUMWRMSR} */
1247	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32TscDeadline(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1248	{
1249	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1250	/** @todo implement TSC deadline timer. */
1251	return VINF_SUCCESS;
1252	}
1253
1254
1255	/** @callback_method_impl{FNCPUMRDMSR} */
1256	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32X2ApicN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1257	{
1258	RT_NOREF_PV(pRange);
1259	return APICReadMsr(pVCpu, idMsr, puValue);
1260	}
1261
1262
1263	/** @callback_method_impl{FNCPUMWRMSR} */
1264	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32X2ApicN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1265	{
1266	RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1267	return APICWriteMsr(pVCpu, idMsr, uValue);
1268	}
1269
1270
1271	/** @callback_method_impl{FNCPUMRDMSR} */
1272	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32DebugInterface(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1273	{
1274	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1275	/** @todo IA32_DEBUG_INTERFACE (no docs) */
1276	*puValue = 0;
1277	return VINF_SUCCESS;
1278	}
1279
1280
1281	/** @callback_method_impl{FNCPUMWRMSR} */
1282	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32DebugInterface(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1283	{
1284	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1285	/** @todo IA32_DEBUG_INTERFACE (no docs) */
1286	return VINF_SUCCESS;
1287	}
1288
1289
1290	/** @callback_method_impl{FNCPUMRDMSR} */
1291	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxBasic(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1292	{
1293	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1294	PCCPUMFEATURES pGuestFeatures = &pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures;
1295	if (pGuestFeatures->fVmx)
1296	{
1297	*puValue = RT_BF_MAKE(VMX_BF_BASIC_VMCS_ID, VMX_E_VMCS_REVISION_ID )
1298	\| RT_BF_MAKE(VMX_BF_BASIC_DUAL_MON, 0 )
1299	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_MEM_TYPE, VMX_BASIC_MEM_TYPE_WB )
1300	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_INS_OUTS, pGuestFeatures->fVmxInsOutInfo)
1301	\| RT_BF_MAKE(VMX_BF_BASIC_TRUE_CTLS, 0 );
1302	}
1303	else
1304	*puValue = 0;
1305	return VINF_SUCCESS;
1306	}
1307
1308
1309	/** @callback_method_impl{FNCPUMRDMSR} */
1310	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxPinbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1311	{
1312	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1313	PCCPUMFEATURES pGuestFeatures = &pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures;
1314	if (pGuestFeatures->fVmx)
1315	{
1316	uint32_t const fFeatures = (pGuestFeatures->fVmxExtIntExit << VMX_BF_PIN_CTLS_EXT_INT_EXIT_SHIFT )
1317	\| (pGuestFeatures->fVmxNmiExit << VMX_BF_PIN_CTLS_NMI_EXIT_SHIFT )
1318	\| (pGuestFeatures->fVmxVirtNmi << VMX_BF_PIN_CTLS_VIRT_NMI_SHIFT )
1319	\| (pGuestFeatures->fVmxPreemptTimer << VMX_BF_PIN_CTLS_PREEMPT_TIMER_SHIFT);
1320	uint32_t const fVal = VMX_PIN_CTLS_DEFAULT1;
1321	uint32_t const fZap = fFeatures \| VMX_PIN_CTLS_DEFAULT1;
1322	AssertMsgReturn((fVal & fZap) == fVal, ("fVal=%#RX32 fZap=%#RX32 fFeatures=%#RX32\n", fVal, fZap, fFeatures),
1323	VERR_CPUM_INVALID_HWVIRT_FEAT_COMBO);
1324	*puValue = RT_MAKE_U64(fVal, fZap);
1325	}
1326	else
1327	*puValue = 0;
1328	return VINF_SUCCESS;
1329	}
1330
1331
1332	/** @callback_method_impl{FNCPUMRDMSR} */
1333	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxProcbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1334	{
1335	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1336	PCCPUMFEATURES pGuestFeatures = &pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures;
1337	if (pGuestFeatures->fVmx)
1338	{
1339	uint32_t const fFeatures = (pGuestFeatures->fVmxIntWindowExit << VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_SHIFT )
1340	\| (pGuestFeatures->fVmxTscOffsetting << VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_SHIFT)
1341	\| (pGuestFeatures->fVmxHltExit << VMX_BF_PROC_CTLS_HLT_EXIT_SHIFT )
1342	\| (pGuestFeatures->fVmxInvlpgExit << VMX_BF_PROC_CTLS_INVLPG_EXIT_SHIFT )
1343	\| (pGuestFeatures->fVmxMwaitExit << VMX_BF_PROC_CTLS_MWAIT_EXIT_SHIFT )
1344	\| (pGuestFeatures->fVmxRdpmcExit << VMX_BF_PROC_CTLS_RDPMC_EXIT_SHIFT )
1345	\| (pGuestFeatures->fVmxRdtscExit << VMX_BF_PROC_CTLS_RDTSC_EXIT_SHIFT )
1346	\| (pGuestFeatures->fVmxCr3LoadExit << VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_SHIFT )
1347	\| (pGuestFeatures->fVmxCr3StoreExit << VMX_BF_PROC_CTLS_CR3_STORE_EXIT_SHIFT )
1348	\| (pGuestFeatures->fVmxCr8LoadExit << VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_SHIFT )
1349	\| (pGuestFeatures->fVmxCr8StoreExit << VMX_BF_PROC_CTLS_CR8_STORE_EXIT_SHIFT )
1350	\| (pGuestFeatures->fVmxTprShadow << VMX_BF_PROC_CTLS_USE_TPR_SHADOW_SHIFT )
1351	\| (pGuestFeatures->fVmxNmiWindowExit << VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_SHIFT )
1352	\| (pGuestFeatures->fVmxMovDRxExit << VMX_BF_PROC_CTLS_MOV_DR_EXIT_SHIFT )
1353	\| (pGuestFeatures->fVmxUncondIoExit << VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_SHIFT )
1354	\| (pGuestFeatures->fVmxUseIoBitmaps << VMX_BF_PROC_CTLS_USE_IO_BITMAPS_SHIFT )
1355	\| (pGuestFeatures->fVmxMonitorTrapFlag << VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_SHIFT )
1356	\| (pGuestFeatures->fVmxUseMsrBitmaps << VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_SHIFT )
1357	\| (pGuestFeatures->fVmxMonitorExit << VMX_BF_PROC_CTLS_MONITOR_EXIT_SHIFT )
1358	\| (pGuestFeatures->fVmxPauseExit << VMX_BF_PROC_CTLS_PAUSE_EXIT_SHIFT )
1359	\| (pGuestFeatures->fVmxSecondaryExecCtls << VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_SHIFT);
1360	uint32_t const fVal = VMX_PROC_CTLS_DEFAULT1;
1361	uint32_t const fZap = fFeatures \| VMX_PROC_CTLS_DEFAULT1;
1362	AssertMsgReturn((fVal & fZap) == fVal, ("fVal=%#RX32 fZap=%#RX32 fFeatures=%#RX32\n", fVal, fZap, fFeatures),
1363	VERR_CPUM_INVALID_HWVIRT_FEAT_COMBO);
1364	*puValue = RT_MAKE_U64(fVal, fZap);
1365	}
1366	else
1367	*puValue = 0;
1368	return VINF_SUCCESS;
1369	}
1370
1371
1372	/** @callback_method_impl{FNCPUMRDMSR} */
1373	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxExitCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1374	{
1375	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1376	PCCPUMFEATURES pGuestFeatures = &pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures;
1377	if (pGuestFeatures->fVmx)
1378	{
1379	uint32_t const fFeatures = (pGuestFeatures->fVmxExitSaveDebugCtls << VMX_BF_EXIT_CTLS_SAVE_DEBUG_SHIFT )
1380	\| (pGuestFeatures->fVmxHostAddrSpaceSize << VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_SHIFT)
1381	\| (pGuestFeatures->fVmxExitAckExtInt << VMX_BF_EXIT_CTLS_ACK_EXT_INT_SHIFT )
1382	\| (pGuestFeatures->fVmxExitSaveEferMsr << VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_SHIFT )
1383	\| (pGuestFeatures->fVmxExitLoadEferMsr << VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_SHIFT )
1384	\| (pGuestFeatures->fVmxSavePreemptTimer << VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_SHIFT );
1385	uint32_t const fVal = VMX_EXIT_CTLS_DEFAULT1;
1386	uint32_t const fZap = fFeatures \| VMX_EXIT_CTLS_DEFAULT1;
1387	AssertMsgReturn((fVal & fZap) == fVal, ("fVal=%#RX32 fZap=%#RX32 fFeatures=%#RX32\n", fVal, fZap, fFeatures),
1388	VERR_CPUM_INVALID_HWVIRT_FEAT_COMBO);
1389	*puValue = RT_MAKE_U64(fVal, fZap);
1390	}
1391	else
1392	*puValue = 0;
1393	return VINF_SUCCESS;
1394	}
1395
1396
1397	/** @callback_method_impl{FNCPUMRDMSR} */
1398	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxEntryCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1399	{
1400	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1401	PCCPUMFEATURES pGuestFeatures = &pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures;
1402	if (pGuestFeatures->fVmx)
1403	{
1404	uint32_t const fFeatures = (pGuestFeatures->fVmxEntryLoadDebugCtls << VMX_BF_ENTRY_CTLS_LOAD_DEBUG_SHIFT )
1405	\| (pGuestFeatures->fVmxIa32eModeGuest << VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_SHIFT)
1406	\| (pGuestFeatures->fVmxEntryLoadEferMsr << VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_SHIFT );
1407	uint32_t const fDefault1 = VMX_ENTRY_CTLS_DEFAULT1;
1408	uint32_t const fVal = fDefault1;
1409	uint32_t const fZap = fFeatures \| fDefault1;
1410	AssertMsgReturn((fVal & fZap) == fVal, ("fVal=%#RX32 fZap=%#RX32 fFeatures=%#RX32\n", fVal, fZap, fFeatures),
1411	VERR_CPUM_INVALID_HWVIRT_FEAT_COMBO);
1412	*puValue = RT_MAKE_U64(fVal, fZap);
1413	}
1414	else
1415	*puValue = 0;
1416	return VINF_SUCCESS;
1417	}
1418
1419
1420	/** @callback_method_impl{FNCPUMRDMSR} */
1421	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxMisc(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1422	{
1423	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1424	PCCPUMFEATURES pGuestFeatures = &pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures;
1425	if (pGuestFeatures->fVmx)
1426	{
1427	/** @todo Think about this especially preemption timer TSC shifts. */
1428	*puValue = 0;
1429	}
1430	else
1431	*puValue = 0;
1432	return VINF_SUCCESS;
1433	}
1434
1435
1436	/** @callback_method_impl{FNCPUMRDMSR} */
1437	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr0Fixed0(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1438	{
1439	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1440	PCCPUMFEATURES pGuestFeatures = &pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures;
1441	if (pGuestFeatures->fVmx)
1442	*puValue = VMX_E_CR0_FIXED0;
1443	else
1444	*puValue = 0;
1445	return VINF_SUCCESS;
1446	}
1447
1448
1449	/** @callback_method_impl{FNCPUMRDMSR} */
1450	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr0Fixed1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1451	{
1452	RT_NOREF_PV(pRange);
1453	PCCPUMFEATURES pGuestFeatures = &pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures;
1454	if (pGuestFeatures->fVmx)
1455	{
1456	int rc = HMVmxGetHostMsr(pVCpu->CTX_SUFF(pVM), idMsr, puValue);
1457	AssertRCReturn(rc, rc);
1458	puValue \|= VMX_E_CR0_FIXED0; / Make sure the CR0 MB1 bits are not clear. */
1459	}
1460	else
1461	*puValue = 0;
1462	return VINF_SUCCESS;
1463	}
1464
1465
1466	/** @callback_method_impl{FNCPUMRDMSR} */
1467	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr4Fixed0(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1468	{
1469	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1470	PCCPUMFEATURES pGuestFeatures = &pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures;
1471	if (pGuestFeatures->fVmx)
1472	*puValue = VMX_E_CR4_FIXED0;
1473	else
1474	*puValue = 0;
1475	return VINF_SUCCESS;
1476	}
1477
1478
1479	/** @callback_method_impl{FNCPUMRDMSR} */
1480	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr4Fixed1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1481	{
1482	RT_NOREF_PV(pRange);
1483	PCCPUMFEATURES pGuestFeatures = &pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures;
1484	if (pGuestFeatures->fVmx)
1485	{
1486	int rc = HMVmxGetHostMsr(pVCpu->CTX_SUFF(pVM), idMsr, puValue);
1487	AssertRCReturn(rc, rc);
1488	puValue \|= VMX_E_CR4_FIXED0; / Make sure the CR4 MB1 bits are not clear. */
1489	}
1490	else
1491	*puValue = 0;
1492	return VINF_SUCCESS;
1493	}
1494
1495
1496	/** @callback_method_impl{FNCPUMRDMSR} */
1497	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxVmcsEnum(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1498	{
1499	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1500	*puValue = 0;
1501	return VINF_SUCCESS;
1502	}
1503
1504
1505	/** @callback_method_impl{FNCPUMRDMSR} */
1506	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxProcBasedCtls2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1507	{
1508	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1509	PCCPUMFEATURES pGuestFeatures = &pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures;
1510	if (pGuestFeatures->fVmx)
1511	{
1512	uint32_t const fFeatures = (pGuestFeatures->fVmxVirtApicAccess << VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_SHIFT )
1513	\| (pGuestFeatures->fVmxEpt << VMX_BF_PROC_CTLS2_EPT_SHIFT )
1514	\| (pGuestFeatures->fVmxDescTableExit << VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_SHIFT )
1515	\| (pGuestFeatures->fVmxRdtscp << VMX_BF_PROC_CTLS2_RDTSCP_SHIFT )
1516	\| (pGuestFeatures->fVmxVirtX2ApicAccess << VMX_BF_PROC_CTLS2_VIRT_X2APIC_ACCESS_SHIFT)
1517	\| (pGuestFeatures->fVmxVpid << VMX_BF_PROC_CTLS2_VPID_SHIFT )
1518	\| (pGuestFeatures->fVmxWbinvdExit << VMX_BF_PROC_CTLS2_WBINVD_EXIT_SHIFT )
1519	\| (pGuestFeatures->fVmxUnrestrictedGuest << VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_SHIFT)
1520	\| (pGuestFeatures->fVmxPauseLoopExit << VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_SHIFT )
1521	\| (pGuestFeatures->fVmxInvpcid << VMX_BF_PROC_CTLS2_INVPCID_SHIFT );
1522	uint32_t const fVal = 0;
1523	uint32_t const fZap = fFeatures;
1524	*puValue = RT_MAKE_U64(fVal, fZap);
1525	}
1526	else
1527	*puValue = 0;
1528	return VINF_SUCCESS;
1529	}
1530
1531
1532	/** @callback_method_impl{FNCPUMRDMSR} */
1533	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxEptVpidCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1534	{
1535	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1536	*puValue = 0;
1537	return VINF_SUCCESS;
1538	}
1539
1540
1541	/** @callback_method_impl{FNCPUMRDMSR} */
1542	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTruePinbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1543	{
1544	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1545	*puValue = 0;
1546	return VINF_SUCCESS;
1547	}
1548
1549
1550	/** @callback_method_impl{FNCPUMRDMSR} */
1551	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTrueProcbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1552	{
1553	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1554	*puValue = 0;
1555	return VINF_SUCCESS;
1556	}
1557
1558
1559	/** @callback_method_impl{FNCPUMRDMSR} */
1560	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTrueExitCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1561	{
1562	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1563	*puValue = 0;
1564	return VINF_SUCCESS;
1565	}
1566
1567
1568	/** @callback_method_impl{FNCPUMRDMSR} */
1569	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTrueEntryCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1570	{
1571	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1572	*puValue = 0;
1573	return VINF_SUCCESS;
1574	}
1575
1576
1577	/** @callback_method_impl{FNCPUMRDMSR} */
1578	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxVmFunc(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1579	{
1580	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1581	*puValue = 0;
1582	return VINF_SUCCESS;
1583	}
1584
1585
1586	/** @callback_method_impl{FNCPUMRDMSR} */
1587	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SpecCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1588	{
1589	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1590	*puValue = pVCpu->cpum.s.GuestMsrs.msr.SpecCtrl;
1591	return VINF_SUCCESS;
1592	}
1593
1594
1595	/** @callback_method_impl{FNCPUMWRMSR} */
1596	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SpecCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1597	{
1598	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1599
1600	/* NB: The STIBP bit can be set even when IBRS is present, regardless of whether STIBP is actually implemented. */
1601	if (uValue & ~(MSR_IA32_SPEC_CTRL_F_IBRS \| MSR_IA32_SPEC_CTRL_F_STIBP))
1602	{
1603	Log(("CPUM: Invalid IA32_SPEC_CTRL bits (trying to write %#llx)\n", uValue));
1604	return VERR_CPUM_RAISE_GP_0;
1605	}
1606
1607	pVCpu->cpum.s.GuestMsrs.msr.SpecCtrl = uValue;
1608	return VINF_SUCCESS;
1609	}
1610
1611
1612	/** @callback_method_impl{FNCPUMWRMSR} */
1613	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PredCmd(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1614	{
1615	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1616	return VINF_SUCCESS;
1617	}
1618
1619
1620	/** @callback_method_impl{FNCPUMRDMSR} */
1621	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ArchCapabilities(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1622	{
1623	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1624	*puValue = pVCpu->cpum.s.GuestMsrs.msr.ArchCaps;
1625	return VINF_SUCCESS;
1626	}
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639	/*
1640	* AMD64
1641	* AMD64
1642	* AMD64
1643	*/
1644
1645
1646	/** @callback_method_impl{FNCPUMRDMSR} */
1647	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64Efer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1648	{
1649	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1650	*puValue = pVCpu->cpum.s.Guest.msrEFER;
1651	return VINF_SUCCESS;
1652	}
1653
1654
1655	/** @callback_method_impl{FNCPUMWRMSR} */
1656	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64Efer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1657	{
1658	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1659	uint64_t uValidatedEfer;
1660	uint64_t const uOldEfer = pVCpu->cpum.s.Guest.msrEFER;
1661	int rc = CPUMQueryValidatedGuestEfer(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.s.Guest.cr0, uOldEfer, uValue, &uValidatedEfer);
1662	if (RT_FAILURE(rc))
1663	return VERR_CPUM_RAISE_GP_0;
1664
1665	CPUMSetGuestMsrEferNoCheck(pVCpu, uOldEfer, uValidatedEfer);
1666	return VINF_SUCCESS;
1667	}
1668
1669
1670	/** @callback_method_impl{FNCPUMRDMSR} */
1671	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64SyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1672	{
1673	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1674	*puValue = pVCpu->cpum.s.Guest.msrSTAR;
1675	return VINF_SUCCESS;
1676	}
1677
1678
1679	/** @callback_method_impl{FNCPUMWRMSR} */
1680	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64SyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1681	{
1682	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1683	pVCpu->cpum.s.Guest.msrSTAR = uValue;
1684	return VINF_SUCCESS;
1685	}
1686
1687
1688	/** @callback_method_impl{FNCPUMRDMSR} */
1689	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64LongSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1690	{
1691	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1692	*puValue = pVCpu->cpum.s.Guest.msrLSTAR;
1693	return VINF_SUCCESS;
1694	}
1695
1696
1697	/** @callback_method_impl{FNCPUMWRMSR} */
1698	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64LongSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1699	{
1700	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1701	if (!X86_IS_CANONICAL(uValue))
1702	{
1703	Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
1704	return VERR_CPUM_RAISE_GP_0;
1705	}
1706	pVCpu->cpum.s.Guest.msrLSTAR = uValue;
1707	return VINF_SUCCESS;
1708	}
1709
1710
1711	/** @callback_method_impl{FNCPUMRDMSR} */
1712	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64CompSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1713	{
1714	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1715	*puValue = pVCpu->cpum.s.Guest.msrCSTAR;
1716	return VINF_SUCCESS;
1717	}
1718
1719
1720	/** @callback_method_impl{FNCPUMWRMSR} */
1721	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64CompSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1722	{
1723	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1724	if (!X86_IS_CANONICAL(uValue))
1725	{
1726	Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
1727	return VERR_CPUM_RAISE_GP_0;
1728	}
1729	pVCpu->cpum.s.Guest.msrCSTAR = uValue;
1730	return VINF_SUCCESS;
1731	}
1732
1733
1734	/** @callback_method_impl{FNCPUMRDMSR} */
1735	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64SyscallFlagMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1736	{
1737	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1738	*puValue = pVCpu->cpum.s.Guest.msrSFMASK;
1739	return VINF_SUCCESS;
1740	}
1741
1742
1743	/** @callback_method_impl{FNCPUMWRMSR} */
1744	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64SyscallFlagMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1745	{
1746	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1747	pVCpu->cpum.s.Guest.msrSFMASK = uValue;
1748	return VINF_SUCCESS;
1749	}
1750
1751
1752	/** @callback_method_impl{FNCPUMRDMSR} */
1753	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64FsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1754	{
1755	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1756	*puValue = pVCpu->cpum.s.Guest.fs.u64Base;
1757	return VINF_SUCCESS;
1758	}
1759
1760
1761	/** @callback_method_impl{FNCPUMWRMSR} */
1762	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64FsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1763	{
1764	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1765	pVCpu->cpum.s.Guest.fs.u64Base = uValue;
1766	return VINF_SUCCESS;
1767	}
1768
1769
1770	/** @callback_method_impl{FNCPUMRDMSR} */
1771	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64GsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1772	{
1773	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1774	*puValue = pVCpu->cpum.s.Guest.gs.u64Base;
1775	return VINF_SUCCESS;
1776	}
1777
1778	/** @callback_method_impl{FNCPUMWRMSR} */
1779	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64GsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1780	{
1781	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1782	pVCpu->cpum.s.Guest.gs.u64Base = uValue;
1783	return VINF_SUCCESS;
1784	}
1785
1786
1787
1788	/** @callback_method_impl{FNCPUMRDMSR} */
1789	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64KernelGsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1790	{
1791	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1792	*puValue = pVCpu->cpum.s.Guest.msrKERNELGSBASE;
1793	return VINF_SUCCESS;
1794	}
1795
1796	/** @callback_method_impl{FNCPUMWRMSR} */
1797	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64KernelGsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1798	{
1799	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1800	pVCpu->cpum.s.Guest.msrKERNELGSBASE = uValue;
1801	return VINF_SUCCESS;
1802	}
1803
1804
1805	/** @callback_method_impl{FNCPUMRDMSR} */
1806	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64TscAux(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1807	{
1808	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1809	*puValue = pVCpu->cpum.s.GuestMsrs.msr.TscAux;
1810	return VINF_SUCCESS;
1811	}
1812
1813	/** @callback_method_impl{FNCPUMWRMSR} */
1814	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64TscAux(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1815	{
1816	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1817	pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
1818	return VINF_SUCCESS;
1819	}
1820
1821
1822	/*
1823	* Intel specific
1824	* Intel specific
1825	* Intel specific
1826	*/
1827
1828	/** @callback_method_impl{FNCPUMRDMSR} */
1829	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelEblCrPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1830	{
1831	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1832	/** @todo recalc clock frequency ratio? */
1833	*puValue = pRange->uValue;
1834	return VINF_SUCCESS;
1835	}
1836
1837
1838	/** @callback_method_impl{FNCPUMWRMSR} */
1839	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelEblCrPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1840	{
1841	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1842	/** @todo Write EBL_CR_POWERON: Remember written bits. */
1843	return VINF_SUCCESS;
1844	}
1845
1846
1847	/** @callback_method_impl{FNCPUMRDMSR} */
1848	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7CoreThreadCount(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1849	{
1850	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1851
1852	/* Note! According to cpuid_set_info in XNU (10.7.0), Westmere CPU only
1853	have a 4-bit core count. */
1854	uint16_t cCores = pVCpu->CTX_SUFF(pVM)->cCpus;
1855	uint16_t cThreads = cCores; /** @todo hyper-threading. */
1856	*puValue = RT_MAKE_U32(cThreads, cCores);
1857	return VINF_SUCCESS;
1858	}
1859
1860
1861	/** @callback_method_impl{FNCPUMRDMSR} */
1862	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP4EbcHardPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1863	{
1864	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1865	/** @todo P4 hard power on config */
1866	*puValue = pRange->uValue;
1867	return VINF_SUCCESS;
1868	}
1869
1870
1871	/** @callback_method_impl{FNCPUMWRMSR} */
1872	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP4EbcHardPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1873	{
1874	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1875	/** @todo P4 hard power on config */
1876	return VINF_SUCCESS;
1877	}
1878
1879
1880	/** @callback_method_impl{FNCPUMRDMSR} */
1881	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP4EbcSoftPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1882	{
1883	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1884	/** @todo P4 soft power on config */
1885	*puValue = pRange->uValue;
1886	return VINF_SUCCESS;
1887	}
1888
1889
1890	/** @callback_method_impl{FNCPUMWRMSR} */
1891	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP4EbcSoftPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1892	{
1893	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1894	/** @todo P4 soft power on config */
1895	return VINF_SUCCESS;
1896	}
1897
1898
1899	/** @callback_method_impl{FNCPUMRDMSR} */
1900	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP4EbcFrequencyId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1901	{
1902	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1903
1904	uint64_t uValue;
1905	PVM pVM = pVCpu->CTX_SUFF(pVM);
1906	uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
1907	if (pVM->cpum.s.GuestFeatures.uModel >= 2)
1908	{
1909	if (uScalableBusHz <= CPUM_SBUSFREQ_100MHZ && pVM->cpum.s.GuestFeatures.uModel <= 2)
1910	{
1911	uScalableBusHz = CPUM_SBUSFREQ_100MHZ;
1912	uValue = 0;
1913	}
1914	else if (uScalableBusHz <= CPUM_SBUSFREQ_133MHZ)
1915	{
1916	uScalableBusHz = CPUM_SBUSFREQ_133MHZ;
1917	uValue = 1;
1918	}
1919	else if (uScalableBusHz <= CPUM_SBUSFREQ_167MHZ)
1920	{
1921	uScalableBusHz = CPUM_SBUSFREQ_167MHZ;
1922	uValue = 3;
1923	}
1924	else if (uScalableBusHz <= CPUM_SBUSFREQ_200MHZ)
1925	{
1926	uScalableBusHz = CPUM_SBUSFREQ_200MHZ;
1927	uValue = 2;
1928	}
1929	else if (uScalableBusHz <= CPUM_SBUSFREQ_267MHZ && pVM->cpum.s.GuestFeatures.uModel > 2)
1930	{
1931	uScalableBusHz = CPUM_SBUSFREQ_267MHZ;
1932	uValue = 0;
1933	}
1934	else
1935	{
1936	uScalableBusHz = CPUM_SBUSFREQ_333MHZ;
1937	uValue = 6;
1938	}
1939	uValue <<= 16;
1940
1941	uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
1942	uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
1943	uValue \|= (uint32_t)uTscRatio << 24;
1944
1945	uValue \|= pRange->uValue & ~UINT64_C(0xff0f0000);
1946	}
1947	else
1948	{
1949	/* Probably more stuff here, but intel doesn't want to tell us. */
1950	uValue = pRange->uValue;
1951	uValue &= ~(RT_BIT_64(21) \| RT_BIT_64(22) \| RT_BIT_64(23)); /* 100 MHz is only documented value */
1952	}
1953
1954	*puValue = uValue;
1955	return VINF_SUCCESS;
1956	}
1957
1958
1959	/** @callback_method_impl{FNCPUMWRMSR} */
1960	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP4EbcFrequencyId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1961	{
1962	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1963	/** @todo P4 bus frequency config */
1964	return VINF_SUCCESS;
1965	}
1966
1967
1968	/** @callback_method_impl{FNCPUMRDMSR} */
1969	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP6FsbFrequency(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1970	{
1971	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1972
1973	/* Convert the scalable bus frequency to the encoding in the intel manual (for core+). */
1974	uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVCpu->CTX_SUFF(pVM));
1975	if (uScalableBusHz <= CPUM_SBUSFREQ_100MHZ)
1976	*puValue = 5;
1977	else if (uScalableBusHz <= CPUM_SBUSFREQ_133MHZ)
1978	*puValue = 1;
1979	else if (uScalableBusHz <= CPUM_SBUSFREQ_167MHZ)
1980	*puValue = 3;
1981	else if (uScalableBusHz <= CPUM_SBUSFREQ_200MHZ)
1982	*puValue = 2;
1983	else if (uScalableBusHz <= CPUM_SBUSFREQ_267MHZ)
1984	*puValue = 0;
1985	else if (uScalableBusHz <= CPUM_SBUSFREQ_333MHZ)
1986	*puValue = 4;
1987	else /if (uScalableBusHz <= CPUM_SBUSFREQ_400MHZ)/
1988	*puValue = 6;
1989
1990	*puValue \|= pRange->uValue & ~UINT64_C(0x7);
1991
1992	return VINF_SUCCESS;
1993	}
1994
1995
1996	/** @callback_method_impl{FNCPUMRDMSR} */
1997	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelPlatformInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1998	{
1999	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2000
2001	/* Just indicate a fixed TSC, no turbo boost, no programmable anything. */
2002	PVM pVM = pVCpu->CTX_SUFF(pVM);
2003	uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
2004	uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
2005	uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
2006	uint64_t uValue = ((uint32_t)uTscRatio << 8) /* TSC invariant frequency. */
2007	\| ((uint64_t)uTscRatio << 40); /* The max turbo frequency. */
2008
2009	/* Ivy bridge has a minimum operating ratio as well. */
2010	if (true) /** @todo detect sandy bridge. */
2011	uValue \|= (uint64_t)uTscRatio << 48;
2012
2013	*puValue = uValue;
2014	return VINF_SUCCESS;
2015	}
2016
2017
2018	/** @callback_method_impl{FNCPUMRDMSR} */
2019	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelFlexRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2020	{
2021	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2022
2023	uint64_t uValue = pRange->uValue & ~UINT64_C(0x1ff00);
2024
2025	PVM pVM = pVCpu->CTX_SUFF(pVM);
2026	uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
2027	uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
2028	uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
2029	uValue \|= (uint32_t)uTscRatio << 8;
2030
2031	*puValue = uValue;
2032	return VINF_SUCCESS;
2033	}
2034
2035
2036	/** @callback_method_impl{FNCPUMWRMSR} */
2037	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelFlexRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2038	{
2039	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2040	/** @todo implement writing MSR_FLEX_RATIO. */
2041	return VINF_SUCCESS;
2042	}
2043
2044
2045	/** @callback_method_impl{FNCPUMRDMSR} */
2046	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelPkgCStConfigControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2047	{
2048	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2049	*puValue = pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl;
2050	return VINF_SUCCESS;
2051	}
2052
2053
2054	/** @callback_method_impl{FNCPUMWRMSR} */
2055	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelPkgCStConfigControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2056	{
2057	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
2058
2059	if (pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl & RT_BIT_64(15))
2060	{
2061	Log(("CPUM: WRMSR %#x (%s), %#llx: Write protected -> #GP\n", idMsr, pRange->szName, uValue));
2062	return VERR_CPUM_RAISE_GP_0;
2063	}
2064	#if 0 /** @todo check what real (old) hardware does. */
2065	if ((uValue & 7) >= 5)
2066	{
2067	Log(("CPUM: WRMSR %#x (%s), %#llx: Invalid limit (%d) -> #GP\n", idMsr, pRange->szName, uValue, (uint32_t)(uValue & 7)));
2068	return VERR_CPUM_RAISE_GP_0;
2069	}
2070	#endif
2071	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = uValue;
2072	return VINF_SUCCESS;
2073	}
2074
2075
2076	/** @callback_method_impl{FNCPUMRDMSR} */
2077	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelPmgIoCaptureBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2078	{
2079	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2080	/** @todo implement I/O mwait wakeup. */
2081	*puValue = 0;
2082	return VINF_SUCCESS;
2083	}
2084
2085
2086	/** @callback_method_impl{FNCPUMWRMSR} */
2087	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelPmgIoCaptureBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2088	{
2089	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2090	/** @todo implement I/O mwait wakeup. */
2091	return VINF_SUCCESS;
2092	}
2093
2094
2095	/** @callback_method_impl{FNCPUMRDMSR} */
2096	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchFromToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2097	{
2098	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2099	/** @todo implement last branch records. */
2100	*puValue = 0;
2101	return VINF_SUCCESS;
2102	}
2103
2104
2105	/** @callback_method_impl{FNCPUMWRMSR} */
2106	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchFromToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2107	{
2108	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2109	/** @todo implement last branch records. */
2110	return VINF_SUCCESS;
2111	}
2112
2113
2114	/** @callback_method_impl{FNCPUMRDMSR} */
2115	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchFromN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2116	{
2117	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2118	/** @todo implement last branch records. */
2119	*puValue = 0;
2120	return VINF_SUCCESS;
2121	}
2122
2123
2124	/** @callback_method_impl{FNCPUMWRMSR} */
2125	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchFromN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2126	{
2127	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
2128	/** @todo implement last branch records. */
2129	/** @todo Probing indicates that bit 63 is settable on SandyBridge, at least
2130	* if the rest of the bits are zero. Automatic sign extending?
2131	* Investigate! */
2132	if (!X86_IS_CANONICAL(uValue))
2133	{
2134	Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
2135	return VERR_CPUM_RAISE_GP_0;
2136	}
2137	return VINF_SUCCESS;
2138	}
2139
2140
2141	/** @callback_method_impl{FNCPUMRDMSR} */
2142	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2143	{
2144	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2145	/** @todo implement last branch records. */
2146	*puValue = 0;
2147	return VINF_SUCCESS;
2148	}
2149
2150
2151	/** @callback_method_impl{FNCPUMWRMSR} */
2152	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2153	{
2154	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2155	/** @todo implement last branch records. */
2156	/** @todo Probing indicates that bit 63 is settable on SandyBridge, at least
2157	* if the rest of the bits are zero. Automatic sign extending?
2158	* Investigate! */
2159	if (!X86_IS_CANONICAL(uValue))
2160	{
2161	Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
2162	return VERR_CPUM_RAISE_GP_0;
2163	}
2164	return VINF_SUCCESS;
2165	}
2166
2167
2168	/** @callback_method_impl{FNCPUMRDMSR} */
2169	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchTos(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2170	{
2171	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2172	/** @todo implement last branch records. */
2173	*puValue = 0;
2174	return VINF_SUCCESS;
2175	}
2176
2177
2178	/** @callback_method_impl{FNCPUMWRMSR} */
2179	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchTos(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2180	{
2181	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2182	/** @todo implement last branch records. */
2183	return VINF_SUCCESS;
2184	}
2185
2186
2187	/** @callback_method_impl{FNCPUMRDMSR} */
2188	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelBblCrCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2189	{
2190	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2191	*puValue = pRange->uValue;
2192	return VINF_SUCCESS;
2193	}
2194
2195
2196	/** @callback_method_impl{FNCPUMWRMSR} */
2197	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelBblCrCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2198	{
2199	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2200	return VINF_SUCCESS;
2201	}
2202
2203
2204	/** @callback_method_impl{FNCPUMRDMSR} */
2205	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelBblCrCtl3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2206	{
2207	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2208	*puValue = pRange->uValue;
2209	return VINF_SUCCESS;
2210	}
2211
2212
2213	/** @callback_method_impl{FNCPUMWRMSR} */
2214	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelBblCrCtl3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2215	{
2216	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2217	return VINF_SUCCESS;
2218	}
2219
2220
2221	/** @callback_method_impl{FNCPUMRDMSR} */
2222	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7TemperatureTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2223	{
2224	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2225	*puValue = pRange->uValue;
2226	return VINF_SUCCESS;
2227	}
2228
2229
2230	/** @callback_method_impl{FNCPUMWRMSR} */
2231	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7TemperatureTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2232	{
2233	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2234	return VINF_SUCCESS;
2235	}
2236
2237
2238	/** @callback_method_impl{FNCPUMRDMSR} */
2239	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7MsrOffCoreResponseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2240	{
2241	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2242	/** @todo machine check. */
2243	*puValue = pRange->uValue;
2244	return VINF_SUCCESS;
2245	}
2246
2247
2248	/** @callback_method_impl{FNCPUMWRMSR} */
2249	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7MsrOffCoreResponseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2250	{
2251	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2252	/** @todo machine check. */
2253	return VINF_SUCCESS;
2254	}
2255
2256
2257	/** @callback_method_impl{FNCPUMRDMSR} */
2258	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7MiscPwrMgmt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2259	{
2260	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2261	*puValue = 0;
2262	return VINF_SUCCESS;
2263	}
2264
2265
2266	/** @callback_method_impl{FNCPUMWRMSR} */
2267	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7MiscPwrMgmt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2268	{
2269	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2270	return VINF_SUCCESS;
2271	}
2272
2273
2274	/** @callback_method_impl{FNCPUMRDMSR} */
2275	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP6CrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2276	{
2277	RT_NOREF_PV(idMsr);
2278	int rc = CPUMGetGuestCRx(pVCpu, pRange->uValue, puValue);
2279	AssertRC(rc);
2280	return VINF_SUCCESS;
2281	}
2282
2283
2284	/** @callback_method_impl{FNCPUMWRMSR} */
2285	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP6CrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2286	{
2287	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2288	/* This CRx interface differs from the MOV CRx, GReg interface in that
2289	#GP(0) isn't raised if unsupported bits are written to. Instead they
2290	are simply ignored and masked off. (Pentium M Dothan) */
2291	/** @todo Implement MSR_P6_CRx writing. Too much effort for very little, if
2292	* any, gain. */
2293	return VINF_SUCCESS;
2294	}
2295
2296
2297	/** @callback_method_impl{FNCPUMRDMSR} */
2298	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCpuId1FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2299	{
2300	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2301	/** @todo implement CPUID masking. */
2302	*puValue = UINT64_MAX;
2303	return VINF_SUCCESS;
2304	}
2305
2306
2307	/** @callback_method_impl{FNCPUMWRMSR} */
2308	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCpuId1FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2309	{
2310	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2311	/** @todo implement CPUID masking. */
2312	return VINF_SUCCESS;
2313	}
2314
2315
2316	/** @callback_method_impl{FNCPUMRDMSR} */
2317	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCpuId1FeatureMaskEax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2318	{
2319	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2320	/** @todo implement CPUID masking. */
2321	*puValue = 0;
2322	return VINF_SUCCESS;
2323	}
2324
2325
2326	/** @callback_method_impl{FNCPUMWRMSR} */
2327	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCpuId1FeatureMaskEax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2328	{
2329	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2330	/** @todo implement CPUID masking. */
2331	return VINF_SUCCESS;
2332	}
2333
2334
2335
2336	/** @callback_method_impl{FNCPUMRDMSR} */
2337	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCpuId80000001FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2338	{
2339	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2340	/** @todo implement CPUID masking. */
2341	*puValue = UINT64_MAX;
2342	return VINF_SUCCESS;
2343	}
2344
2345
2346	/** @callback_method_impl{FNCPUMWRMSR} */
2347	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCpuId80000001FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2348	{
2349	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2350	/** @todo implement CPUID masking. */
2351	return VINF_SUCCESS;
2352	}
2353
2354
2355
2356	/** @callback_method_impl{FNCPUMRDMSR} */
2357	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyAesNiCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2358	{
2359	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2360	/** @todo implement AES-NI. */
2361	puValue = 3; / Bit 0 is lock bit, bit 1 disables AES-NI. That's what they say. */
2362	return VINF_SUCCESS;
2363	}
2364
2365
2366	/** @callback_method_impl{FNCPUMWRMSR} */
2367	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyAesNiCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2368	{
2369	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2370	/** @todo implement AES-NI. */
2371	return VERR_CPUM_RAISE_GP_0;
2372	}
2373
2374
2375	/** @callback_method_impl{FNCPUMRDMSR} */
2376	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7TurboRatioLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2377	{
2378	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2379	/** @todo implement intel C states. */
2380	*puValue = pRange->uValue;
2381	return VINF_SUCCESS;
2382	}
2383
2384
2385	/** @callback_method_impl{FNCPUMWRMSR} */
2386	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7TurboRatioLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2387	{
2388	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2389	/** @todo implement intel C states. */
2390	return VINF_SUCCESS;
2391	}
2392
2393
2394	/** @callback_method_impl{FNCPUMRDMSR} */
2395	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7LbrSelect(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2396	{
2397	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2398	/** @todo implement last-branch-records. */
2399	*puValue = 0;
2400	return VINF_SUCCESS;
2401	}
2402
2403
2404	/** @callback_method_impl{FNCPUMWRMSR} */
2405	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7LbrSelect(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2406	{
2407	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2408	/** @todo implement last-branch-records. */
2409	return VINF_SUCCESS;
2410	}
2411
2412
2413	/** @callback_method_impl{FNCPUMRDMSR} */
2414	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyErrorControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2415	{
2416	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2417	/** @todo implement memory error injection (MSR_ERROR_CONTROL). */
2418	*puValue = 0;
2419	return VINF_SUCCESS;
2420	}
2421
2422
2423	/** @callback_method_impl{FNCPUMWRMSR} */
2424	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyErrorControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2425	{
2426	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2427	/** @todo implement memory error injection (MSR_ERROR_CONTROL). */
2428	return VINF_SUCCESS;
2429	}
2430
2431
2432	/** @callback_method_impl{FNCPUMRDMSR} */
2433	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7VirtualLegacyWireCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2434	{
2435	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2436	/** @todo implement memory VLW? */
2437	*puValue = pRange->uValue;
2438	/* Note: A20M is known to be bit 1 as this was disclosed in spec update
2439	AAJ49/AAK51/????, which documents the inversion of this bit. The
2440	Sandy bridge CPU here has value 0x74, so it probably doesn't have a BIOS
2441	that correct things. Some guesses at the other bits:
2442	bit 2 = INTR
2443	bit 4 = SMI
2444	bit 5 = INIT
2445	bit 6 = NMI */
2446	return VINF_SUCCESS;
2447	}
2448
2449
2450	/** @callback_method_impl{FNCPUMRDMSR} */
2451	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7PowerCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2452	{
2453	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2454	/** @todo intel power management */
2455	*puValue = 0;
2456	return VINF_SUCCESS;
2457	}
2458
2459
2460	/** @callback_method_impl{FNCPUMWRMSR} */
2461	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7PowerCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2462	{
2463	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2464	/** @todo intel power management */
2465	return VINF_SUCCESS;
2466	}
2467
2468
2469	/** @callback_method_impl{FNCPUMRDMSR} */
2470	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyPebsNumAlt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2471	{
2472	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2473	/** @todo intel performance counters. */
2474	*puValue = 0;
2475	return VINF_SUCCESS;
2476	}
2477
2478
2479	/** @callback_method_impl{FNCPUMWRMSR} */
2480	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyPebsNumAlt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2481	{
2482	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2483	/** @todo intel performance counters. */
2484	return VINF_SUCCESS;
2485	}
2486
2487
2488	/** @callback_method_impl{FNCPUMRDMSR} */
2489	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7PebsLdLat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2490	{
2491	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2492	/** @todo intel performance counters. */
2493	*puValue = 0;
2494	return VINF_SUCCESS;
2495	}
2496
2497
2498	/** @callback_method_impl{FNCPUMWRMSR} */
2499	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7PebsLdLat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2500	{
2501	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2502	/** @todo intel performance counters. */
2503	return VINF_SUCCESS;
2504	}
2505
2506
2507	/** @callback_method_impl{FNCPUMRDMSR} */
2508	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7PkgCnResidencyN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2509	{
2510	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2511	/** @todo intel power management. */
2512	*puValue = 0;
2513	return VINF_SUCCESS;
2514	}
2515
2516
2517	/** @callback_method_impl{FNCPUMRDMSR} */
2518	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7CoreCnResidencyN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2519	{
2520	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2521	/** @todo intel power management. */
2522	*puValue = 0;
2523	return VINF_SUCCESS;
2524	}
2525
2526
2527	/** @callback_method_impl{FNCPUMRDMSR} */
2528	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyVrCurrentConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2529	{
2530	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2531	/** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2532	*puValue = 0;
2533	return VINF_SUCCESS;
2534	}
2535
2536
2537	/** @callback_method_impl{FNCPUMWRMSR} */
2538	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyVrCurrentConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2539	{
2540	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2541	/** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2542	return VINF_SUCCESS;
2543	}
2544
2545
2546	/** @callback_method_impl{FNCPUMRDMSR} */
2547	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyVrMiscConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2548	{
2549	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2550	/** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2551	*puValue = 0;
2552	return VINF_SUCCESS;
2553	}
2554
2555
2556	/** @callback_method_impl{FNCPUMWRMSR} */
2557	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyVrMiscConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2558	{
2559	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2560	/** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2561	return VINF_SUCCESS;
2562	}
2563
2564
2565	/** @callback_method_impl{FNCPUMRDMSR} */
2566	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyRaplPowerUnit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2567	{
2568	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2569	/** @todo intel RAPL. */
2570	*puValue = pRange->uValue;
2571	return VINF_SUCCESS;
2572	}
2573
2574
2575	/** @callback_method_impl{FNCPUMWRMSR} */
2576	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyRaplPowerUnit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2577	{
2578	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2579	/* Note! This is documented as read only and except for a Silvermont sample has
2580	always been classified as read only. This is just here to make it compile. */
2581	return VINF_SUCCESS;
2582	}
2583
2584
2585	/** @callback_method_impl{FNCPUMRDMSR} */
2586	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyPkgCnIrtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2587	{
2588	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2589	/** @todo intel power management. */
2590	*puValue = 0;
2591	return VINF_SUCCESS;
2592	}
2593
2594
2595	/** @callback_method_impl{FNCPUMWRMSR} */
2596	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyPkgCnIrtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2597	{
2598	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2599	/** @todo intel power management. */
2600	return VINF_SUCCESS;
2601	}
2602
2603
2604	/** @callback_method_impl{FNCPUMRDMSR} */
2605	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyPkgC2Residency(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2606	{
2607	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2608	/** @todo intel power management. */
2609	*puValue = 0;
2610	return VINF_SUCCESS;
2611	}
2612
2613
2614	/** @callback_method_impl{FNCPUMWRMSR} */
2615	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyPkgC2Residency(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2616	{
2617	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2618	/* Note! This is documented as read only and except for a Silvermont sample has
2619	always been classified as read only. This is just here to make it compile. */
2620	return VINF_SUCCESS;
2621	}
2622
2623
2624	/** @callback_method_impl{FNCPUMRDMSR} */
2625	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2626	{
2627	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2628	/** @todo intel RAPL. */
2629	*puValue = 0;
2630	return VINF_SUCCESS;
2631	}
2632
2633
2634	/** @callback_method_impl{FNCPUMWRMSR} */
2635	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPkgPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2636	{
2637	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2638	/** @todo intel RAPL. */
2639	return VINF_SUCCESS;
2640	}
2641
2642
2643	/** @callback_method_impl{FNCPUMRDMSR} */
2644	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgEnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2645	{
2646	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2647	/** @todo intel power management. */
2648	*puValue = 0;
2649	return VINF_SUCCESS;
2650	}
2651
2652
2653	/** @callback_method_impl{FNCPUMRDMSR} */
2654	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgPerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2655	{
2656	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2657	/** @todo intel power management. */
2658	*puValue = 0;
2659	return VINF_SUCCESS;
2660	}
2661
2662
2663	/** @callback_method_impl{FNCPUMRDMSR} */
2664	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgPowerInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2665	{
2666	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2667	/** @todo intel power management. */
2668	*puValue = 0;
2669	return VINF_SUCCESS;
2670	}
2671
2672
2673	/** @callback_method_impl{FNCPUMRDMSR} */
2674	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2675	{
2676	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2677	/** @todo intel RAPL. */
2678	*puValue = 0;
2679	return VINF_SUCCESS;
2680	}
2681
2682
2683	/** @callback_method_impl{FNCPUMWRMSR} */
2684	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplDramPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2685	{
2686	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2687	/** @todo intel RAPL. */
2688	return VINF_SUCCESS;
2689	}
2690
2691
2692	/** @callback_method_impl{FNCPUMRDMSR} */
2693	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramEnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2694	{
2695	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2696	/** @todo intel power management. */
2697	*puValue = 0;
2698	return VINF_SUCCESS;
2699	}
2700
2701
2702	/** @callback_method_impl{FNCPUMRDMSR} */
2703	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramPerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2704	{
2705	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2706	/** @todo intel power management. */
2707	*puValue = 0;
2708	return VINF_SUCCESS;
2709	}
2710
2711
2712	/** @callback_method_impl{FNCPUMRDMSR} */
2713	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramPowerInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2714	{
2715	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2716	/** @todo intel power management. */
2717	*puValue = 0;
2718	return VINF_SUCCESS;
2719	}
2720
2721
2722	/** @callback_method_impl{FNCPUMRDMSR} */
2723	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2724	{
2725	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2726	/** @todo intel RAPL. */
2727	*puValue = 0;
2728	return VINF_SUCCESS;
2729	}
2730
2731
2732	/** @callback_method_impl{FNCPUMWRMSR} */
2733	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp0PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2734	{
2735	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2736	/** @todo intel RAPL. */
2737	return VINF_SUCCESS;
2738	}
2739
2740
2741	/** @callback_method_impl{FNCPUMRDMSR} */
2742	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0EnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2743	{
2744	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2745	/** @todo intel power management. */
2746	*puValue = 0;
2747	return VINF_SUCCESS;
2748	}
2749
2750
2751	/** @callback_method_impl{FNCPUMRDMSR} */
2752	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2753	{
2754	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2755	/** @todo intel RAPL. */
2756	*puValue = 0;
2757	return VINF_SUCCESS;
2758	}
2759
2760
2761	/** @callback_method_impl{FNCPUMWRMSR} */
2762	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp0Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2763	{
2764	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2765	/** @todo intel RAPL. */
2766	return VINF_SUCCESS;
2767	}
2768
2769
2770	/** @callback_method_impl{FNCPUMRDMSR} */
2771	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2772	{
2773	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2774	/** @todo intel power management. */
2775	*puValue = 0;
2776	return VINF_SUCCESS;
2777	}
2778
2779
2780	/** @callback_method_impl{FNCPUMRDMSR} */
2781	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp1PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2782	{
2783	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2784	/** @todo intel RAPL. */
2785	*puValue = 0;
2786	return VINF_SUCCESS;
2787	}
2788
2789
2790	/** @callback_method_impl{FNCPUMWRMSR} */
2791	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp1PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2792	{
2793	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2794	/** @todo intel RAPL. */
2795	return VINF_SUCCESS;
2796	}
2797
2798
2799	/** @callback_method_impl{FNCPUMRDMSR} */
2800	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp1EnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2801	{
2802	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2803	/** @todo intel power management. */
2804	*puValue = 0;
2805	return VINF_SUCCESS;
2806	}
2807
2808
2809	/** @callback_method_impl{FNCPUMRDMSR} */
2810	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp1Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2811	{
2812	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2813	/** @todo intel RAPL. */
2814	*puValue = 0;
2815	return VINF_SUCCESS;
2816	}
2817
2818
2819	/** @callback_method_impl{FNCPUMWRMSR} */
2820	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp1Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2821	{
2822	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2823	/** @todo intel RAPL. */
2824	return VINF_SUCCESS;
2825	}
2826
2827
2828	/** @callback_method_impl{FNCPUMRDMSR} */
2829	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpNominal(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2830	{
2831	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2832	/** @todo intel power management. */
2833	*puValue = pRange->uValue;
2834	return VINF_SUCCESS;
2835	}
2836
2837
2838	/** @callback_method_impl{FNCPUMRDMSR} */
2839	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpLevel1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2840	{
2841	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2842	/** @todo intel power management. */
2843	*puValue = pRange->uValue;
2844	return VINF_SUCCESS;
2845	}
2846
2847
2848	/** @callback_method_impl{FNCPUMRDMSR} */
2849	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpLevel2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2850	{
2851	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2852	/** @todo intel power management. */
2853	*puValue = pRange->uValue;
2854	return VINF_SUCCESS;
2855	}
2856
2857
2858	/** @callback_method_impl{FNCPUMRDMSR} */
2859	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2860	{
2861	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2862	/** @todo intel power management. */
2863	*puValue = 0;
2864	return VINF_SUCCESS;
2865	}
2866
2867
2868	/** @callback_method_impl{FNCPUMWRMSR} */
2869	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7IvyConfigTdpControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2870	{
2871	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2872	/** @todo intel power management. */
2873	return VINF_SUCCESS;
2874	}
2875
2876
2877	/** @callback_method_impl{FNCPUMRDMSR} */
2878	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyTurboActivationRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2879	{
2880	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2881	/** @todo intel power management. */
2882	*puValue = 0;
2883	return VINF_SUCCESS;
2884	}
2885
2886
2887	/** @callback_method_impl{FNCPUMWRMSR} */
2888	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7IvyTurboActivationRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2889	{
2890	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2891	/** @todo intel power management. */
2892	return VINF_SUCCESS;
2893	}
2894
2895
2896	/** @callback_method_impl{FNCPUMRDMSR} */
2897	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2898	{
2899	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2900	/** @todo uncore msrs. */
2901	*puValue = 0;
2902	return VINF_SUCCESS;
2903	}
2904
2905
2906	/** @callback_method_impl{FNCPUMWRMSR} */
2907	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2908	{
2909	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2910	/** @todo uncore msrs. */
2911	return VINF_SUCCESS;
2912	}
2913
2914
2915	/** @callback_method_impl{FNCPUMRDMSR} */
2916	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2917	{
2918	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2919	/** @todo uncore msrs. */
2920	*puValue = 0;
2921	return VINF_SUCCESS;
2922	}
2923
2924
2925	/** @callback_method_impl{FNCPUMWRMSR} */
2926	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2927	{
2928	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2929	/** @todo uncore msrs. */
2930	return VINF_SUCCESS;
2931	}
2932
2933
2934	/** @callback_method_impl{FNCPUMRDMSR} */
2935	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2936	{
2937	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2938	/** @todo uncore msrs. */
2939	*puValue = 0;
2940	return VINF_SUCCESS;
2941	}
2942
2943
2944	/** @callback_method_impl{FNCPUMWRMSR} */
2945	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2946	{
2947	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2948	/** @todo uncore msrs. */
2949	return VINF_SUCCESS;
2950	}
2951
2952
2953	/** @callback_method_impl{FNCPUMRDMSR} */
2954	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfFixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2955	{
2956	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2957	/** @todo uncore msrs. */
2958	*puValue = 0;
2959	return VINF_SUCCESS;
2960	}
2961
2962
2963	/** @callback_method_impl{FNCPUMWRMSR} */
2964	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfFixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2965	{
2966	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2967	/** @todo uncore msrs. */
2968	return VINF_SUCCESS;
2969	}
2970
2971
2972	/** @callback_method_impl{FNCPUMRDMSR} */
2973	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfFixedCtr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2974	{
2975	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2976	/** @todo uncore msrs. */
2977	*puValue = 0;
2978	return VINF_SUCCESS;
2979	}
2980
2981
2982	/** @callback_method_impl{FNCPUMWRMSR} */
2983	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfFixedCtr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2984	{
2985	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2986	/** @todo uncore msrs. */
2987	return VINF_SUCCESS;
2988	}
2989
2990
2991	/** @callback_method_impl{FNCPUMRDMSR} */
2992	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncCBoxConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2993	{
2994	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2995	/** @todo uncore msrs. */
2996	*puValue = 0;
2997	return VINF_SUCCESS;
2998	}
2999
3000
3001	/** @callback_method_impl{FNCPUMRDMSR} */
3002	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncArbPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3003	{
3004	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3005	/** @todo uncore msrs. */
3006	*puValue = 0;
3007	return VINF_SUCCESS;
3008	}
3009
3010
3011	/** @callback_method_impl{FNCPUMWRMSR} */
3012	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncArbPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3013	{
3014	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3015	/** @todo uncore msrs. */
3016	return VINF_SUCCESS;
3017	}
3018
3019
3020	/** @callback_method_impl{FNCPUMRDMSR} */
3021	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncArbPerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3022	{
3023	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3024	/** @todo uncore msrs. */
3025	*puValue = 0;
3026	return VINF_SUCCESS;
3027	}
3028
3029
3030	/** @callback_method_impl{FNCPUMWRMSR} */
3031	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncArbPerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3032	{
3033	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3034	/** @todo uncore msrs. */
3035	return VINF_SUCCESS;
3036	}
3037
3038
3039	/** @callback_method_impl{FNCPUMRDMSR} */
3040	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SmiCount(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3041	{
3042	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3043
3044	/*
3045	* 31:0 is SMI count (read only), 63:32 reserved.
3046	* Since we don't do SMI, the count is always zero.
3047	*/
3048	*puValue = 0;
3049	return VINF_SUCCESS;
3050	}
3051
3052
3053	/** @callback_method_impl{FNCPUMRDMSR} */
3054	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore2EmttmCrTablesN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3055	{
3056	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3057	/** @todo implement enhanced multi thread termal monitoring? */
3058	*puValue = pRange->uValue;
3059	return VINF_SUCCESS;
3060	}
3061
3062
3063	/** @callback_method_impl{FNCPUMWRMSR} */
3064	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore2EmttmCrTablesN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3065	{
3066	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3067	/** @todo implement enhanced multi thread termal monitoring? */
3068	return VINF_SUCCESS;
3069	}
3070
3071
3072	/** @callback_method_impl{FNCPUMRDMSR} */
3073	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore2SmmCStMiscInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3074	{
3075	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3076	/** @todo SMM & C-states? */
3077	*puValue = 0;
3078	return VINF_SUCCESS;
3079	}
3080
3081
3082	/** @callback_method_impl{FNCPUMWRMSR} */
3083	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore2SmmCStMiscInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3084	{
3085	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3086	/** @todo SMM & C-states? */
3087	return VINF_SUCCESS;
3088	}
3089
3090
3091	/** @callback_method_impl{FNCPUMRDMSR} */
3092	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore1ExtConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3093	{
3094	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3095	/** @todo Core1&2 EXT_CONFIG (whatever that is)? */
3096	*puValue = 0;
3097	return VINF_SUCCESS;
3098	}
3099
3100
3101	/** @callback_method_impl{FNCPUMWRMSR} */
3102	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore1ExtConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3103	{
3104	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3105	/** @todo Core1&2 EXT_CONFIG (whatever that is)? */
3106	return VINF_SUCCESS;
3107	}
3108
3109
3110	/** @callback_method_impl{FNCPUMRDMSR} */
3111	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore1DtsCalControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3112	{
3113	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3114	/** @todo Core1&2(?) DTS_CAL_CTRL (whatever that is)? */
3115	*puValue = 0;
3116	return VINF_SUCCESS;
3117	}
3118
3119
3120	/** @callback_method_impl{FNCPUMWRMSR} */
3121	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore1DtsCalControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3122	{
3123	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3124	/** @todo Core1&2(?) DTS_CAL_CTRL (whatever that is)? */
3125	return VINF_SUCCESS;
3126	}
3127
3128
3129	/** @callback_method_impl{FNCPUMRDMSR} */
3130	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore2PeciControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3131	{
3132	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3133	/** @todo Core2+ platform environment control interface control register? */
3134	*puValue = 0;
3135	return VINF_SUCCESS;
3136	}
3137
3138
3139	/** @callback_method_impl{FNCPUMWRMSR} */
3140	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore2PeciControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3141	{
3142	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3143	/** @todo Core2+ platform environment control interface control register? */
3144	return VINF_SUCCESS;
3145	}
3146
3147
3148	/** @callback_method_impl{FNCPUMRDMSR} */
3149	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelAtSilvCoreC1Recidency(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3150	{
3151	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3152	*puValue = 0;
3153	return VINF_SUCCESS;
3154	}
3155
3156
3157	/*
3158	* Multiple vendor P6 MSRs.
3159	* Multiple vendor P6 MSRs.
3160	* Multiple vendor P6 MSRs.
3161	*
3162	* These MSRs were introduced with the P6 but not elevated to architectural
3163	* MSRs, despite other vendors implementing them.
3164	*/
3165
3166
3167	/** @callback_method_impl{FNCPUMRDMSR} */
3168	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastBranchFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3169	{
3170	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3171	/* AMD seems to just record RIP, while intel claims to record RIP+CS.BASE
3172	if I read the docs correctly, thus the need for separate functions. */
3173	/** @todo implement last branch records. */
3174	*puValue = 0;
3175	return VINF_SUCCESS;
3176	}
3177
3178
3179	/** @callback_method_impl{FNCPUMRDMSR} */
3180	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastBranchToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3181	{
3182	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3183	/** @todo implement last branch records. */
3184	*puValue = 0;
3185	return VINF_SUCCESS;
3186	}
3187
3188
3189	/** @callback_method_impl{FNCPUMRDMSR} */
3190	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastIntFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3191	{
3192	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3193	/** @todo implement last exception records. */
3194	*puValue = 0;
3195	return VINF_SUCCESS;
3196	}
3197
3198
3199	/** @callback_method_impl{FNCPUMWRMSR} */
3200	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_P6LastIntFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3201	{
3202	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3203	/** @todo implement last exception records. */
3204	/* Note! On many CPUs, the high bit of the 0x000001dd register is always writable, even when the result is
3205	a non-cannonical address. */
3206	return VINF_SUCCESS;
3207	}
3208
3209
3210	/** @callback_method_impl{FNCPUMRDMSR} */
3211	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastIntToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3212	{
3213	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3214	/** @todo implement last exception records. */
3215	*puValue = 0;
3216	return VINF_SUCCESS;
3217	}
3218
3219
3220	/** @callback_method_impl{FNCPUMWRMSR} */
3221	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_P6LastIntToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3222	{
3223	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3224	/** @todo implement last exception records. */
3225	return VINF_SUCCESS;
3226	}
3227
3228
3229
3230	/*
3231	* AMD specific
3232	* AMD specific
3233	* AMD specific
3234	*/
3235
3236
3237	/** @callback_method_impl{FNCPUMRDMSR} */
3238	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hTscRate(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3239	{
3240	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3241	/** @todo Implement TscRateMsr */
3242	puValue = RT_MAKE_U64(0, 1); / 1.0 = reset value. */
3243	return VINF_SUCCESS;
3244	}
3245
3246
3247	/** @callback_method_impl{FNCPUMWRMSR} */
3248	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hTscRate(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3249	{
3250	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3251	/** @todo Implement TscRateMsr */
3252	return VINF_SUCCESS;
3253	}
3254
3255
3256	/** @callback_method_impl{FNCPUMRDMSR} */
3257	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hLwpCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3258	{
3259	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3260	/** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
3261	/* Note: Only listes in BKDG for Family 15H. */
3262	*puValue = 0;
3263	return VINF_SUCCESS;
3264	}
3265
3266
3267	/** @callback_method_impl{FNCPUMWRMSR} */
3268	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hLwpCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3269	{
3270	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3271	/** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
3272	return VINF_SUCCESS;
3273	}
3274
3275
3276	/** @callback_method_impl{FNCPUMRDMSR} */
3277	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hLwpCbAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3278	{
3279	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3280	/** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
3281	/* Note: Only listes in BKDG for Family 15H. */
3282	*puValue = 0;
3283	return VINF_SUCCESS;
3284	}
3285
3286
3287	/** @callback_method_impl{FNCPUMWRMSR} */
3288	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hLwpCbAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3289	{
3290	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3291	/** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
3292	return VINF_SUCCESS;
3293	}
3294
3295
3296	/** @callback_method_impl{FNCPUMRDMSR} */
3297	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hMc4MiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3298	{
3299	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3300	/** @todo machine check. */
3301	*puValue = 0;
3302	return VINF_SUCCESS;
3303	}
3304
3305
3306	/** @callback_method_impl{FNCPUMWRMSR} */
3307	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hMc4MiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3308	{
3309	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3310	/** @todo machine check. */
3311	return VINF_SUCCESS;
3312	}
3313
3314
3315	/** @callback_method_impl{FNCPUMRDMSR} */
3316	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8PerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3317	{
3318	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3319	/** @todo AMD performance events. */
3320	*puValue = 0;
3321	return VINF_SUCCESS;
3322	}
3323
3324
3325	/** @callback_method_impl{FNCPUMWRMSR} */
3326	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8PerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3327	{
3328	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3329	/** @todo AMD performance events. */
3330	return VINF_SUCCESS;
3331	}
3332
3333
3334	/** @callback_method_impl{FNCPUMRDMSR} */
3335	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8PerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3336	{
3337	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3338	/** @todo AMD performance events. */
3339	*puValue = 0;
3340	return VINF_SUCCESS;
3341	}
3342
3343
3344	/** @callback_method_impl{FNCPUMWRMSR} */
3345	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8PerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3346	{
3347	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3348	/** @todo AMD performance events. */
3349	return VINF_SUCCESS;
3350	}
3351
3352
3353	/** @callback_method_impl{FNCPUMRDMSR} */
3354	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SysCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3355	{
3356	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3357	/** @todo AMD SYS_CFG */
3358	*puValue = pRange->uValue;
3359	return VINF_SUCCESS;
3360	}
3361
3362
3363	/** @callback_method_impl{FNCPUMWRMSR} */
3364	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SysCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3365	{
3366	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3367	/** @todo AMD SYS_CFG */
3368	return VINF_SUCCESS;
3369	}
3370
3371
3372	/** @callback_method_impl{FNCPUMRDMSR} */
3373	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8HwCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3374	{
3375	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3376	/** @todo AMD HW_CFG */
3377	*puValue = 0;
3378	return VINF_SUCCESS;
3379	}
3380
3381
3382	/** @callback_method_impl{FNCPUMWRMSR} */
3383	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8HwCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3384	{
3385	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3386	/** @todo AMD HW_CFG */
3387	return VINF_SUCCESS;
3388	}
3389
3390
3391	/** @callback_method_impl{FNCPUMRDMSR} */
3392	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IorrBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3393	{
3394	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3395	/** @todo AMD IorrMask/IorrBase */
3396	*puValue = 0;
3397	return VINF_SUCCESS;
3398	}
3399
3400
3401	/** @callback_method_impl{FNCPUMWRMSR} */
3402	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IorrBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3403	{
3404	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3405	/** @todo AMD IorrMask/IorrBase */
3406	return VINF_SUCCESS;
3407	}
3408
3409
3410	/** @callback_method_impl{FNCPUMRDMSR} */
3411	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IorrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3412	{
3413	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3414	/** @todo AMD IorrMask/IorrBase */
3415	*puValue = 0;
3416	return VINF_SUCCESS;
3417	}
3418
3419
3420	/** @callback_method_impl{FNCPUMWRMSR} */
3421	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IorrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3422	{
3423	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3424	/** @todo AMD IorrMask/IorrBase */
3425	return VINF_SUCCESS;
3426	}
3427
3428
3429	/** @callback_method_impl{FNCPUMRDMSR} */
3430	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8TopOfMemN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3431	{
3432	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3433	*puValue = 0;
3434	/** @todo return 4GB - RamHoleSize here for TOPMEM. Figure out what to return
3435	* for TOPMEM2. */
3436	//if (pRange->uValue == 0)
3437	// *puValue = _4G - RamHoleSize;
3438	return VINF_SUCCESS;
3439	}
3440
3441
3442	/** @callback_method_impl{FNCPUMWRMSR} */
3443	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8TopOfMemN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3444	{
3445	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3446	/** @todo AMD TOPMEM and TOPMEM2/TOM2. */
3447	return VINF_SUCCESS;
3448	}
3449
3450
3451	/** @callback_method_impl{FNCPUMRDMSR} */
3452	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8NbCfg1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3453	{
3454	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3455	/** @todo AMD NB_CFG1 */
3456	*puValue = 0;
3457	return VINF_SUCCESS;
3458	}
3459
3460
3461	/** @callback_method_impl{FNCPUMWRMSR} */
3462	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8NbCfg1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3463	{
3464	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3465	/** @todo AMD NB_CFG1 */
3466	return VINF_SUCCESS;
3467	}
3468
3469
3470	/** @callback_method_impl{FNCPUMRDMSR} */
3471	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8McXcptRedir(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3472	{
3473	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3474	/** @todo machine check. */
3475	*puValue = 0;
3476	return VINF_SUCCESS;
3477	}
3478
3479
3480	/** @callback_method_impl{FNCPUMWRMSR} */
3481	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8McXcptRedir(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3482	{
3483	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3484	/** @todo machine check. */
3485	return VINF_SUCCESS;
3486	}
3487
3488
3489	/** @callback_method_impl{FNCPUMRDMSR} */
3490	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuNameN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3491	{
3492	RT_NOREF_PV(idMsr);
3493	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), pRange->uValue / 2 + 0x80000001);
3494	if (pLeaf)
3495	{
3496	if (!(pRange->uValue & 1))
3497	*puValue = RT_MAKE_U64(pLeaf->uEax, pLeaf->uEbx);
3498	else
3499	*puValue = RT_MAKE_U64(pLeaf->uEcx, pLeaf->uEdx);
3500	}
3501	else
3502	*puValue = 0;
3503	return VINF_SUCCESS;
3504	}
3505
3506
3507	/** @callback_method_impl{FNCPUMWRMSR} */
3508	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuNameN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3509	{
3510	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3511	/** @todo Remember guest programmed CPU name. */
3512	return VINF_SUCCESS;
3513	}
3514
3515
3516	/** @callback_method_impl{FNCPUMRDMSR} */
3517	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8HwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3518	{
3519	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3520	/** @todo AMD HTC. */
3521	*puValue = pRange->uValue;
3522	return VINF_SUCCESS;
3523	}
3524
3525
3526	/** @callback_method_impl{FNCPUMWRMSR} */
3527	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8HwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3528	{
3529	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3530	/** @todo AMD HTC. */
3531	return VINF_SUCCESS;
3532	}
3533
3534
3535	/** @callback_method_impl{FNCPUMRDMSR} */
3536	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3537	{
3538	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3539	/** @todo AMD STC. */
3540	*puValue = 0;
3541	return VINF_SUCCESS;
3542	}
3543
3544
3545	/** @callback_method_impl{FNCPUMWRMSR} */
3546	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3547	{
3548	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3549	/** @todo AMD STC. */
3550	return VINF_SUCCESS;
3551	}
3552
3553
3554	/** @callback_method_impl{FNCPUMRDMSR} */
3555	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8FidVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3556	{
3557	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3558	/** @todo AMD FIDVID_CTL. */
3559	*puValue = pRange->uValue;
3560	return VINF_SUCCESS;
3561	}
3562
3563
3564	/** @callback_method_impl{FNCPUMWRMSR} */
3565	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8FidVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3566	{
3567	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3568	/** @todo AMD FIDVID_CTL. */
3569	return VINF_SUCCESS;
3570	}
3571
3572
3573	/** @callback_method_impl{FNCPUMRDMSR} */
3574	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8FidVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3575	{
3576	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3577	/** @todo AMD FIDVID_STATUS. */
3578	*puValue = pRange->uValue;
3579	return VINF_SUCCESS;
3580	}
3581
3582
3583	/** @callback_method_impl{FNCPUMRDMSR} */
3584	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8McCtlMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3585	{
3586	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3587	/** @todo AMD MC. */
3588	*puValue = 0;
3589	return VINF_SUCCESS;
3590	}
3591
3592
3593	/** @callback_method_impl{FNCPUMWRMSR} */
3594	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8McCtlMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3595	{
3596	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3597	/** @todo AMD MC. */
3598	return VINF_SUCCESS;
3599	}
3600
3601
3602	/** @callback_method_impl{FNCPUMRDMSR} */
3603	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmiOnIoTrapN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3604	{
3605	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3606	/** @todo AMD SMM/SMI and I/O trap. */
3607	*puValue = 0;
3608	return VINF_SUCCESS;
3609	}
3610
3611
3612	/** @callback_method_impl{FNCPUMWRMSR} */
3613	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmiOnIoTrapN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3614	{
3615	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3616	/** @todo AMD SMM/SMI and I/O trap. */
3617	return VINF_SUCCESS;
3618	}
3619
3620
3621	/** @callback_method_impl{FNCPUMRDMSR} */
3622	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmiOnIoTrapCtlSts(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3623	{
3624	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3625	/** @todo AMD SMM/SMI and I/O trap. */
3626	*puValue = 0;
3627	return VINF_SUCCESS;
3628	}
3629
3630
3631	/** @callback_method_impl{FNCPUMWRMSR} */
3632	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmiOnIoTrapCtlSts(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3633	{
3634	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3635	/** @todo AMD SMM/SMI and I/O trap. */
3636	return VINF_SUCCESS;
3637	}
3638
3639
3640	/** @callback_method_impl{FNCPUMRDMSR} */
3641	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IntPendingMessage(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3642	{
3643	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3644	/** @todo Interrupt pending message. */
3645	*puValue = 0;
3646	return VINF_SUCCESS;
3647	}
3648
3649
3650	/** @callback_method_impl{FNCPUMWRMSR} */
3651	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IntPendingMessage(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3652	{
3653	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3654	/** @todo Interrupt pending message. */
3655	return VINF_SUCCESS;
3656	}
3657
3658
3659	/** @callback_method_impl{FNCPUMRDMSR} */
3660	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmiTriggerIoCycle(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3661	{
3662	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3663	/** @todo AMD SMM/SMI and trigger I/O cycle. */
3664	*puValue = 0;
3665	return VINF_SUCCESS;
3666	}
3667
3668
3669	/** @callback_method_impl{FNCPUMWRMSR} */
3670	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmiTriggerIoCycle(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3671	{
3672	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3673	/** @todo AMD SMM/SMI and trigger I/O cycle. */
3674	return VINF_SUCCESS;
3675	}
3676
3677
3678	/** @callback_method_impl{FNCPUMRDMSR} */
3679	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hMmioCfgBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3680	{
3681	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3682	/** @todo AMD MMIO Configuration base address. */
3683	*puValue = 0;
3684	return VINF_SUCCESS;
3685	}
3686
3687
3688	/** @callback_method_impl{FNCPUMWRMSR} */
3689	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hMmioCfgBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3690	{
3691	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3692	/** @todo AMD MMIO Configuration base address. */
3693	return VINF_SUCCESS;
3694	}
3695
3696
3697	/** @callback_method_impl{FNCPUMRDMSR} */
3698	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hTrapCtlMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3699	{
3700	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3701	/** @todo AMD 0xc0010059. */
3702	*puValue = 0;
3703	return VINF_SUCCESS;
3704	}
3705
3706
3707	/** @callback_method_impl{FNCPUMWRMSR} */
3708	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hTrapCtlMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3709	{
3710	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3711	/** @todo AMD 0xc0010059. */
3712	return VINF_SUCCESS;
3713	}
3714
3715
3716	/** @callback_method_impl{FNCPUMRDMSR} */
3717	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateCurLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3718	{
3719	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3720	/** @todo AMD P-states. */
3721	*puValue = pRange->uValue;
3722	return VINF_SUCCESS;
3723	}
3724
3725
3726	/** @callback_method_impl{FNCPUMRDMSR} */
3727	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3728	{
3729	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3730	/** @todo AMD P-states. */
3731	*puValue = pRange->uValue;
3732	return VINF_SUCCESS;
3733	}
3734
3735
3736	/** @callback_method_impl{FNCPUMWRMSR} */
3737	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hPStateControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3738	{
3739	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3740	/** @todo AMD P-states. */
3741	return VINF_SUCCESS;
3742	}
3743
3744
3745	/** @callback_method_impl{FNCPUMRDMSR} */
3746	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3747	{
3748	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3749	/** @todo AMD P-states. */
3750	*puValue = pRange->uValue;
3751	return VINF_SUCCESS;
3752	}
3753
3754
3755	/** @callback_method_impl{FNCPUMWRMSR} */
3756	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hPStateStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3757	{
3758	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3759	/** @todo AMD P-states. */
3760	return VINF_SUCCESS;
3761	}
3762
3763
3764	/** @callback_method_impl{FNCPUMRDMSR} */
3765	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3766	{
3767	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3768	/** @todo AMD P-states. */
3769	*puValue = pRange->uValue;
3770	return VINF_SUCCESS;
3771	}
3772
3773
3774	/** @callback_method_impl{FNCPUMWRMSR} */
3775	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hPStateN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3776	{
3777	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3778	/** @todo AMD P-states. */
3779	return VINF_SUCCESS;
3780	}
3781
3782
3783	/** @callback_method_impl{FNCPUMRDMSR} */
3784	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCofVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3785	{
3786	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3787	/** @todo AMD P-states. */
3788	*puValue = pRange->uValue;
3789	return VINF_SUCCESS;
3790	}
3791
3792
3793	/** @callback_method_impl{FNCPUMWRMSR} */
3794	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCofVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3795	{
3796	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3797	/** @todo AMD P-states. */
3798	return VINF_SUCCESS;
3799	}
3800
3801
3802	/** @callback_method_impl{FNCPUMRDMSR} */
3803	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCofVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3804	{
3805	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3806	/** @todo AMD P-states. */
3807	*puValue = pRange->uValue;
3808	return VINF_SUCCESS;
3809	}
3810
3811
3812	/** @callback_method_impl{FNCPUMWRMSR} */
3813	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCofVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3814	{
3815	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3816	/* Note! Writing 0 seems to not GP, not sure if it does anything to the value... */
3817	/** @todo AMD P-states. */
3818	return VINF_SUCCESS;
3819	}
3820
3821
3822	/** @callback_method_impl{FNCPUMRDMSR} */
3823	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCStateIoBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3824	{
3825	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3826	/** @todo AMD C-states. */
3827	*puValue = 0;
3828	return VINF_SUCCESS;
3829	}
3830
3831
3832	/** @callback_method_impl{FNCPUMWRMSR} */
3833	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCStateIoBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3834	{
3835	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3836	/** @todo AMD C-states. */
3837	return VINF_SUCCESS;
3838	}
3839
3840
3841	/** @callback_method_impl{FNCPUMRDMSR} */
3842	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCpuWatchdogTimer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3843	{
3844	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3845	/** @todo AMD machine checks. */
3846	*puValue = 0;
3847	return VINF_SUCCESS;
3848	}
3849
3850
3851	/** @callback_method_impl{FNCPUMWRMSR} */
3852	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCpuWatchdogTimer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3853	{
3854	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3855	/** @todo AMD machine checks. */
3856	return VINF_SUCCESS;
3857	}
3858
3859
3860	/** @callback_method_impl{FNCPUMRDMSR} */
3861	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3862	{
3863	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3864	/** @todo AMD SMM. */
3865	*puValue = 0;
3866	return VINF_SUCCESS;
3867	}
3868
3869
3870	/** @callback_method_impl{FNCPUMWRMSR} */
3871	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3872	{
3873	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3874	/** @todo AMD SMM. */
3875	return VINF_SUCCESS;
3876	}
3877
3878
3879	/** @callback_method_impl{FNCPUMRDMSR} */
3880	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3881	{
3882	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3883	/** @todo AMD SMM. */
3884	*puValue = 0;
3885	return VINF_SUCCESS;
3886	}
3887
3888
3889	/** @callback_method_impl{FNCPUMWRMSR} */
3890	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3891	{
3892	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3893	/** @todo AMD SMM. */
3894	return VINF_SUCCESS;
3895	}
3896
3897
3898
3899	/** @callback_method_impl{FNCPUMRDMSR} */
3900	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3901	{
3902	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3903	/** @todo AMD SMM. */
3904	*puValue = 0;
3905	return VINF_SUCCESS;
3906	}
3907
3908
3909	/** @callback_method_impl{FNCPUMWRMSR} */
3910	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3911	{
3912	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3913	/** @todo AMD SMM. */
3914	return VINF_SUCCESS;
3915	}
3916
3917
3918	/** @callback_method_impl{FNCPUMRDMSR} */
3919	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8VmCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3920	{
3921	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3922	PVM pVM = pVCpu->CTX_SUFF(pVM);
3923	if (pVM->cpum.s.GuestFeatures.fSvm)
3924	*puValue = MSR_K8_VM_CR_LOCK;
3925	else
3926	*puValue = 0;
3927	return VINF_SUCCESS;
3928	}
3929
3930
3931	/** @callback_method_impl{FNCPUMWRMSR} */
3932	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8VmCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3933	{
3934	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
3935	PVM pVM = pVCpu->CTX_SUFF(pVM);
3936	if (pVM->cpum.s.GuestFeatures.fSvm)
3937	{
3938	/* Silently ignore writes to LOCK and SVM_DISABLE bit when the LOCK bit is set (see cpumMsrRd_AmdK8VmCr). */
3939	if (uValue & (MSR_K8_VM_CR_DPD \| MSR_K8_VM_CR_R_INIT \| MSR_K8_VM_CR_DIS_A20M))
3940	return VERR_CPUM_RAISE_GP_0;
3941	return VINF_SUCCESS;
3942	}
3943	return VERR_CPUM_RAISE_GP_0;
3944	}
3945
3946
3947	/** @callback_method_impl{FNCPUMRDMSR} */
3948	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IgnNe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3949	{
3950	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3951	/** @todo AMD IGNNE\# control. */
3952	*puValue = 0;
3953	return VINF_SUCCESS;
3954	}
3955
3956
3957	/** @callback_method_impl{FNCPUMWRMSR} */
3958	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IgnNe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3959	{
3960	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3961	/** @todo AMD IGNNE\# control. */
3962	return VINF_SUCCESS;
3963	}
3964
3965
3966	/** @callback_method_impl{FNCPUMRDMSR} */
3967	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3968	{
3969	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3970	/** @todo AMD SMM. */
3971	*puValue = 0;
3972	return VINF_SUCCESS;
3973	}
3974
3975
3976	/** @callback_method_impl{FNCPUMWRMSR} */
3977	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3978	{
3979	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3980	/** @todo AMD SMM. */
3981	return VINF_SUCCESS;
3982	}
3983
3984
3985	/** @callback_method_impl{FNCPUMRDMSR} */
3986	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8VmHSavePa(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3987	{
3988	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3989	*puValue = pVCpu->cpum.s.Guest.hwvirt.svm.uMsrHSavePa;
3990	return VINF_SUCCESS;
3991	}
3992
3993
3994	/** @callback_method_impl{FNCPUMWRMSR} */
3995	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8VmHSavePa(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3996	{
3997	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
3998	if (uValue & UINT64_C(0xfff))
3999	{
4000	Log(("CPUM: Invalid setting of low 12 bits set writing host-state save area MSR %#x: %#llx\n", idMsr, uValue));
4001	return VERR_CPUM_RAISE_GP_0;
4002	}
4003
4004	uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
4005	if (fInvPhysMask & uValue)
4006	{
4007	Log(("CPUM: Invalid physical address bits set writing host-state save area MSR %#x: %#llx (%#llx)\n",
4008	idMsr, uValue, uValue & fInvPhysMask));
4009	return VERR_CPUM_RAISE_GP_0;
4010	}
4011
4012	pVCpu->cpum.s.Guest.hwvirt.svm.uMsrHSavePa = uValue;
4013	return VINF_SUCCESS;
4014	}
4015
4016
4017	/** @callback_method_impl{FNCPUMRDMSR} */
4018	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hVmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4019	{
4020	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4021	/** @todo AMD SVM. */
4022	puValue = 0; / RAZ */
4023	return VINF_SUCCESS;
4024	}
4025
4026
4027	/** @callback_method_impl{FNCPUMWRMSR} */
4028	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hVmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4029	{
4030	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4031	/** @todo AMD SVM. */
4032	return VINF_SUCCESS;
4033	}
4034
4035
4036	/** @callback_method_impl{FNCPUMRDMSR} */
4037	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hSmmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4038	{
4039	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4040	/** @todo AMD SMM. */
4041	puValue = 0; / RAZ */
4042	return VINF_SUCCESS;
4043	}
4044
4045
4046	/** @callback_method_impl{FNCPUMWRMSR} */
4047	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hSmmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4048	{
4049	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4050	/** @todo AMD SMM. */
4051	return VINF_SUCCESS;
4052	}
4053
4054
4055	/** @callback_method_impl{FNCPUMRDMSR} */
4056	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hLocalSmiStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4057	{
4058	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4059	/** @todo AMD SMM/SMI. */
4060	*puValue = 0;
4061	return VINF_SUCCESS;
4062	}
4063
4064
4065	/** @callback_method_impl{FNCPUMWRMSR} */
4066	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hLocalSmiStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4067	{
4068	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4069	/** @todo AMD SMM/SMI. */
4070	return VINF_SUCCESS;
4071	}
4072
4073
4074	/** @callback_method_impl{FNCPUMRDMSR} */
4075	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hOsVisWrkIdLength(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4076	{
4077	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
4078	/** @todo AMD OS visible workaround. */
4079	*puValue = pRange->uValue;
4080	return VINF_SUCCESS;
4081	}
4082
4083
4084	/** @callback_method_impl{FNCPUMWRMSR} */
4085	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hOsVisWrkIdLength(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4086	{
4087	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4088	/** @todo AMD OS visible workaround. */
4089	return VINF_SUCCESS;
4090	}
4091
4092
4093	/** @callback_method_impl{FNCPUMRDMSR} */
4094	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hOsVisWrkStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4095	{
4096	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4097	/** @todo AMD OS visible workaround. */
4098	*puValue = 0;
4099	return VINF_SUCCESS;
4100	}
4101
4102
4103	/** @callback_method_impl{FNCPUMWRMSR} */
4104	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hOsVisWrkStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4105	{
4106	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4107	/** @todo AMD OS visible workaround. */
4108	return VINF_SUCCESS;
4109	}
4110
4111
4112	/** @callback_method_impl{FNCPUMRDMSR} */
4113	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam16hL2IPerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4114	{
4115	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4116	/** @todo AMD L2I performance counters. */
4117	*puValue = 0;
4118	return VINF_SUCCESS;
4119	}
4120
4121
4122	/** @callback_method_impl{FNCPUMWRMSR} */
4123	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam16hL2IPerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4124	{
4125	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4126	/** @todo AMD L2I performance counters. */
4127	return VINF_SUCCESS;
4128	}
4129
4130
4131	/** @callback_method_impl{FNCPUMRDMSR} */
4132	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam16hL2IPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4133	{
4134	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4135	/** @todo AMD L2I performance counters. */
4136	*puValue = 0;
4137	return VINF_SUCCESS;
4138	}
4139
4140
4141	/** @callback_method_impl{FNCPUMWRMSR} */
4142	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam16hL2IPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4143	{
4144	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4145	/** @todo AMD L2I performance counters. */
4146	return VINF_SUCCESS;
4147	}
4148
4149
4150	/** @callback_method_impl{FNCPUMRDMSR} */
4151	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hNorthbridgePerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4152	{
4153	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4154	/** @todo AMD Northbridge performance counters. */
4155	*puValue = 0;
4156	return VINF_SUCCESS;
4157	}
4158
4159
4160	/** @callback_method_impl{FNCPUMWRMSR} */
4161	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hNorthbridgePerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4162	{
4163	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4164	/** @todo AMD Northbridge performance counters. */
4165	return VINF_SUCCESS;
4166	}
4167
4168
4169	/** @callback_method_impl{FNCPUMRDMSR} */
4170	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hNorthbridgePerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4171	{
4172	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4173	/** @todo AMD Northbridge performance counters. */
4174	*puValue = 0;
4175	return VINF_SUCCESS;
4176	}
4177
4178
4179	/** @callback_method_impl{FNCPUMWRMSR} */
4180	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hNorthbridgePerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4181	{
4182	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4183	/** @todo AMD Northbridge performance counters. */
4184	return VINF_SUCCESS;
4185	}
4186
4187
4188	/** @callback_method_impl{FNCPUMRDMSR} */
4189	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7MicrocodeCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4190	{
4191	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4192	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4193	* cpus. Need to be explored and verify K7 presence. */
4194	/** @todo Undocumented register only seen mentioned in fam15h erratum \#608. */
4195	*puValue = pRange->uValue;
4196	return VINF_SUCCESS;
4197	}
4198
4199
4200	/** @callback_method_impl{FNCPUMWRMSR} */
4201	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7MicrocodeCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4202	{
4203	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4204	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4205	* cpus. Need to be explored and verify K7 presence. */
4206	/** @todo Undocumented register only seen mentioned in fam15h erratum \#608. */
4207	return VINF_SUCCESS;
4208	}
4209
4210
4211	/** @callback_method_impl{FNCPUMRDMSR} */
4212	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7ClusterIdMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4213	{
4214	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4215	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4216	* cpus. Need to be explored and verify K7 presence. */
4217	/** @todo Undocumented register only seen mentioned in fam16h BKDG r3.00 when
4218	* describing EBL_CR_POWERON. */
4219	*puValue = pRange->uValue;
4220	return VINF_SUCCESS;
4221	}
4222
4223
4224	/** @callback_method_impl{FNCPUMWRMSR} */
4225	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7ClusterIdMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4226	{
4227	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4228	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4229	* cpus. Need to be explored and verify K7 presence. */
4230	/** @todo Undocumented register only seen mentioned in fam16h BKDG r3.00 when
4231	* describing EBL_CR_POWERON. */
4232	return VINF_SUCCESS;
4233	}
4234
4235
4236	/** @callback_method_impl{FNCPUMRDMSR} */
4237	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlStd07hEbax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4238	{
4239	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4240	bool fIgnored;
4241	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafEx(pVCpu->CTX_SUFF(pVM), 0x00000007, 0, &fIgnored);
4242	if (pLeaf)
4243	*puValue = RT_MAKE_U64(pLeaf->uEbx, pLeaf->uEax);
4244	else
4245	*puValue = 0;
4246	return VINF_SUCCESS;
4247	}
4248
4249
4250	/** @callback_method_impl{FNCPUMWRMSR} */
4251	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlStd07hEbax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4252	{
4253	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4254	/** @todo Changing CPUID leaf 7/0. */
4255	return VINF_SUCCESS;
4256	}
4257
4258
4259	/** @callback_method_impl{FNCPUMRDMSR} */
4260	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlStd06hEcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4261	{
4262	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4263	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000006);
4264	if (pLeaf)
4265	*puValue = pLeaf->uEcx;
4266	else
4267	*puValue = 0;
4268	return VINF_SUCCESS;
4269	}
4270
4271
4272	/** @callback_method_impl{FNCPUMWRMSR} */
4273	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlStd06hEcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4274	{
4275	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4276	/** @todo Changing CPUID leaf 6. */
4277	return VINF_SUCCESS;
4278	}
4279
4280
4281	/** @callback_method_impl{FNCPUMRDMSR} */
4282	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlStd01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4283	{
4284	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4285	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000001);
4286	if (pLeaf)
4287	*puValue = RT_MAKE_U64(pLeaf->uEdx, pLeaf->uEcx);
4288	else
4289	*puValue = 0;
4290	return VINF_SUCCESS;
4291	}
4292
4293
4294	/** @callback_method_impl{FNCPUMWRMSR} */
4295	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlStd01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4296	{
4297	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4298	/** @todo Changing CPUID leaf 0x80000001. */
4299	return VINF_SUCCESS;
4300	}
4301
4302
4303	/** @callback_method_impl{FNCPUMRDMSR} */
4304	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlExt01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4305	{
4306	RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4307	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x80000001);
4308	if (pLeaf)
4309	*puValue = RT_MAKE_U64(pLeaf->uEdx, pLeaf->uEcx);
4310	else
4311	*puValue = 0;
4312	return VINF_SUCCESS;
4313	}
4314
4315
4316	/** @callback_method_impl{FNCPUMWRMSR} */
4317	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlExt01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4318	{
4319	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4320	/** @todo Changing CPUID leaf 0x80000001. */
4321	return VINF_SUCCESS;
4322	}
4323
4324
4325	/** @callback_method_impl{FNCPUMRDMSR} */
4326	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8PatchLevel(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4327	{
4328	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4329	/** @todo Fake AMD microcode patching. */
4330	*puValue = pRange->uValue;
4331	return VINF_SUCCESS;
4332	}
4333
4334
4335	/** @callback_method_impl{FNCPUMWRMSR} */
4336	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8PatchLoader(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4337	{
4338	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4339	/** @todo Fake AMD microcode patching. */
4340	return VINF_SUCCESS;
4341	}
4342
4343
4344	/** @callback_method_impl{FNCPUMRDMSR} */
4345	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DebugStatusMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4346	{
4347	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4348	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4349	* cpus. Need to be explored and verify K7 presence. */
4350	/** @todo undocumented */
4351	*puValue = 0;
4352	return VINF_SUCCESS;
4353	}
4354
4355
4356	/** @callback_method_impl{FNCPUMWRMSR} */
4357	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DebugStatusMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4358	{
4359	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4360	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4361	* cpus. Need to be explored and verify K7 presence. */
4362	/** @todo undocumented */
4363	return VINF_SUCCESS;
4364	}
4365
4366
4367	/** @callback_method_impl{FNCPUMRDMSR} */
4368	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BHTraceBaseMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4369	{
4370	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4371	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4372	* cpus. Need to be explored and verify K7 presence. */
4373	/** @todo undocumented */
4374	*puValue = 0;
4375	return VINF_SUCCESS;
4376	}
4377
4378
4379	/** @callback_method_impl{FNCPUMWRMSR} */
4380	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BHTraceBaseMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4381	{
4382	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4383	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4384	* cpus. Need to be explored and verify K7 presence. */
4385	/** @todo undocumented */
4386	return VINF_SUCCESS;
4387	}
4388
4389
4390	/** @callback_method_impl{FNCPUMRDMSR} */
4391	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BHTracePtrMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4392	{
4393	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4394	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4395	* cpus. Need to be explored and verify K7 presence. */
4396	/** @todo undocumented */
4397	*puValue = 0;
4398	return VINF_SUCCESS;
4399	}
4400
4401
4402	/** @callback_method_impl{FNCPUMWRMSR} */
4403	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BHTracePtrMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4404	{
4405	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4406	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4407	* cpus. Need to be explored and verify K7 presence. */
4408	/** @todo undocumented */
4409	return VINF_SUCCESS;
4410	}
4411
4412
4413	/** @callback_method_impl{FNCPUMRDMSR} */
4414	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BHTraceLimitMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4415	{
4416	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4417	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4418	* cpus. Need to be explored and verify K7 presence. */
4419	/** @todo undocumented */
4420	*puValue = 0;
4421	return VINF_SUCCESS;
4422	}
4423
4424
4425	/** @callback_method_impl{FNCPUMWRMSR} */
4426	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BHTraceLimitMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4427	{
4428	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4429	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4430	* cpus. Need to be explored and verify K7 presence. */
4431	/** @todo undocumented */
4432	return VINF_SUCCESS;
4433	}
4434
4435
4436	/** @callback_method_impl{FNCPUMRDMSR} */
4437	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7HardwareDebugToolCfgMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4438	{
4439	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4440	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4441	* cpus. Need to be explored and verify K7 presence. */
4442	/** @todo undocumented */
4443	*puValue = 0;
4444	return VINF_SUCCESS;
4445	}
4446
4447
4448	/** @callback_method_impl{FNCPUMWRMSR} */
4449	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7HardwareDebugToolCfgMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4450	{
4451	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4452	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4453	* cpus. Need to be explored and verify K7 presence. */
4454	/** @todo undocumented */
4455	return VINF_SUCCESS;
4456	}
4457
4458
4459	/** @callback_method_impl{FNCPUMRDMSR} */
4460	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7FastFlushCountMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4461	{
4462	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4463	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4464	* cpus. Need to be explored and verify K7 presence. */
4465	/** @todo undocumented */
4466	*puValue = 0;
4467	return VINF_SUCCESS;
4468	}
4469
4470
4471	/** @callback_method_impl{FNCPUMWRMSR} */
4472	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7FastFlushCountMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4473	{
4474	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4475	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4476	* cpus. Need to be explored and verify K7 presence. */
4477	/** @todo undocumented */
4478	return VINF_SUCCESS;
4479	}
4480
4481
4482	/** @callback_method_impl{FNCPUMRDMSR} */
4483	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7NodeId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4484	{
4485	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4486	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4487	* cpus. Need to be explored and verify K7 presence. */
4488	/** @todo AMD node ID and bios scratch. */
4489	puValue = 0; / nodeid = 0; nodes-per-cpu = 1 */
4490	return VINF_SUCCESS;
4491	}
4492
4493
4494	/** @callback_method_impl{FNCPUMWRMSR} */
4495	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7NodeId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4496	{
4497	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4498	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4499	* cpus. Need to be explored and verify K7 presence. */
4500	/** @todo AMD node ID and bios scratch. */
4501	return VINF_SUCCESS;
4502	}
4503
4504
4505	/** @callback_method_impl{FNCPUMRDMSR} */
4506	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DrXAddrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4507	{
4508	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4509	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4510	* cpus. Need to be explored and verify K7 presence. */
4511	/** @todo AMD DRx address masking (range breakpoints). */
4512	*puValue = 0;
4513	return VINF_SUCCESS;
4514	}
4515
4516
4517	/** @callback_method_impl{FNCPUMWRMSR} */
4518	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DrXAddrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4519	{
4520	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4521	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4522	* cpus. Need to be explored and verify K7 presence. */
4523	/** @todo AMD DRx address masking (range breakpoints). */
4524	return VINF_SUCCESS;
4525	}
4526
4527
4528	/** @callback_method_impl{FNCPUMRDMSR} */
4529	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7Dr0DataMatchMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4530	{
4531	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4532	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4533	* cpus. Need to be explored and verify K7 presence. */
4534	/** @todo AMD undocument debugging features. */
4535	*puValue = 0;
4536	return VINF_SUCCESS;
4537	}
4538
4539
4540	/** @callback_method_impl{FNCPUMWRMSR} */
4541	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7Dr0DataMatchMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4542	{
4543	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4544	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4545	* cpus. Need to be explored and verify K7 presence. */
4546	/** @todo AMD undocument debugging features. */
4547	return VINF_SUCCESS;
4548	}
4549
4550
4551	/** @callback_method_impl{FNCPUMRDMSR} */
4552	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7Dr0DataMaskMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4553	{
4554	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4555	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4556	* cpus. Need to be explored and verify K7 presence. */
4557	/** @todo AMD undocument debugging features. */
4558	*puValue = 0;
4559	return VINF_SUCCESS;
4560	}
4561
4562
4563	/** @callback_method_impl{FNCPUMWRMSR} */
4564	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7Dr0DataMaskMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4565	{
4566	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4567	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4568	* cpus. Need to be explored and verify K7 presence. */
4569	/** @todo AMD undocument debugging features. */
4570	return VINF_SUCCESS;
4571	}
4572
4573
4574	/** @callback_method_impl{FNCPUMRDMSR} */
4575	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7LoadStoreCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4576	{
4577	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4578	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4579	* cpus. Need to be explored and verify K7 presence. */
4580	/** @todo AMD load-store config. */
4581	*puValue = 0;
4582	return VINF_SUCCESS;
4583	}
4584
4585
4586	/** @callback_method_impl{FNCPUMWRMSR} */
4587	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7LoadStoreCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4588	{
4589	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4590	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4591	* cpus. Need to be explored and verify K7 presence. */
4592	/** @todo AMD load-store config. */
4593	return VINF_SUCCESS;
4594	}
4595
4596
4597	/** @callback_method_impl{FNCPUMRDMSR} */
4598	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7InstrCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4599	{
4600	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4601	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4602	* cpus. Need to be explored and verify K7 presence. */
4603	/** @todo AMD instruction cache config. */
4604	*puValue = 0;
4605	return VINF_SUCCESS;
4606	}
4607
4608
4609	/** @callback_method_impl{FNCPUMWRMSR} */
4610	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7InstrCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4611	{
4612	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4613	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4614	* cpus. Need to be explored and verify K7 presence. */
4615	/** @todo AMD instruction cache config. */
4616	return VINF_SUCCESS;
4617	}
4618
4619
4620	/** @callback_method_impl{FNCPUMRDMSR} */
4621	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DataCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4622	{
4623	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4624	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4625	* cpus. Need to be explored and verify K7 presence. */
4626	/** @todo AMD data cache config. */
4627	*puValue = 0;
4628	return VINF_SUCCESS;
4629	}
4630
4631
4632	/** @callback_method_impl{FNCPUMWRMSR} */
4633	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DataCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4634	{
4635	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4636	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4637	* cpus. Need to be explored and verify K7 presence. */
4638	/** @todo AMD data cache config. */
4639	return VINF_SUCCESS;
4640	}
4641
4642
4643	/** @callback_method_impl{FNCPUMRDMSR} */
4644	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BusUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4645	{
4646	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4647	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4648	* cpus. Need to be explored and verify K7 presence. */
4649	/** @todo AMD bus unit config. */
4650	*puValue = 0;
4651	return VINF_SUCCESS;
4652	}
4653
4654
4655	/** @callback_method_impl{FNCPUMWRMSR} */
4656	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BusUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4657	{
4658	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4659	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4660	* cpus. Need to be explored and verify K7 presence. */
4661	/** @todo AMD bus unit config. */
4662	return VINF_SUCCESS;
4663	}
4664
4665
4666	/** @callback_method_impl{FNCPUMRDMSR} */
4667	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DebugCtl2Maybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4668	{
4669	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4670	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4671	* cpus. Need to be explored and verify K7 presence. */
4672	/** @todo Undocument AMD debug control register \#2. */
4673	*puValue = 0;
4674	return VINF_SUCCESS;
4675	}
4676
4677
4678	/** @callback_method_impl{FNCPUMWRMSR} */
4679	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DebugCtl2Maybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4680	{
4681	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4682	/** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4683	* cpus. Need to be explored and verify K7 presence. */
4684	/** @todo Undocument AMD debug control register \#2. */
4685	return VINF_SUCCESS;
4686	}
4687
4688
4689	/** @callback_method_impl{FNCPUMRDMSR} */
4690	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hFpuCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4691	{
4692	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4693	/** @todo AMD FPU config. */
4694	*puValue = 0;
4695	return VINF_SUCCESS;
4696	}
4697
4698
4699	/** @callback_method_impl{FNCPUMWRMSR} */
4700	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hFpuCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4701	{
4702	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4703	/** @todo AMD FPU config. */
4704	return VINF_SUCCESS;
4705	}
4706
4707
4708	/** @callback_method_impl{FNCPUMRDMSR} */
4709	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hDecoderCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4710	{
4711	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4712	/** @todo AMD decoder config. */
4713	*puValue = 0;
4714	return VINF_SUCCESS;
4715	}
4716
4717
4718	/** @callback_method_impl{FNCPUMWRMSR} */
4719	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hDecoderCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4720	{
4721	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4722	/** @todo AMD decoder config. */
4723	return VINF_SUCCESS;
4724	}
4725
4726
4727	/** @callback_method_impl{FNCPUMRDMSR} */
4728	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hBusUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4729	{
4730	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4731	/* Note! 10h and 16h */
4732	/** @todo AMD bus unit config. */
4733	*puValue = 0;
4734	return VINF_SUCCESS;
4735	}
4736
4737
4738	/** @callback_method_impl{FNCPUMWRMSR} */
4739	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hBusUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4740	{
4741	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4742	/* Note! 10h and 16h */
4743	/** @todo AMD bus unit config. */
4744	return VINF_SUCCESS;
4745	}
4746
4747
4748	/** @callback_method_impl{FNCPUMRDMSR} */
4749	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hCombUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4750	{
4751	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4752	/** @todo AMD unit config. */
4753	*puValue = 0;
4754	return VINF_SUCCESS;
4755	}
4756
4757
4758	/** @callback_method_impl{FNCPUMWRMSR} */
4759	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hCombUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4760	{
4761	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4762	/** @todo AMD unit config. */
4763	return VINF_SUCCESS;
4764	}
4765
4766
4767	/** @callback_method_impl{FNCPUMRDMSR} */
4768	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hCombUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4769	{
4770	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4771	/** @todo AMD unit config 2. */
4772	*puValue = 0;
4773	return VINF_SUCCESS;
4774	}
4775
4776
4777	/** @callback_method_impl{FNCPUMWRMSR} */
4778	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hCombUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4779	{
4780	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4781	/** @todo AMD unit config 2. */
4782	return VINF_SUCCESS;
4783	}
4784
4785
4786	/** @callback_method_impl{FNCPUMRDMSR} */
4787	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hCombUnitCfg3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4788	{
4789	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4790	/** @todo AMD combined unit config 3. */
4791	*puValue = 0;
4792	return VINF_SUCCESS;
4793	}
4794
4795
4796	/** @callback_method_impl{FNCPUMWRMSR} */
4797	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hCombUnitCfg3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4798	{
4799	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4800	/** @todo AMD combined unit config 3. */
4801	return VINF_SUCCESS;
4802	}
4803
4804
4805	/** @callback_method_impl{FNCPUMRDMSR} */
4806	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hExecUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4807	{
4808	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4809	/** @todo AMD execution unit config. */
4810	*puValue = 0;
4811	return VINF_SUCCESS;
4812	}
4813
4814
4815	/** @callback_method_impl{FNCPUMWRMSR} */
4816	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hExecUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4817	{
4818	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4819	/** @todo AMD execution unit config. */
4820	return VINF_SUCCESS;
4821	}
4822
4823
4824	/** @callback_method_impl{FNCPUMRDMSR} */
4825	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hLoadStoreCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4826	{
4827	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4828	/** @todo AMD load-store config 2. */
4829	*puValue = 0;
4830	return VINF_SUCCESS;
4831	}
4832
4833
4834	/** @callback_method_impl{FNCPUMWRMSR} */
4835	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hLoadStoreCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4836	{
4837	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4838	/** @todo AMD load-store config 2. */
4839	return VINF_SUCCESS;
4840	}
4841
4842
4843	/** @callback_method_impl{FNCPUMRDMSR} */
4844	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsFetchCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4845	{
4846	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4847	/** @todo AMD IBS. */
4848	*puValue = 0;
4849	return VINF_SUCCESS;
4850	}
4851
4852
4853	/** @callback_method_impl{FNCPUMWRMSR} */
4854	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsFetchCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4855	{
4856	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4857	/** @todo AMD IBS. */
4858	return VINF_SUCCESS;
4859	}
4860
4861
4862	/** @callback_method_impl{FNCPUMRDMSR} */
4863	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsFetchLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4864	{
4865	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4866	/** @todo AMD IBS. */
4867	*puValue = 0;
4868	return VINF_SUCCESS;
4869	}
4870
4871
4872	/** @callback_method_impl{FNCPUMWRMSR} */
4873	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsFetchLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4874	{
4875	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4876	/** @todo AMD IBS. */
4877	return VINF_SUCCESS;
4878	}
4879
4880
4881	/** @callback_method_impl{FNCPUMRDMSR} */
4882	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsFetchPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4883	{
4884	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4885	/** @todo AMD IBS. */
4886	*puValue = 0;
4887	return VINF_SUCCESS;
4888	}
4889
4890
4891	/** @callback_method_impl{FNCPUMWRMSR} */
4892	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsFetchPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4893	{
4894	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4895	/** @todo AMD IBS. */
4896	return VINF_SUCCESS;
4897	}
4898
4899
4900	/** @callback_method_impl{FNCPUMRDMSR} */
4901	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpExecCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4902	{
4903	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4904	/** @todo AMD IBS. */
4905	*puValue = 0;
4906	return VINF_SUCCESS;
4907	}
4908
4909
4910	/** @callback_method_impl{FNCPUMWRMSR} */
4911	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpExecCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4912	{
4913	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4914	/** @todo AMD IBS. */
4915	return VINF_SUCCESS;
4916	}
4917
4918
4919	/** @callback_method_impl{FNCPUMRDMSR} */
4920	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpRip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4921	{
4922	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4923	/** @todo AMD IBS. */
4924	*puValue = 0;
4925	return VINF_SUCCESS;
4926	}
4927
4928
4929	/** @callback_method_impl{FNCPUMWRMSR} */
4930	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpRip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4931	{
4932	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4933	/** @todo AMD IBS. */
4934	if (!X86_IS_CANONICAL(uValue))
4935	{
4936	Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
4937	return VERR_CPUM_RAISE_GP_0;
4938	}
4939	return VINF_SUCCESS;
4940	}
4941
4942
4943	/** @callback_method_impl{FNCPUMRDMSR} */
4944	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpData(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4945	{
4946	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4947	/** @todo AMD IBS. */
4948	*puValue = 0;
4949	return VINF_SUCCESS;
4950	}
4951
4952
4953	/** @callback_method_impl{FNCPUMWRMSR} */
4954	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpData(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4955	{
4956	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4957	/** @todo AMD IBS. */
4958	return VINF_SUCCESS;
4959	}
4960
4961
4962	/** @callback_method_impl{FNCPUMRDMSR} */
4963	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpData2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4964	{
4965	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4966	/** @todo AMD IBS. */
4967	*puValue = 0;
4968	return VINF_SUCCESS;
4969	}
4970
4971
4972	/** @callback_method_impl{FNCPUMWRMSR} */
4973	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpData2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4974	{
4975	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4976	/** @todo AMD IBS. */
4977	return VINF_SUCCESS;
4978	}
4979
4980
4981	/** @callback_method_impl{FNCPUMRDMSR} */
4982	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpData3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4983	{
4984	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4985	/** @todo AMD IBS. */
4986	*puValue = 0;
4987	return VINF_SUCCESS;
4988	}
4989
4990
4991	/** @callback_method_impl{FNCPUMWRMSR} */
4992	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpData3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4993	{
4994	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4995	/** @todo AMD IBS. */
4996	return VINF_SUCCESS;
4997	}
4998
4999
5000	/** @callback_method_impl{FNCPUMRDMSR} */
5001	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsDcLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
5002	{
5003	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
5004	/** @todo AMD IBS. */
5005	*puValue = 0;
5006	return VINF_SUCCESS;
5007	}
5008
5009
5010	/** @callback_method_impl{FNCPUMWRMSR} */
5011	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsDcLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
5012	{
5013	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
5014	/** @todo AMD IBS. */
5015	if (!X86_IS_CANONICAL(uValue))
5016	{
5017	Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
5018	return VERR_CPUM_RAISE_GP_0;
5019	}
5020	return VINF_SUCCESS;
5021	}
5022
5023
5024	/** @callback_method_impl{FNCPUMRDMSR} */
5025	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsDcPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
5026	{
5027	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
5028	/** @todo AMD IBS. */
5029	*puValue = 0;
5030	return VINF_SUCCESS;
5031	}
5032
5033
5034	/** @callback_method_impl{FNCPUMWRMSR} */
5035	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsDcPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
5036	{
5037	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
5038	/** @todo AMD IBS. */
5039	return VINF_SUCCESS;
5040	}
5041
5042
5043	/** @callback_method_impl{FNCPUMRDMSR} */
5044	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
5045	{
5046	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
5047	/** @todo AMD IBS. */
5048	*puValue = 0;
5049	return VINF_SUCCESS;
5050	}
5051
5052
5053	/** @callback_method_impl{FNCPUMWRMSR} */
5054	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
5055	{
5056	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
5057	/** @todo AMD IBS. */
5058	return VINF_SUCCESS;
5059	}
5060
5061
5062	/** @callback_method_impl{FNCPUMRDMSR} */
5063	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam14hIbsBrTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
5064	{
5065	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
5066	/** @todo AMD IBS. */
5067	*puValue = 0;
5068	return VINF_SUCCESS;
5069	}
5070
5071
5072	/** @callback_method_impl{FNCPUMWRMSR} */
5073	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam14hIbsBrTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
5074	{
5075	RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
5076	/** @todo AMD IBS. */
5077	if (!X86_IS_CANONICAL(uValue))
5078	{
5079	Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
5080	return VERR_CPUM_RAISE_GP_0;
5081	}
5082	return VINF_SUCCESS;
5083	}
5084
5085
5086
5087	/*
5088	* GIM MSRs.
5089	* GIM MSRs.
5090	* GIM MSRs.
5091	*/
5092
5093
5094	/** @callback_method_impl{FNCPUMRDMSR} */
5095	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Gim(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
5096	{
5097	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5098	/* Raise #GP(0) like a physical CPU would since the nested-hypervisor hasn't intercept these MSRs. */
5099	PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
5100	if (CPUMIsGuestInNestedHwVirtMode(pCtx))
5101	return VERR_CPUM_RAISE_GP_0;
5102	#endif
5103	return GIMReadMsr(pVCpu, idMsr, pRange, puValue);
5104	}
5105
5106
5107	/** @callback_method_impl{FNCPUMWRMSR} */
5108	static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Gim(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
5109	{
5110	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5111	/* Raise #GP(0) like a physical CPU would since the nested-hypervisor hasn't intercept these MSRs. */
5112	PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
5113	if (CPUMIsGuestInNestedHwVirtMode(pCtx))
5114	return VERR_CPUM_RAISE_GP_0;
5115	#endif
5116	return GIMWriteMsr(pVCpu, idMsr, pRange, uValue, uRawValue);
5117	}
5118
5119
5120	/**
5121	* MSR read function table.
5122	*/
5123	static const PFNCPUMRDMSR g_aCpumRdMsrFns[kCpumMsrRdFn_End] =
5124	{
5125	NULL, /* Invalid */
5126	cpumMsrRd_FixedValue,
5127	NULL, /* Alias */
5128	cpumMsrRd_WriteOnly,
5129	cpumMsrRd_Ia32P5McAddr,
5130	cpumMsrRd_Ia32P5McType,
5131	cpumMsrRd_Ia32TimestampCounter,
5132	cpumMsrRd_Ia32PlatformId,
5133	cpumMsrRd_Ia32ApicBase,
5134	cpumMsrRd_Ia32FeatureControl,
5135	cpumMsrRd_Ia32BiosSignId,
5136	cpumMsrRd_Ia32SmmMonitorCtl,
5137	cpumMsrRd_Ia32PmcN,
5138	cpumMsrRd_Ia32MonitorFilterLineSize,
5139	cpumMsrRd_Ia32MPerf,
5140	cpumMsrRd_Ia32APerf,
5141	cpumMsrRd_Ia32MtrrCap,
5142	cpumMsrRd_Ia32MtrrPhysBaseN,
5143	cpumMsrRd_Ia32MtrrPhysMaskN,
5144	cpumMsrRd_Ia32MtrrFixed,
5145	cpumMsrRd_Ia32MtrrDefType,
5146	cpumMsrRd_Ia32Pat,
5147	cpumMsrRd_Ia32SysEnterCs,
5148	cpumMsrRd_Ia32SysEnterEsp,
5149	cpumMsrRd_Ia32SysEnterEip,
5150	cpumMsrRd_Ia32McgCap,
5151	cpumMsrRd_Ia32McgStatus,
5152	cpumMsrRd_Ia32McgCtl,
5153	cpumMsrRd_Ia32DebugCtl,
5154	cpumMsrRd_Ia32SmrrPhysBase,
5155	cpumMsrRd_Ia32SmrrPhysMask,
5156	cpumMsrRd_Ia32PlatformDcaCap,
5157	cpumMsrRd_Ia32CpuDcaCap,
5158	cpumMsrRd_Ia32Dca0Cap,
5159	cpumMsrRd_Ia32PerfEvtSelN,
5160	cpumMsrRd_Ia32PerfStatus,
5161	cpumMsrRd_Ia32PerfCtl,
5162	cpumMsrRd_Ia32FixedCtrN,
5163	cpumMsrRd_Ia32PerfCapabilities,
5164	cpumMsrRd_Ia32FixedCtrCtrl,
5165	cpumMsrRd_Ia32PerfGlobalStatus,
5166	cpumMsrRd_Ia32PerfGlobalCtrl,
5167	cpumMsrRd_Ia32PerfGlobalOvfCtrl,
5168	cpumMsrRd_Ia32PebsEnable,
5169	cpumMsrRd_Ia32ClockModulation,
5170	cpumMsrRd_Ia32ThermInterrupt,
5171	cpumMsrRd_Ia32ThermStatus,
5172	cpumMsrRd_Ia32Therm2Ctl,
5173	cpumMsrRd_Ia32MiscEnable,
5174	cpumMsrRd_Ia32McCtlStatusAddrMiscN,
5175	cpumMsrRd_Ia32McNCtl2,
5176	cpumMsrRd_Ia32DsArea,
5177	cpumMsrRd_Ia32TscDeadline,
5178	cpumMsrRd_Ia32X2ApicN,
5179	cpumMsrRd_Ia32DebugInterface,
5180	cpumMsrRd_Ia32VmxBasic,
5181	cpumMsrRd_Ia32VmxPinbasedCtls,
5182	cpumMsrRd_Ia32VmxProcbasedCtls,
5183	cpumMsrRd_Ia32VmxExitCtls,
5184	cpumMsrRd_Ia32VmxEntryCtls,
5185	cpumMsrRd_Ia32VmxMisc,
5186	cpumMsrRd_Ia32VmxCr0Fixed0,
5187	cpumMsrRd_Ia32VmxCr0Fixed1,
5188	cpumMsrRd_Ia32VmxCr4Fixed0,
5189	cpumMsrRd_Ia32VmxCr4Fixed1,
5190	cpumMsrRd_Ia32VmxVmcsEnum,
5191	cpumMsrRd_Ia32VmxProcBasedCtls2,
5192	cpumMsrRd_Ia32VmxEptVpidCap,
5193	cpumMsrRd_Ia32VmxTruePinbasedCtls,
5194	cpumMsrRd_Ia32VmxTrueProcbasedCtls,
5195	cpumMsrRd_Ia32VmxTrueExitCtls,
5196	cpumMsrRd_Ia32VmxTrueEntryCtls,
5197	cpumMsrRd_Ia32VmxVmFunc,
5198	cpumMsrRd_Ia32SpecCtrl,
5199	cpumMsrRd_Ia32ArchCapabilities,
5200
5201	cpumMsrRd_Amd64Efer,
5202	cpumMsrRd_Amd64SyscallTarget,
5203	cpumMsrRd_Amd64LongSyscallTarget,
5204	cpumMsrRd_Amd64CompSyscallTarget,
5205	cpumMsrRd_Amd64SyscallFlagMask,
5206	cpumMsrRd_Amd64FsBase,
5207	cpumMsrRd_Amd64GsBase,
5208	cpumMsrRd_Amd64KernelGsBase,
5209	cpumMsrRd_Amd64TscAux,
5210
5211	cpumMsrRd_IntelEblCrPowerOn,
5212	cpumMsrRd_IntelI7CoreThreadCount,
5213	cpumMsrRd_IntelP4EbcHardPowerOn,
5214	cpumMsrRd_IntelP4EbcSoftPowerOn,
5215	cpumMsrRd_IntelP4EbcFrequencyId,
5216	cpumMsrRd_IntelP6FsbFrequency,
5217	cpumMsrRd_IntelPlatformInfo,
5218	cpumMsrRd_IntelFlexRatio,
5219	cpumMsrRd_IntelPkgCStConfigControl,
5220	cpumMsrRd_IntelPmgIoCaptureBase,
5221	cpumMsrRd_IntelLastBranchFromToN,
5222	cpumMsrRd_IntelLastBranchFromN,
5223	cpumMsrRd_IntelLastBranchToN,
5224	cpumMsrRd_IntelLastBranchTos,
5225	cpumMsrRd_IntelBblCrCtl,
5226	cpumMsrRd_IntelBblCrCtl3,
5227	cpumMsrRd_IntelI7TemperatureTarget,
5228	cpumMsrRd_IntelI7MsrOffCoreResponseN,
5229	cpumMsrRd_IntelI7MiscPwrMgmt,
5230	cpumMsrRd_IntelP6CrN,
5231	cpumMsrRd_IntelCpuId1FeatureMaskEcdx,
5232	cpumMsrRd_IntelCpuId1FeatureMaskEax,
5233	cpumMsrRd_IntelCpuId80000001FeatureMaskEcdx,
5234	cpumMsrRd_IntelI7SandyAesNiCtl,
5235	cpumMsrRd_IntelI7TurboRatioLimit,
5236	cpumMsrRd_IntelI7LbrSelect,
5237	cpumMsrRd_IntelI7SandyErrorControl,
5238	cpumMsrRd_IntelI7VirtualLegacyWireCap,
5239	cpumMsrRd_IntelI7PowerCtl,
5240	cpumMsrRd_IntelI7SandyPebsNumAlt,
5241	cpumMsrRd_IntelI7PebsLdLat,
5242	cpumMsrRd_IntelI7PkgCnResidencyN,
5243	cpumMsrRd_IntelI7CoreCnResidencyN,
5244	cpumMsrRd_IntelI7SandyVrCurrentConfig,
5245	cpumMsrRd_IntelI7SandyVrMiscConfig,
5246	cpumMsrRd_IntelI7SandyRaplPowerUnit,
5247	cpumMsrRd_IntelI7SandyPkgCnIrtlN,
5248	cpumMsrRd_IntelI7SandyPkgC2Residency,
5249	cpumMsrRd_IntelI7RaplPkgPowerLimit,
5250	cpumMsrRd_IntelI7RaplPkgEnergyStatus,
5251	cpumMsrRd_IntelI7RaplPkgPerfStatus,
5252	cpumMsrRd_IntelI7RaplPkgPowerInfo,
5253	cpumMsrRd_IntelI7RaplDramPowerLimit,
5254	cpumMsrRd_IntelI7RaplDramEnergyStatus,
5255	cpumMsrRd_IntelI7RaplDramPerfStatus,
5256	cpumMsrRd_IntelI7RaplDramPowerInfo,
5257	cpumMsrRd_IntelI7RaplPp0PowerLimit,
5258	cpumMsrRd_IntelI7RaplPp0EnergyStatus,
5259	cpumMsrRd_IntelI7RaplPp0Policy,
5260	cpumMsrRd_IntelI7RaplPp0PerfStatus,
5261	cpumMsrRd_IntelI7RaplPp1PowerLimit,
5262	cpumMsrRd_IntelI7RaplPp1EnergyStatus,
5263	cpumMsrRd_IntelI7RaplPp1Policy,
5264	cpumMsrRd_IntelI7IvyConfigTdpNominal,
5265	cpumMsrRd_IntelI7IvyConfigTdpLevel1,
5266	cpumMsrRd_IntelI7IvyConfigTdpLevel2,
5267	cpumMsrRd_IntelI7IvyConfigTdpControl,
5268	cpumMsrRd_IntelI7IvyTurboActivationRatio,
5269	cpumMsrRd_IntelI7UncPerfGlobalCtrl,
5270	cpumMsrRd_IntelI7UncPerfGlobalStatus,
5271	cpumMsrRd_IntelI7UncPerfGlobalOvfCtrl,
5272	cpumMsrRd_IntelI7UncPerfFixedCtrCtrl,
5273	cpumMsrRd_IntelI7UncPerfFixedCtr,
5274	cpumMsrRd_IntelI7UncCBoxConfig,
5275	cpumMsrRd_IntelI7UncArbPerfCtrN,
5276	cpumMsrRd_IntelI7UncArbPerfEvtSelN,
5277	cpumMsrRd_IntelI7SmiCount,
5278	cpumMsrRd_IntelCore2EmttmCrTablesN,
5279	cpumMsrRd_IntelCore2SmmCStMiscInfo,
5280	cpumMsrRd_IntelCore1ExtConfig,
5281	cpumMsrRd_IntelCore1DtsCalControl,
5282	cpumMsrRd_IntelCore2PeciControl,
5283	cpumMsrRd_IntelAtSilvCoreC1Recidency,
5284
5285	cpumMsrRd_P6LastBranchFromIp,
5286	cpumMsrRd_P6LastBranchToIp,
5287	cpumMsrRd_P6LastIntFromIp,
5288	cpumMsrRd_P6LastIntToIp,
5289
5290	cpumMsrRd_AmdFam15hTscRate,
5291	cpumMsrRd_AmdFam15hLwpCfg,
5292	cpumMsrRd_AmdFam15hLwpCbAddr,
5293	cpumMsrRd_AmdFam10hMc4MiscN,
5294	cpumMsrRd_AmdK8PerfCtlN,
5295	cpumMsrRd_AmdK8PerfCtrN,
5296	cpumMsrRd_AmdK8SysCfg,
5297	cpumMsrRd_AmdK8HwCr,
5298	cpumMsrRd_AmdK8IorrBaseN,
5299	cpumMsrRd_AmdK8IorrMaskN,
5300	cpumMsrRd_AmdK8TopOfMemN,
5301	cpumMsrRd_AmdK8NbCfg1,
5302	cpumMsrRd_AmdK8McXcptRedir,
5303	cpumMsrRd_AmdK8CpuNameN,
5304	cpumMsrRd_AmdK8HwThermalCtrl,
5305	cpumMsrRd_AmdK8SwThermalCtrl,
5306	cpumMsrRd_AmdK8FidVidControl,
5307	cpumMsrRd_AmdK8FidVidStatus,
5308	cpumMsrRd_AmdK8McCtlMaskN,
5309	cpumMsrRd_AmdK8SmiOnIoTrapN,
5310	cpumMsrRd_AmdK8SmiOnIoTrapCtlSts,
5311	cpumMsrRd_AmdK8IntPendingMessage,
5312	cpumMsrRd_AmdK8SmiTriggerIoCycle,
5313	cpumMsrRd_AmdFam10hMmioCfgBaseAddr,
5314	cpumMsrRd_AmdFam10hTrapCtlMaybe,
5315	cpumMsrRd_AmdFam10hPStateCurLimit,
5316	cpumMsrRd_AmdFam10hPStateControl,
5317	cpumMsrRd_AmdFam10hPStateStatus,
5318	cpumMsrRd_AmdFam10hPStateN,
5319	cpumMsrRd_AmdFam10hCofVidControl,
5320	cpumMsrRd_AmdFam10hCofVidStatus,
5321	cpumMsrRd_AmdFam10hCStateIoBaseAddr,
5322	cpumMsrRd_AmdFam10hCpuWatchdogTimer,
5323	cpumMsrRd_AmdK8SmmBase,
5324	cpumMsrRd_AmdK8SmmAddr,
5325	cpumMsrRd_AmdK8SmmMask,
5326	cpumMsrRd_AmdK8VmCr,
5327	cpumMsrRd_AmdK8IgnNe,
5328	cpumMsrRd_AmdK8SmmCtl,
5329	cpumMsrRd_AmdK8VmHSavePa,
5330	cpumMsrRd_AmdFam10hVmLockKey,
5331	cpumMsrRd_AmdFam10hSmmLockKey,
5332	cpumMsrRd_AmdFam10hLocalSmiStatus,
5333	cpumMsrRd_AmdFam10hOsVisWrkIdLength,
5334	cpumMsrRd_AmdFam10hOsVisWrkStatus,
5335	cpumMsrRd_AmdFam16hL2IPerfCtlN,
5336	cpumMsrRd_AmdFam16hL2IPerfCtrN,
5337	cpumMsrRd_AmdFam15hNorthbridgePerfCtlN,
5338	cpumMsrRd_AmdFam15hNorthbridgePerfCtrN,
5339	cpumMsrRd_AmdK7MicrocodeCtl,
5340	cpumMsrRd_AmdK7ClusterIdMaybe,
5341	cpumMsrRd_AmdK8CpuIdCtlStd07hEbax,
5342	cpumMsrRd_AmdK8CpuIdCtlStd06hEcx,
5343	cpumMsrRd_AmdK8CpuIdCtlStd01hEdcx,
5344	cpumMsrRd_AmdK8CpuIdCtlExt01hEdcx,
5345	cpumMsrRd_AmdK8PatchLevel,
5346	cpumMsrRd_AmdK7DebugStatusMaybe,
5347	cpumMsrRd_AmdK7BHTraceBaseMaybe,
5348	cpumMsrRd_AmdK7BHTracePtrMaybe,
5349	cpumMsrRd_AmdK7BHTraceLimitMaybe,
5350	cpumMsrRd_AmdK7HardwareDebugToolCfgMaybe,
5351	cpumMsrRd_AmdK7FastFlushCountMaybe,
5352	cpumMsrRd_AmdK7NodeId,
5353	cpumMsrRd_AmdK7DrXAddrMaskN,
5354	cpumMsrRd_AmdK7Dr0DataMatchMaybe,
5355	cpumMsrRd_AmdK7Dr0DataMaskMaybe,
5356	cpumMsrRd_AmdK7LoadStoreCfg,
5357	cpumMsrRd_AmdK7InstrCacheCfg,
5358	cpumMsrRd_AmdK7DataCacheCfg,
5359	cpumMsrRd_AmdK7BusUnitCfg,
5360	cpumMsrRd_AmdK7DebugCtl2Maybe,
5361	cpumMsrRd_AmdFam15hFpuCfg,
5362	cpumMsrRd_AmdFam15hDecoderCfg,
5363	cpumMsrRd_AmdFam10hBusUnitCfg2,
5364	cpumMsrRd_AmdFam15hCombUnitCfg,
5365	cpumMsrRd_AmdFam15hCombUnitCfg2,
5366	cpumMsrRd_AmdFam15hCombUnitCfg3,
5367	cpumMsrRd_AmdFam15hExecUnitCfg,
5368	cpumMsrRd_AmdFam15hLoadStoreCfg2,
5369	cpumMsrRd_AmdFam10hIbsFetchCtl,
5370	cpumMsrRd_AmdFam10hIbsFetchLinAddr,
5371	cpumMsrRd_AmdFam10hIbsFetchPhysAddr,
5372	cpumMsrRd_AmdFam10hIbsOpExecCtl,
5373	cpumMsrRd_AmdFam10hIbsOpRip,
5374	cpumMsrRd_AmdFam10hIbsOpData,
5375	cpumMsrRd_AmdFam10hIbsOpData2,
5376	cpumMsrRd_AmdFam10hIbsOpData3,
5377	cpumMsrRd_AmdFam10hIbsDcLinAddr,
5378	cpumMsrRd_AmdFam10hIbsDcPhysAddr,
5379	cpumMsrRd_AmdFam10hIbsCtl,
5380	cpumMsrRd_AmdFam14hIbsBrTarget,
5381
5382	cpumMsrRd_Gim
5383	};
5384
5385
5386	/**
5387	* MSR write function table.
5388	*/
5389	static const PFNCPUMWRMSR g_aCpumWrMsrFns[kCpumMsrWrFn_End] =
5390	{
5391	NULL, /* Invalid */
5392	cpumMsrWr_IgnoreWrite,
5393	cpumMsrWr_ReadOnly,
5394	NULL, /* Alias */
5395	cpumMsrWr_Ia32P5McAddr,
5396	cpumMsrWr_Ia32P5McType,
5397	cpumMsrWr_Ia32TimestampCounter,
5398	cpumMsrWr_Ia32ApicBase,
5399	cpumMsrWr_Ia32FeatureControl,
5400	cpumMsrWr_Ia32BiosSignId,
5401	cpumMsrWr_Ia32BiosUpdateTrigger,
5402	cpumMsrWr_Ia32SmmMonitorCtl,
5403	cpumMsrWr_Ia32PmcN,
5404	cpumMsrWr_Ia32MonitorFilterLineSize,
5405	cpumMsrWr_Ia32MPerf,
5406	cpumMsrWr_Ia32APerf,
5407	cpumMsrWr_Ia32MtrrPhysBaseN,
5408	cpumMsrWr_Ia32MtrrPhysMaskN,
5409	cpumMsrWr_Ia32MtrrFixed,
5410	cpumMsrWr_Ia32MtrrDefType,
5411	cpumMsrWr_Ia32Pat,
5412	cpumMsrWr_Ia32SysEnterCs,
5413	cpumMsrWr_Ia32SysEnterEsp,
5414	cpumMsrWr_Ia32SysEnterEip,
5415	cpumMsrWr_Ia32McgStatus,
5416	cpumMsrWr_Ia32McgCtl,
5417	cpumMsrWr_Ia32DebugCtl,
5418	cpumMsrWr_Ia32SmrrPhysBase,
5419	cpumMsrWr_Ia32SmrrPhysMask,
5420	cpumMsrWr_Ia32PlatformDcaCap,
5421	cpumMsrWr_Ia32Dca0Cap,
5422	cpumMsrWr_Ia32PerfEvtSelN,
5423	cpumMsrWr_Ia32PerfStatus,
5424	cpumMsrWr_Ia32PerfCtl,
5425	cpumMsrWr_Ia32FixedCtrN,
5426	cpumMsrWr_Ia32PerfCapabilities,
5427	cpumMsrWr_Ia32FixedCtrCtrl,
5428	cpumMsrWr_Ia32PerfGlobalStatus,
5429	cpumMsrWr_Ia32PerfGlobalCtrl,
5430	cpumMsrWr_Ia32PerfGlobalOvfCtrl,
5431	cpumMsrWr_Ia32PebsEnable,
5432	cpumMsrWr_Ia32ClockModulation,
5433	cpumMsrWr_Ia32ThermInterrupt,
5434	cpumMsrWr_Ia32ThermStatus,
5435	cpumMsrWr_Ia32Therm2Ctl,
5436	cpumMsrWr_Ia32MiscEnable,
5437	cpumMsrWr_Ia32McCtlStatusAddrMiscN,
5438	cpumMsrWr_Ia32McNCtl2,
5439	cpumMsrWr_Ia32DsArea,
5440	cpumMsrWr_Ia32TscDeadline,
5441	cpumMsrWr_Ia32X2ApicN,
5442	cpumMsrWr_Ia32DebugInterface,
5443	cpumMsrWr_Ia32SpecCtrl,
5444	cpumMsrWr_Ia32PredCmd,
5445
5446	cpumMsrWr_Amd64Efer,
5447	cpumMsrWr_Amd64SyscallTarget,
5448	cpumMsrWr_Amd64LongSyscallTarget,
5449	cpumMsrWr_Amd64CompSyscallTarget,
5450	cpumMsrWr_Amd64SyscallFlagMask,
5451	cpumMsrWr_Amd64FsBase,
5452	cpumMsrWr_Amd64GsBase,
5453	cpumMsrWr_Amd64KernelGsBase,
5454	cpumMsrWr_Amd64TscAux,
5455
5456	cpumMsrWr_IntelEblCrPowerOn,
5457	cpumMsrWr_IntelP4EbcHardPowerOn,
5458	cpumMsrWr_IntelP4EbcSoftPowerOn,
5459	cpumMsrWr_IntelP4EbcFrequencyId,
5460	cpumMsrWr_IntelFlexRatio,
5461	cpumMsrWr_IntelPkgCStConfigControl,
5462	cpumMsrWr_IntelPmgIoCaptureBase,
5463	cpumMsrWr_IntelLastBranchFromToN,
5464	cpumMsrWr_IntelLastBranchFromN,
5465	cpumMsrWr_IntelLastBranchToN,
5466	cpumMsrWr_IntelLastBranchTos,
5467	cpumMsrWr_IntelBblCrCtl,
5468	cpumMsrWr_IntelBblCrCtl3,
5469	cpumMsrWr_IntelI7TemperatureTarget,
5470	cpumMsrWr_IntelI7MsrOffCoreResponseN,
5471	cpumMsrWr_IntelI7MiscPwrMgmt,
5472	cpumMsrWr_IntelP6CrN,
5473	cpumMsrWr_IntelCpuId1FeatureMaskEcdx,
5474	cpumMsrWr_IntelCpuId1FeatureMaskEax,
5475	cpumMsrWr_IntelCpuId80000001FeatureMaskEcdx,
5476	cpumMsrWr_IntelI7SandyAesNiCtl,
5477	cpumMsrWr_IntelI7TurboRatioLimit,
5478	cpumMsrWr_IntelI7LbrSelect,
5479	cpumMsrWr_IntelI7SandyErrorControl,
5480	cpumMsrWr_IntelI7PowerCtl,
5481	cpumMsrWr_IntelI7SandyPebsNumAlt,
5482	cpumMsrWr_IntelI7PebsLdLat,
5483	cpumMsrWr_IntelI7SandyVrCurrentConfig,
5484	cpumMsrWr_IntelI7SandyVrMiscConfig,
5485	cpumMsrWr_IntelI7SandyRaplPowerUnit,
5486	cpumMsrWr_IntelI7SandyPkgCnIrtlN,
5487	cpumMsrWr_IntelI7SandyPkgC2Residency,
5488	cpumMsrWr_IntelI7RaplPkgPowerLimit,
5489	cpumMsrWr_IntelI7RaplDramPowerLimit,
5490	cpumMsrWr_IntelI7RaplPp0PowerLimit,
5491	cpumMsrWr_IntelI7RaplPp0Policy,
5492	cpumMsrWr_IntelI7RaplPp1PowerLimit,
5493	cpumMsrWr_IntelI7RaplPp1Policy,
5494	cpumMsrWr_IntelI7IvyConfigTdpControl,
5495	cpumMsrWr_IntelI7IvyTurboActivationRatio,
5496	cpumMsrWr_IntelI7UncPerfGlobalCtrl,
5497	cpumMsrWr_IntelI7UncPerfGlobalStatus,
5498	cpumMsrWr_IntelI7UncPerfGlobalOvfCtrl,
5499	cpumMsrWr_IntelI7UncPerfFixedCtrCtrl,
5500	cpumMsrWr_IntelI7UncPerfFixedCtr,
5501	cpumMsrWr_IntelI7UncArbPerfCtrN,
5502	cpumMsrWr_IntelI7UncArbPerfEvtSelN,
5503	cpumMsrWr_IntelCore2EmttmCrTablesN,
5504	cpumMsrWr_IntelCore2SmmCStMiscInfo,
5505	cpumMsrWr_IntelCore1ExtConfig,
5506	cpumMsrWr_IntelCore1DtsCalControl,
5507	cpumMsrWr_IntelCore2PeciControl,
5508
5509	cpumMsrWr_P6LastIntFromIp,
5510	cpumMsrWr_P6LastIntToIp,
5511
5512	cpumMsrWr_AmdFam15hTscRate,
5513	cpumMsrWr_AmdFam15hLwpCfg,
5514	cpumMsrWr_AmdFam15hLwpCbAddr,
5515	cpumMsrWr_AmdFam10hMc4MiscN,
5516	cpumMsrWr_AmdK8PerfCtlN,
5517	cpumMsrWr_AmdK8PerfCtrN,
5518	cpumMsrWr_AmdK8SysCfg,
5519	cpumMsrWr_AmdK8HwCr,
5520	cpumMsrWr_AmdK8IorrBaseN,
5521	cpumMsrWr_AmdK8IorrMaskN,
5522	cpumMsrWr_AmdK8TopOfMemN,
5523	cpumMsrWr_AmdK8NbCfg1,
5524	cpumMsrWr_AmdK8McXcptRedir,
5525	cpumMsrWr_AmdK8CpuNameN,
5526	cpumMsrWr_AmdK8HwThermalCtrl,
5527	cpumMsrWr_AmdK8SwThermalCtrl,
5528	cpumMsrWr_AmdK8FidVidControl,
5529	cpumMsrWr_AmdK8McCtlMaskN,
5530	cpumMsrWr_AmdK8SmiOnIoTrapN,
5531	cpumMsrWr_AmdK8SmiOnIoTrapCtlSts,
5532	cpumMsrWr_AmdK8IntPendingMessage,
5533	cpumMsrWr_AmdK8SmiTriggerIoCycle,
5534	cpumMsrWr_AmdFam10hMmioCfgBaseAddr,
5535	cpumMsrWr_AmdFam10hTrapCtlMaybe,
5536	cpumMsrWr_AmdFam10hPStateControl,
5537	cpumMsrWr_AmdFam10hPStateStatus,
5538	cpumMsrWr_AmdFam10hPStateN,
5539	cpumMsrWr_AmdFam10hCofVidControl,
5540	cpumMsrWr_AmdFam10hCofVidStatus,
5541	cpumMsrWr_AmdFam10hCStateIoBaseAddr,
5542	cpumMsrWr_AmdFam10hCpuWatchdogTimer,
5543	cpumMsrWr_AmdK8SmmBase,
5544	cpumMsrWr_AmdK8SmmAddr,
5545	cpumMsrWr_AmdK8SmmMask,
5546	cpumMsrWr_AmdK8VmCr,
5547	cpumMsrWr_AmdK8IgnNe,
5548	cpumMsrWr_AmdK8SmmCtl,
5549	cpumMsrWr_AmdK8VmHSavePa,
5550	cpumMsrWr_AmdFam10hVmLockKey,
5551	cpumMsrWr_AmdFam10hSmmLockKey,
5552	cpumMsrWr_AmdFam10hLocalSmiStatus,
5553	cpumMsrWr_AmdFam10hOsVisWrkIdLength,
5554	cpumMsrWr_AmdFam10hOsVisWrkStatus,
5555	cpumMsrWr_AmdFam16hL2IPerfCtlN,
5556	cpumMsrWr_AmdFam16hL2IPerfCtrN,
5557	cpumMsrWr_AmdFam15hNorthbridgePerfCtlN,
5558	cpumMsrWr_AmdFam15hNorthbridgePerfCtrN,
5559	cpumMsrWr_AmdK7MicrocodeCtl,
5560	cpumMsrWr_AmdK7ClusterIdMaybe,
5561	cpumMsrWr_AmdK8CpuIdCtlStd07hEbax,
5562	cpumMsrWr_AmdK8CpuIdCtlStd06hEcx,
5563	cpumMsrWr_AmdK8CpuIdCtlStd01hEdcx,
5564	cpumMsrWr_AmdK8CpuIdCtlExt01hEdcx,
5565	cpumMsrWr_AmdK8PatchLoader,
5566	cpumMsrWr_AmdK7DebugStatusMaybe,
5567	cpumMsrWr_AmdK7BHTraceBaseMaybe,
5568	cpumMsrWr_AmdK7BHTracePtrMaybe,
5569	cpumMsrWr_AmdK7BHTraceLimitMaybe,
5570	cpumMsrWr_AmdK7HardwareDebugToolCfgMaybe,
5571	cpumMsrWr_AmdK7FastFlushCountMaybe,
5572	cpumMsrWr_AmdK7NodeId,
5573	cpumMsrWr_AmdK7DrXAddrMaskN,
5574	cpumMsrWr_AmdK7Dr0DataMatchMaybe,
5575	cpumMsrWr_AmdK7Dr0DataMaskMaybe,
5576	cpumMsrWr_AmdK7LoadStoreCfg,
5577	cpumMsrWr_AmdK7InstrCacheCfg,
5578	cpumMsrWr_AmdK7DataCacheCfg,
5579	cpumMsrWr_AmdK7BusUnitCfg,
5580	cpumMsrWr_AmdK7DebugCtl2Maybe,
5581	cpumMsrWr_AmdFam15hFpuCfg,
5582	cpumMsrWr_AmdFam15hDecoderCfg,
5583	cpumMsrWr_AmdFam10hBusUnitCfg2,
5584	cpumMsrWr_AmdFam15hCombUnitCfg,
5585	cpumMsrWr_AmdFam15hCombUnitCfg2,
5586	cpumMsrWr_AmdFam15hCombUnitCfg3,
5587	cpumMsrWr_AmdFam15hExecUnitCfg,
5588	cpumMsrWr_AmdFam15hLoadStoreCfg2,
5589	cpumMsrWr_AmdFam10hIbsFetchCtl,
5590	cpumMsrWr_AmdFam10hIbsFetchLinAddr,
5591	cpumMsrWr_AmdFam10hIbsFetchPhysAddr,
5592	cpumMsrWr_AmdFam10hIbsOpExecCtl,
5593	cpumMsrWr_AmdFam10hIbsOpRip,
5594	cpumMsrWr_AmdFam10hIbsOpData,
5595	cpumMsrWr_AmdFam10hIbsOpData2,
5596	cpumMsrWr_AmdFam10hIbsOpData3,
5597	cpumMsrWr_AmdFam10hIbsDcLinAddr,
5598	cpumMsrWr_AmdFam10hIbsDcPhysAddr,
5599	cpumMsrWr_AmdFam10hIbsCtl,
5600	cpumMsrWr_AmdFam14hIbsBrTarget,
5601
5602	cpumMsrWr_Gim
5603	};
5604
5605
5606	/**
5607	* Looks up the range for the given MSR.
5608	*
5609	* @returns Pointer to the range if found, NULL if not.
5610	* @param pVM The cross context VM structure.
5611	* @param idMsr The MSR to look up.
5612	*/
5613	# ifndef IN_RING3
5614	static
5615	# endif
5616	PCPUMMSRRANGE cpumLookupMsrRange(PVM pVM, uint32_t idMsr)
5617	{
5618	/*
5619	* Binary lookup.
5620	*/
5621	uint32_t cRanges = pVM->cpum.s.GuestInfo.cMsrRanges;
5622	if (!cRanges)
5623	return NULL;
5624	PCPUMMSRRANGE paRanges = pVM->cpum.s.GuestInfo.CTX_SUFF(paMsrRanges);
5625	for (;;)
5626	{
5627	uint32_t i = cRanges / 2;
5628	if (idMsr < paRanges[i].uFirst)
5629	{
5630	if (i == 0)
5631	break;
5632	cRanges = i;
5633	}
5634	else if (idMsr > paRanges[i].uLast)
5635	{
5636	i++;
5637	if (i >= cRanges)
5638	break;
5639	cRanges -= i;
5640	paRanges = &paRanges[i];
5641	}
5642	else
5643	{
5644	if (paRanges[i].enmRdFn == kCpumMsrRdFn_MsrAlias)
5645	return cpumLookupMsrRange(pVM, paRanges[i].uValue);
5646	return &paRanges[i];
5647	}
5648	}
5649
5650	# ifdef VBOX_STRICT
5651	/*
5652	* Linear lookup to verify the above binary search.
5653	*/
5654	uint32_t cLeft = pVM->cpum.s.GuestInfo.cMsrRanges;
5655	PCPUMMSRRANGE pCur = pVM->cpum.s.GuestInfo.CTX_SUFF(paMsrRanges);
5656	while (cLeft-- > 0)
5657	{
5658	if (idMsr >= pCur->uFirst && idMsr <= pCur->uLast)
5659	{
5660	AssertFailed();
5661	if (pCur->enmRdFn == kCpumMsrRdFn_MsrAlias)
5662	return cpumLookupMsrRange(pVM, pCur->uValue);
5663	return pCur;
5664	}
5665	pCur++;
5666	}
5667	# endif
5668	return NULL;
5669	}
5670
5671
5672	/**
5673	* Query a guest MSR.
5674	*
5675	* The caller is responsible for checking privilege if the call is the result of
5676	* a RDMSR instruction. We'll do the rest.
5677	*
5678	* @retval VINF_SUCCESS on success.
5679	* @retval VINF_CPUM_R3_MSR_READ if the MSR read could not be serviced in the
5680	* current context (raw-mode or ring-0).
5681	* @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR), the caller is
5682	* expected to take the appropriate actions. @a *puValue is set to 0.
5683	* @param pVCpu The cross context virtual CPU structure.
5684	* @param idMsr The MSR.
5685	* @param puValue Where to return the value.
5686	*
5687	* @remarks This will always return the right values, even when we're in the
5688	* recompiler.
5689	*/
5690	VMMDECL(VBOXSTRICTRC) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue)
5691	{
5692	*puValue = 0;
5693
5694	VBOXSTRICTRC rcStrict;
5695	PVM pVM = pVCpu->CTX_SUFF(pVM);
5696	PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, idMsr);
5697	if (pRange)
5698	{
5699	CPUMMSRRDFN enmRdFn = (CPUMMSRRDFN)pRange->enmRdFn;
5700	AssertReturn(enmRdFn > kCpumMsrRdFn_Invalid && enmRdFn < kCpumMsrRdFn_End, VERR_CPUM_IPE_1);
5701
5702	PFNCPUMRDMSR pfnRdMsr = g_aCpumRdMsrFns[enmRdFn];
5703	AssertReturn(pfnRdMsr, VERR_CPUM_IPE_2);
5704
5705	STAM_COUNTER_INC(&pRange->cReads);
5706	STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReads);
5707
5708	rcStrict = pfnRdMsr(pVCpu, idMsr, pRange, puValue);
5709	if (rcStrict == VINF_SUCCESS)
5710	Log2(("CPUM: RDMSR %#x (%s) -> %#llx\n", idMsr, pRange->szName, *puValue));
5711	else if (rcStrict == VERR_CPUM_RAISE_GP_0)
5712	{
5713	Log(("CPUM: RDMSR %#x (%s) -> #GP(0)\n", idMsr, pRange->szName));
5714	STAM_COUNTER_INC(&pRange->cGps);
5715	STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReadsRaiseGp);
5716	}
5717	#ifndef IN_RING3
5718	else if (rcStrict == VINF_CPUM_R3_MSR_READ)
5719	Log(("CPUM: RDMSR %#x (%s) -> ring-3\n", idMsr, pRange->szName));
5720	#endif
5721	else
5722	{
5723	Log(("CPUM: RDMSR %#x (%s) -> rcStrict=%Rrc\n", idMsr, pRange->szName, VBOXSTRICTRC_VAL(rcStrict)));
5724	AssertMsgStmt(RT_FAILURE_NP(rcStrict), ("%Rrc idMsr=%#x\n", VBOXSTRICTRC_VAL(rcStrict), idMsr),
5725	rcStrict = VERR_IPE_UNEXPECTED_INFO_STATUS);
5726	Assert(rcStrict != VERR_EM_INTERPRETER);
5727	}
5728	}
5729	else
5730	{
5731	Log(("CPUM: Unknown RDMSR %#x -> #GP(0)\n", idMsr));
5732	STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReads);
5733	STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReadsUnknown);
5734	rcStrict = VERR_CPUM_RAISE_GP_0;
5735	}
5736	return rcStrict;
5737	}
5738
5739
5740	/**
5741	* Writes to a guest MSR.
5742	*
5743	* The caller is responsible for checking privilege if the call is the result of
5744	* a WRMSR instruction. We'll do the rest.
5745	*
5746	* @retval VINF_SUCCESS on success.
5747	* @retval VINF_CPUM_R3_MSR_WRITE if the MSR write could not be serviced in the
5748	* current context (raw-mode or ring-0).
5749	* @retval VERR_CPUM_RAISE_GP_0 on failure, the caller is expected to take the
5750	* appropriate actions.
5751	*
5752	* @param pVCpu The cross context virtual CPU structure.
5753	* @param idMsr The MSR id.
5754	* @param uValue The value to set.
5755	*
5756	* @remarks Everyone changing MSR values, including the recompiler, shall do it
5757	* by calling this method. This makes sure we have current values and
5758	* that we trigger all the right actions when something changes.
5759	*
5760	* For performance reasons, this actually isn't entirely true for some
5761	* MSRs when in HM mode. The code here and in HM must be aware of
5762	* this.
5763	*/
5764	VMMDECL(VBOXSTRICTRC) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue)
5765	{
5766	VBOXSTRICTRC rcStrict;
5767	PVM pVM = pVCpu->CTX_SUFF(pVM);
5768	PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, idMsr);
5769	if (pRange)
5770	{
5771	STAM_COUNTER_INC(&pRange->cWrites);
5772	STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWrites);
5773
5774	if (!(uValue & pRange->fWrGpMask))
5775	{
5776	CPUMMSRWRFN enmWrFn = (CPUMMSRWRFN)pRange->enmWrFn;
5777	AssertReturn(enmWrFn > kCpumMsrWrFn_Invalid && enmWrFn < kCpumMsrWrFn_End, VERR_CPUM_IPE_1);
5778
5779	PFNCPUMWRMSR pfnWrMsr = g_aCpumWrMsrFns[enmWrFn];
5780	AssertReturn(pfnWrMsr, VERR_CPUM_IPE_2);
5781
5782	uint64_t uValueAdjusted = uValue & ~pRange->fWrIgnMask;
5783	if (uValueAdjusted != uValue)
5784	{
5785	STAM_COUNTER_INC(&pRange->cIgnoredBits);
5786	STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesToIgnoredBits);
5787	}
5788
5789	rcStrict = pfnWrMsr(pVCpu, idMsr, pRange, uValueAdjusted, uValue);
5790	if (rcStrict == VINF_SUCCESS)
5791	Log2(("CPUM: WRMSR %#x (%s), %#llx [%#llx]\n", idMsr, pRange->szName, uValueAdjusted, uValue));
5792	else if (rcStrict == VERR_CPUM_RAISE_GP_0)
5793	{
5794	Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> #GP(0)\n", idMsr, pRange->szName, uValueAdjusted, uValue));
5795	STAM_COUNTER_INC(&pRange->cGps);
5796	STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesRaiseGp);
5797	}
5798	#ifndef IN_RING3
5799	else if (rcStrict == VINF_CPUM_R3_MSR_WRITE)
5800	Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> ring-3\n", idMsr, pRange->szName, uValueAdjusted, uValue));
5801	#endif
5802	else
5803	{
5804	Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> rcStrict=%Rrc\n",
5805	idMsr, pRange->szName, uValueAdjusted, uValue, VBOXSTRICTRC_VAL(rcStrict)));
5806	AssertMsgStmt(RT_FAILURE_NP(rcStrict), ("%Rrc idMsr=%#x\n", VBOXSTRICTRC_VAL(rcStrict), idMsr),
5807	rcStrict = VERR_IPE_UNEXPECTED_INFO_STATUS);
5808	Assert(rcStrict != VERR_EM_INTERPRETER);
5809	}
5810	}
5811	else
5812	{
5813	Log(("CPUM: WRMSR %#x (%s), %#llx -> #GP(0) - invalid bits %#llx\n",
5814	idMsr, pRange->szName, uValue, uValue & pRange->fWrGpMask));
5815	STAM_COUNTER_INC(&pRange->cGps);
5816	STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesRaiseGp);
5817	rcStrict = VERR_CPUM_RAISE_GP_0;
5818	}
5819	}
5820	else
5821	{
5822	Log(("CPUM: Unknown WRMSR %#x, %#llx -> #GP(0)\n", idMsr, uValue));
5823	STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWrites);
5824	STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesUnknown);
5825	rcStrict = VERR_CPUM_RAISE_GP_0;
5826	}
5827	return rcStrict;
5828	}
5829
5830
5831	#if defined(VBOX_STRICT) && defined(IN_RING3)
5832	/**
5833	* Performs some checks on the static data related to MSRs.
5834	*
5835	* @returns VINF_SUCCESS on success, error on failure.
5836	*/
5837	int cpumR3MsrStrictInitChecks(void)
5838	{
5839	#define CPUM_ASSERT_RD_MSR_FN(a_Register) \
5840	AssertReturn(g_aCpumRdMsrFns[kCpumMsrRdFn_##a_Register] == cpumMsrRd_##a_Register, VERR_CPUM_IPE_2);
5841	#define CPUM_ASSERT_WR_MSR_FN(a_Register) \
5842	AssertReturn(g_aCpumWrMsrFns[kCpumMsrWrFn_##a_Register] == cpumMsrWr_##a_Register, VERR_CPUM_IPE_2);
5843
5844	AssertReturn(g_aCpumRdMsrFns[kCpumMsrRdFn_Invalid] == NULL, VERR_CPUM_IPE_2);
5845	CPUM_ASSERT_RD_MSR_FN(FixedValue);
5846	CPUM_ASSERT_RD_MSR_FN(WriteOnly);
5847	CPUM_ASSERT_RD_MSR_FN(Ia32P5McAddr);
5848	CPUM_ASSERT_RD_MSR_FN(Ia32P5McType);
5849	CPUM_ASSERT_RD_MSR_FN(Ia32TimestampCounter);
5850	CPUM_ASSERT_RD_MSR_FN(Ia32PlatformId);
5851	CPUM_ASSERT_RD_MSR_FN(Ia32ApicBase);
5852	CPUM_ASSERT_RD_MSR_FN(Ia32FeatureControl);
5853	CPUM_ASSERT_RD_MSR_FN(Ia32BiosSignId);
5854	CPUM_ASSERT_RD_MSR_FN(Ia32SmmMonitorCtl);
5855	CPUM_ASSERT_RD_MSR_FN(Ia32PmcN);
5856	CPUM_ASSERT_RD_MSR_FN(Ia32MonitorFilterLineSize);
5857	CPUM_ASSERT_RD_MSR_FN(Ia32MPerf);
5858	CPUM_ASSERT_RD_MSR_FN(Ia32APerf);
5859	CPUM_ASSERT_RD_MSR_FN(Ia32MtrrCap);
5860	CPUM_ASSERT_RD_MSR_FN(Ia32MtrrPhysBaseN);
5861	CPUM_ASSERT_RD_MSR_FN(Ia32MtrrPhysMaskN);
5862	CPUM_ASSERT_RD_MSR_FN(Ia32MtrrFixed);
5863	CPUM_ASSERT_RD_MSR_FN(Ia32MtrrDefType);
5864	CPUM_ASSERT_RD_MSR_FN(Ia32Pat);
5865	CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterCs);
5866	CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterEsp);
5867	CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterEip);
5868	CPUM_ASSERT_RD_MSR_FN(Ia32McgCap);
5869	CPUM_ASSERT_RD_MSR_FN(Ia32McgStatus);
5870	CPUM_ASSERT_RD_MSR_FN(Ia32McgCtl);
5871	CPUM_ASSERT_RD_MSR_FN(Ia32DebugCtl);
5872	CPUM_ASSERT_RD_MSR_FN(Ia32SmrrPhysBase);
5873	CPUM_ASSERT_RD_MSR_FN(Ia32SmrrPhysMask);
5874	CPUM_ASSERT_RD_MSR_FN(Ia32PlatformDcaCap);
5875	CPUM_ASSERT_RD_MSR_FN(Ia32CpuDcaCap);
5876	CPUM_ASSERT_RD_MSR_FN(Ia32Dca0Cap);
5877	CPUM_ASSERT_RD_MSR_FN(Ia32PerfEvtSelN);
5878	CPUM_ASSERT_RD_MSR_FN(Ia32PerfStatus);
5879	CPUM_ASSERT_RD_MSR_FN(Ia32PerfCtl);
5880	CPUM_ASSERT_RD_MSR_FN(Ia32FixedCtrN);
5881	CPUM_ASSERT_RD_MSR_FN(Ia32PerfCapabilities);
5882	CPUM_ASSERT_RD_MSR_FN(Ia32FixedCtrCtrl);
5883	CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalStatus);
5884	CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalCtrl);
5885	CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalOvfCtrl);
5886	CPUM_ASSERT_RD_MSR_FN(Ia32PebsEnable);
5887	CPUM_ASSERT_RD_MSR_FN(Ia32ClockModulation);
5888	CPUM_ASSERT_RD_MSR_FN(Ia32ThermInterrupt);
5889	CPUM_ASSERT_RD_MSR_FN(Ia32ThermStatus);
5890	CPUM_ASSERT_RD_MSR_FN(Ia32MiscEnable);
5891	CPUM_ASSERT_RD_MSR_FN(Ia32McCtlStatusAddrMiscN);
5892	CPUM_ASSERT_RD_MSR_FN(Ia32McNCtl2);
5893	CPUM_ASSERT_RD_MSR_FN(Ia32DsArea);
5894	CPUM_ASSERT_RD_MSR_FN(Ia32TscDeadline);
5895	CPUM_ASSERT_RD_MSR_FN(Ia32X2ApicN);
5896	CPUM_ASSERT_RD_MSR_FN(Ia32DebugInterface);
5897	CPUM_ASSERT_RD_MSR_FN(Ia32VmxBasic);
5898	CPUM_ASSERT_RD_MSR_FN(Ia32VmxPinbasedCtls);
5899	CPUM_ASSERT_RD_MSR_FN(Ia32VmxProcbasedCtls);
5900	CPUM_ASSERT_RD_MSR_FN(Ia32VmxExitCtls);
5901	CPUM_ASSERT_RD_MSR_FN(Ia32VmxEntryCtls);
5902	CPUM_ASSERT_RD_MSR_FN(Ia32VmxMisc);
5903	CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr0Fixed0);
5904	CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr0Fixed1);
5905	CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr4Fixed0);
5906	CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr4Fixed1);
5907	CPUM_ASSERT_RD_MSR_FN(Ia32VmxVmcsEnum);
5908	CPUM_ASSERT_RD_MSR_FN(Ia32VmxProcBasedCtls2);
5909	CPUM_ASSERT_RD_MSR_FN(Ia32VmxEptVpidCap);
5910	CPUM_ASSERT_RD_MSR_FN(Ia32VmxTruePinbasedCtls);
5911	CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueProcbasedCtls);
5912	CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueExitCtls);
5913	CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueEntryCtls);
5914	CPUM_ASSERT_RD_MSR_FN(Ia32VmxVmFunc);
5915	CPUM_ASSERT_RD_MSR_FN(Ia32SpecCtrl);
5916	CPUM_ASSERT_RD_MSR_FN(Ia32ArchCapabilities);
5917
5918	CPUM_ASSERT_RD_MSR_FN(Amd64Efer);
5919	CPUM_ASSERT_RD_MSR_FN(Amd64SyscallTarget);
5920	CPUM_ASSERT_RD_MSR_FN(Amd64LongSyscallTarget);
5921	CPUM_ASSERT_RD_MSR_FN(Amd64CompSyscallTarget);
5922	CPUM_ASSERT_RD_MSR_FN(Amd64SyscallFlagMask);
5923	CPUM_ASSERT_RD_MSR_FN(Amd64FsBase);
5924	CPUM_ASSERT_RD_MSR_FN(Amd64GsBase);
5925	CPUM_ASSERT_RD_MSR_FN(Amd64KernelGsBase);
5926	CPUM_ASSERT_RD_MSR_FN(Amd64TscAux);
5927
5928	CPUM_ASSERT_RD_MSR_FN(IntelEblCrPowerOn);
5929	CPUM_ASSERT_RD_MSR_FN(IntelI7CoreThreadCount);
5930	CPUM_ASSERT_RD_MSR_FN(IntelP4EbcHardPowerOn);
5931	CPUM_ASSERT_RD_MSR_FN(IntelP4EbcSoftPowerOn);
5932	CPUM_ASSERT_RD_MSR_FN(IntelP4EbcFrequencyId);
5933	CPUM_ASSERT_RD_MSR_FN(IntelP6FsbFrequency);
5934	CPUM_ASSERT_RD_MSR_FN(IntelPlatformInfo);
5935	CPUM_ASSERT_RD_MSR_FN(IntelFlexRatio);
5936	CPUM_ASSERT_RD_MSR_FN(IntelPkgCStConfigControl);
5937	CPUM_ASSERT_RD_MSR_FN(IntelPmgIoCaptureBase);
5938	CPUM_ASSERT_RD_MSR_FN(IntelLastBranchFromToN);
5939	CPUM_ASSERT_RD_MSR_FN(IntelLastBranchFromN);
5940	CPUM_ASSERT_RD_MSR_FN(IntelLastBranchToN);
5941	CPUM_ASSERT_RD_MSR_FN(IntelLastBranchTos);
5942	CPUM_ASSERT_RD_MSR_FN(IntelBblCrCtl);
5943	CPUM_ASSERT_RD_MSR_FN(IntelBblCrCtl3);
5944	CPUM_ASSERT_RD_MSR_FN(IntelI7TemperatureTarget);
5945	CPUM_ASSERT_RD_MSR_FN(IntelI7MsrOffCoreResponseN);
5946	CPUM_ASSERT_RD_MSR_FN(IntelI7MiscPwrMgmt);
5947	CPUM_ASSERT_RD_MSR_FN(IntelP6CrN);
5948	CPUM_ASSERT_RD_MSR_FN(IntelCpuId1FeatureMaskEcdx);
5949	CPUM_ASSERT_RD_MSR_FN(IntelCpuId1FeatureMaskEax);
5950	CPUM_ASSERT_RD_MSR_FN(IntelCpuId80000001FeatureMaskEcdx);
5951	CPUM_ASSERT_RD_MSR_FN(IntelI7SandyAesNiCtl);
5952	CPUM_ASSERT_RD_MSR_FN(IntelI7TurboRatioLimit);
5953	CPUM_ASSERT_RD_MSR_FN(IntelI7LbrSelect);
5954	CPUM_ASSERT_RD_MSR_FN(IntelI7SandyErrorControl);
5955	CPUM_ASSERT_RD_MSR_FN(IntelI7VirtualLegacyWireCap);
5956	CPUM_ASSERT_RD_MSR_FN(IntelI7PowerCtl);
5957	CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPebsNumAlt);
5958	CPUM_ASSERT_RD_MSR_FN(IntelI7PebsLdLat);
5959	CPUM_ASSERT_RD_MSR_FN(IntelI7PkgCnResidencyN);
5960	CPUM_ASSERT_RD_MSR_FN(IntelI7CoreCnResidencyN);
5961	CPUM_ASSERT_RD_MSR_FN(IntelI7SandyVrCurrentConfig);
5962	CPUM_ASSERT_RD_MSR_FN(IntelI7SandyVrMiscConfig);
5963	CPUM_ASSERT_RD_MSR_FN(IntelI7SandyRaplPowerUnit);
5964	CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPkgCnIrtlN);
5965	CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPkgC2Residency);
5966	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPowerLimit);
5967	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgEnergyStatus);
5968	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPerfStatus);
5969	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPowerInfo);
5970	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPowerLimit);
5971	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramEnergyStatus);
5972	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPerfStatus);
5973	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPowerInfo);
5974	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0PowerLimit);
5975	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0EnergyStatus);
5976	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0Policy);
5977	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0PerfStatus);
5978	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1PowerLimit);
5979	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1EnergyStatus);
5980	CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1Policy);
5981	CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpNominal);
5982	CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpLevel1);
5983	CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpLevel2);
5984	CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpControl);
5985	CPUM_ASSERT_RD_MSR_FN(IntelI7IvyTurboActivationRatio);
5986	CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalCtrl);
5987	CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalStatus);
5988	CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalOvfCtrl);
5989	CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfFixedCtrCtrl);
5990	CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfFixedCtr);
5991	CPUM_ASSERT_RD_MSR_FN(IntelI7UncCBoxConfig);
5992	CPUM_ASSERT_RD_MSR_FN(IntelI7UncArbPerfCtrN);
5993	CPUM_ASSERT_RD_MSR_FN(IntelI7UncArbPerfEvtSelN);
5994	CPUM_ASSERT_RD_MSR_FN(IntelI7SmiCount);
5995	CPUM_ASSERT_RD_MSR_FN(IntelCore2EmttmCrTablesN);
5996	CPUM_ASSERT_RD_MSR_FN(IntelCore2SmmCStMiscInfo);
5997	CPUM_ASSERT_RD_MSR_FN(IntelCore1ExtConfig);
5998	CPUM_ASSERT_RD_MSR_FN(IntelCore1DtsCalControl);
5999	CPUM_ASSERT_RD_MSR_FN(IntelCore2PeciControl);
6000	CPUM_ASSERT_RD_MSR_FN(IntelAtSilvCoreC1Recidency);
6001
6002	CPUM_ASSERT_RD_MSR_FN(P6LastBranchFromIp);
6003	CPUM_ASSERT_RD_MSR_FN(P6LastBranchToIp);
6004	CPUM_ASSERT_RD_MSR_FN(P6LastIntFromIp);
6005	CPUM_ASSERT_RD_MSR_FN(P6LastIntToIp);
6006
6007	CPUM_ASSERT_RD_MSR_FN(AmdFam15hTscRate);
6008	CPUM_ASSERT_RD_MSR_FN(AmdFam15hLwpCfg);
6009	CPUM_ASSERT_RD_MSR_FN(AmdFam15hLwpCbAddr);
6010	CPUM_ASSERT_RD_MSR_FN(AmdFam10hMc4MiscN);
6011	CPUM_ASSERT_RD_MSR_FN(AmdK8PerfCtlN);
6012	CPUM_ASSERT_RD_MSR_FN(AmdK8PerfCtrN);
6013	CPUM_ASSERT_RD_MSR_FN(AmdK8SysCfg);
6014	CPUM_ASSERT_RD_MSR_FN(AmdK8HwCr);
6015	CPUM_ASSERT_RD_MSR_FN(AmdK8IorrBaseN);
6016	CPUM_ASSERT_RD_MSR_FN(AmdK8IorrMaskN);
6017	CPUM_ASSERT_RD_MSR_FN(AmdK8TopOfMemN);
6018	CPUM_ASSERT_RD_MSR_FN(AmdK8NbCfg1);
6019	CPUM_ASSERT_RD_MSR_FN(AmdK8McXcptRedir);
6020	CPUM_ASSERT_RD_MSR_FN(AmdK8CpuNameN);
6021	CPUM_ASSERT_RD_MSR_FN(AmdK8HwThermalCtrl);
6022	CPUM_ASSERT_RD_MSR_FN(AmdK8SwThermalCtrl);
6023	CPUM_ASSERT_RD_MSR_FN(AmdK8FidVidControl);
6024	CPUM_ASSERT_RD_MSR_FN(AmdK8FidVidStatus);
6025	CPUM_ASSERT_RD_MSR_FN(AmdK8McCtlMaskN);
6026	CPUM_ASSERT_RD_MSR_FN(AmdK8SmiOnIoTrapN);
6027	CPUM_ASSERT_RD_MSR_FN(AmdK8SmiOnIoTrapCtlSts);
6028	CPUM_ASSERT_RD_MSR_FN(AmdK8IntPendingMessage);
6029	CPUM_ASSERT_RD_MSR_FN(AmdK8SmiTriggerIoCycle);
6030	CPUM_ASSERT_RD_MSR_FN(AmdFam10hMmioCfgBaseAddr);
6031	CPUM_ASSERT_RD_MSR_FN(AmdFam10hTrapCtlMaybe);
6032	CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateCurLimit);
6033	CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateControl);
6034	CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateStatus);
6035	CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateN);
6036	CPUM_ASSERT_RD_MSR_FN(AmdFam10hCofVidControl);
6037	CPUM_ASSERT_RD_MSR_FN(AmdFam10hCofVidStatus);
6038	CPUM_ASSERT_RD_MSR_FN(AmdFam10hCStateIoBaseAddr);
6039	CPUM_ASSERT_RD_MSR_FN(AmdFam10hCpuWatchdogTimer);
6040	CPUM_ASSERT_RD_MSR_FN(AmdK8SmmBase);
6041	CPUM_ASSERT_RD_MSR_FN(AmdK8SmmAddr);
6042	CPUM_ASSERT_RD_MSR_FN(AmdK8SmmMask);
6043	CPUM_ASSERT_RD_MSR_FN(AmdK8VmCr);
6044	CPUM_ASSERT_RD_MSR_FN(AmdK8IgnNe);
6045	CPUM_ASSERT_RD_MSR_FN(AmdK8SmmCtl);
6046	CPUM_ASSERT_RD_MSR_FN(AmdK8VmHSavePa);
6047	CPUM_ASSERT_RD_MSR_FN(AmdFam10hVmLockKey);
6048	CPUM_ASSERT_RD_MSR_FN(AmdFam10hSmmLockKey);
6049	CPUM_ASSERT_RD_MSR_FN(AmdFam10hLocalSmiStatus);
6050	CPUM_ASSERT_RD_MSR_FN(AmdFam10hOsVisWrkIdLength);
6051	CPUM_ASSERT_RD_MSR_FN(AmdFam10hOsVisWrkStatus);
6052	CPUM_ASSERT_RD_MSR_FN(AmdFam16hL2IPerfCtlN);
6053	CPUM_ASSERT_RD_MSR_FN(AmdFam16hL2IPerfCtrN);
6054	CPUM_ASSERT_RD_MSR_FN(AmdFam15hNorthbridgePerfCtlN);
6055	CPUM_ASSERT_RD_MSR_FN(AmdFam15hNorthbridgePerfCtrN);
6056	CPUM_ASSERT_RD_MSR_FN(AmdK7MicrocodeCtl);
6057	CPUM_ASSERT_RD_MSR_FN(AmdK7ClusterIdMaybe);
6058	CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd07hEbax);
6059	CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd06hEcx);
6060	CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd01hEdcx);
6061	CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlExt01hEdcx);
6062	CPUM_ASSERT_RD_MSR_FN(AmdK8PatchLevel);
6063	CPUM_ASSERT_RD_MSR_FN(AmdK7DebugStatusMaybe);
6064	CPUM_ASSERT_RD_MSR_FN(AmdK7BHTraceBaseMaybe);
6065	CPUM_ASSERT_RD_MSR_FN(AmdK7BHTracePtrMaybe);
6066	CPUM_ASSERT_RD_MSR_FN(AmdK7BHTraceLimitMaybe);
6067	CPUM_ASSERT_RD_MSR_FN(AmdK7HardwareDebugToolCfgMaybe);
6068	CPUM_ASSERT_RD_MSR_FN(AmdK7FastFlushCountMaybe);
6069	CPUM_ASSERT_RD_MSR_FN(AmdK7NodeId);
6070	CPUM_ASSERT_RD_MSR_FN(AmdK7DrXAddrMaskN);
6071	CPUM_ASSERT_RD_MSR_FN(AmdK7Dr0DataMatchMaybe);
6072	CPUM_ASSERT_RD_MSR_FN(AmdK7Dr0DataMaskMaybe);
6073	CPUM_ASSERT_RD_MSR_FN(AmdK7LoadStoreCfg);
6074	CPUM_ASSERT_RD_MSR_FN(AmdK7InstrCacheCfg);
6075	CPUM_ASSERT_RD_MSR_FN(AmdK7DataCacheCfg);
6076	CPUM_ASSERT_RD_MSR_FN(AmdK7BusUnitCfg);
6077	CPUM_ASSERT_RD_MSR_FN(AmdK7DebugCtl2Maybe);
6078	CPUM_ASSERT_RD_MSR_FN(AmdFam15hFpuCfg);
6079	CPUM_ASSERT_RD_MSR_FN(AmdFam15hDecoderCfg);
6080	CPUM_ASSERT_RD_MSR_FN(AmdFam10hBusUnitCfg2);
6081	CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg);
6082	CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg2);
6083	CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg3);
6084	CPUM_ASSERT_RD_MSR_FN(AmdFam15hExecUnitCfg);
6085	CPUM_ASSERT_RD_MSR_FN(AmdFam15hLoadStoreCfg2);
6086	CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchCtl);
6087	CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchLinAddr);
6088	CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchPhysAddr);
6089	CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpExecCtl);
6090	CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpRip);
6091	CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData);
6092	CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData2);
6093	CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData3);
6094	CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsDcLinAddr);
6095	CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsDcPhysAddr);
6096	CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsCtl);
6097	CPUM_ASSERT_RD_MSR_FN(AmdFam14hIbsBrTarget);
6098
6099	CPUM_ASSERT_RD_MSR_FN(Gim)
6100
6101	AssertReturn(g_aCpumWrMsrFns[kCpumMsrWrFn_Invalid] == NULL, VERR_CPUM_IPE_2);
6102	CPUM_ASSERT_WR_MSR_FN(Ia32P5McAddr);
6103	CPUM_ASSERT_WR_MSR_FN(Ia32P5McType);
6104	CPUM_ASSERT_WR_MSR_FN(Ia32TimestampCounter);
6105	CPUM_ASSERT_WR_MSR_FN(Ia32ApicBase);
6106	CPUM_ASSERT_WR_MSR_FN(Ia32FeatureControl);
6107	CPUM_ASSERT_WR_MSR_FN(Ia32BiosSignId);
6108	CPUM_ASSERT_WR_MSR_FN(Ia32BiosUpdateTrigger);
6109	CPUM_ASSERT_WR_MSR_FN(Ia32SmmMonitorCtl);
6110	CPUM_ASSERT_WR_MSR_FN(Ia32PmcN);
6111	CPUM_ASSERT_WR_MSR_FN(Ia32MonitorFilterLineSize);
6112	CPUM_ASSERT_WR_MSR_FN(Ia32MPerf);
6113	CPUM_ASSERT_WR_MSR_FN(Ia32APerf);
6114	CPUM_ASSERT_WR_MSR_FN(Ia32MtrrPhysBaseN);
6115	CPUM_ASSERT_WR_MSR_FN(Ia32MtrrPhysMaskN);
6116	CPUM_ASSERT_WR_MSR_FN(Ia32MtrrFixed);
6117	CPUM_ASSERT_WR_MSR_FN(Ia32MtrrDefType);
6118	CPUM_ASSERT_WR_MSR_FN(Ia32Pat);
6119	CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterCs);
6120	CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterEsp);
6121	CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterEip);
6122	CPUM_ASSERT_WR_MSR_FN(Ia32McgStatus);
6123	CPUM_ASSERT_WR_MSR_FN(Ia32McgCtl);
6124	CPUM_ASSERT_WR_MSR_FN(Ia32DebugCtl);
6125	CPUM_ASSERT_WR_MSR_FN(Ia32SmrrPhysBase);
6126	CPUM_ASSERT_WR_MSR_FN(Ia32SmrrPhysMask);
6127	CPUM_ASSERT_WR_MSR_FN(Ia32PlatformDcaCap);
6128	CPUM_ASSERT_WR_MSR_FN(Ia32Dca0Cap);
6129	CPUM_ASSERT_WR_MSR_FN(Ia32PerfEvtSelN);
6130	CPUM_ASSERT_WR_MSR_FN(Ia32PerfStatus);
6131	CPUM_ASSERT_WR_MSR_FN(Ia32PerfCtl);
6132	CPUM_ASSERT_WR_MSR_FN(Ia32FixedCtrN);
6133	CPUM_ASSERT_WR_MSR_FN(Ia32PerfCapabilities);
6134	CPUM_ASSERT_WR_MSR_FN(Ia32FixedCtrCtrl);
6135	CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalStatus);
6136	CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalCtrl);
6137	CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalOvfCtrl);
6138	CPUM_ASSERT_WR_MSR_FN(Ia32PebsEnable);
6139	CPUM_ASSERT_WR_MSR_FN(Ia32ClockModulation);
6140	CPUM_ASSERT_WR_MSR_FN(Ia32ThermInterrupt);
6141	CPUM_ASSERT_WR_MSR_FN(Ia32ThermStatus);
6142	CPUM_ASSERT_WR_MSR_FN(Ia32MiscEnable);
6143	CPUM_ASSERT_WR_MSR_FN(Ia32McCtlStatusAddrMiscN);
6144	CPUM_ASSERT_WR_MSR_FN(Ia32McNCtl2);
6145	CPUM_ASSERT_WR_MSR_FN(Ia32DsArea);
6146	CPUM_ASSERT_WR_MSR_FN(Ia32TscDeadline);
6147	CPUM_ASSERT_WR_MSR_FN(Ia32X2ApicN);
6148	CPUM_ASSERT_WR_MSR_FN(Ia32DebugInterface);
6149	CPUM_ASSERT_WR_MSR_FN(Ia32SpecCtrl);
6150	CPUM_ASSERT_WR_MSR_FN(Ia32PredCmd);
6151
6152	CPUM_ASSERT_WR_MSR_FN(Amd64Efer);
6153	CPUM_ASSERT_WR_MSR_FN(Amd64SyscallTarget);
6154	CPUM_ASSERT_WR_MSR_FN(Amd64LongSyscallTarget);
6155	CPUM_ASSERT_WR_MSR_FN(Amd64CompSyscallTarget);
6156	CPUM_ASSERT_WR_MSR_FN(Amd64SyscallFlagMask);
6157	CPUM_ASSERT_WR_MSR_FN(Amd64FsBase);
6158	CPUM_ASSERT_WR_MSR_FN(Amd64GsBase);
6159	CPUM_ASSERT_WR_MSR_FN(Amd64KernelGsBase);
6160	CPUM_ASSERT_WR_MSR_FN(Amd64TscAux);
6161
6162	CPUM_ASSERT_WR_MSR_FN(IntelEblCrPowerOn);
6163	CPUM_ASSERT_WR_MSR_FN(IntelP4EbcHardPowerOn);
6164	CPUM_ASSERT_WR_MSR_FN(IntelP4EbcSoftPowerOn);
6165	CPUM_ASSERT_WR_MSR_FN(IntelP4EbcFrequencyId);
6166	CPUM_ASSERT_WR_MSR_FN(IntelFlexRatio);
6167	CPUM_ASSERT_WR_MSR_FN(IntelPkgCStConfigControl);
6168	CPUM_ASSERT_WR_MSR_FN(IntelPmgIoCaptureBase);
6169	CPUM_ASSERT_WR_MSR_FN(IntelLastBranchFromToN);
6170	CPUM_ASSERT_WR_MSR_FN(IntelLastBranchFromN);
6171	CPUM_ASSERT_WR_MSR_FN(IntelLastBranchToN);
6172	CPUM_ASSERT_WR_MSR_FN(IntelLastBranchTos);
6173	CPUM_ASSERT_WR_MSR_FN(IntelBblCrCtl);
6174	CPUM_ASSERT_WR_MSR_FN(IntelBblCrCtl3);
6175	CPUM_ASSERT_WR_MSR_FN(IntelI7TemperatureTarget);
6176	CPUM_ASSERT_WR_MSR_FN(IntelI7MsrOffCoreResponseN);
6177	CPUM_ASSERT_WR_MSR_FN(IntelI7MiscPwrMgmt);
6178	CPUM_ASSERT_WR_MSR_FN(IntelP6CrN);
6179	CPUM_ASSERT_WR_MSR_FN(IntelCpuId1FeatureMaskEcdx);
6180	CPUM_ASSERT_WR_MSR_FN(IntelCpuId1FeatureMaskEax);
6181	CPUM_ASSERT_WR_MSR_FN(IntelCpuId80000001FeatureMaskEcdx);
6182	CPUM_ASSERT_WR_MSR_FN(IntelI7SandyAesNiCtl);
6183	CPUM_ASSERT_WR_MSR_FN(IntelI7TurboRatioLimit);
6184	CPUM_ASSERT_WR_MSR_FN(IntelI7LbrSelect);
6185	CPUM_ASSERT_WR_MSR_FN(IntelI7SandyErrorControl);
6186	CPUM_ASSERT_WR_MSR_FN(IntelI7PowerCtl);
6187	CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPebsNumAlt);
6188	CPUM_ASSERT_WR_MSR_FN(IntelI7PebsLdLat);
6189	CPUM_ASSERT_WR_MSR_FN(IntelI7SandyVrCurrentConfig);
6190	CPUM_ASSERT_WR_MSR_FN(IntelI7SandyVrMiscConfig);
6191	CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPkgCnIrtlN);
6192	CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPkgC2Residency);
6193	CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPkgPowerLimit);
6194	CPUM_ASSERT_WR_MSR_FN(IntelI7RaplDramPowerLimit);
6195	CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp0PowerLimit);
6196	CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp0Policy);
6197	CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp1PowerLimit);
6198	CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp1Policy);
6199	CPUM_ASSERT_WR_MSR_FN(IntelI7IvyConfigTdpControl);
6200	CPUM_ASSERT_WR_MSR_FN(IntelI7IvyTurboActivationRatio);
6201	CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalCtrl);
6202	CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalStatus);
6203	CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalOvfCtrl);
6204	CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfFixedCtrCtrl);
6205	CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfFixedCtr);
6206	CPUM_ASSERT_WR_MSR_FN(IntelI7UncArbPerfCtrN);
6207	CPUM_ASSERT_WR_MSR_FN(IntelI7UncArbPerfEvtSelN);
6208	CPUM_ASSERT_WR_MSR_FN(IntelCore2EmttmCrTablesN);
6209	CPUM_ASSERT_WR_MSR_FN(IntelCore2SmmCStMiscInfo);
6210	CPUM_ASSERT_WR_MSR_FN(IntelCore1ExtConfig);
6211	CPUM_ASSERT_WR_MSR_FN(IntelCore1DtsCalControl);
6212	CPUM_ASSERT_WR_MSR_FN(IntelCore2PeciControl);
6213
6214	CPUM_ASSERT_WR_MSR_FN(P6LastIntFromIp);
6215	CPUM_ASSERT_WR_MSR_FN(P6LastIntToIp);
6216
6217	CPUM_ASSERT_WR_MSR_FN(AmdFam15hTscRate);
6218	CPUM_ASSERT_WR_MSR_FN(AmdFam15hLwpCfg);
6219	CPUM_ASSERT_WR_MSR_FN(AmdFam15hLwpCbAddr);
6220	CPUM_ASSERT_WR_MSR_FN(AmdFam10hMc4MiscN);
6221	CPUM_ASSERT_WR_MSR_FN(AmdK8PerfCtlN);
6222	CPUM_ASSERT_WR_MSR_FN(AmdK8PerfCtrN);
6223	CPUM_ASSERT_WR_MSR_FN(AmdK8SysCfg);
6224	CPUM_ASSERT_WR_MSR_FN(AmdK8HwCr);
6225	CPUM_ASSERT_WR_MSR_FN(AmdK8IorrBaseN);
6226	CPUM_ASSERT_WR_MSR_FN(AmdK8IorrMaskN);
6227	CPUM_ASSERT_WR_MSR_FN(AmdK8TopOfMemN);
6228	CPUM_ASSERT_WR_MSR_FN(AmdK8NbCfg1);
6229	CPUM_ASSERT_WR_MSR_FN(AmdK8McXcptRedir);
6230	CPUM_ASSERT_WR_MSR_FN(AmdK8CpuNameN);
6231	CPUM_ASSERT_WR_MSR_FN(AmdK8HwThermalCtrl);
6232	CPUM_ASSERT_WR_MSR_FN(AmdK8SwThermalCtrl);
6233	CPUM_ASSERT_WR_MSR_FN(AmdK8FidVidControl);
6234	CPUM_ASSERT_WR_MSR_FN(AmdK8McCtlMaskN);
6235	CPUM_ASSERT_WR_MSR_FN(AmdK8SmiOnIoTrapN);
6236	CPUM_ASSERT_WR_MSR_FN(AmdK8SmiOnIoTrapCtlSts);
6237	CPUM_ASSERT_WR_MSR_FN(AmdK8IntPendingMessage);
6238	CPUM_ASSERT_WR_MSR_FN(AmdK8SmiTriggerIoCycle);
6239	CPUM_ASSERT_WR_MSR_FN(AmdFam10hMmioCfgBaseAddr);
6240	CPUM_ASSERT_WR_MSR_FN(AmdFam10hTrapCtlMaybe);
6241	CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateControl);
6242	CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateStatus);
6243	CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateN);
6244	CPUM_ASSERT_WR_MSR_FN(AmdFam10hCofVidControl);
6245	CPUM_ASSERT_WR_MSR_FN(AmdFam10hCofVidStatus);
6246	CPUM_ASSERT_WR_MSR_FN(AmdFam10hCStateIoBaseAddr);
6247	CPUM_ASSERT_WR_MSR_FN(AmdFam10hCpuWatchdogTimer);
6248	CPUM_ASSERT_WR_MSR_FN(AmdK8SmmBase);
6249	CPUM_ASSERT_WR_MSR_FN(AmdK8SmmAddr);
6250	CPUM_ASSERT_WR_MSR_FN(AmdK8SmmMask);
6251	CPUM_ASSERT_WR_MSR_FN(AmdK8VmCr);
6252	CPUM_ASSERT_WR_MSR_FN(AmdK8IgnNe);
6253	CPUM_ASSERT_WR_MSR_FN(AmdK8SmmCtl);
6254	CPUM_ASSERT_WR_MSR_FN(AmdK8VmHSavePa);
6255	CPUM_ASSERT_WR_MSR_FN(AmdFam10hVmLockKey);
6256	CPUM_ASSERT_WR_MSR_FN(AmdFam10hSmmLockKey);
6257	CPUM_ASSERT_WR_MSR_FN(AmdFam10hLocalSmiStatus);
6258	CPUM_ASSERT_WR_MSR_FN(AmdFam10hOsVisWrkIdLength);
6259	CPUM_ASSERT_WR_MSR_FN(AmdFam10hOsVisWrkStatus);
6260	CPUM_ASSERT_WR_MSR_FN(AmdFam16hL2IPerfCtlN);
6261	CPUM_ASSERT_WR_MSR_FN(AmdFam16hL2IPerfCtrN);
6262	CPUM_ASSERT_WR_MSR_FN(AmdFam15hNorthbridgePerfCtlN);
6263	CPUM_ASSERT_WR_MSR_FN(AmdFam15hNorthbridgePerfCtrN);
6264	CPUM_ASSERT_WR_MSR_FN(AmdK7MicrocodeCtl);
6265	CPUM_ASSERT_WR_MSR_FN(AmdK7ClusterIdMaybe);
6266	CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd07hEbax);
6267	CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd06hEcx);
6268	CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd01hEdcx);
6269	CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlExt01hEdcx);
6270	CPUM_ASSERT_WR_MSR_FN(AmdK8PatchLoader);
6271	CPUM_ASSERT_WR_MSR_FN(AmdK7DebugStatusMaybe);
6272	CPUM_ASSERT_WR_MSR_FN(AmdK7BHTraceBaseMaybe);
6273	CPUM_ASSERT_WR_MSR_FN(AmdK7BHTracePtrMaybe);
6274	CPUM_ASSERT_WR_MSR_FN(AmdK7BHTraceLimitMaybe);
6275	CPUM_ASSERT_WR_MSR_FN(AmdK7HardwareDebugToolCfgMaybe);
6276	CPUM_ASSERT_WR_MSR_FN(AmdK7FastFlushCountMaybe);
6277	CPUM_ASSERT_WR_MSR_FN(AmdK7NodeId);
6278	CPUM_ASSERT_WR_MSR_FN(AmdK7DrXAddrMaskN);
6279	CPUM_ASSERT_WR_MSR_FN(AmdK7Dr0DataMatchMaybe);
6280	CPUM_ASSERT_WR_MSR_FN(AmdK7Dr0DataMaskMaybe);
6281	CPUM_ASSERT_WR_MSR_FN(AmdK7LoadStoreCfg);
6282	CPUM_ASSERT_WR_MSR_FN(AmdK7InstrCacheCfg);
6283	CPUM_ASSERT_WR_MSR_FN(AmdK7DataCacheCfg);
6284	CPUM_ASSERT_WR_MSR_FN(AmdK7BusUnitCfg);
6285	CPUM_ASSERT_WR_MSR_FN(AmdK7DebugCtl2Maybe);
6286	CPUM_ASSERT_WR_MSR_FN(AmdFam15hFpuCfg);
6287	CPUM_ASSERT_WR_MSR_FN(AmdFam15hDecoderCfg);
6288	CPUM_ASSERT_WR_MSR_FN(AmdFam10hBusUnitCfg2);
6289	CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg);
6290	CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg2);
6291	CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg3);
6292	CPUM_ASSERT_WR_MSR_FN(AmdFam15hExecUnitCfg);
6293	CPUM_ASSERT_WR_MSR_FN(AmdFam15hLoadStoreCfg2);
6294	CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchCtl);
6295	CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchLinAddr);
6296	CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchPhysAddr);
6297	CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpExecCtl);
6298	CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpRip);
6299	CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData);
6300	CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData2);
6301	CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData3);
6302	CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsDcLinAddr);
6303	CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsDcPhysAddr);
6304	CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsCtl);
6305	CPUM_ASSERT_WR_MSR_FN(AmdFam14hIbsBrTarget);
6306
6307	CPUM_ASSERT_WR_MSR_FN(Gim);
6308
6309	return VINF_SUCCESS;
6310	}
6311	#endif /* VBOX_STRICT && IN_RING3 */
6312
6313
6314	/**
6315	* Gets the scalable bus frequency.
6316	*
6317	* The bus frequency is used as a base in several MSRs that gives the CPU and
6318	* other frequency ratios.
6319	*
6320	* @returns Scalable bus frequency in Hz. Will not return CPUM_SBUSFREQ_UNKNOWN.
6321	* @param pVM The cross context VM structure.
6322	*/
6323	VMMDECL(uint64_t) CPUMGetGuestScalableBusFrequency(PVM pVM)
6324	{
6325	uint64_t uFreq = pVM->cpum.s.GuestInfo.uScalableBusFreq;
6326	if (uFreq == CPUM_SBUSFREQ_UNKNOWN)
6327	uFreq = CPUM_SBUSFREQ_100MHZ;
6328	return uFreq;
6329	}
6330
6331
6332	/**
6333	* Sets the guest EFER MSR without performing any additional checks.
6334	*
6335	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
6336	* @param uOldEfer The previous EFER MSR value.
6337	* @param uValidEfer The new, validated EFER MSR value.
6338	*
6339	* @remarks One would normally call CPUMQueryValidatedGuestEfer before calling this
6340	* function to change the EFER in order to perform an EFER transition.
6341	*/
6342	VMMDECL(void) CPUMSetGuestMsrEferNoCheck(PVMCPU pVCpu, uint64_t uOldEfer, uint64_t uValidEfer)
6343	{
6344	pVCpu->cpum.s.Guest.msrEFER = uValidEfer;
6345
6346	/* AMD64 Architecture Programmer's Manual: 15.15 TLB Control; flush the TLB
6347	if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
6348	if ( (uOldEfer & (MSR_K6_EFER_NXE \| MSR_K6_EFER_LME \| MSR_K6_EFER_LMA))
6349	!= (pVCpu->cpum.s.Guest.msrEFER & (MSR_K6_EFER_NXE \| MSR_K6_EFER_LME \| MSR_K6_EFER_LMA)))
6350	{
6351	/// @todo PGMFlushTLB(pVCpu, cr3, true /fGlobal/);
6352	HMFlushTLB(pVCpu);
6353
6354	/* Notify PGM about NXE changes. */
6355	if ( (uOldEfer & MSR_K6_EFER_NXE)
6356	!= (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE))
6357	PGMNotifyNxeChanged(pVCpu, !(uOldEfer & MSR_K6_EFER_NXE));
6358	}
6359	}
6360
6361
6362	/**
6363	* Checks if a guest PAT MSR write is valid.
6364	*
6365	* @returns @c true if the PAT bit combination is valid, @c false otherwise.
6366	* @param uValue The PAT MSR value.
6367	*/
6368	VMMDECL(bool) CPUMIsPatMsrValid(uint64_t uValue)
6369	{
6370	for (uint32_t cShift = 0; cShift < 63; cShift += 8)
6371	{
6372	/* Check all eight bits because the top 5 bits of each byte are reserved. */
6373	uint8_t uType = (uint8_t)(uValue >> cShift);
6374	if ((uType >= 8) \|\| (uType == 2) \|\| (uType == 3))
6375	{
6376	Log(("CPUM: Invalid PAT type at %u:%u in IA32_PAT: %#llx (%#llx)\n", cShift + 7, cShift, uValue, uType));
6377	return false;
6378	}
6379	}
6380	return true;
6381	}
6382
6383
6384	/**
6385	* Validates an EFER MSR write.
6386	*
6387	* @returns VBox status code.
6388	* @param pVM The cross context VM structure.
6389	* @param uCr0 The CR0 of the CPU corresponding to the EFER MSR.
6390	* @param uOldEfer Value of the previous EFER MSR on the CPU if any.
6391	* @param uNewEfer The new EFER MSR value being written.
6392	* @param puValidEfer Where to store the validated EFER (only updated if
6393	* this function returns VINF_SUCCESS).
6394	*/
6395	VMMDECL(int) CPUMQueryValidatedGuestEfer(PVM pVM, uint64_t uCr0, uint64_t uOldEfer, uint64_t uNewEfer, uint64_t *puValidEfer)
6396	{
6397	uint32_t const fExtFeatures = pVM->cpum.s.aGuestCpuIdPatmExt[0].uEax >= 0x80000001
6398	? pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx
6399	: 0;
6400	uint64_t fMask = 0;
6401	uint64_t const fIgnoreMask = MSR_K6_EFER_LMA;
6402
6403	/* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
6404	if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_NX)
6405	fMask \|= MSR_K6_EFER_NXE;
6406	if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
6407	fMask \|= MSR_K6_EFER_LME;
6408	if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
6409	fMask \|= MSR_K6_EFER_SCE;
6410	if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
6411	fMask \|= MSR_K6_EFER_FFXSR;
6412	if (pVM->cpum.s.GuestFeatures.fSvm)
6413	fMask \|= MSR_K6_EFER_SVME;
6414
6415	/* #GP(0) If anything outside the allowed bits is set. */
6416	if (uNewEfer & ~(fIgnoreMask \| fMask))
6417	{
6418	Log(("CPUM: Settings disallowed EFER bit. uNewEfer=%#RX64 fAllowed=%#RX64 -> #GP(0)\n", uNewEfer, fMask));
6419	return VERR_CPUM_RAISE_GP_0;
6420	}
6421
6422	/* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if
6423	paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
6424	if ( (uOldEfer & MSR_K6_EFER_LME) != (uNewEfer & fMask & MSR_K6_EFER_LME)
6425	&& (uCr0 & X86_CR0_PG))
6426	{
6427	Log(("CPUM: Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
6428	return VERR_CPUM_RAISE_GP_0;
6429	}
6430
6431	/* There are a few more: e.g. MSR_K6_EFER_LMSLE */
6432	AssertMsg(!(uNewEfer & ~( MSR_K6_EFER_NXE
6433	\| MSR_K6_EFER_LME
6434	\| MSR_K6_EFER_LMA /* ignored anyway */
6435	\| MSR_K6_EFER_SCE
6436	\| MSR_K6_EFER_FFXSR
6437	\| MSR_K6_EFER_SVME)),
6438	("Unexpected value %#RX64\n", uNewEfer));
6439
6440	*puValidEfer = (uOldEfer & ~fMask) \| (uNewEfer & fMask);
6441	return VINF_SUCCESS;
6442	}
6443
6444
6445	/**
6446	* Fast way for HM to access the MSR_K8_TSC_AUX register.
6447	*
6448	* @returns The register value.
6449	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
6450	* @thread EMT(pVCpu)
6451	*/
6452	VMM_INT_DECL(uint64_t) CPUMGetGuestTscAux(PVMCPU pVCpu)
6453	{
6454	Assert(!(pVCpu->cpum.s.Guest.fExtrn & CPUMCTX_EXTRN_TSC_AUX));
6455	return pVCpu->cpum.s.GuestMsrs.msr.TscAux;
6456	}
6457
6458
6459	/**
6460	* Fast way for HM to access the MSR_K8_TSC_AUX register.
6461	*
6462	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
6463	* @param uValue The new value.
6464	* @thread EMT(pVCpu)
6465	*/
6466	VMM_INT_DECL(void) CPUMSetGuestTscAux(PVMCPU pVCpu, uint64_t uValue)
6467	{
6468	pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_TSC_AUX;
6469	pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
6470	}
6471
6472
6473	/**
6474	* Fast way for HM to access the IA32_SPEC_CTRL register.
6475	*
6476	* @returns The register value.
6477	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
6478	* @thread EMT(pVCpu)
6479	*/
6480	VMM_INT_DECL(uint64_t) CPUMGetGuestSpecCtrl(PVMCPU pVCpu)
6481	{
6482	return pVCpu->cpum.s.GuestMsrs.msr.SpecCtrl;
6483	}
6484
6485
6486	/**
6487	* Fast way for HM to access the IA32_SPEC_CTRL register.
6488	*
6489	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
6490	* @param uValue The new value.
6491	* @thread EMT(pVCpu)
6492	*/
6493	VMM_INT_DECL(void) CPUMSetGuestSpecCtrl(PVMCPU pVCpu, uint64_t uValue)
6494	{
6495	pVCpu->cpum.s.GuestMsrs.msr.SpecCtrl = uValue;
6496	}
6497

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source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllMsrs.cpp@ 73400

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