VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllMsrs.cpp@ 73992

Last change on this file since 73992 was 73870, checked in by vboxsync, 6 years ago

VMM: Nested VMX: Added VMX CPUID features for RDRAND, RDSEED and PML. Fixed incorrect VMCS field validation for guest-interrupt status.
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File size: 248.2 KB
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1/* $Id: CPUMAllMsrs.cpp 73870 2018-08-24 09:39:44Z vboxsync $ */
2/** @file
3 * CPUM - CPU MSR Registers.
4 */
5
6/*
7 * Copyright (C) 2013-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_CPUM
23#include <VBox/vmm/cpum.h>
24#include <VBox/vmm/apic.h>
25#include <VBox/vmm/hm.h>
26#include <VBox/vmm/hm_vmx.h>
27#include <VBox/vmm/tm.h>
28#include <VBox/vmm/gim.h>
29#include "CPUMInternal.h"
30#include <VBox/vmm/vm.h>
31#include <VBox/err.h>
32
33
34/*********************************************************************************************************************************
35* Defined Constants And Macros *
36*********************************************************************************************************************************/
37/**
38 * Validates the CPUMMSRRANGE::offCpumCpu value and declares a local variable
39 * pointing to it.
40 *
41 * ASSUMES sizeof(a_Type) is a power of two and that the member is aligned
42 * correctly.
43 */
44#define CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(a_pVCpu, a_pRange, a_Type, a_VarName) \
45 AssertMsgReturn( (a_pRange)->offCpumCpu >= 8 \
46 && (a_pRange)->offCpumCpu < sizeof(CPUMCPU) \
47 && !((a_pRange)->offCpumCpu & (RT_MIN(sizeof(a_Type), 8) - 1)) \
48 , ("offCpumCpu=%#x %s\n", (a_pRange)->offCpumCpu, (a_pRange)->szName), \
49 VERR_CPUM_MSR_BAD_CPUMCPU_OFFSET); \
50 a_Type *a_VarName = (a_Type *)((uintptr_t)&(a_pVCpu)->cpum.s + (a_pRange)->offCpumCpu)
51
52
53/*********************************************************************************************************************************
54* Structures and Typedefs *
55*********************************************************************************************************************************/
56
57/**
58 * Implements reading one or more MSRs.
59 *
60 * @returns VBox status code.
61 * @retval VINF_SUCCESS on success.
62 * @retval VINF_CPUM_R3_MSR_READ if the MSR read could not be serviced in the
63 * current context (raw-mode or ring-0).
64 * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR).
65 *
66 * @param pVCpu The cross context virtual CPU structure.
67 * @param idMsr The MSR we're reading.
68 * @param pRange The MSR range descriptor.
69 * @param puValue Where to return the value.
70 */
71typedef DECLCALLBACK(VBOXSTRICTRC) FNCPUMRDMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue);
72/** Pointer to a RDMSR worker for a specific MSR or range of MSRs. */
73typedef FNCPUMRDMSR *PFNCPUMRDMSR;
74
75
76/**
77 * Implements writing one or more MSRs.
78 *
79 * @retval VINF_SUCCESS on success.
80 * @retval VINF_CPUM_R3_MSR_WRITE if the MSR write could not be serviced in the
81 * current context (raw-mode or ring-0).
82 * @retval VERR_CPUM_RAISE_GP_0 on failure.
83 *
84 * @param pVCpu The cross context virtual CPU structure.
85 * @param idMsr The MSR we're writing.
86 * @param pRange The MSR range descriptor.
87 * @param uValue The value to set, ignored bits masked.
88 * @param uRawValue The raw value with the ignored bits not masked.
89 */
90typedef DECLCALLBACK(VBOXSTRICTRC) FNCPUMWRMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue);
91/** Pointer to a WRMSR worker for a specific MSR or range of MSRs. */
92typedef FNCPUMWRMSR *PFNCPUMWRMSR;
93
94
95
96/*
97 * Generic functions.
98 * Generic functions.
99 * Generic functions.
100 */
101
102
103/** @callback_method_impl{FNCPUMRDMSR} */
104static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_FixedValue(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
105{
106 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
107 *puValue = pRange->uValue;
108 return VINF_SUCCESS;
109}
110
111
112/** @callback_method_impl{FNCPUMWRMSR} */
113static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IgnoreWrite(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
114{
115 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
116 Log(("CPUM: Ignoring WRMSR %#x (%s), %#llx\n", idMsr, pRange->szName, uValue));
117 return VINF_SUCCESS;
118}
119
120
121/** @callback_method_impl{FNCPUMRDMSR} */
122static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_WriteOnly(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
123{
124 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(puValue);
125 return VERR_CPUM_RAISE_GP_0;
126}
127
128
129/** @callback_method_impl{FNCPUMWRMSR} */
130static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_ReadOnly(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
131{
132 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
133 Assert(pRange->fWrGpMask == UINT64_MAX);
134 return VERR_CPUM_RAISE_GP_0;
135}
136
137
138
139
140/*
141 * IA32
142 * IA32
143 * IA32
144 */
145
146/** @callback_method_impl{FNCPUMRDMSR} */
147static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32P5McAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
148{
149 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
150 *puValue = 0; /** @todo implement machine check injection. */
151 return VINF_SUCCESS;
152}
153
154
155/** @callback_method_impl{FNCPUMWRMSR} */
156static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32P5McAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
157{
158 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
159 /** @todo implement machine check injection. */
160 return VINF_SUCCESS;
161}
162
163
164/** @callback_method_impl{FNCPUMRDMSR} */
165static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32P5McType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
166{
167 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
168 *puValue = 0; /** @todo implement machine check injection. */
169 return VINF_SUCCESS;
170}
171
172
173/** @callback_method_impl{FNCPUMWRMSR} */
174static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32P5McType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
175{
176 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
177 /** @todo implement machine check injection. */
178 return VINF_SUCCESS;
179}
180
181
182/** @callback_method_impl{FNCPUMRDMSR} */
183static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32TimestampCounter(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
184{
185 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
186 *puValue = TMCpuTickGet(pVCpu);
187#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
188 *puValue = CPUMApplyNestedGuestTscOffset(pVCpu, *puValue);
189#endif
190 return VINF_SUCCESS;
191}
192
193
194/** @callback_method_impl{FNCPUMWRMSR} */
195static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32TimestampCounter(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
196{
197 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
198 TMCpuTickSet(pVCpu->CTX_SUFF(pVM), pVCpu, uValue);
199 return VINF_SUCCESS;
200}
201
202
203/** @callback_method_impl{FNCPUMRDMSR} */
204static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PlatformId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
205{
206 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
207 uint64_t uValue = pRange->uValue;
208 if (uValue & 0x1f00)
209 {
210 /* Max allowed bus ratio present. */
211 /** @todo Implement scaled BUS frequency. */
212 }
213
214 *puValue = uValue;
215 return VINF_SUCCESS;
216}
217
218
219/** @callback_method_impl{FNCPUMRDMSR} */
220static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ApicBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
221{
222 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
223 return APICGetBaseMsr(pVCpu, puValue);
224}
225
226
227/** @callback_method_impl{FNCPUMWRMSR} */
228static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ApicBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
229{
230 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
231 return APICSetBaseMsr(pVCpu, uValue);
232}
233
234
235/**
236 * Get fixed IA32_FEATURE_CONTROL value for NEM and cpumMsrRd_Ia32FeatureControl.
237 *
238 * @returns Fixed IA32_FEATURE_CONTROL value.
239 * @param pVCpu The cross context per CPU structure.
240 */
241VMM_INT_DECL(uint64_t) CPUMGetGuestIa32FeatureControl(PVMCPU pVCpu)
242{
243 /* Always report the MSR lock bit as set, in order to prevent guests from modifiying this MSR. */
244 uint64_t fFeatCtl = MSR_IA32_FEATURE_CONTROL_LOCK;
245
246 /* Report VMX features. */
247 if (pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fVmx)
248 fFeatCtl |= MSR_IA32_FEATURE_CONTROL_VMXON;
249
250 return fFeatCtl;
251}
252
253/** @callback_method_impl{FNCPUMRDMSR} */
254static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32FeatureControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
255{
256 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
257 *puValue = CPUMGetGuestIa32FeatureControl(pVCpu);
258 return VINF_SUCCESS;
259}
260
261
262/** @callback_method_impl{FNCPUMWRMSR} */
263static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32FeatureControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
264{
265 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
266 return VERR_CPUM_RAISE_GP_0;
267}
268
269
270/** @callback_method_impl{FNCPUMRDMSR} */
271static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32BiosSignId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
272{
273 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
274 /** @todo fake microcode update. */
275 *puValue = pRange->uValue;
276 return VINF_SUCCESS;
277}
278
279
280/** @callback_method_impl{FNCPUMWRMSR} */
281static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32BiosSignId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
282{
283 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
284 /* Normally, zero is written to Ia32BiosSignId before reading it in order
285 to select the signature instead of the BBL_CR_D3 behaviour. The GP mask
286 of the database entry should take care of most illegal writes for now, so
287 just ignore all writes atm. */
288 return VINF_SUCCESS;
289}
290
291
292/** @callback_method_impl{FNCPUMWRMSR} */
293static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32BiosUpdateTrigger(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
294{
295 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
296 /** @todo Fake bios update trigger better. The value is the address to an
297 * update package, I think. We should probably GP if it's invalid. */
298 return VINF_SUCCESS;
299}
300
301
302/**
303 * Get MSR_IA32_SMM_MONITOR_CTL value for IEM and cpumMsrRd_Ia32SmmMonitorCtl.
304 *
305 * @returns The MSR_IA32_SMM_MONITOR_CTL value.
306 * @param pVCpu The cross context per CPU structure.
307 */
308VMM_INT_DECL(uint64_t) CPUMGetGuestIa32SmmMonitorCtl(PVMCPU pVCpu)
309{
310 /* We do not support dual-monitor treatment for SMI and SMM. */
311 /** @todo SMM. */
312 RT_NOREF(pVCpu);
313 return 0;
314}
315
316
317/** @callback_method_impl{FNCPUMRDMSR} */
318static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SmmMonitorCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
319{
320 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
321 *puValue = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
322 return VINF_SUCCESS;
323}
324
325
326/** @callback_method_impl{FNCPUMWRMSR} */
327static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SmmMonitorCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
328{
329 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
330 /** @todo SMM. */
331 return VINF_SUCCESS;
332}
333
334
335/** @callback_method_impl{FNCPUMRDMSR} */
336static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PmcN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
337{
338 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
339 /** @todo check CPUID leaf 0ah. */
340 *puValue = 0;
341 return VINF_SUCCESS;
342}
343
344
345/** @callback_method_impl{FNCPUMWRMSR} */
346static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PmcN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
347{
348 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
349 /** @todo check CPUID leaf 0ah. */
350 return VINF_SUCCESS;
351}
352
353
354/** @callback_method_impl{FNCPUMRDMSR} */
355static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MonitorFilterLineSize(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
356{
357 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
358 /** @todo return 0x1000 if we try emulate mwait 100% correctly. */
359 *puValue = 0x40; /** @todo Change to CPU cache line size. */
360 return VINF_SUCCESS;
361}
362
363
364/** @callback_method_impl{FNCPUMWRMSR} */
365static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MonitorFilterLineSize(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
366{
367 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
368 /** @todo should remember writes, though it's supposedly something only a BIOS
369 * would write so, it's not extremely important. */
370 return VINF_SUCCESS;
371}
372
373/** @callback_method_impl{FNCPUMRDMSR} */
374static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MPerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
375{
376 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
377 /** @todo Read MPERF: Adjust against previously written MPERF value. Is TSC
378 * what we want? */
379 *puValue = TMCpuTickGet(pVCpu);
380#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
381 *puValue = CPUMApplyNestedGuestTscOffset(pVCpu, *puValue);
382#endif
383 return VINF_SUCCESS;
384}
385
386
387/** @callback_method_impl{FNCPUMWRMSR} */
388static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MPerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
389{
390 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
391 /** @todo Write MPERF: Calc adjustment. */
392 return VINF_SUCCESS;
393}
394
395
396/** @callback_method_impl{FNCPUMRDMSR} */
397static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32APerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
398{
399 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
400 /** @todo Read APERF: Adjust against previously written MPERF value. Is TSC
401 * what we want? */
402 *puValue = TMCpuTickGet(pVCpu);
403#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
404 *puValue = CPUMApplyNestedGuestTscOffset(pVCpu, *puValue);
405#endif
406 return VINF_SUCCESS;
407}
408
409
410/** @callback_method_impl{FNCPUMWRMSR} */
411static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32APerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
412{
413 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
414 /** @todo Write APERF: Calc adjustment. */
415 return VINF_SUCCESS;
416}
417
418
419/**
420 * Get fixed IA32_MTRR_CAP value for NEM and cpumMsrRd_Ia32MtrrCap.
421 *
422 * @returns Fixed IA32_MTRR_CAP value.
423 * @param pVCpu The cross context per CPU structure.
424 */
425VMM_INT_DECL(uint64_t) CPUMGetGuestIa32MtrrCap(PVMCPU pVCpu)
426{
427 RT_NOREF_PV(pVCpu);
428
429 /* This is currently a bit weird. :-) */
430 uint8_t const cVariableRangeRegs = 0;
431 bool const fSystemManagementRangeRegisters = false;
432 bool const fFixedRangeRegisters = false;
433 bool const fWriteCombiningType = false;
434 return cVariableRangeRegs
435 | (fFixedRangeRegisters ? RT_BIT_64(8) : 0)
436 | (fWriteCombiningType ? RT_BIT_64(10) : 0)
437 | (fSystemManagementRangeRegisters ? RT_BIT_64(11) : 0);
438}
439
440/** @callback_method_impl{FNCPUMRDMSR} */
441static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
442{
443 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
444 *puValue = CPUMGetGuestIa32MtrrCap(pVCpu);
445 return VINF_SUCCESS;
446}
447
448
449/** @callback_method_impl{FNCPUMRDMSR} */
450static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrPhysBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
451{
452 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
453 /** @todo Implement variable MTRR storage. */
454 Assert(pRange->uValue == (idMsr - 0x200) / 2);
455 *puValue = 0;
456 return VINF_SUCCESS;
457}
458
459
460/** @callback_method_impl{FNCPUMWRMSR} */
461static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrPhysBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
462{
463 /*
464 * Validate the value.
465 */
466 Assert(pRange->uValue == (idMsr - 0x200) / 2);
467 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(uRawValue); RT_NOREF_PV(pRange);
468
469 uint8_t uType = uValue & 0xff;
470 if ((uType >= 7) || (uType == 2) || (uType == 3))
471 {
472 Log(("CPUM: Invalid type set writing MTRR PhysBase MSR %#x: %#llx (%#llx)\n", idMsr, uValue, uType));
473 return VERR_CPUM_RAISE_GP_0;
474 }
475
476 uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
477 if (fInvPhysMask & uValue)
478 {
479 Log(("CPUM: Invalid physical address bits set writing MTRR PhysBase MSR %#x: %#llx (%#llx)\n",
480 idMsr, uValue, uValue & fInvPhysMask));
481 return VERR_CPUM_RAISE_GP_0;
482 }
483
484 /*
485 * Store it.
486 */
487 /** @todo Implement variable MTRR storage. */
488 return VINF_SUCCESS;
489}
490
491
492/** @callback_method_impl{FNCPUMRDMSR} */
493static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrPhysMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
494{
495 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
496 /** @todo Implement variable MTRR storage. */
497 Assert(pRange->uValue == (idMsr - 0x200) / 2);
498 *puValue = 0;
499 return VINF_SUCCESS;
500}
501
502
503/** @callback_method_impl{FNCPUMWRMSR} */
504static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrPhysMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
505{
506 /*
507 * Validate the value.
508 */
509 Assert(pRange->uValue == (idMsr - 0x200) / 2);
510 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(uRawValue); RT_NOREF_PV(pRange);
511
512 uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
513 if (fInvPhysMask & uValue)
514 {
515 Log(("CPUM: Invalid physical address bits set writing MTRR PhysMask MSR %#x: %#llx (%#llx)\n",
516 idMsr, uValue, uValue & fInvPhysMask));
517 return VERR_CPUM_RAISE_GP_0;
518 }
519
520 /*
521 * Store it.
522 */
523 /** @todo Implement variable MTRR storage. */
524 return VINF_SUCCESS;
525}
526
527
528/** @callback_method_impl{FNCPUMRDMSR} */
529static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrFixed(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
530{
531 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
532 CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(pVCpu, pRange, uint64_t, puFixedMtrr);
533 *puValue = *puFixedMtrr;
534 return VINF_SUCCESS;
535}
536
537
538/** @callback_method_impl{FNCPUMWRMSR} */
539static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrFixed(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
540{
541 CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(pVCpu, pRange, uint64_t, puFixedMtrr);
542 RT_NOREF_PV(idMsr); RT_NOREF_PV(uRawValue);
543
544 for (uint32_t cShift = 0; cShift < 63; cShift += 8)
545 {
546 uint8_t uType = (uint8_t)(uValue >> cShift);
547 if ((uType >= 7) || (uType == 2) || (uType == 3))
548 {
549 Log(("CPUM: Invalid MTRR type at %u:%u in fixed range (%#x/%s): %#llx (%#llx)\n",
550 cShift + 7, cShift, idMsr, pRange->szName, uValue, uType));
551 return VERR_CPUM_RAISE_GP_0;
552 }
553 }
554 *puFixedMtrr = uValue;
555 return VINF_SUCCESS;
556}
557
558
559/** @callback_method_impl{FNCPUMRDMSR} */
560static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrDefType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
561{
562 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
563 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType;
564 return VINF_SUCCESS;
565}
566
567
568/** @callback_method_impl{FNCPUMWRMSR} */
569static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrDefType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
570{
571 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
572
573 uint8_t uType = uValue & 0xff;
574 if ((uType >= 7) || (uType == 2) || (uType == 3))
575 {
576 Log(("CPUM: Invalid MTRR default type value on %s: %#llx (%#llx)\n", pRange->szName, uValue, uType));
577 return VERR_CPUM_RAISE_GP_0;
578 }
579
580 pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType = uValue;
581 return VINF_SUCCESS;
582}
583
584
585/** @callback_method_impl{FNCPUMRDMSR} */
586static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32Pat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
587{
588 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
589 *puValue = pVCpu->cpum.s.Guest.msrPAT;
590 return VINF_SUCCESS;
591}
592
593
594/** @callback_method_impl{FNCPUMWRMSR} */
595static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32Pat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
596{
597 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
598 if (CPUMIsPatMsrValid(uValue))
599 {
600 pVCpu->cpum.s.Guest.msrPAT = uValue;
601 return VINF_SUCCESS;
602 }
603 return VERR_CPUM_RAISE_GP_0;
604}
605
606
607/** @callback_method_impl{FNCPUMRDMSR} */
608static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SysEnterCs(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
609{
610 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
611 *puValue = pVCpu->cpum.s.Guest.SysEnter.cs;
612 return VINF_SUCCESS;
613}
614
615
616/** @callback_method_impl{FNCPUMWRMSR} */
617static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SysEnterCs(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
618{
619 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
620
621 /* Note! We used to mask this by 0xffff, but turns out real HW doesn't and
622 there are generally 32-bit working bits backing this register. */
623 pVCpu->cpum.s.Guest.SysEnter.cs = uValue;
624 return VINF_SUCCESS;
625}
626
627
628/** @callback_method_impl{FNCPUMRDMSR} */
629static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SysEnterEsp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
630{
631 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
632 *puValue = pVCpu->cpum.s.Guest.SysEnter.esp;
633 return VINF_SUCCESS;
634}
635
636
637/** @callback_method_impl{FNCPUMWRMSR} */
638static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SysEnterEsp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
639{
640 if (X86_IS_CANONICAL(uValue))
641 {
642 pVCpu->cpum.s.Guest.SysEnter.esp = uValue;
643 return VINF_SUCCESS;
644 }
645 Log(("CPUM: IA32_SYSENTER_ESP not canonical! %#llx\n", uValue));
646 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
647 return VERR_CPUM_RAISE_GP_0;
648}
649
650
651/** @callback_method_impl{FNCPUMRDMSR} */
652static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SysEnterEip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
653{
654 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
655 *puValue = pVCpu->cpum.s.Guest.SysEnter.eip;
656 return VINF_SUCCESS;
657}
658
659
660/** @callback_method_impl{FNCPUMWRMSR} */
661static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SysEnterEip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
662{
663 if (X86_IS_CANONICAL(uValue))
664 {
665 pVCpu->cpum.s.Guest.SysEnter.eip = uValue;
666 return VINF_SUCCESS;
667 }
668 LogRel(("CPUM: IA32_SYSENTER_EIP not canonical! %#llx\n", uValue));
669 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
670 return VERR_CPUM_RAISE_GP_0;
671}
672
673
674/** @callback_method_impl{FNCPUMRDMSR} */
675static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McgCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
676{
677#if 0 /** @todo implement machine checks. */
678 *puValue = pRange->uValue & (RT_BIT_64(8) | 0);
679#else
680 *puValue = 0;
681#endif
682 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
683 return VINF_SUCCESS;
684}
685
686
687/** @callback_method_impl{FNCPUMRDMSR} */
688static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McgStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
689{
690 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
691 /** @todo implement machine checks. */
692 *puValue = 0;
693 return VINF_SUCCESS;
694}
695
696
697/** @callback_method_impl{FNCPUMWRMSR} */
698static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McgStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
699{
700 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
701 /** @todo implement machine checks. */
702 return VINF_SUCCESS;
703}
704
705
706/** @callback_method_impl{FNCPUMRDMSR} */
707static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McgCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
708{
709 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
710 /** @todo implement machine checks. */
711 *puValue = 0;
712 return VINF_SUCCESS;
713}
714
715
716/** @callback_method_impl{FNCPUMWRMSR} */
717static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McgCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
718{
719 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
720 /** @todo implement machine checks. */
721 return VINF_SUCCESS;
722}
723
724
725/** @callback_method_impl{FNCPUMRDMSR} */
726static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32DebugCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
727{
728 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
729 /** @todo implement IA32_DEBUGCTL. */
730 *puValue = 0;
731 return VINF_SUCCESS;
732}
733
734
735/** @callback_method_impl{FNCPUMWRMSR} */
736static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32DebugCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
737{
738 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
739 /** @todo implement IA32_DEBUGCTL. */
740 return VINF_SUCCESS;
741}
742
743
744/** @callback_method_impl{FNCPUMRDMSR} */
745static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SmrrPhysBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
746{
747 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
748 /** @todo implement intel SMM. */
749 *puValue = 0;
750 return VINF_SUCCESS;
751}
752
753
754/** @callback_method_impl{FNCPUMWRMSR} */
755static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SmrrPhysBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
756{
757 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
758 /** @todo implement intel SMM. */
759 return VERR_CPUM_RAISE_GP_0;
760}
761
762
763/** @callback_method_impl{FNCPUMRDMSR} */
764static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SmrrPhysMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
765{
766 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
767 /** @todo implement intel SMM. */
768 *puValue = 0;
769 return VINF_SUCCESS;
770}
771
772
773/** @callback_method_impl{FNCPUMWRMSR} */
774static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SmrrPhysMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
775{
776 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
777 /** @todo implement intel SMM. */
778 return VERR_CPUM_RAISE_GP_0;
779}
780
781
782/** @callback_method_impl{FNCPUMRDMSR} */
783static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PlatformDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
784{
785 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
786 /** @todo implement intel direct cache access (DCA)?? */
787 *puValue = 0;
788 return VINF_SUCCESS;
789}
790
791
792/** @callback_method_impl{FNCPUMWRMSR} */
793static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PlatformDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
794{
795 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
796 /** @todo implement intel direct cache access (DCA)?? */
797 return VINF_SUCCESS;
798}
799
800
801/** @callback_method_impl{FNCPUMRDMSR} */
802static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32CpuDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
803{
804 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
805 /** @todo implement intel direct cache access (DCA)?? */
806 *puValue = 0;
807 return VINF_SUCCESS;
808}
809
810
811/** @callback_method_impl{FNCPUMRDMSR} */
812static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32Dca0Cap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
813{
814 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
815 /** @todo implement intel direct cache access (DCA)?? */
816 *puValue = 0;
817 return VINF_SUCCESS;
818}
819
820
821/** @callback_method_impl{FNCPUMWRMSR} */
822static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32Dca0Cap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
823{
824 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
825 /** @todo implement intel direct cache access (DCA)?? */
826 return VINF_SUCCESS;
827}
828
829
830/** @callback_method_impl{FNCPUMRDMSR} */
831static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
832{
833 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
834 /** @todo implement IA32_PERFEVTSEL0+. */
835 *puValue = 0;
836 return VINF_SUCCESS;
837}
838
839
840/** @callback_method_impl{FNCPUMWRMSR} */
841static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
842{
843 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
844 /** @todo implement IA32_PERFEVTSEL0+. */
845 return VINF_SUCCESS;
846}
847
848
849/** @callback_method_impl{FNCPUMRDMSR} */
850static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
851{
852 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
853 uint64_t uValue = pRange->uValue;
854
855 /* Always provide the max bus ratio for now. XNU expects it. */
856 uValue &= ~((UINT64_C(0x1f) << 40) | RT_BIT_64(46));
857
858 PVM pVM = pVCpu->CTX_SUFF(pVM);
859 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
860 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
861 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
862 if (uTscRatio > 0x1f)
863 uTscRatio = 0x1f;
864 uValue |= (uint64_t)uTscRatio << 40;
865
866 *puValue = uValue;
867 return VINF_SUCCESS;
868}
869
870
871/** @callback_method_impl{FNCPUMWRMSR} */
872static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
873{
874 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
875 /* Pentium4 allows writing, but all bits are ignored. */
876 return VINF_SUCCESS;
877}
878
879
880/** @callback_method_impl{FNCPUMRDMSR} */
881static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
882{
883 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
884 /** @todo implement IA32_PERFCTL. */
885 *puValue = 0;
886 return VINF_SUCCESS;
887}
888
889
890/** @callback_method_impl{FNCPUMWRMSR} */
891static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
892{
893 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
894 /** @todo implement IA32_PERFCTL. */
895 return VINF_SUCCESS;
896}
897
898
899/** @callback_method_impl{FNCPUMRDMSR} */
900static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32FixedCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
901{
902 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
903 /** @todo implement IA32_FIXED_CTRn (fixed performance counters). */
904 *puValue = 0;
905 return VINF_SUCCESS;
906}
907
908
909/** @callback_method_impl{FNCPUMWRMSR} */
910static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32FixedCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
911{
912 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
913 /** @todo implement IA32_FIXED_CTRn (fixed performance counters). */
914 return VINF_SUCCESS;
915}
916
917
918/** @callback_method_impl{FNCPUMRDMSR} */
919static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfCapabilities(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
920{
921 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
922 /** @todo implement performance counters. */
923 *puValue = 0;
924 return VINF_SUCCESS;
925}
926
927
928/** @callback_method_impl{FNCPUMWRMSR} */
929static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfCapabilities(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
930{
931 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
932 /** @todo implement performance counters. */
933 return VINF_SUCCESS;
934}
935
936
937/** @callback_method_impl{FNCPUMRDMSR} */
938static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32FixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
939{
940 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
941 /** @todo implement performance counters. */
942 *puValue = 0;
943 return VINF_SUCCESS;
944}
945
946
947/** @callback_method_impl{FNCPUMWRMSR} */
948static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32FixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
949{
950 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
951 /** @todo implement performance counters. */
952 return VINF_SUCCESS;
953}
954
955
956/** @callback_method_impl{FNCPUMRDMSR} */
957static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
958{
959 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
960 /** @todo implement performance counters. */
961 *puValue = 0;
962 return VINF_SUCCESS;
963}
964
965
966/** @callback_method_impl{FNCPUMWRMSR} */
967static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
968{
969 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
970 /** @todo implement performance counters. */
971 return VINF_SUCCESS;
972}
973
974
975/** @callback_method_impl{FNCPUMRDMSR} */
976static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
977{
978 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
979 /** @todo implement performance counters. */
980 *puValue = 0;
981 return VINF_SUCCESS;
982}
983
984
985/** @callback_method_impl{FNCPUMWRMSR} */
986static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
987{
988 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
989 /** @todo implement performance counters. */
990 return VINF_SUCCESS;
991}
992
993
994/** @callback_method_impl{FNCPUMRDMSR} */
995static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
996{
997 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
998 /** @todo implement performance counters. */
999 *puValue = 0;
1000 return VINF_SUCCESS;
1001}
1002
1003
1004/** @callback_method_impl{FNCPUMWRMSR} */
1005static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1006{
1007 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1008 /** @todo implement performance counters. */
1009 return VINF_SUCCESS;
1010}
1011
1012
1013/** @callback_method_impl{FNCPUMRDMSR} */
1014static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PebsEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1015{
1016 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1017 /** @todo implement performance counters. */
1018 *puValue = 0;
1019 return VINF_SUCCESS;
1020}
1021
1022
1023/** @callback_method_impl{FNCPUMWRMSR} */
1024static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PebsEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1025{
1026 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1027 /** @todo implement performance counters. */
1028 return VINF_SUCCESS;
1029}
1030
1031
1032/** @callback_method_impl{FNCPUMRDMSR} */
1033static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ClockModulation(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1034{
1035 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1036 /** @todo implement IA32_CLOCK_MODULATION. */
1037 *puValue = 0;
1038 return VINF_SUCCESS;
1039}
1040
1041
1042/** @callback_method_impl{FNCPUMWRMSR} */
1043static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ClockModulation(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1044{
1045 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1046 /** @todo implement IA32_CLOCK_MODULATION. */
1047 return VINF_SUCCESS;
1048}
1049
1050
1051/** @callback_method_impl{FNCPUMRDMSR} */
1052static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ThermInterrupt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1053{
1054 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1055 /** @todo implement IA32_THERM_INTERRUPT. */
1056 *puValue = 0;
1057 return VINF_SUCCESS;
1058}
1059
1060
1061/** @callback_method_impl{FNCPUMWRMSR} */
1062static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ThermInterrupt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1063{
1064 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1065 /** @todo implement IA32_THERM_STATUS. */
1066 return VINF_SUCCESS;
1067}
1068
1069
1070/** @callback_method_impl{FNCPUMRDMSR} */
1071static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ThermStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1072{
1073 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1074 /** @todo implement IA32_THERM_STATUS. */
1075 *puValue = 0;
1076 return VINF_SUCCESS;
1077}
1078
1079
1080/** @callback_method_impl{FNCPUMWRMSR} */
1081static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ThermStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1082{
1083 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1084 /** @todo implement IA32_THERM_INTERRUPT. */
1085 return VINF_SUCCESS;
1086}
1087
1088
1089/** @callback_method_impl{FNCPUMRDMSR} */
1090static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32Therm2Ctl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1091{
1092 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1093 /** @todo implement IA32_THERM2_CTL. */
1094 *puValue = 0;
1095 return VINF_SUCCESS;
1096}
1097
1098
1099/** @callback_method_impl{FNCPUMWRMSR} */
1100static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32Therm2Ctl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1101{
1102 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1103 /** @todo implement IA32_THERM2_CTL. */
1104 return VINF_SUCCESS;
1105}
1106
1107
1108/** @callback_method_impl{FNCPUMRDMSR} */
1109static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MiscEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1110{
1111 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1112 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
1113 return VINF_SUCCESS;
1114}
1115
1116
1117/** @callback_method_impl{FNCPUMWRMSR} */
1118static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MiscEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1119{
1120 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1121#ifdef LOG_ENABLED
1122 uint64_t const uOld = pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
1123#endif
1124
1125 /* Unsupported bits are generally ignored and stripped by the MSR range
1126 entry that got us here. So, we just need to preserve fixed bits. */
1127 pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = uValue
1128 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
1129 | MSR_IA32_MISC_ENABLE_BTS_UNAVAIL;
1130
1131 Log(("CPUM: IA32_MISC_ENABLE; old=%#llx written=%#llx => %#llx\n",
1132 uOld, uValue, pVCpu->cpum.s.GuestMsrs.msr.MiscEnable));
1133
1134 /** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
1135 /** @todo Wire up MSR_IA32_MISC_ENABLE_XD_DISABLE. */
1136 return VINF_SUCCESS;
1137}
1138
1139
1140/** @callback_method_impl{FNCPUMRDMSR} */
1141static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McCtlStatusAddrMiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1142{
1143 RT_NOREF_PV(pVCpu); RT_NOREF_PV(pRange);
1144
1145 /** @todo Implement machine check exception injection. */
1146 switch (idMsr & 3)
1147 {
1148 case 0:
1149 case 1:
1150 *puValue = 0;
1151 break;
1152
1153 /* The ADDR and MISC registers aren't accessible since the
1154 corresponding STATUS bits are zero. */
1155 case 2:
1156 Log(("CPUM: Reading IA32_MCi_ADDR %#x -> #GP\n", idMsr));
1157 return VERR_CPUM_RAISE_GP_0;
1158 case 3:
1159 Log(("CPUM: Reading IA32_MCi_MISC %#x -> #GP\n", idMsr));
1160 return VERR_CPUM_RAISE_GP_0;
1161 }
1162 return VINF_SUCCESS;
1163}
1164
1165
1166/** @callback_method_impl{FNCPUMWRMSR} */
1167static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McCtlStatusAddrMiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1168{
1169 RT_NOREF_PV(pVCpu); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1170 switch (idMsr & 3)
1171 {
1172 case 0:
1173 /* Ignore writes to the CTL register. */
1174 break;
1175
1176 case 1:
1177 /* According to specs, the STATUS register can only be written to
1178 with the value 0. VBoxCpuReport thinks different for a
1179 Pentium M Dothan, but implementing according to specs now. */
1180 if (uValue != 0)
1181 {
1182 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_STATUS %#x -> #GP\n", uValue, idMsr));
1183 return VERR_CPUM_RAISE_GP_0;
1184 }
1185 break;
1186
1187 /* Specs states that ADDR and MISC can be cleared by writing zeros.
1188 Writing 1s will GP. Need to figure out how this relates to the
1189 ADDRV and MISCV status flags. If writing is independent of those
1190 bits, we need to know whether the CPU really implements them since
1191 that is exposed by writing 0 to them.
1192 Implementing the solution with the fewer GPs for now. */
1193 case 2:
1194 if (uValue != 0)
1195 {
1196 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_ADDR %#x -> #GP\n", uValue, idMsr));
1197 return VERR_CPUM_RAISE_GP_0;
1198 }
1199 break;
1200 case 3:
1201 if (uValue != 0)
1202 {
1203 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_MISC %#x -> #GP\n", uValue, idMsr));
1204 return VERR_CPUM_RAISE_GP_0;
1205 }
1206 break;
1207 }
1208 return VINF_SUCCESS;
1209}
1210
1211
1212/** @callback_method_impl{FNCPUMRDMSR} */
1213static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McNCtl2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1214{
1215 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1216 /** @todo Implement machine check exception injection. */
1217 *puValue = 0;
1218 return VINF_SUCCESS;
1219}
1220
1221
1222/** @callback_method_impl{FNCPUMWRMSR} */
1223static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McNCtl2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1224{
1225 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1226 /** @todo Implement machine check exception injection. */
1227 return VINF_SUCCESS;
1228}
1229
1230
1231/** @callback_method_impl{FNCPUMRDMSR} */
1232static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32DsArea(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1233{
1234 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1235 /** @todo implement IA32_DS_AREA. */
1236 *puValue = 0;
1237 return VINF_SUCCESS;
1238}
1239
1240
1241/** @callback_method_impl{FNCPUMWRMSR} */
1242static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32DsArea(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1243{
1244 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1245 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1246 return VINF_SUCCESS;
1247}
1248
1249
1250/** @callback_method_impl{FNCPUMRDMSR} */
1251static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32TscDeadline(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1252{
1253 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1254 /** @todo implement TSC deadline timer. */
1255 *puValue = 0;
1256 return VINF_SUCCESS;
1257}
1258
1259
1260/** @callback_method_impl{FNCPUMWRMSR} */
1261static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32TscDeadline(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1262{
1263 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1264 /** @todo implement TSC deadline timer. */
1265 return VINF_SUCCESS;
1266}
1267
1268
1269/** @callback_method_impl{FNCPUMRDMSR} */
1270static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32X2ApicN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1271{
1272 RT_NOREF_PV(pRange);
1273 return APICReadMsr(pVCpu, idMsr, puValue);
1274}
1275
1276
1277/** @callback_method_impl{FNCPUMWRMSR} */
1278static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32X2ApicN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1279{
1280 RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1281 return APICWriteMsr(pVCpu, idMsr, uValue);
1282}
1283
1284
1285/** @callback_method_impl{FNCPUMRDMSR} */
1286static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32DebugInterface(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1287{
1288 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1289 /** @todo IA32_DEBUG_INTERFACE (no docs) */
1290 *puValue = 0;
1291 return VINF_SUCCESS;
1292}
1293
1294
1295/** @callback_method_impl{FNCPUMWRMSR} */
1296static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32DebugInterface(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1297{
1298 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1299 /** @todo IA32_DEBUG_INTERFACE (no docs) */
1300 return VINF_SUCCESS;
1301}
1302
1303
1304/**
1305 * Gets IA32_VMX_BASIC for IEM and cpumMsrRd_Ia32VmxBasic.
1306 *
1307 * @returns IA32_VMX_BASIC value.
1308 * @param pVCpu The cross context per CPU structure.
1309 */
1310VMM_INT_DECL(uint64_t) CPUMGetGuestIa32VmxBasic(PVMCPU pVCpu)
1311{
1312 PCCPUMFEATURES pGuestFeatures = &pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures;
1313 uint64_t uVmxMsr;
1314 if (pGuestFeatures->fVmx)
1315 {
1316 uVmxMsr = RT_BF_MAKE(VMX_BF_BASIC_VMCS_ID, VMX_V_VMCS_REVISION_ID )
1317 | RT_BF_MAKE(VMX_BF_BASIC_VMCS_SIZE, VMX_V_VMCS_SIZE )
1318 | RT_BF_MAKE(VMX_BF_BASIC_PHYSADDR_WIDTH, VMX_V_VMCS_PHYSADDR_4G_LIMIT )
1319 | RT_BF_MAKE(VMX_BF_BASIC_DUAL_MON, 0 )
1320 | RT_BF_MAKE(VMX_BF_BASIC_VMCS_MEM_TYPE, VMX_BASIC_MEM_TYPE_WB )
1321 | RT_BF_MAKE(VMX_BF_BASIC_VMCS_INS_OUTS, pGuestFeatures->fVmxInsOutInfo)
1322 | RT_BF_MAKE(VMX_BF_BASIC_TRUE_CTLS, 0 );
1323 }
1324 else
1325 uVmxMsr = 0;
1326 return uVmxMsr;
1327}
1328
1329
1330/** @callback_method_impl{FNCPUMRDMSR} */
1331static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxBasic(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1332{
1333 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1334 *puValue = CPUMGetGuestIa32VmxBasic(pVCpu);
1335 return VINF_SUCCESS;
1336}
1337
1338
1339/** @callback_method_impl{FNCPUMRDMSR} */
1340static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxPinbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1341{
1342 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1343 PCCPUMFEATURES pGuestFeatures = &pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures;
1344 if (pGuestFeatures->fVmx)
1345 {
1346 uint32_t const fFeatures = (pGuestFeatures->fVmxExtIntExit << VMX_BF_PIN_CTLS_EXT_INT_EXIT_SHIFT )
1347 | (pGuestFeatures->fVmxNmiExit << VMX_BF_PIN_CTLS_NMI_EXIT_SHIFT )
1348 | (pGuestFeatures->fVmxVirtNmi << VMX_BF_PIN_CTLS_VIRT_NMI_SHIFT )
1349 | (pGuestFeatures->fVmxPreemptTimer << VMX_BF_PIN_CTLS_PREEMPT_TIMER_SHIFT)
1350 | (pGuestFeatures->fVmxPostedInt << VMX_BF_PIN_CTLS_POSTED_INT_SHIFT );
1351 uint32_t const fVal = VMX_PIN_CTLS_DEFAULT1;
1352 uint32_t const fZap = fFeatures | VMX_PIN_CTLS_DEFAULT1;
1353 AssertMsgReturn((fVal & fZap) == fVal, ("fVal=%#RX32 fZap=%#RX32 fFeatures=%#RX32\n", fVal, fZap, fFeatures),
1354 VERR_CPUM_INVALID_HWVIRT_FEAT_COMBO);
1355 *puValue = RT_MAKE_U64(fVal, fZap);
1356 }
1357 else
1358 *puValue = 0;
1359 return VINF_SUCCESS;
1360}
1361
1362
1363/** @callback_method_impl{FNCPUMRDMSR} */
1364static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxProcbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1365{
1366 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1367 PCCPUMFEATURES pGuestFeatures = &pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures;
1368 if (pGuestFeatures->fVmx)
1369 {
1370 uint32_t const fFeatures = (pGuestFeatures->fVmxIntWindowExit << VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_SHIFT )
1371 | (pGuestFeatures->fVmxTscOffsetting << VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_SHIFT)
1372 | (pGuestFeatures->fVmxHltExit << VMX_BF_PROC_CTLS_HLT_EXIT_SHIFT )
1373 | (pGuestFeatures->fVmxInvlpgExit << VMX_BF_PROC_CTLS_INVLPG_EXIT_SHIFT )
1374 | (pGuestFeatures->fVmxMwaitExit << VMX_BF_PROC_CTLS_MWAIT_EXIT_SHIFT )
1375 | (pGuestFeatures->fVmxRdpmcExit << VMX_BF_PROC_CTLS_RDPMC_EXIT_SHIFT )
1376 | (pGuestFeatures->fVmxRdtscExit << VMX_BF_PROC_CTLS_RDTSC_EXIT_SHIFT )
1377 | (pGuestFeatures->fVmxCr3LoadExit << VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_SHIFT )
1378 | (pGuestFeatures->fVmxCr3StoreExit << VMX_BF_PROC_CTLS_CR3_STORE_EXIT_SHIFT )
1379 | (pGuestFeatures->fVmxCr8LoadExit << VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_SHIFT )
1380 | (pGuestFeatures->fVmxCr8StoreExit << VMX_BF_PROC_CTLS_CR8_STORE_EXIT_SHIFT )
1381 | (pGuestFeatures->fVmxUseTprShadow << VMX_BF_PROC_CTLS_USE_TPR_SHADOW_SHIFT )
1382 | (pGuestFeatures->fVmxNmiWindowExit << VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_SHIFT )
1383 | (pGuestFeatures->fVmxMovDRxExit << VMX_BF_PROC_CTLS_MOV_DR_EXIT_SHIFT )
1384 | (pGuestFeatures->fVmxUncondIoExit << VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_SHIFT )
1385 | (pGuestFeatures->fVmxUseIoBitmaps << VMX_BF_PROC_CTLS_USE_IO_BITMAPS_SHIFT )
1386 | (pGuestFeatures->fVmxMonitorTrapFlag << VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_SHIFT )
1387 | (pGuestFeatures->fVmxUseMsrBitmaps << VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_SHIFT )
1388 | (pGuestFeatures->fVmxMonitorExit << VMX_BF_PROC_CTLS_MONITOR_EXIT_SHIFT )
1389 | (pGuestFeatures->fVmxPauseExit << VMX_BF_PROC_CTLS_PAUSE_EXIT_SHIFT )
1390 | (pGuestFeatures->fVmxSecondaryExecCtls << VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_SHIFT);
1391 uint32_t const fVal = VMX_PROC_CTLS_DEFAULT1;
1392 uint32_t const fZap = fFeatures | VMX_PROC_CTLS_DEFAULT1;
1393 AssertMsgReturn((fVal & fZap) == fVal, ("fVal=%#RX32 fZap=%#RX32 fFeatures=%#RX32\n", fVal, fZap, fFeatures),
1394 VERR_CPUM_INVALID_HWVIRT_FEAT_COMBO);
1395 *puValue = RT_MAKE_U64(fVal, fZap);
1396 }
1397 else
1398 *puValue = 0;
1399 return VINF_SUCCESS;
1400}
1401
1402
1403/** @callback_method_impl{FNCPUMRDMSR} */
1404static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxExitCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1405{
1406 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1407 PCCPUMFEATURES pGuestFeatures = &pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures;
1408 if (pGuestFeatures->fVmx)
1409 {
1410 uint32_t const fFeatures = (pGuestFeatures->fVmxExitSaveDebugCtls << VMX_BF_EXIT_CTLS_SAVE_DEBUG_SHIFT )
1411 | (pGuestFeatures->fVmxHostAddrSpaceSize << VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_SHIFT)
1412 | (pGuestFeatures->fVmxExitAckExtInt << VMX_BF_EXIT_CTLS_ACK_EXT_INT_SHIFT )
1413 | (pGuestFeatures->fVmxExitSavePatMsr << VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_SHIFT )
1414 | (pGuestFeatures->fVmxExitLoadPatMsr << VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_SHIFT )
1415 | (pGuestFeatures->fVmxExitSaveEferMsr << VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_SHIFT )
1416 | (pGuestFeatures->fVmxExitLoadEferMsr << VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_SHIFT )
1417 | (pGuestFeatures->fVmxSavePreemptTimer << VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_SHIFT );
1418 uint32_t const fVal = VMX_EXIT_CTLS_DEFAULT1;
1419 uint32_t const fZap = fFeatures | VMX_EXIT_CTLS_DEFAULT1;
1420 AssertMsgReturn((fVal & fZap) == fVal, ("fVal=%#RX32 fZap=%#RX32 fFeatures=%#RX32\n", fVal, fZap, fFeatures),
1421 VERR_CPUM_INVALID_HWVIRT_FEAT_COMBO);
1422 *puValue = RT_MAKE_U64(fVal, fZap);
1423 }
1424 else
1425 *puValue = 0;
1426 return VINF_SUCCESS;
1427}
1428
1429
1430/** @callback_method_impl{FNCPUMRDMSR} */
1431static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxEntryCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1432{
1433 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1434 PCCPUMFEATURES pGuestFeatures = &pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures;
1435 if (pGuestFeatures->fVmx)
1436 {
1437 uint32_t const fFeatures = (pGuestFeatures->fVmxEntryLoadDebugCtls << VMX_BF_ENTRY_CTLS_LOAD_DEBUG_SHIFT )
1438 | (pGuestFeatures->fVmxIa32eModeGuest << VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_SHIFT)
1439 | (pGuestFeatures->fVmxEntryLoadEferMsr << VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_SHIFT )
1440 | (pGuestFeatures->fVmxEntryLoadPatMsr << VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_SHIFT );
1441 uint32_t const fDefault1 = VMX_ENTRY_CTLS_DEFAULT1;
1442 uint32_t const fVal = fDefault1;
1443 uint32_t const fZap = fFeatures | fDefault1;
1444 AssertMsgReturn((fVal & fZap) == fVal, ("fVal=%#RX32 fZap=%#RX32 fFeatures=%#RX32\n", fVal, fZap, fFeatures),
1445 VERR_CPUM_INVALID_HWVIRT_FEAT_COMBO);
1446 *puValue = RT_MAKE_U64(fVal, fZap);
1447 }
1448 else
1449 *puValue = 0;
1450 return VINF_SUCCESS;
1451}
1452
1453
1454/** @callback_method_impl{FNCPUMRDMSR} */
1455static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxMisc(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1456{
1457 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1458 PCCPUMFEATURES pGuestFeatures = &pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures;
1459 if (pGuestFeatures->fVmx)
1460 {
1461 uint64_t uHostMsr;
1462 int rc = HMVmxGetHostMsr(pVCpu->CTX_SUFF(pVM), idMsr, &uHostMsr);
1463 AssertRCReturn(rc, rc);
1464 uint8_t const cMaxMsrs = RT_MIN(RT_BF_GET(uHostMsr, VMX_BF_MISC_MAX_MSRS), VMX_V_MAX_MSRS);
1465 *puValue = RT_BF_MAKE(VMX_BF_MISC_PREEMPT_TIMER_TSC, VMX_V_PREEMPT_TIMER_SHIFT )
1466 | RT_BF_MAKE(VMX_BF_MISC_EXIT_STORE_EFER_LMA, pGuestFeatures->fVmxExitStoreEferLma )
1467 | RT_BF_MAKE(VMX_BF_MISC_ACTIVITY_STATES, VMX_V_GUEST_ACTIVITY_STATE_MASK )
1468 | RT_BF_MAKE(VMX_BF_MISC_PT, 0 )
1469 | RT_BF_MAKE(VMX_BF_MISC_SMM_READ_SMBASE_MSR, 0 )
1470 | RT_BF_MAKE(VMX_BF_MISC_CR3_TARGET, VMX_V_CR3_TARGET_COUNT )
1471 | RT_BF_MAKE(VMX_BF_MISC_MAX_MSRS, cMaxMsrs )
1472 | RT_BF_MAKE(VMX_BF_MISC_VMXOFF_BLOCK_SMI, 0 )
1473 | RT_BF_MAKE(VMX_BF_MISC_VMWRITE_ALL, pGuestFeatures->fVmxVmwriteAll )
1474 | RT_BF_MAKE(VMX_BF_MISC_ENTRY_INJECT_SOFT_INT, pGuestFeatures->fVmxEntryInjectSoftInt)
1475 | RT_BF_MAKE(VMX_BF_MISC_MSEG_ID, VMX_V_MSEG_REV_ID );
1476 }
1477 else
1478 *puValue = 0;
1479 return VINF_SUCCESS;
1480}
1481
1482
1483/** @callback_method_impl{FNCPUMRDMSR} */
1484static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr0Fixed0(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1485{
1486 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1487 PCCPUMFEATURES pGuestFeatures = &pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures;
1488 if (pGuestFeatures->fVmx)
1489 *puValue = VMX_V_CR0_FIXED0;
1490 else
1491 *puValue = 0;
1492 return VINF_SUCCESS;
1493}
1494
1495
1496/** @callback_method_impl{FNCPUMRDMSR} */
1497static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr0Fixed1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1498{
1499 RT_NOREF_PV(pRange);
1500 PCCPUMFEATURES pGuestFeatures = &pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures;
1501 if (pGuestFeatures->fVmx)
1502 {
1503 int rc = HMVmxGetHostMsr(pVCpu->CTX_SUFF(pVM), idMsr, puValue);
1504 AssertRCReturn(rc, rc);
1505 *puValue |= VMX_V_CR0_FIXED0; /* Make sure the CR0 MB1 bits are not clear. */
1506 }
1507 else
1508 *puValue = 0;
1509 return VINF_SUCCESS;
1510}
1511
1512
1513/** @callback_method_impl{FNCPUMRDMSR} */
1514static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr4Fixed0(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1515{
1516 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1517 PCCPUMFEATURES pGuestFeatures = &pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures;
1518 if (pGuestFeatures->fVmx)
1519 *puValue = VMX_V_CR4_FIXED0;
1520 else
1521 *puValue = 0;
1522 return VINF_SUCCESS;
1523}
1524
1525
1526/** @callback_method_impl{FNCPUMRDMSR} */
1527static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr4Fixed1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1528{
1529 RT_NOREF_PV(pRange);
1530 PCCPUMFEATURES pGuestFeatures = &pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures;
1531 if (pGuestFeatures->fVmx)
1532 {
1533 int rc = HMVmxGetHostMsr(pVCpu->CTX_SUFF(pVM), idMsr, puValue);
1534 AssertRCReturn(rc, rc);
1535 *puValue |= VMX_V_CR4_FIXED0; /* Make sure the CR4 MB1 bits are not clear. */
1536 }
1537 else
1538 *puValue = 0;
1539 return VINF_SUCCESS;
1540}
1541
1542
1543/** @callback_method_impl{FNCPUMRDMSR} */
1544static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxVmcsEnum(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1545{
1546 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1547 PCCPUMFEATURES pGuestFeatures = &pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures;
1548 if (pGuestFeatures->fVmx)
1549 *puValue = VMX_V_VMCS_MAX_INDEX << VMX_BF_VMCS_ENUM_HIGHEST_IDX_SHIFT;
1550 else
1551 *puValue = 0;
1552 return VINF_SUCCESS;
1553}
1554
1555
1556/** @callback_method_impl{FNCPUMRDMSR} */
1557static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxProcBasedCtls2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1558{
1559 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1560 PCCPUMFEATURES pGuestFeatures = &pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures;
1561 if (pGuestFeatures->fVmx)
1562 {
1563 uint32_t const fFeatures = (pGuestFeatures->fVmxVirtApicAccess << VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_SHIFT )
1564 | (pGuestFeatures->fVmxEpt << VMX_BF_PROC_CTLS2_EPT_SHIFT )
1565 | (pGuestFeatures->fVmxDescTableExit << VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_SHIFT )
1566 | (pGuestFeatures->fVmxRdtscp << VMX_BF_PROC_CTLS2_RDTSCP_SHIFT )
1567 | (pGuestFeatures->fVmxVirtX2ApicAccess << VMX_BF_PROC_CTLS2_VIRT_X2APIC_ACCESS_SHIFT)
1568 | (pGuestFeatures->fVmxVpid << VMX_BF_PROC_CTLS2_VPID_SHIFT )
1569 | (pGuestFeatures->fVmxWbinvdExit << VMX_BF_PROC_CTLS2_WBINVD_EXIT_SHIFT )
1570 | (pGuestFeatures->fVmxUnrestrictedGuest << VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_SHIFT)
1571 | (pGuestFeatures->fVmxApicRegVirt << VMX_BF_PROC_CTLS2_APIC_REG_VIRT_SHIFT )
1572 | (pGuestFeatures->fVmxVirtIntDelivery << VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_SHIFT )
1573 | (pGuestFeatures->fVmxPauseLoopExit << VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_SHIFT )
1574 | (pGuestFeatures->fVmxRdrandExit << VMX_BF_PROC_CTLS2_RDRAND_EXIT_SHIFT )
1575 | (pGuestFeatures->fVmxInvpcid << VMX_BF_PROC_CTLS2_INVPCID_SHIFT )
1576 | (pGuestFeatures->fVmxVmFunc << VMX_BF_PROC_CTLS2_VMFUNC_SHIFT )
1577 | (pGuestFeatures->fVmxVmcsShadowing << VMX_BF_PROC_CTLS2_VMCS_SHADOWING_SHIFT )
1578 | (pGuestFeatures->fVmxRdseedExit << VMX_BF_PROC_CTLS2_RDSEED_EXIT_SHIFT )
1579 | (pGuestFeatures->fVmxPml << VMX_BF_PROC_CTLS2_PML_SHIFT )
1580 | (pGuestFeatures->fVmxEptXcptVe << VMX_BF_PROC_CTLS2_EPT_VE_SHIFT )
1581 | (pGuestFeatures->fVmxXsavesXrstors << VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_SHIFT )
1582 | (pGuestFeatures->fVmxUseTscScaling << VMX_BF_PROC_CTLS2_TSC_SCALING_SHIFT );
1583 uint32_t const fVal = 0;
1584 uint32_t const fZap = fFeatures;
1585 *puValue = RT_MAKE_U64(fVal, fZap);
1586 }
1587 else
1588 *puValue = 0;
1589 return VINF_SUCCESS;
1590}
1591
1592
1593/** @callback_method_impl{FNCPUMRDMSR} */
1594static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxEptVpidCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1595{
1596 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1597 *puValue = 0;
1598 return VINF_SUCCESS;
1599}
1600
1601
1602/** @callback_method_impl{FNCPUMRDMSR} */
1603static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTruePinbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1604{
1605 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1606 *puValue = 0;
1607 return VINF_SUCCESS;
1608}
1609
1610
1611/** @callback_method_impl{FNCPUMRDMSR} */
1612static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTrueProcbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1613{
1614 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1615 *puValue = 0;
1616 return VINF_SUCCESS;
1617}
1618
1619
1620/** @callback_method_impl{FNCPUMRDMSR} */
1621static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTrueExitCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1622{
1623 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1624 *puValue = 0;
1625 return VINF_SUCCESS;
1626}
1627
1628
1629/** @callback_method_impl{FNCPUMRDMSR} */
1630static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTrueEntryCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1631{
1632 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1633 *puValue = 0;
1634 return VINF_SUCCESS;
1635}
1636
1637
1638/**
1639 * Gets IA32_VMX_VMFUNC for IEM and cpumMsrRd_Ia32VmxVmFunc.
1640 *
1641 * @returns IA32_VMX_VMFUNC value.
1642 * @param pVCpu The cross context per CPU structure.
1643 */
1644VMM_INT_DECL(uint64_t) CPUMGetGuestIa32VmxVmFunc(PVMCPU pVCpu)
1645{
1646 PCCPUMFEATURES pGuestFeatures = &pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures;
1647 uint64_t uVmxMsr;
1648 if ( pGuestFeatures->fVmx
1649 && pGuestFeatures->fVmxVmFunc)
1650 uVmxMsr = RT_BF_MAKE(VMX_BF_VMFUNC_EPTP_SWITCHING, 1);
1651 else
1652 uVmxMsr = 0;
1653 return uVmxMsr;
1654}
1655
1656
1657/** @callback_method_impl{FNCPUMRDMSR} */
1658static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxVmFunc(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1659{
1660 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1661 *puValue = CPUMGetGuestIa32VmxVmFunc(pVCpu);
1662 return VINF_SUCCESS;
1663}
1664
1665
1666/** @callback_method_impl{FNCPUMRDMSR} */
1667static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SpecCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1668{
1669 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1670 *puValue = pVCpu->cpum.s.GuestMsrs.msr.SpecCtrl;
1671 return VINF_SUCCESS;
1672}
1673
1674
1675/** @callback_method_impl{FNCPUMWRMSR} */
1676static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SpecCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1677{
1678 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1679
1680 /* NB: The STIBP bit can be set even when IBRS is present, regardless of whether STIBP is actually implemented. */
1681 if (uValue & ~(MSR_IA32_SPEC_CTRL_F_IBRS | MSR_IA32_SPEC_CTRL_F_STIBP))
1682 {
1683 Log(("CPUM: Invalid IA32_SPEC_CTRL bits (trying to write %#llx)\n", uValue));
1684 return VERR_CPUM_RAISE_GP_0;
1685 }
1686
1687 pVCpu->cpum.s.GuestMsrs.msr.SpecCtrl = uValue;
1688 return VINF_SUCCESS;
1689}
1690
1691
1692/** @callback_method_impl{FNCPUMWRMSR} */
1693static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PredCmd(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1694{
1695 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1696 return VINF_SUCCESS;
1697}
1698
1699
1700/** @callback_method_impl{FNCPUMRDMSR} */
1701static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ArchCapabilities(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1702{
1703 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1704 *puValue = pVCpu->cpum.s.GuestMsrs.msr.ArchCaps;
1705 return VINF_SUCCESS;
1706}
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719/*
1720 * AMD64
1721 * AMD64
1722 * AMD64
1723 */
1724
1725
1726/** @callback_method_impl{FNCPUMRDMSR} */
1727static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64Efer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1728{
1729 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1730 *puValue = pVCpu->cpum.s.Guest.msrEFER;
1731 return VINF_SUCCESS;
1732}
1733
1734
1735/** @callback_method_impl{FNCPUMWRMSR} */
1736static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64Efer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1737{
1738 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1739 uint64_t uValidatedEfer;
1740 uint64_t const uOldEfer = pVCpu->cpum.s.Guest.msrEFER;
1741 int rc = CPUMQueryValidatedGuestEfer(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.s.Guest.cr0, uOldEfer, uValue, &uValidatedEfer);
1742 if (RT_FAILURE(rc))
1743 return VERR_CPUM_RAISE_GP_0;
1744
1745 CPUMSetGuestMsrEferNoCheck(pVCpu, uOldEfer, uValidatedEfer);
1746 return VINF_SUCCESS;
1747}
1748
1749
1750/** @callback_method_impl{FNCPUMRDMSR} */
1751static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64SyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1752{
1753 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1754 *puValue = pVCpu->cpum.s.Guest.msrSTAR;
1755 return VINF_SUCCESS;
1756}
1757
1758
1759/** @callback_method_impl{FNCPUMWRMSR} */
1760static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64SyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1761{
1762 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1763 pVCpu->cpum.s.Guest.msrSTAR = uValue;
1764 return VINF_SUCCESS;
1765}
1766
1767
1768/** @callback_method_impl{FNCPUMRDMSR} */
1769static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64LongSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1770{
1771 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1772 *puValue = pVCpu->cpum.s.Guest.msrLSTAR;
1773 return VINF_SUCCESS;
1774}
1775
1776
1777/** @callback_method_impl{FNCPUMWRMSR} */
1778static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64LongSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1779{
1780 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1781 if (!X86_IS_CANONICAL(uValue))
1782 {
1783 Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
1784 return VERR_CPUM_RAISE_GP_0;
1785 }
1786 pVCpu->cpum.s.Guest.msrLSTAR = uValue;
1787 return VINF_SUCCESS;
1788}
1789
1790
1791/** @callback_method_impl{FNCPUMRDMSR} */
1792static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64CompSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1793{
1794 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1795 *puValue = pVCpu->cpum.s.Guest.msrCSTAR;
1796 return VINF_SUCCESS;
1797}
1798
1799
1800/** @callback_method_impl{FNCPUMWRMSR} */
1801static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64CompSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1802{
1803 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1804 if (!X86_IS_CANONICAL(uValue))
1805 {
1806 Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
1807 return VERR_CPUM_RAISE_GP_0;
1808 }
1809 pVCpu->cpum.s.Guest.msrCSTAR = uValue;
1810 return VINF_SUCCESS;
1811}
1812
1813
1814/** @callback_method_impl{FNCPUMRDMSR} */
1815static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64SyscallFlagMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1816{
1817 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1818 *puValue = pVCpu->cpum.s.Guest.msrSFMASK;
1819 return VINF_SUCCESS;
1820}
1821
1822
1823/** @callback_method_impl{FNCPUMWRMSR} */
1824static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64SyscallFlagMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1825{
1826 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1827 pVCpu->cpum.s.Guest.msrSFMASK = uValue;
1828 return VINF_SUCCESS;
1829}
1830
1831
1832/** @callback_method_impl{FNCPUMRDMSR} */
1833static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64FsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1834{
1835 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1836 *puValue = pVCpu->cpum.s.Guest.fs.u64Base;
1837 return VINF_SUCCESS;
1838}
1839
1840
1841/** @callback_method_impl{FNCPUMWRMSR} */
1842static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64FsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1843{
1844 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1845 pVCpu->cpum.s.Guest.fs.u64Base = uValue;
1846 return VINF_SUCCESS;
1847}
1848
1849
1850/** @callback_method_impl{FNCPUMRDMSR} */
1851static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64GsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1852{
1853 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1854 *puValue = pVCpu->cpum.s.Guest.gs.u64Base;
1855 return VINF_SUCCESS;
1856}
1857
1858/** @callback_method_impl{FNCPUMWRMSR} */
1859static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64GsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1860{
1861 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1862 pVCpu->cpum.s.Guest.gs.u64Base = uValue;
1863 return VINF_SUCCESS;
1864}
1865
1866
1867
1868/** @callback_method_impl{FNCPUMRDMSR} */
1869static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64KernelGsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1870{
1871 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1872 *puValue = pVCpu->cpum.s.Guest.msrKERNELGSBASE;
1873 return VINF_SUCCESS;
1874}
1875
1876/** @callback_method_impl{FNCPUMWRMSR} */
1877static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64KernelGsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1878{
1879 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1880 pVCpu->cpum.s.Guest.msrKERNELGSBASE = uValue;
1881 return VINF_SUCCESS;
1882}
1883
1884
1885/** @callback_method_impl{FNCPUMRDMSR} */
1886static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64TscAux(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1887{
1888 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1889 *puValue = pVCpu->cpum.s.GuestMsrs.msr.TscAux;
1890 return VINF_SUCCESS;
1891}
1892
1893/** @callback_method_impl{FNCPUMWRMSR} */
1894static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64TscAux(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1895{
1896 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1897 pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
1898 return VINF_SUCCESS;
1899}
1900
1901
1902/*
1903 * Intel specific
1904 * Intel specific
1905 * Intel specific
1906 */
1907
1908/** @callback_method_impl{FNCPUMRDMSR} */
1909static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelEblCrPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1910{
1911 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1912 /** @todo recalc clock frequency ratio? */
1913 *puValue = pRange->uValue;
1914 return VINF_SUCCESS;
1915}
1916
1917
1918/** @callback_method_impl{FNCPUMWRMSR} */
1919static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelEblCrPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1920{
1921 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1922 /** @todo Write EBL_CR_POWERON: Remember written bits. */
1923 return VINF_SUCCESS;
1924}
1925
1926
1927/** @callback_method_impl{FNCPUMRDMSR} */
1928static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7CoreThreadCount(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1929{
1930 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1931
1932 /* Note! According to cpuid_set_info in XNU (10.7.0), Westmere CPU only
1933 have a 4-bit core count. */
1934 uint16_t cCores = pVCpu->CTX_SUFF(pVM)->cCpus;
1935 uint16_t cThreads = cCores; /** @todo hyper-threading. */
1936 *puValue = RT_MAKE_U32(cThreads, cCores);
1937 return VINF_SUCCESS;
1938}
1939
1940
1941/** @callback_method_impl{FNCPUMRDMSR} */
1942static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP4EbcHardPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1943{
1944 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1945 /** @todo P4 hard power on config */
1946 *puValue = pRange->uValue;
1947 return VINF_SUCCESS;
1948}
1949
1950
1951/** @callback_method_impl{FNCPUMWRMSR} */
1952static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP4EbcHardPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1953{
1954 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1955 /** @todo P4 hard power on config */
1956 return VINF_SUCCESS;
1957}
1958
1959
1960/** @callback_method_impl{FNCPUMRDMSR} */
1961static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP4EbcSoftPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1962{
1963 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1964 /** @todo P4 soft power on config */
1965 *puValue = pRange->uValue;
1966 return VINF_SUCCESS;
1967}
1968
1969
1970/** @callback_method_impl{FNCPUMWRMSR} */
1971static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP4EbcSoftPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1972{
1973 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1974 /** @todo P4 soft power on config */
1975 return VINF_SUCCESS;
1976}
1977
1978
1979/** @callback_method_impl{FNCPUMRDMSR} */
1980static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP4EbcFrequencyId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1981{
1982 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1983
1984 uint64_t uValue;
1985 PVM pVM = pVCpu->CTX_SUFF(pVM);
1986 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
1987 if (pVM->cpum.s.GuestFeatures.uModel >= 2)
1988 {
1989 if (uScalableBusHz <= CPUM_SBUSFREQ_100MHZ && pVM->cpum.s.GuestFeatures.uModel <= 2)
1990 {
1991 uScalableBusHz = CPUM_SBUSFREQ_100MHZ;
1992 uValue = 0;
1993 }
1994 else if (uScalableBusHz <= CPUM_SBUSFREQ_133MHZ)
1995 {
1996 uScalableBusHz = CPUM_SBUSFREQ_133MHZ;
1997 uValue = 1;
1998 }
1999 else if (uScalableBusHz <= CPUM_SBUSFREQ_167MHZ)
2000 {
2001 uScalableBusHz = CPUM_SBUSFREQ_167MHZ;
2002 uValue = 3;
2003 }
2004 else if (uScalableBusHz <= CPUM_SBUSFREQ_200MHZ)
2005 {
2006 uScalableBusHz = CPUM_SBUSFREQ_200MHZ;
2007 uValue = 2;
2008 }
2009 else if (uScalableBusHz <= CPUM_SBUSFREQ_267MHZ && pVM->cpum.s.GuestFeatures.uModel > 2)
2010 {
2011 uScalableBusHz = CPUM_SBUSFREQ_267MHZ;
2012 uValue = 0;
2013 }
2014 else
2015 {
2016 uScalableBusHz = CPUM_SBUSFREQ_333MHZ;
2017 uValue = 6;
2018 }
2019 uValue <<= 16;
2020
2021 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
2022 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
2023 uValue |= (uint32_t)uTscRatio << 24;
2024
2025 uValue |= pRange->uValue & ~UINT64_C(0xff0f0000);
2026 }
2027 else
2028 {
2029 /* Probably more stuff here, but intel doesn't want to tell us. */
2030 uValue = pRange->uValue;
2031 uValue &= ~(RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23)); /* 100 MHz is only documented value */
2032 }
2033
2034 *puValue = uValue;
2035 return VINF_SUCCESS;
2036}
2037
2038
2039/** @callback_method_impl{FNCPUMWRMSR} */
2040static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP4EbcFrequencyId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2041{
2042 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2043 /** @todo P4 bus frequency config */
2044 return VINF_SUCCESS;
2045}
2046
2047
2048/** @callback_method_impl{FNCPUMRDMSR} */
2049static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP6FsbFrequency(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2050{
2051 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2052
2053 /* Convert the scalable bus frequency to the encoding in the intel manual (for core+). */
2054 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVCpu->CTX_SUFF(pVM));
2055 if (uScalableBusHz <= CPUM_SBUSFREQ_100MHZ)
2056 *puValue = 5;
2057 else if (uScalableBusHz <= CPUM_SBUSFREQ_133MHZ)
2058 *puValue = 1;
2059 else if (uScalableBusHz <= CPUM_SBUSFREQ_167MHZ)
2060 *puValue = 3;
2061 else if (uScalableBusHz <= CPUM_SBUSFREQ_200MHZ)
2062 *puValue = 2;
2063 else if (uScalableBusHz <= CPUM_SBUSFREQ_267MHZ)
2064 *puValue = 0;
2065 else if (uScalableBusHz <= CPUM_SBUSFREQ_333MHZ)
2066 *puValue = 4;
2067 else /*if (uScalableBusHz <= CPUM_SBUSFREQ_400MHZ)*/
2068 *puValue = 6;
2069
2070 *puValue |= pRange->uValue & ~UINT64_C(0x7);
2071
2072 return VINF_SUCCESS;
2073}
2074
2075
2076/** @callback_method_impl{FNCPUMRDMSR} */
2077static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelPlatformInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2078{
2079 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2080
2081 /* Just indicate a fixed TSC, no turbo boost, no programmable anything. */
2082 PVM pVM = pVCpu->CTX_SUFF(pVM);
2083 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
2084 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
2085 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
2086 uint64_t uValue = ((uint32_t)uTscRatio << 8) /* TSC invariant frequency. */
2087 | ((uint64_t)uTscRatio << 40); /* The max turbo frequency. */
2088
2089 /* Ivy bridge has a minimum operating ratio as well. */
2090 if (true) /** @todo detect sandy bridge. */
2091 uValue |= (uint64_t)uTscRatio << 48;
2092
2093 *puValue = uValue;
2094 return VINF_SUCCESS;
2095}
2096
2097
2098/** @callback_method_impl{FNCPUMRDMSR} */
2099static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelFlexRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2100{
2101 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2102
2103 uint64_t uValue = pRange->uValue & ~UINT64_C(0x1ff00);
2104
2105 PVM pVM = pVCpu->CTX_SUFF(pVM);
2106 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
2107 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
2108 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
2109 uValue |= (uint32_t)uTscRatio << 8;
2110
2111 *puValue = uValue;
2112 return VINF_SUCCESS;
2113}
2114
2115
2116/** @callback_method_impl{FNCPUMWRMSR} */
2117static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelFlexRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2118{
2119 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2120 /** @todo implement writing MSR_FLEX_RATIO. */
2121 return VINF_SUCCESS;
2122}
2123
2124
2125/** @callback_method_impl{FNCPUMRDMSR} */
2126static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelPkgCStConfigControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2127{
2128 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2129 *puValue = pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl;
2130 return VINF_SUCCESS;
2131}
2132
2133
2134/** @callback_method_impl{FNCPUMWRMSR} */
2135static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelPkgCStConfigControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2136{
2137 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
2138
2139 if (pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl & RT_BIT_64(15))
2140 {
2141 Log(("CPUM: WRMSR %#x (%s), %#llx: Write protected -> #GP\n", idMsr, pRange->szName, uValue));
2142 return VERR_CPUM_RAISE_GP_0;
2143 }
2144#if 0 /** @todo check what real (old) hardware does. */
2145 if ((uValue & 7) >= 5)
2146 {
2147 Log(("CPUM: WRMSR %#x (%s), %#llx: Invalid limit (%d) -> #GP\n", idMsr, pRange->szName, uValue, (uint32_t)(uValue & 7)));
2148 return VERR_CPUM_RAISE_GP_0;
2149 }
2150#endif
2151 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = uValue;
2152 return VINF_SUCCESS;
2153}
2154
2155
2156/** @callback_method_impl{FNCPUMRDMSR} */
2157static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelPmgIoCaptureBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2158{
2159 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2160 /** @todo implement I/O mwait wakeup. */
2161 *puValue = 0;
2162 return VINF_SUCCESS;
2163}
2164
2165
2166/** @callback_method_impl{FNCPUMWRMSR} */
2167static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelPmgIoCaptureBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2168{
2169 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2170 /** @todo implement I/O mwait wakeup. */
2171 return VINF_SUCCESS;
2172}
2173
2174
2175/** @callback_method_impl{FNCPUMRDMSR} */
2176static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchFromToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2177{
2178 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2179 /** @todo implement last branch records. */
2180 *puValue = 0;
2181 return VINF_SUCCESS;
2182}
2183
2184
2185/** @callback_method_impl{FNCPUMWRMSR} */
2186static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchFromToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2187{
2188 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2189 /** @todo implement last branch records. */
2190 return VINF_SUCCESS;
2191}
2192
2193
2194/** @callback_method_impl{FNCPUMRDMSR} */
2195static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchFromN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2196{
2197 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2198 /** @todo implement last branch records. */
2199 *puValue = 0;
2200 return VINF_SUCCESS;
2201}
2202
2203
2204/** @callback_method_impl{FNCPUMWRMSR} */
2205static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchFromN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2206{
2207 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
2208 /** @todo implement last branch records. */
2209 /** @todo Probing indicates that bit 63 is settable on SandyBridge, at least
2210 * if the rest of the bits are zero. Automatic sign extending?
2211 * Investigate! */
2212 if (!X86_IS_CANONICAL(uValue))
2213 {
2214 Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
2215 return VERR_CPUM_RAISE_GP_0;
2216 }
2217 return VINF_SUCCESS;
2218}
2219
2220
2221/** @callback_method_impl{FNCPUMRDMSR} */
2222static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2223{
2224 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2225 /** @todo implement last branch records. */
2226 *puValue = 0;
2227 return VINF_SUCCESS;
2228}
2229
2230
2231/** @callback_method_impl{FNCPUMWRMSR} */
2232static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2233{
2234 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2235 /** @todo implement last branch records. */
2236 /** @todo Probing indicates that bit 63 is settable on SandyBridge, at least
2237 * if the rest of the bits are zero. Automatic sign extending?
2238 * Investigate! */
2239 if (!X86_IS_CANONICAL(uValue))
2240 {
2241 Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
2242 return VERR_CPUM_RAISE_GP_0;
2243 }
2244 return VINF_SUCCESS;
2245}
2246
2247
2248/** @callback_method_impl{FNCPUMRDMSR} */
2249static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchTos(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2250{
2251 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2252 /** @todo implement last branch records. */
2253 *puValue = 0;
2254 return VINF_SUCCESS;
2255}
2256
2257
2258/** @callback_method_impl{FNCPUMWRMSR} */
2259static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchTos(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2260{
2261 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2262 /** @todo implement last branch records. */
2263 return VINF_SUCCESS;
2264}
2265
2266
2267/** @callback_method_impl{FNCPUMRDMSR} */
2268static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelBblCrCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2269{
2270 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2271 *puValue = pRange->uValue;
2272 return VINF_SUCCESS;
2273}
2274
2275
2276/** @callback_method_impl{FNCPUMWRMSR} */
2277static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelBblCrCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2278{
2279 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2280 return VINF_SUCCESS;
2281}
2282
2283
2284/** @callback_method_impl{FNCPUMRDMSR} */
2285static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelBblCrCtl3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2286{
2287 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2288 *puValue = pRange->uValue;
2289 return VINF_SUCCESS;
2290}
2291
2292
2293/** @callback_method_impl{FNCPUMWRMSR} */
2294static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelBblCrCtl3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2295{
2296 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2297 return VINF_SUCCESS;
2298}
2299
2300
2301/** @callback_method_impl{FNCPUMRDMSR} */
2302static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7TemperatureTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2303{
2304 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2305 *puValue = pRange->uValue;
2306 return VINF_SUCCESS;
2307}
2308
2309
2310/** @callback_method_impl{FNCPUMWRMSR} */
2311static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7TemperatureTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2312{
2313 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2314 return VINF_SUCCESS;
2315}
2316
2317
2318/** @callback_method_impl{FNCPUMRDMSR} */
2319static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7MsrOffCoreResponseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2320{
2321 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2322 /** @todo machine check. */
2323 *puValue = pRange->uValue;
2324 return VINF_SUCCESS;
2325}
2326
2327
2328/** @callback_method_impl{FNCPUMWRMSR} */
2329static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7MsrOffCoreResponseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2330{
2331 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2332 /** @todo machine check. */
2333 return VINF_SUCCESS;
2334}
2335
2336
2337/** @callback_method_impl{FNCPUMRDMSR} */
2338static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7MiscPwrMgmt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2339{
2340 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2341 *puValue = 0;
2342 return VINF_SUCCESS;
2343}
2344
2345
2346/** @callback_method_impl{FNCPUMWRMSR} */
2347static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7MiscPwrMgmt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2348{
2349 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2350 return VINF_SUCCESS;
2351}
2352
2353
2354/** @callback_method_impl{FNCPUMRDMSR} */
2355static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP6CrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2356{
2357 RT_NOREF_PV(idMsr);
2358 int rc = CPUMGetGuestCRx(pVCpu, pRange->uValue, puValue);
2359 AssertRC(rc);
2360 return VINF_SUCCESS;
2361}
2362
2363
2364/** @callback_method_impl{FNCPUMWRMSR} */
2365static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP6CrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2366{
2367 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2368 /* This CRx interface differs from the MOV CRx, GReg interface in that
2369 #GP(0) isn't raised if unsupported bits are written to. Instead they
2370 are simply ignored and masked off. (Pentium M Dothan) */
2371 /** @todo Implement MSR_P6_CRx writing. Too much effort for very little, if
2372 * any, gain. */
2373 return VINF_SUCCESS;
2374}
2375
2376
2377/** @callback_method_impl{FNCPUMRDMSR} */
2378static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCpuId1FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2379{
2380 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2381 /** @todo implement CPUID masking. */
2382 *puValue = UINT64_MAX;
2383 return VINF_SUCCESS;
2384}
2385
2386
2387/** @callback_method_impl{FNCPUMWRMSR} */
2388static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCpuId1FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2389{
2390 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2391 /** @todo implement CPUID masking. */
2392 return VINF_SUCCESS;
2393}
2394
2395
2396/** @callback_method_impl{FNCPUMRDMSR} */
2397static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCpuId1FeatureMaskEax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2398{
2399 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2400 /** @todo implement CPUID masking. */
2401 *puValue = 0;
2402 return VINF_SUCCESS;
2403}
2404
2405
2406/** @callback_method_impl{FNCPUMWRMSR} */
2407static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCpuId1FeatureMaskEax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2408{
2409 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2410 /** @todo implement CPUID masking. */
2411 return VINF_SUCCESS;
2412}
2413
2414
2415
2416/** @callback_method_impl{FNCPUMRDMSR} */
2417static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCpuId80000001FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2418{
2419 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2420 /** @todo implement CPUID masking. */
2421 *puValue = UINT64_MAX;
2422 return VINF_SUCCESS;
2423}
2424
2425
2426/** @callback_method_impl{FNCPUMWRMSR} */
2427static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCpuId80000001FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2428{
2429 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2430 /** @todo implement CPUID masking. */
2431 return VINF_SUCCESS;
2432}
2433
2434
2435
2436/** @callback_method_impl{FNCPUMRDMSR} */
2437static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyAesNiCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2438{
2439 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2440 /** @todo implement AES-NI. */
2441 *puValue = 3; /* Bit 0 is lock bit, bit 1 disables AES-NI. That's what they say. */
2442 return VINF_SUCCESS;
2443}
2444
2445
2446/** @callback_method_impl{FNCPUMWRMSR} */
2447static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyAesNiCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2448{
2449 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2450 /** @todo implement AES-NI. */
2451 return VERR_CPUM_RAISE_GP_0;
2452}
2453
2454
2455/** @callback_method_impl{FNCPUMRDMSR} */
2456static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7TurboRatioLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2457{
2458 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2459 /** @todo implement intel C states. */
2460 *puValue = pRange->uValue;
2461 return VINF_SUCCESS;
2462}
2463
2464
2465/** @callback_method_impl{FNCPUMWRMSR} */
2466static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7TurboRatioLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2467{
2468 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2469 /** @todo implement intel C states. */
2470 return VINF_SUCCESS;
2471}
2472
2473
2474/** @callback_method_impl{FNCPUMRDMSR} */
2475static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7LbrSelect(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2476{
2477 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2478 /** @todo implement last-branch-records. */
2479 *puValue = 0;
2480 return VINF_SUCCESS;
2481}
2482
2483
2484/** @callback_method_impl{FNCPUMWRMSR} */
2485static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7LbrSelect(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2486{
2487 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2488 /** @todo implement last-branch-records. */
2489 return VINF_SUCCESS;
2490}
2491
2492
2493/** @callback_method_impl{FNCPUMRDMSR} */
2494static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyErrorControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2495{
2496 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2497 /** @todo implement memory error injection (MSR_ERROR_CONTROL). */
2498 *puValue = 0;
2499 return VINF_SUCCESS;
2500}
2501
2502
2503/** @callback_method_impl{FNCPUMWRMSR} */
2504static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyErrorControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2505{
2506 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2507 /** @todo implement memory error injection (MSR_ERROR_CONTROL). */
2508 return VINF_SUCCESS;
2509}
2510
2511
2512/** @callback_method_impl{FNCPUMRDMSR} */
2513static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7VirtualLegacyWireCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2514{
2515 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2516 /** @todo implement memory VLW? */
2517 *puValue = pRange->uValue;
2518 /* Note: A20M is known to be bit 1 as this was disclosed in spec update
2519 AAJ49/AAK51/????, which documents the inversion of this bit. The
2520 Sandy bridge CPU here has value 0x74, so it probably doesn't have a BIOS
2521 that correct things. Some guesses at the other bits:
2522 bit 2 = INTR
2523 bit 4 = SMI
2524 bit 5 = INIT
2525 bit 6 = NMI */
2526 return VINF_SUCCESS;
2527}
2528
2529
2530/** @callback_method_impl{FNCPUMRDMSR} */
2531static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7PowerCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2532{
2533 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2534 /** @todo intel power management */
2535 *puValue = 0;
2536 return VINF_SUCCESS;
2537}
2538
2539
2540/** @callback_method_impl{FNCPUMWRMSR} */
2541static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7PowerCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2542{
2543 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2544 /** @todo intel power management */
2545 return VINF_SUCCESS;
2546}
2547
2548
2549/** @callback_method_impl{FNCPUMRDMSR} */
2550static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyPebsNumAlt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2551{
2552 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2553 /** @todo intel performance counters. */
2554 *puValue = 0;
2555 return VINF_SUCCESS;
2556}
2557
2558
2559/** @callback_method_impl{FNCPUMWRMSR} */
2560static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyPebsNumAlt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2561{
2562 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2563 /** @todo intel performance counters. */
2564 return VINF_SUCCESS;
2565}
2566
2567
2568/** @callback_method_impl{FNCPUMRDMSR} */
2569static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7PebsLdLat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2570{
2571 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2572 /** @todo intel performance counters. */
2573 *puValue = 0;
2574 return VINF_SUCCESS;
2575}
2576
2577
2578/** @callback_method_impl{FNCPUMWRMSR} */
2579static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7PebsLdLat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2580{
2581 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2582 /** @todo intel performance counters. */
2583 return VINF_SUCCESS;
2584}
2585
2586
2587/** @callback_method_impl{FNCPUMRDMSR} */
2588static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7PkgCnResidencyN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2589{
2590 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2591 /** @todo intel power management. */
2592 *puValue = 0;
2593 return VINF_SUCCESS;
2594}
2595
2596
2597/** @callback_method_impl{FNCPUMRDMSR} */
2598static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7CoreCnResidencyN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2599{
2600 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2601 /** @todo intel power management. */
2602 *puValue = 0;
2603 return VINF_SUCCESS;
2604}
2605
2606
2607/** @callback_method_impl{FNCPUMRDMSR} */
2608static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyVrCurrentConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2609{
2610 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2611 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2612 *puValue = 0;
2613 return VINF_SUCCESS;
2614}
2615
2616
2617/** @callback_method_impl{FNCPUMWRMSR} */
2618static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyVrCurrentConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2619{
2620 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2621 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2622 return VINF_SUCCESS;
2623}
2624
2625
2626/** @callback_method_impl{FNCPUMRDMSR} */
2627static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyVrMiscConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2628{
2629 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2630 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2631 *puValue = 0;
2632 return VINF_SUCCESS;
2633}
2634
2635
2636/** @callback_method_impl{FNCPUMWRMSR} */
2637static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyVrMiscConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2638{
2639 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2640 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2641 return VINF_SUCCESS;
2642}
2643
2644
2645/** @callback_method_impl{FNCPUMRDMSR} */
2646static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyRaplPowerUnit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2647{
2648 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2649 /** @todo intel RAPL. */
2650 *puValue = pRange->uValue;
2651 return VINF_SUCCESS;
2652}
2653
2654
2655/** @callback_method_impl{FNCPUMWRMSR} */
2656static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyRaplPowerUnit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2657{
2658 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2659 /* Note! This is documented as read only and except for a Silvermont sample has
2660 always been classified as read only. This is just here to make it compile. */
2661 return VINF_SUCCESS;
2662}
2663
2664
2665/** @callback_method_impl{FNCPUMRDMSR} */
2666static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyPkgCnIrtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2667{
2668 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2669 /** @todo intel power management. */
2670 *puValue = 0;
2671 return VINF_SUCCESS;
2672}
2673
2674
2675/** @callback_method_impl{FNCPUMWRMSR} */
2676static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyPkgCnIrtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2677{
2678 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2679 /** @todo intel power management. */
2680 return VINF_SUCCESS;
2681}
2682
2683
2684/** @callback_method_impl{FNCPUMRDMSR} */
2685static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyPkgC2Residency(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2686{
2687 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2688 /** @todo intel power management. */
2689 *puValue = 0;
2690 return VINF_SUCCESS;
2691}
2692
2693
2694/** @callback_method_impl{FNCPUMWRMSR} */
2695static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyPkgC2Residency(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2696{
2697 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2698 /* Note! This is documented as read only and except for a Silvermont sample has
2699 always been classified as read only. This is just here to make it compile. */
2700 return VINF_SUCCESS;
2701}
2702
2703
2704/** @callback_method_impl{FNCPUMRDMSR} */
2705static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2706{
2707 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2708 /** @todo intel RAPL. */
2709 *puValue = 0;
2710 return VINF_SUCCESS;
2711}
2712
2713
2714/** @callback_method_impl{FNCPUMWRMSR} */
2715static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPkgPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2716{
2717 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2718 /** @todo intel RAPL. */
2719 return VINF_SUCCESS;
2720}
2721
2722
2723/** @callback_method_impl{FNCPUMRDMSR} */
2724static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgEnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2725{
2726 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2727 /** @todo intel power management. */
2728 *puValue = 0;
2729 return VINF_SUCCESS;
2730}
2731
2732
2733/** @callback_method_impl{FNCPUMRDMSR} */
2734static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgPerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2735{
2736 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2737 /** @todo intel power management. */
2738 *puValue = 0;
2739 return VINF_SUCCESS;
2740}
2741
2742
2743/** @callback_method_impl{FNCPUMRDMSR} */
2744static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgPowerInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2745{
2746 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2747 /** @todo intel power management. */
2748 *puValue = 0;
2749 return VINF_SUCCESS;
2750}
2751
2752
2753/** @callback_method_impl{FNCPUMRDMSR} */
2754static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2755{
2756 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2757 /** @todo intel RAPL. */
2758 *puValue = 0;
2759 return VINF_SUCCESS;
2760}
2761
2762
2763/** @callback_method_impl{FNCPUMWRMSR} */
2764static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplDramPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2765{
2766 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2767 /** @todo intel RAPL. */
2768 return VINF_SUCCESS;
2769}
2770
2771
2772/** @callback_method_impl{FNCPUMRDMSR} */
2773static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramEnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2774{
2775 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2776 /** @todo intel power management. */
2777 *puValue = 0;
2778 return VINF_SUCCESS;
2779}
2780
2781
2782/** @callback_method_impl{FNCPUMRDMSR} */
2783static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramPerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2784{
2785 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2786 /** @todo intel power management. */
2787 *puValue = 0;
2788 return VINF_SUCCESS;
2789}
2790
2791
2792/** @callback_method_impl{FNCPUMRDMSR} */
2793static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramPowerInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2794{
2795 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2796 /** @todo intel power management. */
2797 *puValue = 0;
2798 return VINF_SUCCESS;
2799}
2800
2801
2802/** @callback_method_impl{FNCPUMRDMSR} */
2803static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2804{
2805 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2806 /** @todo intel RAPL. */
2807 *puValue = 0;
2808 return VINF_SUCCESS;
2809}
2810
2811
2812/** @callback_method_impl{FNCPUMWRMSR} */
2813static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp0PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2814{
2815 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2816 /** @todo intel RAPL. */
2817 return VINF_SUCCESS;
2818}
2819
2820
2821/** @callback_method_impl{FNCPUMRDMSR} */
2822static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0EnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2823{
2824 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2825 /** @todo intel power management. */
2826 *puValue = 0;
2827 return VINF_SUCCESS;
2828}
2829
2830
2831/** @callback_method_impl{FNCPUMRDMSR} */
2832static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2833{
2834 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2835 /** @todo intel RAPL. */
2836 *puValue = 0;
2837 return VINF_SUCCESS;
2838}
2839
2840
2841/** @callback_method_impl{FNCPUMWRMSR} */
2842static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp0Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2843{
2844 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2845 /** @todo intel RAPL. */
2846 return VINF_SUCCESS;
2847}
2848
2849
2850/** @callback_method_impl{FNCPUMRDMSR} */
2851static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2852{
2853 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2854 /** @todo intel power management. */
2855 *puValue = 0;
2856 return VINF_SUCCESS;
2857}
2858
2859
2860/** @callback_method_impl{FNCPUMRDMSR} */
2861static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp1PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2862{
2863 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2864 /** @todo intel RAPL. */
2865 *puValue = 0;
2866 return VINF_SUCCESS;
2867}
2868
2869
2870/** @callback_method_impl{FNCPUMWRMSR} */
2871static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp1PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2872{
2873 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2874 /** @todo intel RAPL. */
2875 return VINF_SUCCESS;
2876}
2877
2878
2879/** @callback_method_impl{FNCPUMRDMSR} */
2880static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp1EnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2881{
2882 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2883 /** @todo intel power management. */
2884 *puValue = 0;
2885 return VINF_SUCCESS;
2886}
2887
2888
2889/** @callback_method_impl{FNCPUMRDMSR} */
2890static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp1Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2891{
2892 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2893 /** @todo intel RAPL. */
2894 *puValue = 0;
2895 return VINF_SUCCESS;
2896}
2897
2898
2899/** @callback_method_impl{FNCPUMWRMSR} */
2900static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp1Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2901{
2902 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2903 /** @todo intel RAPL. */
2904 return VINF_SUCCESS;
2905}
2906
2907
2908/** @callback_method_impl{FNCPUMRDMSR} */
2909static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpNominal(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2910{
2911 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2912 /** @todo intel power management. */
2913 *puValue = pRange->uValue;
2914 return VINF_SUCCESS;
2915}
2916
2917
2918/** @callback_method_impl{FNCPUMRDMSR} */
2919static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpLevel1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2920{
2921 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2922 /** @todo intel power management. */
2923 *puValue = pRange->uValue;
2924 return VINF_SUCCESS;
2925}
2926
2927
2928/** @callback_method_impl{FNCPUMRDMSR} */
2929static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpLevel2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2930{
2931 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2932 /** @todo intel power management. */
2933 *puValue = pRange->uValue;
2934 return VINF_SUCCESS;
2935}
2936
2937
2938/** @callback_method_impl{FNCPUMRDMSR} */
2939static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2940{
2941 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2942 /** @todo intel power management. */
2943 *puValue = 0;
2944 return VINF_SUCCESS;
2945}
2946
2947
2948/** @callback_method_impl{FNCPUMWRMSR} */
2949static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7IvyConfigTdpControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2950{
2951 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2952 /** @todo intel power management. */
2953 return VINF_SUCCESS;
2954}
2955
2956
2957/** @callback_method_impl{FNCPUMRDMSR} */
2958static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyTurboActivationRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2959{
2960 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2961 /** @todo intel power management. */
2962 *puValue = 0;
2963 return VINF_SUCCESS;
2964}
2965
2966
2967/** @callback_method_impl{FNCPUMWRMSR} */
2968static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7IvyTurboActivationRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2969{
2970 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2971 /** @todo intel power management. */
2972 return VINF_SUCCESS;
2973}
2974
2975
2976/** @callback_method_impl{FNCPUMRDMSR} */
2977static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2978{
2979 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2980 /** @todo uncore msrs. */
2981 *puValue = 0;
2982 return VINF_SUCCESS;
2983}
2984
2985
2986/** @callback_method_impl{FNCPUMWRMSR} */
2987static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2988{
2989 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2990 /** @todo uncore msrs. */
2991 return VINF_SUCCESS;
2992}
2993
2994
2995/** @callback_method_impl{FNCPUMRDMSR} */
2996static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2997{
2998 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2999 /** @todo uncore msrs. */
3000 *puValue = 0;
3001 return VINF_SUCCESS;
3002}
3003
3004
3005/** @callback_method_impl{FNCPUMWRMSR} */
3006static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3007{
3008 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3009 /** @todo uncore msrs. */
3010 return VINF_SUCCESS;
3011}
3012
3013
3014/** @callback_method_impl{FNCPUMRDMSR} */
3015static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3016{
3017 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3018 /** @todo uncore msrs. */
3019 *puValue = 0;
3020 return VINF_SUCCESS;
3021}
3022
3023
3024/** @callback_method_impl{FNCPUMWRMSR} */
3025static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3026{
3027 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3028 /** @todo uncore msrs. */
3029 return VINF_SUCCESS;
3030}
3031
3032
3033/** @callback_method_impl{FNCPUMRDMSR} */
3034static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfFixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3035{
3036 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3037 /** @todo uncore msrs. */
3038 *puValue = 0;
3039 return VINF_SUCCESS;
3040}
3041
3042
3043/** @callback_method_impl{FNCPUMWRMSR} */
3044static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfFixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3045{
3046 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3047 /** @todo uncore msrs. */
3048 return VINF_SUCCESS;
3049}
3050
3051
3052/** @callback_method_impl{FNCPUMRDMSR} */
3053static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfFixedCtr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3054{
3055 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3056 /** @todo uncore msrs. */
3057 *puValue = 0;
3058 return VINF_SUCCESS;
3059}
3060
3061
3062/** @callback_method_impl{FNCPUMWRMSR} */
3063static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfFixedCtr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3064{
3065 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3066 /** @todo uncore msrs. */
3067 return VINF_SUCCESS;
3068}
3069
3070
3071/** @callback_method_impl{FNCPUMRDMSR} */
3072static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncCBoxConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3073{
3074 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3075 /** @todo uncore msrs. */
3076 *puValue = 0;
3077 return VINF_SUCCESS;
3078}
3079
3080
3081/** @callback_method_impl{FNCPUMRDMSR} */
3082static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncArbPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3083{
3084 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3085 /** @todo uncore msrs. */
3086 *puValue = 0;
3087 return VINF_SUCCESS;
3088}
3089
3090
3091/** @callback_method_impl{FNCPUMWRMSR} */
3092static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncArbPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3093{
3094 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3095 /** @todo uncore msrs. */
3096 return VINF_SUCCESS;
3097}
3098
3099
3100/** @callback_method_impl{FNCPUMRDMSR} */
3101static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncArbPerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3102{
3103 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3104 /** @todo uncore msrs. */
3105 *puValue = 0;
3106 return VINF_SUCCESS;
3107}
3108
3109
3110/** @callback_method_impl{FNCPUMWRMSR} */
3111static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncArbPerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3112{
3113 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3114 /** @todo uncore msrs. */
3115 return VINF_SUCCESS;
3116}
3117
3118
3119/** @callback_method_impl{FNCPUMRDMSR} */
3120static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SmiCount(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3121{
3122 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3123
3124 /*
3125 * 31:0 is SMI count (read only), 63:32 reserved.
3126 * Since we don't do SMI, the count is always zero.
3127 */
3128 *puValue = 0;
3129 return VINF_SUCCESS;
3130}
3131
3132
3133/** @callback_method_impl{FNCPUMRDMSR} */
3134static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore2EmttmCrTablesN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3135{
3136 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3137 /** @todo implement enhanced multi thread termal monitoring? */
3138 *puValue = pRange->uValue;
3139 return VINF_SUCCESS;
3140}
3141
3142
3143/** @callback_method_impl{FNCPUMWRMSR} */
3144static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore2EmttmCrTablesN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3145{
3146 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3147 /** @todo implement enhanced multi thread termal monitoring? */
3148 return VINF_SUCCESS;
3149}
3150
3151
3152/** @callback_method_impl{FNCPUMRDMSR} */
3153static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore2SmmCStMiscInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3154{
3155 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3156 /** @todo SMM & C-states? */
3157 *puValue = 0;
3158 return VINF_SUCCESS;
3159}
3160
3161
3162/** @callback_method_impl{FNCPUMWRMSR} */
3163static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore2SmmCStMiscInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3164{
3165 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3166 /** @todo SMM & C-states? */
3167 return VINF_SUCCESS;
3168}
3169
3170
3171/** @callback_method_impl{FNCPUMRDMSR} */
3172static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore1ExtConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3173{
3174 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3175 /** @todo Core1&2 EXT_CONFIG (whatever that is)? */
3176 *puValue = 0;
3177 return VINF_SUCCESS;
3178}
3179
3180
3181/** @callback_method_impl{FNCPUMWRMSR} */
3182static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore1ExtConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3183{
3184 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3185 /** @todo Core1&2 EXT_CONFIG (whatever that is)? */
3186 return VINF_SUCCESS;
3187}
3188
3189
3190/** @callback_method_impl{FNCPUMRDMSR} */
3191static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore1DtsCalControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3192{
3193 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3194 /** @todo Core1&2(?) DTS_CAL_CTRL (whatever that is)? */
3195 *puValue = 0;
3196 return VINF_SUCCESS;
3197}
3198
3199
3200/** @callback_method_impl{FNCPUMWRMSR} */
3201static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore1DtsCalControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3202{
3203 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3204 /** @todo Core1&2(?) DTS_CAL_CTRL (whatever that is)? */
3205 return VINF_SUCCESS;
3206}
3207
3208
3209/** @callback_method_impl{FNCPUMRDMSR} */
3210static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore2PeciControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3211{
3212 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3213 /** @todo Core2+ platform environment control interface control register? */
3214 *puValue = 0;
3215 return VINF_SUCCESS;
3216}
3217
3218
3219/** @callback_method_impl{FNCPUMWRMSR} */
3220static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore2PeciControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3221{
3222 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3223 /** @todo Core2+ platform environment control interface control register? */
3224 return VINF_SUCCESS;
3225}
3226
3227
3228/** @callback_method_impl{FNCPUMRDMSR} */
3229static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelAtSilvCoreC1Recidency(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3230{
3231 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3232 *puValue = 0;
3233 return VINF_SUCCESS;
3234}
3235
3236
3237/*
3238 * Multiple vendor P6 MSRs.
3239 * Multiple vendor P6 MSRs.
3240 * Multiple vendor P6 MSRs.
3241 *
3242 * These MSRs were introduced with the P6 but not elevated to architectural
3243 * MSRs, despite other vendors implementing them.
3244 */
3245
3246
3247/** @callback_method_impl{FNCPUMRDMSR} */
3248static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastBranchFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3249{
3250 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3251 /* AMD seems to just record RIP, while intel claims to record RIP+CS.BASE
3252 if I read the docs correctly, thus the need for separate functions. */
3253 /** @todo implement last branch records. */
3254 *puValue = 0;
3255 return VINF_SUCCESS;
3256}
3257
3258
3259/** @callback_method_impl{FNCPUMRDMSR} */
3260static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastBranchToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3261{
3262 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3263 /** @todo implement last branch records. */
3264 *puValue = 0;
3265 return VINF_SUCCESS;
3266}
3267
3268
3269/** @callback_method_impl{FNCPUMRDMSR} */
3270static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastIntFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3271{
3272 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3273 /** @todo implement last exception records. */
3274 *puValue = 0;
3275 return VINF_SUCCESS;
3276}
3277
3278
3279/** @callback_method_impl{FNCPUMWRMSR} */
3280static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_P6LastIntFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3281{
3282 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3283 /** @todo implement last exception records. */
3284 /* Note! On many CPUs, the high bit of the 0x000001dd register is always writable, even when the result is
3285 a non-cannonical address. */
3286 return VINF_SUCCESS;
3287}
3288
3289
3290/** @callback_method_impl{FNCPUMRDMSR} */
3291static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastIntToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3292{
3293 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3294 /** @todo implement last exception records. */
3295 *puValue = 0;
3296 return VINF_SUCCESS;
3297}
3298
3299
3300/** @callback_method_impl{FNCPUMWRMSR} */
3301static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_P6LastIntToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3302{
3303 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3304 /** @todo implement last exception records. */
3305 return VINF_SUCCESS;
3306}
3307
3308
3309
3310/*
3311 * AMD specific
3312 * AMD specific
3313 * AMD specific
3314 */
3315
3316
3317/** @callback_method_impl{FNCPUMRDMSR} */
3318static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hTscRate(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3319{
3320 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3321 /** @todo Implement TscRateMsr */
3322 *puValue = RT_MAKE_U64(0, 1); /* 1.0 = reset value. */
3323 return VINF_SUCCESS;
3324}
3325
3326
3327/** @callback_method_impl{FNCPUMWRMSR} */
3328static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hTscRate(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3329{
3330 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3331 /** @todo Implement TscRateMsr */
3332 return VINF_SUCCESS;
3333}
3334
3335
3336/** @callback_method_impl{FNCPUMRDMSR} */
3337static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hLwpCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3338{
3339 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3340 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
3341 /* Note: Only listes in BKDG for Family 15H. */
3342 *puValue = 0;
3343 return VINF_SUCCESS;
3344}
3345
3346
3347/** @callback_method_impl{FNCPUMWRMSR} */
3348static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hLwpCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3349{
3350 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3351 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
3352 return VINF_SUCCESS;
3353}
3354
3355
3356/** @callback_method_impl{FNCPUMRDMSR} */
3357static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hLwpCbAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3358{
3359 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3360 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
3361 /* Note: Only listes in BKDG for Family 15H. */
3362 *puValue = 0;
3363 return VINF_SUCCESS;
3364}
3365
3366
3367/** @callback_method_impl{FNCPUMWRMSR} */
3368static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hLwpCbAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3369{
3370 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3371 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
3372 return VINF_SUCCESS;
3373}
3374
3375
3376/** @callback_method_impl{FNCPUMRDMSR} */
3377static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hMc4MiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3378{
3379 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3380 /** @todo machine check. */
3381 *puValue = 0;
3382 return VINF_SUCCESS;
3383}
3384
3385
3386/** @callback_method_impl{FNCPUMWRMSR} */
3387static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hMc4MiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3388{
3389 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3390 /** @todo machine check. */
3391 return VINF_SUCCESS;
3392}
3393
3394
3395/** @callback_method_impl{FNCPUMRDMSR} */
3396static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8PerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3397{
3398 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3399 /** @todo AMD performance events. */
3400 *puValue = 0;
3401 return VINF_SUCCESS;
3402}
3403
3404
3405/** @callback_method_impl{FNCPUMWRMSR} */
3406static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8PerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3407{
3408 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3409 /** @todo AMD performance events. */
3410 return VINF_SUCCESS;
3411}
3412
3413
3414/** @callback_method_impl{FNCPUMRDMSR} */
3415static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8PerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3416{
3417 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3418 /** @todo AMD performance events. */
3419 *puValue = 0;
3420 return VINF_SUCCESS;
3421}
3422
3423
3424/** @callback_method_impl{FNCPUMWRMSR} */
3425static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8PerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3426{
3427 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3428 /** @todo AMD performance events. */
3429 return VINF_SUCCESS;
3430}
3431
3432
3433/** @callback_method_impl{FNCPUMRDMSR} */
3434static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SysCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3435{
3436 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3437 /** @todo AMD SYS_CFG */
3438 *puValue = pRange->uValue;
3439 return VINF_SUCCESS;
3440}
3441
3442
3443/** @callback_method_impl{FNCPUMWRMSR} */
3444static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SysCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3445{
3446 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3447 /** @todo AMD SYS_CFG */
3448 return VINF_SUCCESS;
3449}
3450
3451
3452/** @callback_method_impl{FNCPUMRDMSR} */
3453static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8HwCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3454{
3455 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3456 /** @todo AMD HW_CFG */
3457 *puValue = 0;
3458 return VINF_SUCCESS;
3459}
3460
3461
3462/** @callback_method_impl{FNCPUMWRMSR} */
3463static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8HwCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3464{
3465 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3466 /** @todo AMD HW_CFG */
3467 return VINF_SUCCESS;
3468}
3469
3470
3471/** @callback_method_impl{FNCPUMRDMSR} */
3472static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IorrBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3473{
3474 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3475 /** @todo AMD IorrMask/IorrBase */
3476 *puValue = 0;
3477 return VINF_SUCCESS;
3478}
3479
3480
3481/** @callback_method_impl{FNCPUMWRMSR} */
3482static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IorrBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3483{
3484 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3485 /** @todo AMD IorrMask/IorrBase */
3486 return VINF_SUCCESS;
3487}
3488
3489
3490/** @callback_method_impl{FNCPUMRDMSR} */
3491static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IorrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3492{
3493 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3494 /** @todo AMD IorrMask/IorrBase */
3495 *puValue = 0;
3496 return VINF_SUCCESS;
3497}
3498
3499
3500/** @callback_method_impl{FNCPUMWRMSR} */
3501static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IorrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3502{
3503 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3504 /** @todo AMD IorrMask/IorrBase */
3505 return VINF_SUCCESS;
3506}
3507
3508
3509/** @callback_method_impl{FNCPUMRDMSR} */
3510static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8TopOfMemN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3511{
3512 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3513 *puValue = 0;
3514 /** @todo return 4GB - RamHoleSize here for TOPMEM. Figure out what to return
3515 * for TOPMEM2. */
3516 //if (pRange->uValue == 0)
3517 // *puValue = _4G - RamHoleSize;
3518 return VINF_SUCCESS;
3519}
3520
3521
3522/** @callback_method_impl{FNCPUMWRMSR} */
3523static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8TopOfMemN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3524{
3525 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3526 /** @todo AMD TOPMEM and TOPMEM2/TOM2. */
3527 return VINF_SUCCESS;
3528}
3529
3530
3531/** @callback_method_impl{FNCPUMRDMSR} */
3532static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8NbCfg1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3533{
3534 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3535 /** @todo AMD NB_CFG1 */
3536 *puValue = 0;
3537 return VINF_SUCCESS;
3538}
3539
3540
3541/** @callback_method_impl{FNCPUMWRMSR} */
3542static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8NbCfg1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3543{
3544 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3545 /** @todo AMD NB_CFG1 */
3546 return VINF_SUCCESS;
3547}
3548
3549
3550/** @callback_method_impl{FNCPUMRDMSR} */
3551static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8McXcptRedir(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3552{
3553 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3554 /** @todo machine check. */
3555 *puValue = 0;
3556 return VINF_SUCCESS;
3557}
3558
3559
3560/** @callback_method_impl{FNCPUMWRMSR} */
3561static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8McXcptRedir(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3562{
3563 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3564 /** @todo machine check. */
3565 return VINF_SUCCESS;
3566}
3567
3568
3569/** @callback_method_impl{FNCPUMRDMSR} */
3570static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuNameN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3571{
3572 RT_NOREF_PV(idMsr);
3573 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), pRange->uValue / 2 + 0x80000001);
3574 if (pLeaf)
3575 {
3576 if (!(pRange->uValue & 1))
3577 *puValue = RT_MAKE_U64(pLeaf->uEax, pLeaf->uEbx);
3578 else
3579 *puValue = RT_MAKE_U64(pLeaf->uEcx, pLeaf->uEdx);
3580 }
3581 else
3582 *puValue = 0;
3583 return VINF_SUCCESS;
3584}
3585
3586
3587/** @callback_method_impl{FNCPUMWRMSR} */
3588static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuNameN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3589{
3590 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3591 /** @todo Remember guest programmed CPU name. */
3592 return VINF_SUCCESS;
3593}
3594
3595
3596/** @callback_method_impl{FNCPUMRDMSR} */
3597static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8HwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3598{
3599 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3600 /** @todo AMD HTC. */
3601 *puValue = pRange->uValue;
3602 return VINF_SUCCESS;
3603}
3604
3605
3606/** @callback_method_impl{FNCPUMWRMSR} */
3607static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8HwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3608{
3609 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3610 /** @todo AMD HTC. */
3611 return VINF_SUCCESS;
3612}
3613
3614
3615/** @callback_method_impl{FNCPUMRDMSR} */
3616static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3617{
3618 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3619 /** @todo AMD STC. */
3620 *puValue = 0;
3621 return VINF_SUCCESS;
3622}
3623
3624
3625/** @callback_method_impl{FNCPUMWRMSR} */
3626static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3627{
3628 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3629 /** @todo AMD STC. */
3630 return VINF_SUCCESS;
3631}
3632
3633
3634/** @callback_method_impl{FNCPUMRDMSR} */
3635static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8FidVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3636{
3637 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3638 /** @todo AMD FIDVID_CTL. */
3639 *puValue = pRange->uValue;
3640 return VINF_SUCCESS;
3641}
3642
3643
3644/** @callback_method_impl{FNCPUMWRMSR} */
3645static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8FidVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3646{
3647 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3648 /** @todo AMD FIDVID_CTL. */
3649 return VINF_SUCCESS;
3650}
3651
3652
3653/** @callback_method_impl{FNCPUMRDMSR} */
3654static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8FidVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3655{
3656 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3657 /** @todo AMD FIDVID_STATUS. */
3658 *puValue = pRange->uValue;
3659 return VINF_SUCCESS;
3660}
3661
3662
3663/** @callback_method_impl{FNCPUMRDMSR} */
3664static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8McCtlMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3665{
3666 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3667 /** @todo AMD MC. */
3668 *puValue = 0;
3669 return VINF_SUCCESS;
3670}
3671
3672
3673/** @callback_method_impl{FNCPUMWRMSR} */
3674static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8McCtlMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3675{
3676 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3677 /** @todo AMD MC. */
3678 return VINF_SUCCESS;
3679}
3680
3681
3682/** @callback_method_impl{FNCPUMRDMSR} */
3683static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmiOnIoTrapN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3684{
3685 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3686 /** @todo AMD SMM/SMI and I/O trap. */
3687 *puValue = 0;
3688 return VINF_SUCCESS;
3689}
3690
3691
3692/** @callback_method_impl{FNCPUMWRMSR} */
3693static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmiOnIoTrapN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3694{
3695 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3696 /** @todo AMD SMM/SMI and I/O trap. */
3697 return VINF_SUCCESS;
3698}
3699
3700
3701/** @callback_method_impl{FNCPUMRDMSR} */
3702static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmiOnIoTrapCtlSts(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3703{
3704 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3705 /** @todo AMD SMM/SMI and I/O trap. */
3706 *puValue = 0;
3707 return VINF_SUCCESS;
3708}
3709
3710
3711/** @callback_method_impl{FNCPUMWRMSR} */
3712static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmiOnIoTrapCtlSts(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3713{
3714 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3715 /** @todo AMD SMM/SMI and I/O trap. */
3716 return VINF_SUCCESS;
3717}
3718
3719
3720/** @callback_method_impl{FNCPUMRDMSR} */
3721static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IntPendingMessage(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3722{
3723 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3724 /** @todo Interrupt pending message. */
3725 *puValue = 0;
3726 return VINF_SUCCESS;
3727}
3728
3729
3730/** @callback_method_impl{FNCPUMWRMSR} */
3731static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IntPendingMessage(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3732{
3733 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3734 /** @todo Interrupt pending message. */
3735 return VINF_SUCCESS;
3736}
3737
3738
3739/** @callback_method_impl{FNCPUMRDMSR} */
3740static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmiTriggerIoCycle(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3741{
3742 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3743 /** @todo AMD SMM/SMI and trigger I/O cycle. */
3744 *puValue = 0;
3745 return VINF_SUCCESS;
3746}
3747
3748
3749/** @callback_method_impl{FNCPUMWRMSR} */
3750static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmiTriggerIoCycle(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3751{
3752 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3753 /** @todo AMD SMM/SMI and trigger I/O cycle. */
3754 return VINF_SUCCESS;
3755}
3756
3757
3758/** @callback_method_impl{FNCPUMRDMSR} */
3759static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hMmioCfgBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3760{
3761 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3762 /** @todo AMD MMIO Configuration base address. */
3763 *puValue = 0;
3764 return VINF_SUCCESS;
3765}
3766
3767
3768/** @callback_method_impl{FNCPUMWRMSR} */
3769static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hMmioCfgBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3770{
3771 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3772 /** @todo AMD MMIO Configuration base address. */
3773 return VINF_SUCCESS;
3774}
3775
3776
3777/** @callback_method_impl{FNCPUMRDMSR} */
3778static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hTrapCtlMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3779{
3780 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3781 /** @todo AMD 0xc0010059. */
3782 *puValue = 0;
3783 return VINF_SUCCESS;
3784}
3785
3786
3787/** @callback_method_impl{FNCPUMWRMSR} */
3788static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hTrapCtlMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3789{
3790 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3791 /** @todo AMD 0xc0010059. */
3792 return VINF_SUCCESS;
3793}
3794
3795
3796/** @callback_method_impl{FNCPUMRDMSR} */
3797static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateCurLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3798{
3799 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3800 /** @todo AMD P-states. */
3801 *puValue = pRange->uValue;
3802 return VINF_SUCCESS;
3803}
3804
3805
3806/** @callback_method_impl{FNCPUMRDMSR} */
3807static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3808{
3809 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3810 /** @todo AMD P-states. */
3811 *puValue = pRange->uValue;
3812 return VINF_SUCCESS;
3813}
3814
3815
3816/** @callback_method_impl{FNCPUMWRMSR} */
3817static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hPStateControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3818{
3819 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3820 /** @todo AMD P-states. */
3821 return VINF_SUCCESS;
3822}
3823
3824
3825/** @callback_method_impl{FNCPUMRDMSR} */
3826static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3827{
3828 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3829 /** @todo AMD P-states. */
3830 *puValue = pRange->uValue;
3831 return VINF_SUCCESS;
3832}
3833
3834
3835/** @callback_method_impl{FNCPUMWRMSR} */
3836static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hPStateStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3837{
3838 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3839 /** @todo AMD P-states. */
3840 return VINF_SUCCESS;
3841}
3842
3843
3844/** @callback_method_impl{FNCPUMRDMSR} */
3845static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3846{
3847 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3848 /** @todo AMD P-states. */
3849 *puValue = pRange->uValue;
3850 return VINF_SUCCESS;
3851}
3852
3853
3854/** @callback_method_impl{FNCPUMWRMSR} */
3855static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hPStateN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3856{
3857 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3858 /** @todo AMD P-states. */
3859 return VINF_SUCCESS;
3860}
3861
3862
3863/** @callback_method_impl{FNCPUMRDMSR} */
3864static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCofVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3865{
3866 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3867 /** @todo AMD P-states. */
3868 *puValue = pRange->uValue;
3869 return VINF_SUCCESS;
3870}
3871
3872
3873/** @callback_method_impl{FNCPUMWRMSR} */
3874static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCofVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3875{
3876 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3877 /** @todo AMD P-states. */
3878 return VINF_SUCCESS;
3879}
3880
3881
3882/** @callback_method_impl{FNCPUMRDMSR} */
3883static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCofVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3884{
3885 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3886 /** @todo AMD P-states. */
3887 *puValue = pRange->uValue;
3888 return VINF_SUCCESS;
3889}
3890
3891
3892/** @callback_method_impl{FNCPUMWRMSR} */
3893static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCofVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3894{
3895 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3896 /* Note! Writing 0 seems to not GP, not sure if it does anything to the value... */
3897 /** @todo AMD P-states. */
3898 return VINF_SUCCESS;
3899}
3900
3901
3902/** @callback_method_impl{FNCPUMRDMSR} */
3903static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCStateIoBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3904{
3905 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3906 /** @todo AMD C-states. */
3907 *puValue = 0;
3908 return VINF_SUCCESS;
3909}
3910
3911
3912/** @callback_method_impl{FNCPUMWRMSR} */
3913static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCStateIoBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3914{
3915 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3916 /** @todo AMD C-states. */
3917 return VINF_SUCCESS;
3918}
3919
3920
3921/** @callback_method_impl{FNCPUMRDMSR} */
3922static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCpuWatchdogTimer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3923{
3924 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3925 /** @todo AMD machine checks. */
3926 *puValue = 0;
3927 return VINF_SUCCESS;
3928}
3929
3930
3931/** @callback_method_impl{FNCPUMWRMSR} */
3932static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCpuWatchdogTimer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3933{
3934 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3935 /** @todo AMD machine checks. */
3936 return VINF_SUCCESS;
3937}
3938
3939
3940/** @callback_method_impl{FNCPUMRDMSR} */
3941static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3942{
3943 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3944 /** @todo AMD SMM. */
3945 *puValue = 0;
3946 return VINF_SUCCESS;
3947}
3948
3949
3950/** @callback_method_impl{FNCPUMWRMSR} */
3951static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3952{
3953 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3954 /** @todo AMD SMM. */
3955 return VINF_SUCCESS;
3956}
3957
3958
3959/** @callback_method_impl{FNCPUMRDMSR} */
3960static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3961{
3962 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3963 /** @todo AMD SMM. */
3964 *puValue = 0;
3965 return VINF_SUCCESS;
3966}
3967
3968
3969/** @callback_method_impl{FNCPUMWRMSR} */
3970static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3971{
3972 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3973 /** @todo AMD SMM. */
3974 return VINF_SUCCESS;
3975}
3976
3977
3978
3979/** @callback_method_impl{FNCPUMRDMSR} */
3980static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3981{
3982 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3983 /** @todo AMD SMM. */
3984 *puValue = 0;
3985 return VINF_SUCCESS;
3986}
3987
3988
3989/** @callback_method_impl{FNCPUMWRMSR} */
3990static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3991{
3992 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3993 /** @todo AMD SMM. */
3994 return VINF_SUCCESS;
3995}
3996
3997
3998/** @callback_method_impl{FNCPUMRDMSR} */
3999static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8VmCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4000{
4001 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4002 PVM pVM = pVCpu->CTX_SUFF(pVM);
4003 if (pVM->cpum.s.GuestFeatures.fSvm)
4004 *puValue = MSR_K8_VM_CR_LOCK;
4005 else
4006 *puValue = 0;
4007 return VINF_SUCCESS;
4008}
4009
4010
4011/** @callback_method_impl{FNCPUMWRMSR} */
4012static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8VmCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4013{
4014 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
4015 PVM pVM = pVCpu->CTX_SUFF(pVM);
4016 if (pVM->cpum.s.GuestFeatures.fSvm)
4017 {
4018 /* Silently ignore writes to LOCK and SVM_DISABLE bit when the LOCK bit is set (see cpumMsrRd_AmdK8VmCr). */
4019 if (uValue & (MSR_K8_VM_CR_DPD | MSR_K8_VM_CR_R_INIT | MSR_K8_VM_CR_DIS_A20M))
4020 return VERR_CPUM_RAISE_GP_0;
4021 return VINF_SUCCESS;
4022 }
4023 return VERR_CPUM_RAISE_GP_0;
4024}
4025
4026
4027/** @callback_method_impl{FNCPUMRDMSR} */
4028static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IgnNe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4029{
4030 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4031 /** @todo AMD IGNNE\# control. */
4032 *puValue = 0;
4033 return VINF_SUCCESS;
4034}
4035
4036
4037/** @callback_method_impl{FNCPUMWRMSR} */
4038static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IgnNe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4039{
4040 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4041 /** @todo AMD IGNNE\# control. */
4042 return VINF_SUCCESS;
4043}
4044
4045
4046/** @callback_method_impl{FNCPUMRDMSR} */
4047static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4048{
4049 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4050 /** @todo AMD SMM. */
4051 *puValue = 0;
4052 return VINF_SUCCESS;
4053}
4054
4055
4056/** @callback_method_impl{FNCPUMWRMSR} */
4057static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4058{
4059 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4060 /** @todo AMD SMM. */
4061 return VINF_SUCCESS;
4062}
4063
4064
4065/** @callback_method_impl{FNCPUMRDMSR} */
4066static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8VmHSavePa(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4067{
4068 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4069 *puValue = pVCpu->cpum.s.Guest.hwvirt.svm.uMsrHSavePa;
4070 return VINF_SUCCESS;
4071}
4072
4073
4074/** @callback_method_impl{FNCPUMWRMSR} */
4075static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8VmHSavePa(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4076{
4077 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
4078 if (uValue & UINT64_C(0xfff))
4079 {
4080 Log(("CPUM: Invalid setting of low 12 bits set writing host-state save area MSR %#x: %#llx\n", idMsr, uValue));
4081 return VERR_CPUM_RAISE_GP_0;
4082 }
4083
4084 uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
4085 if (fInvPhysMask & uValue)
4086 {
4087 Log(("CPUM: Invalid physical address bits set writing host-state save area MSR %#x: %#llx (%#llx)\n",
4088 idMsr, uValue, uValue & fInvPhysMask));
4089 return VERR_CPUM_RAISE_GP_0;
4090 }
4091
4092 pVCpu->cpum.s.Guest.hwvirt.svm.uMsrHSavePa = uValue;
4093 return VINF_SUCCESS;
4094}
4095
4096
4097/** @callback_method_impl{FNCPUMRDMSR} */
4098static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hVmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4099{
4100 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4101 /** @todo AMD SVM. */
4102 *puValue = 0; /* RAZ */
4103 return VINF_SUCCESS;
4104}
4105
4106
4107/** @callback_method_impl{FNCPUMWRMSR} */
4108static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hVmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4109{
4110 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4111 /** @todo AMD SVM. */
4112 return VINF_SUCCESS;
4113}
4114
4115
4116/** @callback_method_impl{FNCPUMRDMSR} */
4117static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hSmmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4118{
4119 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4120 /** @todo AMD SMM. */
4121 *puValue = 0; /* RAZ */
4122 return VINF_SUCCESS;
4123}
4124
4125
4126/** @callback_method_impl{FNCPUMWRMSR} */
4127static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hSmmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4128{
4129 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4130 /** @todo AMD SMM. */
4131 return VINF_SUCCESS;
4132}
4133
4134
4135/** @callback_method_impl{FNCPUMRDMSR} */
4136static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hLocalSmiStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4137{
4138 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4139 /** @todo AMD SMM/SMI. */
4140 *puValue = 0;
4141 return VINF_SUCCESS;
4142}
4143
4144
4145/** @callback_method_impl{FNCPUMWRMSR} */
4146static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hLocalSmiStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4147{
4148 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4149 /** @todo AMD SMM/SMI. */
4150 return VINF_SUCCESS;
4151}
4152
4153
4154/** @callback_method_impl{FNCPUMRDMSR} */
4155static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hOsVisWrkIdLength(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4156{
4157 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
4158 /** @todo AMD OS visible workaround. */
4159 *puValue = pRange->uValue;
4160 return VINF_SUCCESS;
4161}
4162
4163
4164/** @callback_method_impl{FNCPUMWRMSR} */
4165static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hOsVisWrkIdLength(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4166{
4167 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4168 /** @todo AMD OS visible workaround. */
4169 return VINF_SUCCESS;
4170}
4171
4172
4173/** @callback_method_impl{FNCPUMRDMSR} */
4174static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hOsVisWrkStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4175{
4176 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4177 /** @todo AMD OS visible workaround. */
4178 *puValue = 0;
4179 return VINF_SUCCESS;
4180}
4181
4182
4183/** @callback_method_impl{FNCPUMWRMSR} */
4184static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hOsVisWrkStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4185{
4186 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4187 /** @todo AMD OS visible workaround. */
4188 return VINF_SUCCESS;
4189}
4190
4191
4192/** @callback_method_impl{FNCPUMRDMSR} */
4193static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam16hL2IPerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4194{
4195 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4196 /** @todo AMD L2I performance counters. */
4197 *puValue = 0;
4198 return VINF_SUCCESS;
4199}
4200
4201
4202/** @callback_method_impl{FNCPUMWRMSR} */
4203static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam16hL2IPerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4204{
4205 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4206 /** @todo AMD L2I performance counters. */
4207 return VINF_SUCCESS;
4208}
4209
4210
4211/** @callback_method_impl{FNCPUMRDMSR} */
4212static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam16hL2IPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4213{
4214 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4215 /** @todo AMD L2I performance counters. */
4216 *puValue = 0;
4217 return VINF_SUCCESS;
4218}
4219
4220
4221/** @callback_method_impl{FNCPUMWRMSR} */
4222static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam16hL2IPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4223{
4224 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4225 /** @todo AMD L2I performance counters. */
4226 return VINF_SUCCESS;
4227}
4228
4229
4230/** @callback_method_impl{FNCPUMRDMSR} */
4231static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hNorthbridgePerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4232{
4233 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4234 /** @todo AMD Northbridge performance counters. */
4235 *puValue = 0;
4236 return VINF_SUCCESS;
4237}
4238
4239
4240/** @callback_method_impl{FNCPUMWRMSR} */
4241static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hNorthbridgePerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4242{
4243 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4244 /** @todo AMD Northbridge performance counters. */
4245 return VINF_SUCCESS;
4246}
4247
4248
4249/** @callback_method_impl{FNCPUMRDMSR} */
4250static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hNorthbridgePerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4251{
4252 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4253 /** @todo AMD Northbridge performance counters. */
4254 *puValue = 0;
4255 return VINF_SUCCESS;
4256}
4257
4258
4259/** @callback_method_impl{FNCPUMWRMSR} */
4260static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hNorthbridgePerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4261{
4262 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4263 /** @todo AMD Northbridge performance counters. */
4264 return VINF_SUCCESS;
4265}
4266
4267
4268/** @callback_method_impl{FNCPUMRDMSR} */
4269static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7MicrocodeCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4270{
4271 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4272 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4273 * cpus. Need to be explored and verify K7 presence. */
4274 /** @todo Undocumented register only seen mentioned in fam15h erratum \#608. */
4275 *puValue = pRange->uValue;
4276 return VINF_SUCCESS;
4277}
4278
4279
4280/** @callback_method_impl{FNCPUMWRMSR} */
4281static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7MicrocodeCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4282{
4283 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4284 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4285 * cpus. Need to be explored and verify K7 presence. */
4286 /** @todo Undocumented register only seen mentioned in fam15h erratum \#608. */
4287 return VINF_SUCCESS;
4288}
4289
4290
4291/** @callback_method_impl{FNCPUMRDMSR} */
4292static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7ClusterIdMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4293{
4294 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4295 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4296 * cpus. Need to be explored and verify K7 presence. */
4297 /** @todo Undocumented register only seen mentioned in fam16h BKDG r3.00 when
4298 * describing EBL_CR_POWERON. */
4299 *puValue = pRange->uValue;
4300 return VINF_SUCCESS;
4301}
4302
4303
4304/** @callback_method_impl{FNCPUMWRMSR} */
4305static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7ClusterIdMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4306{
4307 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4308 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4309 * cpus. Need to be explored and verify K7 presence. */
4310 /** @todo Undocumented register only seen mentioned in fam16h BKDG r3.00 when
4311 * describing EBL_CR_POWERON. */
4312 return VINF_SUCCESS;
4313}
4314
4315
4316/** @callback_method_impl{FNCPUMRDMSR} */
4317static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlStd07hEbax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4318{
4319 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4320 bool fIgnored;
4321 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafEx(pVCpu->CTX_SUFF(pVM), 0x00000007, 0, &fIgnored);
4322 if (pLeaf)
4323 *puValue = RT_MAKE_U64(pLeaf->uEbx, pLeaf->uEax);
4324 else
4325 *puValue = 0;
4326 return VINF_SUCCESS;
4327}
4328
4329
4330/** @callback_method_impl{FNCPUMWRMSR} */
4331static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlStd07hEbax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4332{
4333 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4334 /** @todo Changing CPUID leaf 7/0. */
4335 return VINF_SUCCESS;
4336}
4337
4338
4339/** @callback_method_impl{FNCPUMRDMSR} */
4340static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlStd06hEcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4341{
4342 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4343 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000006);
4344 if (pLeaf)
4345 *puValue = pLeaf->uEcx;
4346 else
4347 *puValue = 0;
4348 return VINF_SUCCESS;
4349}
4350
4351
4352/** @callback_method_impl{FNCPUMWRMSR} */
4353static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlStd06hEcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4354{
4355 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4356 /** @todo Changing CPUID leaf 6. */
4357 return VINF_SUCCESS;
4358}
4359
4360
4361/** @callback_method_impl{FNCPUMRDMSR} */
4362static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlStd01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4363{
4364 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4365 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000001);
4366 if (pLeaf)
4367 *puValue = RT_MAKE_U64(pLeaf->uEdx, pLeaf->uEcx);
4368 else
4369 *puValue = 0;
4370 return VINF_SUCCESS;
4371}
4372
4373
4374/** @callback_method_impl{FNCPUMWRMSR} */
4375static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlStd01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4376{
4377 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4378 /** @todo Changing CPUID leaf 0x80000001. */
4379 return VINF_SUCCESS;
4380}
4381
4382
4383/** @callback_method_impl{FNCPUMRDMSR} */
4384static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlExt01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4385{
4386 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4387 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x80000001);
4388 if (pLeaf)
4389 *puValue = RT_MAKE_U64(pLeaf->uEdx, pLeaf->uEcx);
4390 else
4391 *puValue = 0;
4392 return VINF_SUCCESS;
4393}
4394
4395
4396/** @callback_method_impl{FNCPUMWRMSR} */
4397static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlExt01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4398{
4399 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4400 /** @todo Changing CPUID leaf 0x80000001. */
4401 return VINF_SUCCESS;
4402}
4403
4404
4405/** @callback_method_impl{FNCPUMRDMSR} */
4406static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8PatchLevel(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4407{
4408 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4409 /** @todo Fake AMD microcode patching. */
4410 *puValue = pRange->uValue;
4411 return VINF_SUCCESS;
4412}
4413
4414
4415/** @callback_method_impl{FNCPUMWRMSR} */
4416static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8PatchLoader(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4417{
4418 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4419 /** @todo Fake AMD microcode patching. */
4420 return VINF_SUCCESS;
4421}
4422
4423
4424/** @callback_method_impl{FNCPUMRDMSR} */
4425static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DebugStatusMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4426{
4427 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4428 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4429 * cpus. Need to be explored and verify K7 presence. */
4430 /** @todo undocumented */
4431 *puValue = 0;
4432 return VINF_SUCCESS;
4433}
4434
4435
4436/** @callback_method_impl{FNCPUMWRMSR} */
4437static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DebugStatusMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4438{
4439 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4440 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4441 * cpus. Need to be explored and verify K7 presence. */
4442 /** @todo undocumented */
4443 return VINF_SUCCESS;
4444}
4445
4446
4447/** @callback_method_impl{FNCPUMRDMSR} */
4448static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BHTraceBaseMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4449{
4450 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4451 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4452 * cpus. Need to be explored and verify K7 presence. */
4453 /** @todo undocumented */
4454 *puValue = 0;
4455 return VINF_SUCCESS;
4456}
4457
4458
4459/** @callback_method_impl{FNCPUMWRMSR} */
4460static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BHTraceBaseMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4461{
4462 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4463 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4464 * cpus. Need to be explored and verify K7 presence. */
4465 /** @todo undocumented */
4466 return VINF_SUCCESS;
4467}
4468
4469
4470/** @callback_method_impl{FNCPUMRDMSR} */
4471static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BHTracePtrMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4472{
4473 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4474 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4475 * cpus. Need to be explored and verify K7 presence. */
4476 /** @todo undocumented */
4477 *puValue = 0;
4478 return VINF_SUCCESS;
4479}
4480
4481
4482/** @callback_method_impl{FNCPUMWRMSR} */
4483static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BHTracePtrMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4484{
4485 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4486 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4487 * cpus. Need to be explored and verify K7 presence. */
4488 /** @todo undocumented */
4489 return VINF_SUCCESS;
4490}
4491
4492
4493/** @callback_method_impl{FNCPUMRDMSR} */
4494static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BHTraceLimitMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4495{
4496 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4497 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4498 * cpus. Need to be explored and verify K7 presence. */
4499 /** @todo undocumented */
4500 *puValue = 0;
4501 return VINF_SUCCESS;
4502}
4503
4504
4505/** @callback_method_impl{FNCPUMWRMSR} */
4506static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BHTraceLimitMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4507{
4508 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4509 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4510 * cpus. Need to be explored and verify K7 presence. */
4511 /** @todo undocumented */
4512 return VINF_SUCCESS;
4513}
4514
4515
4516/** @callback_method_impl{FNCPUMRDMSR} */
4517static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7HardwareDebugToolCfgMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4518{
4519 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4520 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4521 * cpus. Need to be explored and verify K7 presence. */
4522 /** @todo undocumented */
4523 *puValue = 0;
4524 return VINF_SUCCESS;
4525}
4526
4527
4528/** @callback_method_impl{FNCPUMWRMSR} */
4529static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7HardwareDebugToolCfgMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4530{
4531 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4532 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4533 * cpus. Need to be explored and verify K7 presence. */
4534 /** @todo undocumented */
4535 return VINF_SUCCESS;
4536}
4537
4538
4539/** @callback_method_impl{FNCPUMRDMSR} */
4540static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7FastFlushCountMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4541{
4542 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4543 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4544 * cpus. Need to be explored and verify K7 presence. */
4545 /** @todo undocumented */
4546 *puValue = 0;
4547 return VINF_SUCCESS;
4548}
4549
4550
4551/** @callback_method_impl{FNCPUMWRMSR} */
4552static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7FastFlushCountMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4553{
4554 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4555 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4556 * cpus. Need to be explored and verify K7 presence. */
4557 /** @todo undocumented */
4558 return VINF_SUCCESS;
4559}
4560
4561
4562/** @callback_method_impl{FNCPUMRDMSR} */
4563static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7NodeId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4564{
4565 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4566 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4567 * cpus. Need to be explored and verify K7 presence. */
4568 /** @todo AMD node ID and bios scratch. */
4569 *puValue = 0; /* nodeid = 0; nodes-per-cpu = 1 */
4570 return VINF_SUCCESS;
4571}
4572
4573
4574/** @callback_method_impl{FNCPUMWRMSR} */
4575static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7NodeId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4576{
4577 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4578 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4579 * cpus. Need to be explored and verify K7 presence. */
4580 /** @todo AMD node ID and bios scratch. */
4581 return VINF_SUCCESS;
4582}
4583
4584
4585/** @callback_method_impl{FNCPUMRDMSR} */
4586static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DrXAddrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4587{
4588 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4589 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4590 * cpus. Need to be explored and verify K7 presence. */
4591 /** @todo AMD DRx address masking (range breakpoints). */
4592 *puValue = 0;
4593 return VINF_SUCCESS;
4594}
4595
4596
4597/** @callback_method_impl{FNCPUMWRMSR} */
4598static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DrXAddrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4599{
4600 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4601 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4602 * cpus. Need to be explored and verify K7 presence. */
4603 /** @todo AMD DRx address masking (range breakpoints). */
4604 return VINF_SUCCESS;
4605}
4606
4607
4608/** @callback_method_impl{FNCPUMRDMSR} */
4609static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7Dr0DataMatchMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4610{
4611 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4612 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4613 * cpus. Need to be explored and verify K7 presence. */
4614 /** @todo AMD undocument debugging features. */
4615 *puValue = 0;
4616 return VINF_SUCCESS;
4617}
4618
4619
4620/** @callback_method_impl{FNCPUMWRMSR} */
4621static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7Dr0DataMatchMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4622{
4623 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4624 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4625 * cpus. Need to be explored and verify K7 presence. */
4626 /** @todo AMD undocument debugging features. */
4627 return VINF_SUCCESS;
4628}
4629
4630
4631/** @callback_method_impl{FNCPUMRDMSR} */
4632static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7Dr0DataMaskMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4633{
4634 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4635 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4636 * cpus. Need to be explored and verify K7 presence. */
4637 /** @todo AMD undocument debugging features. */
4638 *puValue = 0;
4639 return VINF_SUCCESS;
4640}
4641
4642
4643/** @callback_method_impl{FNCPUMWRMSR} */
4644static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7Dr0DataMaskMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4645{
4646 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4647 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4648 * cpus. Need to be explored and verify K7 presence. */
4649 /** @todo AMD undocument debugging features. */
4650 return VINF_SUCCESS;
4651}
4652
4653
4654/** @callback_method_impl{FNCPUMRDMSR} */
4655static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7LoadStoreCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4656{
4657 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4658 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4659 * cpus. Need to be explored and verify K7 presence. */
4660 /** @todo AMD load-store config. */
4661 *puValue = 0;
4662 return VINF_SUCCESS;
4663}
4664
4665
4666/** @callback_method_impl{FNCPUMWRMSR} */
4667static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7LoadStoreCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4668{
4669 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4670 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4671 * cpus. Need to be explored and verify K7 presence. */
4672 /** @todo AMD load-store config. */
4673 return VINF_SUCCESS;
4674}
4675
4676
4677/** @callback_method_impl{FNCPUMRDMSR} */
4678static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7InstrCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4679{
4680 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4681 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4682 * cpus. Need to be explored and verify K7 presence. */
4683 /** @todo AMD instruction cache config. */
4684 *puValue = 0;
4685 return VINF_SUCCESS;
4686}
4687
4688
4689/** @callback_method_impl{FNCPUMWRMSR} */
4690static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7InstrCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4691{
4692 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4693 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4694 * cpus. Need to be explored and verify K7 presence. */
4695 /** @todo AMD instruction cache config. */
4696 return VINF_SUCCESS;
4697}
4698
4699
4700/** @callback_method_impl{FNCPUMRDMSR} */
4701static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DataCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4702{
4703 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4704 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4705 * cpus. Need to be explored and verify K7 presence. */
4706 /** @todo AMD data cache config. */
4707 *puValue = 0;
4708 return VINF_SUCCESS;
4709}
4710
4711
4712/** @callback_method_impl{FNCPUMWRMSR} */
4713static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DataCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4714{
4715 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4716 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4717 * cpus. Need to be explored and verify K7 presence. */
4718 /** @todo AMD data cache config. */
4719 return VINF_SUCCESS;
4720}
4721
4722
4723/** @callback_method_impl{FNCPUMRDMSR} */
4724static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BusUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4725{
4726 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4727 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4728 * cpus. Need to be explored and verify K7 presence. */
4729 /** @todo AMD bus unit config. */
4730 *puValue = 0;
4731 return VINF_SUCCESS;
4732}
4733
4734
4735/** @callback_method_impl{FNCPUMWRMSR} */
4736static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BusUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4737{
4738 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4739 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4740 * cpus. Need to be explored and verify K7 presence. */
4741 /** @todo AMD bus unit config. */
4742 return VINF_SUCCESS;
4743}
4744
4745
4746/** @callback_method_impl{FNCPUMRDMSR} */
4747static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DebugCtl2Maybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4748{
4749 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4750 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4751 * cpus. Need to be explored and verify K7 presence. */
4752 /** @todo Undocument AMD debug control register \#2. */
4753 *puValue = 0;
4754 return VINF_SUCCESS;
4755}
4756
4757
4758/** @callback_method_impl{FNCPUMWRMSR} */
4759static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DebugCtl2Maybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4760{
4761 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4762 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4763 * cpus. Need to be explored and verify K7 presence. */
4764 /** @todo Undocument AMD debug control register \#2. */
4765 return VINF_SUCCESS;
4766}
4767
4768
4769/** @callback_method_impl{FNCPUMRDMSR} */
4770static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hFpuCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4771{
4772 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4773 /** @todo AMD FPU config. */
4774 *puValue = 0;
4775 return VINF_SUCCESS;
4776}
4777
4778
4779/** @callback_method_impl{FNCPUMWRMSR} */
4780static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hFpuCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4781{
4782 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4783 /** @todo AMD FPU config. */
4784 return VINF_SUCCESS;
4785}
4786
4787
4788/** @callback_method_impl{FNCPUMRDMSR} */
4789static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hDecoderCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4790{
4791 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4792 /** @todo AMD decoder config. */
4793 *puValue = 0;
4794 return VINF_SUCCESS;
4795}
4796
4797
4798/** @callback_method_impl{FNCPUMWRMSR} */
4799static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hDecoderCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4800{
4801 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4802 /** @todo AMD decoder config. */
4803 return VINF_SUCCESS;
4804}
4805
4806
4807/** @callback_method_impl{FNCPUMRDMSR} */
4808static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hBusUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4809{
4810 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4811 /* Note! 10h and 16h */
4812 /** @todo AMD bus unit config. */
4813 *puValue = 0;
4814 return VINF_SUCCESS;
4815}
4816
4817
4818/** @callback_method_impl{FNCPUMWRMSR} */
4819static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hBusUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4820{
4821 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4822 /* Note! 10h and 16h */
4823 /** @todo AMD bus unit config. */
4824 return VINF_SUCCESS;
4825}
4826
4827
4828/** @callback_method_impl{FNCPUMRDMSR} */
4829static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hCombUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4830{
4831 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4832 /** @todo AMD unit config. */
4833 *puValue = 0;
4834 return VINF_SUCCESS;
4835}
4836
4837
4838/** @callback_method_impl{FNCPUMWRMSR} */
4839static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hCombUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4840{
4841 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4842 /** @todo AMD unit config. */
4843 return VINF_SUCCESS;
4844}
4845
4846
4847/** @callback_method_impl{FNCPUMRDMSR} */
4848static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hCombUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4849{
4850 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4851 /** @todo AMD unit config 2. */
4852 *puValue = 0;
4853 return VINF_SUCCESS;
4854}
4855
4856
4857/** @callback_method_impl{FNCPUMWRMSR} */
4858static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hCombUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4859{
4860 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4861 /** @todo AMD unit config 2. */
4862 return VINF_SUCCESS;
4863}
4864
4865
4866/** @callback_method_impl{FNCPUMRDMSR} */
4867static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hCombUnitCfg3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4868{
4869 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4870 /** @todo AMD combined unit config 3. */
4871 *puValue = 0;
4872 return VINF_SUCCESS;
4873}
4874
4875
4876/** @callback_method_impl{FNCPUMWRMSR} */
4877static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hCombUnitCfg3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4878{
4879 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4880 /** @todo AMD combined unit config 3. */
4881 return VINF_SUCCESS;
4882}
4883
4884
4885/** @callback_method_impl{FNCPUMRDMSR} */
4886static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hExecUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4887{
4888 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4889 /** @todo AMD execution unit config. */
4890 *puValue = 0;
4891 return VINF_SUCCESS;
4892}
4893
4894
4895/** @callback_method_impl{FNCPUMWRMSR} */
4896static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hExecUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4897{
4898 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4899 /** @todo AMD execution unit config. */
4900 return VINF_SUCCESS;
4901}
4902
4903
4904/** @callback_method_impl{FNCPUMRDMSR} */
4905static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hLoadStoreCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4906{
4907 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4908 /** @todo AMD load-store config 2. */
4909 *puValue = 0;
4910 return VINF_SUCCESS;
4911}
4912
4913
4914/** @callback_method_impl{FNCPUMWRMSR} */
4915static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hLoadStoreCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4916{
4917 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4918 /** @todo AMD load-store config 2. */
4919 return VINF_SUCCESS;
4920}
4921
4922
4923/** @callback_method_impl{FNCPUMRDMSR} */
4924static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsFetchCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4925{
4926 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4927 /** @todo AMD IBS. */
4928 *puValue = 0;
4929 return VINF_SUCCESS;
4930}
4931
4932
4933/** @callback_method_impl{FNCPUMWRMSR} */
4934static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsFetchCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4935{
4936 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4937 /** @todo AMD IBS. */
4938 return VINF_SUCCESS;
4939}
4940
4941
4942/** @callback_method_impl{FNCPUMRDMSR} */
4943static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsFetchLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4944{
4945 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4946 /** @todo AMD IBS. */
4947 *puValue = 0;
4948 return VINF_SUCCESS;
4949}
4950
4951
4952/** @callback_method_impl{FNCPUMWRMSR} */
4953static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsFetchLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4954{
4955 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4956 /** @todo AMD IBS. */
4957 return VINF_SUCCESS;
4958}
4959
4960
4961/** @callback_method_impl{FNCPUMRDMSR} */
4962static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsFetchPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4963{
4964 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4965 /** @todo AMD IBS. */
4966 *puValue = 0;
4967 return VINF_SUCCESS;
4968}
4969
4970
4971/** @callback_method_impl{FNCPUMWRMSR} */
4972static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsFetchPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4973{
4974 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4975 /** @todo AMD IBS. */
4976 return VINF_SUCCESS;
4977}
4978
4979
4980/** @callback_method_impl{FNCPUMRDMSR} */
4981static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpExecCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4982{
4983 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4984 /** @todo AMD IBS. */
4985 *puValue = 0;
4986 return VINF_SUCCESS;
4987}
4988
4989
4990/** @callback_method_impl{FNCPUMWRMSR} */
4991static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpExecCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4992{
4993 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4994 /** @todo AMD IBS. */
4995 return VINF_SUCCESS;
4996}
4997
4998
4999/** @callback_method_impl{FNCPUMRDMSR} */
5000static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpRip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
5001{
5002 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
5003 /** @todo AMD IBS. */
5004 *puValue = 0;
5005 return VINF_SUCCESS;
5006}
5007
5008
5009/** @callback_method_impl{FNCPUMWRMSR} */
5010static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpRip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
5011{
5012 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
5013 /** @todo AMD IBS. */
5014 if (!X86_IS_CANONICAL(uValue))
5015 {
5016 Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
5017 return VERR_CPUM_RAISE_GP_0;
5018 }
5019 return VINF_SUCCESS;
5020}
5021
5022
5023/** @callback_method_impl{FNCPUMRDMSR} */
5024static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpData(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
5025{
5026 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
5027 /** @todo AMD IBS. */
5028 *puValue = 0;
5029 return VINF_SUCCESS;
5030}
5031
5032
5033/** @callback_method_impl{FNCPUMWRMSR} */
5034static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpData(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
5035{
5036 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
5037 /** @todo AMD IBS. */
5038 return VINF_SUCCESS;
5039}
5040
5041
5042/** @callback_method_impl{FNCPUMRDMSR} */
5043static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpData2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
5044{
5045 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
5046 /** @todo AMD IBS. */
5047 *puValue = 0;
5048 return VINF_SUCCESS;
5049}
5050
5051
5052/** @callback_method_impl{FNCPUMWRMSR} */
5053static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpData2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
5054{
5055 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
5056 /** @todo AMD IBS. */
5057 return VINF_SUCCESS;
5058}
5059
5060
5061/** @callback_method_impl{FNCPUMRDMSR} */
5062static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpData3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
5063{
5064 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
5065 /** @todo AMD IBS. */
5066 *puValue = 0;
5067 return VINF_SUCCESS;
5068}
5069
5070
5071/** @callback_method_impl{FNCPUMWRMSR} */
5072static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpData3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
5073{
5074 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
5075 /** @todo AMD IBS. */
5076 return VINF_SUCCESS;
5077}
5078
5079
5080/** @callback_method_impl{FNCPUMRDMSR} */
5081static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsDcLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
5082{
5083 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
5084 /** @todo AMD IBS. */
5085 *puValue = 0;
5086 return VINF_SUCCESS;
5087}
5088
5089
5090/** @callback_method_impl{FNCPUMWRMSR} */
5091static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsDcLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
5092{
5093 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
5094 /** @todo AMD IBS. */
5095 if (!X86_IS_CANONICAL(uValue))
5096 {
5097 Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
5098 return VERR_CPUM_RAISE_GP_0;
5099 }
5100 return VINF_SUCCESS;
5101}
5102
5103
5104/** @callback_method_impl{FNCPUMRDMSR} */
5105static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsDcPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
5106{
5107 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
5108 /** @todo AMD IBS. */
5109 *puValue = 0;
5110 return VINF_SUCCESS;
5111}
5112
5113
5114/** @callback_method_impl{FNCPUMWRMSR} */
5115static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsDcPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
5116{
5117 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
5118 /** @todo AMD IBS. */
5119 return VINF_SUCCESS;
5120}
5121
5122
5123/** @callback_method_impl{FNCPUMRDMSR} */
5124static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
5125{
5126 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
5127 /** @todo AMD IBS. */
5128 *puValue = 0;
5129 return VINF_SUCCESS;
5130}
5131
5132
5133/** @callback_method_impl{FNCPUMWRMSR} */
5134static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
5135{
5136 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
5137 /** @todo AMD IBS. */
5138 return VINF_SUCCESS;
5139}
5140
5141
5142/** @callback_method_impl{FNCPUMRDMSR} */
5143static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam14hIbsBrTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
5144{
5145 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
5146 /** @todo AMD IBS. */
5147 *puValue = 0;
5148 return VINF_SUCCESS;
5149}
5150
5151
5152/** @callback_method_impl{FNCPUMWRMSR} */
5153static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam14hIbsBrTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
5154{
5155 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
5156 /** @todo AMD IBS. */
5157 if (!X86_IS_CANONICAL(uValue))
5158 {
5159 Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
5160 return VERR_CPUM_RAISE_GP_0;
5161 }
5162 return VINF_SUCCESS;
5163}
5164
5165
5166
5167/*
5168 * GIM MSRs.
5169 * GIM MSRs.
5170 * GIM MSRs.
5171 */
5172
5173
5174/** @callback_method_impl{FNCPUMRDMSR} */
5175static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Gim(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
5176{
5177#if defined(VBOX_WITH_NESTED_HWVIRT_SVM) || defined(VBOX_WITH_NESTED_HWVIRT_VMX)
5178 /* Raise #GP(0) like a physical CPU would since the nested-hypervisor hasn't intercept these MSRs. */
5179 if ( CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.s.Guest)
5180 || CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.s.Guest))
5181 return VERR_CPUM_RAISE_GP_0;
5182#endif
5183 return GIMReadMsr(pVCpu, idMsr, pRange, puValue);
5184}
5185
5186
5187/** @callback_method_impl{FNCPUMWRMSR} */
5188static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Gim(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
5189{
5190#if defined(VBOX_WITH_NESTED_HWVIRT_SVM) || defined(VBOX_WITH_NESTED_HWVIRT_VMX)
5191 /* Raise #GP(0) like a physical CPU would since the nested-hypervisor hasn't intercept these MSRs. */
5192 if ( CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.s.Guest)
5193 || CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.s.Guest))
5194 return VERR_CPUM_RAISE_GP_0;
5195#endif
5196 return GIMWriteMsr(pVCpu, idMsr, pRange, uValue, uRawValue);
5197}
5198
5199
5200/**
5201 * MSR read function table.
5202 */
5203static const PFNCPUMRDMSR g_aCpumRdMsrFns[kCpumMsrRdFn_End] =
5204{
5205 NULL, /* Invalid */
5206 cpumMsrRd_FixedValue,
5207 NULL, /* Alias */
5208 cpumMsrRd_WriteOnly,
5209 cpumMsrRd_Ia32P5McAddr,
5210 cpumMsrRd_Ia32P5McType,
5211 cpumMsrRd_Ia32TimestampCounter,
5212 cpumMsrRd_Ia32PlatformId,
5213 cpumMsrRd_Ia32ApicBase,
5214 cpumMsrRd_Ia32FeatureControl,
5215 cpumMsrRd_Ia32BiosSignId,
5216 cpumMsrRd_Ia32SmmMonitorCtl,
5217 cpumMsrRd_Ia32PmcN,
5218 cpumMsrRd_Ia32MonitorFilterLineSize,
5219 cpumMsrRd_Ia32MPerf,
5220 cpumMsrRd_Ia32APerf,
5221 cpumMsrRd_Ia32MtrrCap,
5222 cpumMsrRd_Ia32MtrrPhysBaseN,
5223 cpumMsrRd_Ia32MtrrPhysMaskN,
5224 cpumMsrRd_Ia32MtrrFixed,
5225 cpumMsrRd_Ia32MtrrDefType,
5226 cpumMsrRd_Ia32Pat,
5227 cpumMsrRd_Ia32SysEnterCs,
5228 cpumMsrRd_Ia32SysEnterEsp,
5229 cpumMsrRd_Ia32SysEnterEip,
5230 cpumMsrRd_Ia32McgCap,
5231 cpumMsrRd_Ia32McgStatus,
5232 cpumMsrRd_Ia32McgCtl,
5233 cpumMsrRd_Ia32DebugCtl,
5234 cpumMsrRd_Ia32SmrrPhysBase,
5235 cpumMsrRd_Ia32SmrrPhysMask,
5236 cpumMsrRd_Ia32PlatformDcaCap,
5237 cpumMsrRd_Ia32CpuDcaCap,
5238 cpumMsrRd_Ia32Dca0Cap,
5239 cpumMsrRd_Ia32PerfEvtSelN,
5240 cpumMsrRd_Ia32PerfStatus,
5241 cpumMsrRd_Ia32PerfCtl,
5242 cpumMsrRd_Ia32FixedCtrN,
5243 cpumMsrRd_Ia32PerfCapabilities,
5244 cpumMsrRd_Ia32FixedCtrCtrl,
5245 cpumMsrRd_Ia32PerfGlobalStatus,
5246 cpumMsrRd_Ia32PerfGlobalCtrl,
5247 cpumMsrRd_Ia32PerfGlobalOvfCtrl,
5248 cpumMsrRd_Ia32PebsEnable,
5249 cpumMsrRd_Ia32ClockModulation,
5250 cpumMsrRd_Ia32ThermInterrupt,
5251 cpumMsrRd_Ia32ThermStatus,
5252 cpumMsrRd_Ia32Therm2Ctl,
5253 cpumMsrRd_Ia32MiscEnable,
5254 cpumMsrRd_Ia32McCtlStatusAddrMiscN,
5255 cpumMsrRd_Ia32McNCtl2,
5256 cpumMsrRd_Ia32DsArea,
5257 cpumMsrRd_Ia32TscDeadline,
5258 cpumMsrRd_Ia32X2ApicN,
5259 cpumMsrRd_Ia32DebugInterface,
5260 cpumMsrRd_Ia32VmxBasic,
5261 cpumMsrRd_Ia32VmxPinbasedCtls,
5262 cpumMsrRd_Ia32VmxProcbasedCtls,
5263 cpumMsrRd_Ia32VmxExitCtls,
5264 cpumMsrRd_Ia32VmxEntryCtls,
5265 cpumMsrRd_Ia32VmxMisc,
5266 cpumMsrRd_Ia32VmxCr0Fixed0,
5267 cpumMsrRd_Ia32VmxCr0Fixed1,
5268 cpumMsrRd_Ia32VmxCr4Fixed0,
5269 cpumMsrRd_Ia32VmxCr4Fixed1,
5270 cpumMsrRd_Ia32VmxVmcsEnum,
5271 cpumMsrRd_Ia32VmxProcBasedCtls2,
5272 cpumMsrRd_Ia32VmxEptVpidCap,
5273 cpumMsrRd_Ia32VmxTruePinbasedCtls,
5274 cpumMsrRd_Ia32VmxTrueProcbasedCtls,
5275 cpumMsrRd_Ia32VmxTrueExitCtls,
5276 cpumMsrRd_Ia32VmxTrueEntryCtls,
5277 cpumMsrRd_Ia32VmxVmFunc,
5278 cpumMsrRd_Ia32SpecCtrl,
5279 cpumMsrRd_Ia32ArchCapabilities,
5280
5281 cpumMsrRd_Amd64Efer,
5282 cpumMsrRd_Amd64SyscallTarget,
5283 cpumMsrRd_Amd64LongSyscallTarget,
5284 cpumMsrRd_Amd64CompSyscallTarget,
5285 cpumMsrRd_Amd64SyscallFlagMask,
5286 cpumMsrRd_Amd64FsBase,
5287 cpumMsrRd_Amd64GsBase,
5288 cpumMsrRd_Amd64KernelGsBase,
5289 cpumMsrRd_Amd64TscAux,
5290
5291 cpumMsrRd_IntelEblCrPowerOn,
5292 cpumMsrRd_IntelI7CoreThreadCount,
5293 cpumMsrRd_IntelP4EbcHardPowerOn,
5294 cpumMsrRd_IntelP4EbcSoftPowerOn,
5295 cpumMsrRd_IntelP4EbcFrequencyId,
5296 cpumMsrRd_IntelP6FsbFrequency,
5297 cpumMsrRd_IntelPlatformInfo,
5298 cpumMsrRd_IntelFlexRatio,
5299 cpumMsrRd_IntelPkgCStConfigControl,
5300 cpumMsrRd_IntelPmgIoCaptureBase,
5301 cpumMsrRd_IntelLastBranchFromToN,
5302 cpumMsrRd_IntelLastBranchFromN,
5303 cpumMsrRd_IntelLastBranchToN,
5304 cpumMsrRd_IntelLastBranchTos,
5305 cpumMsrRd_IntelBblCrCtl,
5306 cpumMsrRd_IntelBblCrCtl3,
5307 cpumMsrRd_IntelI7TemperatureTarget,
5308 cpumMsrRd_IntelI7MsrOffCoreResponseN,
5309 cpumMsrRd_IntelI7MiscPwrMgmt,
5310 cpumMsrRd_IntelP6CrN,
5311 cpumMsrRd_IntelCpuId1FeatureMaskEcdx,
5312 cpumMsrRd_IntelCpuId1FeatureMaskEax,
5313 cpumMsrRd_IntelCpuId80000001FeatureMaskEcdx,
5314 cpumMsrRd_IntelI7SandyAesNiCtl,
5315 cpumMsrRd_IntelI7TurboRatioLimit,
5316 cpumMsrRd_IntelI7LbrSelect,
5317 cpumMsrRd_IntelI7SandyErrorControl,
5318 cpumMsrRd_IntelI7VirtualLegacyWireCap,
5319 cpumMsrRd_IntelI7PowerCtl,
5320 cpumMsrRd_IntelI7SandyPebsNumAlt,
5321 cpumMsrRd_IntelI7PebsLdLat,
5322 cpumMsrRd_IntelI7PkgCnResidencyN,
5323 cpumMsrRd_IntelI7CoreCnResidencyN,
5324 cpumMsrRd_IntelI7SandyVrCurrentConfig,
5325 cpumMsrRd_IntelI7SandyVrMiscConfig,
5326 cpumMsrRd_IntelI7SandyRaplPowerUnit,
5327 cpumMsrRd_IntelI7SandyPkgCnIrtlN,
5328 cpumMsrRd_IntelI7SandyPkgC2Residency,
5329 cpumMsrRd_IntelI7RaplPkgPowerLimit,
5330 cpumMsrRd_IntelI7RaplPkgEnergyStatus,
5331 cpumMsrRd_IntelI7RaplPkgPerfStatus,
5332 cpumMsrRd_IntelI7RaplPkgPowerInfo,
5333 cpumMsrRd_IntelI7RaplDramPowerLimit,
5334 cpumMsrRd_IntelI7RaplDramEnergyStatus,
5335 cpumMsrRd_IntelI7RaplDramPerfStatus,
5336 cpumMsrRd_IntelI7RaplDramPowerInfo,
5337 cpumMsrRd_IntelI7RaplPp0PowerLimit,
5338 cpumMsrRd_IntelI7RaplPp0EnergyStatus,
5339 cpumMsrRd_IntelI7RaplPp0Policy,
5340 cpumMsrRd_IntelI7RaplPp0PerfStatus,
5341 cpumMsrRd_IntelI7RaplPp1PowerLimit,
5342 cpumMsrRd_IntelI7RaplPp1EnergyStatus,
5343 cpumMsrRd_IntelI7RaplPp1Policy,
5344 cpumMsrRd_IntelI7IvyConfigTdpNominal,
5345 cpumMsrRd_IntelI7IvyConfigTdpLevel1,
5346 cpumMsrRd_IntelI7IvyConfigTdpLevel2,
5347 cpumMsrRd_IntelI7IvyConfigTdpControl,
5348 cpumMsrRd_IntelI7IvyTurboActivationRatio,
5349 cpumMsrRd_IntelI7UncPerfGlobalCtrl,
5350 cpumMsrRd_IntelI7UncPerfGlobalStatus,
5351 cpumMsrRd_IntelI7UncPerfGlobalOvfCtrl,
5352 cpumMsrRd_IntelI7UncPerfFixedCtrCtrl,
5353 cpumMsrRd_IntelI7UncPerfFixedCtr,
5354 cpumMsrRd_IntelI7UncCBoxConfig,
5355 cpumMsrRd_IntelI7UncArbPerfCtrN,
5356 cpumMsrRd_IntelI7UncArbPerfEvtSelN,
5357 cpumMsrRd_IntelI7SmiCount,
5358 cpumMsrRd_IntelCore2EmttmCrTablesN,
5359 cpumMsrRd_IntelCore2SmmCStMiscInfo,
5360 cpumMsrRd_IntelCore1ExtConfig,
5361 cpumMsrRd_IntelCore1DtsCalControl,
5362 cpumMsrRd_IntelCore2PeciControl,
5363 cpumMsrRd_IntelAtSilvCoreC1Recidency,
5364
5365 cpumMsrRd_P6LastBranchFromIp,
5366 cpumMsrRd_P6LastBranchToIp,
5367 cpumMsrRd_P6LastIntFromIp,
5368 cpumMsrRd_P6LastIntToIp,
5369
5370 cpumMsrRd_AmdFam15hTscRate,
5371 cpumMsrRd_AmdFam15hLwpCfg,
5372 cpumMsrRd_AmdFam15hLwpCbAddr,
5373 cpumMsrRd_AmdFam10hMc4MiscN,
5374 cpumMsrRd_AmdK8PerfCtlN,
5375 cpumMsrRd_AmdK8PerfCtrN,
5376 cpumMsrRd_AmdK8SysCfg,
5377 cpumMsrRd_AmdK8HwCr,
5378 cpumMsrRd_AmdK8IorrBaseN,
5379 cpumMsrRd_AmdK8IorrMaskN,
5380 cpumMsrRd_AmdK8TopOfMemN,
5381 cpumMsrRd_AmdK8NbCfg1,
5382 cpumMsrRd_AmdK8McXcptRedir,
5383 cpumMsrRd_AmdK8CpuNameN,
5384 cpumMsrRd_AmdK8HwThermalCtrl,
5385 cpumMsrRd_AmdK8SwThermalCtrl,
5386 cpumMsrRd_AmdK8FidVidControl,
5387 cpumMsrRd_AmdK8FidVidStatus,
5388 cpumMsrRd_AmdK8McCtlMaskN,
5389 cpumMsrRd_AmdK8SmiOnIoTrapN,
5390 cpumMsrRd_AmdK8SmiOnIoTrapCtlSts,
5391 cpumMsrRd_AmdK8IntPendingMessage,
5392 cpumMsrRd_AmdK8SmiTriggerIoCycle,
5393 cpumMsrRd_AmdFam10hMmioCfgBaseAddr,
5394 cpumMsrRd_AmdFam10hTrapCtlMaybe,
5395 cpumMsrRd_AmdFam10hPStateCurLimit,
5396 cpumMsrRd_AmdFam10hPStateControl,
5397 cpumMsrRd_AmdFam10hPStateStatus,
5398 cpumMsrRd_AmdFam10hPStateN,
5399 cpumMsrRd_AmdFam10hCofVidControl,
5400 cpumMsrRd_AmdFam10hCofVidStatus,
5401 cpumMsrRd_AmdFam10hCStateIoBaseAddr,
5402 cpumMsrRd_AmdFam10hCpuWatchdogTimer,
5403 cpumMsrRd_AmdK8SmmBase,
5404 cpumMsrRd_AmdK8SmmAddr,
5405 cpumMsrRd_AmdK8SmmMask,
5406 cpumMsrRd_AmdK8VmCr,
5407 cpumMsrRd_AmdK8IgnNe,
5408 cpumMsrRd_AmdK8SmmCtl,
5409 cpumMsrRd_AmdK8VmHSavePa,
5410 cpumMsrRd_AmdFam10hVmLockKey,
5411 cpumMsrRd_AmdFam10hSmmLockKey,
5412 cpumMsrRd_AmdFam10hLocalSmiStatus,
5413 cpumMsrRd_AmdFam10hOsVisWrkIdLength,
5414 cpumMsrRd_AmdFam10hOsVisWrkStatus,
5415 cpumMsrRd_AmdFam16hL2IPerfCtlN,
5416 cpumMsrRd_AmdFam16hL2IPerfCtrN,
5417 cpumMsrRd_AmdFam15hNorthbridgePerfCtlN,
5418 cpumMsrRd_AmdFam15hNorthbridgePerfCtrN,
5419 cpumMsrRd_AmdK7MicrocodeCtl,
5420 cpumMsrRd_AmdK7ClusterIdMaybe,
5421 cpumMsrRd_AmdK8CpuIdCtlStd07hEbax,
5422 cpumMsrRd_AmdK8CpuIdCtlStd06hEcx,
5423 cpumMsrRd_AmdK8CpuIdCtlStd01hEdcx,
5424 cpumMsrRd_AmdK8CpuIdCtlExt01hEdcx,
5425 cpumMsrRd_AmdK8PatchLevel,
5426 cpumMsrRd_AmdK7DebugStatusMaybe,
5427 cpumMsrRd_AmdK7BHTraceBaseMaybe,
5428 cpumMsrRd_AmdK7BHTracePtrMaybe,
5429 cpumMsrRd_AmdK7BHTraceLimitMaybe,
5430 cpumMsrRd_AmdK7HardwareDebugToolCfgMaybe,
5431 cpumMsrRd_AmdK7FastFlushCountMaybe,
5432 cpumMsrRd_AmdK7NodeId,
5433 cpumMsrRd_AmdK7DrXAddrMaskN,
5434 cpumMsrRd_AmdK7Dr0DataMatchMaybe,
5435 cpumMsrRd_AmdK7Dr0DataMaskMaybe,
5436 cpumMsrRd_AmdK7LoadStoreCfg,
5437 cpumMsrRd_AmdK7InstrCacheCfg,
5438 cpumMsrRd_AmdK7DataCacheCfg,
5439 cpumMsrRd_AmdK7BusUnitCfg,
5440 cpumMsrRd_AmdK7DebugCtl2Maybe,
5441 cpumMsrRd_AmdFam15hFpuCfg,
5442 cpumMsrRd_AmdFam15hDecoderCfg,
5443 cpumMsrRd_AmdFam10hBusUnitCfg2,
5444 cpumMsrRd_AmdFam15hCombUnitCfg,
5445 cpumMsrRd_AmdFam15hCombUnitCfg2,
5446 cpumMsrRd_AmdFam15hCombUnitCfg3,
5447 cpumMsrRd_AmdFam15hExecUnitCfg,
5448 cpumMsrRd_AmdFam15hLoadStoreCfg2,
5449 cpumMsrRd_AmdFam10hIbsFetchCtl,
5450 cpumMsrRd_AmdFam10hIbsFetchLinAddr,
5451 cpumMsrRd_AmdFam10hIbsFetchPhysAddr,
5452 cpumMsrRd_AmdFam10hIbsOpExecCtl,
5453 cpumMsrRd_AmdFam10hIbsOpRip,
5454 cpumMsrRd_AmdFam10hIbsOpData,
5455 cpumMsrRd_AmdFam10hIbsOpData2,
5456 cpumMsrRd_AmdFam10hIbsOpData3,
5457 cpumMsrRd_AmdFam10hIbsDcLinAddr,
5458 cpumMsrRd_AmdFam10hIbsDcPhysAddr,
5459 cpumMsrRd_AmdFam10hIbsCtl,
5460 cpumMsrRd_AmdFam14hIbsBrTarget,
5461
5462 cpumMsrRd_Gim
5463};
5464
5465
5466/**
5467 * MSR write function table.
5468 */
5469static const PFNCPUMWRMSR g_aCpumWrMsrFns[kCpumMsrWrFn_End] =
5470{
5471 NULL, /* Invalid */
5472 cpumMsrWr_IgnoreWrite,
5473 cpumMsrWr_ReadOnly,
5474 NULL, /* Alias */
5475 cpumMsrWr_Ia32P5McAddr,
5476 cpumMsrWr_Ia32P5McType,
5477 cpumMsrWr_Ia32TimestampCounter,
5478 cpumMsrWr_Ia32ApicBase,
5479 cpumMsrWr_Ia32FeatureControl,
5480 cpumMsrWr_Ia32BiosSignId,
5481 cpumMsrWr_Ia32BiosUpdateTrigger,
5482 cpumMsrWr_Ia32SmmMonitorCtl,
5483 cpumMsrWr_Ia32PmcN,
5484 cpumMsrWr_Ia32MonitorFilterLineSize,
5485 cpumMsrWr_Ia32MPerf,
5486 cpumMsrWr_Ia32APerf,
5487 cpumMsrWr_Ia32MtrrPhysBaseN,
5488 cpumMsrWr_Ia32MtrrPhysMaskN,
5489 cpumMsrWr_Ia32MtrrFixed,
5490 cpumMsrWr_Ia32MtrrDefType,
5491 cpumMsrWr_Ia32Pat,
5492 cpumMsrWr_Ia32SysEnterCs,
5493 cpumMsrWr_Ia32SysEnterEsp,
5494 cpumMsrWr_Ia32SysEnterEip,
5495 cpumMsrWr_Ia32McgStatus,
5496 cpumMsrWr_Ia32McgCtl,
5497 cpumMsrWr_Ia32DebugCtl,
5498 cpumMsrWr_Ia32SmrrPhysBase,
5499 cpumMsrWr_Ia32SmrrPhysMask,
5500 cpumMsrWr_Ia32PlatformDcaCap,
5501 cpumMsrWr_Ia32Dca0Cap,
5502 cpumMsrWr_Ia32PerfEvtSelN,
5503 cpumMsrWr_Ia32PerfStatus,
5504 cpumMsrWr_Ia32PerfCtl,
5505 cpumMsrWr_Ia32FixedCtrN,
5506 cpumMsrWr_Ia32PerfCapabilities,
5507 cpumMsrWr_Ia32FixedCtrCtrl,
5508 cpumMsrWr_Ia32PerfGlobalStatus,
5509 cpumMsrWr_Ia32PerfGlobalCtrl,
5510 cpumMsrWr_Ia32PerfGlobalOvfCtrl,
5511 cpumMsrWr_Ia32PebsEnable,
5512 cpumMsrWr_Ia32ClockModulation,
5513 cpumMsrWr_Ia32ThermInterrupt,
5514 cpumMsrWr_Ia32ThermStatus,
5515 cpumMsrWr_Ia32Therm2Ctl,
5516 cpumMsrWr_Ia32MiscEnable,
5517 cpumMsrWr_Ia32McCtlStatusAddrMiscN,
5518 cpumMsrWr_Ia32McNCtl2,
5519 cpumMsrWr_Ia32DsArea,
5520 cpumMsrWr_Ia32TscDeadline,
5521 cpumMsrWr_Ia32X2ApicN,
5522 cpumMsrWr_Ia32DebugInterface,
5523 cpumMsrWr_Ia32SpecCtrl,
5524 cpumMsrWr_Ia32PredCmd,
5525
5526 cpumMsrWr_Amd64Efer,
5527 cpumMsrWr_Amd64SyscallTarget,
5528 cpumMsrWr_Amd64LongSyscallTarget,
5529 cpumMsrWr_Amd64CompSyscallTarget,
5530 cpumMsrWr_Amd64SyscallFlagMask,
5531 cpumMsrWr_Amd64FsBase,
5532 cpumMsrWr_Amd64GsBase,
5533 cpumMsrWr_Amd64KernelGsBase,
5534 cpumMsrWr_Amd64TscAux,
5535
5536 cpumMsrWr_IntelEblCrPowerOn,
5537 cpumMsrWr_IntelP4EbcHardPowerOn,
5538 cpumMsrWr_IntelP4EbcSoftPowerOn,
5539 cpumMsrWr_IntelP4EbcFrequencyId,
5540 cpumMsrWr_IntelFlexRatio,
5541 cpumMsrWr_IntelPkgCStConfigControl,
5542 cpumMsrWr_IntelPmgIoCaptureBase,
5543 cpumMsrWr_IntelLastBranchFromToN,
5544 cpumMsrWr_IntelLastBranchFromN,
5545 cpumMsrWr_IntelLastBranchToN,
5546 cpumMsrWr_IntelLastBranchTos,
5547 cpumMsrWr_IntelBblCrCtl,
5548 cpumMsrWr_IntelBblCrCtl3,
5549 cpumMsrWr_IntelI7TemperatureTarget,
5550 cpumMsrWr_IntelI7MsrOffCoreResponseN,
5551 cpumMsrWr_IntelI7MiscPwrMgmt,
5552 cpumMsrWr_IntelP6CrN,
5553 cpumMsrWr_IntelCpuId1FeatureMaskEcdx,
5554 cpumMsrWr_IntelCpuId1FeatureMaskEax,
5555 cpumMsrWr_IntelCpuId80000001FeatureMaskEcdx,
5556 cpumMsrWr_IntelI7SandyAesNiCtl,
5557 cpumMsrWr_IntelI7TurboRatioLimit,
5558 cpumMsrWr_IntelI7LbrSelect,
5559 cpumMsrWr_IntelI7SandyErrorControl,
5560 cpumMsrWr_IntelI7PowerCtl,
5561 cpumMsrWr_IntelI7SandyPebsNumAlt,
5562 cpumMsrWr_IntelI7PebsLdLat,
5563 cpumMsrWr_IntelI7SandyVrCurrentConfig,
5564 cpumMsrWr_IntelI7SandyVrMiscConfig,
5565 cpumMsrWr_IntelI7SandyRaplPowerUnit,
5566 cpumMsrWr_IntelI7SandyPkgCnIrtlN,
5567 cpumMsrWr_IntelI7SandyPkgC2Residency,
5568 cpumMsrWr_IntelI7RaplPkgPowerLimit,
5569 cpumMsrWr_IntelI7RaplDramPowerLimit,
5570 cpumMsrWr_IntelI7RaplPp0PowerLimit,
5571 cpumMsrWr_IntelI7RaplPp0Policy,
5572 cpumMsrWr_IntelI7RaplPp1PowerLimit,
5573 cpumMsrWr_IntelI7RaplPp1Policy,
5574 cpumMsrWr_IntelI7IvyConfigTdpControl,
5575 cpumMsrWr_IntelI7IvyTurboActivationRatio,
5576 cpumMsrWr_IntelI7UncPerfGlobalCtrl,
5577 cpumMsrWr_IntelI7UncPerfGlobalStatus,
5578 cpumMsrWr_IntelI7UncPerfGlobalOvfCtrl,
5579 cpumMsrWr_IntelI7UncPerfFixedCtrCtrl,
5580 cpumMsrWr_IntelI7UncPerfFixedCtr,
5581 cpumMsrWr_IntelI7UncArbPerfCtrN,
5582 cpumMsrWr_IntelI7UncArbPerfEvtSelN,
5583 cpumMsrWr_IntelCore2EmttmCrTablesN,
5584 cpumMsrWr_IntelCore2SmmCStMiscInfo,
5585 cpumMsrWr_IntelCore1ExtConfig,
5586 cpumMsrWr_IntelCore1DtsCalControl,
5587 cpumMsrWr_IntelCore2PeciControl,
5588
5589 cpumMsrWr_P6LastIntFromIp,
5590 cpumMsrWr_P6LastIntToIp,
5591
5592 cpumMsrWr_AmdFam15hTscRate,
5593 cpumMsrWr_AmdFam15hLwpCfg,
5594 cpumMsrWr_AmdFam15hLwpCbAddr,
5595 cpumMsrWr_AmdFam10hMc4MiscN,
5596 cpumMsrWr_AmdK8PerfCtlN,
5597 cpumMsrWr_AmdK8PerfCtrN,
5598 cpumMsrWr_AmdK8SysCfg,
5599 cpumMsrWr_AmdK8HwCr,
5600 cpumMsrWr_AmdK8IorrBaseN,
5601 cpumMsrWr_AmdK8IorrMaskN,
5602 cpumMsrWr_AmdK8TopOfMemN,
5603 cpumMsrWr_AmdK8NbCfg1,
5604 cpumMsrWr_AmdK8McXcptRedir,
5605 cpumMsrWr_AmdK8CpuNameN,
5606 cpumMsrWr_AmdK8HwThermalCtrl,
5607 cpumMsrWr_AmdK8SwThermalCtrl,
5608 cpumMsrWr_AmdK8FidVidControl,
5609 cpumMsrWr_AmdK8McCtlMaskN,
5610 cpumMsrWr_AmdK8SmiOnIoTrapN,
5611 cpumMsrWr_AmdK8SmiOnIoTrapCtlSts,
5612 cpumMsrWr_AmdK8IntPendingMessage,
5613 cpumMsrWr_AmdK8SmiTriggerIoCycle,
5614 cpumMsrWr_AmdFam10hMmioCfgBaseAddr,
5615 cpumMsrWr_AmdFam10hTrapCtlMaybe,
5616 cpumMsrWr_AmdFam10hPStateControl,
5617 cpumMsrWr_AmdFam10hPStateStatus,
5618 cpumMsrWr_AmdFam10hPStateN,
5619 cpumMsrWr_AmdFam10hCofVidControl,
5620 cpumMsrWr_AmdFam10hCofVidStatus,
5621 cpumMsrWr_AmdFam10hCStateIoBaseAddr,
5622 cpumMsrWr_AmdFam10hCpuWatchdogTimer,
5623 cpumMsrWr_AmdK8SmmBase,
5624 cpumMsrWr_AmdK8SmmAddr,
5625 cpumMsrWr_AmdK8SmmMask,
5626 cpumMsrWr_AmdK8VmCr,
5627 cpumMsrWr_AmdK8IgnNe,
5628 cpumMsrWr_AmdK8SmmCtl,
5629 cpumMsrWr_AmdK8VmHSavePa,
5630 cpumMsrWr_AmdFam10hVmLockKey,
5631 cpumMsrWr_AmdFam10hSmmLockKey,
5632 cpumMsrWr_AmdFam10hLocalSmiStatus,
5633 cpumMsrWr_AmdFam10hOsVisWrkIdLength,
5634 cpumMsrWr_AmdFam10hOsVisWrkStatus,
5635 cpumMsrWr_AmdFam16hL2IPerfCtlN,
5636 cpumMsrWr_AmdFam16hL2IPerfCtrN,
5637 cpumMsrWr_AmdFam15hNorthbridgePerfCtlN,
5638 cpumMsrWr_AmdFam15hNorthbridgePerfCtrN,
5639 cpumMsrWr_AmdK7MicrocodeCtl,
5640 cpumMsrWr_AmdK7ClusterIdMaybe,
5641 cpumMsrWr_AmdK8CpuIdCtlStd07hEbax,
5642 cpumMsrWr_AmdK8CpuIdCtlStd06hEcx,
5643 cpumMsrWr_AmdK8CpuIdCtlStd01hEdcx,
5644 cpumMsrWr_AmdK8CpuIdCtlExt01hEdcx,
5645 cpumMsrWr_AmdK8PatchLoader,
5646 cpumMsrWr_AmdK7DebugStatusMaybe,
5647 cpumMsrWr_AmdK7BHTraceBaseMaybe,
5648 cpumMsrWr_AmdK7BHTracePtrMaybe,
5649 cpumMsrWr_AmdK7BHTraceLimitMaybe,
5650 cpumMsrWr_AmdK7HardwareDebugToolCfgMaybe,
5651 cpumMsrWr_AmdK7FastFlushCountMaybe,
5652 cpumMsrWr_AmdK7NodeId,
5653 cpumMsrWr_AmdK7DrXAddrMaskN,
5654 cpumMsrWr_AmdK7Dr0DataMatchMaybe,
5655 cpumMsrWr_AmdK7Dr0DataMaskMaybe,
5656 cpumMsrWr_AmdK7LoadStoreCfg,
5657 cpumMsrWr_AmdK7InstrCacheCfg,
5658 cpumMsrWr_AmdK7DataCacheCfg,
5659 cpumMsrWr_AmdK7BusUnitCfg,
5660 cpumMsrWr_AmdK7DebugCtl2Maybe,
5661 cpumMsrWr_AmdFam15hFpuCfg,
5662 cpumMsrWr_AmdFam15hDecoderCfg,
5663 cpumMsrWr_AmdFam10hBusUnitCfg2,
5664 cpumMsrWr_AmdFam15hCombUnitCfg,
5665 cpumMsrWr_AmdFam15hCombUnitCfg2,
5666 cpumMsrWr_AmdFam15hCombUnitCfg3,
5667 cpumMsrWr_AmdFam15hExecUnitCfg,
5668 cpumMsrWr_AmdFam15hLoadStoreCfg2,
5669 cpumMsrWr_AmdFam10hIbsFetchCtl,
5670 cpumMsrWr_AmdFam10hIbsFetchLinAddr,
5671 cpumMsrWr_AmdFam10hIbsFetchPhysAddr,
5672 cpumMsrWr_AmdFam10hIbsOpExecCtl,
5673 cpumMsrWr_AmdFam10hIbsOpRip,
5674 cpumMsrWr_AmdFam10hIbsOpData,
5675 cpumMsrWr_AmdFam10hIbsOpData2,
5676 cpumMsrWr_AmdFam10hIbsOpData3,
5677 cpumMsrWr_AmdFam10hIbsDcLinAddr,
5678 cpumMsrWr_AmdFam10hIbsDcPhysAddr,
5679 cpumMsrWr_AmdFam10hIbsCtl,
5680 cpumMsrWr_AmdFam14hIbsBrTarget,
5681
5682 cpumMsrWr_Gim
5683};
5684
5685
5686/**
5687 * Looks up the range for the given MSR.
5688 *
5689 * @returns Pointer to the range if found, NULL if not.
5690 * @param pVM The cross context VM structure.
5691 * @param idMsr The MSR to look up.
5692 */
5693# ifndef IN_RING3
5694static
5695# endif
5696PCPUMMSRRANGE cpumLookupMsrRange(PVM pVM, uint32_t idMsr)
5697{
5698 /*
5699 * Binary lookup.
5700 */
5701 uint32_t cRanges = pVM->cpum.s.GuestInfo.cMsrRanges;
5702 if (!cRanges)
5703 return NULL;
5704 PCPUMMSRRANGE paRanges = pVM->cpum.s.GuestInfo.CTX_SUFF(paMsrRanges);
5705 for (;;)
5706 {
5707 uint32_t i = cRanges / 2;
5708 if (idMsr < paRanges[i].uFirst)
5709 {
5710 if (i == 0)
5711 break;
5712 cRanges = i;
5713 }
5714 else if (idMsr > paRanges[i].uLast)
5715 {
5716 i++;
5717 if (i >= cRanges)
5718 break;
5719 cRanges -= i;
5720 paRanges = &paRanges[i];
5721 }
5722 else
5723 {
5724 if (paRanges[i].enmRdFn == kCpumMsrRdFn_MsrAlias)
5725 return cpumLookupMsrRange(pVM, paRanges[i].uValue);
5726 return &paRanges[i];
5727 }
5728 }
5729
5730# ifdef VBOX_STRICT
5731 /*
5732 * Linear lookup to verify the above binary search.
5733 */
5734 uint32_t cLeft = pVM->cpum.s.GuestInfo.cMsrRanges;
5735 PCPUMMSRRANGE pCur = pVM->cpum.s.GuestInfo.CTX_SUFF(paMsrRanges);
5736 while (cLeft-- > 0)
5737 {
5738 if (idMsr >= pCur->uFirst && idMsr <= pCur->uLast)
5739 {
5740 AssertFailed();
5741 if (pCur->enmRdFn == kCpumMsrRdFn_MsrAlias)
5742 return cpumLookupMsrRange(pVM, pCur->uValue);
5743 return pCur;
5744 }
5745 pCur++;
5746 }
5747# endif
5748 return NULL;
5749}
5750
5751
5752/**
5753 * Query a guest MSR.
5754 *
5755 * The caller is responsible for checking privilege if the call is the result of
5756 * a RDMSR instruction. We'll do the rest.
5757 *
5758 * @retval VINF_SUCCESS on success.
5759 * @retval VINF_CPUM_R3_MSR_READ if the MSR read could not be serviced in the
5760 * current context (raw-mode or ring-0).
5761 * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR), the caller is
5762 * expected to take the appropriate actions. @a *puValue is set to 0.
5763 * @param pVCpu The cross context virtual CPU structure.
5764 * @param idMsr The MSR.
5765 * @param puValue Where to return the value.
5766 *
5767 * @remarks This will always return the right values, even when we're in the
5768 * recompiler.
5769 */
5770VMMDECL(VBOXSTRICTRC) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue)
5771{
5772 *puValue = 0;
5773
5774 VBOXSTRICTRC rcStrict;
5775 PVM pVM = pVCpu->CTX_SUFF(pVM);
5776 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, idMsr);
5777 if (pRange)
5778 {
5779 CPUMMSRRDFN enmRdFn = (CPUMMSRRDFN)pRange->enmRdFn;
5780 AssertReturn(enmRdFn > kCpumMsrRdFn_Invalid && enmRdFn < kCpumMsrRdFn_End, VERR_CPUM_IPE_1);
5781
5782 PFNCPUMRDMSR pfnRdMsr = g_aCpumRdMsrFns[enmRdFn];
5783 AssertReturn(pfnRdMsr, VERR_CPUM_IPE_2);
5784
5785 STAM_COUNTER_INC(&pRange->cReads);
5786 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReads);
5787
5788 rcStrict = pfnRdMsr(pVCpu, idMsr, pRange, puValue);
5789 if (rcStrict == VINF_SUCCESS)
5790 Log2(("CPUM: RDMSR %#x (%s) -> %#llx\n", idMsr, pRange->szName, *puValue));
5791 else if (rcStrict == VERR_CPUM_RAISE_GP_0)
5792 {
5793 Log(("CPUM: RDMSR %#x (%s) -> #GP(0)\n", idMsr, pRange->szName));
5794 STAM_COUNTER_INC(&pRange->cGps);
5795 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReadsRaiseGp);
5796 }
5797#ifndef IN_RING3
5798 else if (rcStrict == VINF_CPUM_R3_MSR_READ)
5799 Log(("CPUM: RDMSR %#x (%s) -> ring-3\n", idMsr, pRange->szName));
5800#endif
5801 else
5802 {
5803 Log(("CPUM: RDMSR %#x (%s) -> rcStrict=%Rrc\n", idMsr, pRange->szName, VBOXSTRICTRC_VAL(rcStrict)));
5804 AssertMsgStmt(RT_FAILURE_NP(rcStrict), ("%Rrc idMsr=%#x\n", VBOXSTRICTRC_VAL(rcStrict), idMsr),
5805 rcStrict = VERR_IPE_UNEXPECTED_INFO_STATUS);
5806 Assert(rcStrict != VERR_EM_INTERPRETER);
5807 }
5808 }
5809 else
5810 {
5811 Log(("CPUM: Unknown RDMSR %#x -> #GP(0)\n", idMsr));
5812 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReads);
5813 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReadsUnknown);
5814 rcStrict = VERR_CPUM_RAISE_GP_0;
5815 }
5816 return rcStrict;
5817}
5818
5819
5820/**
5821 * Writes to a guest MSR.
5822 *
5823 * The caller is responsible for checking privilege if the call is the result of
5824 * a WRMSR instruction. We'll do the rest.
5825 *
5826 * @retval VINF_SUCCESS on success.
5827 * @retval VINF_CPUM_R3_MSR_WRITE if the MSR write could not be serviced in the
5828 * current context (raw-mode or ring-0).
5829 * @retval VERR_CPUM_RAISE_GP_0 on failure, the caller is expected to take the
5830 * appropriate actions.
5831 *
5832 * @param pVCpu The cross context virtual CPU structure.
5833 * @param idMsr The MSR id.
5834 * @param uValue The value to set.
5835 *
5836 * @remarks Everyone changing MSR values, including the recompiler, shall do it
5837 * by calling this method. This makes sure we have current values and
5838 * that we trigger all the right actions when something changes.
5839 *
5840 * For performance reasons, this actually isn't entirely true for some
5841 * MSRs when in HM mode. The code here and in HM must be aware of
5842 * this.
5843 */
5844VMMDECL(VBOXSTRICTRC) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue)
5845{
5846 VBOXSTRICTRC rcStrict;
5847 PVM pVM = pVCpu->CTX_SUFF(pVM);
5848 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, idMsr);
5849 if (pRange)
5850 {
5851 STAM_COUNTER_INC(&pRange->cWrites);
5852 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWrites);
5853
5854 if (!(uValue & pRange->fWrGpMask))
5855 {
5856 CPUMMSRWRFN enmWrFn = (CPUMMSRWRFN)pRange->enmWrFn;
5857 AssertReturn(enmWrFn > kCpumMsrWrFn_Invalid && enmWrFn < kCpumMsrWrFn_End, VERR_CPUM_IPE_1);
5858
5859 PFNCPUMWRMSR pfnWrMsr = g_aCpumWrMsrFns[enmWrFn];
5860 AssertReturn(pfnWrMsr, VERR_CPUM_IPE_2);
5861
5862 uint64_t uValueAdjusted = uValue & ~pRange->fWrIgnMask;
5863 if (uValueAdjusted != uValue)
5864 {
5865 STAM_COUNTER_INC(&pRange->cIgnoredBits);
5866 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesToIgnoredBits);
5867 }
5868
5869 rcStrict = pfnWrMsr(pVCpu, idMsr, pRange, uValueAdjusted, uValue);
5870 if (rcStrict == VINF_SUCCESS)
5871 Log2(("CPUM: WRMSR %#x (%s), %#llx [%#llx]\n", idMsr, pRange->szName, uValueAdjusted, uValue));
5872 else if (rcStrict == VERR_CPUM_RAISE_GP_0)
5873 {
5874 Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> #GP(0)\n", idMsr, pRange->szName, uValueAdjusted, uValue));
5875 STAM_COUNTER_INC(&pRange->cGps);
5876 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesRaiseGp);
5877 }
5878#ifndef IN_RING3
5879 else if (rcStrict == VINF_CPUM_R3_MSR_WRITE)
5880 Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> ring-3\n", idMsr, pRange->szName, uValueAdjusted, uValue));
5881#endif
5882 else
5883 {
5884 Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> rcStrict=%Rrc\n",
5885 idMsr, pRange->szName, uValueAdjusted, uValue, VBOXSTRICTRC_VAL(rcStrict)));
5886 AssertMsgStmt(RT_FAILURE_NP(rcStrict), ("%Rrc idMsr=%#x\n", VBOXSTRICTRC_VAL(rcStrict), idMsr),
5887 rcStrict = VERR_IPE_UNEXPECTED_INFO_STATUS);
5888 Assert(rcStrict != VERR_EM_INTERPRETER);
5889 }
5890 }
5891 else
5892 {
5893 Log(("CPUM: WRMSR %#x (%s), %#llx -> #GP(0) - invalid bits %#llx\n",
5894 idMsr, pRange->szName, uValue, uValue & pRange->fWrGpMask));
5895 STAM_COUNTER_INC(&pRange->cGps);
5896 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesRaiseGp);
5897 rcStrict = VERR_CPUM_RAISE_GP_0;
5898 }
5899 }
5900 else
5901 {
5902 Log(("CPUM: Unknown WRMSR %#x, %#llx -> #GP(0)\n", idMsr, uValue));
5903 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWrites);
5904 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesUnknown);
5905 rcStrict = VERR_CPUM_RAISE_GP_0;
5906 }
5907 return rcStrict;
5908}
5909
5910
5911#if defined(VBOX_STRICT) && defined(IN_RING3)
5912/**
5913 * Performs some checks on the static data related to MSRs.
5914 *
5915 * @returns VINF_SUCCESS on success, error on failure.
5916 */
5917int cpumR3MsrStrictInitChecks(void)
5918{
5919#define CPUM_ASSERT_RD_MSR_FN(a_Register) \
5920 AssertReturn(g_aCpumRdMsrFns[kCpumMsrRdFn_##a_Register] == cpumMsrRd_##a_Register, VERR_CPUM_IPE_2);
5921#define CPUM_ASSERT_WR_MSR_FN(a_Register) \
5922 AssertReturn(g_aCpumWrMsrFns[kCpumMsrWrFn_##a_Register] == cpumMsrWr_##a_Register, VERR_CPUM_IPE_2);
5923
5924 AssertReturn(g_aCpumRdMsrFns[kCpumMsrRdFn_Invalid] == NULL, VERR_CPUM_IPE_2);
5925 CPUM_ASSERT_RD_MSR_FN(FixedValue);
5926 CPUM_ASSERT_RD_MSR_FN(WriteOnly);
5927 CPUM_ASSERT_RD_MSR_FN(Ia32P5McAddr);
5928 CPUM_ASSERT_RD_MSR_FN(Ia32P5McType);
5929 CPUM_ASSERT_RD_MSR_FN(Ia32TimestampCounter);
5930 CPUM_ASSERT_RD_MSR_FN(Ia32PlatformId);
5931 CPUM_ASSERT_RD_MSR_FN(Ia32ApicBase);
5932 CPUM_ASSERT_RD_MSR_FN(Ia32FeatureControl);
5933 CPUM_ASSERT_RD_MSR_FN(Ia32BiosSignId);
5934 CPUM_ASSERT_RD_MSR_FN(Ia32SmmMonitorCtl);
5935 CPUM_ASSERT_RD_MSR_FN(Ia32PmcN);
5936 CPUM_ASSERT_RD_MSR_FN(Ia32MonitorFilterLineSize);
5937 CPUM_ASSERT_RD_MSR_FN(Ia32MPerf);
5938 CPUM_ASSERT_RD_MSR_FN(Ia32APerf);
5939 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrCap);
5940 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrPhysBaseN);
5941 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrPhysMaskN);
5942 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrFixed);
5943 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrDefType);
5944 CPUM_ASSERT_RD_MSR_FN(Ia32Pat);
5945 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterCs);
5946 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterEsp);
5947 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterEip);
5948 CPUM_ASSERT_RD_MSR_FN(Ia32McgCap);
5949 CPUM_ASSERT_RD_MSR_FN(Ia32McgStatus);
5950 CPUM_ASSERT_RD_MSR_FN(Ia32McgCtl);
5951 CPUM_ASSERT_RD_MSR_FN(Ia32DebugCtl);
5952 CPUM_ASSERT_RD_MSR_FN(Ia32SmrrPhysBase);
5953 CPUM_ASSERT_RD_MSR_FN(Ia32SmrrPhysMask);
5954 CPUM_ASSERT_RD_MSR_FN(Ia32PlatformDcaCap);
5955 CPUM_ASSERT_RD_MSR_FN(Ia32CpuDcaCap);
5956 CPUM_ASSERT_RD_MSR_FN(Ia32Dca0Cap);
5957 CPUM_ASSERT_RD_MSR_FN(Ia32PerfEvtSelN);
5958 CPUM_ASSERT_RD_MSR_FN(Ia32PerfStatus);
5959 CPUM_ASSERT_RD_MSR_FN(Ia32PerfCtl);
5960 CPUM_ASSERT_RD_MSR_FN(Ia32FixedCtrN);
5961 CPUM_ASSERT_RD_MSR_FN(Ia32PerfCapabilities);
5962 CPUM_ASSERT_RD_MSR_FN(Ia32FixedCtrCtrl);
5963 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalStatus);
5964 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalCtrl);
5965 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalOvfCtrl);
5966 CPUM_ASSERT_RD_MSR_FN(Ia32PebsEnable);
5967 CPUM_ASSERT_RD_MSR_FN(Ia32ClockModulation);
5968 CPUM_ASSERT_RD_MSR_FN(Ia32ThermInterrupt);
5969 CPUM_ASSERT_RD_MSR_FN(Ia32ThermStatus);
5970 CPUM_ASSERT_RD_MSR_FN(Ia32MiscEnable);
5971 CPUM_ASSERT_RD_MSR_FN(Ia32McCtlStatusAddrMiscN);
5972 CPUM_ASSERT_RD_MSR_FN(Ia32McNCtl2);
5973 CPUM_ASSERT_RD_MSR_FN(Ia32DsArea);
5974 CPUM_ASSERT_RD_MSR_FN(Ia32TscDeadline);
5975 CPUM_ASSERT_RD_MSR_FN(Ia32X2ApicN);
5976 CPUM_ASSERT_RD_MSR_FN(Ia32DebugInterface);
5977 CPUM_ASSERT_RD_MSR_FN(Ia32VmxBasic);
5978 CPUM_ASSERT_RD_MSR_FN(Ia32VmxPinbasedCtls);
5979 CPUM_ASSERT_RD_MSR_FN(Ia32VmxProcbasedCtls);
5980 CPUM_ASSERT_RD_MSR_FN(Ia32VmxExitCtls);
5981 CPUM_ASSERT_RD_MSR_FN(Ia32VmxEntryCtls);
5982 CPUM_ASSERT_RD_MSR_FN(Ia32VmxMisc);
5983 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr0Fixed0);
5984 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr0Fixed1);
5985 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr4Fixed0);
5986 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr4Fixed1);
5987 CPUM_ASSERT_RD_MSR_FN(Ia32VmxVmcsEnum);
5988 CPUM_ASSERT_RD_MSR_FN(Ia32VmxProcBasedCtls2);
5989 CPUM_ASSERT_RD_MSR_FN(Ia32VmxEptVpidCap);
5990 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTruePinbasedCtls);
5991 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueProcbasedCtls);
5992 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueExitCtls);
5993 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueEntryCtls);
5994 CPUM_ASSERT_RD_MSR_FN(Ia32VmxVmFunc);
5995 CPUM_ASSERT_RD_MSR_FN(Ia32SpecCtrl);
5996 CPUM_ASSERT_RD_MSR_FN(Ia32ArchCapabilities);
5997
5998 CPUM_ASSERT_RD_MSR_FN(Amd64Efer);
5999 CPUM_ASSERT_RD_MSR_FN(Amd64SyscallTarget);
6000 CPUM_ASSERT_RD_MSR_FN(Amd64LongSyscallTarget);
6001 CPUM_ASSERT_RD_MSR_FN(Amd64CompSyscallTarget);
6002 CPUM_ASSERT_RD_MSR_FN(Amd64SyscallFlagMask);
6003 CPUM_ASSERT_RD_MSR_FN(Amd64FsBase);
6004 CPUM_ASSERT_RD_MSR_FN(Amd64GsBase);
6005 CPUM_ASSERT_RD_MSR_FN(Amd64KernelGsBase);
6006 CPUM_ASSERT_RD_MSR_FN(Amd64TscAux);
6007
6008 CPUM_ASSERT_RD_MSR_FN(IntelEblCrPowerOn);
6009 CPUM_ASSERT_RD_MSR_FN(IntelI7CoreThreadCount);
6010 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcHardPowerOn);
6011 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcSoftPowerOn);
6012 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcFrequencyId);
6013 CPUM_ASSERT_RD_MSR_FN(IntelP6FsbFrequency);
6014 CPUM_ASSERT_RD_MSR_FN(IntelPlatformInfo);
6015 CPUM_ASSERT_RD_MSR_FN(IntelFlexRatio);
6016 CPUM_ASSERT_RD_MSR_FN(IntelPkgCStConfigControl);
6017 CPUM_ASSERT_RD_MSR_FN(IntelPmgIoCaptureBase);
6018 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchFromToN);
6019 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchFromN);
6020 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchToN);
6021 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchTos);
6022 CPUM_ASSERT_RD_MSR_FN(IntelBblCrCtl);
6023 CPUM_ASSERT_RD_MSR_FN(IntelBblCrCtl3);
6024 CPUM_ASSERT_RD_MSR_FN(IntelI7TemperatureTarget);
6025 CPUM_ASSERT_RD_MSR_FN(IntelI7MsrOffCoreResponseN);
6026 CPUM_ASSERT_RD_MSR_FN(IntelI7MiscPwrMgmt);
6027 CPUM_ASSERT_RD_MSR_FN(IntelP6CrN);
6028 CPUM_ASSERT_RD_MSR_FN(IntelCpuId1FeatureMaskEcdx);
6029 CPUM_ASSERT_RD_MSR_FN(IntelCpuId1FeatureMaskEax);
6030 CPUM_ASSERT_RD_MSR_FN(IntelCpuId80000001FeatureMaskEcdx);
6031 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyAesNiCtl);
6032 CPUM_ASSERT_RD_MSR_FN(IntelI7TurboRatioLimit);
6033 CPUM_ASSERT_RD_MSR_FN(IntelI7LbrSelect);
6034 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyErrorControl);
6035 CPUM_ASSERT_RD_MSR_FN(IntelI7VirtualLegacyWireCap);
6036 CPUM_ASSERT_RD_MSR_FN(IntelI7PowerCtl);
6037 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPebsNumAlt);
6038 CPUM_ASSERT_RD_MSR_FN(IntelI7PebsLdLat);
6039 CPUM_ASSERT_RD_MSR_FN(IntelI7PkgCnResidencyN);
6040 CPUM_ASSERT_RD_MSR_FN(IntelI7CoreCnResidencyN);
6041 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyVrCurrentConfig);
6042 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyVrMiscConfig);
6043 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyRaplPowerUnit);
6044 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPkgCnIrtlN);
6045 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPkgC2Residency);
6046 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPowerLimit);
6047 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgEnergyStatus);
6048 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPerfStatus);
6049 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPowerInfo);
6050 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPowerLimit);
6051 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramEnergyStatus);
6052 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPerfStatus);
6053 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPowerInfo);
6054 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0PowerLimit);
6055 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0EnergyStatus);
6056 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0Policy);
6057 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0PerfStatus);
6058 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1PowerLimit);
6059 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1EnergyStatus);
6060 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1Policy);
6061 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpNominal);
6062 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpLevel1);
6063 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpLevel2);
6064 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpControl);
6065 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyTurboActivationRatio);
6066 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalCtrl);
6067 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalStatus);
6068 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalOvfCtrl);
6069 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfFixedCtrCtrl);
6070 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfFixedCtr);
6071 CPUM_ASSERT_RD_MSR_FN(IntelI7UncCBoxConfig);
6072 CPUM_ASSERT_RD_MSR_FN(IntelI7UncArbPerfCtrN);
6073 CPUM_ASSERT_RD_MSR_FN(IntelI7UncArbPerfEvtSelN);
6074 CPUM_ASSERT_RD_MSR_FN(IntelI7SmiCount);
6075 CPUM_ASSERT_RD_MSR_FN(IntelCore2EmttmCrTablesN);
6076 CPUM_ASSERT_RD_MSR_FN(IntelCore2SmmCStMiscInfo);
6077 CPUM_ASSERT_RD_MSR_FN(IntelCore1ExtConfig);
6078 CPUM_ASSERT_RD_MSR_FN(IntelCore1DtsCalControl);
6079 CPUM_ASSERT_RD_MSR_FN(IntelCore2PeciControl);
6080 CPUM_ASSERT_RD_MSR_FN(IntelAtSilvCoreC1Recidency);
6081
6082 CPUM_ASSERT_RD_MSR_FN(P6LastBranchFromIp);
6083 CPUM_ASSERT_RD_MSR_FN(P6LastBranchToIp);
6084 CPUM_ASSERT_RD_MSR_FN(P6LastIntFromIp);
6085 CPUM_ASSERT_RD_MSR_FN(P6LastIntToIp);
6086
6087 CPUM_ASSERT_RD_MSR_FN(AmdFam15hTscRate);
6088 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLwpCfg);
6089 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLwpCbAddr);
6090 CPUM_ASSERT_RD_MSR_FN(AmdFam10hMc4MiscN);
6091 CPUM_ASSERT_RD_MSR_FN(AmdK8PerfCtlN);
6092 CPUM_ASSERT_RD_MSR_FN(AmdK8PerfCtrN);
6093 CPUM_ASSERT_RD_MSR_FN(AmdK8SysCfg);
6094 CPUM_ASSERT_RD_MSR_FN(AmdK8HwCr);
6095 CPUM_ASSERT_RD_MSR_FN(AmdK8IorrBaseN);
6096 CPUM_ASSERT_RD_MSR_FN(AmdK8IorrMaskN);
6097 CPUM_ASSERT_RD_MSR_FN(AmdK8TopOfMemN);
6098 CPUM_ASSERT_RD_MSR_FN(AmdK8NbCfg1);
6099 CPUM_ASSERT_RD_MSR_FN(AmdK8McXcptRedir);
6100 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuNameN);
6101 CPUM_ASSERT_RD_MSR_FN(AmdK8HwThermalCtrl);
6102 CPUM_ASSERT_RD_MSR_FN(AmdK8SwThermalCtrl);
6103 CPUM_ASSERT_RD_MSR_FN(AmdK8FidVidControl);
6104 CPUM_ASSERT_RD_MSR_FN(AmdK8FidVidStatus);
6105 CPUM_ASSERT_RD_MSR_FN(AmdK8McCtlMaskN);
6106 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiOnIoTrapN);
6107 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiOnIoTrapCtlSts);
6108 CPUM_ASSERT_RD_MSR_FN(AmdK8IntPendingMessage);
6109 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiTriggerIoCycle);
6110 CPUM_ASSERT_RD_MSR_FN(AmdFam10hMmioCfgBaseAddr);
6111 CPUM_ASSERT_RD_MSR_FN(AmdFam10hTrapCtlMaybe);
6112 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateCurLimit);
6113 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateControl);
6114 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateStatus);
6115 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateN);
6116 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCofVidControl);
6117 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCofVidStatus);
6118 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCStateIoBaseAddr);
6119 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCpuWatchdogTimer);
6120 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmBase);
6121 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmAddr);
6122 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmMask);
6123 CPUM_ASSERT_RD_MSR_FN(AmdK8VmCr);
6124 CPUM_ASSERT_RD_MSR_FN(AmdK8IgnNe);
6125 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmCtl);
6126 CPUM_ASSERT_RD_MSR_FN(AmdK8VmHSavePa);
6127 CPUM_ASSERT_RD_MSR_FN(AmdFam10hVmLockKey);
6128 CPUM_ASSERT_RD_MSR_FN(AmdFam10hSmmLockKey);
6129 CPUM_ASSERT_RD_MSR_FN(AmdFam10hLocalSmiStatus);
6130 CPUM_ASSERT_RD_MSR_FN(AmdFam10hOsVisWrkIdLength);
6131 CPUM_ASSERT_RD_MSR_FN(AmdFam10hOsVisWrkStatus);
6132 CPUM_ASSERT_RD_MSR_FN(AmdFam16hL2IPerfCtlN);
6133 CPUM_ASSERT_RD_MSR_FN(AmdFam16hL2IPerfCtrN);
6134 CPUM_ASSERT_RD_MSR_FN(AmdFam15hNorthbridgePerfCtlN);
6135 CPUM_ASSERT_RD_MSR_FN(AmdFam15hNorthbridgePerfCtrN);
6136 CPUM_ASSERT_RD_MSR_FN(AmdK7MicrocodeCtl);
6137 CPUM_ASSERT_RD_MSR_FN(AmdK7ClusterIdMaybe);
6138 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd07hEbax);
6139 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd06hEcx);
6140 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd01hEdcx);
6141 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlExt01hEdcx);
6142 CPUM_ASSERT_RD_MSR_FN(AmdK8PatchLevel);
6143 CPUM_ASSERT_RD_MSR_FN(AmdK7DebugStatusMaybe);
6144 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTraceBaseMaybe);
6145 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTracePtrMaybe);
6146 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTraceLimitMaybe);
6147 CPUM_ASSERT_RD_MSR_FN(AmdK7HardwareDebugToolCfgMaybe);
6148 CPUM_ASSERT_RD_MSR_FN(AmdK7FastFlushCountMaybe);
6149 CPUM_ASSERT_RD_MSR_FN(AmdK7NodeId);
6150 CPUM_ASSERT_RD_MSR_FN(AmdK7DrXAddrMaskN);
6151 CPUM_ASSERT_RD_MSR_FN(AmdK7Dr0DataMatchMaybe);
6152 CPUM_ASSERT_RD_MSR_FN(AmdK7Dr0DataMaskMaybe);
6153 CPUM_ASSERT_RD_MSR_FN(AmdK7LoadStoreCfg);
6154 CPUM_ASSERT_RD_MSR_FN(AmdK7InstrCacheCfg);
6155 CPUM_ASSERT_RD_MSR_FN(AmdK7DataCacheCfg);
6156 CPUM_ASSERT_RD_MSR_FN(AmdK7BusUnitCfg);
6157 CPUM_ASSERT_RD_MSR_FN(AmdK7DebugCtl2Maybe);
6158 CPUM_ASSERT_RD_MSR_FN(AmdFam15hFpuCfg);
6159 CPUM_ASSERT_RD_MSR_FN(AmdFam15hDecoderCfg);
6160 CPUM_ASSERT_RD_MSR_FN(AmdFam10hBusUnitCfg2);
6161 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg);
6162 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg2);
6163 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg3);
6164 CPUM_ASSERT_RD_MSR_FN(AmdFam15hExecUnitCfg);
6165 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLoadStoreCfg2);
6166 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchCtl);
6167 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchLinAddr);
6168 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchPhysAddr);
6169 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpExecCtl);
6170 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpRip);
6171 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData);
6172 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData2);
6173 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData3);
6174 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsDcLinAddr);
6175 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsDcPhysAddr);
6176 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsCtl);
6177 CPUM_ASSERT_RD_MSR_FN(AmdFam14hIbsBrTarget);
6178
6179 CPUM_ASSERT_RD_MSR_FN(Gim)
6180
6181 AssertReturn(g_aCpumWrMsrFns[kCpumMsrWrFn_Invalid] == NULL, VERR_CPUM_IPE_2);
6182 CPUM_ASSERT_WR_MSR_FN(Ia32P5McAddr);
6183 CPUM_ASSERT_WR_MSR_FN(Ia32P5McType);
6184 CPUM_ASSERT_WR_MSR_FN(Ia32TimestampCounter);
6185 CPUM_ASSERT_WR_MSR_FN(Ia32ApicBase);
6186 CPUM_ASSERT_WR_MSR_FN(Ia32FeatureControl);
6187 CPUM_ASSERT_WR_MSR_FN(Ia32BiosSignId);
6188 CPUM_ASSERT_WR_MSR_FN(Ia32BiosUpdateTrigger);
6189 CPUM_ASSERT_WR_MSR_FN(Ia32SmmMonitorCtl);
6190 CPUM_ASSERT_WR_MSR_FN(Ia32PmcN);
6191 CPUM_ASSERT_WR_MSR_FN(Ia32MonitorFilterLineSize);
6192 CPUM_ASSERT_WR_MSR_FN(Ia32MPerf);
6193 CPUM_ASSERT_WR_MSR_FN(Ia32APerf);
6194 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrPhysBaseN);
6195 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrPhysMaskN);
6196 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrFixed);
6197 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrDefType);
6198 CPUM_ASSERT_WR_MSR_FN(Ia32Pat);
6199 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterCs);
6200 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterEsp);
6201 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterEip);
6202 CPUM_ASSERT_WR_MSR_FN(Ia32McgStatus);
6203 CPUM_ASSERT_WR_MSR_FN(Ia32McgCtl);
6204 CPUM_ASSERT_WR_MSR_FN(Ia32DebugCtl);
6205 CPUM_ASSERT_WR_MSR_FN(Ia32SmrrPhysBase);
6206 CPUM_ASSERT_WR_MSR_FN(Ia32SmrrPhysMask);
6207 CPUM_ASSERT_WR_MSR_FN(Ia32PlatformDcaCap);
6208 CPUM_ASSERT_WR_MSR_FN(Ia32Dca0Cap);
6209 CPUM_ASSERT_WR_MSR_FN(Ia32PerfEvtSelN);
6210 CPUM_ASSERT_WR_MSR_FN(Ia32PerfStatus);
6211 CPUM_ASSERT_WR_MSR_FN(Ia32PerfCtl);
6212 CPUM_ASSERT_WR_MSR_FN(Ia32FixedCtrN);
6213 CPUM_ASSERT_WR_MSR_FN(Ia32PerfCapabilities);
6214 CPUM_ASSERT_WR_MSR_FN(Ia32FixedCtrCtrl);
6215 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalStatus);
6216 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalCtrl);
6217 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalOvfCtrl);
6218 CPUM_ASSERT_WR_MSR_FN(Ia32PebsEnable);
6219 CPUM_ASSERT_WR_MSR_FN(Ia32ClockModulation);
6220 CPUM_ASSERT_WR_MSR_FN(Ia32ThermInterrupt);
6221 CPUM_ASSERT_WR_MSR_FN(Ia32ThermStatus);
6222 CPUM_ASSERT_WR_MSR_FN(Ia32MiscEnable);
6223 CPUM_ASSERT_WR_MSR_FN(Ia32McCtlStatusAddrMiscN);
6224 CPUM_ASSERT_WR_MSR_FN(Ia32McNCtl2);
6225 CPUM_ASSERT_WR_MSR_FN(Ia32DsArea);
6226 CPUM_ASSERT_WR_MSR_FN(Ia32TscDeadline);
6227 CPUM_ASSERT_WR_MSR_FN(Ia32X2ApicN);
6228 CPUM_ASSERT_WR_MSR_FN(Ia32DebugInterface);
6229 CPUM_ASSERT_WR_MSR_FN(Ia32SpecCtrl);
6230 CPUM_ASSERT_WR_MSR_FN(Ia32PredCmd);
6231
6232 CPUM_ASSERT_WR_MSR_FN(Amd64Efer);
6233 CPUM_ASSERT_WR_MSR_FN(Amd64SyscallTarget);
6234 CPUM_ASSERT_WR_MSR_FN(Amd64LongSyscallTarget);
6235 CPUM_ASSERT_WR_MSR_FN(Amd64CompSyscallTarget);
6236 CPUM_ASSERT_WR_MSR_FN(Amd64SyscallFlagMask);
6237 CPUM_ASSERT_WR_MSR_FN(Amd64FsBase);
6238 CPUM_ASSERT_WR_MSR_FN(Amd64GsBase);
6239 CPUM_ASSERT_WR_MSR_FN(Amd64KernelGsBase);
6240 CPUM_ASSERT_WR_MSR_FN(Amd64TscAux);
6241
6242 CPUM_ASSERT_WR_MSR_FN(IntelEblCrPowerOn);
6243 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcHardPowerOn);
6244 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcSoftPowerOn);
6245 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcFrequencyId);
6246 CPUM_ASSERT_WR_MSR_FN(IntelFlexRatio);
6247 CPUM_ASSERT_WR_MSR_FN(IntelPkgCStConfigControl);
6248 CPUM_ASSERT_WR_MSR_FN(IntelPmgIoCaptureBase);
6249 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchFromToN);
6250 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchFromN);
6251 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchToN);
6252 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchTos);
6253 CPUM_ASSERT_WR_MSR_FN(IntelBblCrCtl);
6254 CPUM_ASSERT_WR_MSR_FN(IntelBblCrCtl3);
6255 CPUM_ASSERT_WR_MSR_FN(IntelI7TemperatureTarget);
6256 CPUM_ASSERT_WR_MSR_FN(IntelI7MsrOffCoreResponseN);
6257 CPUM_ASSERT_WR_MSR_FN(IntelI7MiscPwrMgmt);
6258 CPUM_ASSERT_WR_MSR_FN(IntelP6CrN);
6259 CPUM_ASSERT_WR_MSR_FN(IntelCpuId1FeatureMaskEcdx);
6260 CPUM_ASSERT_WR_MSR_FN(IntelCpuId1FeatureMaskEax);
6261 CPUM_ASSERT_WR_MSR_FN(IntelCpuId80000001FeatureMaskEcdx);
6262 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyAesNiCtl);
6263 CPUM_ASSERT_WR_MSR_FN(IntelI7TurboRatioLimit);
6264 CPUM_ASSERT_WR_MSR_FN(IntelI7LbrSelect);
6265 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyErrorControl);
6266 CPUM_ASSERT_WR_MSR_FN(IntelI7PowerCtl);
6267 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPebsNumAlt);
6268 CPUM_ASSERT_WR_MSR_FN(IntelI7PebsLdLat);
6269 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyVrCurrentConfig);
6270 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyVrMiscConfig);
6271 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPkgCnIrtlN);
6272 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPkgC2Residency);
6273 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPkgPowerLimit);
6274 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplDramPowerLimit);
6275 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp0PowerLimit);
6276 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp0Policy);
6277 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp1PowerLimit);
6278 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp1Policy);
6279 CPUM_ASSERT_WR_MSR_FN(IntelI7IvyConfigTdpControl);
6280 CPUM_ASSERT_WR_MSR_FN(IntelI7IvyTurboActivationRatio);
6281 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalCtrl);
6282 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalStatus);
6283 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalOvfCtrl);
6284 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfFixedCtrCtrl);
6285 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfFixedCtr);
6286 CPUM_ASSERT_WR_MSR_FN(IntelI7UncArbPerfCtrN);
6287 CPUM_ASSERT_WR_MSR_FN(IntelI7UncArbPerfEvtSelN);
6288 CPUM_ASSERT_WR_MSR_FN(IntelCore2EmttmCrTablesN);
6289 CPUM_ASSERT_WR_MSR_FN(IntelCore2SmmCStMiscInfo);
6290 CPUM_ASSERT_WR_MSR_FN(IntelCore1ExtConfig);
6291 CPUM_ASSERT_WR_MSR_FN(IntelCore1DtsCalControl);
6292 CPUM_ASSERT_WR_MSR_FN(IntelCore2PeciControl);
6293
6294 CPUM_ASSERT_WR_MSR_FN(P6LastIntFromIp);
6295 CPUM_ASSERT_WR_MSR_FN(P6LastIntToIp);
6296
6297 CPUM_ASSERT_WR_MSR_FN(AmdFam15hTscRate);
6298 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLwpCfg);
6299 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLwpCbAddr);
6300 CPUM_ASSERT_WR_MSR_FN(AmdFam10hMc4MiscN);
6301 CPUM_ASSERT_WR_MSR_FN(AmdK8PerfCtlN);
6302 CPUM_ASSERT_WR_MSR_FN(AmdK8PerfCtrN);
6303 CPUM_ASSERT_WR_MSR_FN(AmdK8SysCfg);
6304 CPUM_ASSERT_WR_MSR_FN(AmdK8HwCr);
6305 CPUM_ASSERT_WR_MSR_FN(AmdK8IorrBaseN);
6306 CPUM_ASSERT_WR_MSR_FN(AmdK8IorrMaskN);
6307 CPUM_ASSERT_WR_MSR_FN(AmdK8TopOfMemN);
6308 CPUM_ASSERT_WR_MSR_FN(AmdK8NbCfg1);
6309 CPUM_ASSERT_WR_MSR_FN(AmdK8McXcptRedir);
6310 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuNameN);
6311 CPUM_ASSERT_WR_MSR_FN(AmdK8HwThermalCtrl);
6312 CPUM_ASSERT_WR_MSR_FN(AmdK8SwThermalCtrl);
6313 CPUM_ASSERT_WR_MSR_FN(AmdK8FidVidControl);
6314 CPUM_ASSERT_WR_MSR_FN(AmdK8McCtlMaskN);
6315 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiOnIoTrapN);
6316 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiOnIoTrapCtlSts);
6317 CPUM_ASSERT_WR_MSR_FN(AmdK8IntPendingMessage);
6318 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiTriggerIoCycle);
6319 CPUM_ASSERT_WR_MSR_FN(AmdFam10hMmioCfgBaseAddr);
6320 CPUM_ASSERT_WR_MSR_FN(AmdFam10hTrapCtlMaybe);
6321 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateControl);
6322 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateStatus);
6323 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateN);
6324 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCofVidControl);
6325 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCofVidStatus);
6326 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCStateIoBaseAddr);
6327 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCpuWatchdogTimer);
6328 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmBase);
6329 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmAddr);
6330 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmMask);
6331 CPUM_ASSERT_WR_MSR_FN(AmdK8VmCr);
6332 CPUM_ASSERT_WR_MSR_FN(AmdK8IgnNe);
6333 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmCtl);
6334 CPUM_ASSERT_WR_MSR_FN(AmdK8VmHSavePa);
6335 CPUM_ASSERT_WR_MSR_FN(AmdFam10hVmLockKey);
6336 CPUM_ASSERT_WR_MSR_FN(AmdFam10hSmmLockKey);
6337 CPUM_ASSERT_WR_MSR_FN(AmdFam10hLocalSmiStatus);
6338 CPUM_ASSERT_WR_MSR_FN(AmdFam10hOsVisWrkIdLength);
6339 CPUM_ASSERT_WR_MSR_FN(AmdFam10hOsVisWrkStatus);
6340 CPUM_ASSERT_WR_MSR_FN(AmdFam16hL2IPerfCtlN);
6341 CPUM_ASSERT_WR_MSR_FN(AmdFam16hL2IPerfCtrN);
6342 CPUM_ASSERT_WR_MSR_FN(AmdFam15hNorthbridgePerfCtlN);
6343 CPUM_ASSERT_WR_MSR_FN(AmdFam15hNorthbridgePerfCtrN);
6344 CPUM_ASSERT_WR_MSR_FN(AmdK7MicrocodeCtl);
6345 CPUM_ASSERT_WR_MSR_FN(AmdK7ClusterIdMaybe);
6346 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd07hEbax);
6347 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd06hEcx);
6348 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd01hEdcx);
6349 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlExt01hEdcx);
6350 CPUM_ASSERT_WR_MSR_FN(AmdK8PatchLoader);
6351 CPUM_ASSERT_WR_MSR_FN(AmdK7DebugStatusMaybe);
6352 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTraceBaseMaybe);
6353 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTracePtrMaybe);
6354 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTraceLimitMaybe);
6355 CPUM_ASSERT_WR_MSR_FN(AmdK7HardwareDebugToolCfgMaybe);
6356 CPUM_ASSERT_WR_MSR_FN(AmdK7FastFlushCountMaybe);
6357 CPUM_ASSERT_WR_MSR_FN(AmdK7NodeId);
6358 CPUM_ASSERT_WR_MSR_FN(AmdK7DrXAddrMaskN);
6359 CPUM_ASSERT_WR_MSR_FN(AmdK7Dr0DataMatchMaybe);
6360 CPUM_ASSERT_WR_MSR_FN(AmdK7Dr0DataMaskMaybe);
6361 CPUM_ASSERT_WR_MSR_FN(AmdK7LoadStoreCfg);
6362 CPUM_ASSERT_WR_MSR_FN(AmdK7InstrCacheCfg);
6363 CPUM_ASSERT_WR_MSR_FN(AmdK7DataCacheCfg);
6364 CPUM_ASSERT_WR_MSR_FN(AmdK7BusUnitCfg);
6365 CPUM_ASSERT_WR_MSR_FN(AmdK7DebugCtl2Maybe);
6366 CPUM_ASSERT_WR_MSR_FN(AmdFam15hFpuCfg);
6367 CPUM_ASSERT_WR_MSR_FN(AmdFam15hDecoderCfg);
6368 CPUM_ASSERT_WR_MSR_FN(AmdFam10hBusUnitCfg2);
6369 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg);
6370 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg2);
6371 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg3);
6372 CPUM_ASSERT_WR_MSR_FN(AmdFam15hExecUnitCfg);
6373 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLoadStoreCfg2);
6374 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchCtl);
6375 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchLinAddr);
6376 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchPhysAddr);
6377 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpExecCtl);
6378 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpRip);
6379 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData);
6380 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData2);
6381 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData3);
6382 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsDcLinAddr);
6383 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsDcPhysAddr);
6384 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsCtl);
6385 CPUM_ASSERT_WR_MSR_FN(AmdFam14hIbsBrTarget);
6386
6387 CPUM_ASSERT_WR_MSR_FN(Gim);
6388
6389 return VINF_SUCCESS;
6390}
6391#endif /* VBOX_STRICT && IN_RING3 */
6392
6393
6394/**
6395 * Gets the scalable bus frequency.
6396 *
6397 * The bus frequency is used as a base in several MSRs that gives the CPU and
6398 * other frequency ratios.
6399 *
6400 * @returns Scalable bus frequency in Hz. Will not return CPUM_SBUSFREQ_UNKNOWN.
6401 * @param pVM The cross context VM structure.
6402 */
6403VMMDECL(uint64_t) CPUMGetGuestScalableBusFrequency(PVM pVM)
6404{
6405 uint64_t uFreq = pVM->cpum.s.GuestInfo.uScalableBusFreq;
6406 if (uFreq == CPUM_SBUSFREQ_UNKNOWN)
6407 uFreq = CPUM_SBUSFREQ_100MHZ;
6408 return uFreq;
6409}
6410
6411
6412/**
6413 * Sets the guest EFER MSR without performing any additional checks.
6414 *
6415 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
6416 * @param uOldEfer The previous EFER MSR value.
6417 * @param uValidEfer The new, validated EFER MSR value.
6418 *
6419 * @remarks One would normally call CPUMQueryValidatedGuestEfer before calling this
6420 * function to change the EFER in order to perform an EFER transition.
6421 */
6422VMMDECL(void) CPUMSetGuestMsrEferNoCheck(PVMCPU pVCpu, uint64_t uOldEfer, uint64_t uValidEfer)
6423{
6424 pVCpu->cpum.s.Guest.msrEFER = uValidEfer;
6425
6426 /* AMD64 Architecture Programmer's Manual: 15.15 TLB Control; flush the TLB
6427 if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
6428 if ( (uOldEfer & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA))
6429 != (pVCpu->cpum.s.Guest.msrEFER & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA)))
6430 {
6431 /// @todo PGMFlushTLB(pVCpu, cr3, true /*fGlobal*/);
6432 HMFlushTLB(pVCpu);
6433
6434 /* Notify PGM about NXE changes. */
6435 if ( (uOldEfer & MSR_K6_EFER_NXE)
6436 != (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE))
6437 PGMNotifyNxeChanged(pVCpu, !(uOldEfer & MSR_K6_EFER_NXE));
6438 }
6439}
6440
6441
6442/**
6443 * Checks if a guest PAT MSR write is valid.
6444 *
6445 * @returns @c true if the PAT bit combination is valid, @c false otherwise.
6446 * @param uValue The PAT MSR value.
6447 */
6448VMMDECL(bool) CPUMIsPatMsrValid(uint64_t uValue)
6449{
6450 for (uint32_t cShift = 0; cShift < 63; cShift += 8)
6451 {
6452 /* Check all eight bits because the top 5 bits of each byte are reserved. */
6453 uint8_t uType = (uint8_t)(uValue >> cShift);
6454 if ((uType >= 8) || (uType == 2) || (uType == 3))
6455 {
6456 Log(("CPUM: Invalid PAT type at %u:%u in IA32_PAT: %#llx (%#llx)\n", cShift + 7, cShift, uValue, uType));
6457 return false;
6458 }
6459 }
6460 return true;
6461}
6462
6463
6464/**
6465 * Validates an EFER MSR write.
6466 *
6467 * @returns VBox status code.
6468 * @param pVM The cross context VM structure.
6469 * @param uCr0 The CR0 of the CPU corresponding to the EFER MSR.
6470 * @param uOldEfer Value of the previous EFER MSR on the CPU if any.
6471 * @param uNewEfer The new EFER MSR value being written.
6472 * @param puValidEfer Where to store the validated EFER (only updated if
6473 * this function returns VINF_SUCCESS).
6474 */
6475VMMDECL(int) CPUMQueryValidatedGuestEfer(PVM pVM, uint64_t uCr0, uint64_t uOldEfer, uint64_t uNewEfer, uint64_t *puValidEfer)
6476{
6477 uint32_t const fExtFeatures = pVM->cpum.s.aGuestCpuIdPatmExt[0].uEax >= 0x80000001
6478 ? pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx
6479 : 0;
6480 uint64_t fMask = 0;
6481 uint64_t const fIgnoreMask = MSR_K6_EFER_LMA;
6482
6483 /* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
6484 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_NX)
6485 fMask |= MSR_K6_EFER_NXE;
6486 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
6487 fMask |= MSR_K6_EFER_LME;
6488 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
6489 fMask |= MSR_K6_EFER_SCE;
6490 if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
6491 fMask |= MSR_K6_EFER_FFXSR;
6492 if (pVM->cpum.s.GuestFeatures.fSvm)
6493 fMask |= MSR_K6_EFER_SVME;
6494
6495 /* #GP(0) If anything outside the allowed bits is set. */
6496 if (uNewEfer & ~(fIgnoreMask | fMask))
6497 {
6498 Log(("CPUM: Settings disallowed EFER bit. uNewEfer=%#RX64 fAllowed=%#RX64 -> #GP(0)\n", uNewEfer, fMask));
6499 return VERR_CPUM_RAISE_GP_0;
6500 }
6501
6502 /* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if
6503 paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
6504 if ( (uOldEfer & MSR_K6_EFER_LME) != (uNewEfer & fMask & MSR_K6_EFER_LME)
6505 && (uCr0 & X86_CR0_PG))
6506 {
6507 Log(("CPUM: Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
6508 return VERR_CPUM_RAISE_GP_0;
6509 }
6510
6511 /* There are a few more: e.g. MSR_K6_EFER_LMSLE */
6512 AssertMsg(!(uNewEfer & ~( MSR_K6_EFER_NXE
6513 | MSR_K6_EFER_LME
6514 | MSR_K6_EFER_LMA /* ignored anyway */
6515 | MSR_K6_EFER_SCE
6516 | MSR_K6_EFER_FFXSR
6517 | MSR_K6_EFER_SVME)),
6518 ("Unexpected value %#RX64\n", uNewEfer));
6519
6520 *puValidEfer = (uOldEfer & ~fMask) | (uNewEfer & fMask);
6521 return VINF_SUCCESS;
6522}
6523
6524
6525/**
6526 * Fast way for HM to access the MSR_K8_TSC_AUX register.
6527 *
6528 * @returns The register value.
6529 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
6530 * @thread EMT(pVCpu)
6531 */
6532VMM_INT_DECL(uint64_t) CPUMGetGuestTscAux(PVMCPU pVCpu)
6533{
6534 Assert(!(pVCpu->cpum.s.Guest.fExtrn & CPUMCTX_EXTRN_TSC_AUX));
6535 return pVCpu->cpum.s.GuestMsrs.msr.TscAux;
6536}
6537
6538
6539/**
6540 * Fast way for HM to access the MSR_K8_TSC_AUX register.
6541 *
6542 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
6543 * @param uValue The new value.
6544 * @thread EMT(pVCpu)
6545 */
6546VMM_INT_DECL(void) CPUMSetGuestTscAux(PVMCPU pVCpu, uint64_t uValue)
6547{
6548 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_TSC_AUX;
6549 pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
6550}
6551
6552
6553/**
6554 * Fast way for HM to access the IA32_SPEC_CTRL register.
6555 *
6556 * @returns The register value.
6557 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
6558 * @thread EMT(pVCpu)
6559 */
6560VMM_INT_DECL(uint64_t) CPUMGetGuestSpecCtrl(PVMCPU pVCpu)
6561{
6562 return pVCpu->cpum.s.GuestMsrs.msr.SpecCtrl;
6563}
6564
6565
6566/**
6567 * Fast way for HM to access the IA32_SPEC_CTRL register.
6568 *
6569 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
6570 * @param uValue The new value.
6571 * @thread EMT(pVCpu)
6572 */
6573VMM_INT_DECL(void) CPUMSetGuestSpecCtrl(PVMCPU pVCpu, uint64_t uValue)
6574{
6575 pVCpu->cpum.s.GuestMsrs.msr.SpecCtrl = uValue;
6576}
6577
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