VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllMsrs.cpp@ 53404

Last change on this file since 53404 was 52770, checked in by vboxsync, 10 years ago

VMM/CPUM: Fix EFER WRMSR to ignore EFER.LMA bit, trunk regression caused by r96058.
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1/* $Id: CPUMAllMsrs.cpp 52770 2014-09-17 11:04:43Z vboxsync $ */
2/** @file
3 * CPUM - CPU MSR Registers.
4 */
5
6/*
7 * Copyright (C) 2013-2014 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_CPUM
22#include <VBox/vmm/cpum.h>
23#include <VBox/vmm/pdmapi.h>
24#include <VBox/vmm/hm.h>
25#include <VBox/vmm/tm.h>
26#include <VBox/vmm/gim.h>
27#include "CPUMInternal.h"
28#include <VBox/vmm/vm.h>
29#include <VBox/err.h>
30
31
32/*******************************************************************************
33* Defined Constants And Macros *
34*******************************************************************************/
35/**
36 * Validates the CPUMMSRRANGE::offCpumCpu value and declares a local variable
37 * pointing to it.
38 *
39 * ASSUMES sizeof(a_Type) is a power of two and that the member is aligned
40 * correctly.
41 */
42#define CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(a_pVCpu, a_pRange, a_Type, a_VarName) \
43 AssertMsgReturn( (a_pRange)->offCpumCpu >= 8 \
44 && (a_pRange)->offCpumCpu < sizeof(CPUMCPU) \
45 && !((a_pRange)->offCpumCpu & (RT_MIN(sizeof(a_Type), 8) - 1)) \
46 , ("offCpumCpu=%#x %s\n", (a_pRange)->offCpumCpu, (a_pRange)->szName), \
47 VERR_CPUM_MSR_BAD_CPUMCPU_OFFSET); \
48 a_Type *a_VarName = (a_Type *)((uintptr_t)&(a_pVCpu)->cpum.s + (a_pRange)->offCpumCpu)
49
50
51/*******************************************************************************
52* Structures and Typedefs *
53*******************************************************************************/
54
55/**
56 * Implements reading one or more MSRs.
57 *
58 * @returns VBox status code.
59 * @retval VINF_SUCCESS on success.
60 * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR).
61 *
62 * @param pVCpu Pointer to the VMCPU.
63 * @param idMsr The MSR we're reading.
64 * @param pRange The MSR range descriptor.
65 * @param puValue Where to return the value.
66 */
67typedef DECLCALLBACK(int) FNCPUMRDMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue);
68/** Pointer to a RDMSR worker for a specific MSR or range of MSRs. */
69typedef FNCPUMRDMSR *PFNCPUMRDMSR;
70
71
72/**
73 * Implements writing one or more MSRs.
74 *
75 * @retval VINF_SUCCESS on success.
76 * @retval VERR_CPUM_RAISE_GP_0 on failure.
77 *
78 * @param pVCpu Pointer to the VMCPU.
79 * @param idMsr The MSR we're writing.
80 * @param pRange The MSR range descriptor.
81 * @param uValue The value to set, ignored bits masked.
82 * @param uRawValue The raw value with the ignored bits not masked.
83 */
84typedef DECLCALLBACK(int) FNCPUMWRMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue);
85/** Pointer to a WRMSR worker for a specific MSR or range of MSRs. */
86typedef FNCPUMWRMSR *PFNCPUMWRMSR;
87
88
89
90/*
91 * Generic functions.
92 * Generic functions.
93 * Generic functions.
94 */
95
96
97/** @callback_method_impl{FNCPUMRDMSR} */
98static DECLCALLBACK(int) cpumMsrRd_FixedValue(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
99{
100 *puValue = pRange->uValue;
101 return VINF_SUCCESS;
102}
103
104
105/** @callback_method_impl{FNCPUMWRMSR} */
106static DECLCALLBACK(int) cpumMsrWr_IgnoreWrite(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
107{
108 Log(("CPUM: Ignoring WRMSR %#x (%s), %#llx\n", idMsr, pRange->szName, uValue));
109 return VINF_SUCCESS;
110}
111
112
113/** @callback_method_impl{FNCPUMRDMSR} */
114static DECLCALLBACK(int) cpumMsrRd_WriteOnly(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
115{
116 return VERR_CPUM_RAISE_GP_0;
117}
118
119
120/** @callback_method_impl{FNCPUMWRMSR} */
121static DECLCALLBACK(int) cpumMsrWr_ReadOnly(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
122{
123 Assert(pRange->fWrGpMask == UINT64_MAX);
124 return VERR_CPUM_RAISE_GP_0;
125}
126
127
128
129
130/*
131 * IA32
132 * IA32
133 * IA32
134 */
135
136/** @callback_method_impl{FNCPUMRDMSR} */
137static DECLCALLBACK(int) cpumMsrRd_Ia32P5McAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
138{
139 *puValue = 0; /** @todo implement machine check injection. */
140 return VINF_SUCCESS;
141}
142
143
144/** @callback_method_impl{FNCPUMWRMSR} */
145static DECLCALLBACK(int) cpumMsrWr_Ia32P5McAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
146{
147 /** @todo implement machine check injection. */
148 return VINF_SUCCESS;
149}
150
151
152/** @callback_method_impl{FNCPUMRDMSR} */
153static DECLCALLBACK(int) cpumMsrRd_Ia32P5McType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
154{
155 *puValue = 0; /** @todo implement machine check injection. */
156 return VINF_SUCCESS;
157}
158
159
160/** @callback_method_impl{FNCPUMWRMSR} */
161static DECLCALLBACK(int) cpumMsrWr_Ia32P5McType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
162{
163 /** @todo implement machine check injection. */
164 return VINF_SUCCESS;
165}
166
167
168/** @callback_method_impl{FNCPUMRDMSR} */
169static DECLCALLBACK(int) cpumMsrRd_Ia32TimestampCounter(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
170{
171 *puValue = TMCpuTickGet(pVCpu);
172 return VINF_SUCCESS;
173}
174
175
176/** @callback_method_impl{FNCPUMWRMSR} */
177static DECLCALLBACK(int) cpumMsrWr_Ia32TimestampCounter(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
178{
179 TMCpuTickSet(pVCpu->CTX_SUFF(pVM), pVCpu, uValue);
180 return VINF_SUCCESS;
181}
182
183
184/** @callback_method_impl{FNCPUMRDMSR} */
185static DECLCALLBACK(int) cpumMsrRd_Ia32PlatformId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
186{
187 uint64_t uValue = pRange->uValue;
188 if (uValue & 0x1f00)
189 {
190 /* Max allowed bus ratio present. */
191 /** @todo Implement scaled BUS frequency. */
192 }
193
194 *puValue = uValue;
195 return VINF_SUCCESS;
196}
197
198
199/** @callback_method_impl{FNCPUMRDMSR} */
200static DECLCALLBACK(int) cpumMsrRd_Ia32ApicBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
201{
202 PVM pVM = pVCpu->CTX_SUFF(pVM);
203#if 0 /** @todo Sort this one out properly. Evidence from ticks 12240 and 12875 suggest the apic base is still readable even
204 * after the apic has been diabled. That makes common sense too. What we need to do here, though, is check whether
205 * there is an APIC device associated with the VM, and GP if there isn't. But that's for later. */
206 if ( !pVM->cpum.s.GuestFeatures.fApic
207 && !pVM->cpum.s.GuestFeatures.fX2Apic)
208 {
209 Log(("CPUM: %s, apic not present -> GP\n", pRange->szName));
210 return VERR_CPUM_RAISE_GP_0;
211 }
212#endif
213
214 *puValue = pVCpu->cpum.s.Guest.msrApicBase;
215 return VINF_SUCCESS;
216}
217
218
219/** @callback_method_impl{FNCPUMWRMSR} */
220static DECLCALLBACK(int) cpumMsrWr_Ia32ApicBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
221{
222 int rc = PDMApicSetBase(pVCpu, uValue);
223 if (rc != VINF_SUCCESS)
224 rc = VERR_CPUM_RAISE_GP_0;
225 return VINF_SUCCESS;
226}
227
228
229/** @callback_method_impl{FNCPUMRDMSR} */
230static DECLCALLBACK(int) cpumMsrRd_Ia32FeatureControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
231{
232 *puValue = 1; /* Locked, no VT-X, no SYSENTER micromanagement. */
233 return VINF_SUCCESS;
234}
235
236
237/** @callback_method_impl{FNCPUMWRMSR} */
238static DECLCALLBACK(int) cpumMsrWr_Ia32FeatureControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
239{
240 return VERR_CPUM_RAISE_GP_0;
241}
242
243
244/** @callback_method_impl{FNCPUMRDMSR} */
245static DECLCALLBACK(int) cpumMsrRd_Ia32BiosSignId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
246{
247 /** @todo fake microcode update. */
248 *puValue = pRange->uValue;
249 return VINF_SUCCESS;
250}
251
252
253/** @callback_method_impl{FNCPUMWRMSR} */
254static DECLCALLBACK(int) cpumMsrWr_Ia32BiosSignId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
255{
256 /* Normally, zero is written to Ia32BiosSignId before reading it in order
257 to select the signature instead of the BBL_CR_D3 behaviour. The GP mask
258 of the database entry should take care of most illegal writes for now, so
259 just ignore all writes atm. */
260 return VINF_SUCCESS;
261}
262
263
264/** @callback_method_impl{FNCPUMWRMSR} */
265static DECLCALLBACK(int) cpumMsrWr_Ia32BiosUpdateTrigger(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
266{
267 /** @todo Fake bios update trigger better. The value is the address to an
268 * update package, I think. We should probably GP if it's invalid. */
269 return VINF_SUCCESS;
270}
271
272
273/** @callback_method_impl{FNCPUMRDMSR} */
274static DECLCALLBACK(int) cpumMsrRd_Ia32SmmMonitorCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
275{
276 /** @todo SMM. */
277 *puValue = 0;
278 return VINF_SUCCESS;
279}
280
281
282/** @callback_method_impl{FNCPUMWRMSR} */
283static DECLCALLBACK(int) cpumMsrWr_Ia32SmmMonitorCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
284{
285 /** @todo SMM. */
286 return VINF_SUCCESS;
287}
288
289
290/** @callback_method_impl{FNCPUMRDMSR} */
291static DECLCALLBACK(int) cpumMsrRd_Ia32PmcN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
292{
293 /** @todo check CPUID leaf 0ah. */
294 *puValue = 0;
295 return VINF_SUCCESS;
296}
297
298
299/** @callback_method_impl{FNCPUMWRMSR} */
300static DECLCALLBACK(int) cpumMsrWr_Ia32PmcN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
301{
302 /** @todo check CPUID leaf 0ah. */
303 return VINF_SUCCESS;
304}
305
306
307/** @callback_method_impl{FNCPUMRDMSR} */
308static DECLCALLBACK(int) cpumMsrRd_Ia32MonitorFilterLineSize(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
309{
310 /** @todo return 0x1000 if we try emulate mwait 100% correctly. */
311 *puValue = 0x40; /** @todo Change to CPU cache line size. */
312 return VINF_SUCCESS;
313}
314
315
316/** @callback_method_impl{FNCPUMWRMSR} */
317static DECLCALLBACK(int) cpumMsrWr_Ia32MonitorFilterLineSize(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
318{
319 /** @todo should remember writes, though it's supposedly something only a BIOS
320 * would write so, it's not extremely important. */
321 return VINF_SUCCESS;
322}
323
324/** @callback_method_impl{FNCPUMRDMSR} */
325static DECLCALLBACK(int) cpumMsrRd_Ia32MPerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
326{
327 /** @todo Read MPERF: Adjust against previously written MPERF value. Is TSC
328 * what we want? */
329 *puValue = TMCpuTickGet(pVCpu);
330 return VINF_SUCCESS;
331}
332
333
334/** @callback_method_impl{FNCPUMWRMSR} */
335static DECLCALLBACK(int) cpumMsrWr_Ia32MPerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
336{
337 /** @todo Write MPERF: Calc adjustment. */
338 return VINF_SUCCESS;
339}
340
341
342/** @callback_method_impl{FNCPUMRDMSR} */
343static DECLCALLBACK(int) cpumMsrRd_Ia32APerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
344{
345 /** @todo Read APERF: Adjust against previously written MPERF value. Is TSC
346 * what we want? */
347 *puValue = TMCpuTickGet(pVCpu);
348 return VINF_SUCCESS;
349}
350
351
352/** @callback_method_impl{FNCPUMWRMSR} */
353static DECLCALLBACK(int) cpumMsrWr_Ia32APerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
354{
355 /** @todo Write APERF: Calc adjustment. */
356 return VINF_SUCCESS;
357}
358
359
360/** @callback_method_impl{FNCPUMWRMSR} */
361static DECLCALLBACK(int) cpumMsrRd_Ia32MtrrCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
362{
363 /* This is currently a bit weird. :-) */
364 uint8_t const cVariableRangeRegs = 0;
365 bool const fSystemManagementRangeRegisters = false;
366 bool const fFixedRangeRegisters = false;
367 bool const fWriteCombiningType = false;
368 *puValue = cVariableRangeRegs
369 | (fFixedRangeRegisters ? RT_BIT_64(8) : 0)
370 | (fWriteCombiningType ? RT_BIT_64(10) : 0)
371 | (fSystemManagementRangeRegisters ? RT_BIT_64(11) : 0);
372 return VINF_SUCCESS;
373}
374
375
376/** @callback_method_impl{FNCPUMRDMSR} */
377static DECLCALLBACK(int) cpumMsrRd_Ia32MtrrPhysBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
378{
379 /** @todo Implement variable MTRR storage. */
380 Assert(pRange->uValue == (idMsr - 0x200) / 2);
381 *puValue = 0;
382 return VINF_SUCCESS;
383}
384
385
386/** @callback_method_impl{FNCPUMWRMSR} */
387static DECLCALLBACK(int) cpumMsrWr_Ia32MtrrPhysBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
388{
389 /*
390 * Validate the value.
391 */
392 Assert(pRange->uValue == (idMsr - 0x200) / 2);
393
394 if ((uValue & 0xff) >= 7)
395 {
396 Log(("CPUM: Invalid type set writing MTRR PhysBase MSR %#x: %#llx (%#llx)\n", idMsr, uValue, uValue & 0xff));
397 return VERR_CPUM_RAISE_GP_0;
398 }
399
400 uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
401 if (fInvPhysMask & uValue)
402 {
403 Log(("CPUM: Invalid physical address bits set writing MTRR PhysBase MSR %#x: %#llx (%#llx)\n",
404 idMsr, uValue, uValue & fInvPhysMask));
405 return VERR_CPUM_RAISE_GP_0;
406 }
407
408 /*
409 * Store it.
410 */
411 /** @todo Implement variable MTRR storage. */
412 return VINF_SUCCESS;
413}
414
415
416/** @callback_method_impl{FNCPUMRDMSR} */
417static DECLCALLBACK(int) cpumMsrRd_Ia32MtrrPhysMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
418{
419 /** @todo Implement variable MTRR storage. */
420 Assert(pRange->uValue == (idMsr - 0x200) / 2);
421 *puValue = 0;
422 return VINF_SUCCESS;
423}
424
425
426/** @callback_method_impl{FNCPUMWRMSR} */
427static DECLCALLBACK(int) cpumMsrWr_Ia32MtrrPhysMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
428{
429 /*
430 * Validate the value.
431 */
432 Assert(pRange->uValue == (idMsr - 0x200) / 2);
433
434 uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
435 if (fInvPhysMask & uValue)
436 {
437 Log(("CPUM: Invalid physical address bits set writing MTRR PhysMask MSR %#x: %#llx (%#llx)\n",
438 idMsr, uValue, uValue & fInvPhysMask));
439 return VERR_CPUM_RAISE_GP_0;
440 }
441
442 /*
443 * Store it.
444 */
445 /** @todo Implement variable MTRR storage. */
446 return VINF_SUCCESS;
447}
448
449
450/** @callback_method_impl{FNCPUMRDMSR} */
451static DECLCALLBACK(int) cpumMsrRd_Ia32MtrrFixed(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
452{
453 CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(pVCpu, pRange, uint64_t, puFixedMtrr);
454 *puValue = *puFixedMtrr;
455 return VINF_SUCCESS;
456}
457
458
459/** @callback_method_impl{FNCPUMWRMSR} */
460static DECLCALLBACK(int) cpumMsrWr_Ia32MtrrFixed(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
461{
462 CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(pVCpu, pRange, uint64_t, puFixedMtrr);
463 for (uint32_t cShift = 0; cShift < 63; cShift += 8)
464 {
465 uint8_t uType = (uint8_t)(uValue >> cShift);
466 if (uType >= 7)
467 {
468 Log(("CPUM: Invalid MTRR type at %u:%u in fixed range (%#x/%s): %#llx (%#llx)\n",
469 cShift + 7, cShift, idMsr, pRange->szName, uValue, uType));
470 return VERR_CPUM_RAISE_GP_0;
471 }
472 }
473 *puFixedMtrr = uValue;
474 return VINF_SUCCESS;
475}
476
477
478/** @callback_method_impl{FNCPUMRDMSR} */
479static DECLCALLBACK(int) cpumMsrRd_Ia32MtrrDefType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
480{
481 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType;
482 return VINF_SUCCESS;
483}
484
485
486/** @callback_method_impl{FNCPUMWRMSR} */
487static DECLCALLBACK(int) cpumMsrWr_Ia32MtrrDefType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
488{
489 if ((uValue & 0xff) >= 7)
490 {
491 Log(("CPUM: Invalid MTRR default type value: %#llx (%#llx)\n", pRange->szName, uValue, uValue & 0xff));
492 return VERR_CPUM_RAISE_GP_0;
493 }
494
495 pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType = uValue;
496 return VINF_SUCCESS;
497}
498
499
500/** @callback_method_impl{FNCPUMRDMSR} */
501static DECLCALLBACK(int) cpumMsrRd_Ia32Pat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
502{
503 *puValue = pVCpu->cpum.s.Guest.msrPAT;
504 return VINF_SUCCESS;
505}
506
507
508/** @callback_method_impl{FNCPUMWRMSR} */
509static DECLCALLBACK(int) cpumMsrWr_Ia32Pat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
510{
511 pVCpu->cpum.s.Guest.msrPAT = uValue;
512 return VINF_SUCCESS;
513}
514
515
516/** @callback_method_impl{FNCPUMRDMSR} */
517static DECLCALLBACK(int) cpumMsrRd_Ia32SysEnterCs(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
518{
519 *puValue = pVCpu->cpum.s.Guest.SysEnter.cs;
520 return VINF_SUCCESS;
521}
522
523
524/** @callback_method_impl{FNCPUMWRMSR} */
525static DECLCALLBACK(int) cpumMsrWr_Ia32SysEnterCs(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
526{
527 /* Note! We used to mask this by 0xffff, but turns out real HW doesn't and
528 there are generally 32-bit working bits backing this register. */
529 pVCpu->cpum.s.Guest.SysEnter.cs = uValue;
530 return VINF_SUCCESS;
531}
532
533
534/** @callback_method_impl{FNCPUMRDMSR} */
535static DECLCALLBACK(int) cpumMsrRd_Ia32SysEnterEsp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
536{
537 *puValue = pVCpu->cpum.s.Guest.SysEnter.esp;
538 return VINF_SUCCESS;
539}
540
541
542/** @callback_method_impl{FNCPUMWRMSR} */
543static DECLCALLBACK(int) cpumMsrWr_Ia32SysEnterEsp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
544{
545 if (X86_IS_CANONICAL(uValue))
546 {
547 pVCpu->cpum.s.Guest.SysEnter.esp = uValue;
548 return VINF_SUCCESS;
549 }
550 Log(("CPUM: IA32_SYSENTER_ESP not canonical! %#llx\n", uValue));
551 return VERR_CPUM_RAISE_GP_0;
552}
553
554
555/** @callback_method_impl{FNCPUMRDMSR} */
556static DECLCALLBACK(int) cpumMsrRd_Ia32SysEnterEip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
557{
558 *puValue = pVCpu->cpum.s.Guest.SysEnter.eip;
559 return VINF_SUCCESS;
560}
561
562
563/** @callback_method_impl{FNCPUMWRMSR} */
564static DECLCALLBACK(int) cpumMsrWr_Ia32SysEnterEip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
565{
566 if (X86_IS_CANONICAL(uValue))
567 {
568 pVCpu->cpum.s.Guest.SysEnter.eip = uValue;
569 return VINF_SUCCESS;
570 }
571#ifdef IN_RING3
572 LogRel(("CPUM: IA32_SYSENTER_EIP not canonical! %#llx\n", uValue));
573#else
574 Log(("CPUM: IA32_SYSENTER_EIP not canonical! %#llx\n", uValue));
575#endif
576 return VERR_CPUM_RAISE_GP_0;
577}
578
579
580/** @callback_method_impl{FNCPUMRDMSR} */
581static DECLCALLBACK(int) cpumMsrRd_Ia32McgCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
582{
583#if 0 /** @todo implement machine checks. */
584 *puValue = pRange->uValue & (RT_BIT_64(8) | 0);
585#else
586 *puValue = 0;
587#endif
588 return VINF_SUCCESS;
589}
590
591
592/** @callback_method_impl{FNCPUMRDMSR} */
593static DECLCALLBACK(int) cpumMsrRd_Ia32McgStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
594{
595 /** @todo implement machine checks. */
596 *puValue = 0;
597 return VINF_SUCCESS;
598}
599
600
601/** @callback_method_impl{FNCPUMWRMSR} */
602static DECLCALLBACK(int) cpumMsrWr_Ia32McgStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
603{
604 /** @todo implement machine checks. */
605 return VINF_SUCCESS;
606}
607
608
609/** @callback_method_impl{FNCPUMRDMSR} */
610static DECLCALLBACK(int) cpumMsrRd_Ia32McgCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
611{
612 /** @todo implement machine checks. */
613 *puValue = 0;
614 return VINF_SUCCESS;
615}
616
617
618/** @callback_method_impl{FNCPUMWRMSR} */
619static DECLCALLBACK(int) cpumMsrWr_Ia32McgCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
620{
621 /** @todo implement machine checks. */
622 return VINF_SUCCESS;
623}
624
625
626/** @callback_method_impl{FNCPUMRDMSR} */
627static DECLCALLBACK(int) cpumMsrRd_Ia32DebugCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
628{
629 /** @todo implement IA32_DEBUGCTL. */
630 *puValue = 0;
631 return VINF_SUCCESS;
632}
633
634
635/** @callback_method_impl{FNCPUMWRMSR} */
636static DECLCALLBACK(int) cpumMsrWr_Ia32DebugCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
637{
638 /** @todo implement IA32_DEBUGCTL. */
639 return VINF_SUCCESS;
640}
641
642
643/** @callback_method_impl{FNCPUMRDMSR} */
644static DECLCALLBACK(int) cpumMsrRd_Ia32SmrrPhysBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
645{
646 /** @todo implement intel SMM. */
647 *puValue = 0;
648 return VINF_SUCCESS;
649}
650
651
652/** @callback_method_impl{FNCPUMWRMSR} */
653static DECLCALLBACK(int) cpumMsrWr_Ia32SmrrPhysBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
654{
655 /** @todo implement intel SMM. */
656 return VERR_CPUM_RAISE_GP_0;
657}
658
659
660/** @callback_method_impl{FNCPUMRDMSR} */
661static DECLCALLBACK(int) cpumMsrRd_Ia32SmrrPhysMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
662{
663 /** @todo implement intel SMM. */
664 *puValue = 0;
665 return VINF_SUCCESS;
666}
667
668
669/** @callback_method_impl{FNCPUMWRMSR} */
670static DECLCALLBACK(int) cpumMsrWr_Ia32SmrrPhysMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
671{
672 /** @todo implement intel SMM. */
673 return VERR_CPUM_RAISE_GP_0;
674}
675
676
677/** @callback_method_impl{FNCPUMRDMSR} */
678static DECLCALLBACK(int) cpumMsrRd_Ia32PlatformDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
679{
680 /** @todo implement intel direct cache access (DCA)?? */
681 *puValue = 0;
682 return VINF_SUCCESS;
683}
684
685
686/** @callback_method_impl{FNCPUMWRMSR} */
687static DECLCALLBACK(int) cpumMsrWr_Ia32PlatformDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
688{
689 /** @todo implement intel direct cache access (DCA)?? */
690 return VINF_SUCCESS;
691}
692
693
694/** @callback_method_impl{FNCPUMRDMSR} */
695static DECLCALLBACK(int) cpumMsrRd_Ia32CpuDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
696{
697 /** @todo implement intel direct cache access (DCA)?? */
698 *puValue = 0;
699 return VINF_SUCCESS;
700}
701
702
703/** @callback_method_impl{FNCPUMRDMSR} */
704static DECLCALLBACK(int) cpumMsrRd_Ia32Dca0Cap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
705{
706 /** @todo implement intel direct cache access (DCA)?? */
707 *puValue = 0;
708 return VINF_SUCCESS;
709}
710
711
712/** @callback_method_impl{FNCPUMWRMSR} */
713static DECLCALLBACK(int) cpumMsrWr_Ia32Dca0Cap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
714{
715 /** @todo implement intel direct cache access (DCA)?? */
716 return VINF_SUCCESS;
717}
718
719
720/** @callback_method_impl{FNCPUMRDMSR} */
721static DECLCALLBACK(int) cpumMsrRd_Ia32PerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
722{
723 /** @todo implement IA32_PERFEVTSEL0+. */
724 *puValue = 0;
725 return VINF_SUCCESS;
726}
727
728
729/** @callback_method_impl{FNCPUMWRMSR} */
730static DECLCALLBACK(int) cpumMsrWr_Ia32PerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
731{
732 /** @todo implement IA32_PERFEVTSEL0+. */
733 return VINF_SUCCESS;
734}
735
736
737/** @callback_method_impl{FNCPUMRDMSR} */
738static DECLCALLBACK(int) cpumMsrRd_Ia32PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
739{
740 uint64_t uValue = pRange->uValue;
741
742 /* Always provide the max bus ratio for now. XNU expects it. */
743 uValue &= ~((UINT64_C(0x1f) << 40) | RT_BIT_64(46));
744
745 PVM pVM = pVCpu->CTX_SUFF(pVM);
746 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
747 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
748 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
749 if (uTscRatio > 0x1f)
750 uTscRatio = 0x1f;
751 uValue |= (uint64_t)uTscRatio << 40;
752
753 *puValue = uValue;
754 return VINF_SUCCESS;
755}
756
757
758/** @callback_method_impl{FNCPUMWRMSR} */
759static DECLCALLBACK(int) cpumMsrWr_Ia32PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
760{
761 /* Pentium4 allows writing, but all bits are ignored. */
762 return VINF_SUCCESS;
763}
764
765
766/** @callback_method_impl{FNCPUMRDMSR} */
767static DECLCALLBACK(int) cpumMsrRd_Ia32PerfCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
768{
769 /** @todo implement IA32_PERFCTL. */
770 *puValue = 0;
771 return VINF_SUCCESS;
772}
773
774
775/** @callback_method_impl{FNCPUMWRMSR} */
776static DECLCALLBACK(int) cpumMsrWr_Ia32PerfCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
777{
778 /** @todo implement IA32_PERFCTL. */
779 return VINF_SUCCESS;
780}
781
782
783/** @callback_method_impl{FNCPUMRDMSR} */
784static DECLCALLBACK(int) cpumMsrRd_Ia32FixedCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
785{
786 /** @todo implement IA32_FIXED_CTRn (fixed performance counters). */
787 *puValue = 0;
788 return VINF_SUCCESS;
789}
790
791
792/** @callback_method_impl{FNCPUMWRMSR} */
793static DECLCALLBACK(int) cpumMsrWr_Ia32FixedCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
794{
795 /** @todo implement IA32_FIXED_CTRn (fixed performance counters). */
796 return VINF_SUCCESS;
797}
798
799
800/** @callback_method_impl{FNCPUMRDMSR} */
801static DECLCALLBACK(int) cpumMsrRd_Ia32PerfCapabilities(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
802{
803 /** @todo implement performance counters. */
804 *puValue = 0;
805 return VINF_SUCCESS;
806}
807
808
809/** @callback_method_impl{FNCPUMWRMSR} */
810static DECLCALLBACK(int) cpumMsrWr_Ia32PerfCapabilities(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
811{
812 /** @todo implement performance counters. */
813 return VINF_SUCCESS;
814}
815
816
817/** @callback_method_impl{FNCPUMRDMSR} */
818static DECLCALLBACK(int) cpumMsrRd_Ia32FixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
819{
820 /** @todo implement performance counters. */
821 *puValue = 0;
822 return VINF_SUCCESS;
823}
824
825
826/** @callback_method_impl{FNCPUMWRMSR} */
827static DECLCALLBACK(int) cpumMsrWr_Ia32FixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
828{
829 /** @todo implement performance counters. */
830 return VINF_SUCCESS;
831}
832
833
834/** @callback_method_impl{FNCPUMRDMSR} */
835static DECLCALLBACK(int) cpumMsrRd_Ia32PerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
836{
837 /** @todo implement performance counters. */
838 *puValue = 0;
839 return VINF_SUCCESS;
840}
841
842
843/** @callback_method_impl{FNCPUMWRMSR} */
844static DECLCALLBACK(int) cpumMsrWr_Ia32PerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
845{
846 /** @todo implement performance counters. */
847 return VINF_SUCCESS;
848}
849
850
851/** @callback_method_impl{FNCPUMRDMSR} */
852static DECLCALLBACK(int) cpumMsrRd_Ia32PerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
853{
854 /** @todo implement performance counters. */
855 *puValue = 0;
856 return VINF_SUCCESS;
857}
858
859
860/** @callback_method_impl{FNCPUMWRMSR} */
861static DECLCALLBACK(int) cpumMsrWr_Ia32PerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
862{
863 /** @todo implement performance counters. */
864 return VINF_SUCCESS;
865}
866
867
868/** @callback_method_impl{FNCPUMRDMSR} */
869static DECLCALLBACK(int) cpumMsrRd_Ia32PerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
870{
871 /** @todo implement performance counters. */
872 *puValue = 0;
873 return VINF_SUCCESS;
874}
875
876
877/** @callback_method_impl{FNCPUMWRMSR} */
878static DECLCALLBACK(int) cpumMsrWr_Ia32PerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
879{
880 /** @todo implement performance counters. */
881 return VINF_SUCCESS;
882}
883
884
885/** @callback_method_impl{FNCPUMRDMSR} */
886static DECLCALLBACK(int) cpumMsrRd_Ia32PebsEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
887{
888 /** @todo implement performance counters. */
889 *puValue = 0;
890 return VINF_SUCCESS;
891}
892
893
894/** @callback_method_impl{FNCPUMWRMSR} */
895static DECLCALLBACK(int) cpumMsrWr_Ia32PebsEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
896{
897 /** @todo implement performance counters. */
898 return VINF_SUCCESS;
899}
900
901
902/** @callback_method_impl{FNCPUMRDMSR} */
903static DECLCALLBACK(int) cpumMsrRd_Ia32ClockModulation(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
904{
905 /** @todo implement IA32_CLOCK_MODULATION. */
906 *puValue = 0;
907 return VINF_SUCCESS;
908}
909
910
911/** @callback_method_impl{FNCPUMWRMSR} */
912static DECLCALLBACK(int) cpumMsrWr_Ia32ClockModulation(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
913{
914 /** @todo implement IA32_CLOCK_MODULATION. */
915 return VINF_SUCCESS;
916}
917
918
919/** @callback_method_impl{FNCPUMRDMSR} */
920static DECLCALLBACK(int) cpumMsrRd_Ia32ThermInterrupt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
921{
922 /** @todo implement IA32_THERM_INTERRUPT. */
923 *puValue = 0;
924 return VINF_SUCCESS;
925}
926
927
928/** @callback_method_impl{FNCPUMWRMSR} */
929static DECLCALLBACK(int) cpumMsrWr_Ia32ThermInterrupt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
930{
931 /** @todo implement IA32_THERM_STATUS. */
932 return VINF_SUCCESS;
933}
934
935
936/** @callback_method_impl{FNCPUMRDMSR} */
937static DECLCALLBACK(int) cpumMsrRd_Ia32ThermStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
938{
939 /** @todo implement IA32_THERM_STATUS. */
940 *puValue = 0;
941 return VINF_SUCCESS;
942}
943
944
945/** @callback_method_impl{FNCPUMWRMSR} */
946static DECLCALLBACK(int) cpumMsrWr_Ia32ThermStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
947{
948 /** @todo implement IA32_THERM_INTERRUPT. */
949 return VINF_SUCCESS;
950}
951
952
953/** @callback_method_impl{FNCPUMRDMSR} */
954static DECLCALLBACK(int) cpumMsrRd_Ia32Therm2Ctl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
955{
956 /** @todo implement IA32_THERM2_CTL. */
957 *puValue = 0;
958 return VINF_SUCCESS;
959}
960
961
962/** @callback_method_impl{FNCPUMWRMSR} */
963static DECLCALLBACK(int) cpumMsrWr_Ia32Therm2Ctl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
964{
965 /** @todo implement IA32_THERM2_CTL. */
966 return VINF_SUCCESS;
967}
968
969
970/** @callback_method_impl{FNCPUMRDMSR} */
971static DECLCALLBACK(int) cpumMsrRd_Ia32MiscEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
972{
973 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
974 return VINF_SUCCESS;
975}
976
977
978/** @callback_method_impl{FNCPUMWRMSR} */
979static DECLCALLBACK(int) cpumMsrWr_Ia32MiscEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
980{
981#ifdef LOG_ENABLED
982 uint64_t const uOld = pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
983#endif
984
985 /* Unsupported bits are generally ignored and stripped by the MSR range
986 entry that got us here. So, we just need to preserve fixed bits. */
987 pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = uValue
988 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
989 | MSR_IA32_MISC_ENABLE_BTS_UNAVAIL;
990
991 Log(("CPUM: IA32_MISC_ENABLE; old=%#llx written=%#llx => %#llx\n",
992 uOld, uValue, pVCpu->cpum.s.GuestMsrs.msr.MiscEnable));
993
994 /** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
995 /** @todo Wire up MSR_IA32_MISC_ENABLE_XD_DISABLE. */
996 return VINF_SUCCESS;
997}
998
999
1000/** @callback_method_impl{FNCPUMRDMSR} */
1001static DECLCALLBACK(int) cpumMsrRd_Ia32McCtlStatusAddrMiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1002{
1003 /** @todo Implement machine check exception injection. */
1004 switch (idMsr & 3)
1005 {
1006 case 0:
1007 case 1:
1008 *puValue = 0;
1009 break;
1010
1011 /* The ADDR and MISC registers aren't accessible since the
1012 corresponding STATUS bits are zero. */
1013 case 2:
1014 Log(("CPUM: Reading IA32_MCi_ADDR %#x -> #GP\n", idMsr));
1015 return VERR_CPUM_RAISE_GP_0;
1016 case 3:
1017 Log(("CPUM: Reading IA32_MCi_MISC %#x -> #GP\n", idMsr));
1018 return VERR_CPUM_RAISE_GP_0;
1019 }
1020 return VINF_SUCCESS;
1021}
1022
1023
1024/** @callback_method_impl{FNCPUMWRMSR} */
1025static DECLCALLBACK(int) cpumMsrWr_Ia32McCtlStatusAddrMiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1026{
1027 switch (idMsr & 3)
1028 {
1029 case 0:
1030 /* Ignore writes to the CTL register. */
1031 break;
1032
1033 case 1:
1034 /* According to specs, the STATUS register can only be written to
1035 with the value 0. VBoxCpuReport thinks different for a
1036 Pentium M Dothan, but implementing according to specs now. */
1037 if (uValue != 0)
1038 {
1039 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_STATUS %#x -> #GP\n", uValue, idMsr));
1040 return VERR_CPUM_RAISE_GP_0;
1041 }
1042 break;
1043
1044 /* Specs states that ADDR and MISC can be cleared by writing zeros.
1045 Writing 1s will GP. Need to figure out how this relates to the
1046 ADDRV and MISCV status flags. If writing is independent of those
1047 bits, we need to know whether the CPU really implements them since
1048 that is exposed by writing 0 to them.
1049 Implementing the solution with the fewer GPs for now. */
1050 case 2:
1051 if (uValue != 0)
1052 {
1053 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_ADDR %#x -> #GP\n", uValue, idMsr));
1054 return VERR_CPUM_RAISE_GP_0;
1055 }
1056 break;
1057 case 3:
1058 if (uValue != 0)
1059 {
1060 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_MISC %#x -> #GP\n", uValue, idMsr));
1061 return VERR_CPUM_RAISE_GP_0;
1062 }
1063 break;
1064 }
1065 return VINF_SUCCESS;
1066}
1067
1068
1069/** @callback_method_impl{FNCPUMRDMSR} */
1070static DECLCALLBACK(int) cpumMsrRd_Ia32McNCtl2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1071{
1072 /** @todo Implement machine check exception injection. */
1073 *puValue = 0;
1074 return VINF_SUCCESS;
1075}
1076
1077
1078/** @callback_method_impl{FNCPUMWRMSR} */
1079static DECLCALLBACK(int) cpumMsrWr_Ia32McNCtl2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1080{
1081 /** @todo Implement machine check exception injection. */
1082 return VINF_SUCCESS;
1083}
1084
1085
1086/** @callback_method_impl{FNCPUMRDMSR} */
1087static DECLCALLBACK(int) cpumMsrRd_Ia32DsArea(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1088{
1089 /** @todo implement IA32_DS_AREA. */
1090 *puValue = 0;
1091 return VINF_SUCCESS;
1092}
1093
1094
1095/** @callback_method_impl{FNCPUMWRMSR} */
1096static DECLCALLBACK(int) cpumMsrWr_Ia32DsArea(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1097{
1098 return VINF_SUCCESS;
1099}
1100
1101
1102/** @callback_method_impl{FNCPUMRDMSR} */
1103static DECLCALLBACK(int) cpumMsrRd_Ia32TscDeadline(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1104{
1105 /** @todo implement TSC deadline timer. */
1106 *puValue = 0;
1107 return VINF_SUCCESS;
1108}
1109
1110
1111/** @callback_method_impl{FNCPUMWRMSR} */
1112static DECLCALLBACK(int) cpumMsrWr_Ia32TscDeadline(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1113{
1114 /** @todo implement TSC deadline timer. */
1115 return VINF_SUCCESS;
1116}
1117
1118
1119/** @callback_method_impl{FNCPUMRDMSR} */
1120static DECLCALLBACK(int) cpumMsrRd_Ia32X2ApicN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1121{
1122 int rc = PDMApicReadMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, puValue);
1123 if (rc != VINF_SUCCESS)
1124 {
1125 Log(("CPUM: X2APIC %#x read => %Rrc => #GP\n", idMsr, rc));
1126 return VERR_CPUM_RAISE_GP_0;
1127 }
1128 return VINF_SUCCESS;
1129}
1130
1131
1132/** @callback_method_impl{FNCPUMWRMSR} */
1133static DECLCALLBACK(int) cpumMsrWr_Ia32X2ApicN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1134{
1135 int rc = PDMApicWriteMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, uValue);
1136 if (rc != VINF_SUCCESS)
1137 {
1138 Log(("CPUM: X2APIC %#x write %#llx => %Rrc => #GP\n", idMsr, rc, uValue));
1139 return VERR_CPUM_RAISE_GP_0;
1140 }
1141 return VINF_SUCCESS;
1142}
1143
1144
1145/** @callback_method_impl{FNCPUMRDMSR} */
1146static DECLCALLBACK(int) cpumMsrRd_Ia32DebugInterface(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1147{
1148 /** @todo IA32_DEBUG_INTERFACE (no docs) */
1149 *puValue = 0;
1150 return VINF_SUCCESS;
1151}
1152
1153
1154/** @callback_method_impl{FNCPUMWRMSR} */
1155static DECLCALLBACK(int) cpumMsrWr_Ia32DebugInterface(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1156{
1157 /** @todo IA32_DEBUG_INTERFACE (no docs) */
1158 return VINF_SUCCESS;
1159}
1160
1161
1162/** @callback_method_impl{FNCPUMRDMSR} */
1163static DECLCALLBACK(int) cpumMsrRd_Ia32VmxBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1164{
1165 *puValue = 0;
1166 return VINF_SUCCESS;
1167}
1168
1169
1170/** @callback_method_impl{FNCPUMRDMSR} */
1171static DECLCALLBACK(int) cpumMsrRd_Ia32VmxPinbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1172{
1173 *puValue = 0;
1174 return VINF_SUCCESS;
1175}
1176
1177
1178/** @callback_method_impl{FNCPUMRDMSR} */
1179static DECLCALLBACK(int) cpumMsrRd_Ia32VmxProcbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1180{
1181 *puValue = 0;
1182 return VINF_SUCCESS;
1183}
1184
1185
1186/** @callback_method_impl{FNCPUMRDMSR} */
1187static DECLCALLBACK(int) cpumMsrRd_Ia32VmxExitCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1188{
1189 *puValue = 0;
1190 return VINF_SUCCESS;
1191}
1192
1193
1194/** @callback_method_impl{FNCPUMRDMSR} */
1195static DECLCALLBACK(int) cpumMsrRd_Ia32VmxEntryCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1196{
1197 *puValue = 0;
1198 return VINF_SUCCESS;
1199}
1200
1201
1202/** @callback_method_impl{FNCPUMRDMSR} */
1203static DECLCALLBACK(int) cpumMsrRd_Ia32VmxMisc(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1204{
1205 *puValue = 0;
1206 return VINF_SUCCESS;
1207}
1208
1209
1210/** @callback_method_impl{FNCPUMRDMSR} */
1211static DECLCALLBACK(int) cpumMsrRd_Ia32VmxCr0Fixed0(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1212{
1213 *puValue = 0;
1214 return VINF_SUCCESS;
1215}
1216
1217
1218/** @callback_method_impl{FNCPUMRDMSR} */
1219static DECLCALLBACK(int) cpumMsrRd_Ia32VmxCr0Fixed1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1220{
1221 *puValue = 0;
1222 return VINF_SUCCESS;
1223}
1224
1225
1226/** @callback_method_impl{FNCPUMRDMSR} */
1227static DECLCALLBACK(int) cpumMsrRd_Ia32VmxCr4Fixed0(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1228{
1229 *puValue = 0;
1230 return VINF_SUCCESS;
1231}
1232
1233
1234/** @callback_method_impl{FNCPUMRDMSR} */
1235static DECLCALLBACK(int) cpumMsrRd_Ia32VmxCr4Fixed1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1236{
1237 *puValue = 0;
1238 return VINF_SUCCESS;
1239}
1240
1241
1242/** @callback_method_impl{FNCPUMRDMSR} */
1243static DECLCALLBACK(int) cpumMsrRd_Ia32VmxVmcsEnum(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1244{
1245 *puValue = 0;
1246 return VINF_SUCCESS;
1247}
1248
1249
1250/** @callback_method_impl{FNCPUMRDMSR} */
1251static DECLCALLBACK(int) cpumMsrRd_Ia32VmxProcBasedCtls2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1252{
1253 *puValue = 0;
1254 return VINF_SUCCESS;
1255}
1256
1257
1258/** @callback_method_impl{FNCPUMRDMSR} */
1259static DECLCALLBACK(int) cpumMsrRd_Ia32VmxEptVpidCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1260{
1261 *puValue = 0;
1262 return VINF_SUCCESS;
1263}
1264
1265
1266/** @callback_method_impl{FNCPUMRDMSR} */
1267static DECLCALLBACK(int) cpumMsrRd_Ia32VmxTruePinbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1268{
1269 *puValue = 0;
1270 return VINF_SUCCESS;
1271}
1272
1273
1274/** @callback_method_impl{FNCPUMRDMSR} */
1275static DECLCALLBACK(int) cpumMsrRd_Ia32VmxTrueProcbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1276{
1277 *puValue = 0;
1278 return VINF_SUCCESS;
1279}
1280
1281
1282/** @callback_method_impl{FNCPUMRDMSR} */
1283static DECLCALLBACK(int) cpumMsrRd_Ia32VmxTrueExitCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1284{
1285 *puValue = 0;
1286 return VINF_SUCCESS;
1287}
1288
1289
1290/** @callback_method_impl{FNCPUMRDMSR} */
1291static DECLCALLBACK(int) cpumMsrRd_Ia32VmxTrueEntryCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1292{
1293 *puValue = 0;
1294 return VINF_SUCCESS;
1295}
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306/*
1307 * AMD64
1308 * AMD64
1309 * AMD64
1310 */
1311
1312
1313/** @callback_method_impl{FNCPUMRDMSR} */
1314static DECLCALLBACK(int) cpumMsrRd_Amd64Efer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1315{
1316 *puValue = pVCpu->cpum.s.Guest.msrEFER;
1317 return VINF_SUCCESS;
1318}
1319
1320
1321/** @callback_method_impl{FNCPUMWRMSR} */
1322static DECLCALLBACK(int) cpumMsrWr_Amd64Efer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1323{
1324 PVM pVM = pVCpu->CTX_SUFF(pVM);
1325 uint64_t const uOldEfer = pVCpu->cpum.s.Guest.msrEFER;
1326 uint32_t const fExtFeatures = pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1327 ? pVM->cpum.s.aGuestCpuIdExt[1].edx
1328 : 0;
1329 uint64_t fMask = 0;
1330 uint64_t fIgnoreMask = MSR_K6_EFER_LMA;
1331
1332 /* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
1333 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_NX)
1334 fMask |= MSR_K6_EFER_NXE;
1335 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
1336 fMask |= MSR_K6_EFER_LME;
1337 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
1338 fMask |= MSR_K6_EFER_SCE;
1339 if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1340 fMask |= MSR_K6_EFER_FFXSR;
1341
1342 /* #GP(0) If anything outside the allowed bits is set. */
1343 if (uValue & ~(fIgnoreMask | fMask))
1344 {
1345 Log(("CPUM: Settings disallowed EFER bit. uValue=%#RX64 fAllowed=%#RX64 -> #GP(0)\n", uValue, fMask));
1346 return VERR_CPUM_RAISE_GP_0;
1347 }
1348
1349 /* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if
1350 paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1351 if ( (uOldEfer & MSR_K6_EFER_LME) != (uValue & fMask & MSR_K6_EFER_LME)
1352 && (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG))
1353 {
1354 Log(("CPUM: Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
1355 return VERR_CPUM_RAISE_GP_0;
1356 }
1357
1358 /* There are a few more: e.g. MSR_K6_EFER_LMSLE */
1359 AssertMsg(!(uValue & ~(MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA /* ignored anyway */ | MSR_K6_EFER_SCE | MSR_K6_EFER_FFXSR)),
1360 ("Unexpected value %RX64\n", uValue));
1361 pVCpu->cpum.s.Guest.msrEFER = (uOldEfer & ~fMask) | (uValue & fMask);
1362
1363 /* AMD64 Architecture Programmer's Manual: 15.15 TLB Control; flush the TLB
1364 if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
1365 if ( (uOldEfer & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA))
1366 != (pVCpu->cpum.s.Guest.msrEFER & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA)))
1367 {
1368 /// @todo PGMFlushTLB(pVCpu, cr3, true /*fGlobal*/);
1369 HMFlushTLB(pVCpu);
1370
1371 /* Notify PGM about NXE changes. */
1372 if ( (uOldEfer & MSR_K6_EFER_NXE)
1373 != (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE))
1374 PGMNotifyNxeChanged(pVCpu, !(uOldEfer & MSR_K6_EFER_NXE));
1375 }
1376 return VINF_SUCCESS;
1377}
1378
1379
1380/** @callback_method_impl{FNCPUMRDMSR} */
1381static DECLCALLBACK(int) cpumMsrRd_Amd64SyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1382{
1383 *puValue = pVCpu->cpum.s.Guest.msrSTAR;
1384 return VINF_SUCCESS;
1385}
1386
1387
1388/** @callback_method_impl{FNCPUMWRMSR} */
1389static DECLCALLBACK(int) cpumMsrWr_Amd64SyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1390{
1391 pVCpu->cpum.s.Guest.msrSTAR = uValue;
1392 return VINF_SUCCESS;
1393}
1394
1395
1396/** @callback_method_impl{FNCPUMRDMSR} */
1397static DECLCALLBACK(int) cpumMsrRd_Amd64LongSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1398{
1399 *puValue = pVCpu->cpum.s.Guest.msrLSTAR;
1400 return VINF_SUCCESS;
1401}
1402
1403
1404/** @callback_method_impl{FNCPUMWRMSR} */
1405static DECLCALLBACK(int) cpumMsrWr_Amd64LongSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1406{
1407 if (!X86_IS_CANONICAL(uValue))
1408 {
1409 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
1410 return VERR_CPUM_RAISE_GP_0;
1411 }
1412 pVCpu->cpum.s.Guest.msrLSTAR = uValue;
1413 return VINF_SUCCESS;
1414}
1415
1416
1417/** @callback_method_impl{FNCPUMRDMSR} */
1418static DECLCALLBACK(int) cpumMsrRd_Amd64CompSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1419{
1420 *puValue = pVCpu->cpum.s.Guest.msrCSTAR;
1421 return VINF_SUCCESS;
1422}
1423
1424
1425/** @callback_method_impl{FNCPUMWRMSR} */
1426static DECLCALLBACK(int) cpumMsrWr_Amd64CompSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1427{
1428 if (!X86_IS_CANONICAL(uValue))
1429 {
1430 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
1431 return VERR_CPUM_RAISE_GP_0;
1432 }
1433 pVCpu->cpum.s.Guest.msrCSTAR = uValue;
1434 return VINF_SUCCESS;
1435}
1436
1437
1438/** @callback_method_impl{FNCPUMRDMSR} */
1439static DECLCALLBACK(int) cpumMsrRd_Amd64SyscallFlagMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1440{
1441 *puValue = pVCpu->cpum.s.Guest.msrSFMASK;
1442 return VINF_SUCCESS;
1443}
1444
1445
1446/** @callback_method_impl{FNCPUMWRMSR} */
1447static DECLCALLBACK(int) cpumMsrWr_Amd64SyscallFlagMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1448{
1449 pVCpu->cpum.s.Guest.msrSFMASK = uValue;
1450 return VINF_SUCCESS;
1451}
1452
1453
1454/** @callback_method_impl{FNCPUMRDMSR} */
1455static DECLCALLBACK(int) cpumMsrRd_Amd64FsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1456{
1457 *puValue = pVCpu->cpum.s.Guest.fs.u64Base;
1458 return VINF_SUCCESS;
1459}
1460
1461
1462/** @callback_method_impl{FNCPUMWRMSR} */
1463static DECLCALLBACK(int) cpumMsrWr_Amd64FsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1464{
1465 pVCpu->cpum.s.Guest.fs.u64Base = uValue;
1466 return VINF_SUCCESS;
1467}
1468
1469
1470/** @callback_method_impl{FNCPUMRDMSR} */
1471static DECLCALLBACK(int) cpumMsrRd_Amd64GsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1472{
1473 *puValue = pVCpu->cpum.s.Guest.gs.u64Base;
1474 return VINF_SUCCESS;
1475}
1476
1477/** @callback_method_impl{FNCPUMWRMSR} */
1478static DECLCALLBACK(int) cpumMsrWr_Amd64GsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1479{
1480 pVCpu->cpum.s.Guest.gs.u64Base = uValue;
1481 return VINF_SUCCESS;
1482}
1483
1484
1485
1486/** @callback_method_impl{FNCPUMRDMSR} */
1487static DECLCALLBACK(int) cpumMsrRd_Amd64KernelGsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1488{
1489 *puValue = pVCpu->cpum.s.Guest.msrKERNELGSBASE;
1490 return VINF_SUCCESS;
1491}
1492
1493/** @callback_method_impl{FNCPUMWRMSR} */
1494static DECLCALLBACK(int) cpumMsrWr_Amd64KernelGsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1495{
1496 pVCpu->cpum.s.Guest.msrKERNELGSBASE = uValue;
1497 return VINF_SUCCESS;
1498}
1499
1500
1501/** @callback_method_impl{FNCPUMRDMSR} */
1502static DECLCALLBACK(int) cpumMsrRd_Amd64TscAux(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1503{
1504 *puValue = pVCpu->cpum.s.GuestMsrs.msr.TscAux;
1505 return VINF_SUCCESS;
1506}
1507
1508/** @callback_method_impl{FNCPUMWRMSR} */
1509static DECLCALLBACK(int) cpumMsrWr_Amd64TscAux(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1510{
1511 pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
1512 return VINF_SUCCESS;
1513}
1514
1515
1516/*
1517 * Intel specific
1518 * Intel specific
1519 * Intel specific
1520 */
1521
1522/** @callback_method_impl{FNCPUMRDMSR} */
1523static DECLCALLBACK(int) cpumMsrRd_IntelEblCrPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1524{
1525 /** @todo recalc clock frequency ratio? */
1526 *puValue = pRange->uValue;
1527 return VINF_SUCCESS;
1528}
1529
1530
1531/** @callback_method_impl{FNCPUMWRMSR} */
1532static DECLCALLBACK(int) cpumMsrWr_IntelEblCrPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1533{
1534 /** @todo Write EBL_CR_POWERON: Remember written bits. */
1535 return VINF_SUCCESS;
1536}
1537
1538
1539/** @callback_method_impl{FNCPUMRDMSR} */
1540static DECLCALLBACK(int) cpumMsrRd_IntelI7CoreThreadCount(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1541{
1542 /* Note! According to cpuid_set_info in XNU (10.7.0), Westmere CPU only
1543 have a 4-bit core count. */
1544 uint16_t cCores = pVCpu->CTX_SUFF(pVM)->cCpus;
1545 uint16_t cThreads = cCores; /** @todo hyper-threading. */
1546 *puValue = RT_MAKE_U32(cThreads, cCores);
1547 return VINF_SUCCESS;
1548}
1549
1550
1551/** @callback_method_impl{FNCPUMRDMSR} */
1552static DECLCALLBACK(int) cpumMsrRd_IntelP4EbcHardPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1553{
1554 /** @todo P4 hard power on config */
1555 *puValue = pRange->uValue;
1556 return VINF_SUCCESS;
1557}
1558
1559
1560/** @callback_method_impl{FNCPUMWRMSR} */
1561static DECLCALLBACK(int) cpumMsrWr_IntelP4EbcHardPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1562{
1563 /** @todo P4 hard power on config */
1564 return VINF_SUCCESS;
1565}
1566
1567
1568/** @callback_method_impl{FNCPUMRDMSR} */
1569static DECLCALLBACK(int) cpumMsrRd_IntelP4EbcSoftPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1570{
1571 /** @todo P4 soft power on config */
1572 *puValue = pRange->uValue;
1573 return VINF_SUCCESS;
1574}
1575
1576
1577/** @callback_method_impl{FNCPUMWRMSR} */
1578static DECLCALLBACK(int) cpumMsrWr_IntelP4EbcSoftPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1579{
1580 /** @todo P4 soft power on config */
1581 return VINF_SUCCESS;
1582}
1583
1584
1585/** @callback_method_impl{FNCPUMRDMSR} */
1586static DECLCALLBACK(int) cpumMsrRd_IntelP4EbcFrequencyId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1587{
1588 uint64_t uValue;
1589 PVM pVM = pVCpu->CTX_SUFF(pVM);
1590 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
1591 if (pVM->cpum.s.GuestFeatures.uModel >= 2)
1592 {
1593 if (uScalableBusHz <= CPUM_SBUSFREQ_100MHZ && pVM->cpum.s.GuestFeatures.uModel <= 2)
1594 {
1595 uScalableBusHz = CPUM_SBUSFREQ_100MHZ;
1596 uValue = 0;
1597 }
1598 else if (uScalableBusHz <= CPUM_SBUSFREQ_133MHZ)
1599 {
1600 uScalableBusHz = CPUM_SBUSFREQ_133MHZ;
1601 uValue = 1;
1602 }
1603 else if (uScalableBusHz <= CPUM_SBUSFREQ_167MHZ)
1604 {
1605 uScalableBusHz = CPUM_SBUSFREQ_167MHZ;
1606 uValue = 3;
1607 }
1608 else if (uScalableBusHz <= CPUM_SBUSFREQ_200MHZ)
1609 {
1610 uScalableBusHz = CPUM_SBUSFREQ_200MHZ;
1611 uValue = 2;
1612 }
1613 else if (uScalableBusHz <= CPUM_SBUSFREQ_267MHZ && pVM->cpum.s.GuestFeatures.uModel > 2)
1614 {
1615 uScalableBusHz = CPUM_SBUSFREQ_267MHZ;
1616 uValue = 0;
1617 }
1618 else
1619 {
1620 uScalableBusHz = CPUM_SBUSFREQ_333MHZ;
1621 uValue = 6;
1622 }
1623 uValue <<= 16;
1624
1625 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
1626 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
1627 uValue |= (uint32_t)uTscRatio << 24;
1628
1629 uValue |= pRange->uValue & ~UINT64_C(0xff0f0000);
1630 }
1631 else
1632 {
1633 /* Probably more stuff here, but intel doesn't want to tell us. */
1634 uValue = pRange->uValue;
1635 uValue &= ~(RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23)); /* 100 MHz is only documented value */
1636 }
1637
1638 *puValue = uValue;
1639 return VINF_SUCCESS;
1640}
1641
1642
1643/** @callback_method_impl{FNCPUMWRMSR} */
1644static DECLCALLBACK(int) cpumMsrWr_IntelP4EbcFrequencyId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1645{
1646 /** @todo P4 bus frequency config */
1647 return VINF_SUCCESS;
1648}
1649
1650
1651/** @callback_method_impl{FNCPUMRDMSR} */
1652static DECLCALLBACK(int) cpumMsrRd_IntelP6FsbFrequency(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1653{
1654 /* Convert the scalable bus frequency to the encoding in the intel manual (for core+). */
1655 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVCpu->CTX_SUFF(pVM));
1656 if (uScalableBusHz <= CPUM_SBUSFREQ_100MHZ)
1657 *puValue = 5;
1658 else if (uScalableBusHz <= CPUM_SBUSFREQ_133MHZ)
1659 *puValue = 1;
1660 else if (uScalableBusHz <= CPUM_SBUSFREQ_167MHZ)
1661 *puValue = 3;
1662 else if (uScalableBusHz <= CPUM_SBUSFREQ_200MHZ)
1663 *puValue = 2;
1664 else if (uScalableBusHz <= CPUM_SBUSFREQ_267MHZ)
1665 *puValue = 0;
1666 else if (uScalableBusHz <= CPUM_SBUSFREQ_333MHZ)
1667 *puValue = 4;
1668 else /*if (uScalableBusHz <= CPUM_SBUSFREQ_400MHZ)*/
1669 *puValue = 6;
1670
1671 *puValue |= pRange->uValue & ~UINT64_C(0x7);
1672
1673 return VINF_SUCCESS;
1674}
1675
1676
1677/** @callback_method_impl{FNCPUMRDMSR} */
1678static DECLCALLBACK(int) cpumMsrRd_IntelPlatformInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1679{
1680 /* Just indicate a fixed TSC, no turbo boost, no programmable anything. */
1681 PVM pVM = pVCpu->CTX_SUFF(pVM);
1682 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
1683 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
1684 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
1685 uint64_t uValue = ((uint32_t)uTscRatio << 8) /* TSC invariant frequency. */
1686 | ((uint64_t)uTscRatio << 40); /* The max turbo frequency. */
1687
1688 /* Ivy bridge has a minimum operating ratio as well. */
1689 if (true) /** @todo detect sandy bridge. */
1690 uValue |= (uint64_t)uTscRatio << 48;
1691
1692 *puValue = uValue;
1693 return VINF_SUCCESS;
1694}
1695
1696
1697/** @callback_method_impl{FNCPUMRDMSR} */
1698static DECLCALLBACK(int) cpumMsrRd_IntelFlexRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1699{
1700 uint64_t uValue = pRange->uValue & ~UINT64_C(0x1ff00);
1701
1702 PVM pVM = pVCpu->CTX_SUFF(pVM);
1703 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
1704 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
1705 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
1706 uValue |= (uint32_t)uTscRatio << 8;
1707
1708 *puValue = uValue;
1709 return VINF_SUCCESS;
1710}
1711
1712
1713/** @callback_method_impl{FNCPUMWRMSR} */
1714static DECLCALLBACK(int) cpumMsrWr_IntelFlexRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1715{
1716 /** @todo implement writing MSR_FLEX_RATIO. */
1717 return VINF_SUCCESS;
1718}
1719
1720
1721/** @callback_method_impl{FNCPUMRDMSR} */
1722static DECLCALLBACK(int) cpumMsrRd_IntelPkgCStConfigControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1723{
1724 *puValue = pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl;
1725 return VINF_SUCCESS;
1726}
1727
1728
1729/** @callback_method_impl{FNCPUMWRMSR} */
1730static DECLCALLBACK(int) cpumMsrWr_IntelPkgCStConfigControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1731{
1732 if (pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl & RT_BIT_64(15))
1733 {
1734 Log(("CPUM: WRMDR %#x (%s), %#llx: Write protected -> #GP\n", idMsr, pRange->szName, uValue));
1735 return VERR_CPUM_RAISE_GP_0;
1736 }
1737#if 0 /** @todo check what real (old) hardware does. */
1738 if ((uValue & 7) >= 5)
1739 {
1740 Log(("CPUM: WRMDR %#x (%s), %#llx: Invalid limit (%d) -> #GP\n", idMsr, pRange->szName, uValue, (uint32_t)(uValue & 7)));
1741 return VERR_CPUM_RAISE_GP_0;
1742 }
1743#endif
1744 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = uValue;
1745 return VINF_SUCCESS;
1746}
1747
1748
1749/** @callback_method_impl{FNCPUMRDMSR} */
1750static DECLCALLBACK(int) cpumMsrRd_IntelPmgIoCaptureBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1751{
1752 /** @todo implement I/O mwait wakeup. */
1753 *puValue = 0;
1754 return VINF_SUCCESS;
1755}
1756
1757
1758/** @callback_method_impl{FNCPUMWRMSR} */
1759static DECLCALLBACK(int) cpumMsrWr_IntelPmgIoCaptureBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1760{
1761 /** @todo implement I/O mwait wakeup. */
1762 return VINF_SUCCESS;
1763}
1764
1765
1766/** @callback_method_impl{FNCPUMRDMSR} */
1767static DECLCALLBACK(int) cpumMsrRd_IntelLastBranchFromToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1768{
1769 /** @todo implement last branch records. */
1770 *puValue = 0;
1771 return VINF_SUCCESS;
1772}
1773
1774
1775/** @callback_method_impl{FNCPUMWRMSR} */
1776static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchFromToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1777{
1778 /** @todo implement last branch records. */
1779 return VINF_SUCCESS;
1780}
1781
1782
1783/** @callback_method_impl{FNCPUMRDMSR} */
1784static DECLCALLBACK(int) cpumMsrRd_IntelLastBranchFromN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1785{
1786 /** @todo implement last branch records. */
1787 *puValue = 0;
1788 return VINF_SUCCESS;
1789}
1790
1791
1792/** @callback_method_impl{FNCPUMWRMSR} */
1793static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchFromN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1794{
1795 /** @todo implement last branch records. */
1796 /** @todo Probing indicates that bit 63 is settable on SandyBridge, at least
1797 * if the rest of the bits are zero. Automatic sign extending?
1798 * Investigate! */
1799 if (!X86_IS_CANONICAL(uValue))
1800 {
1801 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
1802 return VERR_CPUM_RAISE_GP_0;
1803 }
1804 return VINF_SUCCESS;
1805}
1806
1807
1808/** @callback_method_impl{FNCPUMRDMSR} */
1809static DECLCALLBACK(int) cpumMsrRd_IntelLastBranchToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1810{
1811 /** @todo implement last branch records. */
1812 *puValue = 0;
1813 return VINF_SUCCESS;
1814}
1815
1816
1817/** @callback_method_impl{FNCPUMWRMSR} */
1818static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1819{
1820 /** @todo implement last branch records. */
1821 /** @todo Probing indicates that bit 63 is settable on SandyBridge, at least
1822 * if the rest of the bits are zero. Automatic sign extending?
1823 * Investigate! */
1824 if (!X86_IS_CANONICAL(uValue))
1825 {
1826 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
1827 return VERR_CPUM_RAISE_GP_0;
1828 }
1829 return VINF_SUCCESS;
1830}
1831
1832
1833/** @callback_method_impl{FNCPUMRDMSR} */
1834static DECLCALLBACK(int) cpumMsrRd_IntelLastBranchTos(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1835{
1836 /** @todo implement last branch records. */
1837 *puValue = 0;
1838 return VINF_SUCCESS;
1839}
1840
1841
1842/** @callback_method_impl{FNCPUMWRMSR} */
1843static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchTos(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1844{
1845 /** @todo implement last branch records. */
1846 return VINF_SUCCESS;
1847}
1848
1849
1850/** @callback_method_impl{FNCPUMRDMSR} */
1851static DECLCALLBACK(int) cpumMsrRd_IntelBblCrCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1852{
1853 *puValue = pRange->uValue;
1854 return VINF_SUCCESS;
1855}
1856
1857
1858/** @callback_method_impl{FNCPUMWRMSR} */
1859static DECLCALLBACK(int) cpumMsrWr_IntelBblCrCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1860{
1861 return VINF_SUCCESS;
1862}
1863
1864
1865/** @callback_method_impl{FNCPUMRDMSR} */
1866static DECLCALLBACK(int) cpumMsrRd_IntelBblCrCtl3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1867{
1868 *puValue = pRange->uValue;
1869 return VINF_SUCCESS;
1870}
1871
1872
1873/** @callback_method_impl{FNCPUMWRMSR} */
1874static DECLCALLBACK(int) cpumMsrWr_IntelBblCrCtl3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1875{
1876 return VINF_SUCCESS;
1877}
1878
1879
1880/** @callback_method_impl{FNCPUMRDMSR} */
1881static DECLCALLBACK(int) cpumMsrRd_IntelI7TemperatureTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1882{
1883 *puValue = pRange->uValue;
1884 return VINF_SUCCESS;
1885}
1886
1887
1888/** @callback_method_impl{FNCPUMWRMSR} */
1889static DECLCALLBACK(int) cpumMsrWr_IntelI7TemperatureTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1890{
1891 return VINF_SUCCESS;
1892}
1893
1894
1895/** @callback_method_impl{FNCPUMRDMSR} */
1896static DECLCALLBACK(int) cpumMsrRd_IntelI7MsrOffCoreResponseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1897{
1898 /** @todo machine check. */
1899 *puValue = pRange->uValue;
1900 return VINF_SUCCESS;
1901}
1902
1903
1904/** @callback_method_impl{FNCPUMWRMSR} */
1905static DECLCALLBACK(int) cpumMsrWr_IntelI7MsrOffCoreResponseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1906{
1907 /** @todo machine check. */
1908 return VINF_SUCCESS;
1909}
1910
1911
1912/** @callback_method_impl{FNCPUMRDMSR} */
1913static DECLCALLBACK(int) cpumMsrRd_IntelI7MiscPwrMgmt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1914{
1915 *puValue = 0;
1916 return VINF_SUCCESS;
1917}
1918
1919
1920/** @callback_method_impl{FNCPUMWRMSR} */
1921static DECLCALLBACK(int) cpumMsrWr_IntelI7MiscPwrMgmt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1922{
1923 return VINF_SUCCESS;
1924}
1925
1926
1927/** @callback_method_impl{FNCPUMRDMSR} */
1928static DECLCALLBACK(int) cpumMsrRd_IntelP6CrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1929{
1930 int rc = CPUMGetGuestCRx(pVCpu, pRange->uValue, puValue);
1931 AssertRC(rc);
1932 return VINF_SUCCESS;
1933}
1934
1935
1936/** @callback_method_impl{FNCPUMWRMSR} */
1937static DECLCALLBACK(int) cpumMsrWr_IntelP6CrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1938{
1939 /* This CRx interface differs from the MOV CRx, GReg interface in that
1940 #GP(0) isn't raised if unsupported bits are written to. Instead they
1941 are simply ignored and masked off. (Pentium M Dothan) */
1942 /** @todo Implement MSR_P6_CRx writing. Too much effort for very little, if
1943 * any, gain. */
1944 return VINF_SUCCESS;
1945}
1946
1947
1948/** @callback_method_impl{FNCPUMRDMSR} */
1949static DECLCALLBACK(int) cpumMsrRd_IntelCpuId1FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1950{
1951 /** @todo implement CPUID masking. */
1952 *puValue = UINT64_MAX;
1953 return VINF_SUCCESS;
1954}
1955
1956
1957/** @callback_method_impl{FNCPUMWRMSR} */
1958static DECLCALLBACK(int) cpumMsrWr_IntelCpuId1FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1959{
1960 /** @todo implement CPUID masking. */
1961 return VINF_SUCCESS;
1962}
1963
1964
1965/** @callback_method_impl{FNCPUMRDMSR} */
1966static DECLCALLBACK(int) cpumMsrRd_IntelCpuId1FeatureMaskEax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1967{
1968 /** @todo implement CPUID masking. */
1969 return VINF_SUCCESS;
1970}
1971
1972
1973/** @callback_method_impl{FNCPUMWRMSR} */
1974static DECLCALLBACK(int) cpumMsrWr_IntelCpuId1FeatureMaskEax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1975{
1976 /** @todo implement CPUID masking. */
1977 return VINF_SUCCESS;
1978}
1979
1980
1981
1982/** @callback_method_impl{FNCPUMRDMSR} */
1983static DECLCALLBACK(int) cpumMsrRd_IntelCpuId80000001FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1984{
1985 /** @todo implement CPUID masking. */
1986 *puValue = UINT64_MAX;
1987 return VINF_SUCCESS;
1988}
1989
1990
1991/** @callback_method_impl{FNCPUMWRMSR} */
1992static DECLCALLBACK(int) cpumMsrWr_IntelCpuId80000001FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1993{
1994 /** @todo implement CPUID masking. */
1995 return VINF_SUCCESS;
1996}
1997
1998
1999
2000/** @callback_method_impl{FNCPUMRDMSR} */
2001static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyAesNiCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2002{
2003 /** @todo implement AES-NI. */
2004 *puValue = 3; /* Bit 0 is lock bit, bit 1 disables AES-NI. That's what they say. */
2005 return VINF_SUCCESS;
2006}
2007
2008
2009/** @callback_method_impl{FNCPUMWRMSR} */
2010static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyAesNiCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2011{
2012 /** @todo implement AES-NI. */
2013 return VERR_CPUM_RAISE_GP_0;
2014}
2015
2016
2017/** @callback_method_impl{FNCPUMRDMSR} */
2018static DECLCALLBACK(int) cpumMsrRd_IntelI7TurboRatioLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2019{
2020 /** @todo implement intel C states. */
2021 *puValue = pRange->uValue;
2022 return VINF_SUCCESS;
2023}
2024
2025
2026/** @callback_method_impl{FNCPUMWRMSR} */
2027static DECLCALLBACK(int) cpumMsrWr_IntelI7TurboRatioLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2028{
2029 /** @todo implement intel C states. */
2030 return VINF_SUCCESS;
2031}
2032
2033
2034/** @callback_method_impl{FNCPUMRDMSR} */
2035static DECLCALLBACK(int) cpumMsrRd_IntelI7LbrSelect(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2036{
2037 /** @todo implement last-branch-records. */
2038 *puValue = 0;
2039 return VINF_SUCCESS;
2040}
2041
2042
2043/** @callback_method_impl{FNCPUMWRMSR} */
2044static DECLCALLBACK(int) cpumMsrWr_IntelI7LbrSelect(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2045{
2046 /** @todo implement last-branch-records. */
2047 return VINF_SUCCESS;
2048}
2049
2050
2051/** @callback_method_impl{FNCPUMRDMSR} */
2052static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyErrorControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2053{
2054 /** @todo implement memory error injection (MSR_ERROR_CONTROL). */
2055 *puValue = 0;
2056 return VINF_SUCCESS;
2057}
2058
2059
2060/** @callback_method_impl{FNCPUMWRMSR} */
2061static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyErrorControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2062{
2063 /** @todo implement memory error injection (MSR_ERROR_CONTROL). */
2064 return VINF_SUCCESS;
2065}
2066
2067
2068/** @callback_method_impl{FNCPUMRDMSR} */
2069static DECLCALLBACK(int) cpumMsrRd_IntelI7VirtualLegacyWireCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2070{
2071 /** @todo implement memory VLW? */
2072 *puValue = pRange->uValue;
2073 /* Note: A20M is known to be bit 1 as this was disclosed in spec update
2074 AAJ49/AAK51/????, which documents the inversion of this bit. The
2075 Sandy bridge CPU here has value 0x74, so it probably doesn't have a BIOS
2076 that correct things. Some guesses at the other bits:
2077 bit 2 = INTR
2078 bit 4 = SMI
2079 bit 5 = INIT
2080 bit 6 = NMI */
2081 return VINF_SUCCESS;
2082}
2083
2084
2085/** @callback_method_impl{FNCPUMRDMSR} */
2086static DECLCALLBACK(int) cpumMsrRd_IntelI7PowerCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2087{
2088 /** @todo intel power management */
2089 *puValue = 0;
2090 return VINF_SUCCESS;
2091}
2092
2093
2094/** @callback_method_impl{FNCPUMWRMSR} */
2095static DECLCALLBACK(int) cpumMsrWr_IntelI7PowerCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2096{
2097 /** @todo intel power management */
2098 return VINF_SUCCESS;
2099}
2100
2101
2102/** @callback_method_impl{FNCPUMRDMSR} */
2103static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyPebsNumAlt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2104{
2105 /** @todo intel performance counters. */
2106 *puValue = 0;
2107 return VINF_SUCCESS;
2108}
2109
2110
2111/** @callback_method_impl{FNCPUMWRMSR} */
2112static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyPebsNumAlt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2113{
2114 /** @todo intel performance counters. */
2115 return VINF_SUCCESS;
2116}
2117
2118
2119/** @callback_method_impl{FNCPUMRDMSR} */
2120static DECLCALLBACK(int) cpumMsrRd_IntelI7PebsLdLat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2121{
2122 /** @todo intel performance counters. */
2123 *puValue = 0;
2124 return VINF_SUCCESS;
2125}
2126
2127
2128/** @callback_method_impl{FNCPUMWRMSR} */
2129static DECLCALLBACK(int) cpumMsrWr_IntelI7PebsLdLat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2130{
2131 /** @todo intel performance counters. */
2132 return VINF_SUCCESS;
2133}
2134
2135
2136/** @callback_method_impl{FNCPUMRDMSR} */
2137static DECLCALLBACK(int) cpumMsrRd_IntelI7PkgCnResidencyN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2138{
2139 /** @todo intel power management. */
2140 *puValue = 0;
2141 return VINF_SUCCESS;
2142}
2143
2144
2145/** @callback_method_impl{FNCPUMRDMSR} */
2146static DECLCALLBACK(int) cpumMsrRd_IntelI7CoreCnResidencyN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2147{
2148 /** @todo intel power management. */
2149 *puValue = 0;
2150 return VINF_SUCCESS;
2151}
2152
2153
2154/** @callback_method_impl{FNCPUMRDMSR} */
2155static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyVrCurrentConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2156{
2157 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2158 *puValue = 0;
2159 return VINF_SUCCESS;
2160}
2161
2162
2163/** @callback_method_impl{FNCPUMWRMSR} */
2164static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyVrCurrentConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2165{
2166 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2167 return VINF_SUCCESS;
2168}
2169
2170
2171/** @callback_method_impl{FNCPUMRDMSR} */
2172static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyVrMiscConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2173{
2174 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2175 *puValue = 0;
2176 return VINF_SUCCESS;
2177}
2178
2179
2180/** @callback_method_impl{FNCPUMWRMSR} */
2181static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyVrMiscConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2182{
2183 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2184 return VINF_SUCCESS;
2185}
2186
2187
2188/** @callback_method_impl{FNCPUMRDMSR} */
2189static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyRaplPowerUnit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2190{
2191 /** @todo intel RAPL. */
2192 *puValue = pRange->uValue;
2193 return VINF_SUCCESS;
2194}
2195
2196
2197/** @callback_method_impl{FNCPUMRDMSR} */
2198static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyPkgCnIrtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2199{
2200 /** @todo intel power management. */
2201 *puValue = 0;
2202 return VINF_SUCCESS;
2203}
2204
2205
2206/** @callback_method_impl{FNCPUMWRMSR} */
2207static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyPkgCnIrtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2208{
2209 /** @todo intel power management. */
2210 return VINF_SUCCESS;
2211}
2212
2213
2214/** @callback_method_impl{FNCPUMRDMSR} */
2215static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyPkgC2Residency(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2216{
2217 /** @todo intel power management. */
2218 *puValue = 0;
2219 return VINF_SUCCESS;
2220}
2221
2222
2223/** @callback_method_impl{FNCPUMRDMSR} */
2224static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPkgPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2225{
2226 /** @todo intel RAPL. */
2227 *puValue = 0;
2228 return VINF_SUCCESS;
2229}
2230
2231
2232/** @callback_method_impl{FNCPUMWRMSR} */
2233static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPkgPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2234{
2235 /** @todo intel RAPL. */
2236 return VINF_SUCCESS;
2237}
2238
2239
2240/** @callback_method_impl{FNCPUMRDMSR} */
2241static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPkgEnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2242{
2243 /** @todo intel power management. */
2244 *puValue = 0;
2245 return VINF_SUCCESS;
2246}
2247
2248
2249/** @callback_method_impl{FNCPUMRDMSR} */
2250static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPkgPerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2251{
2252 /** @todo intel power management. */
2253 *puValue = 0;
2254 return VINF_SUCCESS;
2255}
2256
2257
2258/** @callback_method_impl{FNCPUMRDMSR} */
2259static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPkgPowerInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2260{
2261 /** @todo intel power management. */
2262 *puValue = 0;
2263 return VINF_SUCCESS;
2264}
2265
2266
2267/** @callback_method_impl{FNCPUMRDMSR} */
2268static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplDramPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2269{
2270 /** @todo intel RAPL. */
2271 *puValue = 0;
2272 return VINF_SUCCESS;
2273}
2274
2275
2276/** @callback_method_impl{FNCPUMWRMSR} */
2277static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplDramPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2278{
2279 /** @todo intel RAPL. */
2280 return VINF_SUCCESS;
2281}
2282
2283
2284/** @callback_method_impl{FNCPUMRDMSR} */
2285static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplDramEnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2286{
2287 /** @todo intel power management. */
2288 *puValue = 0;
2289 return VINF_SUCCESS;
2290}
2291
2292
2293/** @callback_method_impl{FNCPUMRDMSR} */
2294static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplDramPerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2295{
2296 /** @todo intel power management. */
2297 *puValue = 0;
2298 return VINF_SUCCESS;
2299}
2300
2301
2302/** @callback_method_impl{FNCPUMRDMSR} */
2303static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplDramPowerInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2304{
2305 /** @todo intel power management. */
2306 *puValue = 0;
2307 return VINF_SUCCESS;
2308}
2309
2310
2311/** @callback_method_impl{FNCPUMRDMSR} */
2312static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp0PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2313{
2314 /** @todo intel RAPL. */
2315 *puValue = 0;
2316 return VINF_SUCCESS;
2317}
2318
2319
2320/** @callback_method_impl{FNCPUMWRMSR} */
2321static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp0PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2322{
2323 /** @todo intel RAPL. */
2324 return VINF_SUCCESS;
2325}
2326
2327
2328/** @callback_method_impl{FNCPUMRDMSR} */
2329static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp0EnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2330{
2331 /** @todo intel power management. */
2332 *puValue = 0;
2333 return VINF_SUCCESS;
2334}
2335
2336
2337/** @callback_method_impl{FNCPUMRDMSR} */
2338static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp0Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2339{
2340 /** @todo intel RAPL. */
2341 *puValue = 0;
2342 return VINF_SUCCESS;
2343}
2344
2345
2346/** @callback_method_impl{FNCPUMWRMSR} */
2347static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp0Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2348{
2349 /** @todo intel RAPL. */
2350 return VINF_SUCCESS;
2351}
2352
2353
2354/** @callback_method_impl{FNCPUMRDMSR} */
2355static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp0PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2356{
2357 /** @todo intel power management. */
2358 *puValue = 0;
2359 return VINF_SUCCESS;
2360}
2361
2362
2363/** @callback_method_impl{FNCPUMRDMSR} */
2364static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp1PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2365{
2366 /** @todo intel RAPL. */
2367 *puValue = 0;
2368 return VINF_SUCCESS;
2369}
2370
2371
2372/** @callback_method_impl{FNCPUMWRMSR} */
2373static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp1PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2374{
2375 /** @todo intel RAPL. */
2376 return VINF_SUCCESS;
2377}
2378
2379
2380/** @callback_method_impl{FNCPUMRDMSR} */
2381static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp1EnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2382{
2383 /** @todo intel power management. */
2384 *puValue = 0;
2385 return VINF_SUCCESS;
2386}
2387
2388
2389/** @callback_method_impl{FNCPUMRDMSR} */
2390static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp1Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2391{
2392 /** @todo intel RAPL. */
2393 *puValue = 0;
2394 return VINF_SUCCESS;
2395}
2396
2397
2398/** @callback_method_impl{FNCPUMWRMSR} */
2399static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp1Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2400{
2401 /** @todo intel RAPL. */
2402 return VINF_SUCCESS;
2403}
2404
2405
2406/** @callback_method_impl{FNCPUMRDMSR} */
2407static DECLCALLBACK(int) cpumMsrRd_IntelI7IvyConfigTdpNominal(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2408{
2409 /** @todo intel power management. */
2410 *puValue = pRange->uValue;
2411 return VINF_SUCCESS;
2412}
2413
2414
2415/** @callback_method_impl{FNCPUMRDMSR} */
2416static DECLCALLBACK(int) cpumMsrRd_IntelI7IvyConfigTdpLevel1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2417{
2418 /** @todo intel power management. */
2419 *puValue = pRange->uValue;
2420 return VINF_SUCCESS;
2421}
2422
2423
2424/** @callback_method_impl{FNCPUMRDMSR} */
2425static DECLCALLBACK(int) cpumMsrRd_IntelI7IvyConfigTdpLevel2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2426{
2427 /** @todo intel power management. */
2428 *puValue = pRange->uValue;
2429 return VINF_SUCCESS;
2430}
2431
2432
2433/** @callback_method_impl{FNCPUMRDMSR} */
2434static DECLCALLBACK(int) cpumMsrRd_IntelI7IvyConfigTdpControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2435{
2436 /** @todo intel power management. */
2437 *puValue = 0;
2438 return VINF_SUCCESS;
2439}
2440
2441
2442/** @callback_method_impl{FNCPUMWRMSR} */
2443static DECLCALLBACK(int) cpumMsrWr_IntelI7IvyConfigTdpControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2444{
2445 /** @todo intel power management. */
2446 return VINF_SUCCESS;
2447}
2448
2449
2450/** @callback_method_impl{FNCPUMRDMSR} */
2451static DECLCALLBACK(int) cpumMsrRd_IntelI7IvyTurboActivationRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2452{
2453 /** @todo intel power management. */
2454 *puValue = 0;
2455 return VINF_SUCCESS;
2456}
2457
2458
2459/** @callback_method_impl{FNCPUMWRMSR} */
2460static DECLCALLBACK(int) cpumMsrWr_IntelI7IvyTurboActivationRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2461{
2462 /** @todo intel power management. */
2463 return VINF_SUCCESS;
2464}
2465
2466
2467/** @callback_method_impl{FNCPUMRDMSR} */
2468static DECLCALLBACK(int) cpumMsrRd_IntelI7UncPerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2469{
2470 /** @todo uncore msrs. */
2471 *puValue = 0;
2472 return VINF_SUCCESS;
2473}
2474
2475
2476/** @callback_method_impl{FNCPUMWRMSR} */
2477static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2478{
2479 /** @todo uncore msrs. */
2480 return VINF_SUCCESS;
2481}
2482
2483
2484/** @callback_method_impl{FNCPUMRDMSR} */
2485static DECLCALLBACK(int) cpumMsrRd_IntelI7UncPerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2486{
2487 /** @todo uncore msrs. */
2488 *puValue = 0;
2489 return VINF_SUCCESS;
2490}
2491
2492
2493/** @callback_method_impl{FNCPUMWRMSR} */
2494static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2495{
2496 /** @todo uncore msrs. */
2497 return VINF_SUCCESS;
2498}
2499
2500
2501/** @callback_method_impl{FNCPUMRDMSR} */
2502static DECLCALLBACK(int) cpumMsrRd_IntelI7UncPerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2503{
2504 /** @todo uncore msrs. */
2505 *puValue = 0;
2506 return VINF_SUCCESS;
2507}
2508
2509
2510/** @callback_method_impl{FNCPUMWRMSR} */
2511static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2512{
2513 /** @todo uncore msrs. */
2514 return VINF_SUCCESS;
2515}
2516
2517
2518/** @callback_method_impl{FNCPUMRDMSR} */
2519static DECLCALLBACK(int) cpumMsrRd_IntelI7UncPerfFixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2520{
2521 /** @todo uncore msrs. */
2522 *puValue = 0;
2523 return VINF_SUCCESS;
2524}
2525
2526
2527/** @callback_method_impl{FNCPUMWRMSR} */
2528static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfFixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2529{
2530 /** @todo uncore msrs. */
2531 return VINF_SUCCESS;
2532}
2533
2534
2535/** @callback_method_impl{FNCPUMRDMSR} */
2536static DECLCALLBACK(int) cpumMsrRd_IntelI7UncPerfFixedCtr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2537{
2538 /** @todo uncore msrs. */
2539 *puValue = 0;
2540 return VINF_SUCCESS;
2541}
2542
2543
2544/** @callback_method_impl{FNCPUMWRMSR} */
2545static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfFixedCtr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2546{
2547 /** @todo uncore msrs. */
2548 return VINF_SUCCESS;
2549}
2550
2551
2552/** @callback_method_impl{FNCPUMRDMSR} */
2553static DECLCALLBACK(int) cpumMsrRd_IntelI7UncCBoxConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2554{
2555 /** @todo uncore msrs. */
2556 *puValue = 0;
2557 return VINF_SUCCESS;
2558}
2559
2560
2561/** @callback_method_impl{FNCPUMRDMSR} */
2562static DECLCALLBACK(int) cpumMsrRd_IntelI7UncArbPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2563{
2564 /** @todo uncore msrs. */
2565 *puValue = 0;
2566 return VINF_SUCCESS;
2567}
2568
2569
2570/** @callback_method_impl{FNCPUMWRMSR} */
2571static DECLCALLBACK(int) cpumMsrWr_IntelI7UncArbPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2572{
2573 /** @todo uncore msrs. */
2574 return VINF_SUCCESS;
2575}
2576
2577
2578/** @callback_method_impl{FNCPUMRDMSR} */
2579static DECLCALLBACK(int) cpumMsrRd_IntelI7UncArbPerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2580{
2581 /** @todo uncore msrs. */
2582 *puValue = 0;
2583 return VINF_SUCCESS;
2584}
2585
2586
2587/** @callback_method_impl{FNCPUMWRMSR} */
2588static DECLCALLBACK(int) cpumMsrWr_IntelI7UncArbPerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2589{
2590 /** @todo uncore msrs. */
2591 return VINF_SUCCESS;
2592}
2593
2594
2595/** @callback_method_impl{FNCPUMRDMSR} */
2596static DECLCALLBACK(int) cpumMsrRd_IntelCore2EmttmCrTablesN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2597{
2598 /** @todo implement enhanced multi thread termal monitoring? */
2599 *puValue = pRange->uValue;
2600 return VINF_SUCCESS;
2601}
2602
2603
2604/** @callback_method_impl{FNCPUMWRMSR} */
2605static DECLCALLBACK(int) cpumMsrWr_IntelCore2EmttmCrTablesN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2606{
2607 /** @todo implement enhanced multi thread termal monitoring? */
2608 return VINF_SUCCESS;
2609}
2610
2611
2612/** @callback_method_impl{FNCPUMRDMSR} */
2613static DECLCALLBACK(int) cpumMsrRd_IntelCore2SmmCStMiscInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2614{
2615 /** @todo SMM & C-states? */
2616 *puValue = 0;
2617 return VINF_SUCCESS;
2618}
2619
2620
2621/** @callback_method_impl{FNCPUMWRMSR} */
2622static DECLCALLBACK(int) cpumMsrWr_IntelCore2SmmCStMiscInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2623{
2624 /** @todo SMM & C-states? */
2625 return VINF_SUCCESS;
2626}
2627
2628
2629/** @callback_method_impl{FNCPUMRDMSR} */
2630static DECLCALLBACK(int) cpumMsrRd_IntelCore1ExtConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2631{
2632 /** @todo Core1&2 EXT_CONFIG (whatever that is)? */
2633 *puValue = 0;
2634 return VINF_SUCCESS;
2635}
2636
2637
2638/** @callback_method_impl{FNCPUMWRMSR} */
2639static DECLCALLBACK(int) cpumMsrWr_IntelCore1ExtConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2640{
2641 /** @todo Core1&2 EXT_CONFIG (whatever that is)? */
2642 return VINF_SUCCESS;
2643}
2644
2645
2646/** @callback_method_impl{FNCPUMRDMSR} */
2647static DECLCALLBACK(int) cpumMsrRd_IntelCore1DtsCalControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2648{
2649 /** @todo Core1&2(?) DTS_CAL_CTRL (whatever that is)? */
2650 *puValue = 0;
2651 return VINF_SUCCESS;
2652}
2653
2654
2655/** @callback_method_impl{FNCPUMWRMSR} */
2656static DECLCALLBACK(int) cpumMsrWr_IntelCore1DtsCalControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2657{
2658 /** @todo Core1&2(?) DTS_CAL_CTRL (whatever that is)? */
2659 return VINF_SUCCESS;
2660}
2661
2662
2663/** @callback_method_impl{FNCPUMRDMSR} */
2664static DECLCALLBACK(int) cpumMsrRd_IntelCore2PeciControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2665{
2666 /** @todo Core2+ platform environment control interface control register? */
2667 *puValue = 0;
2668 return VINF_SUCCESS;
2669}
2670
2671
2672/** @callback_method_impl{FNCPUMWRMSR} */
2673static DECLCALLBACK(int) cpumMsrWr_IntelCore2PeciControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2674{
2675 /** @todo Core2+ platform environment control interface control register? */
2676 return VINF_SUCCESS;
2677}
2678
2679
2680
2681/*
2682 * Multiple vendor P6 MSRs.
2683 * Multiple vendor P6 MSRs.
2684 * Multiple vendor P6 MSRs.
2685 *
2686 * These MSRs were introduced with the P6 but not elevated to architectural
2687 * MSRs, despite other vendors implementing them.
2688 */
2689
2690
2691/** @callback_method_impl{FNCPUMRDMSR} */
2692static DECLCALLBACK(int) cpumMsrRd_P6LastBranchFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2693{
2694 /* AMD seems to just record RIP, while intel claims to record RIP+CS.BASE
2695 if I read the docs correctly, thus the need for separate functions. */
2696 /** @todo implement last branch records. */
2697 *puValue = 0;
2698 return VINF_SUCCESS;
2699}
2700
2701
2702/** @callback_method_impl{FNCPUMRDMSR} */
2703static DECLCALLBACK(int) cpumMsrRd_P6LastBranchToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2704{
2705 /** @todo implement last branch records. */
2706 *puValue = 0;
2707 return VINF_SUCCESS;
2708}
2709
2710
2711/** @callback_method_impl{FNCPUMRDMSR} */
2712static DECLCALLBACK(int) cpumMsrRd_P6LastIntFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2713{
2714 /** @todo implement last exception records. */
2715 *puValue = 0;
2716 return VINF_SUCCESS;
2717}
2718
2719
2720/** @callback_method_impl{FNCPUMWRMSR} */
2721static DECLCALLBACK(int) cpumMsrWr_P6LastIntFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2722{
2723 /** @todo implement last exception records. */
2724 /* Note! On many CPUs, the high bit of the 0x000001dd register is always writable, even when the result is
2725 a non-cannonical address. */
2726 return VINF_SUCCESS;
2727}
2728
2729
2730/** @callback_method_impl{FNCPUMRDMSR} */
2731static DECLCALLBACK(int) cpumMsrRd_P6LastIntToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2732{
2733 /** @todo implement last exception records. */
2734 *puValue = 0;
2735 return VINF_SUCCESS;
2736}
2737
2738
2739/** @callback_method_impl{FNCPUMWRMSR} */
2740static DECLCALLBACK(int) cpumMsrWr_P6LastIntToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2741{
2742 /** @todo implement last exception records. */
2743 return VINF_SUCCESS;
2744}
2745
2746
2747
2748/*
2749 * AMD specific
2750 * AMD specific
2751 * AMD specific
2752 */
2753
2754
2755/** @callback_method_impl{FNCPUMRDMSR} */
2756static DECLCALLBACK(int) cpumMsrRd_AmdFam15hTscRate(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2757{
2758 /** @todo Implement TscRateMsr */
2759 *puValue = RT_MAKE_U64(0, 1); /* 1.0 = reset value. */
2760 return VINF_SUCCESS;
2761}
2762
2763
2764/** @callback_method_impl{FNCPUMWRMSR} */
2765static DECLCALLBACK(int) cpumMsrWr_AmdFam15hTscRate(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2766{
2767 /** @todo Implement TscRateMsr */
2768 return VINF_SUCCESS;
2769}
2770
2771
2772/** @callback_method_impl{FNCPUMRDMSR} */
2773static DECLCALLBACK(int) cpumMsrRd_AmdFam15hLwpCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2774{
2775 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2776 /* Note: Only listes in BKDG for Family 15H. */
2777 *puValue = 0;
2778 return VINF_SUCCESS;
2779}
2780
2781
2782/** @callback_method_impl{FNCPUMWRMSR} */
2783static DECLCALLBACK(int) cpumMsrWr_AmdFam15hLwpCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2784{
2785 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2786 return VINF_SUCCESS;
2787}
2788
2789
2790/** @callback_method_impl{FNCPUMRDMSR} */
2791static DECLCALLBACK(int) cpumMsrRd_AmdFam15hLwpCbAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2792{
2793 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2794 /* Note: Only listes in BKDG for Family 15H. */
2795 *puValue = 0;
2796 return VINF_SUCCESS;
2797}
2798
2799
2800/** @callback_method_impl{FNCPUMWRMSR} */
2801static DECLCALLBACK(int) cpumMsrWr_AmdFam15hLwpCbAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2802{
2803 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2804 return VINF_SUCCESS;
2805}
2806
2807
2808/** @callback_method_impl{FNCPUMRDMSR} */
2809static DECLCALLBACK(int) cpumMsrRd_AmdFam10hMc4MiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2810{
2811 /** @todo machine check. */
2812 *puValue = 0;
2813 return VINF_SUCCESS;
2814}
2815
2816
2817/** @callback_method_impl{FNCPUMWRMSR} */
2818static DECLCALLBACK(int) cpumMsrWr_AmdFam10hMc4MiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2819{
2820 /** @todo machine check. */
2821 return VINF_SUCCESS;
2822}
2823
2824
2825/** @callback_method_impl{FNCPUMRDMSR} */
2826static DECLCALLBACK(int) cpumMsrRd_AmdK8PerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2827{
2828 /** @todo AMD performance events. */
2829 *puValue = 0;
2830 return VINF_SUCCESS;
2831}
2832
2833
2834/** @callback_method_impl{FNCPUMWRMSR} */
2835static DECLCALLBACK(int) cpumMsrWr_AmdK8PerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2836{
2837 /** @todo AMD performance events. */
2838 return VINF_SUCCESS;
2839}
2840
2841
2842/** @callback_method_impl{FNCPUMRDMSR} */
2843static DECLCALLBACK(int) cpumMsrRd_AmdK8PerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2844{
2845 /** @todo AMD performance events. */
2846 *puValue = 0;
2847 return VINF_SUCCESS;
2848}
2849
2850
2851/** @callback_method_impl{FNCPUMWRMSR} */
2852static DECLCALLBACK(int) cpumMsrWr_AmdK8PerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2853{
2854 /** @todo AMD performance events. */
2855 return VINF_SUCCESS;
2856}
2857
2858
2859/** @callback_method_impl{FNCPUMRDMSR} */
2860static DECLCALLBACK(int) cpumMsrRd_AmdK8SysCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2861{
2862 /** @todo AMD SYS_CFG */
2863 *puValue = pRange->uValue;
2864 return VINF_SUCCESS;
2865}
2866
2867
2868/** @callback_method_impl{FNCPUMWRMSR} */
2869static DECLCALLBACK(int) cpumMsrWr_AmdK8SysCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2870{
2871 /** @todo AMD SYS_CFG */
2872 return VINF_SUCCESS;
2873}
2874
2875
2876/** @callback_method_impl{FNCPUMRDMSR} */
2877static DECLCALLBACK(int) cpumMsrRd_AmdK8HwCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2878{
2879 /** @todo AMD HW_CFG */
2880 *puValue = 0;
2881 return VINF_SUCCESS;
2882}
2883
2884
2885/** @callback_method_impl{FNCPUMWRMSR} */
2886static DECLCALLBACK(int) cpumMsrWr_AmdK8HwCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2887{
2888 /** @todo AMD HW_CFG */
2889 return VINF_SUCCESS;
2890}
2891
2892
2893/** @callback_method_impl{FNCPUMRDMSR} */
2894static DECLCALLBACK(int) cpumMsrRd_AmdK8IorrBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2895{
2896 /** @todo AMD IorrMask/IorrBase */
2897 *puValue = 0;
2898 return VINF_SUCCESS;
2899}
2900
2901
2902/** @callback_method_impl{FNCPUMWRMSR} */
2903static DECLCALLBACK(int) cpumMsrWr_AmdK8IorrBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2904{
2905 /** @todo AMD IorrMask/IorrBase */
2906 return VINF_SUCCESS;
2907}
2908
2909
2910/** @callback_method_impl{FNCPUMRDMSR} */
2911static DECLCALLBACK(int) cpumMsrRd_AmdK8IorrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2912{
2913 /** @todo AMD IorrMask/IorrBase */
2914 *puValue = 0;
2915 return VINF_SUCCESS;
2916}
2917
2918
2919/** @callback_method_impl{FNCPUMWRMSR} */
2920static DECLCALLBACK(int) cpumMsrWr_AmdK8IorrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2921{
2922 /** @todo AMD IorrMask/IorrBase */
2923 return VINF_SUCCESS;
2924}
2925
2926
2927/** @callback_method_impl{FNCPUMRDMSR} */
2928static DECLCALLBACK(int) cpumMsrRd_AmdK8TopOfMemN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2929{
2930 *puValue = 0;
2931 /** @todo return 4GB - RamHoleSize here for TOPMEM. Figure out what to return
2932 * for TOPMEM2. */
2933 //if (pRange->uValue == 0)
2934 // *puValue = _4G - RamHoleSize;
2935 return VINF_SUCCESS;
2936}
2937
2938
2939/** @callback_method_impl{FNCPUMWRMSR} */
2940static DECLCALLBACK(int) cpumMsrWr_AmdK8TopOfMemN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2941{
2942 /** @todo AMD TOPMEM and TOPMEM2/TOM2. */
2943 return VINF_SUCCESS;
2944}
2945
2946
2947/** @callback_method_impl{FNCPUMRDMSR} */
2948static DECLCALLBACK(int) cpumMsrRd_AmdK8NbCfg1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2949{
2950 /** @todo AMD NB_CFG1 */
2951 *puValue = 0;
2952 return VINF_SUCCESS;
2953}
2954
2955
2956/** @callback_method_impl{FNCPUMWRMSR} */
2957static DECLCALLBACK(int) cpumMsrWr_AmdK8NbCfg1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2958{
2959 /** @todo AMD NB_CFG1 */
2960 return VINF_SUCCESS;
2961}
2962
2963
2964/** @callback_method_impl{FNCPUMRDMSR} */
2965static DECLCALLBACK(int) cpumMsrRd_AmdK8McXcptRedir(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2966{
2967 /** @todo machine check. */
2968 *puValue = 0;
2969 return VINF_SUCCESS;
2970}
2971
2972
2973/** @callback_method_impl{FNCPUMWRMSR} */
2974static DECLCALLBACK(int) cpumMsrWr_AmdK8McXcptRedir(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2975{
2976 /** @todo machine check. */
2977 return VINF_SUCCESS;
2978}
2979
2980
2981/** @callback_method_impl{FNCPUMRDMSR} */
2982static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuNameN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2983{
2984 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), pRange->uValue / 2 + 0x80000001, 0);
2985 if (pLeaf)
2986 {
2987 if (!(pRange->uValue & 1))
2988 *puValue = RT_MAKE_U64(pLeaf->uEax, pLeaf->uEbx);
2989 else
2990 *puValue = RT_MAKE_U64(pLeaf->uEcx, pLeaf->uEdx);
2991 }
2992 else
2993 *puValue = 0;
2994 return VINF_SUCCESS;
2995}
2996
2997
2998/** @callback_method_impl{FNCPUMWRMSR} */
2999static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuNameN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3000{
3001 /** @todo Remember guest programmed CPU name. */
3002 return VINF_SUCCESS;
3003}
3004
3005
3006/** @callback_method_impl{FNCPUMRDMSR} */
3007static DECLCALLBACK(int) cpumMsrRd_AmdK8HwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3008{
3009 /** @todo AMD HTC. */
3010 *puValue = pRange->uValue;
3011 return VINF_SUCCESS;
3012}
3013
3014
3015/** @callback_method_impl{FNCPUMWRMSR} */
3016static DECLCALLBACK(int) cpumMsrWr_AmdK8HwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3017{
3018 /** @todo AMD HTC. */
3019 return VINF_SUCCESS;
3020}
3021
3022
3023/** @callback_method_impl{FNCPUMRDMSR} */
3024static DECLCALLBACK(int) cpumMsrRd_AmdK8SwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3025{
3026 /** @todo AMD STC. */
3027 *puValue = 0;
3028 return VINF_SUCCESS;
3029}
3030
3031
3032/** @callback_method_impl{FNCPUMWRMSR} */
3033static DECLCALLBACK(int) cpumMsrWr_AmdK8SwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3034{
3035 /** @todo AMD STC. */
3036 return VINF_SUCCESS;
3037}
3038
3039
3040/** @callback_method_impl{FNCPUMRDMSR} */
3041static DECLCALLBACK(int) cpumMsrRd_AmdK8FidVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3042{
3043 /** @todo AMD FIDVID_CTL. */
3044 *puValue = pRange->uValue;
3045 return VINF_SUCCESS;
3046}
3047
3048
3049/** @callback_method_impl{FNCPUMWRMSR} */
3050static DECLCALLBACK(int) cpumMsrWr_AmdK8FidVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3051{
3052 /** @todo AMD FIDVID_CTL. */
3053 return VINF_SUCCESS;
3054}
3055
3056
3057/** @callback_method_impl{FNCPUMRDMSR} */
3058static DECLCALLBACK(int) cpumMsrRd_AmdK8FidVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3059{
3060 /** @todo AMD FIDVID_STATUS. */
3061 *puValue = pRange->uValue;
3062 return VINF_SUCCESS;
3063}
3064
3065
3066/** @callback_method_impl{FNCPUMRDMSR} */
3067static DECLCALLBACK(int) cpumMsrRd_AmdK8McCtlMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3068{
3069 /** @todo AMD MC. */
3070 *puValue = 0;
3071 return VINF_SUCCESS;
3072}
3073
3074
3075/** @callback_method_impl{FNCPUMWRMSR} */
3076static DECLCALLBACK(int) cpumMsrWr_AmdK8McCtlMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3077{
3078 /** @todo AMD MC. */
3079 return VINF_SUCCESS;
3080}
3081
3082
3083/** @callback_method_impl{FNCPUMRDMSR} */
3084static DECLCALLBACK(int) cpumMsrRd_AmdK8SmiOnIoTrapN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3085{
3086 /** @todo AMD SMM/SMI and I/O trap. */
3087 *puValue = 0;
3088 return VINF_SUCCESS;
3089}
3090
3091
3092/** @callback_method_impl{FNCPUMWRMSR} */
3093static DECLCALLBACK(int) cpumMsrWr_AmdK8SmiOnIoTrapN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3094{
3095 /** @todo AMD SMM/SMI and I/O trap. */
3096 return VINF_SUCCESS;
3097}
3098
3099
3100/** @callback_method_impl{FNCPUMRDMSR} */
3101static DECLCALLBACK(int) cpumMsrRd_AmdK8SmiOnIoTrapCtlSts(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3102{
3103 /** @todo AMD SMM/SMI and I/O trap. */
3104 *puValue = 0;
3105 return VINF_SUCCESS;
3106}
3107
3108
3109/** @callback_method_impl{FNCPUMWRMSR} */
3110static DECLCALLBACK(int) cpumMsrWr_AmdK8SmiOnIoTrapCtlSts(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3111{
3112 /** @todo AMD SMM/SMI and I/O trap. */
3113 return VINF_SUCCESS;
3114}
3115
3116
3117/** @callback_method_impl{FNCPUMRDMSR} */
3118static DECLCALLBACK(int) cpumMsrRd_AmdK8IntPendingMessage(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3119{
3120 /** @todo Interrupt pending message. */
3121 *puValue = 0;
3122 return VINF_SUCCESS;
3123}
3124
3125
3126/** @callback_method_impl{FNCPUMWRMSR} */
3127static DECLCALLBACK(int) cpumMsrWr_AmdK8IntPendingMessage(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3128{
3129 /** @todo Interrupt pending message. */
3130 return VINF_SUCCESS;
3131}
3132
3133
3134/** @callback_method_impl{FNCPUMRDMSR} */
3135static DECLCALLBACK(int) cpumMsrRd_AmdK8SmiTriggerIoCycle(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3136{
3137 /** @todo AMD SMM/SMI and trigger I/O cycle. */
3138 *puValue = 0;
3139 return VINF_SUCCESS;
3140}
3141
3142
3143/** @callback_method_impl{FNCPUMWRMSR} */
3144static DECLCALLBACK(int) cpumMsrWr_AmdK8SmiTriggerIoCycle(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3145{
3146 /** @todo AMD SMM/SMI and trigger I/O cycle. */
3147 return VINF_SUCCESS;
3148}
3149
3150
3151/** @callback_method_impl{FNCPUMRDMSR} */
3152static DECLCALLBACK(int) cpumMsrRd_AmdFam10hMmioCfgBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3153{
3154 /** @todo AMD MMIO Configuration base address. */
3155 *puValue = 0;
3156 return VINF_SUCCESS;
3157}
3158
3159
3160/** @callback_method_impl{FNCPUMWRMSR} */
3161static DECLCALLBACK(int) cpumMsrWr_AmdFam10hMmioCfgBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3162{
3163 /** @todo AMD MMIO Configuration base address. */
3164 return VINF_SUCCESS;
3165}
3166
3167
3168/** @callback_method_impl{FNCPUMRDMSR} */
3169static DECLCALLBACK(int) cpumMsrRd_AmdFam10hTrapCtlMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3170{
3171 /** @todo AMD 0xc0010059. */
3172 *puValue = 0;
3173 return VINF_SUCCESS;
3174}
3175
3176
3177/** @callback_method_impl{FNCPUMWRMSR} */
3178static DECLCALLBACK(int) cpumMsrWr_AmdFam10hTrapCtlMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3179{
3180 /** @todo AMD 0xc0010059. */
3181 return VINF_SUCCESS;
3182}
3183
3184
3185/** @callback_method_impl{FNCPUMRDMSR} */
3186static DECLCALLBACK(int) cpumMsrRd_AmdFam10hPStateCurLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3187{
3188 /** @todo AMD P-states. */
3189 *puValue = pRange->uValue;
3190 return VINF_SUCCESS;
3191}
3192
3193
3194/** @callback_method_impl{FNCPUMRDMSR} */
3195static DECLCALLBACK(int) cpumMsrRd_AmdFam10hPStateControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3196{
3197 /** @todo AMD P-states. */
3198 *puValue = pRange->uValue;
3199 return VINF_SUCCESS;
3200}
3201
3202
3203/** @callback_method_impl{FNCPUMWRMSR} */
3204static DECLCALLBACK(int) cpumMsrWr_AmdFam10hPStateControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3205{
3206 /** @todo AMD P-states. */
3207 return VINF_SUCCESS;
3208}
3209
3210
3211/** @callback_method_impl{FNCPUMRDMSR} */
3212static DECLCALLBACK(int) cpumMsrRd_AmdFam10hPStateStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3213{
3214 /** @todo AMD P-states. */
3215 *puValue = pRange->uValue;
3216 return VINF_SUCCESS;
3217}
3218
3219
3220/** @callback_method_impl{FNCPUMWRMSR} */
3221static DECLCALLBACK(int) cpumMsrWr_AmdFam10hPStateStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3222{
3223 /** @todo AMD P-states. */
3224 return VINF_SUCCESS;
3225}
3226
3227
3228/** @callback_method_impl{FNCPUMRDMSR} */
3229static DECLCALLBACK(int) cpumMsrRd_AmdFam10hPStateN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3230{
3231 /** @todo AMD P-states. */
3232 *puValue = pRange->uValue;
3233 return VINF_SUCCESS;
3234}
3235
3236
3237/** @callback_method_impl{FNCPUMWRMSR} */
3238static DECLCALLBACK(int) cpumMsrWr_AmdFam10hPStateN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3239{
3240 /** @todo AMD P-states. */
3241 return VINF_SUCCESS;
3242}
3243
3244
3245/** @callback_method_impl{FNCPUMRDMSR} */
3246static DECLCALLBACK(int) cpumMsrRd_AmdFam10hCofVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3247{
3248 /** @todo AMD P-states. */
3249 *puValue = pRange->uValue;
3250 return VINF_SUCCESS;
3251}
3252
3253
3254/** @callback_method_impl{FNCPUMWRMSR} */
3255static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCofVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3256{
3257 /** @todo AMD P-states. */
3258 return VINF_SUCCESS;
3259}
3260
3261
3262/** @callback_method_impl{FNCPUMRDMSR} */
3263static DECLCALLBACK(int) cpumMsrRd_AmdFam10hCofVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3264{
3265 /** @todo AMD P-states. */
3266 *puValue = pRange->uValue;
3267 return VINF_SUCCESS;
3268}
3269
3270
3271/** @callback_method_impl{FNCPUMWRMSR} */
3272static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCofVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3273{
3274 /* Note! Writing 0 seems to not GP, not sure if it does anything to the value... */
3275 /** @todo AMD P-states. */
3276 return VINF_SUCCESS;
3277}
3278
3279
3280/** @callback_method_impl{FNCPUMRDMSR} */
3281static DECLCALLBACK(int) cpumMsrRd_AmdFam10hCStateIoBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3282{
3283 /** @todo AMD C-states. */
3284 *puValue = 0;
3285 return VINF_SUCCESS;
3286}
3287
3288
3289/** @callback_method_impl{FNCPUMWRMSR} */
3290static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCStateIoBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3291{
3292 /** @todo AMD C-states. */
3293 return VINF_SUCCESS;
3294}
3295
3296
3297/** @callback_method_impl{FNCPUMRDMSR} */
3298static DECLCALLBACK(int) cpumMsrRd_AmdFam10hCpuWatchdogTimer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3299{
3300 /** @todo AMD machine checks. */
3301 *puValue = 0;
3302 return VINF_SUCCESS;
3303}
3304
3305
3306/** @callback_method_impl{FNCPUMWRMSR} */
3307static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCpuWatchdogTimer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3308{
3309 /** @todo AMD machine checks. */
3310 return VINF_SUCCESS;
3311}
3312
3313
3314/** @callback_method_impl{FNCPUMRDMSR} */
3315static DECLCALLBACK(int) cpumMsrRd_AmdK8SmmBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3316{
3317 /** @todo AMD SMM. */
3318 *puValue = 0;
3319 return VINF_SUCCESS;
3320}
3321
3322
3323/** @callback_method_impl{FNCPUMWRMSR} */
3324static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3325{
3326 /** @todo AMD SMM. */
3327 return VINF_SUCCESS;
3328}
3329
3330
3331/** @callback_method_impl{FNCPUMRDMSR} */
3332static DECLCALLBACK(int) cpumMsrRd_AmdK8SmmAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3333{
3334 /** @todo AMD SMM. */
3335 *puValue = 0;
3336 return VINF_SUCCESS;
3337}
3338
3339
3340/** @callback_method_impl{FNCPUMWRMSR} */
3341static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3342{
3343 /** @todo AMD SMM. */
3344 return VINF_SUCCESS;
3345}
3346
3347
3348
3349/** @callback_method_impl{FNCPUMRDMSR} */
3350static DECLCALLBACK(int) cpumMsrRd_AmdK8SmmMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3351{
3352 /** @todo AMD SMM. */
3353 *puValue = 0;
3354 return VINF_SUCCESS;
3355}
3356
3357
3358/** @callback_method_impl{FNCPUMWRMSR} */
3359static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3360{
3361 /** @todo AMD SMM. */
3362 return VINF_SUCCESS;
3363}
3364
3365
3366/** @callback_method_impl{FNCPUMRDMSR} */
3367static DECLCALLBACK(int) cpumMsrRd_AmdK8VmCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3368{
3369 /** @todo AMD SVM. */
3370 *puValue = 0;
3371 return VINF_SUCCESS;
3372}
3373
3374
3375/** @callback_method_impl{FNCPUMWRMSR} */
3376static DECLCALLBACK(int) cpumMsrWr_AmdK8VmCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3377{
3378 /** @todo AMD SVM. */
3379 return VINF_SUCCESS;
3380}
3381
3382
3383/** @callback_method_impl{FNCPUMRDMSR} */
3384static DECLCALLBACK(int) cpumMsrRd_AmdK8IgnNe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3385{
3386 /** @todo AMD IGNNE\# control. */
3387 *puValue = 0;
3388 return VINF_SUCCESS;
3389}
3390
3391
3392/** @callback_method_impl{FNCPUMWRMSR} */
3393static DECLCALLBACK(int) cpumMsrWr_AmdK8IgnNe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3394{
3395 /** @todo AMD IGNNE\# control. */
3396 return VINF_SUCCESS;
3397}
3398
3399
3400/** @callback_method_impl{FNCPUMRDMSR} */
3401static DECLCALLBACK(int) cpumMsrRd_AmdK8SmmCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3402{
3403 /** @todo AMD SMM. */
3404 *puValue = 0;
3405 return VINF_SUCCESS;
3406}
3407
3408
3409/** @callback_method_impl{FNCPUMWRMSR} */
3410static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3411{
3412 /** @todo AMD SMM. */
3413 return VINF_SUCCESS;
3414}
3415
3416
3417/** @callback_method_impl{FNCPUMRDMSR} */
3418static DECLCALLBACK(int) cpumMsrRd_AmdK8VmHSavePa(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3419{
3420 /** @todo AMD SVM. */
3421 *puValue = 0;
3422 return VINF_SUCCESS;
3423}
3424
3425
3426/** @callback_method_impl{FNCPUMWRMSR} */
3427static DECLCALLBACK(int) cpumMsrWr_AmdK8VmHSavePa(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3428{
3429 /** @todo AMD SVM. */
3430 return VINF_SUCCESS;
3431}
3432
3433
3434/** @callback_method_impl{FNCPUMRDMSR} */
3435static DECLCALLBACK(int) cpumMsrRd_AmdFam10hVmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3436{
3437 /** @todo AMD SVM. */
3438 *puValue = 0; /* RAZ */
3439 return VINF_SUCCESS;
3440}
3441
3442
3443/** @callback_method_impl{FNCPUMWRMSR} */
3444static DECLCALLBACK(int) cpumMsrWr_AmdFam10hVmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3445{
3446 /** @todo AMD SVM. */
3447 return VINF_SUCCESS;
3448}
3449
3450
3451/** @callback_method_impl{FNCPUMRDMSR} */
3452static DECLCALLBACK(int) cpumMsrRd_AmdFam10hSmmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3453{
3454 /** @todo AMD SMM. */
3455 *puValue = 0; /* RAZ */
3456 return VINF_SUCCESS;
3457}
3458
3459
3460/** @callback_method_impl{FNCPUMWRMSR} */
3461static DECLCALLBACK(int) cpumMsrWr_AmdFam10hSmmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3462{
3463 /** @todo AMD SMM. */
3464 return VINF_SUCCESS;
3465}
3466
3467
3468/** @callback_method_impl{FNCPUMRDMSR} */
3469static DECLCALLBACK(int) cpumMsrRd_AmdFam10hLocalSmiStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3470{
3471 /** @todo AMD SMM/SMI. */
3472 *puValue = 0;
3473 return VINF_SUCCESS;
3474}
3475
3476
3477/** @callback_method_impl{FNCPUMWRMSR} */
3478static DECLCALLBACK(int) cpumMsrWr_AmdFam10hLocalSmiStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3479{
3480 /** @todo AMD SMM/SMI. */
3481 return VINF_SUCCESS;
3482}
3483
3484
3485/** @callback_method_impl{FNCPUMRDMSR} */
3486static DECLCALLBACK(int) cpumMsrRd_AmdFam10hOsVisWrkIdLength(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3487{
3488 /** @todo AMD OS visible workaround. */
3489 *puValue = pRange->uValue;
3490 return VINF_SUCCESS;
3491}
3492
3493
3494/** @callback_method_impl{FNCPUMWRMSR} */
3495static DECLCALLBACK(int) cpumMsrWr_AmdFam10hOsVisWrkIdLength(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3496{
3497 /** @todo AMD OS visible workaround. */
3498 return VINF_SUCCESS;
3499}
3500
3501
3502/** @callback_method_impl{FNCPUMRDMSR} */
3503static DECLCALLBACK(int) cpumMsrRd_AmdFam10hOsVisWrkStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3504{
3505 /** @todo AMD OS visible workaround. */
3506 *puValue = 0;
3507 return VINF_SUCCESS;
3508}
3509
3510
3511/** @callback_method_impl{FNCPUMWRMSR} */
3512static DECLCALLBACK(int) cpumMsrWr_AmdFam10hOsVisWrkStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3513{
3514 /** @todo AMD OS visible workaround. */
3515 return VINF_SUCCESS;
3516}
3517
3518
3519/** @callback_method_impl{FNCPUMRDMSR} */
3520static DECLCALLBACK(int) cpumMsrRd_AmdFam16hL2IPerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3521{
3522 /** @todo AMD L2I performance counters. */
3523 *puValue = 0;
3524 return VINF_SUCCESS;
3525}
3526
3527
3528/** @callback_method_impl{FNCPUMWRMSR} */
3529static DECLCALLBACK(int) cpumMsrWr_AmdFam16hL2IPerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3530{
3531 /** @todo AMD L2I performance counters. */
3532 return VINF_SUCCESS;
3533}
3534
3535
3536/** @callback_method_impl{FNCPUMRDMSR} */
3537static DECLCALLBACK(int) cpumMsrRd_AmdFam16hL2IPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3538{
3539 /** @todo AMD L2I performance counters. */
3540 *puValue = 0;
3541 return VINF_SUCCESS;
3542}
3543
3544
3545/** @callback_method_impl{FNCPUMWRMSR} */
3546static DECLCALLBACK(int) cpumMsrWr_AmdFam16hL2IPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3547{
3548 /** @todo AMD L2I performance counters. */
3549 return VINF_SUCCESS;
3550}
3551
3552
3553/** @callback_method_impl{FNCPUMRDMSR} */
3554static DECLCALLBACK(int) cpumMsrRd_AmdFam15hNorthbridgePerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3555{
3556 /** @todo AMD Northbridge performance counters. */
3557 *puValue = 0;
3558 return VINF_SUCCESS;
3559}
3560
3561
3562/** @callback_method_impl{FNCPUMWRMSR} */
3563static DECLCALLBACK(int) cpumMsrWr_AmdFam15hNorthbridgePerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3564{
3565 /** @todo AMD Northbridge performance counters. */
3566 return VINF_SUCCESS;
3567}
3568
3569
3570/** @callback_method_impl{FNCPUMRDMSR} */
3571static DECLCALLBACK(int) cpumMsrRd_AmdFam15hNorthbridgePerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3572{
3573 /** @todo AMD Northbridge performance counters. */
3574 *puValue = 0;
3575 return VINF_SUCCESS;
3576}
3577
3578
3579/** @callback_method_impl{FNCPUMWRMSR} */
3580static DECLCALLBACK(int) cpumMsrWr_AmdFam15hNorthbridgePerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3581{
3582 /** @todo AMD Northbridge performance counters. */
3583 return VINF_SUCCESS;
3584}
3585
3586
3587/** @callback_method_impl{FNCPUMRDMSR} */
3588static DECLCALLBACK(int) cpumMsrRd_AmdK7MicrocodeCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3589{
3590 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3591 * cpus. Need to be explored and verify K7 presence. */
3592 /** @todo Undocumented register only seen mentioned in fam15h erratum \#608. */
3593 *puValue = pRange->uValue;
3594 return VINF_SUCCESS;
3595}
3596
3597
3598/** @callback_method_impl{FNCPUMWRMSR} */
3599static DECLCALLBACK(int) cpumMsrWr_AmdK7MicrocodeCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3600{
3601 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3602 * cpus. Need to be explored and verify K7 presence. */
3603 /** @todo Undocumented register only seen mentioned in fam15h erratum \#608. */
3604 return VINF_SUCCESS;
3605}
3606
3607
3608/** @callback_method_impl{FNCPUMRDMSR} */
3609static DECLCALLBACK(int) cpumMsrRd_AmdK7ClusterIdMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3610{
3611 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3612 * cpus. Need to be explored and verify K7 presence. */
3613 /** @todo Undocumented register only seen mentioned in fam16h BKDG r3.00 when
3614 * describing EBL_CR_POWERON. */
3615 *puValue = pRange->uValue;
3616 return VINF_SUCCESS;
3617}
3618
3619
3620/** @callback_method_impl{FNCPUMWRMSR} */
3621static DECLCALLBACK(int) cpumMsrWr_AmdK7ClusterIdMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3622{
3623 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3624 * cpus. Need to be explored and verify K7 presence. */
3625 /** @todo Undocumented register only seen mentioned in fam16h BKDG r3.00 when
3626 * describing EBL_CR_POWERON. */
3627 return VINF_SUCCESS;
3628}
3629
3630
3631/** @callback_method_impl{FNCPUMRDMSR} */
3632static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuIdCtlStd07hEbax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3633{
3634 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000007, 0);
3635 if (pLeaf)
3636 *puValue = RT_MAKE_U64(pLeaf->uEbx, pLeaf->uEax);
3637 else
3638 *puValue = 0;
3639 return VINF_SUCCESS;
3640}
3641
3642
3643/** @callback_method_impl{FNCPUMWRMSR} */
3644static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlStd07hEbax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3645{
3646 /** @todo Changing CPUID leaf 7/0. */
3647 return VINF_SUCCESS;
3648}
3649
3650
3651/** @callback_method_impl{FNCPUMRDMSR} */
3652static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuIdCtlStd06hEcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3653{
3654 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000006, 0);
3655 if (pLeaf)
3656 *puValue = pLeaf->uEcx;
3657 else
3658 *puValue = 0;
3659 return VINF_SUCCESS;
3660}
3661
3662
3663/** @callback_method_impl{FNCPUMWRMSR} */
3664static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlStd06hEcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3665{
3666 /** @todo Changing CPUID leaf 6. */
3667 return VINF_SUCCESS;
3668}
3669
3670
3671/** @callback_method_impl{FNCPUMRDMSR} */
3672static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuIdCtlStd01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3673{
3674 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000001, 0);
3675 if (pLeaf)
3676 *puValue = RT_MAKE_U64(pLeaf->uEdx, pLeaf->uEcx);
3677 else
3678 *puValue = 0;
3679 return VINF_SUCCESS;
3680}
3681
3682
3683/** @callback_method_impl{FNCPUMWRMSR} */
3684static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlStd01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3685{
3686 /** @todo Changing CPUID leaf 0x80000001. */
3687 return VINF_SUCCESS;
3688}
3689
3690
3691/** @callback_method_impl{FNCPUMRDMSR} */
3692static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuIdCtlExt01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3693{
3694 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x80000001, 0);
3695 if (pLeaf)
3696 *puValue = RT_MAKE_U64(pLeaf->uEdx, pLeaf->uEcx);
3697 else
3698 *puValue = 0;
3699 return VINF_SUCCESS;
3700}
3701
3702
3703/** @callback_method_impl{FNCPUMWRMSR} */
3704static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlExt01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3705{
3706 /** @todo Changing CPUID leaf 0x80000001. */
3707 return VINF_SUCCESS;
3708}
3709
3710
3711/** @callback_method_impl{FNCPUMRDMSR} */
3712static DECLCALLBACK(int) cpumMsrRd_AmdK8PatchLevel(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3713{
3714 /** @todo Fake AMD microcode patching. */
3715 *puValue = pRange->uValue;
3716 return VINF_SUCCESS;
3717}
3718
3719
3720/** @callback_method_impl{FNCPUMWRMSR} */
3721static DECLCALLBACK(int) cpumMsrWr_AmdK8PatchLoader(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3722{
3723 /** @todo Fake AMD microcode patching. */
3724 return VINF_SUCCESS;
3725}
3726
3727
3728/** @callback_method_impl{FNCPUMRDMSR} */
3729static DECLCALLBACK(int) cpumMsrRd_AmdK7DebugStatusMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3730{
3731 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3732 * cpus. Need to be explored and verify K7 presence. */
3733 /** @todo undocumented */
3734 *puValue = 0;
3735 return VINF_SUCCESS;
3736}
3737
3738
3739/** @callback_method_impl{FNCPUMWRMSR} */
3740static DECLCALLBACK(int) cpumMsrWr_AmdK7DebugStatusMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3741{
3742 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3743 * cpus. Need to be explored and verify K7 presence. */
3744 /** @todo undocumented */
3745 return VINF_SUCCESS;
3746}
3747
3748
3749/** @callback_method_impl{FNCPUMRDMSR} */
3750static DECLCALLBACK(int) cpumMsrRd_AmdK7BHTraceBaseMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3751{
3752 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3753 * cpus. Need to be explored and verify K7 presence. */
3754 /** @todo undocumented */
3755 *puValue = 0;
3756 return VINF_SUCCESS;
3757}
3758
3759
3760/** @callback_method_impl{FNCPUMWRMSR} */
3761static DECLCALLBACK(int) cpumMsrWr_AmdK7BHTraceBaseMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3762{
3763 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3764 * cpus. Need to be explored and verify K7 presence. */
3765 /** @todo undocumented */
3766 return VINF_SUCCESS;
3767}
3768
3769
3770/** @callback_method_impl{FNCPUMRDMSR} */
3771static DECLCALLBACK(int) cpumMsrRd_AmdK7BHTracePtrMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3772{
3773 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3774 * cpus. Need to be explored and verify K7 presence. */
3775 /** @todo undocumented */
3776 *puValue = 0;
3777 return VINF_SUCCESS;
3778}
3779
3780
3781/** @callback_method_impl{FNCPUMWRMSR} */
3782static DECLCALLBACK(int) cpumMsrWr_AmdK7BHTracePtrMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3783{
3784 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3785 * cpus. Need to be explored and verify K7 presence. */
3786 /** @todo undocumented */
3787 return VINF_SUCCESS;
3788}
3789
3790
3791/** @callback_method_impl{FNCPUMRDMSR} */
3792static DECLCALLBACK(int) cpumMsrRd_AmdK7BHTraceLimitMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3793{
3794 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3795 * cpus. Need to be explored and verify K7 presence. */
3796 /** @todo undocumented */
3797 *puValue = 0;
3798 return VINF_SUCCESS;
3799}
3800
3801
3802/** @callback_method_impl{FNCPUMWRMSR} */
3803static DECLCALLBACK(int) cpumMsrWr_AmdK7BHTraceLimitMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3804{
3805 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3806 * cpus. Need to be explored and verify K7 presence. */
3807 /** @todo undocumented */
3808 return VINF_SUCCESS;
3809}
3810
3811
3812/** @callback_method_impl{FNCPUMRDMSR} */
3813static DECLCALLBACK(int) cpumMsrRd_AmdK7HardwareDebugToolCfgMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3814{
3815 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3816 * cpus. Need to be explored and verify K7 presence. */
3817 /** @todo undocumented */
3818 *puValue = 0;
3819 return VINF_SUCCESS;
3820}
3821
3822
3823/** @callback_method_impl{FNCPUMWRMSR} */
3824static DECLCALLBACK(int) cpumMsrWr_AmdK7HardwareDebugToolCfgMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3825{
3826 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3827 * cpus. Need to be explored and verify K7 presence. */
3828 /** @todo undocumented */
3829 return VINF_SUCCESS;
3830}
3831
3832
3833/** @callback_method_impl{FNCPUMRDMSR} */
3834static DECLCALLBACK(int) cpumMsrRd_AmdK7FastFlushCountMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3835{
3836 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3837 * cpus. Need to be explored and verify K7 presence. */
3838 /** @todo undocumented */
3839 *puValue = 0;
3840 return VINF_SUCCESS;
3841}
3842
3843
3844/** @callback_method_impl{FNCPUMWRMSR} */
3845static DECLCALLBACK(int) cpumMsrWr_AmdK7FastFlushCountMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3846{
3847 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3848 * cpus. Need to be explored and verify K7 presence. */
3849 /** @todo undocumented */
3850 return VINF_SUCCESS;
3851}
3852
3853
3854/** @callback_method_impl{FNCPUMRDMSR} */
3855static DECLCALLBACK(int) cpumMsrRd_AmdK7NodeId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3856{
3857 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3858 * cpus. Need to be explored and verify K7 presence. */
3859 /** @todo AMD node ID and bios scratch. */
3860 *puValue = 0; /* nodeid = 0; nodes-per-cpu = 1 */
3861 return VINF_SUCCESS;
3862}
3863
3864
3865/** @callback_method_impl{FNCPUMWRMSR} */
3866static DECLCALLBACK(int) cpumMsrWr_AmdK7NodeId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3867{
3868 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3869 * cpus. Need to be explored and verify K7 presence. */
3870 /** @todo AMD node ID and bios scratch. */
3871 return VINF_SUCCESS;
3872}
3873
3874
3875/** @callback_method_impl{FNCPUMRDMSR} */
3876static DECLCALLBACK(int) cpumMsrRd_AmdK7DrXAddrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3877{
3878 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3879 * cpus. Need to be explored and verify K7 presence. */
3880 /** @todo AMD DRx address masking (range breakpoints). */
3881 *puValue = 0;
3882 return VINF_SUCCESS;
3883}
3884
3885
3886/** @callback_method_impl{FNCPUMWRMSR} */
3887static DECLCALLBACK(int) cpumMsrWr_AmdK7DrXAddrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3888{
3889 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3890 * cpus. Need to be explored and verify K7 presence. */
3891 /** @todo AMD DRx address masking (range breakpoints). */
3892 return VINF_SUCCESS;
3893}
3894
3895
3896/** @callback_method_impl{FNCPUMRDMSR} */
3897static DECLCALLBACK(int) cpumMsrRd_AmdK7Dr0DataMatchMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3898{
3899 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3900 * cpus. Need to be explored and verify K7 presence. */
3901 /** @todo AMD undocument debugging features. */
3902 *puValue = 0;
3903 return VINF_SUCCESS;
3904}
3905
3906
3907/** @callback_method_impl{FNCPUMWRMSR} */
3908static DECLCALLBACK(int) cpumMsrWr_AmdK7Dr0DataMatchMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3909{
3910 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3911 * cpus. Need to be explored and verify K7 presence. */
3912 /** @todo AMD undocument debugging features. */
3913 return VINF_SUCCESS;
3914}
3915
3916
3917/** @callback_method_impl{FNCPUMRDMSR} */
3918static DECLCALLBACK(int) cpumMsrRd_AmdK7Dr0DataMaskMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3919{
3920 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3921 * cpus. Need to be explored and verify K7 presence. */
3922 /** @todo AMD undocument debugging features. */
3923 *puValue = 0;
3924 return VINF_SUCCESS;
3925}
3926
3927
3928/** @callback_method_impl{FNCPUMWRMSR} */
3929static DECLCALLBACK(int) cpumMsrWr_AmdK7Dr0DataMaskMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3930{
3931 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3932 * cpus. Need to be explored and verify K7 presence. */
3933 /** @todo AMD undocument debugging features. */
3934 return VINF_SUCCESS;
3935}
3936
3937
3938/** @callback_method_impl{FNCPUMRDMSR} */
3939static DECLCALLBACK(int) cpumMsrRd_AmdK7LoadStoreCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3940{
3941 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3942 * cpus. Need to be explored and verify K7 presence. */
3943 /** @todo AMD load-store config. */
3944 *puValue = 0;
3945 return VINF_SUCCESS;
3946}
3947
3948
3949/** @callback_method_impl{FNCPUMWRMSR} */
3950static DECLCALLBACK(int) cpumMsrWr_AmdK7LoadStoreCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3951{
3952 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3953 * cpus. Need to be explored and verify K7 presence. */
3954 /** @todo AMD load-store config. */
3955 return VINF_SUCCESS;
3956}
3957
3958
3959/** @callback_method_impl{FNCPUMRDMSR} */
3960static DECLCALLBACK(int) cpumMsrRd_AmdK7InstrCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3961{
3962 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3963 * cpus. Need to be explored and verify K7 presence. */
3964 /** @todo AMD instruction cache config. */
3965 *puValue = 0;
3966 return VINF_SUCCESS;
3967}
3968
3969
3970/** @callback_method_impl{FNCPUMWRMSR} */
3971static DECLCALLBACK(int) cpumMsrWr_AmdK7InstrCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3972{
3973 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3974 * cpus. Need to be explored and verify K7 presence. */
3975 /** @todo AMD instruction cache config. */
3976 return VINF_SUCCESS;
3977}
3978
3979
3980/** @callback_method_impl{FNCPUMRDMSR} */
3981static DECLCALLBACK(int) cpumMsrRd_AmdK7DataCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3982{
3983 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3984 * cpus. Need to be explored and verify K7 presence. */
3985 /** @todo AMD data cache config. */
3986 *puValue = 0;
3987 return VINF_SUCCESS;
3988}
3989
3990
3991/** @callback_method_impl{FNCPUMWRMSR} */
3992static DECLCALLBACK(int) cpumMsrWr_AmdK7DataCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3993{
3994 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3995 * cpus. Need to be explored and verify K7 presence. */
3996 /** @todo AMD data cache config. */
3997 return VINF_SUCCESS;
3998}
3999
4000
4001/** @callback_method_impl{FNCPUMRDMSR} */
4002static DECLCALLBACK(int) cpumMsrRd_AmdK7BusUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4003{
4004 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4005 * cpus. Need to be explored and verify K7 presence. */
4006 /** @todo AMD bus unit config. */
4007 *puValue = 0;
4008 return VINF_SUCCESS;
4009}
4010
4011
4012/** @callback_method_impl{FNCPUMWRMSR} */
4013static DECLCALLBACK(int) cpumMsrWr_AmdK7BusUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4014{
4015 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4016 * cpus. Need to be explored and verify K7 presence. */
4017 /** @todo AMD bus unit config. */
4018 return VINF_SUCCESS;
4019}
4020
4021
4022/** @callback_method_impl{FNCPUMRDMSR} */
4023static DECLCALLBACK(int) cpumMsrRd_AmdK7DebugCtl2Maybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4024{
4025 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4026 * cpus. Need to be explored and verify K7 presence. */
4027 /** @todo Undocument AMD debug control register \#2. */
4028 *puValue = 0;
4029 return VINF_SUCCESS;
4030}
4031
4032
4033/** @callback_method_impl{FNCPUMWRMSR} */
4034static DECLCALLBACK(int) cpumMsrWr_AmdK7DebugCtl2Maybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4035{
4036 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4037 * cpus. Need to be explored and verify K7 presence. */
4038 /** @todo Undocument AMD debug control register \#2. */
4039 return VINF_SUCCESS;
4040}
4041
4042
4043/** @callback_method_impl{FNCPUMRDMSR} */
4044static DECLCALLBACK(int) cpumMsrRd_AmdFam15hFpuCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4045{
4046 /** @todo AMD FPU config. */
4047 *puValue = 0;
4048 return VINF_SUCCESS;
4049}
4050
4051
4052/** @callback_method_impl{FNCPUMWRMSR} */
4053static DECLCALLBACK(int) cpumMsrWr_AmdFam15hFpuCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4054{
4055 /** @todo AMD FPU config. */
4056 return VINF_SUCCESS;
4057}
4058
4059
4060/** @callback_method_impl{FNCPUMRDMSR} */
4061static DECLCALLBACK(int) cpumMsrRd_AmdFam15hDecoderCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4062{
4063 /** @todo AMD decoder config. */
4064 *puValue = 0;
4065 return VINF_SUCCESS;
4066}
4067
4068
4069/** @callback_method_impl{FNCPUMWRMSR} */
4070static DECLCALLBACK(int) cpumMsrWr_AmdFam15hDecoderCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4071{
4072 /** @todo AMD decoder config. */
4073 return VINF_SUCCESS;
4074}
4075
4076
4077/** @callback_method_impl{FNCPUMRDMSR} */
4078static DECLCALLBACK(int) cpumMsrRd_AmdFam10hBusUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4079{
4080 /* Note! 10h and 16h */
4081 /** @todo AMD bus unit config. */
4082 *puValue = 0;
4083 return VINF_SUCCESS;
4084}
4085
4086
4087/** @callback_method_impl{FNCPUMWRMSR} */
4088static DECLCALLBACK(int) cpumMsrWr_AmdFam10hBusUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4089{
4090 /* Note! 10h and 16h */
4091 /** @todo AMD bus unit config. */
4092 return VINF_SUCCESS;
4093}
4094
4095
4096/** @callback_method_impl{FNCPUMRDMSR} */
4097static DECLCALLBACK(int) cpumMsrRd_AmdFam15hCombUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4098{
4099 /** @todo AMD unit config. */
4100 *puValue = 0;
4101 return VINF_SUCCESS;
4102}
4103
4104
4105/** @callback_method_impl{FNCPUMWRMSR} */
4106static DECLCALLBACK(int) cpumMsrWr_AmdFam15hCombUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4107{
4108 /** @todo AMD unit config. */
4109 return VINF_SUCCESS;
4110}
4111
4112
4113/** @callback_method_impl{FNCPUMRDMSR} */
4114static DECLCALLBACK(int) cpumMsrRd_AmdFam15hCombUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4115{
4116 /** @todo AMD unit config 2. */
4117 *puValue = 0;
4118 return VINF_SUCCESS;
4119}
4120
4121
4122/** @callback_method_impl{FNCPUMWRMSR} */
4123static DECLCALLBACK(int) cpumMsrWr_AmdFam15hCombUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4124{
4125 /** @todo AMD unit config 2. */
4126 return VINF_SUCCESS;
4127}
4128
4129
4130/** @callback_method_impl{FNCPUMRDMSR} */
4131static DECLCALLBACK(int) cpumMsrRd_AmdFam15hCombUnitCfg3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4132{
4133 /** @todo AMD combined unit config 3. */
4134 *puValue = 0;
4135 return VINF_SUCCESS;
4136}
4137
4138
4139/** @callback_method_impl{FNCPUMWRMSR} */
4140static DECLCALLBACK(int) cpumMsrWr_AmdFam15hCombUnitCfg3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4141{
4142 /** @todo AMD combined unit config 3. */
4143 return VINF_SUCCESS;
4144}
4145
4146
4147/** @callback_method_impl{FNCPUMRDMSR} */
4148static DECLCALLBACK(int) cpumMsrRd_AmdFam15hExecUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4149{
4150 /** @todo AMD execution unit config. */
4151 *puValue = 0;
4152 return VINF_SUCCESS;
4153}
4154
4155
4156/** @callback_method_impl{FNCPUMWRMSR} */
4157static DECLCALLBACK(int) cpumMsrWr_AmdFam15hExecUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4158{
4159 /** @todo AMD execution unit config. */
4160 return VINF_SUCCESS;
4161}
4162
4163
4164/** @callback_method_impl{FNCPUMRDMSR} */
4165static DECLCALLBACK(int) cpumMsrRd_AmdFam15hLoadStoreCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4166{
4167 /** @todo AMD load-store config 2. */
4168 *puValue = 0;
4169 return VINF_SUCCESS;
4170}
4171
4172
4173/** @callback_method_impl{FNCPUMWRMSR} */
4174static DECLCALLBACK(int) cpumMsrWr_AmdFam15hLoadStoreCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4175{
4176 /** @todo AMD load-store config 2. */
4177 return VINF_SUCCESS;
4178}
4179
4180
4181/** @callback_method_impl{FNCPUMRDMSR} */
4182static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsFetchCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4183{
4184 /** @todo AMD IBS. */
4185 *puValue = 0;
4186 return VINF_SUCCESS;
4187}
4188
4189
4190/** @callback_method_impl{FNCPUMWRMSR} */
4191static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsFetchCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4192{
4193 /** @todo AMD IBS. */
4194 return VINF_SUCCESS;
4195}
4196
4197
4198/** @callback_method_impl{FNCPUMRDMSR} */
4199static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsFetchLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4200{
4201 /** @todo AMD IBS. */
4202 *puValue = 0;
4203 return VINF_SUCCESS;
4204}
4205
4206
4207/** @callback_method_impl{FNCPUMWRMSR} */
4208static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsFetchLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4209{
4210 /** @todo AMD IBS. */
4211 return VINF_SUCCESS;
4212}
4213
4214
4215/** @callback_method_impl{FNCPUMRDMSR} */
4216static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsFetchPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4217{
4218 /** @todo AMD IBS. */
4219 *puValue = 0;
4220 return VINF_SUCCESS;
4221}
4222
4223
4224/** @callback_method_impl{FNCPUMWRMSR} */
4225static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsFetchPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4226{
4227 /** @todo AMD IBS. */
4228 return VINF_SUCCESS;
4229}
4230
4231
4232/** @callback_method_impl{FNCPUMRDMSR} */
4233static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpExecCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4234{
4235 /** @todo AMD IBS. */
4236 *puValue = 0;
4237 return VINF_SUCCESS;
4238}
4239
4240
4241/** @callback_method_impl{FNCPUMWRMSR} */
4242static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpExecCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4243{
4244 /** @todo AMD IBS. */
4245 return VINF_SUCCESS;
4246}
4247
4248
4249/** @callback_method_impl{FNCPUMRDMSR} */
4250static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpRip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4251{
4252 /** @todo AMD IBS. */
4253 *puValue = 0;
4254 return VINF_SUCCESS;
4255}
4256
4257
4258/** @callback_method_impl{FNCPUMWRMSR} */
4259static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpRip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4260{
4261 /** @todo AMD IBS. */
4262 if (!X86_IS_CANONICAL(uValue))
4263 {
4264 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
4265 return VERR_CPUM_RAISE_GP_0;
4266 }
4267 return VINF_SUCCESS;
4268}
4269
4270
4271/** @callback_method_impl{FNCPUMRDMSR} */
4272static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpData(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4273{
4274 /** @todo AMD IBS. */
4275 *puValue = 0;
4276 return VINF_SUCCESS;
4277}
4278
4279
4280/** @callback_method_impl{FNCPUMWRMSR} */
4281static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpData(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4282{
4283 /** @todo AMD IBS. */
4284 return VINF_SUCCESS;
4285}
4286
4287
4288/** @callback_method_impl{FNCPUMRDMSR} */
4289static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpData2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4290{
4291 /** @todo AMD IBS. */
4292 *puValue = 0;
4293 return VINF_SUCCESS;
4294}
4295
4296
4297/** @callback_method_impl{FNCPUMWRMSR} */
4298static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpData2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4299{
4300 /** @todo AMD IBS. */
4301 return VINF_SUCCESS;
4302}
4303
4304
4305/** @callback_method_impl{FNCPUMRDMSR} */
4306static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpData3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4307{
4308 /** @todo AMD IBS. */
4309 *puValue = 0;
4310 return VINF_SUCCESS;
4311}
4312
4313
4314/** @callback_method_impl{FNCPUMWRMSR} */
4315static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpData3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4316{
4317 /** @todo AMD IBS. */
4318 return VINF_SUCCESS;
4319}
4320
4321
4322/** @callback_method_impl{FNCPUMRDMSR} */
4323static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsDcLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4324{
4325 /** @todo AMD IBS. */
4326 *puValue = 0;
4327 return VINF_SUCCESS;
4328}
4329
4330
4331/** @callback_method_impl{FNCPUMWRMSR} */
4332static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsDcLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4333{
4334 /** @todo AMD IBS. */
4335 if (!X86_IS_CANONICAL(uValue))
4336 {
4337 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
4338 return VERR_CPUM_RAISE_GP_0;
4339 }
4340 return VINF_SUCCESS;
4341}
4342
4343
4344/** @callback_method_impl{FNCPUMRDMSR} */
4345static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsDcPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4346{
4347 /** @todo AMD IBS. */
4348 *puValue = 0;
4349 return VINF_SUCCESS;
4350}
4351
4352
4353/** @callback_method_impl{FNCPUMWRMSR} */
4354static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsDcPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4355{
4356 /** @todo AMD IBS. */
4357 return VINF_SUCCESS;
4358}
4359
4360
4361/** @callback_method_impl{FNCPUMRDMSR} */
4362static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4363{
4364 /** @todo AMD IBS. */
4365 *puValue = 0;
4366 return VINF_SUCCESS;
4367}
4368
4369
4370/** @callback_method_impl{FNCPUMWRMSR} */
4371static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4372{
4373 /** @todo AMD IBS. */
4374 return VINF_SUCCESS;
4375}
4376
4377
4378/** @callback_method_impl{FNCPUMRDMSR} */
4379static DECLCALLBACK(int) cpumMsrRd_AmdFam14hIbsBrTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4380{
4381 /** @todo AMD IBS. */
4382 *puValue = 0;
4383 return VINF_SUCCESS;
4384}
4385
4386
4387/** @callback_method_impl{FNCPUMWRMSR} */
4388static DECLCALLBACK(int) cpumMsrWr_AmdFam14hIbsBrTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4389{
4390 /** @todo AMD IBS. */
4391 if (!X86_IS_CANONICAL(uValue))
4392 {
4393 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
4394 return VERR_CPUM_RAISE_GP_0;
4395 }
4396 return VINF_SUCCESS;
4397}
4398
4399
4400
4401/*
4402 * GIM MSRs.
4403 * GIM MSRs.
4404 * GIM MSRs.
4405 */
4406
4407
4408/** @callback_method_impl{FNCPUMRDMSR} */
4409static DECLCALLBACK(int) cpumMsrRd_Gim(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4410{
4411 return GIMReadMsr(pVCpu, idMsr, pRange, puValue);
4412}
4413
4414
4415/** @callback_method_impl{FNCPUMWRMSR} */
4416static DECLCALLBACK(int) cpumMsrWr_Gim(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4417{
4418 return GIMWriteMsr(pVCpu, idMsr, pRange, uValue, uRawValue);
4419}
4420
4421
4422/**
4423 * MSR read function table.
4424 */
4425static const PFNCPUMRDMSR g_aCpumRdMsrFns[kCpumMsrRdFn_End] =
4426{
4427 NULL, /* Invalid */
4428 cpumMsrRd_FixedValue,
4429 NULL, /* Alias */
4430 cpumMsrRd_WriteOnly,
4431 cpumMsrRd_Ia32P5McAddr,
4432 cpumMsrRd_Ia32P5McType,
4433 cpumMsrRd_Ia32TimestampCounter,
4434 cpumMsrRd_Ia32PlatformId,
4435 cpumMsrRd_Ia32ApicBase,
4436 cpumMsrRd_Ia32FeatureControl,
4437 cpumMsrRd_Ia32BiosSignId,
4438 cpumMsrRd_Ia32SmmMonitorCtl,
4439 cpumMsrRd_Ia32PmcN,
4440 cpumMsrRd_Ia32MonitorFilterLineSize,
4441 cpumMsrRd_Ia32MPerf,
4442 cpumMsrRd_Ia32APerf,
4443 cpumMsrRd_Ia32MtrrCap,
4444 cpumMsrRd_Ia32MtrrPhysBaseN,
4445 cpumMsrRd_Ia32MtrrPhysMaskN,
4446 cpumMsrRd_Ia32MtrrFixed,
4447 cpumMsrRd_Ia32MtrrDefType,
4448 cpumMsrRd_Ia32Pat,
4449 cpumMsrRd_Ia32SysEnterCs,
4450 cpumMsrRd_Ia32SysEnterEsp,
4451 cpumMsrRd_Ia32SysEnterEip,
4452 cpumMsrRd_Ia32McgCap,
4453 cpumMsrRd_Ia32McgStatus,
4454 cpumMsrRd_Ia32McgCtl,
4455 cpumMsrRd_Ia32DebugCtl,
4456 cpumMsrRd_Ia32SmrrPhysBase,
4457 cpumMsrRd_Ia32SmrrPhysMask,
4458 cpumMsrRd_Ia32PlatformDcaCap,
4459 cpumMsrRd_Ia32CpuDcaCap,
4460 cpumMsrRd_Ia32Dca0Cap,
4461 cpumMsrRd_Ia32PerfEvtSelN,
4462 cpumMsrRd_Ia32PerfStatus,
4463 cpumMsrRd_Ia32PerfCtl,
4464 cpumMsrRd_Ia32FixedCtrN,
4465 cpumMsrRd_Ia32PerfCapabilities,
4466 cpumMsrRd_Ia32FixedCtrCtrl,
4467 cpumMsrRd_Ia32PerfGlobalStatus,
4468 cpumMsrRd_Ia32PerfGlobalCtrl,
4469 cpumMsrRd_Ia32PerfGlobalOvfCtrl,
4470 cpumMsrRd_Ia32PebsEnable,
4471 cpumMsrRd_Ia32ClockModulation,
4472 cpumMsrRd_Ia32ThermInterrupt,
4473 cpumMsrRd_Ia32ThermStatus,
4474 cpumMsrRd_Ia32Therm2Ctl,
4475 cpumMsrRd_Ia32MiscEnable,
4476 cpumMsrRd_Ia32McCtlStatusAddrMiscN,
4477 cpumMsrRd_Ia32McNCtl2,
4478 cpumMsrRd_Ia32DsArea,
4479 cpumMsrRd_Ia32TscDeadline,
4480 cpumMsrRd_Ia32X2ApicN,
4481 cpumMsrRd_Ia32DebugInterface,
4482 cpumMsrRd_Ia32VmxBase,
4483 cpumMsrRd_Ia32VmxPinbasedCtls,
4484 cpumMsrRd_Ia32VmxProcbasedCtls,
4485 cpumMsrRd_Ia32VmxExitCtls,
4486 cpumMsrRd_Ia32VmxEntryCtls,
4487 cpumMsrRd_Ia32VmxMisc,
4488 cpumMsrRd_Ia32VmxCr0Fixed0,
4489 cpumMsrRd_Ia32VmxCr0Fixed1,
4490 cpumMsrRd_Ia32VmxCr4Fixed0,
4491 cpumMsrRd_Ia32VmxCr4Fixed1,
4492 cpumMsrRd_Ia32VmxVmcsEnum,
4493 cpumMsrRd_Ia32VmxProcBasedCtls2,
4494 cpumMsrRd_Ia32VmxEptVpidCap,
4495 cpumMsrRd_Ia32VmxTruePinbasedCtls,
4496 cpumMsrRd_Ia32VmxTrueProcbasedCtls,
4497 cpumMsrRd_Ia32VmxTrueExitCtls,
4498 cpumMsrRd_Ia32VmxTrueEntryCtls,
4499
4500 cpumMsrRd_Amd64Efer,
4501 cpumMsrRd_Amd64SyscallTarget,
4502 cpumMsrRd_Amd64LongSyscallTarget,
4503 cpumMsrRd_Amd64CompSyscallTarget,
4504 cpumMsrRd_Amd64SyscallFlagMask,
4505 cpumMsrRd_Amd64FsBase,
4506 cpumMsrRd_Amd64GsBase,
4507 cpumMsrRd_Amd64KernelGsBase,
4508 cpumMsrRd_Amd64TscAux,
4509
4510 cpumMsrRd_IntelEblCrPowerOn,
4511 cpumMsrRd_IntelI7CoreThreadCount,
4512 cpumMsrRd_IntelP4EbcHardPowerOn,
4513 cpumMsrRd_IntelP4EbcSoftPowerOn,
4514 cpumMsrRd_IntelP4EbcFrequencyId,
4515 cpumMsrRd_IntelP6FsbFrequency,
4516 cpumMsrRd_IntelPlatformInfo,
4517 cpumMsrRd_IntelFlexRatio,
4518 cpumMsrRd_IntelPkgCStConfigControl,
4519 cpumMsrRd_IntelPmgIoCaptureBase,
4520 cpumMsrRd_IntelLastBranchFromToN,
4521 cpumMsrRd_IntelLastBranchFromN,
4522 cpumMsrRd_IntelLastBranchToN,
4523 cpumMsrRd_IntelLastBranchTos,
4524 cpumMsrRd_IntelBblCrCtl,
4525 cpumMsrRd_IntelBblCrCtl3,
4526 cpumMsrRd_IntelI7TemperatureTarget,
4527 cpumMsrRd_IntelI7MsrOffCoreResponseN,
4528 cpumMsrRd_IntelI7MiscPwrMgmt,
4529 cpumMsrRd_IntelP6CrN,
4530 cpumMsrRd_IntelCpuId1FeatureMaskEcdx,
4531 cpumMsrRd_IntelCpuId1FeatureMaskEax,
4532 cpumMsrRd_IntelCpuId80000001FeatureMaskEcdx,
4533 cpumMsrRd_IntelI7SandyAesNiCtl,
4534 cpumMsrRd_IntelI7TurboRatioLimit,
4535 cpumMsrRd_IntelI7LbrSelect,
4536 cpumMsrRd_IntelI7SandyErrorControl,
4537 cpumMsrRd_IntelI7VirtualLegacyWireCap,
4538 cpumMsrRd_IntelI7PowerCtl,
4539 cpumMsrRd_IntelI7SandyPebsNumAlt,
4540 cpumMsrRd_IntelI7PebsLdLat,
4541 cpumMsrRd_IntelI7PkgCnResidencyN,
4542 cpumMsrRd_IntelI7CoreCnResidencyN,
4543 cpumMsrRd_IntelI7SandyVrCurrentConfig,
4544 cpumMsrRd_IntelI7SandyVrMiscConfig,
4545 cpumMsrRd_IntelI7SandyRaplPowerUnit,
4546 cpumMsrRd_IntelI7SandyPkgCnIrtlN,
4547 cpumMsrRd_IntelI7SandyPkgC2Residency,
4548 cpumMsrRd_IntelI7RaplPkgPowerLimit,
4549 cpumMsrRd_IntelI7RaplPkgEnergyStatus,
4550 cpumMsrRd_IntelI7RaplPkgPerfStatus,
4551 cpumMsrRd_IntelI7RaplPkgPowerInfo,
4552 cpumMsrRd_IntelI7RaplDramPowerLimit,
4553 cpumMsrRd_IntelI7RaplDramEnergyStatus,
4554 cpumMsrRd_IntelI7RaplDramPerfStatus,
4555 cpumMsrRd_IntelI7RaplDramPowerInfo,
4556 cpumMsrRd_IntelI7RaplPp0PowerLimit,
4557 cpumMsrRd_IntelI7RaplPp0EnergyStatus,
4558 cpumMsrRd_IntelI7RaplPp0Policy,
4559 cpumMsrRd_IntelI7RaplPp0PerfStatus,
4560 cpumMsrRd_IntelI7RaplPp1PowerLimit,
4561 cpumMsrRd_IntelI7RaplPp1EnergyStatus,
4562 cpumMsrRd_IntelI7RaplPp1Policy,
4563 cpumMsrRd_IntelI7IvyConfigTdpNominal,
4564 cpumMsrRd_IntelI7IvyConfigTdpLevel1,
4565 cpumMsrRd_IntelI7IvyConfigTdpLevel2,
4566 cpumMsrRd_IntelI7IvyConfigTdpControl,
4567 cpumMsrRd_IntelI7IvyTurboActivationRatio,
4568 cpumMsrRd_IntelI7UncPerfGlobalCtrl,
4569 cpumMsrRd_IntelI7UncPerfGlobalStatus,
4570 cpumMsrRd_IntelI7UncPerfGlobalOvfCtrl,
4571 cpumMsrRd_IntelI7UncPerfFixedCtrCtrl,
4572 cpumMsrRd_IntelI7UncPerfFixedCtr,
4573 cpumMsrRd_IntelI7UncCBoxConfig,
4574 cpumMsrRd_IntelI7UncArbPerfCtrN,
4575 cpumMsrRd_IntelI7UncArbPerfEvtSelN,
4576 cpumMsrRd_IntelCore2EmttmCrTablesN,
4577 cpumMsrRd_IntelCore2SmmCStMiscInfo,
4578 cpumMsrRd_IntelCore1ExtConfig,
4579 cpumMsrRd_IntelCore1DtsCalControl,
4580 cpumMsrRd_IntelCore2PeciControl,
4581
4582 cpumMsrRd_P6LastBranchFromIp,
4583 cpumMsrRd_P6LastBranchToIp,
4584 cpumMsrRd_P6LastIntFromIp,
4585 cpumMsrRd_P6LastIntToIp,
4586
4587 cpumMsrRd_AmdFam15hTscRate,
4588 cpumMsrRd_AmdFam15hLwpCfg,
4589 cpumMsrRd_AmdFam15hLwpCbAddr,
4590 cpumMsrRd_AmdFam10hMc4MiscN,
4591 cpumMsrRd_AmdK8PerfCtlN,
4592 cpumMsrRd_AmdK8PerfCtrN,
4593 cpumMsrRd_AmdK8SysCfg,
4594 cpumMsrRd_AmdK8HwCr,
4595 cpumMsrRd_AmdK8IorrBaseN,
4596 cpumMsrRd_AmdK8IorrMaskN,
4597 cpumMsrRd_AmdK8TopOfMemN,
4598 cpumMsrRd_AmdK8NbCfg1,
4599 cpumMsrRd_AmdK8McXcptRedir,
4600 cpumMsrRd_AmdK8CpuNameN,
4601 cpumMsrRd_AmdK8HwThermalCtrl,
4602 cpumMsrRd_AmdK8SwThermalCtrl,
4603 cpumMsrRd_AmdK8FidVidControl,
4604 cpumMsrRd_AmdK8FidVidStatus,
4605 cpumMsrRd_AmdK8McCtlMaskN,
4606 cpumMsrRd_AmdK8SmiOnIoTrapN,
4607 cpumMsrRd_AmdK8SmiOnIoTrapCtlSts,
4608 cpumMsrRd_AmdK8IntPendingMessage,
4609 cpumMsrRd_AmdK8SmiTriggerIoCycle,
4610 cpumMsrRd_AmdFam10hMmioCfgBaseAddr,
4611 cpumMsrRd_AmdFam10hTrapCtlMaybe,
4612 cpumMsrRd_AmdFam10hPStateCurLimit,
4613 cpumMsrRd_AmdFam10hPStateControl,
4614 cpumMsrRd_AmdFam10hPStateStatus,
4615 cpumMsrRd_AmdFam10hPStateN,
4616 cpumMsrRd_AmdFam10hCofVidControl,
4617 cpumMsrRd_AmdFam10hCofVidStatus,
4618 cpumMsrRd_AmdFam10hCStateIoBaseAddr,
4619 cpumMsrRd_AmdFam10hCpuWatchdogTimer,
4620 cpumMsrRd_AmdK8SmmBase,
4621 cpumMsrRd_AmdK8SmmAddr,
4622 cpumMsrRd_AmdK8SmmMask,
4623 cpumMsrRd_AmdK8VmCr,
4624 cpumMsrRd_AmdK8IgnNe,
4625 cpumMsrRd_AmdK8SmmCtl,
4626 cpumMsrRd_AmdK8VmHSavePa,
4627 cpumMsrRd_AmdFam10hVmLockKey,
4628 cpumMsrRd_AmdFam10hSmmLockKey,
4629 cpumMsrRd_AmdFam10hLocalSmiStatus,
4630 cpumMsrRd_AmdFam10hOsVisWrkIdLength,
4631 cpumMsrRd_AmdFam10hOsVisWrkStatus,
4632 cpumMsrRd_AmdFam16hL2IPerfCtlN,
4633 cpumMsrRd_AmdFam16hL2IPerfCtrN,
4634 cpumMsrRd_AmdFam15hNorthbridgePerfCtlN,
4635 cpumMsrRd_AmdFam15hNorthbridgePerfCtrN,
4636 cpumMsrRd_AmdK7MicrocodeCtl,
4637 cpumMsrRd_AmdK7ClusterIdMaybe,
4638 cpumMsrRd_AmdK8CpuIdCtlStd07hEbax,
4639 cpumMsrRd_AmdK8CpuIdCtlStd06hEcx,
4640 cpumMsrRd_AmdK8CpuIdCtlStd01hEdcx,
4641 cpumMsrRd_AmdK8CpuIdCtlExt01hEdcx,
4642 cpumMsrRd_AmdK8PatchLevel,
4643 cpumMsrRd_AmdK7DebugStatusMaybe,
4644 cpumMsrRd_AmdK7BHTraceBaseMaybe,
4645 cpumMsrRd_AmdK7BHTracePtrMaybe,
4646 cpumMsrRd_AmdK7BHTraceLimitMaybe,
4647 cpumMsrRd_AmdK7HardwareDebugToolCfgMaybe,
4648 cpumMsrRd_AmdK7FastFlushCountMaybe,
4649 cpumMsrRd_AmdK7NodeId,
4650 cpumMsrRd_AmdK7DrXAddrMaskN,
4651 cpumMsrRd_AmdK7Dr0DataMatchMaybe,
4652 cpumMsrRd_AmdK7Dr0DataMaskMaybe,
4653 cpumMsrRd_AmdK7LoadStoreCfg,
4654 cpumMsrRd_AmdK7InstrCacheCfg,
4655 cpumMsrRd_AmdK7DataCacheCfg,
4656 cpumMsrRd_AmdK7BusUnitCfg,
4657 cpumMsrRd_AmdK7DebugCtl2Maybe,
4658 cpumMsrRd_AmdFam15hFpuCfg,
4659 cpumMsrRd_AmdFam15hDecoderCfg,
4660 cpumMsrRd_AmdFam10hBusUnitCfg2,
4661 cpumMsrRd_AmdFam15hCombUnitCfg,
4662 cpumMsrRd_AmdFam15hCombUnitCfg2,
4663 cpumMsrRd_AmdFam15hCombUnitCfg3,
4664 cpumMsrRd_AmdFam15hExecUnitCfg,
4665 cpumMsrRd_AmdFam15hLoadStoreCfg2,
4666 cpumMsrRd_AmdFam10hIbsFetchCtl,
4667 cpumMsrRd_AmdFam10hIbsFetchLinAddr,
4668 cpumMsrRd_AmdFam10hIbsFetchPhysAddr,
4669 cpumMsrRd_AmdFam10hIbsOpExecCtl,
4670 cpumMsrRd_AmdFam10hIbsOpRip,
4671 cpumMsrRd_AmdFam10hIbsOpData,
4672 cpumMsrRd_AmdFam10hIbsOpData2,
4673 cpumMsrRd_AmdFam10hIbsOpData3,
4674 cpumMsrRd_AmdFam10hIbsDcLinAddr,
4675 cpumMsrRd_AmdFam10hIbsDcPhysAddr,
4676 cpumMsrRd_AmdFam10hIbsCtl,
4677 cpumMsrRd_AmdFam14hIbsBrTarget,
4678
4679 cpumMsrRd_Gim
4680};
4681
4682
4683/**
4684 * MSR write function table.
4685 */
4686static const PFNCPUMWRMSR g_aCpumWrMsrFns[kCpumMsrWrFn_End] =
4687{
4688 NULL, /* Invalid */
4689 cpumMsrWr_IgnoreWrite,
4690 cpumMsrWr_ReadOnly,
4691 NULL, /* Alias */
4692 cpumMsrWr_Ia32P5McAddr,
4693 cpumMsrWr_Ia32P5McType,
4694 cpumMsrWr_Ia32TimestampCounter,
4695 cpumMsrWr_Ia32ApicBase,
4696 cpumMsrWr_Ia32FeatureControl,
4697 cpumMsrWr_Ia32BiosSignId,
4698 cpumMsrWr_Ia32BiosUpdateTrigger,
4699 cpumMsrWr_Ia32SmmMonitorCtl,
4700 cpumMsrWr_Ia32PmcN,
4701 cpumMsrWr_Ia32MonitorFilterLineSize,
4702 cpumMsrWr_Ia32MPerf,
4703 cpumMsrWr_Ia32APerf,
4704 cpumMsrWr_Ia32MtrrPhysBaseN,
4705 cpumMsrWr_Ia32MtrrPhysMaskN,
4706 cpumMsrWr_Ia32MtrrFixed,
4707 cpumMsrWr_Ia32MtrrDefType,
4708 cpumMsrWr_Ia32Pat,
4709 cpumMsrWr_Ia32SysEnterCs,
4710 cpumMsrWr_Ia32SysEnterEsp,
4711 cpumMsrWr_Ia32SysEnterEip,
4712 cpumMsrWr_Ia32McgStatus,
4713 cpumMsrWr_Ia32McgCtl,
4714 cpumMsrWr_Ia32DebugCtl,
4715 cpumMsrWr_Ia32SmrrPhysBase,
4716 cpumMsrWr_Ia32SmrrPhysMask,
4717 cpumMsrWr_Ia32PlatformDcaCap,
4718 cpumMsrWr_Ia32Dca0Cap,
4719 cpumMsrWr_Ia32PerfEvtSelN,
4720 cpumMsrWr_Ia32PerfStatus,
4721 cpumMsrWr_Ia32PerfCtl,
4722 cpumMsrWr_Ia32FixedCtrN,
4723 cpumMsrWr_Ia32PerfCapabilities,
4724 cpumMsrWr_Ia32FixedCtrCtrl,
4725 cpumMsrWr_Ia32PerfGlobalStatus,
4726 cpumMsrWr_Ia32PerfGlobalCtrl,
4727 cpumMsrWr_Ia32PerfGlobalOvfCtrl,
4728 cpumMsrWr_Ia32PebsEnable,
4729 cpumMsrWr_Ia32ClockModulation,
4730 cpumMsrWr_Ia32ThermInterrupt,
4731 cpumMsrWr_Ia32ThermStatus,
4732 cpumMsrWr_Ia32Therm2Ctl,
4733 cpumMsrWr_Ia32MiscEnable,
4734 cpumMsrWr_Ia32McCtlStatusAddrMiscN,
4735 cpumMsrWr_Ia32McNCtl2,
4736 cpumMsrWr_Ia32DsArea,
4737 cpumMsrWr_Ia32TscDeadline,
4738 cpumMsrWr_Ia32X2ApicN,
4739 cpumMsrWr_Ia32DebugInterface,
4740
4741 cpumMsrWr_Amd64Efer,
4742 cpumMsrWr_Amd64SyscallTarget,
4743 cpumMsrWr_Amd64LongSyscallTarget,
4744 cpumMsrWr_Amd64CompSyscallTarget,
4745 cpumMsrWr_Amd64SyscallFlagMask,
4746 cpumMsrWr_Amd64FsBase,
4747 cpumMsrWr_Amd64GsBase,
4748 cpumMsrWr_Amd64KernelGsBase,
4749 cpumMsrWr_Amd64TscAux,
4750
4751 cpumMsrWr_IntelEblCrPowerOn,
4752 cpumMsrWr_IntelP4EbcHardPowerOn,
4753 cpumMsrWr_IntelP4EbcSoftPowerOn,
4754 cpumMsrWr_IntelP4EbcFrequencyId,
4755 cpumMsrWr_IntelFlexRatio,
4756 cpumMsrWr_IntelPkgCStConfigControl,
4757 cpumMsrWr_IntelPmgIoCaptureBase,
4758 cpumMsrWr_IntelLastBranchFromToN,
4759 cpumMsrWr_IntelLastBranchFromN,
4760 cpumMsrWr_IntelLastBranchToN,
4761 cpumMsrWr_IntelLastBranchTos,
4762 cpumMsrWr_IntelBblCrCtl,
4763 cpumMsrWr_IntelBblCrCtl3,
4764 cpumMsrWr_IntelI7TemperatureTarget,
4765 cpumMsrWr_IntelI7MsrOffCoreResponseN,
4766 cpumMsrWr_IntelI7MiscPwrMgmt,
4767 cpumMsrWr_IntelP6CrN,
4768 cpumMsrWr_IntelCpuId1FeatureMaskEcdx,
4769 cpumMsrWr_IntelCpuId1FeatureMaskEax,
4770 cpumMsrWr_IntelCpuId80000001FeatureMaskEcdx,
4771 cpumMsrWr_IntelI7SandyAesNiCtl,
4772 cpumMsrWr_IntelI7TurboRatioLimit,
4773 cpumMsrWr_IntelI7LbrSelect,
4774 cpumMsrWr_IntelI7SandyErrorControl,
4775 cpumMsrWr_IntelI7PowerCtl,
4776 cpumMsrWr_IntelI7SandyPebsNumAlt,
4777 cpumMsrWr_IntelI7PebsLdLat,
4778 cpumMsrWr_IntelI7SandyVrCurrentConfig,
4779 cpumMsrWr_IntelI7SandyVrMiscConfig,
4780 cpumMsrWr_IntelI7SandyPkgCnIrtlN,
4781 cpumMsrWr_IntelI7RaplPkgPowerLimit,
4782 cpumMsrWr_IntelI7RaplDramPowerLimit,
4783 cpumMsrWr_IntelI7RaplPp0PowerLimit,
4784 cpumMsrWr_IntelI7RaplPp0Policy,
4785 cpumMsrWr_IntelI7RaplPp1PowerLimit,
4786 cpumMsrWr_IntelI7RaplPp1Policy,
4787 cpumMsrWr_IntelI7IvyConfigTdpControl,
4788 cpumMsrWr_IntelI7IvyTurboActivationRatio,
4789 cpumMsrWr_IntelI7UncPerfGlobalCtrl,
4790 cpumMsrWr_IntelI7UncPerfGlobalStatus,
4791 cpumMsrWr_IntelI7UncPerfGlobalOvfCtrl,
4792 cpumMsrWr_IntelI7UncPerfFixedCtrCtrl,
4793 cpumMsrWr_IntelI7UncPerfFixedCtr,
4794 cpumMsrWr_IntelI7UncArbPerfCtrN,
4795 cpumMsrWr_IntelI7UncArbPerfEvtSelN,
4796 cpumMsrWr_IntelCore2EmttmCrTablesN,
4797 cpumMsrWr_IntelCore2SmmCStMiscInfo,
4798 cpumMsrWr_IntelCore1ExtConfig,
4799 cpumMsrWr_IntelCore1DtsCalControl,
4800 cpumMsrWr_IntelCore2PeciControl,
4801
4802 cpumMsrWr_P6LastIntFromIp,
4803 cpumMsrWr_P6LastIntToIp,
4804
4805 cpumMsrWr_AmdFam15hTscRate,
4806 cpumMsrWr_AmdFam15hLwpCfg,
4807 cpumMsrWr_AmdFam15hLwpCbAddr,
4808 cpumMsrWr_AmdFam10hMc4MiscN,
4809 cpumMsrWr_AmdK8PerfCtlN,
4810 cpumMsrWr_AmdK8PerfCtrN,
4811 cpumMsrWr_AmdK8SysCfg,
4812 cpumMsrWr_AmdK8HwCr,
4813 cpumMsrWr_AmdK8IorrBaseN,
4814 cpumMsrWr_AmdK8IorrMaskN,
4815 cpumMsrWr_AmdK8TopOfMemN,
4816 cpumMsrWr_AmdK8NbCfg1,
4817 cpumMsrWr_AmdK8McXcptRedir,
4818 cpumMsrWr_AmdK8CpuNameN,
4819 cpumMsrWr_AmdK8HwThermalCtrl,
4820 cpumMsrWr_AmdK8SwThermalCtrl,
4821 cpumMsrWr_AmdK8FidVidControl,
4822 cpumMsrWr_AmdK8McCtlMaskN,
4823 cpumMsrWr_AmdK8SmiOnIoTrapN,
4824 cpumMsrWr_AmdK8SmiOnIoTrapCtlSts,
4825 cpumMsrWr_AmdK8IntPendingMessage,
4826 cpumMsrWr_AmdK8SmiTriggerIoCycle,
4827 cpumMsrWr_AmdFam10hMmioCfgBaseAddr,
4828 cpumMsrWr_AmdFam10hTrapCtlMaybe,
4829 cpumMsrWr_AmdFam10hPStateControl,
4830 cpumMsrWr_AmdFam10hPStateStatus,
4831 cpumMsrWr_AmdFam10hPStateN,
4832 cpumMsrWr_AmdFam10hCofVidControl,
4833 cpumMsrWr_AmdFam10hCofVidStatus,
4834 cpumMsrWr_AmdFam10hCStateIoBaseAddr,
4835 cpumMsrWr_AmdFam10hCpuWatchdogTimer,
4836 cpumMsrWr_AmdK8SmmBase,
4837 cpumMsrWr_AmdK8SmmAddr,
4838 cpumMsrWr_AmdK8SmmMask,
4839 cpumMsrWr_AmdK8VmCr,
4840 cpumMsrWr_AmdK8IgnNe,
4841 cpumMsrWr_AmdK8SmmCtl,
4842 cpumMsrWr_AmdK8VmHSavePa,
4843 cpumMsrWr_AmdFam10hVmLockKey,
4844 cpumMsrWr_AmdFam10hSmmLockKey,
4845 cpumMsrWr_AmdFam10hLocalSmiStatus,
4846 cpumMsrWr_AmdFam10hOsVisWrkIdLength,
4847 cpumMsrWr_AmdFam10hOsVisWrkStatus,
4848 cpumMsrWr_AmdFam16hL2IPerfCtlN,
4849 cpumMsrWr_AmdFam16hL2IPerfCtrN,
4850 cpumMsrWr_AmdFam15hNorthbridgePerfCtlN,
4851 cpumMsrWr_AmdFam15hNorthbridgePerfCtrN,
4852 cpumMsrWr_AmdK7MicrocodeCtl,
4853 cpumMsrWr_AmdK7ClusterIdMaybe,
4854 cpumMsrWr_AmdK8CpuIdCtlStd07hEbax,
4855 cpumMsrWr_AmdK8CpuIdCtlStd06hEcx,
4856 cpumMsrWr_AmdK8CpuIdCtlStd01hEdcx,
4857 cpumMsrWr_AmdK8CpuIdCtlExt01hEdcx,
4858 cpumMsrWr_AmdK8PatchLoader,
4859 cpumMsrWr_AmdK7DebugStatusMaybe,
4860 cpumMsrWr_AmdK7BHTraceBaseMaybe,
4861 cpumMsrWr_AmdK7BHTracePtrMaybe,
4862 cpumMsrWr_AmdK7BHTraceLimitMaybe,
4863 cpumMsrWr_AmdK7HardwareDebugToolCfgMaybe,
4864 cpumMsrWr_AmdK7FastFlushCountMaybe,
4865 cpumMsrWr_AmdK7NodeId,
4866 cpumMsrWr_AmdK7DrXAddrMaskN,
4867 cpumMsrWr_AmdK7Dr0DataMatchMaybe,
4868 cpumMsrWr_AmdK7Dr0DataMaskMaybe,
4869 cpumMsrWr_AmdK7LoadStoreCfg,
4870 cpumMsrWr_AmdK7InstrCacheCfg,
4871 cpumMsrWr_AmdK7DataCacheCfg,
4872 cpumMsrWr_AmdK7BusUnitCfg,
4873 cpumMsrWr_AmdK7DebugCtl2Maybe,
4874 cpumMsrWr_AmdFam15hFpuCfg,
4875 cpumMsrWr_AmdFam15hDecoderCfg,
4876 cpumMsrWr_AmdFam10hBusUnitCfg2,
4877 cpumMsrWr_AmdFam15hCombUnitCfg,
4878 cpumMsrWr_AmdFam15hCombUnitCfg2,
4879 cpumMsrWr_AmdFam15hCombUnitCfg3,
4880 cpumMsrWr_AmdFam15hExecUnitCfg,
4881 cpumMsrWr_AmdFam15hLoadStoreCfg2,
4882 cpumMsrWr_AmdFam10hIbsFetchCtl,
4883 cpumMsrWr_AmdFam10hIbsFetchLinAddr,
4884 cpumMsrWr_AmdFam10hIbsFetchPhysAddr,
4885 cpumMsrWr_AmdFam10hIbsOpExecCtl,
4886 cpumMsrWr_AmdFam10hIbsOpRip,
4887 cpumMsrWr_AmdFam10hIbsOpData,
4888 cpumMsrWr_AmdFam10hIbsOpData2,
4889 cpumMsrWr_AmdFam10hIbsOpData3,
4890 cpumMsrWr_AmdFam10hIbsDcLinAddr,
4891 cpumMsrWr_AmdFam10hIbsDcPhysAddr,
4892 cpumMsrWr_AmdFam10hIbsCtl,
4893 cpumMsrWr_AmdFam14hIbsBrTarget,
4894
4895 cpumMsrWr_Gim
4896};
4897
4898
4899/**
4900 * Looks up the range for the given MSR.
4901 *
4902 * @returns Pointer to the range if found, NULL if not.
4903 * @param pVM The cross context VM structure.
4904 * @param idMsr The MSR to look up.
4905 */
4906# ifndef IN_RING3
4907static
4908# endif
4909PCPUMMSRRANGE cpumLookupMsrRange(PVM pVM, uint32_t idMsr)
4910{
4911 /*
4912 * Binary lookup.
4913 */
4914 uint32_t cRanges = pVM->cpum.s.GuestInfo.cMsrRanges;
4915 if (!cRanges)
4916 return NULL;
4917 PCPUMMSRRANGE paRanges = pVM->cpum.s.GuestInfo.CTX_SUFF(paMsrRanges);
4918 for (;;)
4919 {
4920 uint32_t i = cRanges / 2;
4921 if (idMsr < paRanges[i].uFirst)
4922 {
4923 if (i == 0)
4924 break;
4925 cRanges = i;
4926 }
4927 else if (idMsr > paRanges[i].uLast)
4928 {
4929 i++;
4930 if (i >= cRanges)
4931 break;
4932 cRanges -= i;
4933 paRanges = &paRanges[i];
4934 }
4935 else
4936 {
4937 if (paRanges[i].enmRdFn == kCpumMsrRdFn_MsrAlias)
4938 return cpumLookupMsrRange(pVM, paRanges[i].uValue);
4939 return &paRanges[i];
4940 }
4941 }
4942
4943# ifdef VBOX_STRICT
4944 /*
4945 * Linear lookup to verify the above binary search.
4946 */
4947 uint32_t cLeft = pVM->cpum.s.GuestInfo.cMsrRanges;
4948 PCPUMMSRRANGE pCur = pVM->cpum.s.GuestInfo.CTX_SUFF(paMsrRanges);
4949 while (cLeft-- > 0)
4950 {
4951 if (idMsr >= pCur->uFirst && idMsr <= pCur->uLast)
4952 {
4953 AssertFailed();
4954 if (pCur->enmRdFn == kCpumMsrRdFn_MsrAlias)
4955 return cpumLookupMsrRange(pVM, pCur->uValue);
4956 return pCur;
4957 }
4958 pCur++;
4959 }
4960# endif
4961 return NULL;
4962}
4963
4964#ifdef VBOX_WITH_NEW_MSR_CODE
4965
4966/**
4967 * Query a guest MSR.
4968 *
4969 * The caller is responsible for checking privilege if the call is the result of
4970 * a RDMSR instruction. We'll do the rest.
4971 *
4972 * @retval VINF_SUCCESS on success.
4973 * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR), the caller is
4974 * expected to take the appropriate actions. @a *puValue is set to 0.
4975 * @param pVCpu Pointer to the VMCPU.
4976 * @param idMsr The MSR.
4977 * @param puValue Where to return the value.
4978 *
4979 * @remarks This will always return the right values, even when we're in the
4980 * recompiler.
4981 */
4982VMMDECL(int) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue)
4983{
4984 *puValue = 0;
4985
4986 int rc;
4987 PVM pVM = pVCpu->CTX_SUFF(pVM);
4988 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, idMsr);
4989 if (pRange)
4990 {
4991 CPUMMSRRDFN enmRdFn = (CPUMMSRRDFN)pRange->enmRdFn;
4992 AssertReturn(enmRdFn > kCpumMsrRdFn_Invalid && enmRdFn < kCpumMsrRdFn_End, VERR_CPUM_IPE_1);
4993
4994 PFNCPUMRDMSR pfnRdMsr = g_aCpumRdMsrFns[enmRdFn];
4995 AssertReturn(pfnRdMsr, VERR_CPUM_IPE_2);
4996
4997 STAM_COUNTER_INC(&pRange->cReads);
4998 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReads);
4999
5000 rc = pfnRdMsr(pVCpu, idMsr, pRange, puValue);
5001 if (RT_SUCCESS(rc))
5002 {
5003 Log2(("CPUM: RDMSR %#x (%s) -> %#llx\n", idMsr, pRange->szName, *puValue));
5004 AssertMsg(rc == VINF_SUCCESS, ("%Rrc idMsr=%#x\n", rc, idMsr));
5005 }
5006 else if (rc == VERR_CPUM_RAISE_GP_0)
5007 {
5008 Log(("CPUM: RDMSR %#x (%s) -> #GP(0)\n", idMsr, pRange->szName));
5009 STAM_COUNTER_INC(&pRange->cGps);
5010 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReadsRaiseGp);
5011 }
5012 else
5013 Log(("CPUM: RDMSR %#x (%s) -> rc=%Rrc\n", idMsr, pRange->szName, rc));
5014 }
5015 else
5016 {
5017 Log(("CPUM: Unknown RDMSR %#x -> #GP(0)\n", idMsr));
5018 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReads);
5019 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReadsUnknown);
5020 rc = VERR_CPUM_RAISE_GP_0;
5021 }
5022 return rc;
5023}
5024
5025
5026/**
5027 * Writes to a guest MSR.
5028 *
5029 * The caller is responsible for checking privilege if the call is the result of
5030 * a WRMSR instruction. We'll do the rest.
5031 *
5032 * @retval VINF_SUCCESS on success.
5033 * @retval VERR_CPUM_RAISE_GP_0 on failure, the caller is expected to take the
5034 * appropriate actions.
5035 *
5036 * @param pVCpu Pointer to the VMCPU.
5037 * @param idMsr The MSR id.
5038 * @param uValue The value to set.
5039 *
5040 * @remarks Everyone changing MSR values, including the recompiler, shall do it
5041 * by calling this method. This makes sure we have current values and
5042 * that we trigger all the right actions when something changes.
5043 *
5044 * For performance reasons, this actually isn't entirely true for some
5045 * MSRs when in HM mode. The code here and in HM must be aware of
5046 * this.
5047 */
5048VMMDECL(int) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue)
5049{
5050 int rc;
5051 PVM pVM = pVCpu->CTX_SUFF(pVM);
5052 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, idMsr);
5053 if (pRange)
5054 {
5055 STAM_COUNTER_INC(&pRange->cWrites);
5056 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWrites);
5057
5058 if (!(uValue & pRange->fWrGpMask))
5059 {
5060 CPUMMSRWRFN enmWrFn = (CPUMMSRWRFN)pRange->enmWrFn;
5061 AssertReturn(enmWrFn > kCpumMsrWrFn_Invalid && enmWrFn < kCpumMsrWrFn_End, VERR_CPUM_IPE_1);
5062
5063 PFNCPUMWRMSR pfnWrMsr = g_aCpumWrMsrFns[enmWrFn];
5064 AssertReturn(pfnWrMsr, VERR_CPUM_IPE_2);
5065
5066 uint64_t uValueAdjusted = uValue & ~pRange->fWrIgnMask;
5067 if (uValueAdjusted != uValue)
5068 {
5069 STAM_COUNTER_INC(&pRange->cIgnoredBits);
5070 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesToIgnoredBits);
5071 }
5072
5073 rc = pfnWrMsr(pVCpu, idMsr, pRange, uValueAdjusted, uValue);
5074 if (RT_SUCCESS(rc))
5075 {
5076 Log2(("CPUM: WRMSR %#x (%s), %#llx [%#llx]\n", idMsr, pRange->szName, uValueAdjusted, uValue));
5077 AssertMsg(rc == VINF_SUCCESS, ("%Rrc idMsr=%#x\n", rc, idMsr));
5078 }
5079 else if (rc == VERR_CPUM_RAISE_GP_0)
5080 {
5081 Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> #GP(0)\n", idMsr, pRange->szName, uValueAdjusted, uValue));
5082 STAM_COUNTER_INC(&pRange->cGps);
5083 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesRaiseGp);
5084 }
5085 else
5086 Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> rc=%Rrc\n", idMsr, pRange->szName, uValueAdjusted, uValue, rc));
5087 }
5088 else
5089 {
5090 Log(("CPUM: WRMSR %#x (%s), %#llx -> #GP(0) - invalid bits %#llx\n",
5091 idMsr, pRange->szName, uValue, uValue & pRange->fWrGpMask));
5092 STAM_COUNTER_INC(&pRange->cGps);
5093 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesRaiseGp);
5094 rc = VERR_CPUM_RAISE_GP_0;
5095 }
5096 }
5097 else
5098 {
5099 Log(("CPUM: Unknown WRMSR %#x, %#llx -> #GP(0)\n", idMsr, uValue));
5100 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWrites);
5101 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesUnknown);
5102 rc = VERR_CPUM_RAISE_GP_0;
5103 }
5104 return rc;
5105}
5106
5107#endif /* VBOX_WITH_NEW_MSR_CODE */
5108
5109
5110#if defined(VBOX_STRICT) && defined(IN_RING3)
5111/**
5112 * Performs some checks on the static data related to MSRs.
5113 *
5114 * @returns VINF_SUCCESS on success, error on failure.
5115 */
5116int cpumR3MsrStrictInitChecks(void)
5117{
5118#define CPUM_ASSERT_RD_MSR_FN(a_Register) \
5119 AssertReturn(g_aCpumRdMsrFns[kCpumMsrRdFn_##a_Register] == cpumMsrRd_##a_Register, VERR_CPUM_IPE_2);
5120#define CPUM_ASSERT_WR_MSR_FN(a_Register) \
5121 AssertReturn(g_aCpumWrMsrFns[kCpumMsrWrFn_##a_Register] == cpumMsrWr_##a_Register, VERR_CPUM_IPE_2);
5122
5123 AssertReturn(g_aCpumRdMsrFns[kCpumMsrRdFn_Invalid] == NULL, VERR_CPUM_IPE_2);
5124 CPUM_ASSERT_RD_MSR_FN(FixedValue);
5125 CPUM_ASSERT_RD_MSR_FN(WriteOnly);
5126 CPUM_ASSERT_RD_MSR_FN(Ia32P5McAddr);
5127 CPUM_ASSERT_RD_MSR_FN(Ia32P5McType);
5128 CPUM_ASSERT_RD_MSR_FN(Ia32TimestampCounter);
5129 CPUM_ASSERT_RD_MSR_FN(Ia32PlatformId);
5130 CPUM_ASSERT_RD_MSR_FN(Ia32ApicBase);
5131 CPUM_ASSERT_RD_MSR_FN(Ia32FeatureControl);
5132 CPUM_ASSERT_RD_MSR_FN(Ia32BiosSignId);
5133 CPUM_ASSERT_RD_MSR_FN(Ia32SmmMonitorCtl);
5134 CPUM_ASSERT_RD_MSR_FN(Ia32PmcN);
5135 CPUM_ASSERT_RD_MSR_FN(Ia32MonitorFilterLineSize);
5136 CPUM_ASSERT_RD_MSR_FN(Ia32MPerf);
5137 CPUM_ASSERT_RD_MSR_FN(Ia32APerf);
5138 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrCap);
5139 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrPhysBaseN);
5140 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrPhysMaskN);
5141 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrFixed);
5142 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrDefType);
5143 CPUM_ASSERT_RD_MSR_FN(Ia32Pat);
5144 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterCs);
5145 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterEsp);
5146 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterEip);
5147 CPUM_ASSERT_RD_MSR_FN(Ia32McgCap);
5148 CPUM_ASSERT_RD_MSR_FN(Ia32McgStatus);
5149 CPUM_ASSERT_RD_MSR_FN(Ia32McgCtl);
5150 CPUM_ASSERT_RD_MSR_FN(Ia32DebugCtl);
5151 CPUM_ASSERT_RD_MSR_FN(Ia32SmrrPhysBase);
5152 CPUM_ASSERT_RD_MSR_FN(Ia32SmrrPhysMask);
5153 CPUM_ASSERT_RD_MSR_FN(Ia32PlatformDcaCap);
5154 CPUM_ASSERT_RD_MSR_FN(Ia32CpuDcaCap);
5155 CPUM_ASSERT_RD_MSR_FN(Ia32Dca0Cap);
5156 CPUM_ASSERT_RD_MSR_FN(Ia32PerfEvtSelN);
5157 CPUM_ASSERT_RD_MSR_FN(Ia32PerfStatus);
5158 CPUM_ASSERT_RD_MSR_FN(Ia32PerfCtl);
5159 CPUM_ASSERT_RD_MSR_FN(Ia32FixedCtrN);
5160 CPUM_ASSERT_RD_MSR_FN(Ia32PerfCapabilities);
5161 CPUM_ASSERT_RD_MSR_FN(Ia32FixedCtrCtrl);
5162 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalStatus);
5163 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalCtrl);
5164 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalOvfCtrl);
5165 CPUM_ASSERT_RD_MSR_FN(Ia32PebsEnable);
5166 CPUM_ASSERT_RD_MSR_FN(Ia32ClockModulation);
5167 CPUM_ASSERT_RD_MSR_FN(Ia32ThermInterrupt);
5168 CPUM_ASSERT_RD_MSR_FN(Ia32ThermStatus);
5169 CPUM_ASSERT_RD_MSR_FN(Ia32MiscEnable);
5170 CPUM_ASSERT_RD_MSR_FN(Ia32McCtlStatusAddrMiscN);
5171 CPUM_ASSERT_RD_MSR_FN(Ia32McNCtl2);
5172 CPUM_ASSERT_RD_MSR_FN(Ia32DsArea);
5173 CPUM_ASSERT_RD_MSR_FN(Ia32TscDeadline);
5174 CPUM_ASSERT_RD_MSR_FN(Ia32X2ApicN);
5175 CPUM_ASSERT_RD_MSR_FN(Ia32DebugInterface);
5176 CPUM_ASSERT_RD_MSR_FN(Ia32VmxBase);
5177 CPUM_ASSERT_RD_MSR_FN(Ia32VmxPinbasedCtls);
5178 CPUM_ASSERT_RD_MSR_FN(Ia32VmxProcbasedCtls);
5179 CPUM_ASSERT_RD_MSR_FN(Ia32VmxExitCtls);
5180 CPUM_ASSERT_RD_MSR_FN(Ia32VmxEntryCtls);
5181 CPUM_ASSERT_RD_MSR_FN(Ia32VmxMisc);
5182 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr0Fixed0);
5183 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr0Fixed1);
5184 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr4Fixed0);
5185 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr4Fixed1);
5186 CPUM_ASSERT_RD_MSR_FN(Ia32VmxVmcsEnum);
5187 CPUM_ASSERT_RD_MSR_FN(Ia32VmxProcBasedCtls2);
5188 CPUM_ASSERT_RD_MSR_FN(Ia32VmxEptVpidCap);
5189 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTruePinbasedCtls);
5190 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueProcbasedCtls);
5191 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueExitCtls);
5192 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueEntryCtls);
5193
5194 CPUM_ASSERT_RD_MSR_FN(Amd64Efer);
5195 CPUM_ASSERT_RD_MSR_FN(Amd64SyscallTarget);
5196 CPUM_ASSERT_RD_MSR_FN(Amd64LongSyscallTarget);
5197 CPUM_ASSERT_RD_MSR_FN(Amd64CompSyscallTarget);
5198 CPUM_ASSERT_RD_MSR_FN(Amd64SyscallFlagMask);
5199 CPUM_ASSERT_RD_MSR_FN(Amd64FsBase);
5200 CPUM_ASSERT_RD_MSR_FN(Amd64GsBase);
5201 CPUM_ASSERT_RD_MSR_FN(Amd64KernelGsBase);
5202 CPUM_ASSERT_RD_MSR_FN(Amd64TscAux);
5203
5204 CPUM_ASSERT_RD_MSR_FN(IntelEblCrPowerOn);
5205 CPUM_ASSERT_RD_MSR_FN(IntelI7CoreThreadCount);
5206 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcHardPowerOn);
5207 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcSoftPowerOn);
5208 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcFrequencyId);
5209 CPUM_ASSERT_RD_MSR_FN(IntelP6FsbFrequency);
5210 CPUM_ASSERT_RD_MSR_FN(IntelPlatformInfo);
5211 CPUM_ASSERT_RD_MSR_FN(IntelFlexRatio);
5212 CPUM_ASSERT_RD_MSR_FN(IntelPkgCStConfigControl);
5213 CPUM_ASSERT_RD_MSR_FN(IntelPmgIoCaptureBase);
5214 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchFromToN);
5215 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchFromN);
5216 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchToN);
5217 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchTos);
5218 CPUM_ASSERT_RD_MSR_FN(IntelBblCrCtl);
5219 CPUM_ASSERT_RD_MSR_FN(IntelBblCrCtl3);
5220 CPUM_ASSERT_RD_MSR_FN(IntelI7TemperatureTarget);
5221 CPUM_ASSERT_RD_MSR_FN(IntelI7MsrOffCoreResponseN);
5222 CPUM_ASSERT_RD_MSR_FN(IntelI7MiscPwrMgmt);
5223 CPUM_ASSERT_RD_MSR_FN(IntelP6CrN);
5224 CPUM_ASSERT_RD_MSR_FN(IntelCpuId1FeatureMaskEcdx);
5225 CPUM_ASSERT_RD_MSR_FN(IntelCpuId1FeatureMaskEax);
5226 CPUM_ASSERT_RD_MSR_FN(IntelCpuId80000001FeatureMaskEcdx);
5227 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyAesNiCtl);
5228 CPUM_ASSERT_RD_MSR_FN(IntelI7TurboRatioLimit);
5229 CPUM_ASSERT_RD_MSR_FN(IntelI7LbrSelect);
5230 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyErrorControl);
5231 CPUM_ASSERT_RD_MSR_FN(IntelI7VirtualLegacyWireCap);
5232 CPUM_ASSERT_RD_MSR_FN(IntelI7PowerCtl);
5233 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPebsNumAlt);
5234 CPUM_ASSERT_RD_MSR_FN(IntelI7PebsLdLat);
5235 CPUM_ASSERT_RD_MSR_FN(IntelI7PkgCnResidencyN);
5236 CPUM_ASSERT_RD_MSR_FN(IntelI7CoreCnResidencyN);
5237 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyVrCurrentConfig);
5238 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyVrMiscConfig);
5239 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyRaplPowerUnit);
5240 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPkgCnIrtlN);
5241 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPkgC2Residency);
5242 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPowerLimit);
5243 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgEnergyStatus);
5244 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPerfStatus);
5245 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPowerInfo);
5246 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPowerLimit);
5247 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramEnergyStatus);
5248 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPerfStatus);
5249 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPowerInfo);
5250 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0PowerLimit);
5251 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0EnergyStatus);
5252 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0Policy);
5253 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0PerfStatus);
5254 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1PowerLimit);
5255 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1EnergyStatus);
5256 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1Policy);
5257 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpNominal);
5258 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpLevel1);
5259 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpLevel2);
5260 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpControl);
5261 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyTurboActivationRatio);
5262 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalCtrl);
5263 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalStatus);
5264 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalOvfCtrl);
5265 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfFixedCtrCtrl);
5266 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfFixedCtr);
5267 CPUM_ASSERT_RD_MSR_FN(IntelI7UncCBoxConfig);
5268 CPUM_ASSERT_RD_MSR_FN(IntelI7UncArbPerfCtrN);
5269 CPUM_ASSERT_RD_MSR_FN(IntelI7UncArbPerfEvtSelN);
5270 CPUM_ASSERT_RD_MSR_FN(IntelCore2EmttmCrTablesN);
5271 CPUM_ASSERT_RD_MSR_FN(IntelCore2SmmCStMiscInfo);
5272 CPUM_ASSERT_RD_MSR_FN(IntelCore1ExtConfig);
5273 CPUM_ASSERT_RD_MSR_FN(IntelCore1DtsCalControl);
5274 CPUM_ASSERT_RD_MSR_FN(IntelCore2PeciControl);
5275
5276 CPUM_ASSERT_RD_MSR_FN(P6LastBranchFromIp);
5277 CPUM_ASSERT_RD_MSR_FN(P6LastBranchToIp);
5278 CPUM_ASSERT_RD_MSR_FN(P6LastIntFromIp);
5279 CPUM_ASSERT_RD_MSR_FN(P6LastIntToIp);
5280
5281 CPUM_ASSERT_RD_MSR_FN(AmdFam15hTscRate);
5282 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLwpCfg);
5283 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLwpCbAddr);
5284 CPUM_ASSERT_RD_MSR_FN(AmdFam10hMc4MiscN);
5285 CPUM_ASSERT_RD_MSR_FN(AmdK8PerfCtlN);
5286 CPUM_ASSERT_RD_MSR_FN(AmdK8PerfCtrN);
5287 CPUM_ASSERT_RD_MSR_FN(AmdK8SysCfg);
5288 CPUM_ASSERT_RD_MSR_FN(AmdK8HwCr);
5289 CPUM_ASSERT_RD_MSR_FN(AmdK8IorrBaseN);
5290 CPUM_ASSERT_RD_MSR_FN(AmdK8IorrMaskN);
5291 CPUM_ASSERT_RD_MSR_FN(AmdK8TopOfMemN);
5292 CPUM_ASSERT_RD_MSR_FN(AmdK8NbCfg1);
5293 CPUM_ASSERT_RD_MSR_FN(AmdK8McXcptRedir);
5294 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuNameN);
5295 CPUM_ASSERT_RD_MSR_FN(AmdK8HwThermalCtrl);
5296 CPUM_ASSERT_RD_MSR_FN(AmdK8SwThermalCtrl);
5297 CPUM_ASSERT_RD_MSR_FN(AmdK8FidVidControl);
5298 CPUM_ASSERT_RD_MSR_FN(AmdK8FidVidStatus);
5299 CPUM_ASSERT_RD_MSR_FN(AmdK8McCtlMaskN);
5300 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiOnIoTrapN);
5301 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiOnIoTrapCtlSts);
5302 CPUM_ASSERT_RD_MSR_FN(AmdK8IntPendingMessage);
5303 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiTriggerIoCycle);
5304 CPUM_ASSERT_RD_MSR_FN(AmdFam10hMmioCfgBaseAddr);
5305 CPUM_ASSERT_RD_MSR_FN(AmdFam10hTrapCtlMaybe);
5306 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateCurLimit);
5307 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateControl);
5308 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateStatus);
5309 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateN);
5310 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCofVidControl);
5311 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCofVidStatus);
5312 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCStateIoBaseAddr);
5313 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCpuWatchdogTimer);
5314 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmBase);
5315 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmAddr);
5316 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmMask);
5317 CPUM_ASSERT_RD_MSR_FN(AmdK8VmCr);
5318 CPUM_ASSERT_RD_MSR_FN(AmdK8IgnNe);
5319 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmCtl);
5320 CPUM_ASSERT_RD_MSR_FN(AmdK8VmHSavePa);
5321 CPUM_ASSERT_RD_MSR_FN(AmdFam10hVmLockKey);
5322 CPUM_ASSERT_RD_MSR_FN(AmdFam10hSmmLockKey);
5323 CPUM_ASSERT_RD_MSR_FN(AmdFam10hLocalSmiStatus);
5324 CPUM_ASSERT_RD_MSR_FN(AmdFam10hOsVisWrkIdLength);
5325 CPUM_ASSERT_RD_MSR_FN(AmdFam10hOsVisWrkStatus);
5326 CPUM_ASSERT_RD_MSR_FN(AmdFam16hL2IPerfCtlN);
5327 CPUM_ASSERT_RD_MSR_FN(AmdFam16hL2IPerfCtrN);
5328 CPUM_ASSERT_RD_MSR_FN(AmdFam15hNorthbridgePerfCtlN);
5329 CPUM_ASSERT_RD_MSR_FN(AmdFam15hNorthbridgePerfCtrN);
5330 CPUM_ASSERT_RD_MSR_FN(AmdK7MicrocodeCtl);
5331 CPUM_ASSERT_RD_MSR_FN(AmdK7ClusterIdMaybe);
5332 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd07hEbax);
5333 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd06hEcx);
5334 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd01hEdcx);
5335 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlExt01hEdcx);
5336 CPUM_ASSERT_RD_MSR_FN(AmdK8PatchLevel);
5337 CPUM_ASSERT_RD_MSR_FN(AmdK7DebugStatusMaybe);
5338 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTraceBaseMaybe);
5339 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTracePtrMaybe);
5340 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTraceLimitMaybe);
5341 CPUM_ASSERT_RD_MSR_FN(AmdK7HardwareDebugToolCfgMaybe);
5342 CPUM_ASSERT_RD_MSR_FN(AmdK7FastFlushCountMaybe);
5343 CPUM_ASSERT_RD_MSR_FN(AmdK7NodeId);
5344 CPUM_ASSERT_RD_MSR_FN(AmdK7DrXAddrMaskN);
5345 CPUM_ASSERT_RD_MSR_FN(AmdK7Dr0DataMatchMaybe);
5346 CPUM_ASSERT_RD_MSR_FN(AmdK7Dr0DataMaskMaybe);
5347 CPUM_ASSERT_RD_MSR_FN(AmdK7LoadStoreCfg);
5348 CPUM_ASSERT_RD_MSR_FN(AmdK7InstrCacheCfg);
5349 CPUM_ASSERT_RD_MSR_FN(AmdK7DataCacheCfg);
5350 CPUM_ASSERT_RD_MSR_FN(AmdK7BusUnitCfg);
5351 CPUM_ASSERT_RD_MSR_FN(AmdK7DebugCtl2Maybe);
5352 CPUM_ASSERT_RD_MSR_FN(AmdFam15hFpuCfg);
5353 CPUM_ASSERT_RD_MSR_FN(AmdFam15hDecoderCfg);
5354 CPUM_ASSERT_RD_MSR_FN(AmdFam10hBusUnitCfg2);
5355 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg);
5356 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg2);
5357 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg3);
5358 CPUM_ASSERT_RD_MSR_FN(AmdFam15hExecUnitCfg);
5359 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLoadStoreCfg2);
5360 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchCtl);
5361 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchLinAddr);
5362 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchPhysAddr);
5363 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpExecCtl);
5364 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpRip);
5365 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData);
5366 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData2);
5367 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData3);
5368 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsDcLinAddr);
5369 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsDcPhysAddr);
5370 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsCtl);
5371 CPUM_ASSERT_RD_MSR_FN(AmdFam14hIbsBrTarget);
5372
5373 CPUM_ASSERT_RD_MSR_FN(Gim)
5374
5375 AssertReturn(g_aCpumWrMsrFns[kCpumMsrWrFn_Invalid] == NULL, VERR_CPUM_IPE_2);
5376 CPUM_ASSERT_WR_MSR_FN(Ia32P5McAddr);
5377 CPUM_ASSERT_WR_MSR_FN(Ia32P5McType);
5378 CPUM_ASSERT_WR_MSR_FN(Ia32TimestampCounter);
5379 CPUM_ASSERT_WR_MSR_FN(Ia32ApicBase);
5380 CPUM_ASSERT_WR_MSR_FN(Ia32FeatureControl);
5381 CPUM_ASSERT_WR_MSR_FN(Ia32BiosSignId);
5382 CPUM_ASSERT_WR_MSR_FN(Ia32BiosUpdateTrigger);
5383 CPUM_ASSERT_WR_MSR_FN(Ia32SmmMonitorCtl);
5384 CPUM_ASSERT_WR_MSR_FN(Ia32PmcN);
5385 CPUM_ASSERT_WR_MSR_FN(Ia32MonitorFilterLineSize);
5386 CPUM_ASSERT_WR_MSR_FN(Ia32MPerf);
5387 CPUM_ASSERT_WR_MSR_FN(Ia32APerf);
5388 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrPhysBaseN);
5389 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrPhysMaskN);
5390 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrFixed);
5391 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrDefType);
5392 CPUM_ASSERT_WR_MSR_FN(Ia32Pat);
5393 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterCs);
5394 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterEsp);
5395 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterEip);
5396 CPUM_ASSERT_WR_MSR_FN(Ia32McgStatus);
5397 CPUM_ASSERT_WR_MSR_FN(Ia32McgCtl);
5398 CPUM_ASSERT_WR_MSR_FN(Ia32DebugCtl);
5399 CPUM_ASSERT_WR_MSR_FN(Ia32SmrrPhysBase);
5400 CPUM_ASSERT_WR_MSR_FN(Ia32SmrrPhysMask);
5401 CPUM_ASSERT_WR_MSR_FN(Ia32PlatformDcaCap);
5402 CPUM_ASSERT_WR_MSR_FN(Ia32Dca0Cap);
5403 CPUM_ASSERT_WR_MSR_FN(Ia32PerfEvtSelN);
5404 CPUM_ASSERT_WR_MSR_FN(Ia32PerfStatus);
5405 CPUM_ASSERT_WR_MSR_FN(Ia32PerfCtl);
5406 CPUM_ASSERT_WR_MSR_FN(Ia32FixedCtrN);
5407 CPUM_ASSERT_WR_MSR_FN(Ia32PerfCapabilities);
5408 CPUM_ASSERT_WR_MSR_FN(Ia32FixedCtrCtrl);
5409 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalStatus);
5410 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalCtrl);
5411 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalOvfCtrl);
5412 CPUM_ASSERT_WR_MSR_FN(Ia32PebsEnable);
5413 CPUM_ASSERT_WR_MSR_FN(Ia32ClockModulation);
5414 CPUM_ASSERT_WR_MSR_FN(Ia32ThermInterrupt);
5415 CPUM_ASSERT_WR_MSR_FN(Ia32ThermStatus);
5416 CPUM_ASSERT_WR_MSR_FN(Ia32MiscEnable);
5417 CPUM_ASSERT_WR_MSR_FN(Ia32McCtlStatusAddrMiscN);
5418 CPUM_ASSERT_WR_MSR_FN(Ia32McNCtl2);
5419 CPUM_ASSERT_WR_MSR_FN(Ia32DsArea);
5420 CPUM_ASSERT_WR_MSR_FN(Ia32TscDeadline);
5421 CPUM_ASSERT_WR_MSR_FN(Ia32X2ApicN);
5422 CPUM_ASSERT_WR_MSR_FN(Ia32DebugInterface);
5423
5424 CPUM_ASSERT_WR_MSR_FN(Amd64Efer);
5425 CPUM_ASSERT_WR_MSR_FN(Amd64SyscallTarget);
5426 CPUM_ASSERT_WR_MSR_FN(Amd64LongSyscallTarget);
5427 CPUM_ASSERT_WR_MSR_FN(Amd64CompSyscallTarget);
5428 CPUM_ASSERT_WR_MSR_FN(Amd64SyscallFlagMask);
5429 CPUM_ASSERT_WR_MSR_FN(Amd64FsBase);
5430 CPUM_ASSERT_WR_MSR_FN(Amd64GsBase);
5431 CPUM_ASSERT_WR_MSR_FN(Amd64KernelGsBase);
5432 CPUM_ASSERT_WR_MSR_FN(Amd64TscAux);
5433
5434 CPUM_ASSERT_WR_MSR_FN(IntelEblCrPowerOn);
5435 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcHardPowerOn);
5436 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcSoftPowerOn);
5437 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcFrequencyId);
5438 CPUM_ASSERT_WR_MSR_FN(IntelFlexRatio);
5439 CPUM_ASSERT_WR_MSR_FN(IntelPkgCStConfigControl);
5440 CPUM_ASSERT_WR_MSR_FN(IntelPmgIoCaptureBase);
5441 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchFromToN);
5442 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchFromN);
5443 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchToN);
5444 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchTos);
5445 CPUM_ASSERT_WR_MSR_FN(IntelBblCrCtl);
5446 CPUM_ASSERT_WR_MSR_FN(IntelBblCrCtl3);
5447 CPUM_ASSERT_WR_MSR_FN(IntelI7TemperatureTarget);
5448 CPUM_ASSERT_WR_MSR_FN(IntelI7MsrOffCoreResponseN);
5449 CPUM_ASSERT_WR_MSR_FN(IntelI7MiscPwrMgmt);
5450 CPUM_ASSERT_WR_MSR_FN(IntelP6CrN);
5451 CPUM_ASSERT_WR_MSR_FN(IntelCpuId1FeatureMaskEcdx);
5452 CPUM_ASSERT_WR_MSR_FN(IntelCpuId1FeatureMaskEax);
5453 CPUM_ASSERT_WR_MSR_FN(IntelCpuId80000001FeatureMaskEcdx);
5454 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyAesNiCtl);
5455 CPUM_ASSERT_WR_MSR_FN(IntelI7TurboRatioLimit);
5456 CPUM_ASSERT_WR_MSR_FN(IntelI7LbrSelect);
5457 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyErrorControl);
5458 CPUM_ASSERT_WR_MSR_FN(IntelI7PowerCtl);
5459 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPebsNumAlt);
5460 CPUM_ASSERT_WR_MSR_FN(IntelI7PebsLdLat);
5461 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyVrCurrentConfig);
5462 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyVrMiscConfig);
5463 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPkgCnIrtlN);
5464 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPkgPowerLimit);
5465 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplDramPowerLimit);
5466 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp0PowerLimit);
5467 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp0Policy);
5468 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp1PowerLimit);
5469 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp1Policy);
5470 CPUM_ASSERT_WR_MSR_FN(IntelI7IvyConfigTdpControl);
5471 CPUM_ASSERT_WR_MSR_FN(IntelI7IvyTurboActivationRatio);
5472 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalCtrl);
5473 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalStatus);
5474 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalOvfCtrl);
5475 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfFixedCtrCtrl);
5476 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfFixedCtr);
5477 CPUM_ASSERT_WR_MSR_FN(IntelI7UncArbPerfCtrN);
5478 CPUM_ASSERT_WR_MSR_FN(IntelI7UncArbPerfEvtSelN);
5479 CPUM_ASSERT_WR_MSR_FN(IntelCore2EmttmCrTablesN);
5480 CPUM_ASSERT_WR_MSR_FN(IntelCore2SmmCStMiscInfo);
5481 CPUM_ASSERT_WR_MSR_FN(IntelCore1ExtConfig);
5482 CPUM_ASSERT_WR_MSR_FN(IntelCore1DtsCalControl);
5483 CPUM_ASSERT_WR_MSR_FN(IntelCore2PeciControl);
5484
5485 CPUM_ASSERT_WR_MSR_FN(P6LastIntFromIp);
5486 CPUM_ASSERT_WR_MSR_FN(P6LastIntToIp);
5487
5488 CPUM_ASSERT_WR_MSR_FN(AmdFam15hTscRate);
5489 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLwpCfg);
5490 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLwpCbAddr);
5491 CPUM_ASSERT_WR_MSR_FN(AmdFam10hMc4MiscN);
5492 CPUM_ASSERT_WR_MSR_FN(AmdK8PerfCtlN);
5493 CPUM_ASSERT_WR_MSR_FN(AmdK8PerfCtrN);
5494 CPUM_ASSERT_WR_MSR_FN(AmdK8SysCfg);
5495 CPUM_ASSERT_WR_MSR_FN(AmdK8HwCr);
5496 CPUM_ASSERT_WR_MSR_FN(AmdK8IorrBaseN);
5497 CPUM_ASSERT_WR_MSR_FN(AmdK8IorrMaskN);
5498 CPUM_ASSERT_WR_MSR_FN(AmdK8TopOfMemN);
5499 CPUM_ASSERT_WR_MSR_FN(AmdK8NbCfg1);
5500 CPUM_ASSERT_WR_MSR_FN(AmdK8McXcptRedir);
5501 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuNameN);
5502 CPUM_ASSERT_WR_MSR_FN(AmdK8HwThermalCtrl);
5503 CPUM_ASSERT_WR_MSR_FN(AmdK8SwThermalCtrl);
5504 CPUM_ASSERT_WR_MSR_FN(AmdK8FidVidControl);
5505 CPUM_ASSERT_WR_MSR_FN(AmdK8McCtlMaskN);
5506 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiOnIoTrapN);
5507 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiOnIoTrapCtlSts);
5508 CPUM_ASSERT_WR_MSR_FN(AmdK8IntPendingMessage);
5509 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiTriggerIoCycle);
5510 CPUM_ASSERT_WR_MSR_FN(AmdFam10hMmioCfgBaseAddr);
5511 CPUM_ASSERT_WR_MSR_FN(AmdFam10hTrapCtlMaybe);
5512 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateControl);
5513 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateStatus);
5514 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateN);
5515 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCofVidControl);
5516 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCofVidStatus);
5517 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCStateIoBaseAddr);
5518 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCpuWatchdogTimer);
5519 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmBase);
5520 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmAddr);
5521 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmMask);
5522 CPUM_ASSERT_WR_MSR_FN(AmdK8VmCr);
5523 CPUM_ASSERT_WR_MSR_FN(AmdK8IgnNe);
5524 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmCtl);
5525 CPUM_ASSERT_WR_MSR_FN(AmdK8VmHSavePa);
5526 CPUM_ASSERT_WR_MSR_FN(AmdFam10hVmLockKey);
5527 CPUM_ASSERT_WR_MSR_FN(AmdFam10hSmmLockKey);
5528 CPUM_ASSERT_WR_MSR_FN(AmdFam10hLocalSmiStatus);
5529 CPUM_ASSERT_WR_MSR_FN(AmdFam10hOsVisWrkIdLength);
5530 CPUM_ASSERT_WR_MSR_FN(AmdFam10hOsVisWrkStatus);
5531 CPUM_ASSERT_WR_MSR_FN(AmdFam16hL2IPerfCtlN);
5532 CPUM_ASSERT_WR_MSR_FN(AmdFam16hL2IPerfCtrN);
5533 CPUM_ASSERT_WR_MSR_FN(AmdFam15hNorthbridgePerfCtlN);
5534 CPUM_ASSERT_WR_MSR_FN(AmdFam15hNorthbridgePerfCtrN);
5535 CPUM_ASSERT_WR_MSR_FN(AmdK7MicrocodeCtl);
5536 CPUM_ASSERT_WR_MSR_FN(AmdK7ClusterIdMaybe);
5537 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd07hEbax);
5538 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd06hEcx);
5539 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd01hEdcx);
5540 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlExt01hEdcx);
5541 CPUM_ASSERT_WR_MSR_FN(AmdK8PatchLoader);
5542 CPUM_ASSERT_WR_MSR_FN(AmdK7DebugStatusMaybe);
5543 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTraceBaseMaybe);
5544 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTracePtrMaybe);
5545 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTraceLimitMaybe);
5546 CPUM_ASSERT_WR_MSR_FN(AmdK7HardwareDebugToolCfgMaybe);
5547 CPUM_ASSERT_WR_MSR_FN(AmdK7FastFlushCountMaybe);
5548 CPUM_ASSERT_WR_MSR_FN(AmdK7NodeId);
5549 CPUM_ASSERT_WR_MSR_FN(AmdK7DrXAddrMaskN);
5550 CPUM_ASSERT_WR_MSR_FN(AmdK7Dr0DataMatchMaybe);
5551 CPUM_ASSERT_WR_MSR_FN(AmdK7Dr0DataMaskMaybe);
5552 CPUM_ASSERT_WR_MSR_FN(AmdK7LoadStoreCfg);
5553 CPUM_ASSERT_WR_MSR_FN(AmdK7InstrCacheCfg);
5554 CPUM_ASSERT_WR_MSR_FN(AmdK7DataCacheCfg);
5555 CPUM_ASSERT_WR_MSR_FN(AmdK7BusUnitCfg);
5556 CPUM_ASSERT_WR_MSR_FN(AmdK7DebugCtl2Maybe);
5557 CPUM_ASSERT_WR_MSR_FN(AmdFam15hFpuCfg);
5558 CPUM_ASSERT_WR_MSR_FN(AmdFam15hDecoderCfg);
5559 CPUM_ASSERT_WR_MSR_FN(AmdFam10hBusUnitCfg2);
5560 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg);
5561 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg2);
5562 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg3);
5563 CPUM_ASSERT_WR_MSR_FN(AmdFam15hExecUnitCfg);
5564 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLoadStoreCfg2);
5565 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchCtl);
5566 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchLinAddr);
5567 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchPhysAddr);
5568 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpExecCtl);
5569 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpRip);
5570 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData);
5571 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData2);
5572 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData3);
5573 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsDcLinAddr);
5574 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsDcPhysAddr);
5575 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsCtl);
5576 CPUM_ASSERT_WR_MSR_FN(AmdFam14hIbsBrTarget);
5577
5578 CPUM_ASSERT_WR_MSR_FN(Gim);
5579
5580 return VINF_SUCCESS;
5581}
5582#endif /* VBOX_STRICT && IN_RING3 */
5583
5584
5585/**
5586 * Gets the scalable bus frequency.
5587 *
5588 * The bus frequency is used as a base in several MSRs that gives the CPU and
5589 * other frequency ratios.
5590 *
5591 * @returns Scalable bus frequency in Hz. Will not return CPUM_SBUSFREQ_UNKNOWN.
5592 * @param pVM Pointer to the shared VM structure.
5593 */
5594VMMDECL(uint64_t) CPUMGetGuestScalableBusFrequency(PVM pVM)
5595{
5596 uint64_t uFreq = pVM->cpum.s.GuestInfo.uScalableBusFreq;
5597 if (uFreq == CPUM_SBUSFREQ_UNKNOWN)
5598 uFreq = CPUM_SBUSFREQ_100MHZ;
5599 return uFreq;
5600}
5601
5602
5603#ifdef IN_RING0
5604
5605/**
5606 * Fast way for HM to access the MSR_K8_TSC_AUX register.
5607 *
5608 * @returns The register value.
5609 * @param pVCpu Pointer to the cross context CPU structure for
5610 * the calling EMT.
5611 * @thread EMT(pVCpu)
5612 */
5613VMMR0_INT_DECL(uint64_t) CPUMR0GetGuestTscAux(PVMCPU pVCpu)
5614{
5615 return pVCpu->cpum.s.GuestMsrs.msr.TscAux;
5616}
5617
5618
5619/**
5620 * Fast way for HM to access the MSR_K8_TSC_AUX register.
5621 *
5622 * @param pVCpu Pointer to the cross context CPU structure for
5623 * the calling EMT.
5624 * @param uValue The new value.
5625 * @thread EMT(pVCpu)
5626 */
5627VMMR0_INT_DECL(void) CPUMR0SetGuestTscAux(PVMCPU pVCpu, uint64_t uValue)
5628{
5629 pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
5630}
5631
5632#endif /* IN_RING0 */
5633
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