VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllMsrs.cpp@ 57952

Last change on this file since 57952 was 57558, checked in by vboxsync, 9 years ago

VMM: unused vars.
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File size: 189.8 KB
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1/* $Id: CPUMAllMsrs.cpp 57558 2015-08-27 12:40:38Z vboxsync $ */
2/** @file
3 * CPUM - CPU MSR Registers.
4 */
5
6/*
7 * Copyright (C) 2013-2015 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_CPUM
23#include <VBox/vmm/cpum.h>
24#include <VBox/vmm/pdmapi.h>
25#include <VBox/vmm/hm.h>
26#include <VBox/vmm/tm.h>
27#include <VBox/vmm/gim.h>
28#include "CPUMInternal.h"
29#include <VBox/vmm/vm.h>
30#include <VBox/err.h>
31
32
33/*********************************************************************************************************************************
34* Defined Constants And Macros *
35*********************************************************************************************************************************/
36/**
37 * Validates the CPUMMSRRANGE::offCpumCpu value and declares a local variable
38 * pointing to it.
39 *
40 * ASSUMES sizeof(a_Type) is a power of two and that the member is aligned
41 * correctly.
42 */
43#define CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(a_pVCpu, a_pRange, a_Type, a_VarName) \
44 AssertMsgReturn( (a_pRange)->offCpumCpu >= 8 \
45 && (a_pRange)->offCpumCpu < sizeof(CPUMCPU) \
46 && !((a_pRange)->offCpumCpu & (RT_MIN(sizeof(a_Type), 8) - 1)) \
47 , ("offCpumCpu=%#x %s\n", (a_pRange)->offCpumCpu, (a_pRange)->szName), \
48 VERR_CPUM_MSR_BAD_CPUMCPU_OFFSET); \
49 a_Type *a_VarName = (a_Type *)((uintptr_t)&(a_pVCpu)->cpum.s + (a_pRange)->offCpumCpu)
50
51
52/*********************************************************************************************************************************
53* Structures and Typedefs *
54*********************************************************************************************************************************/
55
56/**
57 * Implements reading one or more MSRs.
58 *
59 * @returns VBox status code.
60 * @retval VINF_SUCCESS on success.
61 * @retval VINF_CPUM_R3_MSR_READ if the MSR read could not be serviced in the
62 * current context (raw-mode or ring-0).
63 * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR).
64 *
65 * @param pVCpu Pointer to the VMCPU.
66 * @param idMsr The MSR we're reading.
67 * @param pRange The MSR range descriptor.
68 * @param puValue Where to return the value.
69 */
70typedef DECLCALLBACK(VBOXSTRICTRC) FNCPUMRDMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue);
71/** Pointer to a RDMSR worker for a specific MSR or range of MSRs. */
72typedef FNCPUMRDMSR *PFNCPUMRDMSR;
73
74
75/**
76 * Implements writing one or more MSRs.
77 *
78 * @retval VINF_SUCCESS on success.
79 * @retval VINF_CPUM_R3_MSR_WRITE if the MSR write could not be serviced in the
80 * current context (raw-mode or ring-0).
81 * @retval VERR_CPUM_RAISE_GP_0 on failure.
82 *
83 * @param pVCpu Pointer to the VMCPU.
84 * @param idMsr The MSR we're writing.
85 * @param pRange The MSR range descriptor.
86 * @param uValue The value to set, ignored bits masked.
87 * @param uRawValue The raw value with the ignored bits not masked.
88 */
89typedef DECLCALLBACK(VBOXSTRICTRC) FNCPUMWRMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue);
90/** Pointer to a WRMSR worker for a specific MSR or range of MSRs. */
91typedef FNCPUMWRMSR *PFNCPUMWRMSR;
92
93
94
95/*
96 * Generic functions.
97 * Generic functions.
98 * Generic functions.
99 */
100
101
102/** @callback_method_impl{FNCPUMRDMSR} */
103static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_FixedValue(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
104{
105 *puValue = pRange->uValue;
106 return VINF_SUCCESS;
107}
108
109
110/** @callback_method_impl{FNCPUMWRMSR} */
111static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IgnoreWrite(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
112{
113 Log(("CPUM: Ignoring WRMSR %#x (%s), %#llx\n", idMsr, pRange->szName, uValue));
114 return VINF_SUCCESS;
115}
116
117
118/** @callback_method_impl{FNCPUMRDMSR} */
119static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_WriteOnly(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
120{
121 return VERR_CPUM_RAISE_GP_0;
122}
123
124
125/** @callback_method_impl{FNCPUMWRMSR} */
126static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_ReadOnly(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
127{
128 Assert(pRange->fWrGpMask == UINT64_MAX);
129 return VERR_CPUM_RAISE_GP_0;
130}
131
132
133
134
135/*
136 * IA32
137 * IA32
138 * IA32
139 */
140
141/** @callback_method_impl{FNCPUMRDMSR} */
142static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32P5McAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
143{
144 *puValue = 0; /** @todo implement machine check injection. */
145 return VINF_SUCCESS;
146}
147
148
149/** @callback_method_impl{FNCPUMWRMSR} */
150static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32P5McAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
151{
152 /** @todo implement machine check injection. */
153 return VINF_SUCCESS;
154}
155
156
157/** @callback_method_impl{FNCPUMRDMSR} */
158static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32P5McType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
159{
160 *puValue = 0; /** @todo implement machine check injection. */
161 return VINF_SUCCESS;
162}
163
164
165/** @callback_method_impl{FNCPUMWRMSR} */
166static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32P5McType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
167{
168 /** @todo implement machine check injection. */
169 return VINF_SUCCESS;
170}
171
172
173/** @callback_method_impl{FNCPUMRDMSR} */
174static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32TimestampCounter(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
175{
176 *puValue = TMCpuTickGet(pVCpu);
177 return VINF_SUCCESS;
178}
179
180
181/** @callback_method_impl{FNCPUMWRMSR} */
182static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32TimestampCounter(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
183{
184 TMCpuTickSet(pVCpu->CTX_SUFF(pVM), pVCpu, uValue);
185 return VINF_SUCCESS;
186}
187
188
189/** @callback_method_impl{FNCPUMRDMSR} */
190static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PlatformId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
191{
192 uint64_t uValue = pRange->uValue;
193 if (uValue & 0x1f00)
194 {
195 /* Max allowed bus ratio present. */
196 /** @todo Implement scaled BUS frequency. */
197 }
198
199 *puValue = uValue;
200 return VINF_SUCCESS;
201}
202
203
204/** @callback_method_impl{FNCPUMRDMSR} */
205static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ApicBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
206{
207#if 0 /** @todo Sort this one out properly. Evidence from ticks 12240 and 12875 suggest the apic base is still readable even
208 * after the apic has been diabled. That makes common sense too. What we need to do here, though, is check whether
209 * there is an APIC device associated with the VM, and GP if there isn't. But that's for later. */
210 PVM pVM = pVCpu->CTX_SUFF(pVM);
211 if ( !pVM->cpum.s.GuestFeatures.fApic
212 && !pVM->cpum.s.GuestFeatures.fX2Apic)
213 {
214 Log(("CPUM: %s, apic not present -> GP\n", pRange->szName));
215 return VERR_CPUM_RAISE_GP_0;
216 }
217#endif
218
219 *puValue = pVCpu->cpum.s.Guest.msrApicBase;
220 return VINF_SUCCESS;
221}
222
223
224/** @callback_method_impl{FNCPUMWRMSR} */
225static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ApicBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
226{
227 int rc = PDMApicSetBase(pVCpu, uValue);
228 if (rc != VINF_SUCCESS)
229 rc = VERR_CPUM_RAISE_GP_0;
230 return VINF_SUCCESS;
231}
232
233
234/** @callback_method_impl{FNCPUMRDMSR} */
235static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32FeatureControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
236{
237 *puValue = 1; /* Locked, no VT-X, no SYSENTER micromanagement. */
238 return VINF_SUCCESS;
239}
240
241
242/** @callback_method_impl{FNCPUMWRMSR} */
243static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32FeatureControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
244{
245 return VERR_CPUM_RAISE_GP_0;
246}
247
248
249/** @callback_method_impl{FNCPUMRDMSR} */
250static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32BiosSignId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
251{
252 /** @todo fake microcode update. */
253 *puValue = pRange->uValue;
254 return VINF_SUCCESS;
255}
256
257
258/** @callback_method_impl{FNCPUMWRMSR} */
259static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32BiosSignId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
260{
261 /* Normally, zero is written to Ia32BiosSignId before reading it in order
262 to select the signature instead of the BBL_CR_D3 behaviour. The GP mask
263 of the database entry should take care of most illegal writes for now, so
264 just ignore all writes atm. */
265 return VINF_SUCCESS;
266}
267
268
269/** @callback_method_impl{FNCPUMWRMSR} */
270static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32BiosUpdateTrigger(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
271{
272 /** @todo Fake bios update trigger better. The value is the address to an
273 * update package, I think. We should probably GP if it's invalid. */
274 return VINF_SUCCESS;
275}
276
277
278/** @callback_method_impl{FNCPUMRDMSR} */
279static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SmmMonitorCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
280{
281 /** @todo SMM. */
282 *puValue = 0;
283 return VINF_SUCCESS;
284}
285
286
287/** @callback_method_impl{FNCPUMWRMSR} */
288static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SmmMonitorCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
289{
290 /** @todo SMM. */
291 return VINF_SUCCESS;
292}
293
294
295/** @callback_method_impl{FNCPUMRDMSR} */
296static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PmcN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
297{
298 /** @todo check CPUID leaf 0ah. */
299 *puValue = 0;
300 return VINF_SUCCESS;
301}
302
303
304/** @callback_method_impl{FNCPUMWRMSR} */
305static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PmcN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
306{
307 /** @todo check CPUID leaf 0ah. */
308 return VINF_SUCCESS;
309}
310
311
312/** @callback_method_impl{FNCPUMRDMSR} */
313static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MonitorFilterLineSize(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
314{
315 /** @todo return 0x1000 if we try emulate mwait 100% correctly. */
316 *puValue = 0x40; /** @todo Change to CPU cache line size. */
317 return VINF_SUCCESS;
318}
319
320
321/** @callback_method_impl{FNCPUMWRMSR} */
322static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MonitorFilterLineSize(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
323{
324 /** @todo should remember writes, though it's supposedly something only a BIOS
325 * would write so, it's not extremely important. */
326 return VINF_SUCCESS;
327}
328
329/** @callback_method_impl{FNCPUMRDMSR} */
330static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MPerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
331{
332 /** @todo Read MPERF: Adjust against previously written MPERF value. Is TSC
333 * what we want? */
334 *puValue = TMCpuTickGet(pVCpu);
335 return VINF_SUCCESS;
336}
337
338
339/** @callback_method_impl{FNCPUMWRMSR} */
340static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MPerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
341{
342 /** @todo Write MPERF: Calc adjustment. */
343 return VINF_SUCCESS;
344}
345
346
347/** @callback_method_impl{FNCPUMRDMSR} */
348static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32APerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
349{
350 /** @todo Read APERF: Adjust against previously written MPERF value. Is TSC
351 * what we want? */
352 *puValue = TMCpuTickGet(pVCpu);
353 return VINF_SUCCESS;
354}
355
356
357/** @callback_method_impl{FNCPUMWRMSR} */
358static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32APerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
359{
360 /** @todo Write APERF: Calc adjustment. */
361 return VINF_SUCCESS;
362}
363
364
365/** @callback_method_impl{FNCPUMWRMSR} */
366static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
367{
368 /* This is currently a bit weird. :-) */
369 uint8_t const cVariableRangeRegs = 0;
370 bool const fSystemManagementRangeRegisters = false;
371 bool const fFixedRangeRegisters = false;
372 bool const fWriteCombiningType = false;
373 *puValue = cVariableRangeRegs
374 | (fFixedRangeRegisters ? RT_BIT_64(8) : 0)
375 | (fWriteCombiningType ? RT_BIT_64(10) : 0)
376 | (fSystemManagementRangeRegisters ? RT_BIT_64(11) : 0);
377 return VINF_SUCCESS;
378}
379
380
381/** @callback_method_impl{FNCPUMRDMSR} */
382static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrPhysBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
383{
384 /** @todo Implement variable MTRR storage. */
385 Assert(pRange->uValue == (idMsr - 0x200) / 2);
386 *puValue = 0;
387 return VINF_SUCCESS;
388}
389
390
391/** @callback_method_impl{FNCPUMWRMSR} */
392static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrPhysBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
393{
394 /*
395 * Validate the value.
396 */
397 Assert(pRange->uValue == (idMsr - 0x200) / 2);
398
399 if ((uValue & 0xff) >= 7)
400 {
401 Log(("CPUM: Invalid type set writing MTRR PhysBase MSR %#x: %#llx (%#llx)\n", idMsr, uValue, uValue & 0xff));
402 return VERR_CPUM_RAISE_GP_0;
403 }
404
405 uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
406 if (fInvPhysMask & uValue)
407 {
408 Log(("CPUM: Invalid physical address bits set writing MTRR PhysBase MSR %#x: %#llx (%#llx)\n",
409 idMsr, uValue, uValue & fInvPhysMask));
410 return VERR_CPUM_RAISE_GP_0;
411 }
412
413 /*
414 * Store it.
415 */
416 /** @todo Implement variable MTRR storage. */
417 return VINF_SUCCESS;
418}
419
420
421/** @callback_method_impl{FNCPUMRDMSR} */
422static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrPhysMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
423{
424 /** @todo Implement variable MTRR storage. */
425 Assert(pRange->uValue == (idMsr - 0x200) / 2);
426 *puValue = 0;
427 return VINF_SUCCESS;
428}
429
430
431/** @callback_method_impl{FNCPUMWRMSR} */
432static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrPhysMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
433{
434 /*
435 * Validate the value.
436 */
437 Assert(pRange->uValue == (idMsr - 0x200) / 2);
438
439 uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
440 if (fInvPhysMask & uValue)
441 {
442 Log(("CPUM: Invalid physical address bits set writing MTRR PhysMask MSR %#x: %#llx (%#llx)\n",
443 idMsr, uValue, uValue & fInvPhysMask));
444 return VERR_CPUM_RAISE_GP_0;
445 }
446
447 /*
448 * Store it.
449 */
450 /** @todo Implement variable MTRR storage. */
451 return VINF_SUCCESS;
452}
453
454
455/** @callback_method_impl{FNCPUMRDMSR} */
456static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrFixed(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
457{
458 CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(pVCpu, pRange, uint64_t, puFixedMtrr);
459 *puValue = *puFixedMtrr;
460 return VINF_SUCCESS;
461}
462
463
464/** @callback_method_impl{FNCPUMWRMSR} */
465static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrFixed(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
466{
467 CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(pVCpu, pRange, uint64_t, puFixedMtrr);
468 for (uint32_t cShift = 0; cShift < 63; cShift += 8)
469 {
470 uint8_t uType = (uint8_t)(uValue >> cShift);
471 if (uType >= 7)
472 {
473 Log(("CPUM: Invalid MTRR type at %u:%u in fixed range (%#x/%s): %#llx (%#llx)\n",
474 cShift + 7, cShift, idMsr, pRange->szName, uValue, uType));
475 return VERR_CPUM_RAISE_GP_0;
476 }
477 }
478 *puFixedMtrr = uValue;
479 return VINF_SUCCESS;
480}
481
482
483/** @callback_method_impl{FNCPUMRDMSR} */
484static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrDefType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
485{
486 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType;
487 return VINF_SUCCESS;
488}
489
490
491/** @callback_method_impl{FNCPUMWRMSR} */
492static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrDefType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
493{
494 if ((uValue & 0xff) >= 7)
495 {
496 Log(("CPUM: Invalid MTRR default type value on %s: %#llx (%#llx)\n", pRange->szName, uValue, uValue & 0xff));
497 return VERR_CPUM_RAISE_GP_0;
498 }
499
500 pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType = uValue;
501 return VINF_SUCCESS;
502}
503
504
505/** @callback_method_impl{FNCPUMRDMSR} */
506static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32Pat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
507{
508 *puValue = pVCpu->cpum.s.Guest.msrPAT;
509 return VINF_SUCCESS;
510}
511
512
513/** @callback_method_impl{FNCPUMWRMSR} */
514static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32Pat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
515{
516 pVCpu->cpum.s.Guest.msrPAT = uValue;
517 return VINF_SUCCESS;
518}
519
520
521/** @callback_method_impl{FNCPUMRDMSR} */
522static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SysEnterCs(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
523{
524 *puValue = pVCpu->cpum.s.Guest.SysEnter.cs;
525 return VINF_SUCCESS;
526}
527
528
529/** @callback_method_impl{FNCPUMWRMSR} */
530static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SysEnterCs(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
531{
532 /* Note! We used to mask this by 0xffff, but turns out real HW doesn't and
533 there are generally 32-bit working bits backing this register. */
534 pVCpu->cpum.s.Guest.SysEnter.cs = uValue;
535 return VINF_SUCCESS;
536}
537
538
539/** @callback_method_impl{FNCPUMRDMSR} */
540static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SysEnterEsp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
541{
542 *puValue = pVCpu->cpum.s.Guest.SysEnter.esp;
543 return VINF_SUCCESS;
544}
545
546
547/** @callback_method_impl{FNCPUMWRMSR} */
548static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SysEnterEsp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
549{
550 if (X86_IS_CANONICAL(uValue))
551 {
552 pVCpu->cpum.s.Guest.SysEnter.esp = uValue;
553 return VINF_SUCCESS;
554 }
555 Log(("CPUM: IA32_SYSENTER_ESP not canonical! %#llx\n", uValue));
556 return VERR_CPUM_RAISE_GP_0;
557}
558
559
560/** @callback_method_impl{FNCPUMRDMSR} */
561static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SysEnterEip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
562{
563 *puValue = pVCpu->cpum.s.Guest.SysEnter.eip;
564 return VINF_SUCCESS;
565}
566
567
568/** @callback_method_impl{FNCPUMWRMSR} */
569static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SysEnterEip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
570{
571 if (X86_IS_CANONICAL(uValue))
572 {
573 pVCpu->cpum.s.Guest.SysEnter.eip = uValue;
574 return VINF_SUCCESS;
575 }
576#ifdef IN_RING3
577 LogRel(("CPUM: IA32_SYSENTER_EIP not canonical! %#llx\n", uValue));
578#else
579 Log(("CPUM: IA32_SYSENTER_EIP not canonical! %#llx\n", uValue));
580#endif
581 return VERR_CPUM_RAISE_GP_0;
582}
583
584
585/** @callback_method_impl{FNCPUMRDMSR} */
586static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McgCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
587{
588#if 0 /** @todo implement machine checks. */
589 *puValue = pRange->uValue & (RT_BIT_64(8) | 0);
590#else
591 *puValue = 0;
592#endif
593 return VINF_SUCCESS;
594}
595
596
597/** @callback_method_impl{FNCPUMRDMSR} */
598static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McgStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
599{
600 /** @todo implement machine checks. */
601 *puValue = 0;
602 return VINF_SUCCESS;
603}
604
605
606/** @callback_method_impl{FNCPUMWRMSR} */
607static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McgStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
608{
609 /** @todo implement machine checks. */
610 return VINF_SUCCESS;
611}
612
613
614/** @callback_method_impl{FNCPUMRDMSR} */
615static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McgCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
616{
617 /** @todo implement machine checks. */
618 *puValue = 0;
619 return VINF_SUCCESS;
620}
621
622
623/** @callback_method_impl{FNCPUMWRMSR} */
624static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McgCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
625{
626 /** @todo implement machine checks. */
627 return VINF_SUCCESS;
628}
629
630
631/** @callback_method_impl{FNCPUMRDMSR} */
632static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32DebugCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
633{
634 /** @todo implement IA32_DEBUGCTL. */
635 *puValue = 0;
636 return VINF_SUCCESS;
637}
638
639
640/** @callback_method_impl{FNCPUMWRMSR} */
641static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32DebugCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
642{
643 /** @todo implement IA32_DEBUGCTL. */
644 return VINF_SUCCESS;
645}
646
647
648/** @callback_method_impl{FNCPUMRDMSR} */
649static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SmrrPhysBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
650{
651 /** @todo implement intel SMM. */
652 *puValue = 0;
653 return VINF_SUCCESS;
654}
655
656
657/** @callback_method_impl{FNCPUMWRMSR} */
658static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SmrrPhysBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
659{
660 /** @todo implement intel SMM. */
661 return VERR_CPUM_RAISE_GP_0;
662}
663
664
665/** @callback_method_impl{FNCPUMRDMSR} */
666static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SmrrPhysMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
667{
668 /** @todo implement intel SMM. */
669 *puValue = 0;
670 return VINF_SUCCESS;
671}
672
673
674/** @callback_method_impl{FNCPUMWRMSR} */
675static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SmrrPhysMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
676{
677 /** @todo implement intel SMM. */
678 return VERR_CPUM_RAISE_GP_0;
679}
680
681
682/** @callback_method_impl{FNCPUMRDMSR} */
683static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PlatformDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
684{
685 /** @todo implement intel direct cache access (DCA)?? */
686 *puValue = 0;
687 return VINF_SUCCESS;
688}
689
690
691/** @callback_method_impl{FNCPUMWRMSR} */
692static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PlatformDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
693{
694 /** @todo implement intel direct cache access (DCA)?? */
695 return VINF_SUCCESS;
696}
697
698
699/** @callback_method_impl{FNCPUMRDMSR} */
700static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32CpuDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
701{
702 /** @todo implement intel direct cache access (DCA)?? */
703 *puValue = 0;
704 return VINF_SUCCESS;
705}
706
707
708/** @callback_method_impl{FNCPUMRDMSR} */
709static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32Dca0Cap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
710{
711 /** @todo implement intel direct cache access (DCA)?? */
712 *puValue = 0;
713 return VINF_SUCCESS;
714}
715
716
717/** @callback_method_impl{FNCPUMWRMSR} */
718static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32Dca0Cap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
719{
720 /** @todo implement intel direct cache access (DCA)?? */
721 return VINF_SUCCESS;
722}
723
724
725/** @callback_method_impl{FNCPUMRDMSR} */
726static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
727{
728 /** @todo implement IA32_PERFEVTSEL0+. */
729 *puValue = 0;
730 return VINF_SUCCESS;
731}
732
733
734/** @callback_method_impl{FNCPUMWRMSR} */
735static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
736{
737 /** @todo implement IA32_PERFEVTSEL0+. */
738 return VINF_SUCCESS;
739}
740
741
742/** @callback_method_impl{FNCPUMRDMSR} */
743static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
744{
745 uint64_t uValue = pRange->uValue;
746
747 /* Always provide the max bus ratio for now. XNU expects it. */
748 uValue &= ~((UINT64_C(0x1f) << 40) | RT_BIT_64(46));
749
750 PVM pVM = pVCpu->CTX_SUFF(pVM);
751 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
752 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
753 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
754 if (uTscRatio > 0x1f)
755 uTscRatio = 0x1f;
756 uValue |= (uint64_t)uTscRatio << 40;
757
758 *puValue = uValue;
759 return VINF_SUCCESS;
760}
761
762
763/** @callback_method_impl{FNCPUMWRMSR} */
764static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
765{
766 /* Pentium4 allows writing, but all bits are ignored. */
767 return VINF_SUCCESS;
768}
769
770
771/** @callback_method_impl{FNCPUMRDMSR} */
772static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
773{
774 /** @todo implement IA32_PERFCTL. */
775 *puValue = 0;
776 return VINF_SUCCESS;
777}
778
779
780/** @callback_method_impl{FNCPUMWRMSR} */
781static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
782{
783 /** @todo implement IA32_PERFCTL. */
784 return VINF_SUCCESS;
785}
786
787
788/** @callback_method_impl{FNCPUMRDMSR} */
789static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32FixedCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
790{
791 /** @todo implement IA32_FIXED_CTRn (fixed performance counters). */
792 *puValue = 0;
793 return VINF_SUCCESS;
794}
795
796
797/** @callback_method_impl{FNCPUMWRMSR} */
798static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32FixedCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
799{
800 /** @todo implement IA32_FIXED_CTRn (fixed performance counters). */
801 return VINF_SUCCESS;
802}
803
804
805/** @callback_method_impl{FNCPUMRDMSR} */
806static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfCapabilities(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
807{
808 /** @todo implement performance counters. */
809 *puValue = 0;
810 return VINF_SUCCESS;
811}
812
813
814/** @callback_method_impl{FNCPUMWRMSR} */
815static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfCapabilities(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
816{
817 /** @todo implement performance counters. */
818 return VINF_SUCCESS;
819}
820
821
822/** @callback_method_impl{FNCPUMRDMSR} */
823static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32FixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
824{
825 /** @todo implement performance counters. */
826 *puValue = 0;
827 return VINF_SUCCESS;
828}
829
830
831/** @callback_method_impl{FNCPUMWRMSR} */
832static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32FixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
833{
834 /** @todo implement performance counters. */
835 return VINF_SUCCESS;
836}
837
838
839/** @callback_method_impl{FNCPUMRDMSR} */
840static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
841{
842 /** @todo implement performance counters. */
843 *puValue = 0;
844 return VINF_SUCCESS;
845}
846
847
848/** @callback_method_impl{FNCPUMWRMSR} */
849static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
850{
851 /** @todo implement performance counters. */
852 return VINF_SUCCESS;
853}
854
855
856/** @callback_method_impl{FNCPUMRDMSR} */
857static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
858{
859 /** @todo implement performance counters. */
860 *puValue = 0;
861 return VINF_SUCCESS;
862}
863
864
865/** @callback_method_impl{FNCPUMWRMSR} */
866static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
867{
868 /** @todo implement performance counters. */
869 return VINF_SUCCESS;
870}
871
872
873/** @callback_method_impl{FNCPUMRDMSR} */
874static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
875{
876 /** @todo implement performance counters. */
877 *puValue = 0;
878 return VINF_SUCCESS;
879}
880
881
882/** @callback_method_impl{FNCPUMWRMSR} */
883static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
884{
885 /** @todo implement performance counters. */
886 return VINF_SUCCESS;
887}
888
889
890/** @callback_method_impl{FNCPUMRDMSR} */
891static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PebsEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
892{
893 /** @todo implement performance counters. */
894 *puValue = 0;
895 return VINF_SUCCESS;
896}
897
898
899/** @callback_method_impl{FNCPUMWRMSR} */
900static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PebsEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
901{
902 /** @todo implement performance counters. */
903 return VINF_SUCCESS;
904}
905
906
907/** @callback_method_impl{FNCPUMRDMSR} */
908static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ClockModulation(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
909{
910 /** @todo implement IA32_CLOCK_MODULATION. */
911 *puValue = 0;
912 return VINF_SUCCESS;
913}
914
915
916/** @callback_method_impl{FNCPUMWRMSR} */
917static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ClockModulation(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
918{
919 /** @todo implement IA32_CLOCK_MODULATION. */
920 return VINF_SUCCESS;
921}
922
923
924/** @callback_method_impl{FNCPUMRDMSR} */
925static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ThermInterrupt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
926{
927 /** @todo implement IA32_THERM_INTERRUPT. */
928 *puValue = 0;
929 return VINF_SUCCESS;
930}
931
932
933/** @callback_method_impl{FNCPUMWRMSR} */
934static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ThermInterrupt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
935{
936 /** @todo implement IA32_THERM_STATUS. */
937 return VINF_SUCCESS;
938}
939
940
941/** @callback_method_impl{FNCPUMRDMSR} */
942static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ThermStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
943{
944 /** @todo implement IA32_THERM_STATUS. */
945 *puValue = 0;
946 return VINF_SUCCESS;
947}
948
949
950/** @callback_method_impl{FNCPUMWRMSR} */
951static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ThermStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
952{
953 /** @todo implement IA32_THERM_INTERRUPT. */
954 return VINF_SUCCESS;
955}
956
957
958/** @callback_method_impl{FNCPUMRDMSR} */
959static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32Therm2Ctl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
960{
961 /** @todo implement IA32_THERM2_CTL. */
962 *puValue = 0;
963 return VINF_SUCCESS;
964}
965
966
967/** @callback_method_impl{FNCPUMWRMSR} */
968static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32Therm2Ctl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
969{
970 /** @todo implement IA32_THERM2_CTL. */
971 return VINF_SUCCESS;
972}
973
974
975/** @callback_method_impl{FNCPUMRDMSR} */
976static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MiscEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
977{
978 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
979 return VINF_SUCCESS;
980}
981
982
983/** @callback_method_impl{FNCPUMWRMSR} */
984static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MiscEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
985{
986#ifdef LOG_ENABLED
987 uint64_t const uOld = pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
988#endif
989
990 /* Unsupported bits are generally ignored and stripped by the MSR range
991 entry that got us here. So, we just need to preserve fixed bits. */
992 pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = uValue
993 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
994 | MSR_IA32_MISC_ENABLE_BTS_UNAVAIL;
995
996 Log(("CPUM: IA32_MISC_ENABLE; old=%#llx written=%#llx => %#llx\n",
997 uOld, uValue, pVCpu->cpum.s.GuestMsrs.msr.MiscEnable));
998
999 /** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
1000 /** @todo Wire up MSR_IA32_MISC_ENABLE_XD_DISABLE. */
1001 return VINF_SUCCESS;
1002}
1003
1004
1005/** @callback_method_impl{FNCPUMRDMSR} */
1006static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McCtlStatusAddrMiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1007{
1008 /** @todo Implement machine check exception injection. */
1009 switch (idMsr & 3)
1010 {
1011 case 0:
1012 case 1:
1013 *puValue = 0;
1014 break;
1015
1016 /* The ADDR and MISC registers aren't accessible since the
1017 corresponding STATUS bits are zero. */
1018 case 2:
1019 Log(("CPUM: Reading IA32_MCi_ADDR %#x -> #GP\n", idMsr));
1020 return VERR_CPUM_RAISE_GP_0;
1021 case 3:
1022 Log(("CPUM: Reading IA32_MCi_MISC %#x -> #GP\n", idMsr));
1023 return VERR_CPUM_RAISE_GP_0;
1024 }
1025 return VINF_SUCCESS;
1026}
1027
1028
1029/** @callback_method_impl{FNCPUMWRMSR} */
1030static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McCtlStatusAddrMiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1031{
1032 switch (idMsr & 3)
1033 {
1034 case 0:
1035 /* Ignore writes to the CTL register. */
1036 break;
1037
1038 case 1:
1039 /* According to specs, the STATUS register can only be written to
1040 with the value 0. VBoxCpuReport thinks different for a
1041 Pentium M Dothan, but implementing according to specs now. */
1042 if (uValue != 0)
1043 {
1044 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_STATUS %#x -> #GP\n", uValue, idMsr));
1045 return VERR_CPUM_RAISE_GP_0;
1046 }
1047 break;
1048
1049 /* Specs states that ADDR and MISC can be cleared by writing zeros.
1050 Writing 1s will GP. Need to figure out how this relates to the
1051 ADDRV and MISCV status flags. If writing is independent of those
1052 bits, we need to know whether the CPU really implements them since
1053 that is exposed by writing 0 to them.
1054 Implementing the solution with the fewer GPs for now. */
1055 case 2:
1056 if (uValue != 0)
1057 {
1058 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_ADDR %#x -> #GP\n", uValue, idMsr));
1059 return VERR_CPUM_RAISE_GP_0;
1060 }
1061 break;
1062 case 3:
1063 if (uValue != 0)
1064 {
1065 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_MISC %#x -> #GP\n", uValue, idMsr));
1066 return VERR_CPUM_RAISE_GP_0;
1067 }
1068 break;
1069 }
1070 return VINF_SUCCESS;
1071}
1072
1073
1074/** @callback_method_impl{FNCPUMRDMSR} */
1075static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McNCtl2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1076{
1077 /** @todo Implement machine check exception injection. */
1078 *puValue = 0;
1079 return VINF_SUCCESS;
1080}
1081
1082
1083/** @callback_method_impl{FNCPUMWRMSR} */
1084static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McNCtl2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1085{
1086 /** @todo Implement machine check exception injection. */
1087 return VINF_SUCCESS;
1088}
1089
1090
1091/** @callback_method_impl{FNCPUMRDMSR} */
1092static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32DsArea(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1093{
1094 /** @todo implement IA32_DS_AREA. */
1095 *puValue = 0;
1096 return VINF_SUCCESS;
1097}
1098
1099
1100/** @callback_method_impl{FNCPUMWRMSR} */
1101static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32DsArea(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1102{
1103 return VINF_SUCCESS;
1104}
1105
1106
1107/** @callback_method_impl{FNCPUMRDMSR} */
1108static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32TscDeadline(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1109{
1110 /** @todo implement TSC deadline timer. */
1111 *puValue = 0;
1112 return VINF_SUCCESS;
1113}
1114
1115
1116/** @callback_method_impl{FNCPUMWRMSR} */
1117static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32TscDeadline(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1118{
1119 /** @todo implement TSC deadline timer. */
1120 return VINF_SUCCESS;
1121}
1122
1123
1124/** @callback_method_impl{FNCPUMRDMSR} */
1125static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32X2ApicN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1126{
1127 int rc = PDMApicReadMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, puValue);
1128 if (rc != VINF_SUCCESS)
1129 {
1130 Log(("CPUM: X2APIC %#x read => %Rrc => #GP\n", idMsr, rc));
1131 return VERR_CPUM_RAISE_GP_0;
1132 }
1133 return VINF_SUCCESS;
1134}
1135
1136
1137/** @callback_method_impl{FNCPUMWRMSR} */
1138static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32X2ApicN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1139{
1140 int rc = PDMApicWriteMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, uValue);
1141 if (rc != VINF_SUCCESS)
1142 {
1143 Log(("CPUM: X2APIC %#x write %#llx => %Rrc => #GP\n", idMsr, rc, uValue));
1144 return VERR_CPUM_RAISE_GP_0;
1145 }
1146 return VINF_SUCCESS;
1147}
1148
1149
1150/** @callback_method_impl{FNCPUMRDMSR} */
1151static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32DebugInterface(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1152{
1153 /** @todo IA32_DEBUG_INTERFACE (no docs) */
1154 *puValue = 0;
1155 return VINF_SUCCESS;
1156}
1157
1158
1159/** @callback_method_impl{FNCPUMWRMSR} */
1160static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32DebugInterface(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1161{
1162 /** @todo IA32_DEBUG_INTERFACE (no docs) */
1163 return VINF_SUCCESS;
1164}
1165
1166
1167/** @callback_method_impl{FNCPUMRDMSR} */
1168static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1169{
1170 *puValue = 0;
1171 return VINF_SUCCESS;
1172}
1173
1174
1175/** @callback_method_impl{FNCPUMRDMSR} */
1176static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxPinbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1177{
1178 *puValue = 0;
1179 return VINF_SUCCESS;
1180}
1181
1182
1183/** @callback_method_impl{FNCPUMRDMSR} */
1184static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxProcbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1185{
1186 *puValue = 0;
1187 return VINF_SUCCESS;
1188}
1189
1190
1191/** @callback_method_impl{FNCPUMRDMSR} */
1192static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxExitCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1193{
1194 *puValue = 0;
1195 return VINF_SUCCESS;
1196}
1197
1198
1199/** @callback_method_impl{FNCPUMRDMSR} */
1200static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxEntryCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1201{
1202 *puValue = 0;
1203 return VINF_SUCCESS;
1204}
1205
1206
1207/** @callback_method_impl{FNCPUMRDMSR} */
1208static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxMisc(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1209{
1210 *puValue = 0;
1211 return VINF_SUCCESS;
1212}
1213
1214
1215/** @callback_method_impl{FNCPUMRDMSR} */
1216static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr0Fixed0(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1217{
1218 *puValue = 0;
1219 return VINF_SUCCESS;
1220}
1221
1222
1223/** @callback_method_impl{FNCPUMRDMSR} */
1224static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr0Fixed1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1225{
1226 *puValue = 0;
1227 return VINF_SUCCESS;
1228}
1229
1230
1231/** @callback_method_impl{FNCPUMRDMSR} */
1232static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr4Fixed0(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1233{
1234 *puValue = 0;
1235 return VINF_SUCCESS;
1236}
1237
1238
1239/** @callback_method_impl{FNCPUMRDMSR} */
1240static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr4Fixed1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1241{
1242 *puValue = 0;
1243 return VINF_SUCCESS;
1244}
1245
1246
1247/** @callback_method_impl{FNCPUMRDMSR} */
1248static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxVmcsEnum(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1249{
1250 *puValue = 0;
1251 return VINF_SUCCESS;
1252}
1253
1254
1255/** @callback_method_impl{FNCPUMRDMSR} */
1256static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxProcBasedCtls2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1257{
1258 *puValue = 0;
1259 return VINF_SUCCESS;
1260}
1261
1262
1263/** @callback_method_impl{FNCPUMRDMSR} */
1264static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxEptVpidCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1265{
1266 *puValue = 0;
1267 return VINF_SUCCESS;
1268}
1269
1270
1271/** @callback_method_impl{FNCPUMRDMSR} */
1272static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTruePinbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1273{
1274 *puValue = 0;
1275 return VINF_SUCCESS;
1276}
1277
1278
1279/** @callback_method_impl{FNCPUMRDMSR} */
1280static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTrueProcbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1281{
1282 *puValue = 0;
1283 return VINF_SUCCESS;
1284}
1285
1286
1287/** @callback_method_impl{FNCPUMRDMSR} */
1288static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTrueExitCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1289{
1290 *puValue = 0;
1291 return VINF_SUCCESS;
1292}
1293
1294
1295/** @callback_method_impl{FNCPUMRDMSR} */
1296static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTrueEntryCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1297{
1298 *puValue = 0;
1299 return VINF_SUCCESS;
1300}
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311/*
1312 * AMD64
1313 * AMD64
1314 * AMD64
1315 */
1316
1317
1318/** @callback_method_impl{FNCPUMRDMSR} */
1319static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64Efer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1320{
1321 *puValue = pVCpu->cpum.s.Guest.msrEFER;
1322 return VINF_SUCCESS;
1323}
1324
1325
1326/** @callback_method_impl{FNCPUMWRMSR} */
1327static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64Efer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1328{
1329 PVM pVM = pVCpu->CTX_SUFF(pVM);
1330 uint64_t const uOldEfer = pVCpu->cpum.s.Guest.msrEFER;
1331 uint32_t const fExtFeatures = pVM->cpum.s.aGuestCpuIdPatmExt[0].uEax >= 0x80000001
1332 ? pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx
1333 : 0;
1334 uint64_t fMask = 0;
1335 uint64_t fIgnoreMask = MSR_K6_EFER_LMA;
1336
1337 /* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
1338 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_NX)
1339 fMask |= MSR_K6_EFER_NXE;
1340 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
1341 fMask |= MSR_K6_EFER_LME;
1342 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
1343 fMask |= MSR_K6_EFER_SCE;
1344 if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1345 fMask |= MSR_K6_EFER_FFXSR;
1346
1347 /* #GP(0) If anything outside the allowed bits is set. */
1348 if (uValue & ~(fIgnoreMask | fMask))
1349 {
1350 Log(("CPUM: Settings disallowed EFER bit. uValue=%#RX64 fAllowed=%#RX64 -> #GP(0)\n", uValue, fMask));
1351 return VERR_CPUM_RAISE_GP_0;
1352 }
1353
1354 /* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if
1355 paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1356 if ( (uOldEfer & MSR_K6_EFER_LME) != (uValue & fMask & MSR_K6_EFER_LME)
1357 && (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG))
1358 {
1359 Log(("CPUM: Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
1360 return VERR_CPUM_RAISE_GP_0;
1361 }
1362
1363 /* There are a few more: e.g. MSR_K6_EFER_LMSLE */
1364 AssertMsg(!(uValue & ~(MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA /* ignored anyway */ | MSR_K6_EFER_SCE | MSR_K6_EFER_FFXSR)),
1365 ("Unexpected value %RX64\n", uValue));
1366 pVCpu->cpum.s.Guest.msrEFER = (uOldEfer & ~fMask) | (uValue & fMask);
1367
1368 /* AMD64 Architecture Programmer's Manual: 15.15 TLB Control; flush the TLB
1369 if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
1370 if ( (uOldEfer & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA))
1371 != (pVCpu->cpum.s.Guest.msrEFER & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA)))
1372 {
1373 /// @todo PGMFlushTLB(pVCpu, cr3, true /*fGlobal*/);
1374 HMFlushTLB(pVCpu);
1375
1376 /* Notify PGM about NXE changes. */
1377 if ( (uOldEfer & MSR_K6_EFER_NXE)
1378 != (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE))
1379 PGMNotifyNxeChanged(pVCpu, !(uOldEfer & MSR_K6_EFER_NXE));
1380 }
1381 return VINF_SUCCESS;
1382}
1383
1384
1385/** @callback_method_impl{FNCPUMRDMSR} */
1386static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64SyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1387{
1388 *puValue = pVCpu->cpum.s.Guest.msrSTAR;
1389 return VINF_SUCCESS;
1390}
1391
1392
1393/** @callback_method_impl{FNCPUMWRMSR} */
1394static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64SyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1395{
1396 pVCpu->cpum.s.Guest.msrSTAR = uValue;
1397 return VINF_SUCCESS;
1398}
1399
1400
1401/** @callback_method_impl{FNCPUMRDMSR} */
1402static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64LongSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1403{
1404 *puValue = pVCpu->cpum.s.Guest.msrLSTAR;
1405 return VINF_SUCCESS;
1406}
1407
1408
1409/** @callback_method_impl{FNCPUMWRMSR} */
1410static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64LongSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1411{
1412 if (!X86_IS_CANONICAL(uValue))
1413 {
1414 Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
1415 return VERR_CPUM_RAISE_GP_0;
1416 }
1417 pVCpu->cpum.s.Guest.msrLSTAR = uValue;
1418 return VINF_SUCCESS;
1419}
1420
1421
1422/** @callback_method_impl{FNCPUMRDMSR} */
1423static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64CompSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1424{
1425 *puValue = pVCpu->cpum.s.Guest.msrCSTAR;
1426 return VINF_SUCCESS;
1427}
1428
1429
1430/** @callback_method_impl{FNCPUMWRMSR} */
1431static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64CompSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1432{
1433 if (!X86_IS_CANONICAL(uValue))
1434 {
1435 Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
1436 return VERR_CPUM_RAISE_GP_0;
1437 }
1438 pVCpu->cpum.s.Guest.msrCSTAR = uValue;
1439 return VINF_SUCCESS;
1440}
1441
1442
1443/** @callback_method_impl{FNCPUMRDMSR} */
1444static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64SyscallFlagMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1445{
1446 *puValue = pVCpu->cpum.s.Guest.msrSFMASK;
1447 return VINF_SUCCESS;
1448}
1449
1450
1451/** @callback_method_impl{FNCPUMWRMSR} */
1452static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64SyscallFlagMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1453{
1454 pVCpu->cpum.s.Guest.msrSFMASK = uValue;
1455 return VINF_SUCCESS;
1456}
1457
1458
1459/** @callback_method_impl{FNCPUMRDMSR} */
1460static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64FsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1461{
1462 *puValue = pVCpu->cpum.s.Guest.fs.u64Base;
1463 return VINF_SUCCESS;
1464}
1465
1466
1467/** @callback_method_impl{FNCPUMWRMSR} */
1468static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64FsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1469{
1470 pVCpu->cpum.s.Guest.fs.u64Base = uValue;
1471 return VINF_SUCCESS;
1472}
1473
1474
1475/** @callback_method_impl{FNCPUMRDMSR} */
1476static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64GsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1477{
1478 *puValue = pVCpu->cpum.s.Guest.gs.u64Base;
1479 return VINF_SUCCESS;
1480}
1481
1482/** @callback_method_impl{FNCPUMWRMSR} */
1483static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64GsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1484{
1485 pVCpu->cpum.s.Guest.gs.u64Base = uValue;
1486 return VINF_SUCCESS;
1487}
1488
1489
1490
1491/** @callback_method_impl{FNCPUMRDMSR} */
1492static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64KernelGsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1493{
1494 *puValue = pVCpu->cpum.s.Guest.msrKERNELGSBASE;
1495 return VINF_SUCCESS;
1496}
1497
1498/** @callback_method_impl{FNCPUMWRMSR} */
1499static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64KernelGsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1500{
1501 pVCpu->cpum.s.Guest.msrKERNELGSBASE = uValue;
1502 return VINF_SUCCESS;
1503}
1504
1505
1506/** @callback_method_impl{FNCPUMRDMSR} */
1507static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64TscAux(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1508{
1509 *puValue = pVCpu->cpum.s.GuestMsrs.msr.TscAux;
1510 return VINF_SUCCESS;
1511}
1512
1513/** @callback_method_impl{FNCPUMWRMSR} */
1514static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64TscAux(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1515{
1516 pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
1517 return VINF_SUCCESS;
1518}
1519
1520
1521/*
1522 * Intel specific
1523 * Intel specific
1524 * Intel specific
1525 */
1526
1527/** @callback_method_impl{FNCPUMRDMSR} */
1528static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelEblCrPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1529{
1530 /** @todo recalc clock frequency ratio? */
1531 *puValue = pRange->uValue;
1532 return VINF_SUCCESS;
1533}
1534
1535
1536/** @callback_method_impl{FNCPUMWRMSR} */
1537static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelEblCrPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1538{
1539 /** @todo Write EBL_CR_POWERON: Remember written bits. */
1540 return VINF_SUCCESS;
1541}
1542
1543
1544/** @callback_method_impl{FNCPUMRDMSR} */
1545static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7CoreThreadCount(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1546{
1547 /* Note! According to cpuid_set_info in XNU (10.7.0), Westmere CPU only
1548 have a 4-bit core count. */
1549 uint16_t cCores = pVCpu->CTX_SUFF(pVM)->cCpus;
1550 uint16_t cThreads = cCores; /** @todo hyper-threading. */
1551 *puValue = RT_MAKE_U32(cThreads, cCores);
1552 return VINF_SUCCESS;
1553}
1554
1555
1556/** @callback_method_impl{FNCPUMRDMSR} */
1557static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP4EbcHardPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1558{
1559 /** @todo P4 hard power on config */
1560 *puValue = pRange->uValue;
1561 return VINF_SUCCESS;
1562}
1563
1564
1565/** @callback_method_impl{FNCPUMWRMSR} */
1566static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP4EbcHardPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1567{
1568 /** @todo P4 hard power on config */
1569 return VINF_SUCCESS;
1570}
1571
1572
1573/** @callback_method_impl{FNCPUMRDMSR} */
1574static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP4EbcSoftPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1575{
1576 /** @todo P4 soft power on config */
1577 *puValue = pRange->uValue;
1578 return VINF_SUCCESS;
1579}
1580
1581
1582/** @callback_method_impl{FNCPUMWRMSR} */
1583static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP4EbcSoftPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1584{
1585 /** @todo P4 soft power on config */
1586 return VINF_SUCCESS;
1587}
1588
1589
1590/** @callback_method_impl{FNCPUMRDMSR} */
1591static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP4EbcFrequencyId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1592{
1593 uint64_t uValue;
1594 PVM pVM = pVCpu->CTX_SUFF(pVM);
1595 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
1596 if (pVM->cpum.s.GuestFeatures.uModel >= 2)
1597 {
1598 if (uScalableBusHz <= CPUM_SBUSFREQ_100MHZ && pVM->cpum.s.GuestFeatures.uModel <= 2)
1599 {
1600 uScalableBusHz = CPUM_SBUSFREQ_100MHZ;
1601 uValue = 0;
1602 }
1603 else if (uScalableBusHz <= CPUM_SBUSFREQ_133MHZ)
1604 {
1605 uScalableBusHz = CPUM_SBUSFREQ_133MHZ;
1606 uValue = 1;
1607 }
1608 else if (uScalableBusHz <= CPUM_SBUSFREQ_167MHZ)
1609 {
1610 uScalableBusHz = CPUM_SBUSFREQ_167MHZ;
1611 uValue = 3;
1612 }
1613 else if (uScalableBusHz <= CPUM_SBUSFREQ_200MHZ)
1614 {
1615 uScalableBusHz = CPUM_SBUSFREQ_200MHZ;
1616 uValue = 2;
1617 }
1618 else if (uScalableBusHz <= CPUM_SBUSFREQ_267MHZ && pVM->cpum.s.GuestFeatures.uModel > 2)
1619 {
1620 uScalableBusHz = CPUM_SBUSFREQ_267MHZ;
1621 uValue = 0;
1622 }
1623 else
1624 {
1625 uScalableBusHz = CPUM_SBUSFREQ_333MHZ;
1626 uValue = 6;
1627 }
1628 uValue <<= 16;
1629
1630 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
1631 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
1632 uValue |= (uint32_t)uTscRatio << 24;
1633
1634 uValue |= pRange->uValue & ~UINT64_C(0xff0f0000);
1635 }
1636 else
1637 {
1638 /* Probably more stuff here, but intel doesn't want to tell us. */
1639 uValue = pRange->uValue;
1640 uValue &= ~(RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23)); /* 100 MHz is only documented value */
1641 }
1642
1643 *puValue = uValue;
1644 return VINF_SUCCESS;
1645}
1646
1647
1648/** @callback_method_impl{FNCPUMWRMSR} */
1649static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP4EbcFrequencyId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1650{
1651 /** @todo P4 bus frequency config */
1652 return VINF_SUCCESS;
1653}
1654
1655
1656/** @callback_method_impl{FNCPUMRDMSR} */
1657static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP6FsbFrequency(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1658{
1659 /* Convert the scalable bus frequency to the encoding in the intel manual (for core+). */
1660 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVCpu->CTX_SUFF(pVM));
1661 if (uScalableBusHz <= CPUM_SBUSFREQ_100MHZ)
1662 *puValue = 5;
1663 else if (uScalableBusHz <= CPUM_SBUSFREQ_133MHZ)
1664 *puValue = 1;
1665 else if (uScalableBusHz <= CPUM_SBUSFREQ_167MHZ)
1666 *puValue = 3;
1667 else if (uScalableBusHz <= CPUM_SBUSFREQ_200MHZ)
1668 *puValue = 2;
1669 else if (uScalableBusHz <= CPUM_SBUSFREQ_267MHZ)
1670 *puValue = 0;
1671 else if (uScalableBusHz <= CPUM_SBUSFREQ_333MHZ)
1672 *puValue = 4;
1673 else /*if (uScalableBusHz <= CPUM_SBUSFREQ_400MHZ)*/
1674 *puValue = 6;
1675
1676 *puValue |= pRange->uValue & ~UINT64_C(0x7);
1677
1678 return VINF_SUCCESS;
1679}
1680
1681
1682/** @callback_method_impl{FNCPUMRDMSR} */
1683static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelPlatformInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1684{
1685 /* Just indicate a fixed TSC, no turbo boost, no programmable anything. */
1686 PVM pVM = pVCpu->CTX_SUFF(pVM);
1687 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
1688 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
1689 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
1690 uint64_t uValue = ((uint32_t)uTscRatio << 8) /* TSC invariant frequency. */
1691 | ((uint64_t)uTscRatio << 40); /* The max turbo frequency. */
1692
1693 /* Ivy bridge has a minimum operating ratio as well. */
1694 if (true) /** @todo detect sandy bridge. */
1695 uValue |= (uint64_t)uTscRatio << 48;
1696
1697 *puValue = uValue;
1698 return VINF_SUCCESS;
1699}
1700
1701
1702/** @callback_method_impl{FNCPUMRDMSR} */
1703static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelFlexRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1704{
1705 uint64_t uValue = pRange->uValue & ~UINT64_C(0x1ff00);
1706
1707 PVM pVM = pVCpu->CTX_SUFF(pVM);
1708 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
1709 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
1710 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
1711 uValue |= (uint32_t)uTscRatio << 8;
1712
1713 *puValue = uValue;
1714 return VINF_SUCCESS;
1715}
1716
1717
1718/** @callback_method_impl{FNCPUMWRMSR} */
1719static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelFlexRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1720{
1721 /** @todo implement writing MSR_FLEX_RATIO. */
1722 return VINF_SUCCESS;
1723}
1724
1725
1726/** @callback_method_impl{FNCPUMRDMSR} */
1727static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelPkgCStConfigControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1728{
1729 *puValue = pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl;
1730 return VINF_SUCCESS;
1731}
1732
1733
1734/** @callback_method_impl{FNCPUMWRMSR} */
1735static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelPkgCStConfigControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1736{
1737 if (pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl & RT_BIT_64(15))
1738 {
1739 Log(("CPUM: WRMDR %#x (%s), %#llx: Write protected -> #GP\n", idMsr, pRange->szName, uValue));
1740 return VERR_CPUM_RAISE_GP_0;
1741 }
1742#if 0 /** @todo check what real (old) hardware does. */
1743 if ((uValue & 7) >= 5)
1744 {
1745 Log(("CPUM: WRMDR %#x (%s), %#llx: Invalid limit (%d) -> #GP\n", idMsr, pRange->szName, uValue, (uint32_t)(uValue & 7)));
1746 return VERR_CPUM_RAISE_GP_0;
1747 }
1748#endif
1749 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = uValue;
1750 return VINF_SUCCESS;
1751}
1752
1753
1754/** @callback_method_impl{FNCPUMRDMSR} */
1755static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelPmgIoCaptureBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1756{
1757 /** @todo implement I/O mwait wakeup. */
1758 *puValue = 0;
1759 return VINF_SUCCESS;
1760}
1761
1762
1763/** @callback_method_impl{FNCPUMWRMSR} */
1764static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelPmgIoCaptureBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1765{
1766 /** @todo implement I/O mwait wakeup. */
1767 return VINF_SUCCESS;
1768}
1769
1770
1771/** @callback_method_impl{FNCPUMRDMSR} */
1772static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchFromToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1773{
1774 /** @todo implement last branch records. */
1775 *puValue = 0;
1776 return VINF_SUCCESS;
1777}
1778
1779
1780/** @callback_method_impl{FNCPUMWRMSR} */
1781static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchFromToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1782{
1783 /** @todo implement last branch records. */
1784 return VINF_SUCCESS;
1785}
1786
1787
1788/** @callback_method_impl{FNCPUMRDMSR} */
1789static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchFromN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1790{
1791 /** @todo implement last branch records. */
1792 *puValue = 0;
1793 return VINF_SUCCESS;
1794}
1795
1796
1797/** @callback_method_impl{FNCPUMWRMSR} */
1798static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchFromN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1799{
1800 /** @todo implement last branch records. */
1801 /** @todo Probing indicates that bit 63 is settable on SandyBridge, at least
1802 * if the rest of the bits are zero. Automatic sign extending?
1803 * Investigate! */
1804 if (!X86_IS_CANONICAL(uValue))
1805 {
1806 Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
1807 return VERR_CPUM_RAISE_GP_0;
1808 }
1809 return VINF_SUCCESS;
1810}
1811
1812
1813/** @callback_method_impl{FNCPUMRDMSR} */
1814static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1815{
1816 /** @todo implement last branch records. */
1817 *puValue = 0;
1818 return VINF_SUCCESS;
1819}
1820
1821
1822/** @callback_method_impl{FNCPUMWRMSR} */
1823static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1824{
1825 /** @todo implement last branch records. */
1826 /** @todo Probing indicates that bit 63 is settable on SandyBridge, at least
1827 * if the rest of the bits are zero. Automatic sign extending?
1828 * Investigate! */
1829 if (!X86_IS_CANONICAL(uValue))
1830 {
1831 Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
1832 return VERR_CPUM_RAISE_GP_0;
1833 }
1834 return VINF_SUCCESS;
1835}
1836
1837
1838/** @callback_method_impl{FNCPUMRDMSR} */
1839static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchTos(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1840{
1841 /** @todo implement last branch records. */
1842 *puValue = 0;
1843 return VINF_SUCCESS;
1844}
1845
1846
1847/** @callback_method_impl{FNCPUMWRMSR} */
1848static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchTos(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1849{
1850 /** @todo implement last branch records. */
1851 return VINF_SUCCESS;
1852}
1853
1854
1855/** @callback_method_impl{FNCPUMRDMSR} */
1856static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelBblCrCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1857{
1858 *puValue = pRange->uValue;
1859 return VINF_SUCCESS;
1860}
1861
1862
1863/** @callback_method_impl{FNCPUMWRMSR} */
1864static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelBblCrCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1865{
1866 return VINF_SUCCESS;
1867}
1868
1869
1870/** @callback_method_impl{FNCPUMRDMSR} */
1871static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelBblCrCtl3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1872{
1873 *puValue = pRange->uValue;
1874 return VINF_SUCCESS;
1875}
1876
1877
1878/** @callback_method_impl{FNCPUMWRMSR} */
1879static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelBblCrCtl3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1880{
1881 return VINF_SUCCESS;
1882}
1883
1884
1885/** @callback_method_impl{FNCPUMRDMSR} */
1886static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7TemperatureTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1887{
1888 *puValue = pRange->uValue;
1889 return VINF_SUCCESS;
1890}
1891
1892
1893/** @callback_method_impl{FNCPUMWRMSR} */
1894static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7TemperatureTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1895{
1896 return VINF_SUCCESS;
1897}
1898
1899
1900/** @callback_method_impl{FNCPUMRDMSR} */
1901static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7MsrOffCoreResponseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1902{
1903 /** @todo machine check. */
1904 *puValue = pRange->uValue;
1905 return VINF_SUCCESS;
1906}
1907
1908
1909/** @callback_method_impl{FNCPUMWRMSR} */
1910static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7MsrOffCoreResponseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1911{
1912 /** @todo machine check. */
1913 return VINF_SUCCESS;
1914}
1915
1916
1917/** @callback_method_impl{FNCPUMRDMSR} */
1918static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7MiscPwrMgmt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1919{
1920 *puValue = 0;
1921 return VINF_SUCCESS;
1922}
1923
1924
1925/** @callback_method_impl{FNCPUMWRMSR} */
1926static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7MiscPwrMgmt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1927{
1928 return VINF_SUCCESS;
1929}
1930
1931
1932/** @callback_method_impl{FNCPUMRDMSR} */
1933static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP6CrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1934{
1935 int rc = CPUMGetGuestCRx(pVCpu, pRange->uValue, puValue);
1936 AssertRC(rc);
1937 return VINF_SUCCESS;
1938}
1939
1940
1941/** @callback_method_impl{FNCPUMWRMSR} */
1942static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP6CrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1943{
1944 /* This CRx interface differs from the MOV CRx, GReg interface in that
1945 #GP(0) isn't raised if unsupported bits are written to. Instead they
1946 are simply ignored and masked off. (Pentium M Dothan) */
1947 /** @todo Implement MSR_P6_CRx writing. Too much effort for very little, if
1948 * any, gain. */
1949 return VINF_SUCCESS;
1950}
1951
1952
1953/** @callback_method_impl{FNCPUMRDMSR} */
1954static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCpuId1FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1955{
1956 /** @todo implement CPUID masking. */
1957 *puValue = UINT64_MAX;
1958 return VINF_SUCCESS;
1959}
1960
1961
1962/** @callback_method_impl{FNCPUMWRMSR} */
1963static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCpuId1FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1964{
1965 /** @todo implement CPUID masking. */
1966 return VINF_SUCCESS;
1967}
1968
1969
1970/** @callback_method_impl{FNCPUMRDMSR} */
1971static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCpuId1FeatureMaskEax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1972{
1973 /** @todo implement CPUID masking. */
1974 return VINF_SUCCESS;
1975}
1976
1977
1978/** @callback_method_impl{FNCPUMWRMSR} */
1979static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCpuId1FeatureMaskEax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1980{
1981 /** @todo implement CPUID masking. */
1982 return VINF_SUCCESS;
1983}
1984
1985
1986
1987/** @callback_method_impl{FNCPUMRDMSR} */
1988static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCpuId80000001FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1989{
1990 /** @todo implement CPUID masking. */
1991 *puValue = UINT64_MAX;
1992 return VINF_SUCCESS;
1993}
1994
1995
1996/** @callback_method_impl{FNCPUMWRMSR} */
1997static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCpuId80000001FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1998{
1999 /** @todo implement CPUID masking. */
2000 return VINF_SUCCESS;
2001}
2002
2003
2004
2005/** @callback_method_impl{FNCPUMRDMSR} */
2006static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyAesNiCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2007{
2008 /** @todo implement AES-NI. */
2009 *puValue = 3; /* Bit 0 is lock bit, bit 1 disables AES-NI. That's what they say. */
2010 return VINF_SUCCESS;
2011}
2012
2013
2014/** @callback_method_impl{FNCPUMWRMSR} */
2015static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyAesNiCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2016{
2017 /** @todo implement AES-NI. */
2018 return VERR_CPUM_RAISE_GP_0;
2019}
2020
2021
2022/** @callback_method_impl{FNCPUMRDMSR} */
2023static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7TurboRatioLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2024{
2025 /** @todo implement intel C states. */
2026 *puValue = pRange->uValue;
2027 return VINF_SUCCESS;
2028}
2029
2030
2031/** @callback_method_impl{FNCPUMWRMSR} */
2032static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7TurboRatioLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2033{
2034 /** @todo implement intel C states. */
2035 return VINF_SUCCESS;
2036}
2037
2038
2039/** @callback_method_impl{FNCPUMRDMSR} */
2040static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7LbrSelect(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2041{
2042 /** @todo implement last-branch-records. */
2043 *puValue = 0;
2044 return VINF_SUCCESS;
2045}
2046
2047
2048/** @callback_method_impl{FNCPUMWRMSR} */
2049static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7LbrSelect(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2050{
2051 /** @todo implement last-branch-records. */
2052 return VINF_SUCCESS;
2053}
2054
2055
2056/** @callback_method_impl{FNCPUMRDMSR} */
2057static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyErrorControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2058{
2059 /** @todo implement memory error injection (MSR_ERROR_CONTROL). */
2060 *puValue = 0;
2061 return VINF_SUCCESS;
2062}
2063
2064
2065/** @callback_method_impl{FNCPUMWRMSR} */
2066static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyErrorControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2067{
2068 /** @todo implement memory error injection (MSR_ERROR_CONTROL). */
2069 return VINF_SUCCESS;
2070}
2071
2072
2073/** @callback_method_impl{FNCPUMRDMSR} */
2074static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7VirtualLegacyWireCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2075{
2076 /** @todo implement memory VLW? */
2077 *puValue = pRange->uValue;
2078 /* Note: A20M is known to be bit 1 as this was disclosed in spec update
2079 AAJ49/AAK51/????, which documents the inversion of this bit. The
2080 Sandy bridge CPU here has value 0x74, so it probably doesn't have a BIOS
2081 that correct things. Some guesses at the other bits:
2082 bit 2 = INTR
2083 bit 4 = SMI
2084 bit 5 = INIT
2085 bit 6 = NMI */
2086 return VINF_SUCCESS;
2087}
2088
2089
2090/** @callback_method_impl{FNCPUMRDMSR} */
2091static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7PowerCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2092{
2093 /** @todo intel power management */
2094 *puValue = 0;
2095 return VINF_SUCCESS;
2096}
2097
2098
2099/** @callback_method_impl{FNCPUMWRMSR} */
2100static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7PowerCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2101{
2102 /** @todo intel power management */
2103 return VINF_SUCCESS;
2104}
2105
2106
2107/** @callback_method_impl{FNCPUMRDMSR} */
2108static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyPebsNumAlt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2109{
2110 /** @todo intel performance counters. */
2111 *puValue = 0;
2112 return VINF_SUCCESS;
2113}
2114
2115
2116/** @callback_method_impl{FNCPUMWRMSR} */
2117static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyPebsNumAlt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2118{
2119 /** @todo intel performance counters. */
2120 return VINF_SUCCESS;
2121}
2122
2123
2124/** @callback_method_impl{FNCPUMRDMSR} */
2125static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7PebsLdLat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2126{
2127 /** @todo intel performance counters. */
2128 *puValue = 0;
2129 return VINF_SUCCESS;
2130}
2131
2132
2133/** @callback_method_impl{FNCPUMWRMSR} */
2134static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7PebsLdLat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2135{
2136 /** @todo intel performance counters. */
2137 return VINF_SUCCESS;
2138}
2139
2140
2141/** @callback_method_impl{FNCPUMRDMSR} */
2142static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7PkgCnResidencyN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2143{
2144 /** @todo intel power management. */
2145 *puValue = 0;
2146 return VINF_SUCCESS;
2147}
2148
2149
2150/** @callback_method_impl{FNCPUMRDMSR} */
2151static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7CoreCnResidencyN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2152{
2153 /** @todo intel power management. */
2154 *puValue = 0;
2155 return VINF_SUCCESS;
2156}
2157
2158
2159/** @callback_method_impl{FNCPUMRDMSR} */
2160static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyVrCurrentConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2161{
2162 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2163 *puValue = 0;
2164 return VINF_SUCCESS;
2165}
2166
2167
2168/** @callback_method_impl{FNCPUMWRMSR} */
2169static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyVrCurrentConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2170{
2171 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2172 return VINF_SUCCESS;
2173}
2174
2175
2176/** @callback_method_impl{FNCPUMRDMSR} */
2177static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyVrMiscConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2178{
2179 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2180 *puValue = 0;
2181 return VINF_SUCCESS;
2182}
2183
2184
2185/** @callback_method_impl{FNCPUMWRMSR} */
2186static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyVrMiscConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2187{
2188 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2189 return VINF_SUCCESS;
2190}
2191
2192
2193/** @callback_method_impl{FNCPUMRDMSR} */
2194static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyRaplPowerUnit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2195{
2196 /** @todo intel RAPL. */
2197 *puValue = pRange->uValue;
2198 return VINF_SUCCESS;
2199}
2200
2201
2202/** @callback_method_impl{FNCPUMRDMSR} */
2203static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyPkgCnIrtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2204{
2205 /** @todo intel power management. */
2206 *puValue = 0;
2207 return VINF_SUCCESS;
2208}
2209
2210
2211/** @callback_method_impl{FNCPUMWRMSR} */
2212static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyPkgCnIrtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2213{
2214 /** @todo intel power management. */
2215 return VINF_SUCCESS;
2216}
2217
2218
2219/** @callback_method_impl{FNCPUMRDMSR} */
2220static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyPkgC2Residency(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2221{
2222 /** @todo intel power management. */
2223 *puValue = 0;
2224 return VINF_SUCCESS;
2225}
2226
2227
2228/** @callback_method_impl{FNCPUMRDMSR} */
2229static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2230{
2231 /** @todo intel RAPL. */
2232 *puValue = 0;
2233 return VINF_SUCCESS;
2234}
2235
2236
2237/** @callback_method_impl{FNCPUMWRMSR} */
2238static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPkgPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2239{
2240 /** @todo intel RAPL. */
2241 return VINF_SUCCESS;
2242}
2243
2244
2245/** @callback_method_impl{FNCPUMRDMSR} */
2246static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgEnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2247{
2248 /** @todo intel power management. */
2249 *puValue = 0;
2250 return VINF_SUCCESS;
2251}
2252
2253
2254/** @callback_method_impl{FNCPUMRDMSR} */
2255static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgPerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2256{
2257 /** @todo intel power management. */
2258 *puValue = 0;
2259 return VINF_SUCCESS;
2260}
2261
2262
2263/** @callback_method_impl{FNCPUMRDMSR} */
2264static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgPowerInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2265{
2266 /** @todo intel power management. */
2267 *puValue = 0;
2268 return VINF_SUCCESS;
2269}
2270
2271
2272/** @callback_method_impl{FNCPUMRDMSR} */
2273static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2274{
2275 /** @todo intel RAPL. */
2276 *puValue = 0;
2277 return VINF_SUCCESS;
2278}
2279
2280
2281/** @callback_method_impl{FNCPUMWRMSR} */
2282static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplDramPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2283{
2284 /** @todo intel RAPL. */
2285 return VINF_SUCCESS;
2286}
2287
2288
2289/** @callback_method_impl{FNCPUMRDMSR} */
2290static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramEnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2291{
2292 /** @todo intel power management. */
2293 *puValue = 0;
2294 return VINF_SUCCESS;
2295}
2296
2297
2298/** @callback_method_impl{FNCPUMRDMSR} */
2299static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramPerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2300{
2301 /** @todo intel power management. */
2302 *puValue = 0;
2303 return VINF_SUCCESS;
2304}
2305
2306
2307/** @callback_method_impl{FNCPUMRDMSR} */
2308static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramPowerInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2309{
2310 /** @todo intel power management. */
2311 *puValue = 0;
2312 return VINF_SUCCESS;
2313}
2314
2315
2316/** @callback_method_impl{FNCPUMRDMSR} */
2317static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2318{
2319 /** @todo intel RAPL. */
2320 *puValue = 0;
2321 return VINF_SUCCESS;
2322}
2323
2324
2325/** @callback_method_impl{FNCPUMWRMSR} */
2326static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp0PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2327{
2328 /** @todo intel RAPL. */
2329 return VINF_SUCCESS;
2330}
2331
2332
2333/** @callback_method_impl{FNCPUMRDMSR} */
2334static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0EnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2335{
2336 /** @todo intel power management. */
2337 *puValue = 0;
2338 return VINF_SUCCESS;
2339}
2340
2341
2342/** @callback_method_impl{FNCPUMRDMSR} */
2343static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2344{
2345 /** @todo intel RAPL. */
2346 *puValue = 0;
2347 return VINF_SUCCESS;
2348}
2349
2350
2351/** @callback_method_impl{FNCPUMWRMSR} */
2352static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp0Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2353{
2354 /** @todo intel RAPL. */
2355 return VINF_SUCCESS;
2356}
2357
2358
2359/** @callback_method_impl{FNCPUMRDMSR} */
2360static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2361{
2362 /** @todo intel power management. */
2363 *puValue = 0;
2364 return VINF_SUCCESS;
2365}
2366
2367
2368/** @callback_method_impl{FNCPUMRDMSR} */
2369static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp1PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2370{
2371 /** @todo intel RAPL. */
2372 *puValue = 0;
2373 return VINF_SUCCESS;
2374}
2375
2376
2377/** @callback_method_impl{FNCPUMWRMSR} */
2378static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp1PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2379{
2380 /** @todo intel RAPL. */
2381 return VINF_SUCCESS;
2382}
2383
2384
2385/** @callback_method_impl{FNCPUMRDMSR} */
2386static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp1EnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2387{
2388 /** @todo intel power management. */
2389 *puValue = 0;
2390 return VINF_SUCCESS;
2391}
2392
2393
2394/** @callback_method_impl{FNCPUMRDMSR} */
2395static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp1Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2396{
2397 /** @todo intel RAPL. */
2398 *puValue = 0;
2399 return VINF_SUCCESS;
2400}
2401
2402
2403/** @callback_method_impl{FNCPUMWRMSR} */
2404static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp1Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2405{
2406 /** @todo intel RAPL. */
2407 return VINF_SUCCESS;
2408}
2409
2410
2411/** @callback_method_impl{FNCPUMRDMSR} */
2412static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpNominal(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2413{
2414 /** @todo intel power management. */
2415 *puValue = pRange->uValue;
2416 return VINF_SUCCESS;
2417}
2418
2419
2420/** @callback_method_impl{FNCPUMRDMSR} */
2421static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpLevel1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2422{
2423 /** @todo intel power management. */
2424 *puValue = pRange->uValue;
2425 return VINF_SUCCESS;
2426}
2427
2428
2429/** @callback_method_impl{FNCPUMRDMSR} */
2430static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpLevel2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2431{
2432 /** @todo intel power management. */
2433 *puValue = pRange->uValue;
2434 return VINF_SUCCESS;
2435}
2436
2437
2438/** @callback_method_impl{FNCPUMRDMSR} */
2439static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2440{
2441 /** @todo intel power management. */
2442 *puValue = 0;
2443 return VINF_SUCCESS;
2444}
2445
2446
2447/** @callback_method_impl{FNCPUMWRMSR} */
2448static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7IvyConfigTdpControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2449{
2450 /** @todo intel power management. */
2451 return VINF_SUCCESS;
2452}
2453
2454
2455/** @callback_method_impl{FNCPUMRDMSR} */
2456static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyTurboActivationRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2457{
2458 /** @todo intel power management. */
2459 *puValue = 0;
2460 return VINF_SUCCESS;
2461}
2462
2463
2464/** @callback_method_impl{FNCPUMWRMSR} */
2465static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7IvyTurboActivationRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2466{
2467 /** @todo intel power management. */
2468 return VINF_SUCCESS;
2469}
2470
2471
2472/** @callback_method_impl{FNCPUMRDMSR} */
2473static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2474{
2475 /** @todo uncore msrs. */
2476 *puValue = 0;
2477 return VINF_SUCCESS;
2478}
2479
2480
2481/** @callback_method_impl{FNCPUMWRMSR} */
2482static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2483{
2484 /** @todo uncore msrs. */
2485 return VINF_SUCCESS;
2486}
2487
2488
2489/** @callback_method_impl{FNCPUMRDMSR} */
2490static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2491{
2492 /** @todo uncore msrs. */
2493 *puValue = 0;
2494 return VINF_SUCCESS;
2495}
2496
2497
2498/** @callback_method_impl{FNCPUMWRMSR} */
2499static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2500{
2501 /** @todo uncore msrs. */
2502 return VINF_SUCCESS;
2503}
2504
2505
2506/** @callback_method_impl{FNCPUMRDMSR} */
2507static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2508{
2509 /** @todo uncore msrs. */
2510 *puValue = 0;
2511 return VINF_SUCCESS;
2512}
2513
2514
2515/** @callback_method_impl{FNCPUMWRMSR} */
2516static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2517{
2518 /** @todo uncore msrs. */
2519 return VINF_SUCCESS;
2520}
2521
2522
2523/** @callback_method_impl{FNCPUMRDMSR} */
2524static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfFixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2525{
2526 /** @todo uncore msrs. */
2527 *puValue = 0;
2528 return VINF_SUCCESS;
2529}
2530
2531
2532/** @callback_method_impl{FNCPUMWRMSR} */
2533static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfFixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2534{
2535 /** @todo uncore msrs. */
2536 return VINF_SUCCESS;
2537}
2538
2539
2540/** @callback_method_impl{FNCPUMRDMSR} */
2541static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfFixedCtr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2542{
2543 /** @todo uncore msrs. */
2544 *puValue = 0;
2545 return VINF_SUCCESS;
2546}
2547
2548
2549/** @callback_method_impl{FNCPUMWRMSR} */
2550static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfFixedCtr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2551{
2552 /** @todo uncore msrs. */
2553 return VINF_SUCCESS;
2554}
2555
2556
2557/** @callback_method_impl{FNCPUMRDMSR} */
2558static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncCBoxConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2559{
2560 /** @todo uncore msrs. */
2561 *puValue = 0;
2562 return VINF_SUCCESS;
2563}
2564
2565
2566/** @callback_method_impl{FNCPUMRDMSR} */
2567static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncArbPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2568{
2569 /** @todo uncore msrs. */
2570 *puValue = 0;
2571 return VINF_SUCCESS;
2572}
2573
2574
2575/** @callback_method_impl{FNCPUMWRMSR} */
2576static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncArbPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2577{
2578 /** @todo uncore msrs. */
2579 return VINF_SUCCESS;
2580}
2581
2582
2583/** @callback_method_impl{FNCPUMRDMSR} */
2584static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncArbPerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2585{
2586 /** @todo uncore msrs. */
2587 *puValue = 0;
2588 return VINF_SUCCESS;
2589}
2590
2591
2592/** @callback_method_impl{FNCPUMWRMSR} */
2593static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncArbPerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2594{
2595 /** @todo uncore msrs. */
2596 return VINF_SUCCESS;
2597}
2598
2599
2600/** @callback_method_impl{FNCPUMRDMSR} */
2601static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore2EmttmCrTablesN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2602{
2603 /** @todo implement enhanced multi thread termal monitoring? */
2604 *puValue = pRange->uValue;
2605 return VINF_SUCCESS;
2606}
2607
2608
2609/** @callback_method_impl{FNCPUMWRMSR} */
2610static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore2EmttmCrTablesN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2611{
2612 /** @todo implement enhanced multi thread termal monitoring? */
2613 return VINF_SUCCESS;
2614}
2615
2616
2617/** @callback_method_impl{FNCPUMRDMSR} */
2618static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore2SmmCStMiscInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2619{
2620 /** @todo SMM & C-states? */
2621 *puValue = 0;
2622 return VINF_SUCCESS;
2623}
2624
2625
2626/** @callback_method_impl{FNCPUMWRMSR} */
2627static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore2SmmCStMiscInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2628{
2629 /** @todo SMM & C-states? */
2630 return VINF_SUCCESS;
2631}
2632
2633
2634/** @callback_method_impl{FNCPUMRDMSR} */
2635static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore1ExtConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2636{
2637 /** @todo Core1&2 EXT_CONFIG (whatever that is)? */
2638 *puValue = 0;
2639 return VINF_SUCCESS;
2640}
2641
2642
2643/** @callback_method_impl{FNCPUMWRMSR} */
2644static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore1ExtConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2645{
2646 /** @todo Core1&2 EXT_CONFIG (whatever that is)? */
2647 return VINF_SUCCESS;
2648}
2649
2650
2651/** @callback_method_impl{FNCPUMRDMSR} */
2652static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore1DtsCalControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2653{
2654 /** @todo Core1&2(?) DTS_CAL_CTRL (whatever that is)? */
2655 *puValue = 0;
2656 return VINF_SUCCESS;
2657}
2658
2659
2660/** @callback_method_impl{FNCPUMWRMSR} */
2661static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore1DtsCalControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2662{
2663 /** @todo Core1&2(?) DTS_CAL_CTRL (whatever that is)? */
2664 return VINF_SUCCESS;
2665}
2666
2667
2668/** @callback_method_impl{FNCPUMRDMSR} */
2669static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore2PeciControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2670{
2671 /** @todo Core2+ platform environment control interface control register? */
2672 *puValue = 0;
2673 return VINF_SUCCESS;
2674}
2675
2676
2677/** @callback_method_impl{FNCPUMWRMSR} */
2678static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore2PeciControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2679{
2680 /** @todo Core2+ platform environment control interface control register? */
2681 return VINF_SUCCESS;
2682}
2683
2684
2685
2686/*
2687 * Multiple vendor P6 MSRs.
2688 * Multiple vendor P6 MSRs.
2689 * Multiple vendor P6 MSRs.
2690 *
2691 * These MSRs were introduced with the P6 but not elevated to architectural
2692 * MSRs, despite other vendors implementing them.
2693 */
2694
2695
2696/** @callback_method_impl{FNCPUMRDMSR} */
2697static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastBranchFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2698{
2699 /* AMD seems to just record RIP, while intel claims to record RIP+CS.BASE
2700 if I read the docs correctly, thus the need for separate functions. */
2701 /** @todo implement last branch records. */
2702 *puValue = 0;
2703 return VINF_SUCCESS;
2704}
2705
2706
2707/** @callback_method_impl{FNCPUMRDMSR} */
2708static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastBranchToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2709{
2710 /** @todo implement last branch records. */
2711 *puValue = 0;
2712 return VINF_SUCCESS;
2713}
2714
2715
2716/** @callback_method_impl{FNCPUMRDMSR} */
2717static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastIntFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2718{
2719 /** @todo implement last exception records. */
2720 *puValue = 0;
2721 return VINF_SUCCESS;
2722}
2723
2724
2725/** @callback_method_impl{FNCPUMWRMSR} */
2726static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_P6LastIntFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2727{
2728 /** @todo implement last exception records. */
2729 /* Note! On many CPUs, the high bit of the 0x000001dd register is always writable, even when the result is
2730 a non-cannonical address. */
2731 return VINF_SUCCESS;
2732}
2733
2734
2735/** @callback_method_impl{FNCPUMRDMSR} */
2736static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastIntToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2737{
2738 /** @todo implement last exception records. */
2739 *puValue = 0;
2740 return VINF_SUCCESS;
2741}
2742
2743
2744/** @callback_method_impl{FNCPUMWRMSR} */
2745static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_P6LastIntToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2746{
2747 /** @todo implement last exception records. */
2748 return VINF_SUCCESS;
2749}
2750
2751
2752
2753/*
2754 * AMD specific
2755 * AMD specific
2756 * AMD specific
2757 */
2758
2759
2760/** @callback_method_impl{FNCPUMRDMSR} */
2761static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hTscRate(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2762{
2763 /** @todo Implement TscRateMsr */
2764 *puValue = RT_MAKE_U64(0, 1); /* 1.0 = reset value. */
2765 return VINF_SUCCESS;
2766}
2767
2768
2769/** @callback_method_impl{FNCPUMWRMSR} */
2770static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hTscRate(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2771{
2772 /** @todo Implement TscRateMsr */
2773 return VINF_SUCCESS;
2774}
2775
2776
2777/** @callback_method_impl{FNCPUMRDMSR} */
2778static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hLwpCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2779{
2780 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2781 /* Note: Only listes in BKDG for Family 15H. */
2782 *puValue = 0;
2783 return VINF_SUCCESS;
2784}
2785
2786
2787/** @callback_method_impl{FNCPUMWRMSR} */
2788static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hLwpCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2789{
2790 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2791 return VINF_SUCCESS;
2792}
2793
2794
2795/** @callback_method_impl{FNCPUMRDMSR} */
2796static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hLwpCbAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2797{
2798 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2799 /* Note: Only listes in BKDG for Family 15H. */
2800 *puValue = 0;
2801 return VINF_SUCCESS;
2802}
2803
2804
2805/** @callback_method_impl{FNCPUMWRMSR} */
2806static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hLwpCbAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2807{
2808 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2809 return VINF_SUCCESS;
2810}
2811
2812
2813/** @callback_method_impl{FNCPUMRDMSR} */
2814static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hMc4MiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2815{
2816 /** @todo machine check. */
2817 *puValue = 0;
2818 return VINF_SUCCESS;
2819}
2820
2821
2822/** @callback_method_impl{FNCPUMWRMSR} */
2823static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hMc4MiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2824{
2825 /** @todo machine check. */
2826 return VINF_SUCCESS;
2827}
2828
2829
2830/** @callback_method_impl{FNCPUMRDMSR} */
2831static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8PerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2832{
2833 /** @todo AMD performance events. */
2834 *puValue = 0;
2835 return VINF_SUCCESS;
2836}
2837
2838
2839/** @callback_method_impl{FNCPUMWRMSR} */
2840static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8PerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2841{
2842 /** @todo AMD performance events. */
2843 return VINF_SUCCESS;
2844}
2845
2846
2847/** @callback_method_impl{FNCPUMRDMSR} */
2848static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8PerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2849{
2850 /** @todo AMD performance events. */
2851 *puValue = 0;
2852 return VINF_SUCCESS;
2853}
2854
2855
2856/** @callback_method_impl{FNCPUMWRMSR} */
2857static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8PerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2858{
2859 /** @todo AMD performance events. */
2860 return VINF_SUCCESS;
2861}
2862
2863
2864/** @callback_method_impl{FNCPUMRDMSR} */
2865static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SysCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2866{
2867 /** @todo AMD SYS_CFG */
2868 *puValue = pRange->uValue;
2869 return VINF_SUCCESS;
2870}
2871
2872
2873/** @callback_method_impl{FNCPUMWRMSR} */
2874static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SysCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2875{
2876 /** @todo AMD SYS_CFG */
2877 return VINF_SUCCESS;
2878}
2879
2880
2881/** @callback_method_impl{FNCPUMRDMSR} */
2882static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8HwCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2883{
2884 /** @todo AMD HW_CFG */
2885 *puValue = 0;
2886 return VINF_SUCCESS;
2887}
2888
2889
2890/** @callback_method_impl{FNCPUMWRMSR} */
2891static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8HwCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2892{
2893 /** @todo AMD HW_CFG */
2894 return VINF_SUCCESS;
2895}
2896
2897
2898/** @callback_method_impl{FNCPUMRDMSR} */
2899static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IorrBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2900{
2901 /** @todo AMD IorrMask/IorrBase */
2902 *puValue = 0;
2903 return VINF_SUCCESS;
2904}
2905
2906
2907/** @callback_method_impl{FNCPUMWRMSR} */
2908static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IorrBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2909{
2910 /** @todo AMD IorrMask/IorrBase */
2911 return VINF_SUCCESS;
2912}
2913
2914
2915/** @callback_method_impl{FNCPUMRDMSR} */
2916static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IorrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2917{
2918 /** @todo AMD IorrMask/IorrBase */
2919 *puValue = 0;
2920 return VINF_SUCCESS;
2921}
2922
2923
2924/** @callback_method_impl{FNCPUMWRMSR} */
2925static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IorrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2926{
2927 /** @todo AMD IorrMask/IorrBase */
2928 return VINF_SUCCESS;
2929}
2930
2931
2932/** @callback_method_impl{FNCPUMRDMSR} */
2933static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8TopOfMemN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2934{
2935 *puValue = 0;
2936 /** @todo return 4GB - RamHoleSize here for TOPMEM. Figure out what to return
2937 * for TOPMEM2. */
2938 //if (pRange->uValue == 0)
2939 // *puValue = _4G - RamHoleSize;
2940 return VINF_SUCCESS;
2941}
2942
2943
2944/** @callback_method_impl{FNCPUMWRMSR} */
2945static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8TopOfMemN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2946{
2947 /** @todo AMD TOPMEM and TOPMEM2/TOM2. */
2948 return VINF_SUCCESS;
2949}
2950
2951
2952/** @callback_method_impl{FNCPUMRDMSR} */
2953static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8NbCfg1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2954{
2955 /** @todo AMD NB_CFG1 */
2956 *puValue = 0;
2957 return VINF_SUCCESS;
2958}
2959
2960
2961/** @callback_method_impl{FNCPUMWRMSR} */
2962static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8NbCfg1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2963{
2964 /** @todo AMD NB_CFG1 */
2965 return VINF_SUCCESS;
2966}
2967
2968
2969/** @callback_method_impl{FNCPUMRDMSR} */
2970static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8McXcptRedir(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2971{
2972 /** @todo machine check. */
2973 *puValue = 0;
2974 return VINF_SUCCESS;
2975}
2976
2977
2978/** @callback_method_impl{FNCPUMWRMSR} */
2979static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8McXcptRedir(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2980{
2981 /** @todo machine check. */
2982 return VINF_SUCCESS;
2983}
2984
2985
2986/** @callback_method_impl{FNCPUMRDMSR} */
2987static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuNameN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2988{
2989 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), pRange->uValue / 2 + 0x80000001);
2990 if (pLeaf)
2991 {
2992 if (!(pRange->uValue & 1))
2993 *puValue = RT_MAKE_U64(pLeaf->uEax, pLeaf->uEbx);
2994 else
2995 *puValue = RT_MAKE_U64(pLeaf->uEcx, pLeaf->uEdx);
2996 }
2997 else
2998 *puValue = 0;
2999 return VINF_SUCCESS;
3000}
3001
3002
3003/** @callback_method_impl{FNCPUMWRMSR} */
3004static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuNameN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3005{
3006 /** @todo Remember guest programmed CPU name. */
3007 return VINF_SUCCESS;
3008}
3009
3010
3011/** @callback_method_impl{FNCPUMRDMSR} */
3012static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8HwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3013{
3014 /** @todo AMD HTC. */
3015 *puValue = pRange->uValue;
3016 return VINF_SUCCESS;
3017}
3018
3019
3020/** @callback_method_impl{FNCPUMWRMSR} */
3021static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8HwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3022{
3023 /** @todo AMD HTC. */
3024 return VINF_SUCCESS;
3025}
3026
3027
3028/** @callback_method_impl{FNCPUMRDMSR} */
3029static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3030{
3031 /** @todo AMD STC. */
3032 *puValue = 0;
3033 return VINF_SUCCESS;
3034}
3035
3036
3037/** @callback_method_impl{FNCPUMWRMSR} */
3038static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3039{
3040 /** @todo AMD STC. */
3041 return VINF_SUCCESS;
3042}
3043
3044
3045/** @callback_method_impl{FNCPUMRDMSR} */
3046static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8FidVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3047{
3048 /** @todo AMD FIDVID_CTL. */
3049 *puValue = pRange->uValue;
3050 return VINF_SUCCESS;
3051}
3052
3053
3054/** @callback_method_impl{FNCPUMWRMSR} */
3055static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8FidVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3056{
3057 /** @todo AMD FIDVID_CTL. */
3058 return VINF_SUCCESS;
3059}
3060
3061
3062/** @callback_method_impl{FNCPUMRDMSR} */
3063static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8FidVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3064{
3065 /** @todo AMD FIDVID_STATUS. */
3066 *puValue = pRange->uValue;
3067 return VINF_SUCCESS;
3068}
3069
3070
3071/** @callback_method_impl{FNCPUMRDMSR} */
3072static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8McCtlMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3073{
3074 /** @todo AMD MC. */
3075 *puValue = 0;
3076 return VINF_SUCCESS;
3077}
3078
3079
3080/** @callback_method_impl{FNCPUMWRMSR} */
3081static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8McCtlMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3082{
3083 /** @todo AMD MC. */
3084 return VINF_SUCCESS;
3085}
3086
3087
3088/** @callback_method_impl{FNCPUMRDMSR} */
3089static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmiOnIoTrapN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3090{
3091 /** @todo AMD SMM/SMI and I/O trap. */
3092 *puValue = 0;
3093 return VINF_SUCCESS;
3094}
3095
3096
3097/** @callback_method_impl{FNCPUMWRMSR} */
3098static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmiOnIoTrapN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3099{
3100 /** @todo AMD SMM/SMI and I/O trap. */
3101 return VINF_SUCCESS;
3102}
3103
3104
3105/** @callback_method_impl{FNCPUMRDMSR} */
3106static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmiOnIoTrapCtlSts(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3107{
3108 /** @todo AMD SMM/SMI and I/O trap. */
3109 *puValue = 0;
3110 return VINF_SUCCESS;
3111}
3112
3113
3114/** @callback_method_impl{FNCPUMWRMSR} */
3115static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmiOnIoTrapCtlSts(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3116{
3117 /** @todo AMD SMM/SMI and I/O trap. */
3118 return VINF_SUCCESS;
3119}
3120
3121
3122/** @callback_method_impl{FNCPUMRDMSR} */
3123static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IntPendingMessage(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3124{
3125 /** @todo Interrupt pending message. */
3126 *puValue = 0;
3127 return VINF_SUCCESS;
3128}
3129
3130
3131/** @callback_method_impl{FNCPUMWRMSR} */
3132static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IntPendingMessage(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3133{
3134 /** @todo Interrupt pending message. */
3135 return VINF_SUCCESS;
3136}
3137
3138
3139/** @callback_method_impl{FNCPUMRDMSR} */
3140static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmiTriggerIoCycle(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3141{
3142 /** @todo AMD SMM/SMI and trigger I/O cycle. */
3143 *puValue = 0;
3144 return VINF_SUCCESS;
3145}
3146
3147
3148/** @callback_method_impl{FNCPUMWRMSR} */
3149static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmiTriggerIoCycle(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3150{
3151 /** @todo AMD SMM/SMI and trigger I/O cycle. */
3152 return VINF_SUCCESS;
3153}
3154
3155
3156/** @callback_method_impl{FNCPUMRDMSR} */
3157static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hMmioCfgBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3158{
3159 /** @todo AMD MMIO Configuration base address. */
3160 *puValue = 0;
3161 return VINF_SUCCESS;
3162}
3163
3164
3165/** @callback_method_impl{FNCPUMWRMSR} */
3166static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hMmioCfgBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3167{
3168 /** @todo AMD MMIO Configuration base address. */
3169 return VINF_SUCCESS;
3170}
3171
3172
3173/** @callback_method_impl{FNCPUMRDMSR} */
3174static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hTrapCtlMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3175{
3176 /** @todo AMD 0xc0010059. */
3177 *puValue = 0;
3178 return VINF_SUCCESS;
3179}
3180
3181
3182/** @callback_method_impl{FNCPUMWRMSR} */
3183static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hTrapCtlMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3184{
3185 /** @todo AMD 0xc0010059. */
3186 return VINF_SUCCESS;
3187}
3188
3189
3190/** @callback_method_impl{FNCPUMRDMSR} */
3191static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateCurLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3192{
3193 /** @todo AMD P-states. */
3194 *puValue = pRange->uValue;
3195 return VINF_SUCCESS;
3196}
3197
3198
3199/** @callback_method_impl{FNCPUMRDMSR} */
3200static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3201{
3202 /** @todo AMD P-states. */
3203 *puValue = pRange->uValue;
3204 return VINF_SUCCESS;
3205}
3206
3207
3208/** @callback_method_impl{FNCPUMWRMSR} */
3209static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hPStateControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3210{
3211 /** @todo AMD P-states. */
3212 return VINF_SUCCESS;
3213}
3214
3215
3216/** @callback_method_impl{FNCPUMRDMSR} */
3217static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3218{
3219 /** @todo AMD P-states. */
3220 *puValue = pRange->uValue;
3221 return VINF_SUCCESS;
3222}
3223
3224
3225/** @callback_method_impl{FNCPUMWRMSR} */
3226static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hPStateStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3227{
3228 /** @todo AMD P-states. */
3229 return VINF_SUCCESS;
3230}
3231
3232
3233/** @callback_method_impl{FNCPUMRDMSR} */
3234static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3235{
3236 /** @todo AMD P-states. */
3237 *puValue = pRange->uValue;
3238 return VINF_SUCCESS;
3239}
3240
3241
3242/** @callback_method_impl{FNCPUMWRMSR} */
3243static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hPStateN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3244{
3245 /** @todo AMD P-states. */
3246 return VINF_SUCCESS;
3247}
3248
3249
3250/** @callback_method_impl{FNCPUMRDMSR} */
3251static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCofVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3252{
3253 /** @todo AMD P-states. */
3254 *puValue = pRange->uValue;
3255 return VINF_SUCCESS;
3256}
3257
3258
3259/** @callback_method_impl{FNCPUMWRMSR} */
3260static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCofVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3261{
3262 /** @todo AMD P-states. */
3263 return VINF_SUCCESS;
3264}
3265
3266
3267/** @callback_method_impl{FNCPUMRDMSR} */
3268static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCofVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3269{
3270 /** @todo AMD P-states. */
3271 *puValue = pRange->uValue;
3272 return VINF_SUCCESS;
3273}
3274
3275
3276/** @callback_method_impl{FNCPUMWRMSR} */
3277static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCofVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3278{
3279 /* Note! Writing 0 seems to not GP, not sure if it does anything to the value... */
3280 /** @todo AMD P-states. */
3281 return VINF_SUCCESS;
3282}
3283
3284
3285/** @callback_method_impl{FNCPUMRDMSR} */
3286static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCStateIoBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3287{
3288 /** @todo AMD C-states. */
3289 *puValue = 0;
3290 return VINF_SUCCESS;
3291}
3292
3293
3294/** @callback_method_impl{FNCPUMWRMSR} */
3295static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCStateIoBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3296{
3297 /** @todo AMD C-states. */
3298 return VINF_SUCCESS;
3299}
3300
3301
3302/** @callback_method_impl{FNCPUMRDMSR} */
3303static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCpuWatchdogTimer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3304{
3305 /** @todo AMD machine checks. */
3306 *puValue = 0;
3307 return VINF_SUCCESS;
3308}
3309
3310
3311/** @callback_method_impl{FNCPUMWRMSR} */
3312static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCpuWatchdogTimer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3313{
3314 /** @todo AMD machine checks. */
3315 return VINF_SUCCESS;
3316}
3317
3318
3319/** @callback_method_impl{FNCPUMRDMSR} */
3320static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3321{
3322 /** @todo AMD SMM. */
3323 *puValue = 0;
3324 return VINF_SUCCESS;
3325}
3326
3327
3328/** @callback_method_impl{FNCPUMWRMSR} */
3329static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3330{
3331 /** @todo AMD SMM. */
3332 return VINF_SUCCESS;
3333}
3334
3335
3336/** @callback_method_impl{FNCPUMRDMSR} */
3337static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3338{
3339 /** @todo AMD SMM. */
3340 *puValue = 0;
3341 return VINF_SUCCESS;
3342}
3343
3344
3345/** @callback_method_impl{FNCPUMWRMSR} */
3346static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3347{
3348 /** @todo AMD SMM. */
3349 return VINF_SUCCESS;
3350}
3351
3352
3353
3354/** @callback_method_impl{FNCPUMRDMSR} */
3355static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3356{
3357 /** @todo AMD SMM. */
3358 *puValue = 0;
3359 return VINF_SUCCESS;
3360}
3361
3362
3363/** @callback_method_impl{FNCPUMWRMSR} */
3364static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3365{
3366 /** @todo AMD SMM. */
3367 return VINF_SUCCESS;
3368}
3369
3370
3371/** @callback_method_impl{FNCPUMRDMSR} */
3372static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8VmCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3373{
3374 /** @todo AMD SVM. */
3375 *puValue = 0;
3376 return VINF_SUCCESS;
3377}
3378
3379
3380/** @callback_method_impl{FNCPUMWRMSR} */
3381static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8VmCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3382{
3383 /** @todo AMD SVM. */
3384 return VINF_SUCCESS;
3385}
3386
3387
3388/** @callback_method_impl{FNCPUMRDMSR} */
3389static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IgnNe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3390{
3391 /** @todo AMD IGNNE\# control. */
3392 *puValue = 0;
3393 return VINF_SUCCESS;
3394}
3395
3396
3397/** @callback_method_impl{FNCPUMWRMSR} */
3398static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IgnNe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3399{
3400 /** @todo AMD IGNNE\# control. */
3401 return VINF_SUCCESS;
3402}
3403
3404
3405/** @callback_method_impl{FNCPUMRDMSR} */
3406static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3407{
3408 /** @todo AMD SMM. */
3409 *puValue = 0;
3410 return VINF_SUCCESS;
3411}
3412
3413
3414/** @callback_method_impl{FNCPUMWRMSR} */
3415static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3416{
3417 /** @todo AMD SMM. */
3418 return VINF_SUCCESS;
3419}
3420
3421
3422/** @callback_method_impl{FNCPUMRDMSR} */
3423static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8VmHSavePa(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3424{
3425 /** @todo AMD SVM. */
3426 *puValue = 0;
3427 return VINF_SUCCESS;
3428}
3429
3430
3431/** @callback_method_impl{FNCPUMWRMSR} */
3432static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8VmHSavePa(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3433{
3434 /** @todo AMD SVM. */
3435 return VINF_SUCCESS;
3436}
3437
3438
3439/** @callback_method_impl{FNCPUMRDMSR} */
3440static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hVmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3441{
3442 /** @todo AMD SVM. */
3443 *puValue = 0; /* RAZ */
3444 return VINF_SUCCESS;
3445}
3446
3447
3448/** @callback_method_impl{FNCPUMWRMSR} */
3449static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hVmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3450{
3451 /** @todo AMD SVM. */
3452 return VINF_SUCCESS;
3453}
3454
3455
3456/** @callback_method_impl{FNCPUMRDMSR} */
3457static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hSmmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3458{
3459 /** @todo AMD SMM. */
3460 *puValue = 0; /* RAZ */
3461 return VINF_SUCCESS;
3462}
3463
3464
3465/** @callback_method_impl{FNCPUMWRMSR} */
3466static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hSmmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3467{
3468 /** @todo AMD SMM. */
3469 return VINF_SUCCESS;
3470}
3471
3472
3473/** @callback_method_impl{FNCPUMRDMSR} */
3474static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hLocalSmiStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3475{
3476 /** @todo AMD SMM/SMI. */
3477 *puValue = 0;
3478 return VINF_SUCCESS;
3479}
3480
3481
3482/** @callback_method_impl{FNCPUMWRMSR} */
3483static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hLocalSmiStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3484{
3485 /** @todo AMD SMM/SMI. */
3486 return VINF_SUCCESS;
3487}
3488
3489
3490/** @callback_method_impl{FNCPUMRDMSR} */
3491static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hOsVisWrkIdLength(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3492{
3493 /** @todo AMD OS visible workaround. */
3494 *puValue = pRange->uValue;
3495 return VINF_SUCCESS;
3496}
3497
3498
3499/** @callback_method_impl{FNCPUMWRMSR} */
3500static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hOsVisWrkIdLength(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3501{
3502 /** @todo AMD OS visible workaround. */
3503 return VINF_SUCCESS;
3504}
3505
3506
3507/** @callback_method_impl{FNCPUMRDMSR} */
3508static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hOsVisWrkStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3509{
3510 /** @todo AMD OS visible workaround. */
3511 *puValue = 0;
3512 return VINF_SUCCESS;
3513}
3514
3515
3516/** @callback_method_impl{FNCPUMWRMSR} */
3517static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hOsVisWrkStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3518{
3519 /** @todo AMD OS visible workaround. */
3520 return VINF_SUCCESS;
3521}
3522
3523
3524/** @callback_method_impl{FNCPUMRDMSR} */
3525static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam16hL2IPerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3526{
3527 /** @todo AMD L2I performance counters. */
3528 *puValue = 0;
3529 return VINF_SUCCESS;
3530}
3531
3532
3533/** @callback_method_impl{FNCPUMWRMSR} */
3534static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam16hL2IPerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3535{
3536 /** @todo AMD L2I performance counters. */
3537 return VINF_SUCCESS;
3538}
3539
3540
3541/** @callback_method_impl{FNCPUMRDMSR} */
3542static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam16hL2IPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3543{
3544 /** @todo AMD L2I performance counters. */
3545 *puValue = 0;
3546 return VINF_SUCCESS;
3547}
3548
3549
3550/** @callback_method_impl{FNCPUMWRMSR} */
3551static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam16hL2IPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3552{
3553 /** @todo AMD L2I performance counters. */
3554 return VINF_SUCCESS;
3555}
3556
3557
3558/** @callback_method_impl{FNCPUMRDMSR} */
3559static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hNorthbridgePerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3560{
3561 /** @todo AMD Northbridge performance counters. */
3562 *puValue = 0;
3563 return VINF_SUCCESS;
3564}
3565
3566
3567/** @callback_method_impl{FNCPUMWRMSR} */
3568static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hNorthbridgePerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3569{
3570 /** @todo AMD Northbridge performance counters. */
3571 return VINF_SUCCESS;
3572}
3573
3574
3575/** @callback_method_impl{FNCPUMRDMSR} */
3576static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hNorthbridgePerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3577{
3578 /** @todo AMD Northbridge performance counters. */
3579 *puValue = 0;
3580 return VINF_SUCCESS;
3581}
3582
3583
3584/** @callback_method_impl{FNCPUMWRMSR} */
3585static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hNorthbridgePerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3586{
3587 /** @todo AMD Northbridge performance counters. */
3588 return VINF_SUCCESS;
3589}
3590
3591
3592/** @callback_method_impl{FNCPUMRDMSR} */
3593static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7MicrocodeCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3594{
3595 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3596 * cpus. Need to be explored and verify K7 presence. */
3597 /** @todo Undocumented register only seen mentioned in fam15h erratum \#608. */
3598 *puValue = pRange->uValue;
3599 return VINF_SUCCESS;
3600}
3601
3602
3603/** @callback_method_impl{FNCPUMWRMSR} */
3604static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7MicrocodeCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3605{
3606 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3607 * cpus. Need to be explored and verify K7 presence. */
3608 /** @todo Undocumented register only seen mentioned in fam15h erratum \#608. */
3609 return VINF_SUCCESS;
3610}
3611
3612
3613/** @callback_method_impl{FNCPUMRDMSR} */
3614static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7ClusterIdMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3615{
3616 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3617 * cpus. Need to be explored and verify K7 presence. */
3618 /** @todo Undocumented register only seen mentioned in fam16h BKDG r3.00 when
3619 * describing EBL_CR_POWERON. */
3620 *puValue = pRange->uValue;
3621 return VINF_SUCCESS;
3622}
3623
3624
3625/** @callback_method_impl{FNCPUMWRMSR} */
3626static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7ClusterIdMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3627{
3628 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3629 * cpus. Need to be explored and verify K7 presence. */
3630 /** @todo Undocumented register only seen mentioned in fam16h BKDG r3.00 when
3631 * describing EBL_CR_POWERON. */
3632 return VINF_SUCCESS;
3633}
3634
3635
3636/** @callback_method_impl{FNCPUMRDMSR} */
3637static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlStd07hEbax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3638{
3639 bool fIgnored;
3640 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafEx(pVCpu->CTX_SUFF(pVM), 0x00000007, 0, &fIgnored);
3641 if (pLeaf)
3642 *puValue = RT_MAKE_U64(pLeaf->uEbx, pLeaf->uEax);
3643 else
3644 *puValue = 0;
3645 return VINF_SUCCESS;
3646}
3647
3648
3649/** @callback_method_impl{FNCPUMWRMSR} */
3650static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlStd07hEbax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3651{
3652 /** @todo Changing CPUID leaf 7/0. */
3653 return VINF_SUCCESS;
3654}
3655
3656
3657/** @callback_method_impl{FNCPUMRDMSR} */
3658static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlStd06hEcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3659{
3660 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000006);
3661 if (pLeaf)
3662 *puValue = pLeaf->uEcx;
3663 else
3664 *puValue = 0;
3665 return VINF_SUCCESS;
3666}
3667
3668
3669/** @callback_method_impl{FNCPUMWRMSR} */
3670static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlStd06hEcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3671{
3672 /** @todo Changing CPUID leaf 6. */
3673 return VINF_SUCCESS;
3674}
3675
3676
3677/** @callback_method_impl{FNCPUMRDMSR} */
3678static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlStd01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3679{
3680 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000001);
3681 if (pLeaf)
3682 *puValue = RT_MAKE_U64(pLeaf->uEdx, pLeaf->uEcx);
3683 else
3684 *puValue = 0;
3685 return VINF_SUCCESS;
3686}
3687
3688
3689/** @callback_method_impl{FNCPUMWRMSR} */
3690static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlStd01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3691{
3692 /** @todo Changing CPUID leaf 0x80000001. */
3693 return VINF_SUCCESS;
3694}
3695
3696
3697/** @callback_method_impl{FNCPUMRDMSR} */
3698static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlExt01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3699{
3700 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x80000001);
3701 if (pLeaf)
3702 *puValue = RT_MAKE_U64(pLeaf->uEdx, pLeaf->uEcx);
3703 else
3704 *puValue = 0;
3705 return VINF_SUCCESS;
3706}
3707
3708
3709/** @callback_method_impl{FNCPUMWRMSR} */
3710static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlExt01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3711{
3712 /** @todo Changing CPUID leaf 0x80000001. */
3713 return VINF_SUCCESS;
3714}
3715
3716
3717/** @callback_method_impl{FNCPUMRDMSR} */
3718static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8PatchLevel(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3719{
3720 /** @todo Fake AMD microcode patching. */
3721 *puValue = pRange->uValue;
3722 return VINF_SUCCESS;
3723}
3724
3725
3726/** @callback_method_impl{FNCPUMWRMSR} */
3727static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8PatchLoader(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3728{
3729 /** @todo Fake AMD microcode patching. */
3730 return VINF_SUCCESS;
3731}
3732
3733
3734/** @callback_method_impl{FNCPUMRDMSR} */
3735static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DebugStatusMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3736{
3737 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3738 * cpus. Need to be explored and verify K7 presence. */
3739 /** @todo undocumented */
3740 *puValue = 0;
3741 return VINF_SUCCESS;
3742}
3743
3744
3745/** @callback_method_impl{FNCPUMWRMSR} */
3746static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DebugStatusMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3747{
3748 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3749 * cpus. Need to be explored and verify K7 presence. */
3750 /** @todo undocumented */
3751 return VINF_SUCCESS;
3752}
3753
3754
3755/** @callback_method_impl{FNCPUMRDMSR} */
3756static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BHTraceBaseMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3757{
3758 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3759 * cpus. Need to be explored and verify K7 presence. */
3760 /** @todo undocumented */
3761 *puValue = 0;
3762 return VINF_SUCCESS;
3763}
3764
3765
3766/** @callback_method_impl{FNCPUMWRMSR} */
3767static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BHTraceBaseMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3768{
3769 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3770 * cpus. Need to be explored and verify K7 presence. */
3771 /** @todo undocumented */
3772 return VINF_SUCCESS;
3773}
3774
3775
3776/** @callback_method_impl{FNCPUMRDMSR} */
3777static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BHTracePtrMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3778{
3779 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3780 * cpus. Need to be explored and verify K7 presence. */
3781 /** @todo undocumented */
3782 *puValue = 0;
3783 return VINF_SUCCESS;
3784}
3785
3786
3787/** @callback_method_impl{FNCPUMWRMSR} */
3788static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BHTracePtrMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3789{
3790 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3791 * cpus. Need to be explored and verify K7 presence. */
3792 /** @todo undocumented */
3793 return VINF_SUCCESS;
3794}
3795
3796
3797/** @callback_method_impl{FNCPUMRDMSR} */
3798static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BHTraceLimitMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3799{
3800 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3801 * cpus. Need to be explored and verify K7 presence. */
3802 /** @todo undocumented */
3803 *puValue = 0;
3804 return VINF_SUCCESS;
3805}
3806
3807
3808/** @callback_method_impl{FNCPUMWRMSR} */
3809static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BHTraceLimitMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3810{
3811 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3812 * cpus. Need to be explored and verify K7 presence. */
3813 /** @todo undocumented */
3814 return VINF_SUCCESS;
3815}
3816
3817
3818/** @callback_method_impl{FNCPUMRDMSR} */
3819static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7HardwareDebugToolCfgMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3820{
3821 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3822 * cpus. Need to be explored and verify K7 presence. */
3823 /** @todo undocumented */
3824 *puValue = 0;
3825 return VINF_SUCCESS;
3826}
3827
3828
3829/** @callback_method_impl{FNCPUMWRMSR} */
3830static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7HardwareDebugToolCfgMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3831{
3832 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3833 * cpus. Need to be explored and verify K7 presence. */
3834 /** @todo undocumented */
3835 return VINF_SUCCESS;
3836}
3837
3838
3839/** @callback_method_impl{FNCPUMRDMSR} */
3840static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7FastFlushCountMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3841{
3842 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3843 * cpus. Need to be explored and verify K7 presence. */
3844 /** @todo undocumented */
3845 *puValue = 0;
3846 return VINF_SUCCESS;
3847}
3848
3849
3850/** @callback_method_impl{FNCPUMWRMSR} */
3851static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7FastFlushCountMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3852{
3853 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3854 * cpus. Need to be explored and verify K7 presence. */
3855 /** @todo undocumented */
3856 return VINF_SUCCESS;
3857}
3858
3859
3860/** @callback_method_impl{FNCPUMRDMSR} */
3861static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7NodeId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3862{
3863 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3864 * cpus. Need to be explored and verify K7 presence. */
3865 /** @todo AMD node ID and bios scratch. */
3866 *puValue = 0; /* nodeid = 0; nodes-per-cpu = 1 */
3867 return VINF_SUCCESS;
3868}
3869
3870
3871/** @callback_method_impl{FNCPUMWRMSR} */
3872static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7NodeId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3873{
3874 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3875 * cpus. Need to be explored and verify K7 presence. */
3876 /** @todo AMD node ID and bios scratch. */
3877 return VINF_SUCCESS;
3878}
3879
3880
3881/** @callback_method_impl{FNCPUMRDMSR} */
3882static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DrXAddrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3883{
3884 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3885 * cpus. Need to be explored and verify K7 presence. */
3886 /** @todo AMD DRx address masking (range breakpoints). */
3887 *puValue = 0;
3888 return VINF_SUCCESS;
3889}
3890
3891
3892/** @callback_method_impl{FNCPUMWRMSR} */
3893static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DrXAddrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3894{
3895 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3896 * cpus. Need to be explored and verify K7 presence. */
3897 /** @todo AMD DRx address masking (range breakpoints). */
3898 return VINF_SUCCESS;
3899}
3900
3901
3902/** @callback_method_impl{FNCPUMRDMSR} */
3903static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7Dr0DataMatchMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3904{
3905 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3906 * cpus. Need to be explored and verify K7 presence. */
3907 /** @todo AMD undocument debugging features. */
3908 *puValue = 0;
3909 return VINF_SUCCESS;
3910}
3911
3912
3913/** @callback_method_impl{FNCPUMWRMSR} */
3914static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7Dr0DataMatchMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3915{
3916 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3917 * cpus. Need to be explored and verify K7 presence. */
3918 /** @todo AMD undocument debugging features. */
3919 return VINF_SUCCESS;
3920}
3921
3922
3923/** @callback_method_impl{FNCPUMRDMSR} */
3924static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7Dr0DataMaskMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3925{
3926 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3927 * cpus. Need to be explored and verify K7 presence. */
3928 /** @todo AMD undocument debugging features. */
3929 *puValue = 0;
3930 return VINF_SUCCESS;
3931}
3932
3933
3934/** @callback_method_impl{FNCPUMWRMSR} */
3935static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7Dr0DataMaskMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3936{
3937 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3938 * cpus. Need to be explored and verify K7 presence. */
3939 /** @todo AMD undocument debugging features. */
3940 return VINF_SUCCESS;
3941}
3942
3943
3944/** @callback_method_impl{FNCPUMRDMSR} */
3945static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7LoadStoreCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3946{
3947 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3948 * cpus. Need to be explored and verify K7 presence. */
3949 /** @todo AMD load-store config. */
3950 *puValue = 0;
3951 return VINF_SUCCESS;
3952}
3953
3954
3955/** @callback_method_impl{FNCPUMWRMSR} */
3956static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7LoadStoreCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3957{
3958 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3959 * cpus. Need to be explored and verify K7 presence. */
3960 /** @todo AMD load-store config. */
3961 return VINF_SUCCESS;
3962}
3963
3964
3965/** @callback_method_impl{FNCPUMRDMSR} */
3966static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7InstrCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3967{
3968 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3969 * cpus. Need to be explored and verify K7 presence. */
3970 /** @todo AMD instruction cache config. */
3971 *puValue = 0;
3972 return VINF_SUCCESS;
3973}
3974
3975
3976/** @callback_method_impl{FNCPUMWRMSR} */
3977static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7InstrCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3978{
3979 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3980 * cpus. Need to be explored and verify K7 presence. */
3981 /** @todo AMD instruction cache config. */
3982 return VINF_SUCCESS;
3983}
3984
3985
3986/** @callback_method_impl{FNCPUMRDMSR} */
3987static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DataCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3988{
3989 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3990 * cpus. Need to be explored and verify K7 presence. */
3991 /** @todo AMD data cache config. */
3992 *puValue = 0;
3993 return VINF_SUCCESS;
3994}
3995
3996
3997/** @callback_method_impl{FNCPUMWRMSR} */
3998static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DataCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3999{
4000 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4001 * cpus. Need to be explored and verify K7 presence. */
4002 /** @todo AMD data cache config. */
4003 return VINF_SUCCESS;
4004}
4005
4006
4007/** @callback_method_impl{FNCPUMRDMSR} */
4008static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BusUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4009{
4010 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4011 * cpus. Need to be explored and verify K7 presence. */
4012 /** @todo AMD bus unit config. */
4013 *puValue = 0;
4014 return VINF_SUCCESS;
4015}
4016
4017
4018/** @callback_method_impl{FNCPUMWRMSR} */
4019static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BusUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4020{
4021 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4022 * cpus. Need to be explored and verify K7 presence. */
4023 /** @todo AMD bus unit config. */
4024 return VINF_SUCCESS;
4025}
4026
4027
4028/** @callback_method_impl{FNCPUMRDMSR} */
4029static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DebugCtl2Maybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4030{
4031 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4032 * cpus. Need to be explored and verify K7 presence. */
4033 /** @todo Undocument AMD debug control register \#2. */
4034 *puValue = 0;
4035 return VINF_SUCCESS;
4036}
4037
4038
4039/** @callback_method_impl{FNCPUMWRMSR} */
4040static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DebugCtl2Maybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4041{
4042 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4043 * cpus. Need to be explored and verify K7 presence. */
4044 /** @todo Undocument AMD debug control register \#2. */
4045 return VINF_SUCCESS;
4046}
4047
4048
4049/** @callback_method_impl{FNCPUMRDMSR} */
4050static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hFpuCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4051{
4052 /** @todo AMD FPU config. */
4053 *puValue = 0;
4054 return VINF_SUCCESS;
4055}
4056
4057
4058/** @callback_method_impl{FNCPUMWRMSR} */
4059static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hFpuCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4060{
4061 /** @todo AMD FPU config. */
4062 return VINF_SUCCESS;
4063}
4064
4065
4066/** @callback_method_impl{FNCPUMRDMSR} */
4067static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hDecoderCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4068{
4069 /** @todo AMD decoder config. */
4070 *puValue = 0;
4071 return VINF_SUCCESS;
4072}
4073
4074
4075/** @callback_method_impl{FNCPUMWRMSR} */
4076static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hDecoderCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4077{
4078 /** @todo AMD decoder config. */
4079 return VINF_SUCCESS;
4080}
4081
4082
4083/** @callback_method_impl{FNCPUMRDMSR} */
4084static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hBusUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4085{
4086 /* Note! 10h and 16h */
4087 /** @todo AMD bus unit config. */
4088 *puValue = 0;
4089 return VINF_SUCCESS;
4090}
4091
4092
4093/** @callback_method_impl{FNCPUMWRMSR} */
4094static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hBusUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4095{
4096 /* Note! 10h and 16h */
4097 /** @todo AMD bus unit config. */
4098 return VINF_SUCCESS;
4099}
4100
4101
4102/** @callback_method_impl{FNCPUMRDMSR} */
4103static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hCombUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4104{
4105 /** @todo AMD unit config. */
4106 *puValue = 0;
4107 return VINF_SUCCESS;
4108}
4109
4110
4111/** @callback_method_impl{FNCPUMWRMSR} */
4112static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hCombUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4113{
4114 /** @todo AMD unit config. */
4115 return VINF_SUCCESS;
4116}
4117
4118
4119/** @callback_method_impl{FNCPUMRDMSR} */
4120static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hCombUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4121{
4122 /** @todo AMD unit config 2. */
4123 *puValue = 0;
4124 return VINF_SUCCESS;
4125}
4126
4127
4128/** @callback_method_impl{FNCPUMWRMSR} */
4129static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hCombUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4130{
4131 /** @todo AMD unit config 2. */
4132 return VINF_SUCCESS;
4133}
4134
4135
4136/** @callback_method_impl{FNCPUMRDMSR} */
4137static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hCombUnitCfg3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4138{
4139 /** @todo AMD combined unit config 3. */
4140 *puValue = 0;
4141 return VINF_SUCCESS;
4142}
4143
4144
4145/** @callback_method_impl{FNCPUMWRMSR} */
4146static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hCombUnitCfg3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4147{
4148 /** @todo AMD combined unit config 3. */
4149 return VINF_SUCCESS;
4150}
4151
4152
4153/** @callback_method_impl{FNCPUMRDMSR} */
4154static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hExecUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4155{
4156 /** @todo AMD execution unit config. */
4157 *puValue = 0;
4158 return VINF_SUCCESS;
4159}
4160
4161
4162/** @callback_method_impl{FNCPUMWRMSR} */
4163static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hExecUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4164{
4165 /** @todo AMD execution unit config. */
4166 return VINF_SUCCESS;
4167}
4168
4169
4170/** @callback_method_impl{FNCPUMRDMSR} */
4171static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hLoadStoreCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4172{
4173 /** @todo AMD load-store config 2. */
4174 *puValue = 0;
4175 return VINF_SUCCESS;
4176}
4177
4178
4179/** @callback_method_impl{FNCPUMWRMSR} */
4180static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hLoadStoreCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4181{
4182 /** @todo AMD load-store config 2. */
4183 return VINF_SUCCESS;
4184}
4185
4186
4187/** @callback_method_impl{FNCPUMRDMSR} */
4188static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsFetchCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4189{
4190 /** @todo AMD IBS. */
4191 *puValue = 0;
4192 return VINF_SUCCESS;
4193}
4194
4195
4196/** @callback_method_impl{FNCPUMWRMSR} */
4197static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsFetchCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4198{
4199 /** @todo AMD IBS. */
4200 return VINF_SUCCESS;
4201}
4202
4203
4204/** @callback_method_impl{FNCPUMRDMSR} */
4205static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsFetchLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4206{
4207 /** @todo AMD IBS. */
4208 *puValue = 0;
4209 return VINF_SUCCESS;
4210}
4211
4212
4213/** @callback_method_impl{FNCPUMWRMSR} */
4214static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsFetchLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4215{
4216 /** @todo AMD IBS. */
4217 return VINF_SUCCESS;
4218}
4219
4220
4221/** @callback_method_impl{FNCPUMRDMSR} */
4222static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsFetchPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4223{
4224 /** @todo AMD IBS. */
4225 *puValue = 0;
4226 return VINF_SUCCESS;
4227}
4228
4229
4230/** @callback_method_impl{FNCPUMWRMSR} */
4231static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsFetchPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4232{
4233 /** @todo AMD IBS. */
4234 return VINF_SUCCESS;
4235}
4236
4237
4238/** @callback_method_impl{FNCPUMRDMSR} */
4239static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpExecCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4240{
4241 /** @todo AMD IBS. */
4242 *puValue = 0;
4243 return VINF_SUCCESS;
4244}
4245
4246
4247/** @callback_method_impl{FNCPUMWRMSR} */
4248static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpExecCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4249{
4250 /** @todo AMD IBS. */
4251 return VINF_SUCCESS;
4252}
4253
4254
4255/** @callback_method_impl{FNCPUMRDMSR} */
4256static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpRip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4257{
4258 /** @todo AMD IBS. */
4259 *puValue = 0;
4260 return VINF_SUCCESS;
4261}
4262
4263
4264/** @callback_method_impl{FNCPUMWRMSR} */
4265static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpRip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4266{
4267 /** @todo AMD IBS. */
4268 if (!X86_IS_CANONICAL(uValue))
4269 {
4270 Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
4271 return VERR_CPUM_RAISE_GP_0;
4272 }
4273 return VINF_SUCCESS;
4274}
4275
4276
4277/** @callback_method_impl{FNCPUMRDMSR} */
4278static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpData(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4279{
4280 /** @todo AMD IBS. */
4281 *puValue = 0;
4282 return VINF_SUCCESS;
4283}
4284
4285
4286/** @callback_method_impl{FNCPUMWRMSR} */
4287static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpData(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4288{
4289 /** @todo AMD IBS. */
4290 return VINF_SUCCESS;
4291}
4292
4293
4294/** @callback_method_impl{FNCPUMRDMSR} */
4295static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpData2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4296{
4297 /** @todo AMD IBS. */
4298 *puValue = 0;
4299 return VINF_SUCCESS;
4300}
4301
4302
4303/** @callback_method_impl{FNCPUMWRMSR} */
4304static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpData2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4305{
4306 /** @todo AMD IBS. */
4307 return VINF_SUCCESS;
4308}
4309
4310
4311/** @callback_method_impl{FNCPUMRDMSR} */
4312static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpData3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4313{
4314 /** @todo AMD IBS. */
4315 *puValue = 0;
4316 return VINF_SUCCESS;
4317}
4318
4319
4320/** @callback_method_impl{FNCPUMWRMSR} */
4321static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpData3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4322{
4323 /** @todo AMD IBS. */
4324 return VINF_SUCCESS;
4325}
4326
4327
4328/** @callback_method_impl{FNCPUMRDMSR} */
4329static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsDcLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4330{
4331 /** @todo AMD IBS. */
4332 *puValue = 0;
4333 return VINF_SUCCESS;
4334}
4335
4336
4337/** @callback_method_impl{FNCPUMWRMSR} */
4338static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsDcLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4339{
4340 /** @todo AMD IBS. */
4341 if (!X86_IS_CANONICAL(uValue))
4342 {
4343 Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
4344 return VERR_CPUM_RAISE_GP_0;
4345 }
4346 return VINF_SUCCESS;
4347}
4348
4349
4350/** @callback_method_impl{FNCPUMRDMSR} */
4351static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsDcPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4352{
4353 /** @todo AMD IBS. */
4354 *puValue = 0;
4355 return VINF_SUCCESS;
4356}
4357
4358
4359/** @callback_method_impl{FNCPUMWRMSR} */
4360static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsDcPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4361{
4362 /** @todo AMD IBS. */
4363 return VINF_SUCCESS;
4364}
4365
4366
4367/** @callback_method_impl{FNCPUMRDMSR} */
4368static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4369{
4370 /** @todo AMD IBS. */
4371 *puValue = 0;
4372 return VINF_SUCCESS;
4373}
4374
4375
4376/** @callback_method_impl{FNCPUMWRMSR} */
4377static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4378{
4379 /** @todo AMD IBS. */
4380 return VINF_SUCCESS;
4381}
4382
4383
4384/** @callback_method_impl{FNCPUMRDMSR} */
4385static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam14hIbsBrTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4386{
4387 /** @todo AMD IBS. */
4388 *puValue = 0;
4389 return VINF_SUCCESS;
4390}
4391
4392
4393/** @callback_method_impl{FNCPUMWRMSR} */
4394static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam14hIbsBrTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4395{
4396 /** @todo AMD IBS. */
4397 if (!X86_IS_CANONICAL(uValue))
4398 {
4399 Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
4400 return VERR_CPUM_RAISE_GP_0;
4401 }
4402 return VINF_SUCCESS;
4403}
4404
4405
4406
4407/*
4408 * GIM MSRs.
4409 * GIM MSRs.
4410 * GIM MSRs.
4411 */
4412
4413
4414/** @callback_method_impl{FNCPUMRDMSR} */
4415static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Gim(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4416{
4417 return GIMReadMsr(pVCpu, idMsr, pRange, puValue);
4418}
4419
4420
4421/** @callback_method_impl{FNCPUMWRMSR} */
4422static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Gim(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4423{
4424 return GIMWriteMsr(pVCpu, idMsr, pRange, uValue, uRawValue);
4425}
4426
4427
4428/**
4429 * MSR read function table.
4430 */
4431static const PFNCPUMRDMSR g_aCpumRdMsrFns[kCpumMsrRdFn_End] =
4432{
4433 NULL, /* Invalid */
4434 cpumMsrRd_FixedValue,
4435 NULL, /* Alias */
4436 cpumMsrRd_WriteOnly,
4437 cpumMsrRd_Ia32P5McAddr,
4438 cpumMsrRd_Ia32P5McType,
4439 cpumMsrRd_Ia32TimestampCounter,
4440 cpumMsrRd_Ia32PlatformId,
4441 cpumMsrRd_Ia32ApicBase,
4442 cpumMsrRd_Ia32FeatureControl,
4443 cpumMsrRd_Ia32BiosSignId,
4444 cpumMsrRd_Ia32SmmMonitorCtl,
4445 cpumMsrRd_Ia32PmcN,
4446 cpumMsrRd_Ia32MonitorFilterLineSize,
4447 cpumMsrRd_Ia32MPerf,
4448 cpumMsrRd_Ia32APerf,
4449 cpumMsrRd_Ia32MtrrCap,
4450 cpumMsrRd_Ia32MtrrPhysBaseN,
4451 cpumMsrRd_Ia32MtrrPhysMaskN,
4452 cpumMsrRd_Ia32MtrrFixed,
4453 cpumMsrRd_Ia32MtrrDefType,
4454 cpumMsrRd_Ia32Pat,
4455 cpumMsrRd_Ia32SysEnterCs,
4456 cpumMsrRd_Ia32SysEnterEsp,
4457 cpumMsrRd_Ia32SysEnterEip,
4458 cpumMsrRd_Ia32McgCap,
4459 cpumMsrRd_Ia32McgStatus,
4460 cpumMsrRd_Ia32McgCtl,
4461 cpumMsrRd_Ia32DebugCtl,
4462 cpumMsrRd_Ia32SmrrPhysBase,
4463 cpumMsrRd_Ia32SmrrPhysMask,
4464 cpumMsrRd_Ia32PlatformDcaCap,
4465 cpumMsrRd_Ia32CpuDcaCap,
4466 cpumMsrRd_Ia32Dca0Cap,
4467 cpumMsrRd_Ia32PerfEvtSelN,
4468 cpumMsrRd_Ia32PerfStatus,
4469 cpumMsrRd_Ia32PerfCtl,
4470 cpumMsrRd_Ia32FixedCtrN,
4471 cpumMsrRd_Ia32PerfCapabilities,
4472 cpumMsrRd_Ia32FixedCtrCtrl,
4473 cpumMsrRd_Ia32PerfGlobalStatus,
4474 cpumMsrRd_Ia32PerfGlobalCtrl,
4475 cpumMsrRd_Ia32PerfGlobalOvfCtrl,
4476 cpumMsrRd_Ia32PebsEnable,
4477 cpumMsrRd_Ia32ClockModulation,
4478 cpumMsrRd_Ia32ThermInterrupt,
4479 cpumMsrRd_Ia32ThermStatus,
4480 cpumMsrRd_Ia32Therm2Ctl,
4481 cpumMsrRd_Ia32MiscEnable,
4482 cpumMsrRd_Ia32McCtlStatusAddrMiscN,
4483 cpumMsrRd_Ia32McNCtl2,
4484 cpumMsrRd_Ia32DsArea,
4485 cpumMsrRd_Ia32TscDeadline,
4486 cpumMsrRd_Ia32X2ApicN,
4487 cpumMsrRd_Ia32DebugInterface,
4488 cpumMsrRd_Ia32VmxBase,
4489 cpumMsrRd_Ia32VmxPinbasedCtls,
4490 cpumMsrRd_Ia32VmxProcbasedCtls,
4491 cpumMsrRd_Ia32VmxExitCtls,
4492 cpumMsrRd_Ia32VmxEntryCtls,
4493 cpumMsrRd_Ia32VmxMisc,
4494 cpumMsrRd_Ia32VmxCr0Fixed0,
4495 cpumMsrRd_Ia32VmxCr0Fixed1,
4496 cpumMsrRd_Ia32VmxCr4Fixed0,
4497 cpumMsrRd_Ia32VmxCr4Fixed1,
4498 cpumMsrRd_Ia32VmxVmcsEnum,
4499 cpumMsrRd_Ia32VmxProcBasedCtls2,
4500 cpumMsrRd_Ia32VmxEptVpidCap,
4501 cpumMsrRd_Ia32VmxTruePinbasedCtls,
4502 cpumMsrRd_Ia32VmxTrueProcbasedCtls,
4503 cpumMsrRd_Ia32VmxTrueExitCtls,
4504 cpumMsrRd_Ia32VmxTrueEntryCtls,
4505
4506 cpumMsrRd_Amd64Efer,
4507 cpumMsrRd_Amd64SyscallTarget,
4508 cpumMsrRd_Amd64LongSyscallTarget,
4509 cpumMsrRd_Amd64CompSyscallTarget,
4510 cpumMsrRd_Amd64SyscallFlagMask,
4511 cpumMsrRd_Amd64FsBase,
4512 cpumMsrRd_Amd64GsBase,
4513 cpumMsrRd_Amd64KernelGsBase,
4514 cpumMsrRd_Amd64TscAux,
4515
4516 cpumMsrRd_IntelEblCrPowerOn,
4517 cpumMsrRd_IntelI7CoreThreadCount,
4518 cpumMsrRd_IntelP4EbcHardPowerOn,
4519 cpumMsrRd_IntelP4EbcSoftPowerOn,
4520 cpumMsrRd_IntelP4EbcFrequencyId,
4521 cpumMsrRd_IntelP6FsbFrequency,
4522 cpumMsrRd_IntelPlatformInfo,
4523 cpumMsrRd_IntelFlexRatio,
4524 cpumMsrRd_IntelPkgCStConfigControl,
4525 cpumMsrRd_IntelPmgIoCaptureBase,
4526 cpumMsrRd_IntelLastBranchFromToN,
4527 cpumMsrRd_IntelLastBranchFromN,
4528 cpumMsrRd_IntelLastBranchToN,
4529 cpumMsrRd_IntelLastBranchTos,
4530 cpumMsrRd_IntelBblCrCtl,
4531 cpumMsrRd_IntelBblCrCtl3,
4532 cpumMsrRd_IntelI7TemperatureTarget,
4533 cpumMsrRd_IntelI7MsrOffCoreResponseN,
4534 cpumMsrRd_IntelI7MiscPwrMgmt,
4535 cpumMsrRd_IntelP6CrN,
4536 cpumMsrRd_IntelCpuId1FeatureMaskEcdx,
4537 cpumMsrRd_IntelCpuId1FeatureMaskEax,
4538 cpumMsrRd_IntelCpuId80000001FeatureMaskEcdx,
4539 cpumMsrRd_IntelI7SandyAesNiCtl,
4540 cpumMsrRd_IntelI7TurboRatioLimit,
4541 cpumMsrRd_IntelI7LbrSelect,
4542 cpumMsrRd_IntelI7SandyErrorControl,
4543 cpumMsrRd_IntelI7VirtualLegacyWireCap,
4544 cpumMsrRd_IntelI7PowerCtl,
4545 cpumMsrRd_IntelI7SandyPebsNumAlt,
4546 cpumMsrRd_IntelI7PebsLdLat,
4547 cpumMsrRd_IntelI7PkgCnResidencyN,
4548 cpumMsrRd_IntelI7CoreCnResidencyN,
4549 cpumMsrRd_IntelI7SandyVrCurrentConfig,
4550 cpumMsrRd_IntelI7SandyVrMiscConfig,
4551 cpumMsrRd_IntelI7SandyRaplPowerUnit,
4552 cpumMsrRd_IntelI7SandyPkgCnIrtlN,
4553 cpumMsrRd_IntelI7SandyPkgC2Residency,
4554 cpumMsrRd_IntelI7RaplPkgPowerLimit,
4555 cpumMsrRd_IntelI7RaplPkgEnergyStatus,
4556 cpumMsrRd_IntelI7RaplPkgPerfStatus,
4557 cpumMsrRd_IntelI7RaplPkgPowerInfo,
4558 cpumMsrRd_IntelI7RaplDramPowerLimit,
4559 cpumMsrRd_IntelI7RaplDramEnergyStatus,
4560 cpumMsrRd_IntelI7RaplDramPerfStatus,
4561 cpumMsrRd_IntelI7RaplDramPowerInfo,
4562 cpumMsrRd_IntelI7RaplPp0PowerLimit,
4563 cpumMsrRd_IntelI7RaplPp0EnergyStatus,
4564 cpumMsrRd_IntelI7RaplPp0Policy,
4565 cpumMsrRd_IntelI7RaplPp0PerfStatus,
4566 cpumMsrRd_IntelI7RaplPp1PowerLimit,
4567 cpumMsrRd_IntelI7RaplPp1EnergyStatus,
4568 cpumMsrRd_IntelI7RaplPp1Policy,
4569 cpumMsrRd_IntelI7IvyConfigTdpNominal,
4570 cpumMsrRd_IntelI7IvyConfigTdpLevel1,
4571 cpumMsrRd_IntelI7IvyConfigTdpLevel2,
4572 cpumMsrRd_IntelI7IvyConfigTdpControl,
4573 cpumMsrRd_IntelI7IvyTurboActivationRatio,
4574 cpumMsrRd_IntelI7UncPerfGlobalCtrl,
4575 cpumMsrRd_IntelI7UncPerfGlobalStatus,
4576 cpumMsrRd_IntelI7UncPerfGlobalOvfCtrl,
4577 cpumMsrRd_IntelI7UncPerfFixedCtrCtrl,
4578 cpumMsrRd_IntelI7UncPerfFixedCtr,
4579 cpumMsrRd_IntelI7UncCBoxConfig,
4580 cpumMsrRd_IntelI7UncArbPerfCtrN,
4581 cpumMsrRd_IntelI7UncArbPerfEvtSelN,
4582 cpumMsrRd_IntelCore2EmttmCrTablesN,
4583 cpumMsrRd_IntelCore2SmmCStMiscInfo,
4584 cpumMsrRd_IntelCore1ExtConfig,
4585 cpumMsrRd_IntelCore1DtsCalControl,
4586 cpumMsrRd_IntelCore2PeciControl,
4587
4588 cpumMsrRd_P6LastBranchFromIp,
4589 cpumMsrRd_P6LastBranchToIp,
4590 cpumMsrRd_P6LastIntFromIp,
4591 cpumMsrRd_P6LastIntToIp,
4592
4593 cpumMsrRd_AmdFam15hTscRate,
4594 cpumMsrRd_AmdFam15hLwpCfg,
4595 cpumMsrRd_AmdFam15hLwpCbAddr,
4596 cpumMsrRd_AmdFam10hMc4MiscN,
4597 cpumMsrRd_AmdK8PerfCtlN,
4598 cpumMsrRd_AmdK8PerfCtrN,
4599 cpumMsrRd_AmdK8SysCfg,
4600 cpumMsrRd_AmdK8HwCr,
4601 cpumMsrRd_AmdK8IorrBaseN,
4602 cpumMsrRd_AmdK8IorrMaskN,
4603 cpumMsrRd_AmdK8TopOfMemN,
4604 cpumMsrRd_AmdK8NbCfg1,
4605 cpumMsrRd_AmdK8McXcptRedir,
4606 cpumMsrRd_AmdK8CpuNameN,
4607 cpumMsrRd_AmdK8HwThermalCtrl,
4608 cpumMsrRd_AmdK8SwThermalCtrl,
4609 cpumMsrRd_AmdK8FidVidControl,
4610 cpumMsrRd_AmdK8FidVidStatus,
4611 cpumMsrRd_AmdK8McCtlMaskN,
4612 cpumMsrRd_AmdK8SmiOnIoTrapN,
4613 cpumMsrRd_AmdK8SmiOnIoTrapCtlSts,
4614 cpumMsrRd_AmdK8IntPendingMessage,
4615 cpumMsrRd_AmdK8SmiTriggerIoCycle,
4616 cpumMsrRd_AmdFam10hMmioCfgBaseAddr,
4617 cpumMsrRd_AmdFam10hTrapCtlMaybe,
4618 cpumMsrRd_AmdFam10hPStateCurLimit,
4619 cpumMsrRd_AmdFam10hPStateControl,
4620 cpumMsrRd_AmdFam10hPStateStatus,
4621 cpumMsrRd_AmdFam10hPStateN,
4622 cpumMsrRd_AmdFam10hCofVidControl,
4623 cpumMsrRd_AmdFam10hCofVidStatus,
4624 cpumMsrRd_AmdFam10hCStateIoBaseAddr,
4625 cpumMsrRd_AmdFam10hCpuWatchdogTimer,
4626 cpumMsrRd_AmdK8SmmBase,
4627 cpumMsrRd_AmdK8SmmAddr,
4628 cpumMsrRd_AmdK8SmmMask,
4629 cpumMsrRd_AmdK8VmCr,
4630 cpumMsrRd_AmdK8IgnNe,
4631 cpumMsrRd_AmdK8SmmCtl,
4632 cpumMsrRd_AmdK8VmHSavePa,
4633 cpumMsrRd_AmdFam10hVmLockKey,
4634 cpumMsrRd_AmdFam10hSmmLockKey,
4635 cpumMsrRd_AmdFam10hLocalSmiStatus,
4636 cpumMsrRd_AmdFam10hOsVisWrkIdLength,
4637 cpumMsrRd_AmdFam10hOsVisWrkStatus,
4638 cpumMsrRd_AmdFam16hL2IPerfCtlN,
4639 cpumMsrRd_AmdFam16hL2IPerfCtrN,
4640 cpumMsrRd_AmdFam15hNorthbridgePerfCtlN,
4641 cpumMsrRd_AmdFam15hNorthbridgePerfCtrN,
4642 cpumMsrRd_AmdK7MicrocodeCtl,
4643 cpumMsrRd_AmdK7ClusterIdMaybe,
4644 cpumMsrRd_AmdK8CpuIdCtlStd07hEbax,
4645 cpumMsrRd_AmdK8CpuIdCtlStd06hEcx,
4646 cpumMsrRd_AmdK8CpuIdCtlStd01hEdcx,
4647 cpumMsrRd_AmdK8CpuIdCtlExt01hEdcx,
4648 cpumMsrRd_AmdK8PatchLevel,
4649 cpumMsrRd_AmdK7DebugStatusMaybe,
4650 cpumMsrRd_AmdK7BHTraceBaseMaybe,
4651 cpumMsrRd_AmdK7BHTracePtrMaybe,
4652 cpumMsrRd_AmdK7BHTraceLimitMaybe,
4653 cpumMsrRd_AmdK7HardwareDebugToolCfgMaybe,
4654 cpumMsrRd_AmdK7FastFlushCountMaybe,
4655 cpumMsrRd_AmdK7NodeId,
4656 cpumMsrRd_AmdK7DrXAddrMaskN,
4657 cpumMsrRd_AmdK7Dr0DataMatchMaybe,
4658 cpumMsrRd_AmdK7Dr0DataMaskMaybe,
4659 cpumMsrRd_AmdK7LoadStoreCfg,
4660 cpumMsrRd_AmdK7InstrCacheCfg,
4661 cpumMsrRd_AmdK7DataCacheCfg,
4662 cpumMsrRd_AmdK7BusUnitCfg,
4663 cpumMsrRd_AmdK7DebugCtl2Maybe,
4664 cpumMsrRd_AmdFam15hFpuCfg,
4665 cpumMsrRd_AmdFam15hDecoderCfg,
4666 cpumMsrRd_AmdFam10hBusUnitCfg2,
4667 cpumMsrRd_AmdFam15hCombUnitCfg,
4668 cpumMsrRd_AmdFam15hCombUnitCfg2,
4669 cpumMsrRd_AmdFam15hCombUnitCfg3,
4670 cpumMsrRd_AmdFam15hExecUnitCfg,
4671 cpumMsrRd_AmdFam15hLoadStoreCfg2,
4672 cpumMsrRd_AmdFam10hIbsFetchCtl,
4673 cpumMsrRd_AmdFam10hIbsFetchLinAddr,
4674 cpumMsrRd_AmdFam10hIbsFetchPhysAddr,
4675 cpumMsrRd_AmdFam10hIbsOpExecCtl,
4676 cpumMsrRd_AmdFam10hIbsOpRip,
4677 cpumMsrRd_AmdFam10hIbsOpData,
4678 cpumMsrRd_AmdFam10hIbsOpData2,
4679 cpumMsrRd_AmdFam10hIbsOpData3,
4680 cpumMsrRd_AmdFam10hIbsDcLinAddr,
4681 cpumMsrRd_AmdFam10hIbsDcPhysAddr,
4682 cpumMsrRd_AmdFam10hIbsCtl,
4683 cpumMsrRd_AmdFam14hIbsBrTarget,
4684
4685 cpumMsrRd_Gim
4686};
4687
4688
4689/**
4690 * MSR write function table.
4691 */
4692static const PFNCPUMWRMSR g_aCpumWrMsrFns[kCpumMsrWrFn_End] =
4693{
4694 NULL, /* Invalid */
4695 cpumMsrWr_IgnoreWrite,
4696 cpumMsrWr_ReadOnly,
4697 NULL, /* Alias */
4698 cpumMsrWr_Ia32P5McAddr,
4699 cpumMsrWr_Ia32P5McType,
4700 cpumMsrWr_Ia32TimestampCounter,
4701 cpumMsrWr_Ia32ApicBase,
4702 cpumMsrWr_Ia32FeatureControl,
4703 cpumMsrWr_Ia32BiosSignId,
4704 cpumMsrWr_Ia32BiosUpdateTrigger,
4705 cpumMsrWr_Ia32SmmMonitorCtl,
4706 cpumMsrWr_Ia32PmcN,
4707 cpumMsrWr_Ia32MonitorFilterLineSize,
4708 cpumMsrWr_Ia32MPerf,
4709 cpumMsrWr_Ia32APerf,
4710 cpumMsrWr_Ia32MtrrPhysBaseN,
4711 cpumMsrWr_Ia32MtrrPhysMaskN,
4712 cpumMsrWr_Ia32MtrrFixed,
4713 cpumMsrWr_Ia32MtrrDefType,
4714 cpumMsrWr_Ia32Pat,
4715 cpumMsrWr_Ia32SysEnterCs,
4716 cpumMsrWr_Ia32SysEnterEsp,
4717 cpumMsrWr_Ia32SysEnterEip,
4718 cpumMsrWr_Ia32McgStatus,
4719 cpumMsrWr_Ia32McgCtl,
4720 cpumMsrWr_Ia32DebugCtl,
4721 cpumMsrWr_Ia32SmrrPhysBase,
4722 cpumMsrWr_Ia32SmrrPhysMask,
4723 cpumMsrWr_Ia32PlatformDcaCap,
4724 cpumMsrWr_Ia32Dca0Cap,
4725 cpumMsrWr_Ia32PerfEvtSelN,
4726 cpumMsrWr_Ia32PerfStatus,
4727 cpumMsrWr_Ia32PerfCtl,
4728 cpumMsrWr_Ia32FixedCtrN,
4729 cpumMsrWr_Ia32PerfCapabilities,
4730 cpumMsrWr_Ia32FixedCtrCtrl,
4731 cpumMsrWr_Ia32PerfGlobalStatus,
4732 cpumMsrWr_Ia32PerfGlobalCtrl,
4733 cpumMsrWr_Ia32PerfGlobalOvfCtrl,
4734 cpumMsrWr_Ia32PebsEnable,
4735 cpumMsrWr_Ia32ClockModulation,
4736 cpumMsrWr_Ia32ThermInterrupt,
4737 cpumMsrWr_Ia32ThermStatus,
4738 cpumMsrWr_Ia32Therm2Ctl,
4739 cpumMsrWr_Ia32MiscEnable,
4740 cpumMsrWr_Ia32McCtlStatusAddrMiscN,
4741 cpumMsrWr_Ia32McNCtl2,
4742 cpumMsrWr_Ia32DsArea,
4743 cpumMsrWr_Ia32TscDeadline,
4744 cpumMsrWr_Ia32X2ApicN,
4745 cpumMsrWr_Ia32DebugInterface,
4746
4747 cpumMsrWr_Amd64Efer,
4748 cpumMsrWr_Amd64SyscallTarget,
4749 cpumMsrWr_Amd64LongSyscallTarget,
4750 cpumMsrWr_Amd64CompSyscallTarget,
4751 cpumMsrWr_Amd64SyscallFlagMask,
4752 cpumMsrWr_Amd64FsBase,
4753 cpumMsrWr_Amd64GsBase,
4754 cpumMsrWr_Amd64KernelGsBase,
4755 cpumMsrWr_Amd64TscAux,
4756
4757 cpumMsrWr_IntelEblCrPowerOn,
4758 cpumMsrWr_IntelP4EbcHardPowerOn,
4759 cpumMsrWr_IntelP4EbcSoftPowerOn,
4760 cpumMsrWr_IntelP4EbcFrequencyId,
4761 cpumMsrWr_IntelFlexRatio,
4762 cpumMsrWr_IntelPkgCStConfigControl,
4763 cpumMsrWr_IntelPmgIoCaptureBase,
4764 cpumMsrWr_IntelLastBranchFromToN,
4765 cpumMsrWr_IntelLastBranchFromN,
4766 cpumMsrWr_IntelLastBranchToN,
4767 cpumMsrWr_IntelLastBranchTos,
4768 cpumMsrWr_IntelBblCrCtl,
4769 cpumMsrWr_IntelBblCrCtl3,
4770 cpumMsrWr_IntelI7TemperatureTarget,
4771 cpumMsrWr_IntelI7MsrOffCoreResponseN,
4772 cpumMsrWr_IntelI7MiscPwrMgmt,
4773 cpumMsrWr_IntelP6CrN,
4774 cpumMsrWr_IntelCpuId1FeatureMaskEcdx,
4775 cpumMsrWr_IntelCpuId1FeatureMaskEax,
4776 cpumMsrWr_IntelCpuId80000001FeatureMaskEcdx,
4777 cpumMsrWr_IntelI7SandyAesNiCtl,
4778 cpumMsrWr_IntelI7TurboRatioLimit,
4779 cpumMsrWr_IntelI7LbrSelect,
4780 cpumMsrWr_IntelI7SandyErrorControl,
4781 cpumMsrWr_IntelI7PowerCtl,
4782 cpumMsrWr_IntelI7SandyPebsNumAlt,
4783 cpumMsrWr_IntelI7PebsLdLat,
4784 cpumMsrWr_IntelI7SandyVrCurrentConfig,
4785 cpumMsrWr_IntelI7SandyVrMiscConfig,
4786 cpumMsrWr_IntelI7SandyPkgCnIrtlN,
4787 cpumMsrWr_IntelI7RaplPkgPowerLimit,
4788 cpumMsrWr_IntelI7RaplDramPowerLimit,
4789 cpumMsrWr_IntelI7RaplPp0PowerLimit,
4790 cpumMsrWr_IntelI7RaplPp0Policy,
4791 cpumMsrWr_IntelI7RaplPp1PowerLimit,
4792 cpumMsrWr_IntelI7RaplPp1Policy,
4793 cpumMsrWr_IntelI7IvyConfigTdpControl,
4794 cpumMsrWr_IntelI7IvyTurboActivationRatio,
4795 cpumMsrWr_IntelI7UncPerfGlobalCtrl,
4796 cpumMsrWr_IntelI7UncPerfGlobalStatus,
4797 cpumMsrWr_IntelI7UncPerfGlobalOvfCtrl,
4798 cpumMsrWr_IntelI7UncPerfFixedCtrCtrl,
4799 cpumMsrWr_IntelI7UncPerfFixedCtr,
4800 cpumMsrWr_IntelI7UncArbPerfCtrN,
4801 cpumMsrWr_IntelI7UncArbPerfEvtSelN,
4802 cpumMsrWr_IntelCore2EmttmCrTablesN,
4803 cpumMsrWr_IntelCore2SmmCStMiscInfo,
4804 cpumMsrWr_IntelCore1ExtConfig,
4805 cpumMsrWr_IntelCore1DtsCalControl,
4806 cpumMsrWr_IntelCore2PeciControl,
4807
4808 cpumMsrWr_P6LastIntFromIp,
4809 cpumMsrWr_P6LastIntToIp,
4810
4811 cpumMsrWr_AmdFam15hTscRate,
4812 cpumMsrWr_AmdFam15hLwpCfg,
4813 cpumMsrWr_AmdFam15hLwpCbAddr,
4814 cpumMsrWr_AmdFam10hMc4MiscN,
4815 cpumMsrWr_AmdK8PerfCtlN,
4816 cpumMsrWr_AmdK8PerfCtrN,
4817 cpumMsrWr_AmdK8SysCfg,
4818 cpumMsrWr_AmdK8HwCr,
4819 cpumMsrWr_AmdK8IorrBaseN,
4820 cpumMsrWr_AmdK8IorrMaskN,
4821 cpumMsrWr_AmdK8TopOfMemN,
4822 cpumMsrWr_AmdK8NbCfg1,
4823 cpumMsrWr_AmdK8McXcptRedir,
4824 cpumMsrWr_AmdK8CpuNameN,
4825 cpumMsrWr_AmdK8HwThermalCtrl,
4826 cpumMsrWr_AmdK8SwThermalCtrl,
4827 cpumMsrWr_AmdK8FidVidControl,
4828 cpumMsrWr_AmdK8McCtlMaskN,
4829 cpumMsrWr_AmdK8SmiOnIoTrapN,
4830 cpumMsrWr_AmdK8SmiOnIoTrapCtlSts,
4831 cpumMsrWr_AmdK8IntPendingMessage,
4832 cpumMsrWr_AmdK8SmiTriggerIoCycle,
4833 cpumMsrWr_AmdFam10hMmioCfgBaseAddr,
4834 cpumMsrWr_AmdFam10hTrapCtlMaybe,
4835 cpumMsrWr_AmdFam10hPStateControl,
4836 cpumMsrWr_AmdFam10hPStateStatus,
4837 cpumMsrWr_AmdFam10hPStateN,
4838 cpumMsrWr_AmdFam10hCofVidControl,
4839 cpumMsrWr_AmdFam10hCofVidStatus,
4840 cpumMsrWr_AmdFam10hCStateIoBaseAddr,
4841 cpumMsrWr_AmdFam10hCpuWatchdogTimer,
4842 cpumMsrWr_AmdK8SmmBase,
4843 cpumMsrWr_AmdK8SmmAddr,
4844 cpumMsrWr_AmdK8SmmMask,
4845 cpumMsrWr_AmdK8VmCr,
4846 cpumMsrWr_AmdK8IgnNe,
4847 cpumMsrWr_AmdK8SmmCtl,
4848 cpumMsrWr_AmdK8VmHSavePa,
4849 cpumMsrWr_AmdFam10hVmLockKey,
4850 cpumMsrWr_AmdFam10hSmmLockKey,
4851 cpumMsrWr_AmdFam10hLocalSmiStatus,
4852 cpumMsrWr_AmdFam10hOsVisWrkIdLength,
4853 cpumMsrWr_AmdFam10hOsVisWrkStatus,
4854 cpumMsrWr_AmdFam16hL2IPerfCtlN,
4855 cpumMsrWr_AmdFam16hL2IPerfCtrN,
4856 cpumMsrWr_AmdFam15hNorthbridgePerfCtlN,
4857 cpumMsrWr_AmdFam15hNorthbridgePerfCtrN,
4858 cpumMsrWr_AmdK7MicrocodeCtl,
4859 cpumMsrWr_AmdK7ClusterIdMaybe,
4860 cpumMsrWr_AmdK8CpuIdCtlStd07hEbax,
4861 cpumMsrWr_AmdK8CpuIdCtlStd06hEcx,
4862 cpumMsrWr_AmdK8CpuIdCtlStd01hEdcx,
4863 cpumMsrWr_AmdK8CpuIdCtlExt01hEdcx,
4864 cpumMsrWr_AmdK8PatchLoader,
4865 cpumMsrWr_AmdK7DebugStatusMaybe,
4866 cpumMsrWr_AmdK7BHTraceBaseMaybe,
4867 cpumMsrWr_AmdK7BHTracePtrMaybe,
4868 cpumMsrWr_AmdK7BHTraceLimitMaybe,
4869 cpumMsrWr_AmdK7HardwareDebugToolCfgMaybe,
4870 cpumMsrWr_AmdK7FastFlushCountMaybe,
4871 cpumMsrWr_AmdK7NodeId,
4872 cpumMsrWr_AmdK7DrXAddrMaskN,
4873 cpumMsrWr_AmdK7Dr0DataMatchMaybe,
4874 cpumMsrWr_AmdK7Dr0DataMaskMaybe,
4875 cpumMsrWr_AmdK7LoadStoreCfg,
4876 cpumMsrWr_AmdK7InstrCacheCfg,
4877 cpumMsrWr_AmdK7DataCacheCfg,
4878 cpumMsrWr_AmdK7BusUnitCfg,
4879 cpumMsrWr_AmdK7DebugCtl2Maybe,
4880 cpumMsrWr_AmdFam15hFpuCfg,
4881 cpumMsrWr_AmdFam15hDecoderCfg,
4882 cpumMsrWr_AmdFam10hBusUnitCfg2,
4883 cpumMsrWr_AmdFam15hCombUnitCfg,
4884 cpumMsrWr_AmdFam15hCombUnitCfg2,
4885 cpumMsrWr_AmdFam15hCombUnitCfg3,
4886 cpumMsrWr_AmdFam15hExecUnitCfg,
4887 cpumMsrWr_AmdFam15hLoadStoreCfg2,
4888 cpumMsrWr_AmdFam10hIbsFetchCtl,
4889 cpumMsrWr_AmdFam10hIbsFetchLinAddr,
4890 cpumMsrWr_AmdFam10hIbsFetchPhysAddr,
4891 cpumMsrWr_AmdFam10hIbsOpExecCtl,
4892 cpumMsrWr_AmdFam10hIbsOpRip,
4893 cpumMsrWr_AmdFam10hIbsOpData,
4894 cpumMsrWr_AmdFam10hIbsOpData2,
4895 cpumMsrWr_AmdFam10hIbsOpData3,
4896 cpumMsrWr_AmdFam10hIbsDcLinAddr,
4897 cpumMsrWr_AmdFam10hIbsDcPhysAddr,
4898 cpumMsrWr_AmdFam10hIbsCtl,
4899 cpumMsrWr_AmdFam14hIbsBrTarget,
4900
4901 cpumMsrWr_Gim
4902};
4903
4904
4905/**
4906 * Looks up the range for the given MSR.
4907 *
4908 * @returns Pointer to the range if found, NULL if not.
4909 * @param pVM The cross context VM structure.
4910 * @param idMsr The MSR to look up.
4911 */
4912# ifndef IN_RING3
4913static
4914# endif
4915PCPUMMSRRANGE cpumLookupMsrRange(PVM pVM, uint32_t idMsr)
4916{
4917 /*
4918 * Binary lookup.
4919 */
4920 uint32_t cRanges = pVM->cpum.s.GuestInfo.cMsrRanges;
4921 if (!cRanges)
4922 return NULL;
4923 PCPUMMSRRANGE paRanges = pVM->cpum.s.GuestInfo.CTX_SUFF(paMsrRanges);
4924 for (;;)
4925 {
4926 uint32_t i = cRanges / 2;
4927 if (idMsr < paRanges[i].uFirst)
4928 {
4929 if (i == 0)
4930 break;
4931 cRanges = i;
4932 }
4933 else if (idMsr > paRanges[i].uLast)
4934 {
4935 i++;
4936 if (i >= cRanges)
4937 break;
4938 cRanges -= i;
4939 paRanges = &paRanges[i];
4940 }
4941 else
4942 {
4943 if (paRanges[i].enmRdFn == kCpumMsrRdFn_MsrAlias)
4944 return cpumLookupMsrRange(pVM, paRanges[i].uValue);
4945 return &paRanges[i];
4946 }
4947 }
4948
4949# ifdef VBOX_STRICT
4950 /*
4951 * Linear lookup to verify the above binary search.
4952 */
4953 uint32_t cLeft = pVM->cpum.s.GuestInfo.cMsrRanges;
4954 PCPUMMSRRANGE pCur = pVM->cpum.s.GuestInfo.CTX_SUFF(paMsrRanges);
4955 while (cLeft-- > 0)
4956 {
4957 if (idMsr >= pCur->uFirst && idMsr <= pCur->uLast)
4958 {
4959 AssertFailed();
4960 if (pCur->enmRdFn == kCpumMsrRdFn_MsrAlias)
4961 return cpumLookupMsrRange(pVM, pCur->uValue);
4962 return pCur;
4963 }
4964 pCur++;
4965 }
4966# endif
4967 return NULL;
4968}
4969
4970
4971/**
4972 * Query a guest MSR.
4973 *
4974 * The caller is responsible for checking privilege if the call is the result of
4975 * a RDMSR instruction. We'll do the rest.
4976 *
4977 * @retval VINF_SUCCESS on success.
4978 * @retval VINF_CPUM_R3_MSR_READ if the MSR read could not be serviced in the
4979 * current context (raw-mode or ring-0).
4980 * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR), the caller is
4981 * expected to take the appropriate actions. @a *puValue is set to 0.
4982 * @param pVCpu Pointer to the VMCPU.
4983 * @param idMsr The MSR.
4984 * @param puValue Where to return the value.
4985 *
4986 * @remarks This will always return the right values, even when we're in the
4987 * recompiler.
4988 */
4989VMMDECL(VBOXSTRICTRC) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue)
4990{
4991 *puValue = 0;
4992
4993 VBOXSTRICTRC rcStrict;
4994 PVM pVM = pVCpu->CTX_SUFF(pVM);
4995 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, idMsr);
4996 if (pRange)
4997 {
4998 CPUMMSRRDFN enmRdFn = (CPUMMSRRDFN)pRange->enmRdFn;
4999 AssertReturn(enmRdFn > kCpumMsrRdFn_Invalid && enmRdFn < kCpumMsrRdFn_End, VERR_CPUM_IPE_1);
5000
5001 PFNCPUMRDMSR pfnRdMsr = g_aCpumRdMsrFns[enmRdFn];
5002 AssertReturn(pfnRdMsr, VERR_CPUM_IPE_2);
5003
5004 STAM_COUNTER_INC(&pRange->cReads);
5005 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReads);
5006
5007 rcStrict = pfnRdMsr(pVCpu, idMsr, pRange, puValue);
5008 if (rcStrict == VINF_SUCCESS)
5009 Log2(("CPUM: RDMSR %#x (%s) -> %#llx\n", idMsr, pRange->szName, *puValue));
5010 else if (rcStrict == VERR_CPUM_RAISE_GP_0)
5011 {
5012 Log(("CPUM: RDMSR %#x (%s) -> #GP(0)\n", idMsr, pRange->szName));
5013 STAM_COUNTER_INC(&pRange->cGps);
5014 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReadsRaiseGp);
5015 }
5016#ifndef IN_RING3
5017 else if (rcStrict == VINF_CPUM_R3_MSR_READ)
5018 Log(("CPUM: RDMSR %#x (%s) -> ring-3\n", idMsr, pRange->szName));
5019#endif
5020 else
5021 {
5022 Log(("CPUM: RDMSR %#x (%s) -> rcStrict=%Rrc\n", idMsr, pRange->szName, VBOXSTRICTRC_VAL(rcStrict)));
5023 AssertMsgStmt(RT_FAILURE_NP(rcStrict), ("%Rrc idMsr=%#x\n", VBOXSTRICTRC_VAL(rcStrict), idMsr),
5024 rcStrict = VERR_IPE_UNEXPECTED_INFO_STATUS);
5025 Assert(rcStrict != VERR_EM_INTERPRETER);
5026 }
5027 }
5028 else
5029 {
5030 Log(("CPUM: Unknown RDMSR %#x -> #GP(0)\n", idMsr));
5031 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReads);
5032 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReadsUnknown);
5033 rcStrict = VERR_CPUM_RAISE_GP_0;
5034 }
5035 return rcStrict;
5036}
5037
5038
5039/**
5040 * Writes to a guest MSR.
5041 *
5042 * The caller is responsible for checking privilege if the call is the result of
5043 * a WRMSR instruction. We'll do the rest.
5044 *
5045 * @retval VINF_SUCCESS on success.
5046 * @retval VINF_CPUM_R3_MSR_WRITE if the MSR write could not be serviced in the
5047 * current context (raw-mode or ring-0).
5048 * @retval VERR_CPUM_RAISE_GP_0 on failure, the caller is expected to take the
5049 * appropriate actions.
5050 *
5051 * @param pVCpu Pointer to the VMCPU.
5052 * @param idMsr The MSR id.
5053 * @param uValue The value to set.
5054 *
5055 * @remarks Everyone changing MSR values, including the recompiler, shall do it
5056 * by calling this method. This makes sure we have current values and
5057 * that we trigger all the right actions when something changes.
5058 *
5059 * For performance reasons, this actually isn't entirely true for some
5060 * MSRs when in HM mode. The code here and in HM must be aware of
5061 * this.
5062 */
5063VMMDECL(VBOXSTRICTRC) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue)
5064{
5065 VBOXSTRICTRC rcStrict;
5066 PVM pVM = pVCpu->CTX_SUFF(pVM);
5067 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, idMsr);
5068 if (pRange)
5069 {
5070 STAM_COUNTER_INC(&pRange->cWrites);
5071 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWrites);
5072
5073 if (!(uValue & pRange->fWrGpMask))
5074 {
5075 CPUMMSRWRFN enmWrFn = (CPUMMSRWRFN)pRange->enmWrFn;
5076 AssertReturn(enmWrFn > kCpumMsrWrFn_Invalid && enmWrFn < kCpumMsrWrFn_End, VERR_CPUM_IPE_1);
5077
5078 PFNCPUMWRMSR pfnWrMsr = g_aCpumWrMsrFns[enmWrFn];
5079 AssertReturn(pfnWrMsr, VERR_CPUM_IPE_2);
5080
5081 uint64_t uValueAdjusted = uValue & ~pRange->fWrIgnMask;
5082 if (uValueAdjusted != uValue)
5083 {
5084 STAM_COUNTER_INC(&pRange->cIgnoredBits);
5085 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesToIgnoredBits);
5086 }
5087
5088 rcStrict = pfnWrMsr(pVCpu, idMsr, pRange, uValueAdjusted, uValue);
5089 if (rcStrict == VINF_SUCCESS)
5090 Log2(("CPUM: WRMSR %#x (%s), %#llx [%#llx]\n", idMsr, pRange->szName, uValueAdjusted, uValue));
5091 else if (rcStrict == VERR_CPUM_RAISE_GP_0)
5092 {
5093 Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> #GP(0)\n", idMsr, pRange->szName, uValueAdjusted, uValue));
5094 STAM_COUNTER_INC(&pRange->cGps);
5095 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesRaiseGp);
5096 }
5097#ifndef IN_RING3
5098 else if (rcStrict == VINF_CPUM_R3_MSR_WRITE)
5099 Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> ring-3\n", idMsr, pRange->szName, uValueAdjusted, uValue));
5100#endif
5101 else
5102 {
5103 Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> rcStrict=%Rrc\n",
5104 idMsr, pRange->szName, uValueAdjusted, uValue, VBOXSTRICTRC_VAL(rcStrict)));
5105 AssertMsgStmt(RT_FAILURE_NP(rcStrict), ("%Rrc idMsr=%#x\n", VBOXSTRICTRC_VAL(rcStrict), idMsr),
5106 rcStrict = VERR_IPE_UNEXPECTED_INFO_STATUS);
5107 Assert(rcStrict != VERR_EM_INTERPRETER);
5108 }
5109 }
5110 else
5111 {
5112 Log(("CPUM: WRMSR %#x (%s), %#llx -> #GP(0) - invalid bits %#llx\n",
5113 idMsr, pRange->szName, uValue, uValue & pRange->fWrGpMask));
5114 STAM_COUNTER_INC(&pRange->cGps);
5115 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesRaiseGp);
5116 rcStrict = VERR_CPUM_RAISE_GP_0;
5117 }
5118 }
5119 else
5120 {
5121 Log(("CPUM: Unknown WRMSR %#x, %#llx -> #GP(0)\n", idMsr, uValue));
5122 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWrites);
5123 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesUnknown);
5124 rcStrict = VERR_CPUM_RAISE_GP_0;
5125 }
5126 return rcStrict;
5127}
5128
5129
5130#if defined(VBOX_STRICT) && defined(IN_RING3)
5131/**
5132 * Performs some checks on the static data related to MSRs.
5133 *
5134 * @returns VINF_SUCCESS on success, error on failure.
5135 */
5136int cpumR3MsrStrictInitChecks(void)
5137{
5138#define CPUM_ASSERT_RD_MSR_FN(a_Register) \
5139 AssertReturn(g_aCpumRdMsrFns[kCpumMsrRdFn_##a_Register] == cpumMsrRd_##a_Register, VERR_CPUM_IPE_2);
5140#define CPUM_ASSERT_WR_MSR_FN(a_Register) \
5141 AssertReturn(g_aCpumWrMsrFns[kCpumMsrWrFn_##a_Register] == cpumMsrWr_##a_Register, VERR_CPUM_IPE_2);
5142
5143 AssertReturn(g_aCpumRdMsrFns[kCpumMsrRdFn_Invalid] == NULL, VERR_CPUM_IPE_2);
5144 CPUM_ASSERT_RD_MSR_FN(FixedValue);
5145 CPUM_ASSERT_RD_MSR_FN(WriteOnly);
5146 CPUM_ASSERT_RD_MSR_FN(Ia32P5McAddr);
5147 CPUM_ASSERT_RD_MSR_FN(Ia32P5McType);
5148 CPUM_ASSERT_RD_MSR_FN(Ia32TimestampCounter);
5149 CPUM_ASSERT_RD_MSR_FN(Ia32PlatformId);
5150 CPUM_ASSERT_RD_MSR_FN(Ia32ApicBase);
5151 CPUM_ASSERT_RD_MSR_FN(Ia32FeatureControl);
5152 CPUM_ASSERT_RD_MSR_FN(Ia32BiosSignId);
5153 CPUM_ASSERT_RD_MSR_FN(Ia32SmmMonitorCtl);
5154 CPUM_ASSERT_RD_MSR_FN(Ia32PmcN);
5155 CPUM_ASSERT_RD_MSR_FN(Ia32MonitorFilterLineSize);
5156 CPUM_ASSERT_RD_MSR_FN(Ia32MPerf);
5157 CPUM_ASSERT_RD_MSR_FN(Ia32APerf);
5158 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrCap);
5159 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrPhysBaseN);
5160 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrPhysMaskN);
5161 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrFixed);
5162 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrDefType);
5163 CPUM_ASSERT_RD_MSR_FN(Ia32Pat);
5164 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterCs);
5165 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterEsp);
5166 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterEip);
5167 CPUM_ASSERT_RD_MSR_FN(Ia32McgCap);
5168 CPUM_ASSERT_RD_MSR_FN(Ia32McgStatus);
5169 CPUM_ASSERT_RD_MSR_FN(Ia32McgCtl);
5170 CPUM_ASSERT_RD_MSR_FN(Ia32DebugCtl);
5171 CPUM_ASSERT_RD_MSR_FN(Ia32SmrrPhysBase);
5172 CPUM_ASSERT_RD_MSR_FN(Ia32SmrrPhysMask);
5173 CPUM_ASSERT_RD_MSR_FN(Ia32PlatformDcaCap);
5174 CPUM_ASSERT_RD_MSR_FN(Ia32CpuDcaCap);
5175 CPUM_ASSERT_RD_MSR_FN(Ia32Dca0Cap);
5176 CPUM_ASSERT_RD_MSR_FN(Ia32PerfEvtSelN);
5177 CPUM_ASSERT_RD_MSR_FN(Ia32PerfStatus);
5178 CPUM_ASSERT_RD_MSR_FN(Ia32PerfCtl);
5179 CPUM_ASSERT_RD_MSR_FN(Ia32FixedCtrN);
5180 CPUM_ASSERT_RD_MSR_FN(Ia32PerfCapabilities);
5181 CPUM_ASSERT_RD_MSR_FN(Ia32FixedCtrCtrl);
5182 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalStatus);
5183 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalCtrl);
5184 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalOvfCtrl);
5185 CPUM_ASSERT_RD_MSR_FN(Ia32PebsEnable);
5186 CPUM_ASSERT_RD_MSR_FN(Ia32ClockModulation);
5187 CPUM_ASSERT_RD_MSR_FN(Ia32ThermInterrupt);
5188 CPUM_ASSERT_RD_MSR_FN(Ia32ThermStatus);
5189 CPUM_ASSERT_RD_MSR_FN(Ia32MiscEnable);
5190 CPUM_ASSERT_RD_MSR_FN(Ia32McCtlStatusAddrMiscN);
5191 CPUM_ASSERT_RD_MSR_FN(Ia32McNCtl2);
5192 CPUM_ASSERT_RD_MSR_FN(Ia32DsArea);
5193 CPUM_ASSERT_RD_MSR_FN(Ia32TscDeadline);
5194 CPUM_ASSERT_RD_MSR_FN(Ia32X2ApicN);
5195 CPUM_ASSERT_RD_MSR_FN(Ia32DebugInterface);
5196 CPUM_ASSERT_RD_MSR_FN(Ia32VmxBase);
5197 CPUM_ASSERT_RD_MSR_FN(Ia32VmxPinbasedCtls);
5198 CPUM_ASSERT_RD_MSR_FN(Ia32VmxProcbasedCtls);
5199 CPUM_ASSERT_RD_MSR_FN(Ia32VmxExitCtls);
5200 CPUM_ASSERT_RD_MSR_FN(Ia32VmxEntryCtls);
5201 CPUM_ASSERT_RD_MSR_FN(Ia32VmxMisc);
5202 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr0Fixed0);
5203 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr0Fixed1);
5204 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr4Fixed0);
5205 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr4Fixed1);
5206 CPUM_ASSERT_RD_MSR_FN(Ia32VmxVmcsEnum);
5207 CPUM_ASSERT_RD_MSR_FN(Ia32VmxProcBasedCtls2);
5208 CPUM_ASSERT_RD_MSR_FN(Ia32VmxEptVpidCap);
5209 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTruePinbasedCtls);
5210 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueProcbasedCtls);
5211 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueExitCtls);
5212 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueEntryCtls);
5213
5214 CPUM_ASSERT_RD_MSR_FN(Amd64Efer);
5215 CPUM_ASSERT_RD_MSR_FN(Amd64SyscallTarget);
5216 CPUM_ASSERT_RD_MSR_FN(Amd64LongSyscallTarget);
5217 CPUM_ASSERT_RD_MSR_FN(Amd64CompSyscallTarget);
5218 CPUM_ASSERT_RD_MSR_FN(Amd64SyscallFlagMask);
5219 CPUM_ASSERT_RD_MSR_FN(Amd64FsBase);
5220 CPUM_ASSERT_RD_MSR_FN(Amd64GsBase);
5221 CPUM_ASSERT_RD_MSR_FN(Amd64KernelGsBase);
5222 CPUM_ASSERT_RD_MSR_FN(Amd64TscAux);
5223
5224 CPUM_ASSERT_RD_MSR_FN(IntelEblCrPowerOn);
5225 CPUM_ASSERT_RD_MSR_FN(IntelI7CoreThreadCount);
5226 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcHardPowerOn);
5227 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcSoftPowerOn);
5228 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcFrequencyId);
5229 CPUM_ASSERT_RD_MSR_FN(IntelP6FsbFrequency);
5230 CPUM_ASSERT_RD_MSR_FN(IntelPlatformInfo);
5231 CPUM_ASSERT_RD_MSR_FN(IntelFlexRatio);
5232 CPUM_ASSERT_RD_MSR_FN(IntelPkgCStConfigControl);
5233 CPUM_ASSERT_RD_MSR_FN(IntelPmgIoCaptureBase);
5234 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchFromToN);
5235 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchFromN);
5236 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchToN);
5237 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchTos);
5238 CPUM_ASSERT_RD_MSR_FN(IntelBblCrCtl);
5239 CPUM_ASSERT_RD_MSR_FN(IntelBblCrCtl3);
5240 CPUM_ASSERT_RD_MSR_FN(IntelI7TemperatureTarget);
5241 CPUM_ASSERT_RD_MSR_FN(IntelI7MsrOffCoreResponseN);
5242 CPUM_ASSERT_RD_MSR_FN(IntelI7MiscPwrMgmt);
5243 CPUM_ASSERT_RD_MSR_FN(IntelP6CrN);
5244 CPUM_ASSERT_RD_MSR_FN(IntelCpuId1FeatureMaskEcdx);
5245 CPUM_ASSERT_RD_MSR_FN(IntelCpuId1FeatureMaskEax);
5246 CPUM_ASSERT_RD_MSR_FN(IntelCpuId80000001FeatureMaskEcdx);
5247 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyAesNiCtl);
5248 CPUM_ASSERT_RD_MSR_FN(IntelI7TurboRatioLimit);
5249 CPUM_ASSERT_RD_MSR_FN(IntelI7LbrSelect);
5250 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyErrorControl);
5251 CPUM_ASSERT_RD_MSR_FN(IntelI7VirtualLegacyWireCap);
5252 CPUM_ASSERT_RD_MSR_FN(IntelI7PowerCtl);
5253 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPebsNumAlt);
5254 CPUM_ASSERT_RD_MSR_FN(IntelI7PebsLdLat);
5255 CPUM_ASSERT_RD_MSR_FN(IntelI7PkgCnResidencyN);
5256 CPUM_ASSERT_RD_MSR_FN(IntelI7CoreCnResidencyN);
5257 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyVrCurrentConfig);
5258 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyVrMiscConfig);
5259 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyRaplPowerUnit);
5260 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPkgCnIrtlN);
5261 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPkgC2Residency);
5262 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPowerLimit);
5263 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgEnergyStatus);
5264 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPerfStatus);
5265 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPowerInfo);
5266 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPowerLimit);
5267 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramEnergyStatus);
5268 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPerfStatus);
5269 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPowerInfo);
5270 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0PowerLimit);
5271 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0EnergyStatus);
5272 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0Policy);
5273 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0PerfStatus);
5274 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1PowerLimit);
5275 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1EnergyStatus);
5276 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1Policy);
5277 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpNominal);
5278 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpLevel1);
5279 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpLevel2);
5280 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpControl);
5281 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyTurboActivationRatio);
5282 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalCtrl);
5283 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalStatus);
5284 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalOvfCtrl);
5285 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfFixedCtrCtrl);
5286 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfFixedCtr);
5287 CPUM_ASSERT_RD_MSR_FN(IntelI7UncCBoxConfig);
5288 CPUM_ASSERT_RD_MSR_FN(IntelI7UncArbPerfCtrN);
5289 CPUM_ASSERT_RD_MSR_FN(IntelI7UncArbPerfEvtSelN);
5290 CPUM_ASSERT_RD_MSR_FN(IntelCore2EmttmCrTablesN);
5291 CPUM_ASSERT_RD_MSR_FN(IntelCore2SmmCStMiscInfo);
5292 CPUM_ASSERT_RD_MSR_FN(IntelCore1ExtConfig);
5293 CPUM_ASSERT_RD_MSR_FN(IntelCore1DtsCalControl);
5294 CPUM_ASSERT_RD_MSR_FN(IntelCore2PeciControl);
5295
5296 CPUM_ASSERT_RD_MSR_FN(P6LastBranchFromIp);
5297 CPUM_ASSERT_RD_MSR_FN(P6LastBranchToIp);
5298 CPUM_ASSERT_RD_MSR_FN(P6LastIntFromIp);
5299 CPUM_ASSERT_RD_MSR_FN(P6LastIntToIp);
5300
5301 CPUM_ASSERT_RD_MSR_FN(AmdFam15hTscRate);
5302 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLwpCfg);
5303 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLwpCbAddr);
5304 CPUM_ASSERT_RD_MSR_FN(AmdFam10hMc4MiscN);
5305 CPUM_ASSERT_RD_MSR_FN(AmdK8PerfCtlN);
5306 CPUM_ASSERT_RD_MSR_FN(AmdK8PerfCtrN);
5307 CPUM_ASSERT_RD_MSR_FN(AmdK8SysCfg);
5308 CPUM_ASSERT_RD_MSR_FN(AmdK8HwCr);
5309 CPUM_ASSERT_RD_MSR_FN(AmdK8IorrBaseN);
5310 CPUM_ASSERT_RD_MSR_FN(AmdK8IorrMaskN);
5311 CPUM_ASSERT_RD_MSR_FN(AmdK8TopOfMemN);
5312 CPUM_ASSERT_RD_MSR_FN(AmdK8NbCfg1);
5313 CPUM_ASSERT_RD_MSR_FN(AmdK8McXcptRedir);
5314 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuNameN);
5315 CPUM_ASSERT_RD_MSR_FN(AmdK8HwThermalCtrl);
5316 CPUM_ASSERT_RD_MSR_FN(AmdK8SwThermalCtrl);
5317 CPUM_ASSERT_RD_MSR_FN(AmdK8FidVidControl);
5318 CPUM_ASSERT_RD_MSR_FN(AmdK8FidVidStatus);
5319 CPUM_ASSERT_RD_MSR_FN(AmdK8McCtlMaskN);
5320 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiOnIoTrapN);
5321 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiOnIoTrapCtlSts);
5322 CPUM_ASSERT_RD_MSR_FN(AmdK8IntPendingMessage);
5323 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiTriggerIoCycle);
5324 CPUM_ASSERT_RD_MSR_FN(AmdFam10hMmioCfgBaseAddr);
5325 CPUM_ASSERT_RD_MSR_FN(AmdFam10hTrapCtlMaybe);
5326 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateCurLimit);
5327 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateControl);
5328 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateStatus);
5329 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateN);
5330 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCofVidControl);
5331 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCofVidStatus);
5332 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCStateIoBaseAddr);
5333 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCpuWatchdogTimer);
5334 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmBase);
5335 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmAddr);
5336 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmMask);
5337 CPUM_ASSERT_RD_MSR_FN(AmdK8VmCr);
5338 CPUM_ASSERT_RD_MSR_FN(AmdK8IgnNe);
5339 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmCtl);
5340 CPUM_ASSERT_RD_MSR_FN(AmdK8VmHSavePa);
5341 CPUM_ASSERT_RD_MSR_FN(AmdFam10hVmLockKey);
5342 CPUM_ASSERT_RD_MSR_FN(AmdFam10hSmmLockKey);
5343 CPUM_ASSERT_RD_MSR_FN(AmdFam10hLocalSmiStatus);
5344 CPUM_ASSERT_RD_MSR_FN(AmdFam10hOsVisWrkIdLength);
5345 CPUM_ASSERT_RD_MSR_FN(AmdFam10hOsVisWrkStatus);
5346 CPUM_ASSERT_RD_MSR_FN(AmdFam16hL2IPerfCtlN);
5347 CPUM_ASSERT_RD_MSR_FN(AmdFam16hL2IPerfCtrN);
5348 CPUM_ASSERT_RD_MSR_FN(AmdFam15hNorthbridgePerfCtlN);
5349 CPUM_ASSERT_RD_MSR_FN(AmdFam15hNorthbridgePerfCtrN);
5350 CPUM_ASSERT_RD_MSR_FN(AmdK7MicrocodeCtl);
5351 CPUM_ASSERT_RD_MSR_FN(AmdK7ClusterIdMaybe);
5352 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd07hEbax);
5353 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd06hEcx);
5354 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd01hEdcx);
5355 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlExt01hEdcx);
5356 CPUM_ASSERT_RD_MSR_FN(AmdK8PatchLevel);
5357 CPUM_ASSERT_RD_MSR_FN(AmdK7DebugStatusMaybe);
5358 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTraceBaseMaybe);
5359 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTracePtrMaybe);
5360 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTraceLimitMaybe);
5361 CPUM_ASSERT_RD_MSR_FN(AmdK7HardwareDebugToolCfgMaybe);
5362 CPUM_ASSERT_RD_MSR_FN(AmdK7FastFlushCountMaybe);
5363 CPUM_ASSERT_RD_MSR_FN(AmdK7NodeId);
5364 CPUM_ASSERT_RD_MSR_FN(AmdK7DrXAddrMaskN);
5365 CPUM_ASSERT_RD_MSR_FN(AmdK7Dr0DataMatchMaybe);
5366 CPUM_ASSERT_RD_MSR_FN(AmdK7Dr0DataMaskMaybe);
5367 CPUM_ASSERT_RD_MSR_FN(AmdK7LoadStoreCfg);
5368 CPUM_ASSERT_RD_MSR_FN(AmdK7InstrCacheCfg);
5369 CPUM_ASSERT_RD_MSR_FN(AmdK7DataCacheCfg);
5370 CPUM_ASSERT_RD_MSR_FN(AmdK7BusUnitCfg);
5371 CPUM_ASSERT_RD_MSR_FN(AmdK7DebugCtl2Maybe);
5372 CPUM_ASSERT_RD_MSR_FN(AmdFam15hFpuCfg);
5373 CPUM_ASSERT_RD_MSR_FN(AmdFam15hDecoderCfg);
5374 CPUM_ASSERT_RD_MSR_FN(AmdFam10hBusUnitCfg2);
5375 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg);
5376 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg2);
5377 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg3);
5378 CPUM_ASSERT_RD_MSR_FN(AmdFam15hExecUnitCfg);
5379 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLoadStoreCfg2);
5380 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchCtl);
5381 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchLinAddr);
5382 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchPhysAddr);
5383 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpExecCtl);
5384 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpRip);
5385 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData);
5386 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData2);
5387 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData3);
5388 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsDcLinAddr);
5389 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsDcPhysAddr);
5390 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsCtl);
5391 CPUM_ASSERT_RD_MSR_FN(AmdFam14hIbsBrTarget);
5392
5393 CPUM_ASSERT_RD_MSR_FN(Gim)
5394
5395 AssertReturn(g_aCpumWrMsrFns[kCpumMsrWrFn_Invalid] == NULL, VERR_CPUM_IPE_2);
5396 CPUM_ASSERT_WR_MSR_FN(Ia32P5McAddr);
5397 CPUM_ASSERT_WR_MSR_FN(Ia32P5McType);
5398 CPUM_ASSERT_WR_MSR_FN(Ia32TimestampCounter);
5399 CPUM_ASSERT_WR_MSR_FN(Ia32ApicBase);
5400 CPUM_ASSERT_WR_MSR_FN(Ia32FeatureControl);
5401 CPUM_ASSERT_WR_MSR_FN(Ia32BiosSignId);
5402 CPUM_ASSERT_WR_MSR_FN(Ia32BiosUpdateTrigger);
5403 CPUM_ASSERT_WR_MSR_FN(Ia32SmmMonitorCtl);
5404 CPUM_ASSERT_WR_MSR_FN(Ia32PmcN);
5405 CPUM_ASSERT_WR_MSR_FN(Ia32MonitorFilterLineSize);
5406 CPUM_ASSERT_WR_MSR_FN(Ia32MPerf);
5407 CPUM_ASSERT_WR_MSR_FN(Ia32APerf);
5408 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrPhysBaseN);
5409 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrPhysMaskN);
5410 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrFixed);
5411 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrDefType);
5412 CPUM_ASSERT_WR_MSR_FN(Ia32Pat);
5413 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterCs);
5414 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterEsp);
5415 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterEip);
5416 CPUM_ASSERT_WR_MSR_FN(Ia32McgStatus);
5417 CPUM_ASSERT_WR_MSR_FN(Ia32McgCtl);
5418 CPUM_ASSERT_WR_MSR_FN(Ia32DebugCtl);
5419 CPUM_ASSERT_WR_MSR_FN(Ia32SmrrPhysBase);
5420 CPUM_ASSERT_WR_MSR_FN(Ia32SmrrPhysMask);
5421 CPUM_ASSERT_WR_MSR_FN(Ia32PlatformDcaCap);
5422 CPUM_ASSERT_WR_MSR_FN(Ia32Dca0Cap);
5423 CPUM_ASSERT_WR_MSR_FN(Ia32PerfEvtSelN);
5424 CPUM_ASSERT_WR_MSR_FN(Ia32PerfStatus);
5425 CPUM_ASSERT_WR_MSR_FN(Ia32PerfCtl);
5426 CPUM_ASSERT_WR_MSR_FN(Ia32FixedCtrN);
5427 CPUM_ASSERT_WR_MSR_FN(Ia32PerfCapabilities);
5428 CPUM_ASSERT_WR_MSR_FN(Ia32FixedCtrCtrl);
5429 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalStatus);
5430 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalCtrl);
5431 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalOvfCtrl);
5432 CPUM_ASSERT_WR_MSR_FN(Ia32PebsEnable);
5433 CPUM_ASSERT_WR_MSR_FN(Ia32ClockModulation);
5434 CPUM_ASSERT_WR_MSR_FN(Ia32ThermInterrupt);
5435 CPUM_ASSERT_WR_MSR_FN(Ia32ThermStatus);
5436 CPUM_ASSERT_WR_MSR_FN(Ia32MiscEnable);
5437 CPUM_ASSERT_WR_MSR_FN(Ia32McCtlStatusAddrMiscN);
5438 CPUM_ASSERT_WR_MSR_FN(Ia32McNCtl2);
5439 CPUM_ASSERT_WR_MSR_FN(Ia32DsArea);
5440 CPUM_ASSERT_WR_MSR_FN(Ia32TscDeadline);
5441 CPUM_ASSERT_WR_MSR_FN(Ia32X2ApicN);
5442 CPUM_ASSERT_WR_MSR_FN(Ia32DebugInterface);
5443
5444 CPUM_ASSERT_WR_MSR_FN(Amd64Efer);
5445 CPUM_ASSERT_WR_MSR_FN(Amd64SyscallTarget);
5446 CPUM_ASSERT_WR_MSR_FN(Amd64LongSyscallTarget);
5447 CPUM_ASSERT_WR_MSR_FN(Amd64CompSyscallTarget);
5448 CPUM_ASSERT_WR_MSR_FN(Amd64SyscallFlagMask);
5449 CPUM_ASSERT_WR_MSR_FN(Amd64FsBase);
5450 CPUM_ASSERT_WR_MSR_FN(Amd64GsBase);
5451 CPUM_ASSERT_WR_MSR_FN(Amd64KernelGsBase);
5452 CPUM_ASSERT_WR_MSR_FN(Amd64TscAux);
5453
5454 CPUM_ASSERT_WR_MSR_FN(IntelEblCrPowerOn);
5455 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcHardPowerOn);
5456 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcSoftPowerOn);
5457 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcFrequencyId);
5458 CPUM_ASSERT_WR_MSR_FN(IntelFlexRatio);
5459 CPUM_ASSERT_WR_MSR_FN(IntelPkgCStConfigControl);
5460 CPUM_ASSERT_WR_MSR_FN(IntelPmgIoCaptureBase);
5461 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchFromToN);
5462 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchFromN);
5463 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchToN);
5464 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchTos);
5465 CPUM_ASSERT_WR_MSR_FN(IntelBblCrCtl);
5466 CPUM_ASSERT_WR_MSR_FN(IntelBblCrCtl3);
5467 CPUM_ASSERT_WR_MSR_FN(IntelI7TemperatureTarget);
5468 CPUM_ASSERT_WR_MSR_FN(IntelI7MsrOffCoreResponseN);
5469 CPUM_ASSERT_WR_MSR_FN(IntelI7MiscPwrMgmt);
5470 CPUM_ASSERT_WR_MSR_FN(IntelP6CrN);
5471 CPUM_ASSERT_WR_MSR_FN(IntelCpuId1FeatureMaskEcdx);
5472 CPUM_ASSERT_WR_MSR_FN(IntelCpuId1FeatureMaskEax);
5473 CPUM_ASSERT_WR_MSR_FN(IntelCpuId80000001FeatureMaskEcdx);
5474 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyAesNiCtl);
5475 CPUM_ASSERT_WR_MSR_FN(IntelI7TurboRatioLimit);
5476 CPUM_ASSERT_WR_MSR_FN(IntelI7LbrSelect);
5477 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyErrorControl);
5478 CPUM_ASSERT_WR_MSR_FN(IntelI7PowerCtl);
5479 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPebsNumAlt);
5480 CPUM_ASSERT_WR_MSR_FN(IntelI7PebsLdLat);
5481 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyVrCurrentConfig);
5482 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyVrMiscConfig);
5483 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPkgCnIrtlN);
5484 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPkgPowerLimit);
5485 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplDramPowerLimit);
5486 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp0PowerLimit);
5487 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp0Policy);
5488 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp1PowerLimit);
5489 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp1Policy);
5490 CPUM_ASSERT_WR_MSR_FN(IntelI7IvyConfigTdpControl);
5491 CPUM_ASSERT_WR_MSR_FN(IntelI7IvyTurboActivationRatio);
5492 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalCtrl);
5493 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalStatus);
5494 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalOvfCtrl);
5495 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfFixedCtrCtrl);
5496 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfFixedCtr);
5497 CPUM_ASSERT_WR_MSR_FN(IntelI7UncArbPerfCtrN);
5498 CPUM_ASSERT_WR_MSR_FN(IntelI7UncArbPerfEvtSelN);
5499 CPUM_ASSERT_WR_MSR_FN(IntelCore2EmttmCrTablesN);
5500 CPUM_ASSERT_WR_MSR_FN(IntelCore2SmmCStMiscInfo);
5501 CPUM_ASSERT_WR_MSR_FN(IntelCore1ExtConfig);
5502 CPUM_ASSERT_WR_MSR_FN(IntelCore1DtsCalControl);
5503 CPUM_ASSERT_WR_MSR_FN(IntelCore2PeciControl);
5504
5505 CPUM_ASSERT_WR_MSR_FN(P6LastIntFromIp);
5506 CPUM_ASSERT_WR_MSR_FN(P6LastIntToIp);
5507
5508 CPUM_ASSERT_WR_MSR_FN(AmdFam15hTscRate);
5509 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLwpCfg);
5510 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLwpCbAddr);
5511 CPUM_ASSERT_WR_MSR_FN(AmdFam10hMc4MiscN);
5512 CPUM_ASSERT_WR_MSR_FN(AmdK8PerfCtlN);
5513 CPUM_ASSERT_WR_MSR_FN(AmdK8PerfCtrN);
5514 CPUM_ASSERT_WR_MSR_FN(AmdK8SysCfg);
5515 CPUM_ASSERT_WR_MSR_FN(AmdK8HwCr);
5516 CPUM_ASSERT_WR_MSR_FN(AmdK8IorrBaseN);
5517 CPUM_ASSERT_WR_MSR_FN(AmdK8IorrMaskN);
5518 CPUM_ASSERT_WR_MSR_FN(AmdK8TopOfMemN);
5519 CPUM_ASSERT_WR_MSR_FN(AmdK8NbCfg1);
5520 CPUM_ASSERT_WR_MSR_FN(AmdK8McXcptRedir);
5521 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuNameN);
5522 CPUM_ASSERT_WR_MSR_FN(AmdK8HwThermalCtrl);
5523 CPUM_ASSERT_WR_MSR_FN(AmdK8SwThermalCtrl);
5524 CPUM_ASSERT_WR_MSR_FN(AmdK8FidVidControl);
5525 CPUM_ASSERT_WR_MSR_FN(AmdK8McCtlMaskN);
5526 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiOnIoTrapN);
5527 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiOnIoTrapCtlSts);
5528 CPUM_ASSERT_WR_MSR_FN(AmdK8IntPendingMessage);
5529 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiTriggerIoCycle);
5530 CPUM_ASSERT_WR_MSR_FN(AmdFam10hMmioCfgBaseAddr);
5531 CPUM_ASSERT_WR_MSR_FN(AmdFam10hTrapCtlMaybe);
5532 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateControl);
5533 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateStatus);
5534 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateN);
5535 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCofVidControl);
5536 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCofVidStatus);
5537 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCStateIoBaseAddr);
5538 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCpuWatchdogTimer);
5539 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmBase);
5540 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmAddr);
5541 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmMask);
5542 CPUM_ASSERT_WR_MSR_FN(AmdK8VmCr);
5543 CPUM_ASSERT_WR_MSR_FN(AmdK8IgnNe);
5544 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmCtl);
5545 CPUM_ASSERT_WR_MSR_FN(AmdK8VmHSavePa);
5546 CPUM_ASSERT_WR_MSR_FN(AmdFam10hVmLockKey);
5547 CPUM_ASSERT_WR_MSR_FN(AmdFam10hSmmLockKey);
5548 CPUM_ASSERT_WR_MSR_FN(AmdFam10hLocalSmiStatus);
5549 CPUM_ASSERT_WR_MSR_FN(AmdFam10hOsVisWrkIdLength);
5550 CPUM_ASSERT_WR_MSR_FN(AmdFam10hOsVisWrkStatus);
5551 CPUM_ASSERT_WR_MSR_FN(AmdFam16hL2IPerfCtlN);
5552 CPUM_ASSERT_WR_MSR_FN(AmdFam16hL2IPerfCtrN);
5553 CPUM_ASSERT_WR_MSR_FN(AmdFam15hNorthbridgePerfCtlN);
5554 CPUM_ASSERT_WR_MSR_FN(AmdFam15hNorthbridgePerfCtrN);
5555 CPUM_ASSERT_WR_MSR_FN(AmdK7MicrocodeCtl);
5556 CPUM_ASSERT_WR_MSR_FN(AmdK7ClusterIdMaybe);
5557 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd07hEbax);
5558 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd06hEcx);
5559 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd01hEdcx);
5560 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlExt01hEdcx);
5561 CPUM_ASSERT_WR_MSR_FN(AmdK8PatchLoader);
5562 CPUM_ASSERT_WR_MSR_FN(AmdK7DebugStatusMaybe);
5563 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTraceBaseMaybe);
5564 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTracePtrMaybe);
5565 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTraceLimitMaybe);
5566 CPUM_ASSERT_WR_MSR_FN(AmdK7HardwareDebugToolCfgMaybe);
5567 CPUM_ASSERT_WR_MSR_FN(AmdK7FastFlushCountMaybe);
5568 CPUM_ASSERT_WR_MSR_FN(AmdK7NodeId);
5569 CPUM_ASSERT_WR_MSR_FN(AmdK7DrXAddrMaskN);
5570 CPUM_ASSERT_WR_MSR_FN(AmdK7Dr0DataMatchMaybe);
5571 CPUM_ASSERT_WR_MSR_FN(AmdK7Dr0DataMaskMaybe);
5572 CPUM_ASSERT_WR_MSR_FN(AmdK7LoadStoreCfg);
5573 CPUM_ASSERT_WR_MSR_FN(AmdK7InstrCacheCfg);
5574 CPUM_ASSERT_WR_MSR_FN(AmdK7DataCacheCfg);
5575 CPUM_ASSERT_WR_MSR_FN(AmdK7BusUnitCfg);
5576 CPUM_ASSERT_WR_MSR_FN(AmdK7DebugCtl2Maybe);
5577 CPUM_ASSERT_WR_MSR_FN(AmdFam15hFpuCfg);
5578 CPUM_ASSERT_WR_MSR_FN(AmdFam15hDecoderCfg);
5579 CPUM_ASSERT_WR_MSR_FN(AmdFam10hBusUnitCfg2);
5580 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg);
5581 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg2);
5582 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg3);
5583 CPUM_ASSERT_WR_MSR_FN(AmdFam15hExecUnitCfg);
5584 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLoadStoreCfg2);
5585 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchCtl);
5586 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchLinAddr);
5587 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchPhysAddr);
5588 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpExecCtl);
5589 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpRip);
5590 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData);
5591 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData2);
5592 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData3);
5593 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsDcLinAddr);
5594 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsDcPhysAddr);
5595 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsCtl);
5596 CPUM_ASSERT_WR_MSR_FN(AmdFam14hIbsBrTarget);
5597
5598 CPUM_ASSERT_WR_MSR_FN(Gim);
5599
5600 return VINF_SUCCESS;
5601}
5602#endif /* VBOX_STRICT && IN_RING3 */
5603
5604
5605/**
5606 * Gets the scalable bus frequency.
5607 *
5608 * The bus frequency is used as a base in several MSRs that gives the CPU and
5609 * other frequency ratios.
5610 *
5611 * @returns Scalable bus frequency in Hz. Will not return CPUM_SBUSFREQ_UNKNOWN.
5612 * @param pVM Pointer to the shared VM structure.
5613 */
5614VMMDECL(uint64_t) CPUMGetGuestScalableBusFrequency(PVM pVM)
5615{
5616 uint64_t uFreq = pVM->cpum.s.GuestInfo.uScalableBusFreq;
5617 if (uFreq == CPUM_SBUSFREQ_UNKNOWN)
5618 uFreq = CPUM_SBUSFREQ_100MHZ;
5619 return uFreq;
5620}
5621
5622
5623#ifdef IN_RING0
5624
5625/**
5626 * Fast way for HM to access the MSR_K8_TSC_AUX register.
5627 *
5628 * @returns The register value.
5629 * @param pVCpu Pointer to the cross context CPU structure for
5630 * the calling EMT.
5631 * @thread EMT(pVCpu)
5632 */
5633VMMR0_INT_DECL(uint64_t) CPUMR0GetGuestTscAux(PVMCPU pVCpu)
5634{
5635 return pVCpu->cpum.s.GuestMsrs.msr.TscAux;
5636}
5637
5638
5639/**
5640 * Fast way for HM to access the MSR_K8_TSC_AUX register.
5641 *
5642 * @param pVCpu Pointer to the cross context CPU structure for
5643 * the calling EMT.
5644 * @param uValue The new value.
5645 * @thread EMT(pVCpu)
5646 */
5647VMMR0_INT_DECL(void) CPUMR0SetGuestTscAux(PVMCPU pVCpu, uint64_t uValue)
5648{
5649 pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
5650}
5651
5652#endif /* IN_RING0 */
5653
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