VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllMsrs.cpp@ 70215

Last change on this file since 70215 was 70071, checked in by vboxsync, 7 years ago

VMM/CPUM: Raise #GP(0) like a physical CPU would when a nested-hypervisor doesn't intercept GIM MSRs.
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File size: 231.0 KB
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1/* $Id: CPUMAllMsrs.cpp 70071 2017-12-12 05:42:25Z vboxsync $ */
2/** @file
3 * CPUM - CPU MSR Registers.
4 */
5
6/*
7 * Copyright (C) 2013-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_CPUM
23#include <VBox/vmm/cpum.h>
24#include <VBox/vmm/apic.h>
25#include <VBox/vmm/hm.h>
26#include <VBox/vmm/tm.h>
27#include <VBox/vmm/gim.h>
28#include "CPUMInternal.h"
29#include <VBox/vmm/vm.h>
30#include <VBox/err.h>
31
32
33/*********************************************************************************************************************************
34* Defined Constants And Macros *
35*********************************************************************************************************************************/
36/**
37 * Validates the CPUMMSRRANGE::offCpumCpu value and declares a local variable
38 * pointing to it.
39 *
40 * ASSUMES sizeof(a_Type) is a power of two and that the member is aligned
41 * correctly.
42 */
43#define CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(a_pVCpu, a_pRange, a_Type, a_VarName) \
44 AssertMsgReturn( (a_pRange)->offCpumCpu >= 8 \
45 && (a_pRange)->offCpumCpu < sizeof(CPUMCPU) \
46 && !((a_pRange)->offCpumCpu & (RT_MIN(sizeof(a_Type), 8) - 1)) \
47 , ("offCpumCpu=%#x %s\n", (a_pRange)->offCpumCpu, (a_pRange)->szName), \
48 VERR_CPUM_MSR_BAD_CPUMCPU_OFFSET); \
49 a_Type *a_VarName = (a_Type *)((uintptr_t)&(a_pVCpu)->cpum.s + (a_pRange)->offCpumCpu)
50
51
52/*********************************************************************************************************************************
53* Structures and Typedefs *
54*********************************************************************************************************************************/
55
56/**
57 * Implements reading one or more MSRs.
58 *
59 * @returns VBox status code.
60 * @retval VINF_SUCCESS on success.
61 * @retval VINF_CPUM_R3_MSR_READ if the MSR read could not be serviced in the
62 * current context (raw-mode or ring-0).
63 * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR).
64 *
65 * @param pVCpu The cross context virtual CPU structure.
66 * @param idMsr The MSR we're reading.
67 * @param pRange The MSR range descriptor.
68 * @param puValue Where to return the value.
69 */
70typedef DECLCALLBACK(VBOXSTRICTRC) FNCPUMRDMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue);
71/** Pointer to a RDMSR worker for a specific MSR or range of MSRs. */
72typedef FNCPUMRDMSR *PFNCPUMRDMSR;
73
74
75/**
76 * Implements writing one or more MSRs.
77 *
78 * @retval VINF_SUCCESS on success.
79 * @retval VINF_CPUM_R3_MSR_WRITE if the MSR write could not be serviced in the
80 * current context (raw-mode or ring-0).
81 * @retval VERR_CPUM_RAISE_GP_0 on failure.
82 *
83 * @param pVCpu The cross context virtual CPU structure.
84 * @param idMsr The MSR we're writing.
85 * @param pRange The MSR range descriptor.
86 * @param uValue The value to set, ignored bits masked.
87 * @param uRawValue The raw value with the ignored bits not masked.
88 */
89typedef DECLCALLBACK(VBOXSTRICTRC) FNCPUMWRMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue);
90/** Pointer to a WRMSR worker for a specific MSR or range of MSRs. */
91typedef FNCPUMWRMSR *PFNCPUMWRMSR;
92
93
94
95/*
96 * Generic functions.
97 * Generic functions.
98 * Generic functions.
99 */
100
101
102/** @callback_method_impl{FNCPUMRDMSR} */
103static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_FixedValue(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
104{
105 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
106 *puValue = pRange->uValue;
107 return VINF_SUCCESS;
108}
109
110
111/** @callback_method_impl{FNCPUMWRMSR} */
112static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IgnoreWrite(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
113{
114 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
115 Log(("CPUM: Ignoring WRMSR %#x (%s), %#llx\n", idMsr, pRange->szName, uValue));
116 return VINF_SUCCESS;
117}
118
119
120/** @callback_method_impl{FNCPUMRDMSR} */
121static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_WriteOnly(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
122{
123 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(puValue);
124 return VERR_CPUM_RAISE_GP_0;
125}
126
127
128/** @callback_method_impl{FNCPUMWRMSR} */
129static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_ReadOnly(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
130{
131 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
132 Assert(pRange->fWrGpMask == UINT64_MAX);
133 return VERR_CPUM_RAISE_GP_0;
134}
135
136
137
138
139/*
140 * IA32
141 * IA32
142 * IA32
143 */
144
145/** @callback_method_impl{FNCPUMRDMSR} */
146static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32P5McAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
147{
148 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
149 *puValue = 0; /** @todo implement machine check injection. */
150 return VINF_SUCCESS;
151}
152
153
154/** @callback_method_impl{FNCPUMWRMSR} */
155static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32P5McAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
156{
157 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
158 /** @todo implement machine check injection. */
159 return VINF_SUCCESS;
160}
161
162
163/** @callback_method_impl{FNCPUMRDMSR} */
164static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32P5McType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
165{
166 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
167 *puValue = 0; /** @todo implement machine check injection. */
168 return VINF_SUCCESS;
169}
170
171
172/** @callback_method_impl{FNCPUMWRMSR} */
173static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32P5McType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
174{
175 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
176 /** @todo implement machine check injection. */
177 return VINF_SUCCESS;
178}
179
180
181/** @callback_method_impl{FNCPUMRDMSR} */
182static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32TimestampCounter(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
183{
184 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
185 *puValue = TMCpuTickGet(pVCpu);
186#ifdef VBOX_WITH_NESTED_HWVIRT
187 *puValue = CPUMApplyNestedGuestTscOffset(pVCpu, *puValue);
188#endif
189 return VINF_SUCCESS;
190}
191
192
193/** @callback_method_impl{FNCPUMWRMSR} */
194static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32TimestampCounter(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
195{
196 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
197 TMCpuTickSet(pVCpu->CTX_SUFF(pVM), pVCpu, uValue);
198 return VINF_SUCCESS;
199}
200
201
202/** @callback_method_impl{FNCPUMRDMSR} */
203static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PlatformId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
204{
205 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
206 uint64_t uValue = pRange->uValue;
207 if (uValue & 0x1f00)
208 {
209 /* Max allowed bus ratio present. */
210 /** @todo Implement scaled BUS frequency. */
211 }
212
213 *puValue = uValue;
214 return VINF_SUCCESS;
215}
216
217
218/** @callback_method_impl{FNCPUMRDMSR} */
219static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ApicBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
220{
221 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
222 return APICGetBaseMsr(pVCpu, puValue);
223}
224
225
226/** @callback_method_impl{FNCPUMWRMSR} */
227static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ApicBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
228{
229 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
230 return APICSetBaseMsr(pVCpu, uValue);
231}
232
233
234/** @callback_method_impl{FNCPUMRDMSR} */
235static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32FeatureControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
236{
237 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
238 *puValue = 1; /* Locked, no VT-X, no SYSENTER micromanagement. */
239 return VINF_SUCCESS;
240}
241
242
243/** @callback_method_impl{FNCPUMWRMSR} */
244static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32FeatureControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
245{
246 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
247 return VERR_CPUM_RAISE_GP_0;
248}
249
250
251/** @callback_method_impl{FNCPUMRDMSR} */
252static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32BiosSignId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
253{
254 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
255 /** @todo fake microcode update. */
256 *puValue = pRange->uValue;
257 return VINF_SUCCESS;
258}
259
260
261/** @callback_method_impl{FNCPUMWRMSR} */
262static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32BiosSignId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
263{
264 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
265 /* Normally, zero is written to Ia32BiosSignId before reading it in order
266 to select the signature instead of the BBL_CR_D3 behaviour. The GP mask
267 of the database entry should take care of most illegal writes for now, so
268 just ignore all writes atm. */
269 return VINF_SUCCESS;
270}
271
272
273/** @callback_method_impl{FNCPUMWRMSR} */
274static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32BiosUpdateTrigger(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
275{
276 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
277 /** @todo Fake bios update trigger better. The value is the address to an
278 * update package, I think. We should probably GP if it's invalid. */
279 return VINF_SUCCESS;
280}
281
282
283/** @callback_method_impl{FNCPUMRDMSR} */
284static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SmmMonitorCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
285{
286 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
287 /** @todo SMM. */
288 *puValue = 0;
289 return VINF_SUCCESS;
290}
291
292
293/** @callback_method_impl{FNCPUMWRMSR} */
294static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SmmMonitorCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
295{
296 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
297 /** @todo SMM. */
298 return VINF_SUCCESS;
299}
300
301
302/** @callback_method_impl{FNCPUMRDMSR} */
303static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PmcN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
304{
305 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
306 /** @todo check CPUID leaf 0ah. */
307 *puValue = 0;
308 return VINF_SUCCESS;
309}
310
311
312/** @callback_method_impl{FNCPUMWRMSR} */
313static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PmcN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
314{
315 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
316 /** @todo check CPUID leaf 0ah. */
317 return VINF_SUCCESS;
318}
319
320
321/** @callback_method_impl{FNCPUMRDMSR} */
322static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MonitorFilterLineSize(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
323{
324 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
325 /** @todo return 0x1000 if we try emulate mwait 100% correctly. */
326 *puValue = 0x40; /** @todo Change to CPU cache line size. */
327 return VINF_SUCCESS;
328}
329
330
331/** @callback_method_impl{FNCPUMWRMSR} */
332static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MonitorFilterLineSize(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
333{
334 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
335 /** @todo should remember writes, though it's supposedly something only a BIOS
336 * would write so, it's not extremely important. */
337 return VINF_SUCCESS;
338}
339
340/** @callback_method_impl{FNCPUMRDMSR} */
341static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MPerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
342{
343 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
344 /** @todo Read MPERF: Adjust against previously written MPERF value. Is TSC
345 * what we want? */
346 *puValue = TMCpuTickGet(pVCpu);
347#ifdef VBOX_WITH_NESTED_HWVIRT
348 *puValue = CPUMApplyNestedGuestTscOffset(pVCpu, *puValue);
349#endif
350 return VINF_SUCCESS;
351}
352
353
354/** @callback_method_impl{FNCPUMWRMSR} */
355static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MPerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
356{
357 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
358 /** @todo Write MPERF: Calc adjustment. */
359 return VINF_SUCCESS;
360}
361
362
363/** @callback_method_impl{FNCPUMRDMSR} */
364static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32APerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
365{
366 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
367 /** @todo Read APERF: Adjust against previously written MPERF value. Is TSC
368 * what we want? */
369 *puValue = TMCpuTickGet(pVCpu);
370#ifdef VBOX_WITH_NESTED_HWVIRT
371 *puValue = CPUMApplyNestedGuestTscOffset(pVCpu, *puValue);
372#endif
373 return VINF_SUCCESS;
374}
375
376
377/** @callback_method_impl{FNCPUMWRMSR} */
378static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32APerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
379{
380 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
381 /** @todo Write APERF: Calc adjustment. */
382 return VINF_SUCCESS;
383}
384
385
386/** @callback_method_impl{FNCPUMRDMSR} */
387static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
388{
389 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
390
391 /* This is currently a bit weird. :-) */
392 uint8_t const cVariableRangeRegs = 0;
393 bool const fSystemManagementRangeRegisters = false;
394 bool const fFixedRangeRegisters = false;
395 bool const fWriteCombiningType = false;
396 *puValue = cVariableRangeRegs
397 | (fFixedRangeRegisters ? RT_BIT_64(8) : 0)
398 | (fWriteCombiningType ? RT_BIT_64(10) : 0)
399 | (fSystemManagementRangeRegisters ? RT_BIT_64(11) : 0);
400 return VINF_SUCCESS;
401}
402
403
404/** @callback_method_impl{FNCPUMRDMSR} */
405static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrPhysBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
406{
407 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
408 /** @todo Implement variable MTRR storage. */
409 Assert(pRange->uValue == (idMsr - 0x200) / 2);
410 *puValue = 0;
411 return VINF_SUCCESS;
412}
413
414
415/** @callback_method_impl{FNCPUMWRMSR} */
416static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrPhysBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
417{
418 /*
419 * Validate the value.
420 */
421 Assert(pRange->uValue == (idMsr - 0x200) / 2);
422 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(uRawValue); RT_NOREF_PV(pRange);
423
424 uint8_t uType = uValue & 0xff;
425 if ((uType >= 7) || (uType == 2) || (uType == 3))
426 {
427 Log(("CPUM: Invalid type set writing MTRR PhysBase MSR %#x: %#llx (%#llx)\n", idMsr, uValue, uType));
428 return VERR_CPUM_RAISE_GP_0;
429 }
430
431 uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
432 if (fInvPhysMask & uValue)
433 {
434 Log(("CPUM: Invalid physical address bits set writing MTRR PhysBase MSR %#x: %#llx (%#llx)\n",
435 idMsr, uValue, uValue & fInvPhysMask));
436 return VERR_CPUM_RAISE_GP_0;
437 }
438
439 /*
440 * Store it.
441 */
442 /** @todo Implement variable MTRR storage. */
443 return VINF_SUCCESS;
444}
445
446
447/** @callback_method_impl{FNCPUMRDMSR} */
448static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrPhysMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
449{
450 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
451 /** @todo Implement variable MTRR storage. */
452 Assert(pRange->uValue == (idMsr - 0x200) / 2);
453 *puValue = 0;
454 return VINF_SUCCESS;
455}
456
457
458/** @callback_method_impl{FNCPUMWRMSR} */
459static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrPhysMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
460{
461 /*
462 * Validate the value.
463 */
464 Assert(pRange->uValue == (idMsr - 0x200) / 2);
465 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(uRawValue); RT_NOREF_PV(pRange);
466
467 uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
468 if (fInvPhysMask & uValue)
469 {
470 Log(("CPUM: Invalid physical address bits set writing MTRR PhysMask MSR %#x: %#llx (%#llx)\n",
471 idMsr, uValue, uValue & fInvPhysMask));
472 return VERR_CPUM_RAISE_GP_0;
473 }
474
475 /*
476 * Store it.
477 */
478 /** @todo Implement variable MTRR storage. */
479 return VINF_SUCCESS;
480}
481
482
483/** @callback_method_impl{FNCPUMRDMSR} */
484static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrFixed(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
485{
486 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
487 CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(pVCpu, pRange, uint64_t, puFixedMtrr);
488 *puValue = *puFixedMtrr;
489 return VINF_SUCCESS;
490}
491
492
493/** @callback_method_impl{FNCPUMWRMSR} */
494static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrFixed(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
495{
496 CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(pVCpu, pRange, uint64_t, puFixedMtrr);
497 RT_NOREF_PV(idMsr); RT_NOREF_PV(uRawValue);
498
499 for (uint32_t cShift = 0; cShift < 63; cShift += 8)
500 {
501 uint8_t uType = (uint8_t)(uValue >> cShift);
502 if ((uType >= 7) || (uType == 2) || (uType == 3))
503 {
504 Log(("CPUM: Invalid MTRR type at %u:%u in fixed range (%#x/%s): %#llx (%#llx)\n",
505 cShift + 7, cShift, idMsr, pRange->szName, uValue, uType));
506 return VERR_CPUM_RAISE_GP_0;
507 }
508 }
509 *puFixedMtrr = uValue;
510 return VINF_SUCCESS;
511}
512
513
514/** @callback_method_impl{FNCPUMRDMSR} */
515static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MtrrDefType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
516{
517 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
518 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType;
519 return VINF_SUCCESS;
520}
521
522
523/** @callback_method_impl{FNCPUMWRMSR} */
524static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MtrrDefType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
525{
526 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
527
528 uint8_t uType = uValue & 0xff;
529 if ((uType >= 7) || (uType == 2) || (uType == 3))
530 {
531 Log(("CPUM: Invalid MTRR default type value on %s: %#llx (%#llx)\n", pRange->szName, uValue, uType));
532 return VERR_CPUM_RAISE_GP_0;
533 }
534
535 pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType = uValue;
536 return VINF_SUCCESS;
537}
538
539
540/** @callback_method_impl{FNCPUMRDMSR} */
541static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32Pat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
542{
543 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
544 *puValue = pVCpu->cpum.s.Guest.msrPAT;
545 return VINF_SUCCESS;
546}
547
548
549/** @callback_method_impl{FNCPUMWRMSR} */
550static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32Pat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
551{
552 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
553
554 for (uint32_t cShift = 0; cShift < 63; cShift += 8)
555 {
556 /* Check all eight bits because the top 5 bits of each byte are reserved. */
557 uint8_t uType = (uint8_t)(uValue >> cShift);
558 if ((uType >= 8) || (uType == 2) || (uType == 3))
559 {
560 Log(("CPUM: Invalid PAT type at %u:%u in IA32_PAT: %#llx (%#llx)\n",
561 cShift + 7, cShift, uValue, uType));
562 return VERR_CPUM_RAISE_GP_0;
563 }
564 }
565
566 pVCpu->cpum.s.Guest.msrPAT = uValue;
567 return VINF_SUCCESS;
568}
569
570
571/** @callback_method_impl{FNCPUMRDMSR} */
572static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SysEnterCs(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
573{
574 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
575 *puValue = pVCpu->cpum.s.Guest.SysEnter.cs;
576 return VINF_SUCCESS;
577}
578
579
580/** @callback_method_impl{FNCPUMWRMSR} */
581static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SysEnterCs(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
582{
583 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
584
585 /* Note! We used to mask this by 0xffff, but turns out real HW doesn't and
586 there are generally 32-bit working bits backing this register. */
587 pVCpu->cpum.s.Guest.SysEnter.cs = uValue;
588 return VINF_SUCCESS;
589}
590
591
592/** @callback_method_impl{FNCPUMRDMSR} */
593static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SysEnterEsp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
594{
595 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
596 *puValue = pVCpu->cpum.s.Guest.SysEnter.esp;
597 return VINF_SUCCESS;
598}
599
600
601/** @callback_method_impl{FNCPUMWRMSR} */
602static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SysEnterEsp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
603{
604 if (X86_IS_CANONICAL(uValue))
605 {
606 pVCpu->cpum.s.Guest.SysEnter.esp = uValue;
607 return VINF_SUCCESS;
608 }
609 Log(("CPUM: IA32_SYSENTER_ESP not canonical! %#llx\n", uValue));
610 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
611 return VERR_CPUM_RAISE_GP_0;
612}
613
614
615/** @callback_method_impl{FNCPUMRDMSR} */
616static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SysEnterEip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
617{
618 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
619 *puValue = pVCpu->cpum.s.Guest.SysEnter.eip;
620 return VINF_SUCCESS;
621}
622
623
624/** @callback_method_impl{FNCPUMWRMSR} */
625static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SysEnterEip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
626{
627 if (X86_IS_CANONICAL(uValue))
628 {
629 pVCpu->cpum.s.Guest.SysEnter.eip = uValue;
630 return VINF_SUCCESS;
631 }
632#ifdef IN_RING3
633 LogRel(("CPUM: IA32_SYSENTER_EIP not canonical! %#llx\n", uValue));
634#else
635 Log(("CPUM: IA32_SYSENTER_EIP not canonical! %#llx\n", uValue));
636#endif
637 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
638 return VERR_CPUM_RAISE_GP_0;
639}
640
641
642/** @callback_method_impl{FNCPUMRDMSR} */
643static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McgCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
644{
645#if 0 /** @todo implement machine checks. */
646 *puValue = pRange->uValue & (RT_BIT_64(8) | 0);
647#else
648 *puValue = 0;
649#endif
650 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
651 return VINF_SUCCESS;
652}
653
654
655/** @callback_method_impl{FNCPUMRDMSR} */
656static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McgStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
657{
658 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
659 /** @todo implement machine checks. */
660 *puValue = 0;
661 return VINF_SUCCESS;
662}
663
664
665/** @callback_method_impl{FNCPUMWRMSR} */
666static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McgStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
667{
668 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
669 /** @todo implement machine checks. */
670 return VINF_SUCCESS;
671}
672
673
674/** @callback_method_impl{FNCPUMRDMSR} */
675static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McgCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
676{
677 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
678 /** @todo implement machine checks. */
679 *puValue = 0;
680 return VINF_SUCCESS;
681}
682
683
684/** @callback_method_impl{FNCPUMWRMSR} */
685static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McgCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
686{
687 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
688 /** @todo implement machine checks. */
689 return VINF_SUCCESS;
690}
691
692
693/** @callback_method_impl{FNCPUMRDMSR} */
694static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32DebugCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
695{
696 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
697 /** @todo implement IA32_DEBUGCTL. */
698 *puValue = 0;
699 return VINF_SUCCESS;
700}
701
702
703/** @callback_method_impl{FNCPUMWRMSR} */
704static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32DebugCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
705{
706 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
707 /** @todo implement IA32_DEBUGCTL. */
708 return VINF_SUCCESS;
709}
710
711
712/** @callback_method_impl{FNCPUMRDMSR} */
713static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SmrrPhysBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
714{
715 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
716 /** @todo implement intel SMM. */
717 *puValue = 0;
718 return VINF_SUCCESS;
719}
720
721
722/** @callback_method_impl{FNCPUMWRMSR} */
723static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SmrrPhysBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
724{
725 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
726 /** @todo implement intel SMM. */
727 return VERR_CPUM_RAISE_GP_0;
728}
729
730
731/** @callback_method_impl{FNCPUMRDMSR} */
732static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32SmrrPhysMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
733{
734 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
735 /** @todo implement intel SMM. */
736 *puValue = 0;
737 return VINF_SUCCESS;
738}
739
740
741/** @callback_method_impl{FNCPUMWRMSR} */
742static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32SmrrPhysMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
743{
744 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
745 /** @todo implement intel SMM. */
746 return VERR_CPUM_RAISE_GP_0;
747}
748
749
750/** @callback_method_impl{FNCPUMRDMSR} */
751static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PlatformDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
752{
753 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
754 /** @todo implement intel direct cache access (DCA)?? */
755 *puValue = 0;
756 return VINF_SUCCESS;
757}
758
759
760/** @callback_method_impl{FNCPUMWRMSR} */
761static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PlatformDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
762{
763 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
764 /** @todo implement intel direct cache access (DCA)?? */
765 return VINF_SUCCESS;
766}
767
768
769/** @callback_method_impl{FNCPUMRDMSR} */
770static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32CpuDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
771{
772 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
773 /** @todo implement intel direct cache access (DCA)?? */
774 *puValue = 0;
775 return VINF_SUCCESS;
776}
777
778
779/** @callback_method_impl{FNCPUMRDMSR} */
780static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32Dca0Cap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
781{
782 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
783 /** @todo implement intel direct cache access (DCA)?? */
784 *puValue = 0;
785 return VINF_SUCCESS;
786}
787
788
789/** @callback_method_impl{FNCPUMWRMSR} */
790static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32Dca0Cap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
791{
792 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
793 /** @todo implement intel direct cache access (DCA)?? */
794 return VINF_SUCCESS;
795}
796
797
798/** @callback_method_impl{FNCPUMRDMSR} */
799static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
800{
801 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
802 /** @todo implement IA32_PERFEVTSEL0+. */
803 *puValue = 0;
804 return VINF_SUCCESS;
805}
806
807
808/** @callback_method_impl{FNCPUMWRMSR} */
809static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
810{
811 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
812 /** @todo implement IA32_PERFEVTSEL0+. */
813 return VINF_SUCCESS;
814}
815
816
817/** @callback_method_impl{FNCPUMRDMSR} */
818static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
819{
820 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
821 uint64_t uValue = pRange->uValue;
822
823 /* Always provide the max bus ratio for now. XNU expects it. */
824 uValue &= ~((UINT64_C(0x1f) << 40) | RT_BIT_64(46));
825
826 PVM pVM = pVCpu->CTX_SUFF(pVM);
827 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
828 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
829 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
830 if (uTscRatio > 0x1f)
831 uTscRatio = 0x1f;
832 uValue |= (uint64_t)uTscRatio << 40;
833
834 *puValue = uValue;
835 return VINF_SUCCESS;
836}
837
838
839/** @callback_method_impl{FNCPUMWRMSR} */
840static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
841{
842 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
843 /* Pentium4 allows writing, but all bits are ignored. */
844 return VINF_SUCCESS;
845}
846
847
848/** @callback_method_impl{FNCPUMRDMSR} */
849static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
850{
851 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
852 /** @todo implement IA32_PERFCTL. */
853 *puValue = 0;
854 return VINF_SUCCESS;
855}
856
857
858/** @callback_method_impl{FNCPUMWRMSR} */
859static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
860{
861 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
862 /** @todo implement IA32_PERFCTL. */
863 return VINF_SUCCESS;
864}
865
866
867/** @callback_method_impl{FNCPUMRDMSR} */
868static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32FixedCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
869{
870 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
871 /** @todo implement IA32_FIXED_CTRn (fixed performance counters). */
872 *puValue = 0;
873 return VINF_SUCCESS;
874}
875
876
877/** @callback_method_impl{FNCPUMWRMSR} */
878static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32FixedCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
879{
880 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
881 /** @todo implement IA32_FIXED_CTRn (fixed performance counters). */
882 return VINF_SUCCESS;
883}
884
885
886/** @callback_method_impl{FNCPUMRDMSR} */
887static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfCapabilities(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
888{
889 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
890 /** @todo implement performance counters. */
891 *puValue = 0;
892 return VINF_SUCCESS;
893}
894
895
896/** @callback_method_impl{FNCPUMWRMSR} */
897static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfCapabilities(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
898{
899 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
900 /** @todo implement performance counters. */
901 return VINF_SUCCESS;
902}
903
904
905/** @callback_method_impl{FNCPUMRDMSR} */
906static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32FixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
907{
908 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
909 /** @todo implement performance counters. */
910 *puValue = 0;
911 return VINF_SUCCESS;
912}
913
914
915/** @callback_method_impl{FNCPUMWRMSR} */
916static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32FixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
917{
918 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
919 /** @todo implement performance counters. */
920 return VINF_SUCCESS;
921}
922
923
924/** @callback_method_impl{FNCPUMRDMSR} */
925static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
926{
927 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
928 /** @todo implement performance counters. */
929 *puValue = 0;
930 return VINF_SUCCESS;
931}
932
933
934/** @callback_method_impl{FNCPUMWRMSR} */
935static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
936{
937 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
938 /** @todo implement performance counters. */
939 return VINF_SUCCESS;
940}
941
942
943/** @callback_method_impl{FNCPUMRDMSR} */
944static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
945{
946 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
947 /** @todo implement performance counters. */
948 *puValue = 0;
949 return VINF_SUCCESS;
950}
951
952
953/** @callback_method_impl{FNCPUMWRMSR} */
954static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
955{
956 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
957 /** @todo implement performance counters. */
958 return VINF_SUCCESS;
959}
960
961
962/** @callback_method_impl{FNCPUMRDMSR} */
963static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
964{
965 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
966 /** @todo implement performance counters. */
967 *puValue = 0;
968 return VINF_SUCCESS;
969}
970
971
972/** @callback_method_impl{FNCPUMWRMSR} */
973static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
974{
975 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
976 /** @todo implement performance counters. */
977 return VINF_SUCCESS;
978}
979
980
981/** @callback_method_impl{FNCPUMRDMSR} */
982static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32PebsEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
983{
984 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
985 /** @todo implement performance counters. */
986 *puValue = 0;
987 return VINF_SUCCESS;
988}
989
990
991/** @callback_method_impl{FNCPUMWRMSR} */
992static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32PebsEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
993{
994 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
995 /** @todo implement performance counters. */
996 return VINF_SUCCESS;
997}
998
999
1000/** @callback_method_impl{FNCPUMRDMSR} */
1001static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ClockModulation(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1002{
1003 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1004 /** @todo implement IA32_CLOCK_MODULATION. */
1005 *puValue = 0;
1006 return VINF_SUCCESS;
1007}
1008
1009
1010/** @callback_method_impl{FNCPUMWRMSR} */
1011static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ClockModulation(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1012{
1013 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1014 /** @todo implement IA32_CLOCK_MODULATION. */
1015 return VINF_SUCCESS;
1016}
1017
1018
1019/** @callback_method_impl{FNCPUMRDMSR} */
1020static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ThermInterrupt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1021{
1022 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1023 /** @todo implement IA32_THERM_INTERRUPT. */
1024 *puValue = 0;
1025 return VINF_SUCCESS;
1026}
1027
1028
1029/** @callback_method_impl{FNCPUMWRMSR} */
1030static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ThermInterrupt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1031{
1032 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1033 /** @todo implement IA32_THERM_STATUS. */
1034 return VINF_SUCCESS;
1035}
1036
1037
1038/** @callback_method_impl{FNCPUMRDMSR} */
1039static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32ThermStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1040{
1041 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1042 /** @todo implement IA32_THERM_STATUS. */
1043 *puValue = 0;
1044 return VINF_SUCCESS;
1045}
1046
1047
1048/** @callback_method_impl{FNCPUMWRMSR} */
1049static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32ThermStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1050{
1051 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1052 /** @todo implement IA32_THERM_INTERRUPT. */
1053 return VINF_SUCCESS;
1054}
1055
1056
1057/** @callback_method_impl{FNCPUMRDMSR} */
1058static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32Therm2Ctl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1059{
1060 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1061 /** @todo implement IA32_THERM2_CTL. */
1062 *puValue = 0;
1063 return VINF_SUCCESS;
1064}
1065
1066
1067/** @callback_method_impl{FNCPUMWRMSR} */
1068static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32Therm2Ctl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1069{
1070 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1071 /** @todo implement IA32_THERM2_CTL. */
1072 return VINF_SUCCESS;
1073}
1074
1075
1076/** @callback_method_impl{FNCPUMRDMSR} */
1077static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32MiscEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1078{
1079 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1080 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
1081 return VINF_SUCCESS;
1082}
1083
1084
1085/** @callback_method_impl{FNCPUMWRMSR} */
1086static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32MiscEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1087{
1088 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1089#ifdef LOG_ENABLED
1090 uint64_t const uOld = pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
1091#endif
1092
1093 /* Unsupported bits are generally ignored and stripped by the MSR range
1094 entry that got us here. So, we just need to preserve fixed bits. */
1095 pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = uValue
1096 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
1097 | MSR_IA32_MISC_ENABLE_BTS_UNAVAIL;
1098
1099 Log(("CPUM: IA32_MISC_ENABLE; old=%#llx written=%#llx => %#llx\n",
1100 uOld, uValue, pVCpu->cpum.s.GuestMsrs.msr.MiscEnable));
1101
1102 /** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
1103 /** @todo Wire up MSR_IA32_MISC_ENABLE_XD_DISABLE. */
1104 return VINF_SUCCESS;
1105}
1106
1107
1108/** @callback_method_impl{FNCPUMRDMSR} */
1109static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McCtlStatusAddrMiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1110{
1111 RT_NOREF_PV(pVCpu); RT_NOREF_PV(pRange);
1112
1113 /** @todo Implement machine check exception injection. */
1114 switch (idMsr & 3)
1115 {
1116 case 0:
1117 case 1:
1118 *puValue = 0;
1119 break;
1120
1121 /* The ADDR and MISC registers aren't accessible since the
1122 corresponding STATUS bits are zero. */
1123 case 2:
1124 Log(("CPUM: Reading IA32_MCi_ADDR %#x -> #GP\n", idMsr));
1125 return VERR_CPUM_RAISE_GP_0;
1126 case 3:
1127 Log(("CPUM: Reading IA32_MCi_MISC %#x -> #GP\n", idMsr));
1128 return VERR_CPUM_RAISE_GP_0;
1129 }
1130 return VINF_SUCCESS;
1131}
1132
1133
1134/** @callback_method_impl{FNCPUMWRMSR} */
1135static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McCtlStatusAddrMiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1136{
1137 RT_NOREF_PV(pVCpu); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1138 switch (idMsr & 3)
1139 {
1140 case 0:
1141 /* Ignore writes to the CTL register. */
1142 break;
1143
1144 case 1:
1145 /* According to specs, the STATUS register can only be written to
1146 with the value 0. VBoxCpuReport thinks different for a
1147 Pentium M Dothan, but implementing according to specs now. */
1148 if (uValue != 0)
1149 {
1150 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_STATUS %#x -> #GP\n", uValue, idMsr));
1151 return VERR_CPUM_RAISE_GP_0;
1152 }
1153 break;
1154
1155 /* Specs states that ADDR and MISC can be cleared by writing zeros.
1156 Writing 1s will GP. Need to figure out how this relates to the
1157 ADDRV and MISCV status flags. If writing is independent of those
1158 bits, we need to know whether the CPU really implements them since
1159 that is exposed by writing 0 to them.
1160 Implementing the solution with the fewer GPs for now. */
1161 case 2:
1162 if (uValue != 0)
1163 {
1164 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_ADDR %#x -> #GP\n", uValue, idMsr));
1165 return VERR_CPUM_RAISE_GP_0;
1166 }
1167 break;
1168 case 3:
1169 if (uValue != 0)
1170 {
1171 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_MISC %#x -> #GP\n", uValue, idMsr));
1172 return VERR_CPUM_RAISE_GP_0;
1173 }
1174 break;
1175 }
1176 return VINF_SUCCESS;
1177}
1178
1179
1180/** @callback_method_impl{FNCPUMRDMSR} */
1181static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32McNCtl2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1182{
1183 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1184 /** @todo Implement machine check exception injection. */
1185 *puValue = 0;
1186 return VINF_SUCCESS;
1187}
1188
1189
1190/** @callback_method_impl{FNCPUMWRMSR} */
1191static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32McNCtl2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1192{
1193 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1194 /** @todo Implement machine check exception injection. */
1195 return VINF_SUCCESS;
1196}
1197
1198
1199/** @callback_method_impl{FNCPUMRDMSR} */
1200static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32DsArea(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1201{
1202 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1203 /** @todo implement IA32_DS_AREA. */
1204 *puValue = 0;
1205 return VINF_SUCCESS;
1206}
1207
1208
1209/** @callback_method_impl{FNCPUMWRMSR} */
1210static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32DsArea(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1211{
1212 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1213 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1214 return VINF_SUCCESS;
1215}
1216
1217
1218/** @callback_method_impl{FNCPUMRDMSR} */
1219static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32TscDeadline(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1220{
1221 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1222 /** @todo implement TSC deadline timer. */
1223 *puValue = 0;
1224 return VINF_SUCCESS;
1225}
1226
1227
1228/** @callback_method_impl{FNCPUMWRMSR} */
1229static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32TscDeadline(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1230{
1231 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1232 /** @todo implement TSC deadline timer. */
1233 return VINF_SUCCESS;
1234}
1235
1236
1237/** @callback_method_impl{FNCPUMRDMSR} */
1238static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32X2ApicN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1239{
1240 RT_NOREF_PV(pRange);
1241 return APICReadMsr(pVCpu, idMsr, puValue);
1242}
1243
1244
1245/** @callback_method_impl{FNCPUMWRMSR} */
1246static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32X2ApicN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1247{
1248 RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1249 return APICWriteMsr(pVCpu, idMsr, uValue);
1250}
1251
1252
1253/** @callback_method_impl{FNCPUMRDMSR} */
1254static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32DebugInterface(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1255{
1256 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1257 /** @todo IA32_DEBUG_INTERFACE (no docs) */
1258 *puValue = 0;
1259 return VINF_SUCCESS;
1260}
1261
1262
1263/** @callback_method_impl{FNCPUMWRMSR} */
1264static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Ia32DebugInterface(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1265{
1266 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1267 /** @todo IA32_DEBUG_INTERFACE (no docs) */
1268 return VINF_SUCCESS;
1269}
1270
1271
1272/** @callback_method_impl{FNCPUMRDMSR} */
1273static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1274{
1275 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1276 *puValue = 0;
1277 return VINF_SUCCESS;
1278}
1279
1280
1281/** @callback_method_impl{FNCPUMRDMSR} */
1282static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxPinbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1283{
1284 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1285 *puValue = 0;
1286 return VINF_SUCCESS;
1287}
1288
1289
1290/** @callback_method_impl{FNCPUMRDMSR} */
1291static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxProcbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1292{
1293 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1294 *puValue = 0;
1295 return VINF_SUCCESS;
1296}
1297
1298
1299/** @callback_method_impl{FNCPUMRDMSR} */
1300static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxExitCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1301{
1302 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1303 *puValue = 0;
1304 return VINF_SUCCESS;
1305}
1306
1307
1308/** @callback_method_impl{FNCPUMRDMSR} */
1309static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxEntryCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1310{
1311 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1312 *puValue = 0;
1313 return VINF_SUCCESS;
1314}
1315
1316
1317/** @callback_method_impl{FNCPUMRDMSR} */
1318static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxMisc(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1319{
1320 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1321 *puValue = 0;
1322 return VINF_SUCCESS;
1323}
1324
1325
1326/** @callback_method_impl{FNCPUMRDMSR} */
1327static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr0Fixed0(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1328{
1329 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1330 *puValue = 0;
1331 return VINF_SUCCESS;
1332}
1333
1334
1335/** @callback_method_impl{FNCPUMRDMSR} */
1336static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr0Fixed1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1337{
1338 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1339 *puValue = 0;
1340 return VINF_SUCCESS;
1341}
1342
1343
1344/** @callback_method_impl{FNCPUMRDMSR} */
1345static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr4Fixed0(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1346{
1347 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1348 *puValue = 0;
1349 return VINF_SUCCESS;
1350}
1351
1352
1353/** @callback_method_impl{FNCPUMRDMSR} */
1354static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxCr4Fixed1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1355{
1356 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1357 *puValue = 0;
1358 return VINF_SUCCESS;
1359}
1360
1361
1362/** @callback_method_impl{FNCPUMRDMSR} */
1363static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxVmcsEnum(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1364{
1365 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1366 *puValue = 0;
1367 return VINF_SUCCESS;
1368}
1369
1370
1371/** @callback_method_impl{FNCPUMRDMSR} */
1372static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxProcBasedCtls2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1373{
1374 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1375 *puValue = 0;
1376 return VINF_SUCCESS;
1377}
1378
1379
1380/** @callback_method_impl{FNCPUMRDMSR} */
1381static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxEptVpidCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1382{
1383 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1384 *puValue = 0;
1385 return VINF_SUCCESS;
1386}
1387
1388
1389/** @callback_method_impl{FNCPUMRDMSR} */
1390static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTruePinbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1391{
1392 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1393 *puValue = 0;
1394 return VINF_SUCCESS;
1395}
1396
1397
1398/** @callback_method_impl{FNCPUMRDMSR} */
1399static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTrueProcbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1400{
1401 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1402 *puValue = 0;
1403 return VINF_SUCCESS;
1404}
1405
1406
1407/** @callback_method_impl{FNCPUMRDMSR} */
1408static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTrueExitCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1409{
1410 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1411 *puValue = 0;
1412 return VINF_SUCCESS;
1413}
1414
1415
1416/** @callback_method_impl{FNCPUMRDMSR} */
1417static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTrueEntryCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1418{
1419 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1420 *puValue = 0;
1421 return VINF_SUCCESS;
1422}
1423
1424
1425/** @callback_method_impl{FNCPUMRDMSR} */
1426static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxVmFunc(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1427{
1428 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1429 *puValue = 0;
1430 return VINF_SUCCESS;
1431}
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442/*
1443 * AMD64
1444 * AMD64
1445 * AMD64
1446 */
1447
1448
1449/** @callback_method_impl{FNCPUMRDMSR} */
1450static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64Efer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1451{
1452 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1453 *puValue = pVCpu->cpum.s.Guest.msrEFER;
1454 return VINF_SUCCESS;
1455}
1456
1457
1458/** @callback_method_impl{FNCPUMWRMSR} */
1459static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64Efer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1460{
1461 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1462 uint64_t uValidatedEfer;
1463 uint64_t const uOldEfer = pVCpu->cpum.s.Guest.msrEFER;
1464 int rc = CPUMQueryValidatedGuestEfer(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.s.Guest.cr0, uOldEfer, uValue, &uValidatedEfer);
1465 if (RT_FAILURE(rc))
1466 return VERR_CPUM_RAISE_GP_0;
1467
1468 CPUMSetGuestMsrEferNoCheck(pVCpu, uOldEfer, uValidatedEfer);
1469 return VINF_SUCCESS;
1470}
1471
1472
1473/** @callback_method_impl{FNCPUMRDMSR} */
1474static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64SyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1475{
1476 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1477 *puValue = pVCpu->cpum.s.Guest.msrSTAR;
1478 return VINF_SUCCESS;
1479}
1480
1481
1482/** @callback_method_impl{FNCPUMWRMSR} */
1483static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64SyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1484{
1485 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1486 pVCpu->cpum.s.Guest.msrSTAR = uValue;
1487 return VINF_SUCCESS;
1488}
1489
1490
1491/** @callback_method_impl{FNCPUMRDMSR} */
1492static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64LongSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1493{
1494 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1495 *puValue = pVCpu->cpum.s.Guest.msrLSTAR;
1496 return VINF_SUCCESS;
1497}
1498
1499
1500/** @callback_method_impl{FNCPUMWRMSR} */
1501static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64LongSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1502{
1503 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1504 if (!X86_IS_CANONICAL(uValue))
1505 {
1506 Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
1507 return VERR_CPUM_RAISE_GP_0;
1508 }
1509 pVCpu->cpum.s.Guest.msrLSTAR = uValue;
1510 return VINF_SUCCESS;
1511}
1512
1513
1514/** @callback_method_impl{FNCPUMRDMSR} */
1515static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64CompSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1516{
1517 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1518 *puValue = pVCpu->cpum.s.Guest.msrCSTAR;
1519 return VINF_SUCCESS;
1520}
1521
1522
1523/** @callback_method_impl{FNCPUMWRMSR} */
1524static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64CompSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1525{
1526 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1527 if (!X86_IS_CANONICAL(uValue))
1528 {
1529 Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
1530 return VERR_CPUM_RAISE_GP_0;
1531 }
1532 pVCpu->cpum.s.Guest.msrCSTAR = uValue;
1533 return VINF_SUCCESS;
1534}
1535
1536
1537/** @callback_method_impl{FNCPUMRDMSR} */
1538static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64SyscallFlagMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1539{
1540 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1541 *puValue = pVCpu->cpum.s.Guest.msrSFMASK;
1542 return VINF_SUCCESS;
1543}
1544
1545
1546/** @callback_method_impl{FNCPUMWRMSR} */
1547static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64SyscallFlagMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1548{
1549 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1550 pVCpu->cpum.s.Guest.msrSFMASK = uValue;
1551 return VINF_SUCCESS;
1552}
1553
1554
1555/** @callback_method_impl{FNCPUMRDMSR} */
1556static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64FsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1557{
1558 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1559 *puValue = pVCpu->cpum.s.Guest.fs.u64Base;
1560 return VINF_SUCCESS;
1561}
1562
1563
1564/** @callback_method_impl{FNCPUMWRMSR} */
1565static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64FsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1566{
1567 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1568 pVCpu->cpum.s.Guest.fs.u64Base = uValue;
1569 return VINF_SUCCESS;
1570}
1571
1572
1573/** @callback_method_impl{FNCPUMRDMSR} */
1574static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64GsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1575{
1576 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1577 *puValue = pVCpu->cpum.s.Guest.gs.u64Base;
1578 return VINF_SUCCESS;
1579}
1580
1581/** @callback_method_impl{FNCPUMWRMSR} */
1582static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64GsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1583{
1584 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1585 pVCpu->cpum.s.Guest.gs.u64Base = uValue;
1586 return VINF_SUCCESS;
1587}
1588
1589
1590
1591/** @callback_method_impl{FNCPUMRDMSR} */
1592static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64KernelGsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1593{
1594 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1595 *puValue = pVCpu->cpum.s.Guest.msrKERNELGSBASE;
1596 return VINF_SUCCESS;
1597}
1598
1599/** @callback_method_impl{FNCPUMWRMSR} */
1600static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64KernelGsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1601{
1602 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1603 pVCpu->cpum.s.Guest.msrKERNELGSBASE = uValue;
1604 return VINF_SUCCESS;
1605}
1606
1607
1608/** @callback_method_impl{FNCPUMRDMSR} */
1609static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Amd64TscAux(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1610{
1611 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1612 *puValue = pVCpu->cpum.s.GuestMsrs.msr.TscAux;
1613 return VINF_SUCCESS;
1614}
1615
1616/** @callback_method_impl{FNCPUMWRMSR} */
1617static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Amd64TscAux(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1618{
1619 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1620 pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
1621 return VINF_SUCCESS;
1622}
1623
1624
1625/*
1626 * Intel specific
1627 * Intel specific
1628 * Intel specific
1629 */
1630
1631/** @callback_method_impl{FNCPUMRDMSR} */
1632static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelEblCrPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1633{
1634 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1635 /** @todo recalc clock frequency ratio? */
1636 *puValue = pRange->uValue;
1637 return VINF_SUCCESS;
1638}
1639
1640
1641/** @callback_method_impl{FNCPUMWRMSR} */
1642static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelEblCrPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1643{
1644 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1645 /** @todo Write EBL_CR_POWERON: Remember written bits. */
1646 return VINF_SUCCESS;
1647}
1648
1649
1650/** @callback_method_impl{FNCPUMRDMSR} */
1651static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7CoreThreadCount(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1652{
1653 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1654
1655 /* Note! According to cpuid_set_info in XNU (10.7.0), Westmere CPU only
1656 have a 4-bit core count. */
1657 uint16_t cCores = pVCpu->CTX_SUFF(pVM)->cCpus;
1658 uint16_t cThreads = cCores; /** @todo hyper-threading. */
1659 *puValue = RT_MAKE_U32(cThreads, cCores);
1660 return VINF_SUCCESS;
1661}
1662
1663
1664/** @callback_method_impl{FNCPUMRDMSR} */
1665static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP4EbcHardPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1666{
1667 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1668 /** @todo P4 hard power on config */
1669 *puValue = pRange->uValue;
1670 return VINF_SUCCESS;
1671}
1672
1673
1674/** @callback_method_impl{FNCPUMWRMSR} */
1675static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP4EbcHardPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1676{
1677 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1678 /** @todo P4 hard power on config */
1679 return VINF_SUCCESS;
1680}
1681
1682
1683/** @callback_method_impl{FNCPUMRDMSR} */
1684static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP4EbcSoftPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1685{
1686 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1687 /** @todo P4 soft power on config */
1688 *puValue = pRange->uValue;
1689 return VINF_SUCCESS;
1690}
1691
1692
1693/** @callback_method_impl{FNCPUMWRMSR} */
1694static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP4EbcSoftPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1695{
1696 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1697 /** @todo P4 soft power on config */
1698 return VINF_SUCCESS;
1699}
1700
1701
1702/** @callback_method_impl{FNCPUMRDMSR} */
1703static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP4EbcFrequencyId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1704{
1705 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1706
1707 uint64_t uValue;
1708 PVM pVM = pVCpu->CTX_SUFF(pVM);
1709 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
1710 if (pVM->cpum.s.GuestFeatures.uModel >= 2)
1711 {
1712 if (uScalableBusHz <= CPUM_SBUSFREQ_100MHZ && pVM->cpum.s.GuestFeatures.uModel <= 2)
1713 {
1714 uScalableBusHz = CPUM_SBUSFREQ_100MHZ;
1715 uValue = 0;
1716 }
1717 else if (uScalableBusHz <= CPUM_SBUSFREQ_133MHZ)
1718 {
1719 uScalableBusHz = CPUM_SBUSFREQ_133MHZ;
1720 uValue = 1;
1721 }
1722 else if (uScalableBusHz <= CPUM_SBUSFREQ_167MHZ)
1723 {
1724 uScalableBusHz = CPUM_SBUSFREQ_167MHZ;
1725 uValue = 3;
1726 }
1727 else if (uScalableBusHz <= CPUM_SBUSFREQ_200MHZ)
1728 {
1729 uScalableBusHz = CPUM_SBUSFREQ_200MHZ;
1730 uValue = 2;
1731 }
1732 else if (uScalableBusHz <= CPUM_SBUSFREQ_267MHZ && pVM->cpum.s.GuestFeatures.uModel > 2)
1733 {
1734 uScalableBusHz = CPUM_SBUSFREQ_267MHZ;
1735 uValue = 0;
1736 }
1737 else
1738 {
1739 uScalableBusHz = CPUM_SBUSFREQ_333MHZ;
1740 uValue = 6;
1741 }
1742 uValue <<= 16;
1743
1744 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
1745 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
1746 uValue |= (uint32_t)uTscRatio << 24;
1747
1748 uValue |= pRange->uValue & ~UINT64_C(0xff0f0000);
1749 }
1750 else
1751 {
1752 /* Probably more stuff here, but intel doesn't want to tell us. */
1753 uValue = pRange->uValue;
1754 uValue &= ~(RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23)); /* 100 MHz is only documented value */
1755 }
1756
1757 *puValue = uValue;
1758 return VINF_SUCCESS;
1759}
1760
1761
1762/** @callback_method_impl{FNCPUMWRMSR} */
1763static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP4EbcFrequencyId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1764{
1765 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1766 /** @todo P4 bus frequency config */
1767 return VINF_SUCCESS;
1768}
1769
1770
1771/** @callback_method_impl{FNCPUMRDMSR} */
1772static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP6FsbFrequency(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1773{
1774 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1775
1776 /* Convert the scalable bus frequency to the encoding in the intel manual (for core+). */
1777 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVCpu->CTX_SUFF(pVM));
1778 if (uScalableBusHz <= CPUM_SBUSFREQ_100MHZ)
1779 *puValue = 5;
1780 else if (uScalableBusHz <= CPUM_SBUSFREQ_133MHZ)
1781 *puValue = 1;
1782 else if (uScalableBusHz <= CPUM_SBUSFREQ_167MHZ)
1783 *puValue = 3;
1784 else if (uScalableBusHz <= CPUM_SBUSFREQ_200MHZ)
1785 *puValue = 2;
1786 else if (uScalableBusHz <= CPUM_SBUSFREQ_267MHZ)
1787 *puValue = 0;
1788 else if (uScalableBusHz <= CPUM_SBUSFREQ_333MHZ)
1789 *puValue = 4;
1790 else /*if (uScalableBusHz <= CPUM_SBUSFREQ_400MHZ)*/
1791 *puValue = 6;
1792
1793 *puValue |= pRange->uValue & ~UINT64_C(0x7);
1794
1795 return VINF_SUCCESS;
1796}
1797
1798
1799/** @callback_method_impl{FNCPUMRDMSR} */
1800static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelPlatformInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1801{
1802 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1803
1804 /* Just indicate a fixed TSC, no turbo boost, no programmable anything. */
1805 PVM pVM = pVCpu->CTX_SUFF(pVM);
1806 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
1807 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
1808 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
1809 uint64_t uValue = ((uint32_t)uTscRatio << 8) /* TSC invariant frequency. */
1810 | ((uint64_t)uTscRatio << 40); /* The max turbo frequency. */
1811
1812 /* Ivy bridge has a minimum operating ratio as well. */
1813 if (true) /** @todo detect sandy bridge. */
1814 uValue |= (uint64_t)uTscRatio << 48;
1815
1816 *puValue = uValue;
1817 return VINF_SUCCESS;
1818}
1819
1820
1821/** @callback_method_impl{FNCPUMRDMSR} */
1822static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelFlexRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1823{
1824 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1825
1826 uint64_t uValue = pRange->uValue & ~UINT64_C(0x1ff00);
1827
1828 PVM pVM = pVCpu->CTX_SUFF(pVM);
1829 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
1830 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
1831 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
1832 uValue |= (uint32_t)uTscRatio << 8;
1833
1834 *puValue = uValue;
1835 return VINF_SUCCESS;
1836}
1837
1838
1839/** @callback_method_impl{FNCPUMWRMSR} */
1840static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelFlexRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1841{
1842 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1843 /** @todo implement writing MSR_FLEX_RATIO. */
1844 return VINF_SUCCESS;
1845}
1846
1847
1848/** @callback_method_impl{FNCPUMRDMSR} */
1849static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelPkgCStConfigControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1850{
1851 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1852 *puValue = pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl;
1853 return VINF_SUCCESS;
1854}
1855
1856
1857/** @callback_method_impl{FNCPUMWRMSR} */
1858static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelPkgCStConfigControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1859{
1860 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1861
1862 if (pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl & RT_BIT_64(15))
1863 {
1864 Log(("CPUM: WRMSR %#x (%s), %#llx: Write protected -> #GP\n", idMsr, pRange->szName, uValue));
1865 return VERR_CPUM_RAISE_GP_0;
1866 }
1867#if 0 /** @todo check what real (old) hardware does. */
1868 if ((uValue & 7) >= 5)
1869 {
1870 Log(("CPUM: WRMSR %#x (%s), %#llx: Invalid limit (%d) -> #GP\n", idMsr, pRange->szName, uValue, (uint32_t)(uValue & 7)));
1871 return VERR_CPUM_RAISE_GP_0;
1872 }
1873#endif
1874 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = uValue;
1875 return VINF_SUCCESS;
1876}
1877
1878
1879/** @callback_method_impl{FNCPUMRDMSR} */
1880static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelPmgIoCaptureBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1881{
1882 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1883 /** @todo implement I/O mwait wakeup. */
1884 *puValue = 0;
1885 return VINF_SUCCESS;
1886}
1887
1888
1889/** @callback_method_impl{FNCPUMWRMSR} */
1890static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelPmgIoCaptureBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1891{
1892 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1893 /** @todo implement I/O mwait wakeup. */
1894 return VINF_SUCCESS;
1895}
1896
1897
1898/** @callback_method_impl{FNCPUMRDMSR} */
1899static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchFromToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1900{
1901 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1902 /** @todo implement last branch records. */
1903 *puValue = 0;
1904 return VINF_SUCCESS;
1905}
1906
1907
1908/** @callback_method_impl{FNCPUMWRMSR} */
1909static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchFromToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1910{
1911 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1912 /** @todo implement last branch records. */
1913 return VINF_SUCCESS;
1914}
1915
1916
1917/** @callback_method_impl{FNCPUMRDMSR} */
1918static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchFromN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1919{
1920 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1921 /** @todo implement last branch records. */
1922 *puValue = 0;
1923 return VINF_SUCCESS;
1924}
1925
1926
1927/** @callback_method_impl{FNCPUMWRMSR} */
1928static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchFromN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1929{
1930 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
1931 /** @todo implement last branch records. */
1932 /** @todo Probing indicates that bit 63 is settable on SandyBridge, at least
1933 * if the rest of the bits are zero. Automatic sign extending?
1934 * Investigate! */
1935 if (!X86_IS_CANONICAL(uValue))
1936 {
1937 Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
1938 return VERR_CPUM_RAISE_GP_0;
1939 }
1940 return VINF_SUCCESS;
1941}
1942
1943
1944/** @callback_method_impl{FNCPUMRDMSR} */
1945static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1946{
1947 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1948 /** @todo implement last branch records. */
1949 *puValue = 0;
1950 return VINF_SUCCESS;
1951}
1952
1953
1954/** @callback_method_impl{FNCPUMWRMSR} */
1955static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1956{
1957 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1958 /** @todo implement last branch records. */
1959 /** @todo Probing indicates that bit 63 is settable on SandyBridge, at least
1960 * if the rest of the bits are zero. Automatic sign extending?
1961 * Investigate! */
1962 if (!X86_IS_CANONICAL(uValue))
1963 {
1964 Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
1965 return VERR_CPUM_RAISE_GP_0;
1966 }
1967 return VINF_SUCCESS;
1968}
1969
1970
1971/** @callback_method_impl{FNCPUMRDMSR} */
1972static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelLastBranchTos(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1973{
1974 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1975 /** @todo implement last branch records. */
1976 *puValue = 0;
1977 return VINF_SUCCESS;
1978}
1979
1980
1981/** @callback_method_impl{FNCPUMWRMSR} */
1982static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelLastBranchTos(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1983{
1984 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
1985 /** @todo implement last branch records. */
1986 return VINF_SUCCESS;
1987}
1988
1989
1990/** @callback_method_impl{FNCPUMRDMSR} */
1991static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelBblCrCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1992{
1993 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
1994 *puValue = pRange->uValue;
1995 return VINF_SUCCESS;
1996}
1997
1998
1999/** @callback_method_impl{FNCPUMWRMSR} */
2000static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelBblCrCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2001{
2002 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2003 return VINF_SUCCESS;
2004}
2005
2006
2007/** @callback_method_impl{FNCPUMRDMSR} */
2008static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelBblCrCtl3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2009{
2010 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2011 *puValue = pRange->uValue;
2012 return VINF_SUCCESS;
2013}
2014
2015
2016/** @callback_method_impl{FNCPUMWRMSR} */
2017static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelBblCrCtl3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2018{
2019 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2020 return VINF_SUCCESS;
2021}
2022
2023
2024/** @callback_method_impl{FNCPUMRDMSR} */
2025static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7TemperatureTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2026{
2027 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2028 *puValue = pRange->uValue;
2029 return VINF_SUCCESS;
2030}
2031
2032
2033/** @callback_method_impl{FNCPUMWRMSR} */
2034static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7TemperatureTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2035{
2036 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2037 return VINF_SUCCESS;
2038}
2039
2040
2041/** @callback_method_impl{FNCPUMRDMSR} */
2042static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7MsrOffCoreResponseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2043{
2044 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2045 /** @todo machine check. */
2046 *puValue = pRange->uValue;
2047 return VINF_SUCCESS;
2048}
2049
2050
2051/** @callback_method_impl{FNCPUMWRMSR} */
2052static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7MsrOffCoreResponseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2053{
2054 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2055 /** @todo machine check. */
2056 return VINF_SUCCESS;
2057}
2058
2059
2060/** @callback_method_impl{FNCPUMRDMSR} */
2061static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7MiscPwrMgmt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2062{
2063 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2064 *puValue = 0;
2065 return VINF_SUCCESS;
2066}
2067
2068
2069/** @callback_method_impl{FNCPUMWRMSR} */
2070static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7MiscPwrMgmt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2071{
2072 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2073 return VINF_SUCCESS;
2074}
2075
2076
2077/** @callback_method_impl{FNCPUMRDMSR} */
2078static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelP6CrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2079{
2080 RT_NOREF_PV(idMsr);
2081 int rc = CPUMGetGuestCRx(pVCpu, pRange->uValue, puValue);
2082 AssertRC(rc);
2083 return VINF_SUCCESS;
2084}
2085
2086
2087/** @callback_method_impl{FNCPUMWRMSR} */
2088static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelP6CrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2089{
2090 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2091 /* This CRx interface differs from the MOV CRx, GReg interface in that
2092 #GP(0) isn't raised if unsupported bits are written to. Instead they
2093 are simply ignored and masked off. (Pentium M Dothan) */
2094 /** @todo Implement MSR_P6_CRx writing. Too much effort for very little, if
2095 * any, gain. */
2096 return VINF_SUCCESS;
2097}
2098
2099
2100/** @callback_method_impl{FNCPUMRDMSR} */
2101static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCpuId1FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2102{
2103 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2104 /** @todo implement CPUID masking. */
2105 *puValue = UINT64_MAX;
2106 return VINF_SUCCESS;
2107}
2108
2109
2110/** @callback_method_impl{FNCPUMWRMSR} */
2111static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCpuId1FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2112{
2113 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2114 /** @todo implement CPUID masking. */
2115 return VINF_SUCCESS;
2116}
2117
2118
2119/** @callback_method_impl{FNCPUMRDMSR} */
2120static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCpuId1FeatureMaskEax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2121{
2122 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2123 /** @todo implement CPUID masking. */
2124 *puValue = 0;
2125 return VINF_SUCCESS;
2126}
2127
2128
2129/** @callback_method_impl{FNCPUMWRMSR} */
2130static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCpuId1FeatureMaskEax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2131{
2132 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2133 /** @todo implement CPUID masking. */
2134 return VINF_SUCCESS;
2135}
2136
2137
2138
2139/** @callback_method_impl{FNCPUMRDMSR} */
2140static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCpuId80000001FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2141{
2142 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2143 /** @todo implement CPUID masking. */
2144 *puValue = UINT64_MAX;
2145 return VINF_SUCCESS;
2146}
2147
2148
2149/** @callback_method_impl{FNCPUMWRMSR} */
2150static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCpuId80000001FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2151{
2152 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2153 /** @todo implement CPUID masking. */
2154 return VINF_SUCCESS;
2155}
2156
2157
2158
2159/** @callback_method_impl{FNCPUMRDMSR} */
2160static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyAesNiCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2161{
2162 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2163 /** @todo implement AES-NI. */
2164 *puValue = 3; /* Bit 0 is lock bit, bit 1 disables AES-NI. That's what they say. */
2165 return VINF_SUCCESS;
2166}
2167
2168
2169/** @callback_method_impl{FNCPUMWRMSR} */
2170static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyAesNiCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2171{
2172 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2173 /** @todo implement AES-NI. */
2174 return VERR_CPUM_RAISE_GP_0;
2175}
2176
2177
2178/** @callback_method_impl{FNCPUMRDMSR} */
2179static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7TurboRatioLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2180{
2181 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2182 /** @todo implement intel C states. */
2183 *puValue = pRange->uValue;
2184 return VINF_SUCCESS;
2185}
2186
2187
2188/** @callback_method_impl{FNCPUMWRMSR} */
2189static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7TurboRatioLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2190{
2191 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2192 /** @todo implement intel C states. */
2193 return VINF_SUCCESS;
2194}
2195
2196
2197/** @callback_method_impl{FNCPUMRDMSR} */
2198static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7LbrSelect(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2199{
2200 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2201 /** @todo implement last-branch-records. */
2202 *puValue = 0;
2203 return VINF_SUCCESS;
2204}
2205
2206
2207/** @callback_method_impl{FNCPUMWRMSR} */
2208static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7LbrSelect(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2209{
2210 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2211 /** @todo implement last-branch-records. */
2212 return VINF_SUCCESS;
2213}
2214
2215
2216/** @callback_method_impl{FNCPUMRDMSR} */
2217static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyErrorControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2218{
2219 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2220 /** @todo implement memory error injection (MSR_ERROR_CONTROL). */
2221 *puValue = 0;
2222 return VINF_SUCCESS;
2223}
2224
2225
2226/** @callback_method_impl{FNCPUMWRMSR} */
2227static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyErrorControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2228{
2229 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2230 /** @todo implement memory error injection (MSR_ERROR_CONTROL). */
2231 return VINF_SUCCESS;
2232}
2233
2234
2235/** @callback_method_impl{FNCPUMRDMSR} */
2236static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7VirtualLegacyWireCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2237{
2238 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2239 /** @todo implement memory VLW? */
2240 *puValue = pRange->uValue;
2241 /* Note: A20M is known to be bit 1 as this was disclosed in spec update
2242 AAJ49/AAK51/????, which documents the inversion of this bit. The
2243 Sandy bridge CPU here has value 0x74, so it probably doesn't have a BIOS
2244 that correct things. Some guesses at the other bits:
2245 bit 2 = INTR
2246 bit 4 = SMI
2247 bit 5 = INIT
2248 bit 6 = NMI */
2249 return VINF_SUCCESS;
2250}
2251
2252
2253/** @callback_method_impl{FNCPUMRDMSR} */
2254static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7PowerCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2255{
2256 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2257 /** @todo intel power management */
2258 *puValue = 0;
2259 return VINF_SUCCESS;
2260}
2261
2262
2263/** @callback_method_impl{FNCPUMWRMSR} */
2264static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7PowerCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2265{
2266 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2267 /** @todo intel power management */
2268 return VINF_SUCCESS;
2269}
2270
2271
2272/** @callback_method_impl{FNCPUMRDMSR} */
2273static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyPebsNumAlt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2274{
2275 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2276 /** @todo intel performance counters. */
2277 *puValue = 0;
2278 return VINF_SUCCESS;
2279}
2280
2281
2282/** @callback_method_impl{FNCPUMWRMSR} */
2283static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyPebsNumAlt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2284{
2285 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2286 /** @todo intel performance counters. */
2287 return VINF_SUCCESS;
2288}
2289
2290
2291/** @callback_method_impl{FNCPUMRDMSR} */
2292static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7PebsLdLat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2293{
2294 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2295 /** @todo intel performance counters. */
2296 *puValue = 0;
2297 return VINF_SUCCESS;
2298}
2299
2300
2301/** @callback_method_impl{FNCPUMWRMSR} */
2302static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7PebsLdLat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2303{
2304 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2305 /** @todo intel performance counters. */
2306 return VINF_SUCCESS;
2307}
2308
2309
2310/** @callback_method_impl{FNCPUMRDMSR} */
2311static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7PkgCnResidencyN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2312{
2313 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2314 /** @todo intel power management. */
2315 *puValue = 0;
2316 return VINF_SUCCESS;
2317}
2318
2319
2320/** @callback_method_impl{FNCPUMRDMSR} */
2321static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7CoreCnResidencyN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2322{
2323 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2324 /** @todo intel power management. */
2325 *puValue = 0;
2326 return VINF_SUCCESS;
2327}
2328
2329
2330/** @callback_method_impl{FNCPUMRDMSR} */
2331static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyVrCurrentConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2332{
2333 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2334 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2335 *puValue = 0;
2336 return VINF_SUCCESS;
2337}
2338
2339
2340/** @callback_method_impl{FNCPUMWRMSR} */
2341static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyVrCurrentConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2342{
2343 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2344 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2345 return VINF_SUCCESS;
2346}
2347
2348
2349/** @callback_method_impl{FNCPUMRDMSR} */
2350static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyVrMiscConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2351{
2352 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2353 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2354 *puValue = 0;
2355 return VINF_SUCCESS;
2356}
2357
2358
2359/** @callback_method_impl{FNCPUMWRMSR} */
2360static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyVrMiscConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2361{
2362 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2363 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2364 return VINF_SUCCESS;
2365}
2366
2367
2368/** @callback_method_impl{FNCPUMRDMSR} */
2369static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyRaplPowerUnit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2370{
2371 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2372 /** @todo intel RAPL. */
2373 *puValue = pRange->uValue;
2374 return VINF_SUCCESS;
2375}
2376
2377
2378/** @callback_method_impl{FNCPUMWRMSR} */
2379static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyRaplPowerUnit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2380{
2381 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2382 /* Note! This is documented as read only and except for a Silvermont sample has
2383 always been classified as read only. This is just here to make it compile. */
2384 return VINF_SUCCESS;
2385}
2386
2387
2388/** @callback_method_impl{FNCPUMRDMSR} */
2389static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyPkgCnIrtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2390{
2391 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2392 /** @todo intel power management. */
2393 *puValue = 0;
2394 return VINF_SUCCESS;
2395}
2396
2397
2398/** @callback_method_impl{FNCPUMWRMSR} */
2399static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyPkgCnIrtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2400{
2401 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2402 /** @todo intel power management. */
2403 return VINF_SUCCESS;
2404}
2405
2406
2407/** @callback_method_impl{FNCPUMRDMSR} */
2408static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyPkgC2Residency(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2409{
2410 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2411 /** @todo intel power management. */
2412 *puValue = 0;
2413 return VINF_SUCCESS;
2414}
2415
2416
2417/** @callback_method_impl{FNCPUMWRMSR} */
2418static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyPkgC2Residency(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2419{
2420 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2421 /* Note! This is documented as read only and except for a Silvermont sample has
2422 always been classified as read only. This is just here to make it compile. */
2423 return VINF_SUCCESS;
2424}
2425
2426
2427/** @callback_method_impl{FNCPUMRDMSR} */
2428static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2429{
2430 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2431 /** @todo intel RAPL. */
2432 *puValue = 0;
2433 return VINF_SUCCESS;
2434}
2435
2436
2437/** @callback_method_impl{FNCPUMWRMSR} */
2438static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPkgPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2439{
2440 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2441 /** @todo intel RAPL. */
2442 return VINF_SUCCESS;
2443}
2444
2445
2446/** @callback_method_impl{FNCPUMRDMSR} */
2447static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgEnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2448{
2449 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2450 /** @todo intel power management. */
2451 *puValue = 0;
2452 return VINF_SUCCESS;
2453}
2454
2455
2456/** @callback_method_impl{FNCPUMRDMSR} */
2457static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgPerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2458{
2459 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2460 /** @todo intel power management. */
2461 *puValue = 0;
2462 return VINF_SUCCESS;
2463}
2464
2465
2466/** @callback_method_impl{FNCPUMRDMSR} */
2467static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPkgPowerInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2468{
2469 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2470 /** @todo intel power management. */
2471 *puValue = 0;
2472 return VINF_SUCCESS;
2473}
2474
2475
2476/** @callback_method_impl{FNCPUMRDMSR} */
2477static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2478{
2479 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2480 /** @todo intel RAPL. */
2481 *puValue = 0;
2482 return VINF_SUCCESS;
2483}
2484
2485
2486/** @callback_method_impl{FNCPUMWRMSR} */
2487static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplDramPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2488{
2489 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2490 /** @todo intel RAPL. */
2491 return VINF_SUCCESS;
2492}
2493
2494
2495/** @callback_method_impl{FNCPUMRDMSR} */
2496static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramEnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2497{
2498 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2499 /** @todo intel power management. */
2500 *puValue = 0;
2501 return VINF_SUCCESS;
2502}
2503
2504
2505/** @callback_method_impl{FNCPUMRDMSR} */
2506static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramPerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2507{
2508 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2509 /** @todo intel power management. */
2510 *puValue = 0;
2511 return VINF_SUCCESS;
2512}
2513
2514
2515/** @callback_method_impl{FNCPUMRDMSR} */
2516static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplDramPowerInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2517{
2518 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2519 /** @todo intel power management. */
2520 *puValue = 0;
2521 return VINF_SUCCESS;
2522}
2523
2524
2525/** @callback_method_impl{FNCPUMRDMSR} */
2526static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2527{
2528 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2529 /** @todo intel RAPL. */
2530 *puValue = 0;
2531 return VINF_SUCCESS;
2532}
2533
2534
2535/** @callback_method_impl{FNCPUMWRMSR} */
2536static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp0PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2537{
2538 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2539 /** @todo intel RAPL. */
2540 return VINF_SUCCESS;
2541}
2542
2543
2544/** @callback_method_impl{FNCPUMRDMSR} */
2545static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0EnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2546{
2547 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2548 /** @todo intel power management. */
2549 *puValue = 0;
2550 return VINF_SUCCESS;
2551}
2552
2553
2554/** @callback_method_impl{FNCPUMRDMSR} */
2555static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2556{
2557 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2558 /** @todo intel RAPL. */
2559 *puValue = 0;
2560 return VINF_SUCCESS;
2561}
2562
2563
2564/** @callback_method_impl{FNCPUMWRMSR} */
2565static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp0Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2566{
2567 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2568 /** @todo intel RAPL. */
2569 return VINF_SUCCESS;
2570}
2571
2572
2573/** @callback_method_impl{FNCPUMRDMSR} */
2574static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp0PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2575{
2576 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2577 /** @todo intel power management. */
2578 *puValue = 0;
2579 return VINF_SUCCESS;
2580}
2581
2582
2583/** @callback_method_impl{FNCPUMRDMSR} */
2584static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp1PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2585{
2586 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2587 /** @todo intel RAPL. */
2588 *puValue = 0;
2589 return VINF_SUCCESS;
2590}
2591
2592
2593/** @callback_method_impl{FNCPUMWRMSR} */
2594static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp1PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2595{
2596 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2597 /** @todo intel RAPL. */
2598 return VINF_SUCCESS;
2599}
2600
2601
2602/** @callback_method_impl{FNCPUMRDMSR} */
2603static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp1EnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2604{
2605 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2606 /** @todo intel power management. */
2607 *puValue = 0;
2608 return VINF_SUCCESS;
2609}
2610
2611
2612/** @callback_method_impl{FNCPUMRDMSR} */
2613static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7RaplPp1Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2614{
2615 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2616 /** @todo intel RAPL. */
2617 *puValue = 0;
2618 return VINF_SUCCESS;
2619}
2620
2621
2622/** @callback_method_impl{FNCPUMWRMSR} */
2623static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7RaplPp1Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2624{
2625 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2626 /** @todo intel RAPL. */
2627 return VINF_SUCCESS;
2628}
2629
2630
2631/** @callback_method_impl{FNCPUMRDMSR} */
2632static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpNominal(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2633{
2634 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2635 /** @todo intel power management. */
2636 *puValue = pRange->uValue;
2637 return VINF_SUCCESS;
2638}
2639
2640
2641/** @callback_method_impl{FNCPUMRDMSR} */
2642static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpLevel1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2643{
2644 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2645 /** @todo intel power management. */
2646 *puValue = pRange->uValue;
2647 return VINF_SUCCESS;
2648}
2649
2650
2651/** @callback_method_impl{FNCPUMRDMSR} */
2652static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpLevel2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2653{
2654 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2655 /** @todo intel power management. */
2656 *puValue = pRange->uValue;
2657 return VINF_SUCCESS;
2658}
2659
2660
2661/** @callback_method_impl{FNCPUMRDMSR} */
2662static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyConfigTdpControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2663{
2664 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2665 /** @todo intel power management. */
2666 *puValue = 0;
2667 return VINF_SUCCESS;
2668}
2669
2670
2671/** @callback_method_impl{FNCPUMWRMSR} */
2672static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7IvyConfigTdpControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2673{
2674 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2675 /** @todo intel power management. */
2676 return VINF_SUCCESS;
2677}
2678
2679
2680/** @callback_method_impl{FNCPUMRDMSR} */
2681static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7IvyTurboActivationRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2682{
2683 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2684 /** @todo intel power management. */
2685 *puValue = 0;
2686 return VINF_SUCCESS;
2687}
2688
2689
2690/** @callback_method_impl{FNCPUMWRMSR} */
2691static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7IvyTurboActivationRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2692{
2693 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2694 /** @todo intel power management. */
2695 return VINF_SUCCESS;
2696}
2697
2698
2699/** @callback_method_impl{FNCPUMRDMSR} */
2700static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2701{
2702 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2703 /** @todo uncore msrs. */
2704 *puValue = 0;
2705 return VINF_SUCCESS;
2706}
2707
2708
2709/** @callback_method_impl{FNCPUMWRMSR} */
2710static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2711{
2712 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2713 /** @todo uncore msrs. */
2714 return VINF_SUCCESS;
2715}
2716
2717
2718/** @callback_method_impl{FNCPUMRDMSR} */
2719static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2720{
2721 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2722 /** @todo uncore msrs. */
2723 *puValue = 0;
2724 return VINF_SUCCESS;
2725}
2726
2727
2728/** @callback_method_impl{FNCPUMWRMSR} */
2729static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2730{
2731 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2732 /** @todo uncore msrs. */
2733 return VINF_SUCCESS;
2734}
2735
2736
2737/** @callback_method_impl{FNCPUMRDMSR} */
2738static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2739{
2740 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2741 /** @todo uncore msrs. */
2742 *puValue = 0;
2743 return VINF_SUCCESS;
2744}
2745
2746
2747/** @callback_method_impl{FNCPUMWRMSR} */
2748static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2749{
2750 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2751 /** @todo uncore msrs. */
2752 return VINF_SUCCESS;
2753}
2754
2755
2756/** @callback_method_impl{FNCPUMRDMSR} */
2757static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfFixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2758{
2759 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2760 /** @todo uncore msrs. */
2761 *puValue = 0;
2762 return VINF_SUCCESS;
2763}
2764
2765
2766/** @callback_method_impl{FNCPUMWRMSR} */
2767static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfFixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2768{
2769 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2770 /** @todo uncore msrs. */
2771 return VINF_SUCCESS;
2772}
2773
2774
2775/** @callback_method_impl{FNCPUMRDMSR} */
2776static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncPerfFixedCtr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2777{
2778 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2779 /** @todo uncore msrs. */
2780 *puValue = 0;
2781 return VINF_SUCCESS;
2782}
2783
2784
2785/** @callback_method_impl{FNCPUMWRMSR} */
2786static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncPerfFixedCtr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2787{
2788 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2789 /** @todo uncore msrs. */
2790 return VINF_SUCCESS;
2791}
2792
2793
2794/** @callback_method_impl{FNCPUMRDMSR} */
2795static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncCBoxConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2796{
2797 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2798 /** @todo uncore msrs. */
2799 *puValue = 0;
2800 return VINF_SUCCESS;
2801}
2802
2803
2804/** @callback_method_impl{FNCPUMRDMSR} */
2805static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncArbPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2806{
2807 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2808 /** @todo uncore msrs. */
2809 *puValue = 0;
2810 return VINF_SUCCESS;
2811}
2812
2813
2814/** @callback_method_impl{FNCPUMWRMSR} */
2815static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncArbPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2816{
2817 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2818 /** @todo uncore msrs. */
2819 return VINF_SUCCESS;
2820}
2821
2822
2823/** @callback_method_impl{FNCPUMRDMSR} */
2824static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7UncArbPerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2825{
2826 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2827 /** @todo uncore msrs. */
2828 *puValue = 0;
2829 return VINF_SUCCESS;
2830}
2831
2832
2833/** @callback_method_impl{FNCPUMWRMSR} */
2834static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7UncArbPerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2835{
2836 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2837 /** @todo uncore msrs. */
2838 return VINF_SUCCESS;
2839}
2840
2841
2842/** @callback_method_impl{FNCPUMRDMSR} */
2843static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SmiCount(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2844{
2845 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2846
2847 /*
2848 * 31:0 is SMI count (read only), 63:32 reserved.
2849 * Since we don't do SMI, the count is always zero.
2850 */
2851 *puValue = 0;
2852 return VINF_SUCCESS;
2853}
2854
2855
2856/** @callback_method_impl{FNCPUMRDMSR} */
2857static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore2EmttmCrTablesN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2858{
2859 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2860 /** @todo implement enhanced multi thread termal monitoring? */
2861 *puValue = pRange->uValue;
2862 return VINF_SUCCESS;
2863}
2864
2865
2866/** @callback_method_impl{FNCPUMWRMSR} */
2867static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore2EmttmCrTablesN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2868{
2869 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2870 /** @todo implement enhanced multi thread termal monitoring? */
2871 return VINF_SUCCESS;
2872}
2873
2874
2875/** @callback_method_impl{FNCPUMRDMSR} */
2876static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore2SmmCStMiscInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2877{
2878 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2879 /** @todo SMM & C-states? */
2880 *puValue = 0;
2881 return VINF_SUCCESS;
2882}
2883
2884
2885/** @callback_method_impl{FNCPUMWRMSR} */
2886static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore2SmmCStMiscInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2887{
2888 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2889 /** @todo SMM & C-states? */
2890 return VINF_SUCCESS;
2891}
2892
2893
2894/** @callback_method_impl{FNCPUMRDMSR} */
2895static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore1ExtConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2896{
2897 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2898 /** @todo Core1&2 EXT_CONFIG (whatever that is)? */
2899 *puValue = 0;
2900 return VINF_SUCCESS;
2901}
2902
2903
2904/** @callback_method_impl{FNCPUMWRMSR} */
2905static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore1ExtConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2906{
2907 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2908 /** @todo Core1&2 EXT_CONFIG (whatever that is)? */
2909 return VINF_SUCCESS;
2910}
2911
2912
2913/** @callback_method_impl{FNCPUMRDMSR} */
2914static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore1DtsCalControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2915{
2916 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2917 /** @todo Core1&2(?) DTS_CAL_CTRL (whatever that is)? */
2918 *puValue = 0;
2919 return VINF_SUCCESS;
2920}
2921
2922
2923/** @callback_method_impl{FNCPUMWRMSR} */
2924static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore1DtsCalControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2925{
2926 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2927 /** @todo Core1&2(?) DTS_CAL_CTRL (whatever that is)? */
2928 return VINF_SUCCESS;
2929}
2930
2931
2932/** @callback_method_impl{FNCPUMRDMSR} */
2933static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore2PeciControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2934{
2935 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2936 /** @todo Core2+ platform environment control interface control register? */
2937 *puValue = 0;
2938 return VINF_SUCCESS;
2939}
2940
2941
2942/** @callback_method_impl{FNCPUMWRMSR} */
2943static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelCore2PeciControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2944{
2945 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
2946 /** @todo Core2+ platform environment control interface control register? */
2947 return VINF_SUCCESS;
2948}
2949
2950
2951/** @callback_method_impl{FNCPUMRDMSR} */
2952static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelAtSilvCoreC1Recidency(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2953{
2954 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2955 *puValue = 0;
2956 return VINF_SUCCESS;
2957}
2958
2959
2960/*
2961 * Multiple vendor P6 MSRs.
2962 * Multiple vendor P6 MSRs.
2963 * Multiple vendor P6 MSRs.
2964 *
2965 * These MSRs were introduced with the P6 but not elevated to architectural
2966 * MSRs, despite other vendors implementing them.
2967 */
2968
2969
2970/** @callback_method_impl{FNCPUMRDMSR} */
2971static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastBranchFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2972{
2973 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2974 /* AMD seems to just record RIP, while intel claims to record RIP+CS.BASE
2975 if I read the docs correctly, thus the need for separate functions. */
2976 /** @todo implement last branch records. */
2977 *puValue = 0;
2978 return VINF_SUCCESS;
2979}
2980
2981
2982/** @callback_method_impl{FNCPUMRDMSR} */
2983static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastBranchToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2984{
2985 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2986 /** @todo implement last branch records. */
2987 *puValue = 0;
2988 return VINF_SUCCESS;
2989}
2990
2991
2992/** @callback_method_impl{FNCPUMRDMSR} */
2993static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastIntFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2994{
2995 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
2996 /** @todo implement last exception records. */
2997 *puValue = 0;
2998 return VINF_SUCCESS;
2999}
3000
3001
3002/** @callback_method_impl{FNCPUMWRMSR} */
3003static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_P6LastIntFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3004{
3005 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3006 /** @todo implement last exception records. */
3007 /* Note! On many CPUs, the high bit of the 0x000001dd register is always writable, even when the result is
3008 a non-cannonical address. */
3009 return VINF_SUCCESS;
3010}
3011
3012
3013/** @callback_method_impl{FNCPUMRDMSR} */
3014static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_P6LastIntToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3015{
3016 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3017 /** @todo implement last exception records. */
3018 *puValue = 0;
3019 return VINF_SUCCESS;
3020}
3021
3022
3023/** @callback_method_impl{FNCPUMWRMSR} */
3024static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_P6LastIntToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3025{
3026 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3027 /** @todo implement last exception records. */
3028 return VINF_SUCCESS;
3029}
3030
3031
3032
3033/*
3034 * AMD specific
3035 * AMD specific
3036 * AMD specific
3037 */
3038
3039
3040/** @callback_method_impl{FNCPUMRDMSR} */
3041static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hTscRate(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3042{
3043 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3044 /** @todo Implement TscRateMsr */
3045 *puValue = RT_MAKE_U64(0, 1); /* 1.0 = reset value. */
3046 return VINF_SUCCESS;
3047}
3048
3049
3050/** @callback_method_impl{FNCPUMWRMSR} */
3051static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hTscRate(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3052{
3053 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3054 /** @todo Implement TscRateMsr */
3055 return VINF_SUCCESS;
3056}
3057
3058
3059/** @callback_method_impl{FNCPUMRDMSR} */
3060static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hLwpCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3061{
3062 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3063 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
3064 /* Note: Only listes in BKDG for Family 15H. */
3065 *puValue = 0;
3066 return VINF_SUCCESS;
3067}
3068
3069
3070/** @callback_method_impl{FNCPUMWRMSR} */
3071static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hLwpCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3072{
3073 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3074 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
3075 return VINF_SUCCESS;
3076}
3077
3078
3079/** @callback_method_impl{FNCPUMRDMSR} */
3080static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hLwpCbAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3081{
3082 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3083 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
3084 /* Note: Only listes in BKDG for Family 15H. */
3085 *puValue = 0;
3086 return VINF_SUCCESS;
3087}
3088
3089
3090/** @callback_method_impl{FNCPUMWRMSR} */
3091static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hLwpCbAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3092{
3093 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3094 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
3095 return VINF_SUCCESS;
3096}
3097
3098
3099/** @callback_method_impl{FNCPUMRDMSR} */
3100static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hMc4MiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3101{
3102 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3103 /** @todo machine check. */
3104 *puValue = 0;
3105 return VINF_SUCCESS;
3106}
3107
3108
3109/** @callback_method_impl{FNCPUMWRMSR} */
3110static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hMc4MiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3111{
3112 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3113 /** @todo machine check. */
3114 return VINF_SUCCESS;
3115}
3116
3117
3118/** @callback_method_impl{FNCPUMRDMSR} */
3119static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8PerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3120{
3121 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3122 /** @todo AMD performance events. */
3123 *puValue = 0;
3124 return VINF_SUCCESS;
3125}
3126
3127
3128/** @callback_method_impl{FNCPUMWRMSR} */
3129static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8PerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3130{
3131 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3132 /** @todo AMD performance events. */
3133 return VINF_SUCCESS;
3134}
3135
3136
3137/** @callback_method_impl{FNCPUMRDMSR} */
3138static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8PerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3139{
3140 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3141 /** @todo AMD performance events. */
3142 *puValue = 0;
3143 return VINF_SUCCESS;
3144}
3145
3146
3147/** @callback_method_impl{FNCPUMWRMSR} */
3148static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8PerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3149{
3150 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3151 /** @todo AMD performance events. */
3152 return VINF_SUCCESS;
3153}
3154
3155
3156/** @callback_method_impl{FNCPUMRDMSR} */
3157static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SysCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3158{
3159 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3160 /** @todo AMD SYS_CFG */
3161 *puValue = pRange->uValue;
3162 return VINF_SUCCESS;
3163}
3164
3165
3166/** @callback_method_impl{FNCPUMWRMSR} */
3167static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SysCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3168{
3169 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3170 /** @todo AMD SYS_CFG */
3171 return VINF_SUCCESS;
3172}
3173
3174
3175/** @callback_method_impl{FNCPUMRDMSR} */
3176static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8HwCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3177{
3178 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3179 /** @todo AMD HW_CFG */
3180 *puValue = 0;
3181 return VINF_SUCCESS;
3182}
3183
3184
3185/** @callback_method_impl{FNCPUMWRMSR} */
3186static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8HwCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3187{
3188 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3189 /** @todo AMD HW_CFG */
3190 return VINF_SUCCESS;
3191}
3192
3193
3194/** @callback_method_impl{FNCPUMRDMSR} */
3195static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IorrBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3196{
3197 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3198 /** @todo AMD IorrMask/IorrBase */
3199 *puValue = 0;
3200 return VINF_SUCCESS;
3201}
3202
3203
3204/** @callback_method_impl{FNCPUMWRMSR} */
3205static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IorrBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3206{
3207 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3208 /** @todo AMD IorrMask/IorrBase */
3209 return VINF_SUCCESS;
3210}
3211
3212
3213/** @callback_method_impl{FNCPUMRDMSR} */
3214static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IorrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3215{
3216 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3217 /** @todo AMD IorrMask/IorrBase */
3218 *puValue = 0;
3219 return VINF_SUCCESS;
3220}
3221
3222
3223/** @callback_method_impl{FNCPUMWRMSR} */
3224static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IorrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3225{
3226 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3227 /** @todo AMD IorrMask/IorrBase */
3228 return VINF_SUCCESS;
3229}
3230
3231
3232/** @callback_method_impl{FNCPUMRDMSR} */
3233static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8TopOfMemN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3234{
3235 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3236 *puValue = 0;
3237 /** @todo return 4GB - RamHoleSize here for TOPMEM. Figure out what to return
3238 * for TOPMEM2. */
3239 //if (pRange->uValue == 0)
3240 // *puValue = _4G - RamHoleSize;
3241 return VINF_SUCCESS;
3242}
3243
3244
3245/** @callback_method_impl{FNCPUMWRMSR} */
3246static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8TopOfMemN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3247{
3248 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3249 /** @todo AMD TOPMEM and TOPMEM2/TOM2. */
3250 return VINF_SUCCESS;
3251}
3252
3253
3254/** @callback_method_impl{FNCPUMRDMSR} */
3255static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8NbCfg1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3256{
3257 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3258 /** @todo AMD NB_CFG1 */
3259 *puValue = 0;
3260 return VINF_SUCCESS;
3261}
3262
3263
3264/** @callback_method_impl{FNCPUMWRMSR} */
3265static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8NbCfg1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3266{
3267 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3268 /** @todo AMD NB_CFG1 */
3269 return VINF_SUCCESS;
3270}
3271
3272
3273/** @callback_method_impl{FNCPUMRDMSR} */
3274static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8McXcptRedir(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3275{
3276 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3277 /** @todo machine check. */
3278 *puValue = 0;
3279 return VINF_SUCCESS;
3280}
3281
3282
3283/** @callback_method_impl{FNCPUMWRMSR} */
3284static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8McXcptRedir(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3285{
3286 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3287 /** @todo machine check. */
3288 return VINF_SUCCESS;
3289}
3290
3291
3292/** @callback_method_impl{FNCPUMRDMSR} */
3293static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuNameN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3294{
3295 RT_NOREF_PV(idMsr);
3296 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), pRange->uValue / 2 + 0x80000001);
3297 if (pLeaf)
3298 {
3299 if (!(pRange->uValue & 1))
3300 *puValue = RT_MAKE_U64(pLeaf->uEax, pLeaf->uEbx);
3301 else
3302 *puValue = RT_MAKE_U64(pLeaf->uEcx, pLeaf->uEdx);
3303 }
3304 else
3305 *puValue = 0;
3306 return VINF_SUCCESS;
3307}
3308
3309
3310/** @callback_method_impl{FNCPUMWRMSR} */
3311static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuNameN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3312{
3313 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3314 /** @todo Remember guest programmed CPU name. */
3315 return VINF_SUCCESS;
3316}
3317
3318
3319/** @callback_method_impl{FNCPUMRDMSR} */
3320static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8HwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3321{
3322 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3323 /** @todo AMD HTC. */
3324 *puValue = pRange->uValue;
3325 return VINF_SUCCESS;
3326}
3327
3328
3329/** @callback_method_impl{FNCPUMWRMSR} */
3330static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8HwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3331{
3332 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3333 /** @todo AMD HTC. */
3334 return VINF_SUCCESS;
3335}
3336
3337
3338/** @callback_method_impl{FNCPUMRDMSR} */
3339static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3340{
3341 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3342 /** @todo AMD STC. */
3343 *puValue = 0;
3344 return VINF_SUCCESS;
3345}
3346
3347
3348/** @callback_method_impl{FNCPUMWRMSR} */
3349static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3350{
3351 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3352 /** @todo AMD STC. */
3353 return VINF_SUCCESS;
3354}
3355
3356
3357/** @callback_method_impl{FNCPUMRDMSR} */
3358static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8FidVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3359{
3360 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3361 /** @todo AMD FIDVID_CTL. */
3362 *puValue = pRange->uValue;
3363 return VINF_SUCCESS;
3364}
3365
3366
3367/** @callback_method_impl{FNCPUMWRMSR} */
3368static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8FidVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3369{
3370 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3371 /** @todo AMD FIDVID_CTL. */
3372 return VINF_SUCCESS;
3373}
3374
3375
3376/** @callback_method_impl{FNCPUMRDMSR} */
3377static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8FidVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3378{
3379 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3380 /** @todo AMD FIDVID_STATUS. */
3381 *puValue = pRange->uValue;
3382 return VINF_SUCCESS;
3383}
3384
3385
3386/** @callback_method_impl{FNCPUMRDMSR} */
3387static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8McCtlMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3388{
3389 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3390 /** @todo AMD MC. */
3391 *puValue = 0;
3392 return VINF_SUCCESS;
3393}
3394
3395
3396/** @callback_method_impl{FNCPUMWRMSR} */
3397static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8McCtlMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3398{
3399 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3400 /** @todo AMD MC. */
3401 return VINF_SUCCESS;
3402}
3403
3404
3405/** @callback_method_impl{FNCPUMRDMSR} */
3406static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmiOnIoTrapN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3407{
3408 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3409 /** @todo AMD SMM/SMI and I/O trap. */
3410 *puValue = 0;
3411 return VINF_SUCCESS;
3412}
3413
3414
3415/** @callback_method_impl{FNCPUMWRMSR} */
3416static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmiOnIoTrapN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3417{
3418 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3419 /** @todo AMD SMM/SMI and I/O trap. */
3420 return VINF_SUCCESS;
3421}
3422
3423
3424/** @callback_method_impl{FNCPUMRDMSR} */
3425static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmiOnIoTrapCtlSts(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3426{
3427 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3428 /** @todo AMD SMM/SMI and I/O trap. */
3429 *puValue = 0;
3430 return VINF_SUCCESS;
3431}
3432
3433
3434/** @callback_method_impl{FNCPUMWRMSR} */
3435static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmiOnIoTrapCtlSts(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3436{
3437 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3438 /** @todo AMD SMM/SMI and I/O trap. */
3439 return VINF_SUCCESS;
3440}
3441
3442
3443/** @callback_method_impl{FNCPUMRDMSR} */
3444static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IntPendingMessage(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3445{
3446 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3447 /** @todo Interrupt pending message. */
3448 *puValue = 0;
3449 return VINF_SUCCESS;
3450}
3451
3452
3453/** @callback_method_impl{FNCPUMWRMSR} */
3454static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IntPendingMessage(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3455{
3456 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3457 /** @todo Interrupt pending message. */
3458 return VINF_SUCCESS;
3459}
3460
3461
3462/** @callback_method_impl{FNCPUMRDMSR} */
3463static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmiTriggerIoCycle(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3464{
3465 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3466 /** @todo AMD SMM/SMI and trigger I/O cycle. */
3467 *puValue = 0;
3468 return VINF_SUCCESS;
3469}
3470
3471
3472/** @callback_method_impl{FNCPUMWRMSR} */
3473static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmiTriggerIoCycle(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3474{
3475 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3476 /** @todo AMD SMM/SMI and trigger I/O cycle. */
3477 return VINF_SUCCESS;
3478}
3479
3480
3481/** @callback_method_impl{FNCPUMRDMSR} */
3482static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hMmioCfgBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3483{
3484 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3485 /** @todo AMD MMIO Configuration base address. */
3486 *puValue = 0;
3487 return VINF_SUCCESS;
3488}
3489
3490
3491/** @callback_method_impl{FNCPUMWRMSR} */
3492static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hMmioCfgBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3493{
3494 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3495 /** @todo AMD MMIO Configuration base address. */
3496 return VINF_SUCCESS;
3497}
3498
3499
3500/** @callback_method_impl{FNCPUMRDMSR} */
3501static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hTrapCtlMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3502{
3503 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3504 /** @todo AMD 0xc0010059. */
3505 *puValue = 0;
3506 return VINF_SUCCESS;
3507}
3508
3509
3510/** @callback_method_impl{FNCPUMWRMSR} */
3511static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hTrapCtlMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3512{
3513 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3514 /** @todo AMD 0xc0010059. */
3515 return VINF_SUCCESS;
3516}
3517
3518
3519/** @callback_method_impl{FNCPUMRDMSR} */
3520static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateCurLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3521{
3522 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3523 /** @todo AMD P-states. */
3524 *puValue = pRange->uValue;
3525 return VINF_SUCCESS;
3526}
3527
3528
3529/** @callback_method_impl{FNCPUMRDMSR} */
3530static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3531{
3532 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3533 /** @todo AMD P-states. */
3534 *puValue = pRange->uValue;
3535 return VINF_SUCCESS;
3536}
3537
3538
3539/** @callback_method_impl{FNCPUMWRMSR} */
3540static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hPStateControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3541{
3542 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3543 /** @todo AMD P-states. */
3544 return VINF_SUCCESS;
3545}
3546
3547
3548/** @callback_method_impl{FNCPUMRDMSR} */
3549static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3550{
3551 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3552 /** @todo AMD P-states. */
3553 *puValue = pRange->uValue;
3554 return VINF_SUCCESS;
3555}
3556
3557
3558/** @callback_method_impl{FNCPUMWRMSR} */
3559static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hPStateStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3560{
3561 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3562 /** @todo AMD P-states. */
3563 return VINF_SUCCESS;
3564}
3565
3566
3567/** @callback_method_impl{FNCPUMRDMSR} */
3568static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hPStateN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3569{
3570 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3571 /** @todo AMD P-states. */
3572 *puValue = pRange->uValue;
3573 return VINF_SUCCESS;
3574}
3575
3576
3577/** @callback_method_impl{FNCPUMWRMSR} */
3578static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hPStateN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3579{
3580 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3581 /** @todo AMD P-states. */
3582 return VINF_SUCCESS;
3583}
3584
3585
3586/** @callback_method_impl{FNCPUMRDMSR} */
3587static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCofVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3588{
3589 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3590 /** @todo AMD P-states. */
3591 *puValue = pRange->uValue;
3592 return VINF_SUCCESS;
3593}
3594
3595
3596/** @callback_method_impl{FNCPUMWRMSR} */
3597static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCofVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3598{
3599 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3600 /** @todo AMD P-states. */
3601 return VINF_SUCCESS;
3602}
3603
3604
3605/** @callback_method_impl{FNCPUMRDMSR} */
3606static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCofVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3607{
3608 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3609 /** @todo AMD P-states. */
3610 *puValue = pRange->uValue;
3611 return VINF_SUCCESS;
3612}
3613
3614
3615/** @callback_method_impl{FNCPUMWRMSR} */
3616static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCofVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3617{
3618 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3619 /* Note! Writing 0 seems to not GP, not sure if it does anything to the value... */
3620 /** @todo AMD P-states. */
3621 return VINF_SUCCESS;
3622}
3623
3624
3625/** @callback_method_impl{FNCPUMRDMSR} */
3626static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCStateIoBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3627{
3628 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3629 /** @todo AMD C-states. */
3630 *puValue = 0;
3631 return VINF_SUCCESS;
3632}
3633
3634
3635/** @callback_method_impl{FNCPUMWRMSR} */
3636static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCStateIoBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3637{
3638 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3639 /** @todo AMD C-states. */
3640 return VINF_SUCCESS;
3641}
3642
3643
3644/** @callback_method_impl{FNCPUMRDMSR} */
3645static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hCpuWatchdogTimer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3646{
3647 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3648 /** @todo AMD machine checks. */
3649 *puValue = 0;
3650 return VINF_SUCCESS;
3651}
3652
3653
3654/** @callback_method_impl{FNCPUMWRMSR} */
3655static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hCpuWatchdogTimer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3656{
3657 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3658 /** @todo AMD machine checks. */
3659 return VINF_SUCCESS;
3660}
3661
3662
3663/** @callback_method_impl{FNCPUMRDMSR} */
3664static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3665{
3666 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3667 /** @todo AMD SMM. */
3668 *puValue = 0;
3669 return VINF_SUCCESS;
3670}
3671
3672
3673/** @callback_method_impl{FNCPUMWRMSR} */
3674static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3675{
3676 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3677 /** @todo AMD SMM. */
3678 return VINF_SUCCESS;
3679}
3680
3681
3682/** @callback_method_impl{FNCPUMRDMSR} */
3683static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3684{
3685 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3686 /** @todo AMD SMM. */
3687 *puValue = 0;
3688 return VINF_SUCCESS;
3689}
3690
3691
3692/** @callback_method_impl{FNCPUMWRMSR} */
3693static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3694{
3695 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3696 /** @todo AMD SMM. */
3697 return VINF_SUCCESS;
3698}
3699
3700
3701
3702/** @callback_method_impl{FNCPUMRDMSR} */
3703static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3704{
3705 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3706 /** @todo AMD SMM. */
3707 *puValue = 0;
3708 return VINF_SUCCESS;
3709}
3710
3711
3712/** @callback_method_impl{FNCPUMWRMSR} */
3713static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3714{
3715 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3716 /** @todo AMD SMM. */
3717 return VINF_SUCCESS;
3718}
3719
3720
3721/** @callback_method_impl{FNCPUMRDMSR} */
3722static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8VmCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3723{
3724 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3725 PVM pVM = pVCpu->CTX_SUFF(pVM);
3726 if (pVM->cpum.s.GuestFeatures.fSvm)
3727 *puValue = MSR_K8_VM_CR_LOCK;
3728 else
3729 *puValue = 0;
3730 return VINF_SUCCESS;
3731}
3732
3733
3734/** @callback_method_impl{FNCPUMWRMSR} */
3735static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8VmCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3736{
3737 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
3738 PVM pVM = pVCpu->CTX_SUFF(pVM);
3739 if (pVM->cpum.s.GuestFeatures.fSvm)
3740 {
3741 /* Silently ignore writes to LOCK and SVM_DISABLE bit when the LOCK bit is set (see cpumMsrRd_AmdK8VmCr). */
3742 if (uValue & (MSR_K8_VM_CR_DPD | MSR_K8_VM_CR_R_INIT | MSR_K8_VM_CR_DIS_A20M))
3743 return VERR_CPUM_RAISE_GP_0;
3744 return VINF_SUCCESS;
3745 }
3746 return VERR_CPUM_RAISE_GP_0;
3747}
3748
3749
3750/** @callback_method_impl{FNCPUMRDMSR} */
3751static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8IgnNe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3752{
3753 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3754 /** @todo AMD IGNNE\# control. */
3755 *puValue = 0;
3756 return VINF_SUCCESS;
3757}
3758
3759
3760/** @callback_method_impl{FNCPUMWRMSR} */
3761static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8IgnNe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3762{
3763 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3764 /** @todo AMD IGNNE\# control. */
3765 return VINF_SUCCESS;
3766}
3767
3768
3769/** @callback_method_impl{FNCPUMRDMSR} */
3770static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8SmmCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3771{
3772 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3773 /** @todo AMD SMM. */
3774 *puValue = 0;
3775 return VINF_SUCCESS;
3776}
3777
3778
3779/** @callback_method_impl{FNCPUMWRMSR} */
3780static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8SmmCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3781{
3782 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3783 /** @todo AMD SMM. */
3784 return VINF_SUCCESS;
3785}
3786
3787
3788/** @callback_method_impl{FNCPUMRDMSR} */
3789static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8VmHSavePa(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3790{
3791 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3792 *puValue = pVCpu->cpum.s.Guest.hwvirt.svm.uMsrHSavePa;
3793 return VINF_SUCCESS;
3794}
3795
3796
3797/** @callback_method_impl{FNCPUMWRMSR} */
3798static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8VmHSavePa(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3799{
3800 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
3801 if (uValue & UINT64_C(0xfff))
3802 {
3803 Log(("CPUM: Invalid setting of low 12 bits set writing host-state save area MSR %#x: %#llx\n", idMsr, uValue));
3804 return VERR_CPUM_RAISE_GP_0;
3805 }
3806
3807 uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
3808 if (fInvPhysMask & uValue)
3809 {
3810 Log(("CPUM: Invalid physical address bits set writing host-state save area MSR %#x: %#llx (%#llx)\n",
3811 idMsr, uValue, uValue & fInvPhysMask));
3812 return VERR_CPUM_RAISE_GP_0;
3813 }
3814
3815 pVCpu->cpum.s.Guest.hwvirt.svm.uMsrHSavePa = uValue;
3816 return VINF_SUCCESS;
3817}
3818
3819
3820/** @callback_method_impl{FNCPUMRDMSR} */
3821static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hVmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3822{
3823 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3824 /** @todo AMD SVM. */
3825 *puValue = 0; /* RAZ */
3826 return VINF_SUCCESS;
3827}
3828
3829
3830/** @callback_method_impl{FNCPUMWRMSR} */
3831static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hVmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3832{
3833 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3834 /** @todo AMD SVM. */
3835 return VINF_SUCCESS;
3836}
3837
3838
3839/** @callback_method_impl{FNCPUMRDMSR} */
3840static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hSmmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3841{
3842 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3843 /** @todo AMD SMM. */
3844 *puValue = 0; /* RAZ */
3845 return VINF_SUCCESS;
3846}
3847
3848
3849/** @callback_method_impl{FNCPUMWRMSR} */
3850static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hSmmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3851{
3852 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3853 /** @todo AMD SMM. */
3854 return VINF_SUCCESS;
3855}
3856
3857
3858/** @callback_method_impl{FNCPUMRDMSR} */
3859static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hLocalSmiStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3860{
3861 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3862 /** @todo AMD SMM/SMI. */
3863 *puValue = 0;
3864 return VINF_SUCCESS;
3865}
3866
3867
3868/** @callback_method_impl{FNCPUMWRMSR} */
3869static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hLocalSmiStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3870{
3871 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3872 /** @todo AMD SMM/SMI. */
3873 return VINF_SUCCESS;
3874}
3875
3876
3877/** @callback_method_impl{FNCPUMRDMSR} */
3878static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hOsVisWrkIdLength(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3879{
3880 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr);
3881 /** @todo AMD OS visible workaround. */
3882 *puValue = pRange->uValue;
3883 return VINF_SUCCESS;
3884}
3885
3886
3887/** @callback_method_impl{FNCPUMWRMSR} */
3888static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hOsVisWrkIdLength(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3889{
3890 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3891 /** @todo AMD OS visible workaround. */
3892 return VINF_SUCCESS;
3893}
3894
3895
3896/** @callback_method_impl{FNCPUMRDMSR} */
3897static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hOsVisWrkStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3898{
3899 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3900 /** @todo AMD OS visible workaround. */
3901 *puValue = 0;
3902 return VINF_SUCCESS;
3903}
3904
3905
3906/** @callback_method_impl{FNCPUMWRMSR} */
3907static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hOsVisWrkStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3908{
3909 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3910 /** @todo AMD OS visible workaround. */
3911 return VINF_SUCCESS;
3912}
3913
3914
3915/** @callback_method_impl{FNCPUMRDMSR} */
3916static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam16hL2IPerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3917{
3918 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3919 /** @todo AMD L2I performance counters. */
3920 *puValue = 0;
3921 return VINF_SUCCESS;
3922}
3923
3924
3925/** @callback_method_impl{FNCPUMWRMSR} */
3926static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam16hL2IPerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3927{
3928 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3929 /** @todo AMD L2I performance counters. */
3930 return VINF_SUCCESS;
3931}
3932
3933
3934/** @callback_method_impl{FNCPUMRDMSR} */
3935static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam16hL2IPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3936{
3937 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3938 /** @todo AMD L2I performance counters. */
3939 *puValue = 0;
3940 return VINF_SUCCESS;
3941}
3942
3943
3944/** @callback_method_impl{FNCPUMWRMSR} */
3945static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam16hL2IPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3946{
3947 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3948 /** @todo AMD L2I performance counters. */
3949 return VINF_SUCCESS;
3950}
3951
3952
3953/** @callback_method_impl{FNCPUMRDMSR} */
3954static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hNorthbridgePerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3955{
3956 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3957 /** @todo AMD Northbridge performance counters. */
3958 *puValue = 0;
3959 return VINF_SUCCESS;
3960}
3961
3962
3963/** @callback_method_impl{FNCPUMWRMSR} */
3964static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hNorthbridgePerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3965{
3966 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3967 /** @todo AMD Northbridge performance counters. */
3968 return VINF_SUCCESS;
3969}
3970
3971
3972/** @callback_method_impl{FNCPUMRDMSR} */
3973static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hNorthbridgePerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3974{
3975 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3976 /** @todo AMD Northbridge performance counters. */
3977 *puValue = 0;
3978 return VINF_SUCCESS;
3979}
3980
3981
3982/** @callback_method_impl{FNCPUMWRMSR} */
3983static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hNorthbridgePerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3984{
3985 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
3986 /** @todo AMD Northbridge performance counters. */
3987 return VINF_SUCCESS;
3988}
3989
3990
3991/** @callback_method_impl{FNCPUMRDMSR} */
3992static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7MicrocodeCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3993{
3994 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
3995 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3996 * cpus. Need to be explored and verify K7 presence. */
3997 /** @todo Undocumented register only seen mentioned in fam15h erratum \#608. */
3998 *puValue = pRange->uValue;
3999 return VINF_SUCCESS;
4000}
4001
4002
4003/** @callback_method_impl{FNCPUMWRMSR} */
4004static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7MicrocodeCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4005{
4006 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4007 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4008 * cpus. Need to be explored and verify K7 presence. */
4009 /** @todo Undocumented register only seen mentioned in fam15h erratum \#608. */
4010 return VINF_SUCCESS;
4011}
4012
4013
4014/** @callback_method_impl{FNCPUMRDMSR} */
4015static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7ClusterIdMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4016{
4017 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4018 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4019 * cpus. Need to be explored and verify K7 presence. */
4020 /** @todo Undocumented register only seen mentioned in fam16h BKDG r3.00 when
4021 * describing EBL_CR_POWERON. */
4022 *puValue = pRange->uValue;
4023 return VINF_SUCCESS;
4024}
4025
4026
4027/** @callback_method_impl{FNCPUMWRMSR} */
4028static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7ClusterIdMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4029{
4030 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4031 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4032 * cpus. Need to be explored and verify K7 presence. */
4033 /** @todo Undocumented register only seen mentioned in fam16h BKDG r3.00 when
4034 * describing EBL_CR_POWERON. */
4035 return VINF_SUCCESS;
4036}
4037
4038
4039/** @callback_method_impl{FNCPUMRDMSR} */
4040static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlStd07hEbax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4041{
4042 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4043 bool fIgnored;
4044 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafEx(pVCpu->CTX_SUFF(pVM), 0x00000007, 0, &fIgnored);
4045 if (pLeaf)
4046 *puValue = RT_MAKE_U64(pLeaf->uEbx, pLeaf->uEax);
4047 else
4048 *puValue = 0;
4049 return VINF_SUCCESS;
4050}
4051
4052
4053/** @callback_method_impl{FNCPUMWRMSR} */
4054static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlStd07hEbax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4055{
4056 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4057 /** @todo Changing CPUID leaf 7/0. */
4058 return VINF_SUCCESS;
4059}
4060
4061
4062/** @callback_method_impl{FNCPUMRDMSR} */
4063static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlStd06hEcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4064{
4065 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4066 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000006);
4067 if (pLeaf)
4068 *puValue = pLeaf->uEcx;
4069 else
4070 *puValue = 0;
4071 return VINF_SUCCESS;
4072}
4073
4074
4075/** @callback_method_impl{FNCPUMWRMSR} */
4076static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlStd06hEcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4077{
4078 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4079 /** @todo Changing CPUID leaf 6. */
4080 return VINF_SUCCESS;
4081}
4082
4083
4084/** @callback_method_impl{FNCPUMRDMSR} */
4085static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlStd01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4086{
4087 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4088 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000001);
4089 if (pLeaf)
4090 *puValue = RT_MAKE_U64(pLeaf->uEdx, pLeaf->uEcx);
4091 else
4092 *puValue = 0;
4093 return VINF_SUCCESS;
4094}
4095
4096
4097/** @callback_method_impl{FNCPUMWRMSR} */
4098static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlStd01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4099{
4100 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4101 /** @todo Changing CPUID leaf 0x80000001. */
4102 return VINF_SUCCESS;
4103}
4104
4105
4106/** @callback_method_impl{FNCPUMRDMSR} */
4107static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8CpuIdCtlExt01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4108{
4109 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4110 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x80000001);
4111 if (pLeaf)
4112 *puValue = RT_MAKE_U64(pLeaf->uEdx, pLeaf->uEcx);
4113 else
4114 *puValue = 0;
4115 return VINF_SUCCESS;
4116}
4117
4118
4119/** @callback_method_impl{FNCPUMWRMSR} */
4120static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8CpuIdCtlExt01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4121{
4122 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4123 /** @todo Changing CPUID leaf 0x80000001. */
4124 return VINF_SUCCESS;
4125}
4126
4127
4128/** @callback_method_impl{FNCPUMRDMSR} */
4129static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK8PatchLevel(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4130{
4131 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4132 /** @todo Fake AMD microcode patching. */
4133 *puValue = pRange->uValue;
4134 return VINF_SUCCESS;
4135}
4136
4137
4138/** @callback_method_impl{FNCPUMWRMSR} */
4139static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK8PatchLoader(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4140{
4141 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4142 /** @todo Fake AMD microcode patching. */
4143 return VINF_SUCCESS;
4144}
4145
4146
4147/** @callback_method_impl{FNCPUMRDMSR} */
4148static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DebugStatusMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4149{
4150 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4151 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4152 * cpus. Need to be explored and verify K7 presence. */
4153 /** @todo undocumented */
4154 *puValue = 0;
4155 return VINF_SUCCESS;
4156}
4157
4158
4159/** @callback_method_impl{FNCPUMWRMSR} */
4160static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DebugStatusMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4161{
4162 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4163 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4164 * cpus. Need to be explored and verify K7 presence. */
4165 /** @todo undocumented */
4166 return VINF_SUCCESS;
4167}
4168
4169
4170/** @callback_method_impl{FNCPUMRDMSR} */
4171static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BHTraceBaseMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4172{
4173 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4174 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4175 * cpus. Need to be explored and verify K7 presence. */
4176 /** @todo undocumented */
4177 *puValue = 0;
4178 return VINF_SUCCESS;
4179}
4180
4181
4182/** @callback_method_impl{FNCPUMWRMSR} */
4183static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BHTraceBaseMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4184{
4185 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4186 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4187 * cpus. Need to be explored and verify K7 presence. */
4188 /** @todo undocumented */
4189 return VINF_SUCCESS;
4190}
4191
4192
4193/** @callback_method_impl{FNCPUMRDMSR} */
4194static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BHTracePtrMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4195{
4196 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4197 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4198 * cpus. Need to be explored and verify K7 presence. */
4199 /** @todo undocumented */
4200 *puValue = 0;
4201 return VINF_SUCCESS;
4202}
4203
4204
4205/** @callback_method_impl{FNCPUMWRMSR} */
4206static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BHTracePtrMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4207{
4208 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4209 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4210 * cpus. Need to be explored and verify K7 presence. */
4211 /** @todo undocumented */
4212 return VINF_SUCCESS;
4213}
4214
4215
4216/** @callback_method_impl{FNCPUMRDMSR} */
4217static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BHTraceLimitMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4218{
4219 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4220 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4221 * cpus. Need to be explored and verify K7 presence. */
4222 /** @todo undocumented */
4223 *puValue = 0;
4224 return VINF_SUCCESS;
4225}
4226
4227
4228/** @callback_method_impl{FNCPUMWRMSR} */
4229static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BHTraceLimitMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4230{
4231 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4232 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4233 * cpus. Need to be explored and verify K7 presence. */
4234 /** @todo undocumented */
4235 return VINF_SUCCESS;
4236}
4237
4238
4239/** @callback_method_impl{FNCPUMRDMSR} */
4240static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7HardwareDebugToolCfgMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4241{
4242 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4243 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4244 * cpus. Need to be explored and verify K7 presence. */
4245 /** @todo undocumented */
4246 *puValue = 0;
4247 return VINF_SUCCESS;
4248}
4249
4250
4251/** @callback_method_impl{FNCPUMWRMSR} */
4252static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7HardwareDebugToolCfgMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4253{
4254 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4255 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4256 * cpus. Need to be explored and verify K7 presence. */
4257 /** @todo undocumented */
4258 return VINF_SUCCESS;
4259}
4260
4261
4262/** @callback_method_impl{FNCPUMRDMSR} */
4263static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7FastFlushCountMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4264{
4265 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4266 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4267 * cpus. Need to be explored and verify K7 presence. */
4268 /** @todo undocumented */
4269 *puValue = 0;
4270 return VINF_SUCCESS;
4271}
4272
4273
4274/** @callback_method_impl{FNCPUMWRMSR} */
4275static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7FastFlushCountMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4276{
4277 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4278 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4279 * cpus. Need to be explored and verify K7 presence. */
4280 /** @todo undocumented */
4281 return VINF_SUCCESS;
4282}
4283
4284
4285/** @callback_method_impl{FNCPUMRDMSR} */
4286static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7NodeId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4287{
4288 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4289 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4290 * cpus. Need to be explored and verify K7 presence. */
4291 /** @todo AMD node ID and bios scratch. */
4292 *puValue = 0; /* nodeid = 0; nodes-per-cpu = 1 */
4293 return VINF_SUCCESS;
4294}
4295
4296
4297/** @callback_method_impl{FNCPUMWRMSR} */
4298static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7NodeId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4299{
4300 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4301 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4302 * cpus. Need to be explored and verify K7 presence. */
4303 /** @todo AMD node ID and bios scratch. */
4304 return VINF_SUCCESS;
4305}
4306
4307
4308/** @callback_method_impl{FNCPUMRDMSR} */
4309static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DrXAddrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4310{
4311 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4312 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4313 * cpus. Need to be explored and verify K7 presence. */
4314 /** @todo AMD DRx address masking (range breakpoints). */
4315 *puValue = 0;
4316 return VINF_SUCCESS;
4317}
4318
4319
4320/** @callback_method_impl{FNCPUMWRMSR} */
4321static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DrXAddrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4322{
4323 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4324 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4325 * cpus. Need to be explored and verify K7 presence. */
4326 /** @todo AMD DRx address masking (range breakpoints). */
4327 return VINF_SUCCESS;
4328}
4329
4330
4331/** @callback_method_impl{FNCPUMRDMSR} */
4332static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7Dr0DataMatchMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4333{
4334 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4335 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4336 * cpus. Need to be explored and verify K7 presence. */
4337 /** @todo AMD undocument debugging features. */
4338 *puValue = 0;
4339 return VINF_SUCCESS;
4340}
4341
4342
4343/** @callback_method_impl{FNCPUMWRMSR} */
4344static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7Dr0DataMatchMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4345{
4346 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4347 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4348 * cpus. Need to be explored and verify K7 presence. */
4349 /** @todo AMD undocument debugging features. */
4350 return VINF_SUCCESS;
4351}
4352
4353
4354/** @callback_method_impl{FNCPUMRDMSR} */
4355static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7Dr0DataMaskMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4356{
4357 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4358 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4359 * cpus. Need to be explored and verify K7 presence. */
4360 /** @todo AMD undocument debugging features. */
4361 *puValue = 0;
4362 return VINF_SUCCESS;
4363}
4364
4365
4366/** @callback_method_impl{FNCPUMWRMSR} */
4367static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7Dr0DataMaskMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4368{
4369 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4370 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4371 * cpus. Need to be explored and verify K7 presence. */
4372 /** @todo AMD undocument debugging features. */
4373 return VINF_SUCCESS;
4374}
4375
4376
4377/** @callback_method_impl{FNCPUMRDMSR} */
4378static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7LoadStoreCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4379{
4380 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4381 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4382 * cpus. Need to be explored and verify K7 presence. */
4383 /** @todo AMD load-store config. */
4384 *puValue = 0;
4385 return VINF_SUCCESS;
4386}
4387
4388
4389/** @callback_method_impl{FNCPUMWRMSR} */
4390static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7LoadStoreCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4391{
4392 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4393 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4394 * cpus. Need to be explored and verify K7 presence. */
4395 /** @todo AMD load-store config. */
4396 return VINF_SUCCESS;
4397}
4398
4399
4400/** @callback_method_impl{FNCPUMRDMSR} */
4401static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7InstrCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4402{
4403 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4404 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4405 * cpus. Need to be explored and verify K7 presence. */
4406 /** @todo AMD instruction cache config. */
4407 *puValue = 0;
4408 return VINF_SUCCESS;
4409}
4410
4411
4412/** @callback_method_impl{FNCPUMWRMSR} */
4413static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7InstrCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4414{
4415 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4416 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4417 * cpus. Need to be explored and verify K7 presence. */
4418 /** @todo AMD instruction cache config. */
4419 return VINF_SUCCESS;
4420}
4421
4422
4423/** @callback_method_impl{FNCPUMRDMSR} */
4424static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DataCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4425{
4426 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4427 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4428 * cpus. Need to be explored and verify K7 presence. */
4429 /** @todo AMD data cache config. */
4430 *puValue = 0;
4431 return VINF_SUCCESS;
4432}
4433
4434
4435/** @callback_method_impl{FNCPUMWRMSR} */
4436static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DataCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4437{
4438 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4439 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4440 * cpus. Need to be explored and verify K7 presence. */
4441 /** @todo AMD data cache config. */
4442 return VINF_SUCCESS;
4443}
4444
4445
4446/** @callback_method_impl{FNCPUMRDMSR} */
4447static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7BusUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4448{
4449 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4450 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4451 * cpus. Need to be explored and verify K7 presence. */
4452 /** @todo AMD bus unit config. */
4453 *puValue = 0;
4454 return VINF_SUCCESS;
4455}
4456
4457
4458/** @callback_method_impl{FNCPUMWRMSR} */
4459static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7BusUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4460{
4461 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4462 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4463 * cpus. Need to be explored and verify K7 presence. */
4464 /** @todo AMD bus unit config. */
4465 return VINF_SUCCESS;
4466}
4467
4468
4469/** @callback_method_impl{FNCPUMRDMSR} */
4470static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdK7DebugCtl2Maybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4471{
4472 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4473 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4474 * cpus. Need to be explored and verify K7 presence. */
4475 /** @todo Undocument AMD debug control register \#2. */
4476 *puValue = 0;
4477 return VINF_SUCCESS;
4478}
4479
4480
4481/** @callback_method_impl{FNCPUMWRMSR} */
4482static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdK7DebugCtl2Maybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4483{
4484 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4485 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4486 * cpus. Need to be explored and verify K7 presence. */
4487 /** @todo Undocument AMD debug control register \#2. */
4488 return VINF_SUCCESS;
4489}
4490
4491
4492/** @callback_method_impl{FNCPUMRDMSR} */
4493static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hFpuCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4494{
4495 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4496 /** @todo AMD FPU config. */
4497 *puValue = 0;
4498 return VINF_SUCCESS;
4499}
4500
4501
4502/** @callback_method_impl{FNCPUMWRMSR} */
4503static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hFpuCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4504{
4505 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4506 /** @todo AMD FPU config. */
4507 return VINF_SUCCESS;
4508}
4509
4510
4511/** @callback_method_impl{FNCPUMRDMSR} */
4512static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hDecoderCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4513{
4514 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4515 /** @todo AMD decoder config. */
4516 *puValue = 0;
4517 return VINF_SUCCESS;
4518}
4519
4520
4521/** @callback_method_impl{FNCPUMWRMSR} */
4522static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hDecoderCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4523{
4524 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4525 /** @todo AMD decoder config. */
4526 return VINF_SUCCESS;
4527}
4528
4529
4530/** @callback_method_impl{FNCPUMRDMSR} */
4531static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hBusUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4532{
4533 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4534 /* Note! 10h and 16h */
4535 /** @todo AMD bus unit config. */
4536 *puValue = 0;
4537 return VINF_SUCCESS;
4538}
4539
4540
4541/** @callback_method_impl{FNCPUMWRMSR} */
4542static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hBusUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4543{
4544 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4545 /* Note! 10h and 16h */
4546 /** @todo AMD bus unit config. */
4547 return VINF_SUCCESS;
4548}
4549
4550
4551/** @callback_method_impl{FNCPUMRDMSR} */
4552static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hCombUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4553{
4554 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4555 /** @todo AMD unit config. */
4556 *puValue = 0;
4557 return VINF_SUCCESS;
4558}
4559
4560
4561/** @callback_method_impl{FNCPUMWRMSR} */
4562static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hCombUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4563{
4564 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4565 /** @todo AMD unit config. */
4566 return VINF_SUCCESS;
4567}
4568
4569
4570/** @callback_method_impl{FNCPUMRDMSR} */
4571static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hCombUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4572{
4573 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4574 /** @todo AMD unit config 2. */
4575 *puValue = 0;
4576 return VINF_SUCCESS;
4577}
4578
4579
4580/** @callback_method_impl{FNCPUMWRMSR} */
4581static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hCombUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4582{
4583 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4584 /** @todo AMD unit config 2. */
4585 return VINF_SUCCESS;
4586}
4587
4588
4589/** @callback_method_impl{FNCPUMRDMSR} */
4590static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hCombUnitCfg3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4591{
4592 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4593 /** @todo AMD combined unit config 3. */
4594 *puValue = 0;
4595 return VINF_SUCCESS;
4596}
4597
4598
4599/** @callback_method_impl{FNCPUMWRMSR} */
4600static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hCombUnitCfg3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4601{
4602 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4603 /** @todo AMD combined unit config 3. */
4604 return VINF_SUCCESS;
4605}
4606
4607
4608/** @callback_method_impl{FNCPUMRDMSR} */
4609static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hExecUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4610{
4611 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4612 /** @todo AMD execution unit config. */
4613 *puValue = 0;
4614 return VINF_SUCCESS;
4615}
4616
4617
4618/** @callback_method_impl{FNCPUMWRMSR} */
4619static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hExecUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4620{
4621 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4622 /** @todo AMD execution unit config. */
4623 return VINF_SUCCESS;
4624}
4625
4626
4627/** @callback_method_impl{FNCPUMRDMSR} */
4628static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam15hLoadStoreCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4629{
4630 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4631 /** @todo AMD load-store config 2. */
4632 *puValue = 0;
4633 return VINF_SUCCESS;
4634}
4635
4636
4637/** @callback_method_impl{FNCPUMWRMSR} */
4638static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam15hLoadStoreCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4639{
4640 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4641 /** @todo AMD load-store config 2. */
4642 return VINF_SUCCESS;
4643}
4644
4645
4646/** @callback_method_impl{FNCPUMRDMSR} */
4647static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsFetchCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4648{
4649 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4650 /** @todo AMD IBS. */
4651 *puValue = 0;
4652 return VINF_SUCCESS;
4653}
4654
4655
4656/** @callback_method_impl{FNCPUMWRMSR} */
4657static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsFetchCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4658{
4659 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4660 /** @todo AMD IBS. */
4661 return VINF_SUCCESS;
4662}
4663
4664
4665/** @callback_method_impl{FNCPUMRDMSR} */
4666static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsFetchLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4667{
4668 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4669 /** @todo AMD IBS. */
4670 *puValue = 0;
4671 return VINF_SUCCESS;
4672}
4673
4674
4675/** @callback_method_impl{FNCPUMWRMSR} */
4676static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsFetchLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4677{
4678 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4679 /** @todo AMD IBS. */
4680 return VINF_SUCCESS;
4681}
4682
4683
4684/** @callback_method_impl{FNCPUMRDMSR} */
4685static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsFetchPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4686{
4687 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4688 /** @todo AMD IBS. */
4689 *puValue = 0;
4690 return VINF_SUCCESS;
4691}
4692
4693
4694/** @callback_method_impl{FNCPUMWRMSR} */
4695static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsFetchPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4696{
4697 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4698 /** @todo AMD IBS. */
4699 return VINF_SUCCESS;
4700}
4701
4702
4703/** @callback_method_impl{FNCPUMRDMSR} */
4704static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpExecCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4705{
4706 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4707 /** @todo AMD IBS. */
4708 *puValue = 0;
4709 return VINF_SUCCESS;
4710}
4711
4712
4713/** @callback_method_impl{FNCPUMWRMSR} */
4714static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpExecCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4715{
4716 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4717 /** @todo AMD IBS. */
4718 return VINF_SUCCESS;
4719}
4720
4721
4722/** @callback_method_impl{FNCPUMRDMSR} */
4723static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpRip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4724{
4725 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4726 /** @todo AMD IBS. */
4727 *puValue = 0;
4728 return VINF_SUCCESS;
4729}
4730
4731
4732/** @callback_method_impl{FNCPUMWRMSR} */
4733static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpRip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4734{
4735 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4736 /** @todo AMD IBS. */
4737 if (!X86_IS_CANONICAL(uValue))
4738 {
4739 Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
4740 return VERR_CPUM_RAISE_GP_0;
4741 }
4742 return VINF_SUCCESS;
4743}
4744
4745
4746/** @callback_method_impl{FNCPUMRDMSR} */
4747static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpData(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4748{
4749 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4750 /** @todo AMD IBS. */
4751 *puValue = 0;
4752 return VINF_SUCCESS;
4753}
4754
4755
4756/** @callback_method_impl{FNCPUMWRMSR} */
4757static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpData(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4758{
4759 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4760 /** @todo AMD IBS. */
4761 return VINF_SUCCESS;
4762}
4763
4764
4765/** @callback_method_impl{FNCPUMRDMSR} */
4766static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpData2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4767{
4768 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4769 /** @todo AMD IBS. */
4770 *puValue = 0;
4771 return VINF_SUCCESS;
4772}
4773
4774
4775/** @callback_method_impl{FNCPUMWRMSR} */
4776static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpData2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4777{
4778 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4779 /** @todo AMD IBS. */
4780 return VINF_SUCCESS;
4781}
4782
4783
4784/** @callback_method_impl{FNCPUMRDMSR} */
4785static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsOpData3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4786{
4787 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4788 /** @todo AMD IBS. */
4789 *puValue = 0;
4790 return VINF_SUCCESS;
4791}
4792
4793
4794/** @callback_method_impl{FNCPUMWRMSR} */
4795static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsOpData3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4796{
4797 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4798 /** @todo AMD IBS. */
4799 return VINF_SUCCESS;
4800}
4801
4802
4803/** @callback_method_impl{FNCPUMRDMSR} */
4804static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsDcLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4805{
4806 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4807 /** @todo AMD IBS. */
4808 *puValue = 0;
4809 return VINF_SUCCESS;
4810}
4811
4812
4813/** @callback_method_impl{FNCPUMWRMSR} */
4814static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsDcLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4815{
4816 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4817 /** @todo AMD IBS. */
4818 if (!X86_IS_CANONICAL(uValue))
4819 {
4820 Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
4821 return VERR_CPUM_RAISE_GP_0;
4822 }
4823 return VINF_SUCCESS;
4824}
4825
4826
4827/** @callback_method_impl{FNCPUMRDMSR} */
4828static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsDcPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4829{
4830 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4831 /** @todo AMD IBS. */
4832 *puValue = 0;
4833 return VINF_SUCCESS;
4834}
4835
4836
4837/** @callback_method_impl{FNCPUMWRMSR} */
4838static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsDcPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4839{
4840 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4841 /** @todo AMD IBS. */
4842 return VINF_SUCCESS;
4843}
4844
4845
4846/** @callback_method_impl{FNCPUMRDMSR} */
4847static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam10hIbsCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4848{
4849 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4850 /** @todo AMD IBS. */
4851 *puValue = 0;
4852 return VINF_SUCCESS;
4853}
4854
4855
4856/** @callback_method_impl{FNCPUMWRMSR} */
4857static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam10hIbsCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4858{
4859 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4860 /** @todo AMD IBS. */
4861 return VINF_SUCCESS;
4862}
4863
4864
4865/** @callback_method_impl{FNCPUMRDMSR} */
4866static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_AmdFam14hIbsBrTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4867{
4868 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
4869 /** @todo AMD IBS. */
4870 *puValue = 0;
4871 return VINF_SUCCESS;
4872}
4873
4874
4875/** @callback_method_impl{FNCPUMWRMSR} */
4876static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_AmdFam14hIbsBrTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4877{
4878 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
4879 /** @todo AMD IBS. */
4880 if (!X86_IS_CANONICAL(uValue))
4881 {
4882 Log(("CPUM: wrmsr %s(%#x), %#llx -> #GP - not canonical\n", pRange->szName, idMsr, uValue));
4883 return VERR_CPUM_RAISE_GP_0;
4884 }
4885 return VINF_SUCCESS;
4886}
4887
4888
4889
4890/*
4891 * GIM MSRs.
4892 * GIM MSRs.
4893 * GIM MSRs.
4894 */
4895
4896
4897/** @callback_method_impl{FNCPUMRDMSR} */
4898static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Gim(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4899{
4900#ifdef VBOX_WITH_NESTED_HWVIRT
4901 /* Raise #GP(0) like a physical CPU would since the nested-hypervisor hasn't intercept these MSRs. */
4902 PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
4903 if (CPUMIsGuestInNestedHwVirtMode(pCtx))
4904 return VERR_CPUM_RAISE_GP_0;
4905#endif
4906 return GIMReadMsr(pVCpu, idMsr, pRange, puValue);
4907}
4908
4909
4910/** @callback_method_impl{FNCPUMWRMSR} */
4911static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_Gim(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4912{
4913#ifdef VBOX_WITH_NESTED_HWVIRT
4914 /* Raise #GP(0) like a physical CPU would since the nested-hypervisor hasn't intercept these MSRs. */
4915 PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
4916 if (CPUMIsGuestInNestedHwVirtMode(pCtx))
4917 return VERR_CPUM_RAISE_GP_0;
4918#endif
4919 return GIMWriteMsr(pVCpu, idMsr, pRange, uValue, uRawValue);
4920}
4921
4922
4923/**
4924 * MSR read function table.
4925 */
4926static const PFNCPUMRDMSR g_aCpumRdMsrFns[kCpumMsrRdFn_End] =
4927{
4928 NULL, /* Invalid */
4929 cpumMsrRd_FixedValue,
4930 NULL, /* Alias */
4931 cpumMsrRd_WriteOnly,
4932 cpumMsrRd_Ia32P5McAddr,
4933 cpumMsrRd_Ia32P5McType,
4934 cpumMsrRd_Ia32TimestampCounter,
4935 cpumMsrRd_Ia32PlatformId,
4936 cpumMsrRd_Ia32ApicBase,
4937 cpumMsrRd_Ia32FeatureControl,
4938 cpumMsrRd_Ia32BiosSignId,
4939 cpumMsrRd_Ia32SmmMonitorCtl,
4940 cpumMsrRd_Ia32PmcN,
4941 cpumMsrRd_Ia32MonitorFilterLineSize,
4942 cpumMsrRd_Ia32MPerf,
4943 cpumMsrRd_Ia32APerf,
4944 cpumMsrRd_Ia32MtrrCap,
4945 cpumMsrRd_Ia32MtrrPhysBaseN,
4946 cpumMsrRd_Ia32MtrrPhysMaskN,
4947 cpumMsrRd_Ia32MtrrFixed,
4948 cpumMsrRd_Ia32MtrrDefType,
4949 cpumMsrRd_Ia32Pat,
4950 cpumMsrRd_Ia32SysEnterCs,
4951 cpumMsrRd_Ia32SysEnterEsp,
4952 cpumMsrRd_Ia32SysEnterEip,
4953 cpumMsrRd_Ia32McgCap,
4954 cpumMsrRd_Ia32McgStatus,
4955 cpumMsrRd_Ia32McgCtl,
4956 cpumMsrRd_Ia32DebugCtl,
4957 cpumMsrRd_Ia32SmrrPhysBase,
4958 cpumMsrRd_Ia32SmrrPhysMask,
4959 cpumMsrRd_Ia32PlatformDcaCap,
4960 cpumMsrRd_Ia32CpuDcaCap,
4961 cpumMsrRd_Ia32Dca0Cap,
4962 cpumMsrRd_Ia32PerfEvtSelN,
4963 cpumMsrRd_Ia32PerfStatus,
4964 cpumMsrRd_Ia32PerfCtl,
4965 cpumMsrRd_Ia32FixedCtrN,
4966 cpumMsrRd_Ia32PerfCapabilities,
4967 cpumMsrRd_Ia32FixedCtrCtrl,
4968 cpumMsrRd_Ia32PerfGlobalStatus,
4969 cpumMsrRd_Ia32PerfGlobalCtrl,
4970 cpumMsrRd_Ia32PerfGlobalOvfCtrl,
4971 cpumMsrRd_Ia32PebsEnable,
4972 cpumMsrRd_Ia32ClockModulation,
4973 cpumMsrRd_Ia32ThermInterrupt,
4974 cpumMsrRd_Ia32ThermStatus,
4975 cpumMsrRd_Ia32Therm2Ctl,
4976 cpumMsrRd_Ia32MiscEnable,
4977 cpumMsrRd_Ia32McCtlStatusAddrMiscN,
4978 cpumMsrRd_Ia32McNCtl2,
4979 cpumMsrRd_Ia32DsArea,
4980 cpumMsrRd_Ia32TscDeadline,
4981 cpumMsrRd_Ia32X2ApicN,
4982 cpumMsrRd_Ia32DebugInterface,
4983 cpumMsrRd_Ia32VmxBase,
4984 cpumMsrRd_Ia32VmxPinbasedCtls,
4985 cpumMsrRd_Ia32VmxProcbasedCtls,
4986 cpumMsrRd_Ia32VmxExitCtls,
4987 cpumMsrRd_Ia32VmxEntryCtls,
4988 cpumMsrRd_Ia32VmxMisc,
4989 cpumMsrRd_Ia32VmxCr0Fixed0,
4990 cpumMsrRd_Ia32VmxCr0Fixed1,
4991 cpumMsrRd_Ia32VmxCr4Fixed0,
4992 cpumMsrRd_Ia32VmxCr4Fixed1,
4993 cpumMsrRd_Ia32VmxVmcsEnum,
4994 cpumMsrRd_Ia32VmxProcBasedCtls2,
4995 cpumMsrRd_Ia32VmxEptVpidCap,
4996 cpumMsrRd_Ia32VmxTruePinbasedCtls,
4997 cpumMsrRd_Ia32VmxTrueProcbasedCtls,
4998 cpumMsrRd_Ia32VmxTrueExitCtls,
4999 cpumMsrRd_Ia32VmxTrueEntryCtls,
5000 cpumMsrRd_Ia32VmxVmFunc,
5001
5002 cpumMsrRd_Amd64Efer,
5003 cpumMsrRd_Amd64SyscallTarget,
5004 cpumMsrRd_Amd64LongSyscallTarget,
5005 cpumMsrRd_Amd64CompSyscallTarget,
5006 cpumMsrRd_Amd64SyscallFlagMask,
5007 cpumMsrRd_Amd64FsBase,
5008 cpumMsrRd_Amd64GsBase,
5009 cpumMsrRd_Amd64KernelGsBase,
5010 cpumMsrRd_Amd64TscAux,
5011
5012 cpumMsrRd_IntelEblCrPowerOn,
5013 cpumMsrRd_IntelI7CoreThreadCount,
5014 cpumMsrRd_IntelP4EbcHardPowerOn,
5015 cpumMsrRd_IntelP4EbcSoftPowerOn,
5016 cpumMsrRd_IntelP4EbcFrequencyId,
5017 cpumMsrRd_IntelP6FsbFrequency,
5018 cpumMsrRd_IntelPlatformInfo,
5019 cpumMsrRd_IntelFlexRatio,
5020 cpumMsrRd_IntelPkgCStConfigControl,
5021 cpumMsrRd_IntelPmgIoCaptureBase,
5022 cpumMsrRd_IntelLastBranchFromToN,
5023 cpumMsrRd_IntelLastBranchFromN,
5024 cpumMsrRd_IntelLastBranchToN,
5025 cpumMsrRd_IntelLastBranchTos,
5026 cpumMsrRd_IntelBblCrCtl,
5027 cpumMsrRd_IntelBblCrCtl3,
5028 cpumMsrRd_IntelI7TemperatureTarget,
5029 cpumMsrRd_IntelI7MsrOffCoreResponseN,
5030 cpumMsrRd_IntelI7MiscPwrMgmt,
5031 cpumMsrRd_IntelP6CrN,
5032 cpumMsrRd_IntelCpuId1FeatureMaskEcdx,
5033 cpumMsrRd_IntelCpuId1FeatureMaskEax,
5034 cpumMsrRd_IntelCpuId80000001FeatureMaskEcdx,
5035 cpumMsrRd_IntelI7SandyAesNiCtl,
5036 cpumMsrRd_IntelI7TurboRatioLimit,
5037 cpumMsrRd_IntelI7LbrSelect,
5038 cpumMsrRd_IntelI7SandyErrorControl,
5039 cpumMsrRd_IntelI7VirtualLegacyWireCap,
5040 cpumMsrRd_IntelI7PowerCtl,
5041 cpumMsrRd_IntelI7SandyPebsNumAlt,
5042 cpumMsrRd_IntelI7PebsLdLat,
5043 cpumMsrRd_IntelI7PkgCnResidencyN,
5044 cpumMsrRd_IntelI7CoreCnResidencyN,
5045 cpumMsrRd_IntelI7SandyVrCurrentConfig,
5046 cpumMsrRd_IntelI7SandyVrMiscConfig,
5047 cpumMsrRd_IntelI7SandyRaplPowerUnit,
5048 cpumMsrRd_IntelI7SandyPkgCnIrtlN,
5049 cpumMsrRd_IntelI7SandyPkgC2Residency,
5050 cpumMsrRd_IntelI7RaplPkgPowerLimit,
5051 cpumMsrRd_IntelI7RaplPkgEnergyStatus,
5052 cpumMsrRd_IntelI7RaplPkgPerfStatus,
5053 cpumMsrRd_IntelI7RaplPkgPowerInfo,
5054 cpumMsrRd_IntelI7RaplDramPowerLimit,
5055 cpumMsrRd_IntelI7RaplDramEnergyStatus,
5056 cpumMsrRd_IntelI7RaplDramPerfStatus,
5057 cpumMsrRd_IntelI7RaplDramPowerInfo,
5058 cpumMsrRd_IntelI7RaplPp0PowerLimit,
5059 cpumMsrRd_IntelI7RaplPp0EnergyStatus,
5060 cpumMsrRd_IntelI7RaplPp0Policy,
5061 cpumMsrRd_IntelI7RaplPp0PerfStatus,
5062 cpumMsrRd_IntelI7RaplPp1PowerLimit,
5063 cpumMsrRd_IntelI7RaplPp1EnergyStatus,
5064 cpumMsrRd_IntelI7RaplPp1Policy,
5065 cpumMsrRd_IntelI7IvyConfigTdpNominal,
5066 cpumMsrRd_IntelI7IvyConfigTdpLevel1,
5067 cpumMsrRd_IntelI7IvyConfigTdpLevel2,
5068 cpumMsrRd_IntelI7IvyConfigTdpControl,
5069 cpumMsrRd_IntelI7IvyTurboActivationRatio,
5070 cpumMsrRd_IntelI7UncPerfGlobalCtrl,
5071 cpumMsrRd_IntelI7UncPerfGlobalStatus,
5072 cpumMsrRd_IntelI7UncPerfGlobalOvfCtrl,
5073 cpumMsrRd_IntelI7UncPerfFixedCtrCtrl,
5074 cpumMsrRd_IntelI7UncPerfFixedCtr,
5075 cpumMsrRd_IntelI7UncCBoxConfig,
5076 cpumMsrRd_IntelI7UncArbPerfCtrN,
5077 cpumMsrRd_IntelI7UncArbPerfEvtSelN,
5078 cpumMsrRd_IntelI7SmiCount,
5079 cpumMsrRd_IntelCore2EmttmCrTablesN,
5080 cpumMsrRd_IntelCore2SmmCStMiscInfo,
5081 cpumMsrRd_IntelCore1ExtConfig,
5082 cpumMsrRd_IntelCore1DtsCalControl,
5083 cpumMsrRd_IntelCore2PeciControl,
5084 cpumMsrRd_IntelAtSilvCoreC1Recidency,
5085
5086 cpumMsrRd_P6LastBranchFromIp,
5087 cpumMsrRd_P6LastBranchToIp,
5088 cpumMsrRd_P6LastIntFromIp,
5089 cpumMsrRd_P6LastIntToIp,
5090
5091 cpumMsrRd_AmdFam15hTscRate,
5092 cpumMsrRd_AmdFam15hLwpCfg,
5093 cpumMsrRd_AmdFam15hLwpCbAddr,
5094 cpumMsrRd_AmdFam10hMc4MiscN,
5095 cpumMsrRd_AmdK8PerfCtlN,
5096 cpumMsrRd_AmdK8PerfCtrN,
5097 cpumMsrRd_AmdK8SysCfg,
5098 cpumMsrRd_AmdK8HwCr,
5099 cpumMsrRd_AmdK8IorrBaseN,
5100 cpumMsrRd_AmdK8IorrMaskN,
5101 cpumMsrRd_AmdK8TopOfMemN,
5102 cpumMsrRd_AmdK8NbCfg1,
5103 cpumMsrRd_AmdK8McXcptRedir,
5104 cpumMsrRd_AmdK8CpuNameN,
5105 cpumMsrRd_AmdK8HwThermalCtrl,
5106 cpumMsrRd_AmdK8SwThermalCtrl,
5107 cpumMsrRd_AmdK8FidVidControl,
5108 cpumMsrRd_AmdK8FidVidStatus,
5109 cpumMsrRd_AmdK8McCtlMaskN,
5110 cpumMsrRd_AmdK8SmiOnIoTrapN,
5111 cpumMsrRd_AmdK8SmiOnIoTrapCtlSts,
5112 cpumMsrRd_AmdK8IntPendingMessage,
5113 cpumMsrRd_AmdK8SmiTriggerIoCycle,
5114 cpumMsrRd_AmdFam10hMmioCfgBaseAddr,
5115 cpumMsrRd_AmdFam10hTrapCtlMaybe,
5116 cpumMsrRd_AmdFam10hPStateCurLimit,
5117 cpumMsrRd_AmdFam10hPStateControl,
5118 cpumMsrRd_AmdFam10hPStateStatus,
5119 cpumMsrRd_AmdFam10hPStateN,
5120 cpumMsrRd_AmdFam10hCofVidControl,
5121 cpumMsrRd_AmdFam10hCofVidStatus,
5122 cpumMsrRd_AmdFam10hCStateIoBaseAddr,
5123 cpumMsrRd_AmdFam10hCpuWatchdogTimer,
5124 cpumMsrRd_AmdK8SmmBase,
5125 cpumMsrRd_AmdK8SmmAddr,
5126 cpumMsrRd_AmdK8SmmMask,
5127 cpumMsrRd_AmdK8VmCr,
5128 cpumMsrRd_AmdK8IgnNe,
5129 cpumMsrRd_AmdK8SmmCtl,
5130 cpumMsrRd_AmdK8VmHSavePa,
5131 cpumMsrRd_AmdFam10hVmLockKey,
5132 cpumMsrRd_AmdFam10hSmmLockKey,
5133 cpumMsrRd_AmdFam10hLocalSmiStatus,
5134 cpumMsrRd_AmdFam10hOsVisWrkIdLength,
5135 cpumMsrRd_AmdFam10hOsVisWrkStatus,
5136 cpumMsrRd_AmdFam16hL2IPerfCtlN,
5137 cpumMsrRd_AmdFam16hL2IPerfCtrN,
5138 cpumMsrRd_AmdFam15hNorthbridgePerfCtlN,
5139 cpumMsrRd_AmdFam15hNorthbridgePerfCtrN,
5140 cpumMsrRd_AmdK7MicrocodeCtl,
5141 cpumMsrRd_AmdK7ClusterIdMaybe,
5142 cpumMsrRd_AmdK8CpuIdCtlStd07hEbax,
5143 cpumMsrRd_AmdK8CpuIdCtlStd06hEcx,
5144 cpumMsrRd_AmdK8CpuIdCtlStd01hEdcx,
5145 cpumMsrRd_AmdK8CpuIdCtlExt01hEdcx,
5146 cpumMsrRd_AmdK8PatchLevel,
5147 cpumMsrRd_AmdK7DebugStatusMaybe,
5148 cpumMsrRd_AmdK7BHTraceBaseMaybe,
5149 cpumMsrRd_AmdK7BHTracePtrMaybe,
5150 cpumMsrRd_AmdK7BHTraceLimitMaybe,
5151 cpumMsrRd_AmdK7HardwareDebugToolCfgMaybe,
5152 cpumMsrRd_AmdK7FastFlushCountMaybe,
5153 cpumMsrRd_AmdK7NodeId,
5154 cpumMsrRd_AmdK7DrXAddrMaskN,
5155 cpumMsrRd_AmdK7Dr0DataMatchMaybe,
5156 cpumMsrRd_AmdK7Dr0DataMaskMaybe,
5157 cpumMsrRd_AmdK7LoadStoreCfg,
5158 cpumMsrRd_AmdK7InstrCacheCfg,
5159 cpumMsrRd_AmdK7DataCacheCfg,
5160 cpumMsrRd_AmdK7BusUnitCfg,
5161 cpumMsrRd_AmdK7DebugCtl2Maybe,
5162 cpumMsrRd_AmdFam15hFpuCfg,
5163 cpumMsrRd_AmdFam15hDecoderCfg,
5164 cpumMsrRd_AmdFam10hBusUnitCfg2,
5165 cpumMsrRd_AmdFam15hCombUnitCfg,
5166 cpumMsrRd_AmdFam15hCombUnitCfg2,
5167 cpumMsrRd_AmdFam15hCombUnitCfg3,
5168 cpumMsrRd_AmdFam15hExecUnitCfg,
5169 cpumMsrRd_AmdFam15hLoadStoreCfg2,
5170 cpumMsrRd_AmdFam10hIbsFetchCtl,
5171 cpumMsrRd_AmdFam10hIbsFetchLinAddr,
5172 cpumMsrRd_AmdFam10hIbsFetchPhysAddr,
5173 cpumMsrRd_AmdFam10hIbsOpExecCtl,
5174 cpumMsrRd_AmdFam10hIbsOpRip,
5175 cpumMsrRd_AmdFam10hIbsOpData,
5176 cpumMsrRd_AmdFam10hIbsOpData2,
5177 cpumMsrRd_AmdFam10hIbsOpData3,
5178 cpumMsrRd_AmdFam10hIbsDcLinAddr,
5179 cpumMsrRd_AmdFam10hIbsDcPhysAddr,
5180 cpumMsrRd_AmdFam10hIbsCtl,
5181 cpumMsrRd_AmdFam14hIbsBrTarget,
5182
5183 cpumMsrRd_Gim
5184};
5185
5186
5187/**
5188 * MSR write function table.
5189 */
5190static const PFNCPUMWRMSR g_aCpumWrMsrFns[kCpumMsrWrFn_End] =
5191{
5192 NULL, /* Invalid */
5193 cpumMsrWr_IgnoreWrite,
5194 cpumMsrWr_ReadOnly,
5195 NULL, /* Alias */
5196 cpumMsrWr_Ia32P5McAddr,
5197 cpumMsrWr_Ia32P5McType,
5198 cpumMsrWr_Ia32TimestampCounter,
5199 cpumMsrWr_Ia32ApicBase,
5200 cpumMsrWr_Ia32FeatureControl,
5201 cpumMsrWr_Ia32BiosSignId,
5202 cpumMsrWr_Ia32BiosUpdateTrigger,
5203 cpumMsrWr_Ia32SmmMonitorCtl,
5204 cpumMsrWr_Ia32PmcN,
5205 cpumMsrWr_Ia32MonitorFilterLineSize,
5206 cpumMsrWr_Ia32MPerf,
5207 cpumMsrWr_Ia32APerf,
5208 cpumMsrWr_Ia32MtrrPhysBaseN,
5209 cpumMsrWr_Ia32MtrrPhysMaskN,
5210 cpumMsrWr_Ia32MtrrFixed,
5211 cpumMsrWr_Ia32MtrrDefType,
5212 cpumMsrWr_Ia32Pat,
5213 cpumMsrWr_Ia32SysEnterCs,
5214 cpumMsrWr_Ia32SysEnterEsp,
5215 cpumMsrWr_Ia32SysEnterEip,
5216 cpumMsrWr_Ia32McgStatus,
5217 cpumMsrWr_Ia32McgCtl,
5218 cpumMsrWr_Ia32DebugCtl,
5219 cpumMsrWr_Ia32SmrrPhysBase,
5220 cpumMsrWr_Ia32SmrrPhysMask,
5221 cpumMsrWr_Ia32PlatformDcaCap,
5222 cpumMsrWr_Ia32Dca0Cap,
5223 cpumMsrWr_Ia32PerfEvtSelN,
5224 cpumMsrWr_Ia32PerfStatus,
5225 cpumMsrWr_Ia32PerfCtl,
5226 cpumMsrWr_Ia32FixedCtrN,
5227 cpumMsrWr_Ia32PerfCapabilities,
5228 cpumMsrWr_Ia32FixedCtrCtrl,
5229 cpumMsrWr_Ia32PerfGlobalStatus,
5230 cpumMsrWr_Ia32PerfGlobalCtrl,
5231 cpumMsrWr_Ia32PerfGlobalOvfCtrl,
5232 cpumMsrWr_Ia32PebsEnable,
5233 cpumMsrWr_Ia32ClockModulation,
5234 cpumMsrWr_Ia32ThermInterrupt,
5235 cpumMsrWr_Ia32ThermStatus,
5236 cpumMsrWr_Ia32Therm2Ctl,
5237 cpumMsrWr_Ia32MiscEnable,
5238 cpumMsrWr_Ia32McCtlStatusAddrMiscN,
5239 cpumMsrWr_Ia32McNCtl2,
5240 cpumMsrWr_Ia32DsArea,
5241 cpumMsrWr_Ia32TscDeadline,
5242 cpumMsrWr_Ia32X2ApicN,
5243 cpumMsrWr_Ia32DebugInterface,
5244
5245 cpumMsrWr_Amd64Efer,
5246 cpumMsrWr_Amd64SyscallTarget,
5247 cpumMsrWr_Amd64LongSyscallTarget,
5248 cpumMsrWr_Amd64CompSyscallTarget,
5249 cpumMsrWr_Amd64SyscallFlagMask,
5250 cpumMsrWr_Amd64FsBase,
5251 cpumMsrWr_Amd64GsBase,
5252 cpumMsrWr_Amd64KernelGsBase,
5253 cpumMsrWr_Amd64TscAux,
5254
5255 cpumMsrWr_IntelEblCrPowerOn,
5256 cpumMsrWr_IntelP4EbcHardPowerOn,
5257 cpumMsrWr_IntelP4EbcSoftPowerOn,
5258 cpumMsrWr_IntelP4EbcFrequencyId,
5259 cpumMsrWr_IntelFlexRatio,
5260 cpumMsrWr_IntelPkgCStConfigControl,
5261 cpumMsrWr_IntelPmgIoCaptureBase,
5262 cpumMsrWr_IntelLastBranchFromToN,
5263 cpumMsrWr_IntelLastBranchFromN,
5264 cpumMsrWr_IntelLastBranchToN,
5265 cpumMsrWr_IntelLastBranchTos,
5266 cpumMsrWr_IntelBblCrCtl,
5267 cpumMsrWr_IntelBblCrCtl3,
5268 cpumMsrWr_IntelI7TemperatureTarget,
5269 cpumMsrWr_IntelI7MsrOffCoreResponseN,
5270 cpumMsrWr_IntelI7MiscPwrMgmt,
5271 cpumMsrWr_IntelP6CrN,
5272 cpumMsrWr_IntelCpuId1FeatureMaskEcdx,
5273 cpumMsrWr_IntelCpuId1FeatureMaskEax,
5274 cpumMsrWr_IntelCpuId80000001FeatureMaskEcdx,
5275 cpumMsrWr_IntelI7SandyAesNiCtl,
5276 cpumMsrWr_IntelI7TurboRatioLimit,
5277 cpumMsrWr_IntelI7LbrSelect,
5278 cpumMsrWr_IntelI7SandyErrorControl,
5279 cpumMsrWr_IntelI7PowerCtl,
5280 cpumMsrWr_IntelI7SandyPebsNumAlt,
5281 cpumMsrWr_IntelI7PebsLdLat,
5282 cpumMsrWr_IntelI7SandyVrCurrentConfig,
5283 cpumMsrWr_IntelI7SandyVrMiscConfig,
5284 cpumMsrWr_IntelI7SandyRaplPowerUnit,
5285 cpumMsrWr_IntelI7SandyPkgCnIrtlN,
5286 cpumMsrWr_IntelI7SandyPkgC2Residency,
5287 cpumMsrWr_IntelI7RaplPkgPowerLimit,
5288 cpumMsrWr_IntelI7RaplDramPowerLimit,
5289 cpumMsrWr_IntelI7RaplPp0PowerLimit,
5290 cpumMsrWr_IntelI7RaplPp0Policy,
5291 cpumMsrWr_IntelI7RaplPp1PowerLimit,
5292 cpumMsrWr_IntelI7RaplPp1Policy,
5293 cpumMsrWr_IntelI7IvyConfigTdpControl,
5294 cpumMsrWr_IntelI7IvyTurboActivationRatio,
5295 cpumMsrWr_IntelI7UncPerfGlobalCtrl,
5296 cpumMsrWr_IntelI7UncPerfGlobalStatus,
5297 cpumMsrWr_IntelI7UncPerfGlobalOvfCtrl,
5298 cpumMsrWr_IntelI7UncPerfFixedCtrCtrl,
5299 cpumMsrWr_IntelI7UncPerfFixedCtr,
5300 cpumMsrWr_IntelI7UncArbPerfCtrN,
5301 cpumMsrWr_IntelI7UncArbPerfEvtSelN,
5302 cpumMsrWr_IntelCore2EmttmCrTablesN,
5303 cpumMsrWr_IntelCore2SmmCStMiscInfo,
5304 cpumMsrWr_IntelCore1ExtConfig,
5305 cpumMsrWr_IntelCore1DtsCalControl,
5306 cpumMsrWr_IntelCore2PeciControl,
5307
5308 cpumMsrWr_P6LastIntFromIp,
5309 cpumMsrWr_P6LastIntToIp,
5310
5311 cpumMsrWr_AmdFam15hTscRate,
5312 cpumMsrWr_AmdFam15hLwpCfg,
5313 cpumMsrWr_AmdFam15hLwpCbAddr,
5314 cpumMsrWr_AmdFam10hMc4MiscN,
5315 cpumMsrWr_AmdK8PerfCtlN,
5316 cpumMsrWr_AmdK8PerfCtrN,
5317 cpumMsrWr_AmdK8SysCfg,
5318 cpumMsrWr_AmdK8HwCr,
5319 cpumMsrWr_AmdK8IorrBaseN,
5320 cpumMsrWr_AmdK8IorrMaskN,
5321 cpumMsrWr_AmdK8TopOfMemN,
5322 cpumMsrWr_AmdK8NbCfg1,
5323 cpumMsrWr_AmdK8McXcptRedir,
5324 cpumMsrWr_AmdK8CpuNameN,
5325 cpumMsrWr_AmdK8HwThermalCtrl,
5326 cpumMsrWr_AmdK8SwThermalCtrl,
5327 cpumMsrWr_AmdK8FidVidControl,
5328 cpumMsrWr_AmdK8McCtlMaskN,
5329 cpumMsrWr_AmdK8SmiOnIoTrapN,
5330 cpumMsrWr_AmdK8SmiOnIoTrapCtlSts,
5331 cpumMsrWr_AmdK8IntPendingMessage,
5332 cpumMsrWr_AmdK8SmiTriggerIoCycle,
5333 cpumMsrWr_AmdFam10hMmioCfgBaseAddr,
5334 cpumMsrWr_AmdFam10hTrapCtlMaybe,
5335 cpumMsrWr_AmdFam10hPStateControl,
5336 cpumMsrWr_AmdFam10hPStateStatus,
5337 cpumMsrWr_AmdFam10hPStateN,
5338 cpumMsrWr_AmdFam10hCofVidControl,
5339 cpumMsrWr_AmdFam10hCofVidStatus,
5340 cpumMsrWr_AmdFam10hCStateIoBaseAddr,
5341 cpumMsrWr_AmdFam10hCpuWatchdogTimer,
5342 cpumMsrWr_AmdK8SmmBase,
5343 cpumMsrWr_AmdK8SmmAddr,
5344 cpumMsrWr_AmdK8SmmMask,
5345 cpumMsrWr_AmdK8VmCr,
5346 cpumMsrWr_AmdK8IgnNe,
5347 cpumMsrWr_AmdK8SmmCtl,
5348 cpumMsrWr_AmdK8VmHSavePa,
5349 cpumMsrWr_AmdFam10hVmLockKey,
5350 cpumMsrWr_AmdFam10hSmmLockKey,
5351 cpumMsrWr_AmdFam10hLocalSmiStatus,
5352 cpumMsrWr_AmdFam10hOsVisWrkIdLength,
5353 cpumMsrWr_AmdFam10hOsVisWrkStatus,
5354 cpumMsrWr_AmdFam16hL2IPerfCtlN,
5355 cpumMsrWr_AmdFam16hL2IPerfCtrN,
5356 cpumMsrWr_AmdFam15hNorthbridgePerfCtlN,
5357 cpumMsrWr_AmdFam15hNorthbridgePerfCtrN,
5358 cpumMsrWr_AmdK7MicrocodeCtl,
5359 cpumMsrWr_AmdK7ClusterIdMaybe,
5360 cpumMsrWr_AmdK8CpuIdCtlStd07hEbax,
5361 cpumMsrWr_AmdK8CpuIdCtlStd06hEcx,
5362 cpumMsrWr_AmdK8CpuIdCtlStd01hEdcx,
5363 cpumMsrWr_AmdK8CpuIdCtlExt01hEdcx,
5364 cpumMsrWr_AmdK8PatchLoader,
5365 cpumMsrWr_AmdK7DebugStatusMaybe,
5366 cpumMsrWr_AmdK7BHTraceBaseMaybe,
5367 cpumMsrWr_AmdK7BHTracePtrMaybe,
5368 cpumMsrWr_AmdK7BHTraceLimitMaybe,
5369 cpumMsrWr_AmdK7HardwareDebugToolCfgMaybe,
5370 cpumMsrWr_AmdK7FastFlushCountMaybe,
5371 cpumMsrWr_AmdK7NodeId,
5372 cpumMsrWr_AmdK7DrXAddrMaskN,
5373 cpumMsrWr_AmdK7Dr0DataMatchMaybe,
5374 cpumMsrWr_AmdK7Dr0DataMaskMaybe,
5375 cpumMsrWr_AmdK7LoadStoreCfg,
5376 cpumMsrWr_AmdK7InstrCacheCfg,
5377 cpumMsrWr_AmdK7DataCacheCfg,
5378 cpumMsrWr_AmdK7BusUnitCfg,
5379 cpumMsrWr_AmdK7DebugCtl2Maybe,
5380 cpumMsrWr_AmdFam15hFpuCfg,
5381 cpumMsrWr_AmdFam15hDecoderCfg,
5382 cpumMsrWr_AmdFam10hBusUnitCfg2,
5383 cpumMsrWr_AmdFam15hCombUnitCfg,
5384 cpumMsrWr_AmdFam15hCombUnitCfg2,
5385 cpumMsrWr_AmdFam15hCombUnitCfg3,
5386 cpumMsrWr_AmdFam15hExecUnitCfg,
5387 cpumMsrWr_AmdFam15hLoadStoreCfg2,
5388 cpumMsrWr_AmdFam10hIbsFetchCtl,
5389 cpumMsrWr_AmdFam10hIbsFetchLinAddr,
5390 cpumMsrWr_AmdFam10hIbsFetchPhysAddr,
5391 cpumMsrWr_AmdFam10hIbsOpExecCtl,
5392 cpumMsrWr_AmdFam10hIbsOpRip,
5393 cpumMsrWr_AmdFam10hIbsOpData,
5394 cpumMsrWr_AmdFam10hIbsOpData2,
5395 cpumMsrWr_AmdFam10hIbsOpData3,
5396 cpumMsrWr_AmdFam10hIbsDcLinAddr,
5397 cpumMsrWr_AmdFam10hIbsDcPhysAddr,
5398 cpumMsrWr_AmdFam10hIbsCtl,
5399 cpumMsrWr_AmdFam14hIbsBrTarget,
5400
5401 cpumMsrWr_Gim
5402};
5403
5404
5405/**
5406 * Looks up the range for the given MSR.
5407 *
5408 * @returns Pointer to the range if found, NULL if not.
5409 * @param pVM The cross context VM structure.
5410 * @param idMsr The MSR to look up.
5411 */
5412# ifndef IN_RING3
5413static
5414# endif
5415PCPUMMSRRANGE cpumLookupMsrRange(PVM pVM, uint32_t idMsr)
5416{
5417 /*
5418 * Binary lookup.
5419 */
5420 uint32_t cRanges = pVM->cpum.s.GuestInfo.cMsrRanges;
5421 if (!cRanges)
5422 return NULL;
5423 PCPUMMSRRANGE paRanges = pVM->cpum.s.GuestInfo.CTX_SUFF(paMsrRanges);
5424 for (;;)
5425 {
5426 uint32_t i = cRanges / 2;
5427 if (idMsr < paRanges[i].uFirst)
5428 {
5429 if (i == 0)
5430 break;
5431 cRanges = i;
5432 }
5433 else if (idMsr > paRanges[i].uLast)
5434 {
5435 i++;
5436 if (i >= cRanges)
5437 break;
5438 cRanges -= i;
5439 paRanges = &paRanges[i];
5440 }
5441 else
5442 {
5443 if (paRanges[i].enmRdFn == kCpumMsrRdFn_MsrAlias)
5444 return cpumLookupMsrRange(pVM, paRanges[i].uValue);
5445 return &paRanges[i];
5446 }
5447 }
5448
5449# ifdef VBOX_STRICT
5450 /*
5451 * Linear lookup to verify the above binary search.
5452 */
5453 uint32_t cLeft = pVM->cpum.s.GuestInfo.cMsrRanges;
5454 PCPUMMSRRANGE pCur = pVM->cpum.s.GuestInfo.CTX_SUFF(paMsrRanges);
5455 while (cLeft-- > 0)
5456 {
5457 if (idMsr >= pCur->uFirst && idMsr <= pCur->uLast)
5458 {
5459 AssertFailed();
5460 if (pCur->enmRdFn == kCpumMsrRdFn_MsrAlias)
5461 return cpumLookupMsrRange(pVM, pCur->uValue);
5462 return pCur;
5463 }
5464 pCur++;
5465 }
5466# endif
5467 return NULL;
5468}
5469
5470
5471/**
5472 * Query a guest MSR.
5473 *
5474 * The caller is responsible for checking privilege if the call is the result of
5475 * a RDMSR instruction. We'll do the rest.
5476 *
5477 * @retval VINF_SUCCESS on success.
5478 * @retval VINF_CPUM_R3_MSR_READ if the MSR read could not be serviced in the
5479 * current context (raw-mode or ring-0).
5480 * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR), the caller is
5481 * expected to take the appropriate actions. @a *puValue is set to 0.
5482 * @param pVCpu The cross context virtual CPU structure.
5483 * @param idMsr The MSR.
5484 * @param puValue Where to return the value.
5485 *
5486 * @remarks This will always return the right values, even when we're in the
5487 * recompiler.
5488 */
5489VMMDECL(VBOXSTRICTRC) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue)
5490{
5491 *puValue = 0;
5492
5493 VBOXSTRICTRC rcStrict;
5494 PVM pVM = pVCpu->CTX_SUFF(pVM);
5495 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, idMsr);
5496 if (pRange)
5497 {
5498 CPUMMSRRDFN enmRdFn = (CPUMMSRRDFN)pRange->enmRdFn;
5499 AssertReturn(enmRdFn > kCpumMsrRdFn_Invalid && enmRdFn < kCpumMsrRdFn_End, VERR_CPUM_IPE_1);
5500
5501 PFNCPUMRDMSR pfnRdMsr = g_aCpumRdMsrFns[enmRdFn];
5502 AssertReturn(pfnRdMsr, VERR_CPUM_IPE_2);
5503
5504 STAM_COUNTER_INC(&pRange->cReads);
5505 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReads);
5506
5507 rcStrict = pfnRdMsr(pVCpu, idMsr, pRange, puValue);
5508 if (rcStrict == VINF_SUCCESS)
5509 Log2(("CPUM: RDMSR %#x (%s) -> %#llx\n", idMsr, pRange->szName, *puValue));
5510 else if (rcStrict == VERR_CPUM_RAISE_GP_0)
5511 {
5512 Log(("CPUM: RDMSR %#x (%s) -> #GP(0)\n", idMsr, pRange->szName));
5513 STAM_COUNTER_INC(&pRange->cGps);
5514 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReadsRaiseGp);
5515 }
5516#ifndef IN_RING3
5517 else if (rcStrict == VINF_CPUM_R3_MSR_READ)
5518 Log(("CPUM: RDMSR %#x (%s) -> ring-3\n", idMsr, pRange->szName));
5519#endif
5520 else
5521 {
5522 Log(("CPUM: RDMSR %#x (%s) -> rcStrict=%Rrc\n", idMsr, pRange->szName, VBOXSTRICTRC_VAL(rcStrict)));
5523 AssertMsgStmt(RT_FAILURE_NP(rcStrict), ("%Rrc idMsr=%#x\n", VBOXSTRICTRC_VAL(rcStrict), idMsr),
5524 rcStrict = VERR_IPE_UNEXPECTED_INFO_STATUS);
5525 Assert(rcStrict != VERR_EM_INTERPRETER);
5526 }
5527 }
5528 else
5529 {
5530 Log(("CPUM: Unknown RDMSR %#x -> #GP(0)\n", idMsr));
5531 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReads);
5532 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReadsUnknown);
5533 rcStrict = VERR_CPUM_RAISE_GP_0;
5534 }
5535 return rcStrict;
5536}
5537
5538
5539/**
5540 * Writes to a guest MSR.
5541 *
5542 * The caller is responsible for checking privilege if the call is the result of
5543 * a WRMSR instruction. We'll do the rest.
5544 *
5545 * @retval VINF_SUCCESS on success.
5546 * @retval VINF_CPUM_R3_MSR_WRITE if the MSR write could not be serviced in the
5547 * current context (raw-mode or ring-0).
5548 * @retval VERR_CPUM_RAISE_GP_0 on failure, the caller is expected to take the
5549 * appropriate actions.
5550 *
5551 * @param pVCpu The cross context virtual CPU structure.
5552 * @param idMsr The MSR id.
5553 * @param uValue The value to set.
5554 *
5555 * @remarks Everyone changing MSR values, including the recompiler, shall do it
5556 * by calling this method. This makes sure we have current values and
5557 * that we trigger all the right actions when something changes.
5558 *
5559 * For performance reasons, this actually isn't entirely true for some
5560 * MSRs when in HM mode. The code here and in HM must be aware of
5561 * this.
5562 */
5563VMMDECL(VBOXSTRICTRC) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue)
5564{
5565 VBOXSTRICTRC rcStrict;
5566 PVM pVM = pVCpu->CTX_SUFF(pVM);
5567 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, idMsr);
5568 if (pRange)
5569 {
5570 STAM_COUNTER_INC(&pRange->cWrites);
5571 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWrites);
5572
5573 if (!(uValue & pRange->fWrGpMask))
5574 {
5575 CPUMMSRWRFN enmWrFn = (CPUMMSRWRFN)pRange->enmWrFn;
5576 AssertReturn(enmWrFn > kCpumMsrWrFn_Invalid && enmWrFn < kCpumMsrWrFn_End, VERR_CPUM_IPE_1);
5577
5578 PFNCPUMWRMSR pfnWrMsr = g_aCpumWrMsrFns[enmWrFn];
5579 AssertReturn(pfnWrMsr, VERR_CPUM_IPE_2);
5580
5581 uint64_t uValueAdjusted = uValue & ~pRange->fWrIgnMask;
5582 if (uValueAdjusted != uValue)
5583 {
5584 STAM_COUNTER_INC(&pRange->cIgnoredBits);
5585 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesToIgnoredBits);
5586 }
5587
5588 rcStrict = pfnWrMsr(pVCpu, idMsr, pRange, uValueAdjusted, uValue);
5589 if (rcStrict == VINF_SUCCESS)
5590 Log2(("CPUM: WRMSR %#x (%s), %#llx [%#llx]\n", idMsr, pRange->szName, uValueAdjusted, uValue));
5591 else if (rcStrict == VERR_CPUM_RAISE_GP_0)
5592 {
5593 Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> #GP(0)\n", idMsr, pRange->szName, uValueAdjusted, uValue));
5594 STAM_COUNTER_INC(&pRange->cGps);
5595 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesRaiseGp);
5596 }
5597#ifndef IN_RING3
5598 else if (rcStrict == VINF_CPUM_R3_MSR_WRITE)
5599 Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> ring-3\n", idMsr, pRange->szName, uValueAdjusted, uValue));
5600#endif
5601 else
5602 {
5603 Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> rcStrict=%Rrc\n",
5604 idMsr, pRange->szName, uValueAdjusted, uValue, VBOXSTRICTRC_VAL(rcStrict)));
5605 AssertMsgStmt(RT_FAILURE_NP(rcStrict), ("%Rrc idMsr=%#x\n", VBOXSTRICTRC_VAL(rcStrict), idMsr),
5606 rcStrict = VERR_IPE_UNEXPECTED_INFO_STATUS);
5607 Assert(rcStrict != VERR_EM_INTERPRETER);
5608 }
5609 }
5610 else
5611 {
5612 Log(("CPUM: WRMSR %#x (%s), %#llx -> #GP(0) - invalid bits %#llx\n",
5613 idMsr, pRange->szName, uValue, uValue & pRange->fWrGpMask));
5614 STAM_COUNTER_INC(&pRange->cGps);
5615 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesRaiseGp);
5616 rcStrict = VERR_CPUM_RAISE_GP_0;
5617 }
5618 }
5619 else
5620 {
5621 Log(("CPUM: Unknown WRMSR %#x, %#llx -> #GP(0)\n", idMsr, uValue));
5622 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWrites);
5623 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesUnknown);
5624 rcStrict = VERR_CPUM_RAISE_GP_0;
5625 }
5626 return rcStrict;
5627}
5628
5629
5630#if defined(VBOX_STRICT) && defined(IN_RING3)
5631/**
5632 * Performs some checks on the static data related to MSRs.
5633 *
5634 * @returns VINF_SUCCESS on success, error on failure.
5635 */
5636int cpumR3MsrStrictInitChecks(void)
5637{
5638#define CPUM_ASSERT_RD_MSR_FN(a_Register) \
5639 AssertReturn(g_aCpumRdMsrFns[kCpumMsrRdFn_##a_Register] == cpumMsrRd_##a_Register, VERR_CPUM_IPE_2);
5640#define CPUM_ASSERT_WR_MSR_FN(a_Register) \
5641 AssertReturn(g_aCpumWrMsrFns[kCpumMsrWrFn_##a_Register] == cpumMsrWr_##a_Register, VERR_CPUM_IPE_2);
5642
5643 AssertReturn(g_aCpumRdMsrFns[kCpumMsrRdFn_Invalid] == NULL, VERR_CPUM_IPE_2);
5644 CPUM_ASSERT_RD_MSR_FN(FixedValue);
5645 CPUM_ASSERT_RD_MSR_FN(WriteOnly);
5646 CPUM_ASSERT_RD_MSR_FN(Ia32P5McAddr);
5647 CPUM_ASSERT_RD_MSR_FN(Ia32P5McType);
5648 CPUM_ASSERT_RD_MSR_FN(Ia32TimestampCounter);
5649 CPUM_ASSERT_RD_MSR_FN(Ia32PlatformId);
5650 CPUM_ASSERT_RD_MSR_FN(Ia32ApicBase);
5651 CPUM_ASSERT_RD_MSR_FN(Ia32FeatureControl);
5652 CPUM_ASSERT_RD_MSR_FN(Ia32BiosSignId);
5653 CPUM_ASSERT_RD_MSR_FN(Ia32SmmMonitorCtl);
5654 CPUM_ASSERT_RD_MSR_FN(Ia32PmcN);
5655 CPUM_ASSERT_RD_MSR_FN(Ia32MonitorFilterLineSize);
5656 CPUM_ASSERT_RD_MSR_FN(Ia32MPerf);
5657 CPUM_ASSERT_RD_MSR_FN(Ia32APerf);
5658 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrCap);
5659 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrPhysBaseN);
5660 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrPhysMaskN);
5661 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrFixed);
5662 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrDefType);
5663 CPUM_ASSERT_RD_MSR_FN(Ia32Pat);
5664 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterCs);
5665 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterEsp);
5666 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterEip);
5667 CPUM_ASSERT_RD_MSR_FN(Ia32McgCap);
5668 CPUM_ASSERT_RD_MSR_FN(Ia32McgStatus);
5669 CPUM_ASSERT_RD_MSR_FN(Ia32McgCtl);
5670 CPUM_ASSERT_RD_MSR_FN(Ia32DebugCtl);
5671 CPUM_ASSERT_RD_MSR_FN(Ia32SmrrPhysBase);
5672 CPUM_ASSERT_RD_MSR_FN(Ia32SmrrPhysMask);
5673 CPUM_ASSERT_RD_MSR_FN(Ia32PlatformDcaCap);
5674 CPUM_ASSERT_RD_MSR_FN(Ia32CpuDcaCap);
5675 CPUM_ASSERT_RD_MSR_FN(Ia32Dca0Cap);
5676 CPUM_ASSERT_RD_MSR_FN(Ia32PerfEvtSelN);
5677 CPUM_ASSERT_RD_MSR_FN(Ia32PerfStatus);
5678 CPUM_ASSERT_RD_MSR_FN(Ia32PerfCtl);
5679 CPUM_ASSERT_RD_MSR_FN(Ia32FixedCtrN);
5680 CPUM_ASSERT_RD_MSR_FN(Ia32PerfCapabilities);
5681 CPUM_ASSERT_RD_MSR_FN(Ia32FixedCtrCtrl);
5682 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalStatus);
5683 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalCtrl);
5684 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalOvfCtrl);
5685 CPUM_ASSERT_RD_MSR_FN(Ia32PebsEnable);
5686 CPUM_ASSERT_RD_MSR_FN(Ia32ClockModulation);
5687 CPUM_ASSERT_RD_MSR_FN(Ia32ThermInterrupt);
5688 CPUM_ASSERT_RD_MSR_FN(Ia32ThermStatus);
5689 CPUM_ASSERT_RD_MSR_FN(Ia32MiscEnable);
5690 CPUM_ASSERT_RD_MSR_FN(Ia32McCtlStatusAddrMiscN);
5691 CPUM_ASSERT_RD_MSR_FN(Ia32McNCtl2);
5692 CPUM_ASSERT_RD_MSR_FN(Ia32DsArea);
5693 CPUM_ASSERT_RD_MSR_FN(Ia32TscDeadline);
5694 CPUM_ASSERT_RD_MSR_FN(Ia32X2ApicN);
5695 CPUM_ASSERT_RD_MSR_FN(Ia32DebugInterface);
5696 CPUM_ASSERT_RD_MSR_FN(Ia32VmxBase);
5697 CPUM_ASSERT_RD_MSR_FN(Ia32VmxPinbasedCtls);
5698 CPUM_ASSERT_RD_MSR_FN(Ia32VmxProcbasedCtls);
5699 CPUM_ASSERT_RD_MSR_FN(Ia32VmxExitCtls);
5700 CPUM_ASSERT_RD_MSR_FN(Ia32VmxEntryCtls);
5701 CPUM_ASSERT_RD_MSR_FN(Ia32VmxMisc);
5702 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr0Fixed0);
5703 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr0Fixed1);
5704 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr4Fixed0);
5705 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr4Fixed1);
5706 CPUM_ASSERT_RD_MSR_FN(Ia32VmxVmcsEnum);
5707 CPUM_ASSERT_RD_MSR_FN(Ia32VmxProcBasedCtls2);
5708 CPUM_ASSERT_RD_MSR_FN(Ia32VmxEptVpidCap);
5709 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTruePinbasedCtls);
5710 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueProcbasedCtls);
5711 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueExitCtls);
5712 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueEntryCtls);
5713 CPUM_ASSERT_RD_MSR_FN(Ia32VmxVmFunc);
5714
5715 CPUM_ASSERT_RD_MSR_FN(Amd64Efer);
5716 CPUM_ASSERT_RD_MSR_FN(Amd64SyscallTarget);
5717 CPUM_ASSERT_RD_MSR_FN(Amd64LongSyscallTarget);
5718 CPUM_ASSERT_RD_MSR_FN(Amd64CompSyscallTarget);
5719 CPUM_ASSERT_RD_MSR_FN(Amd64SyscallFlagMask);
5720 CPUM_ASSERT_RD_MSR_FN(Amd64FsBase);
5721 CPUM_ASSERT_RD_MSR_FN(Amd64GsBase);
5722 CPUM_ASSERT_RD_MSR_FN(Amd64KernelGsBase);
5723 CPUM_ASSERT_RD_MSR_FN(Amd64TscAux);
5724
5725 CPUM_ASSERT_RD_MSR_FN(IntelEblCrPowerOn);
5726 CPUM_ASSERT_RD_MSR_FN(IntelI7CoreThreadCount);
5727 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcHardPowerOn);
5728 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcSoftPowerOn);
5729 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcFrequencyId);
5730 CPUM_ASSERT_RD_MSR_FN(IntelP6FsbFrequency);
5731 CPUM_ASSERT_RD_MSR_FN(IntelPlatformInfo);
5732 CPUM_ASSERT_RD_MSR_FN(IntelFlexRatio);
5733 CPUM_ASSERT_RD_MSR_FN(IntelPkgCStConfigControl);
5734 CPUM_ASSERT_RD_MSR_FN(IntelPmgIoCaptureBase);
5735 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchFromToN);
5736 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchFromN);
5737 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchToN);
5738 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchTos);
5739 CPUM_ASSERT_RD_MSR_FN(IntelBblCrCtl);
5740 CPUM_ASSERT_RD_MSR_FN(IntelBblCrCtl3);
5741 CPUM_ASSERT_RD_MSR_FN(IntelI7TemperatureTarget);
5742 CPUM_ASSERT_RD_MSR_FN(IntelI7MsrOffCoreResponseN);
5743 CPUM_ASSERT_RD_MSR_FN(IntelI7MiscPwrMgmt);
5744 CPUM_ASSERT_RD_MSR_FN(IntelP6CrN);
5745 CPUM_ASSERT_RD_MSR_FN(IntelCpuId1FeatureMaskEcdx);
5746 CPUM_ASSERT_RD_MSR_FN(IntelCpuId1FeatureMaskEax);
5747 CPUM_ASSERT_RD_MSR_FN(IntelCpuId80000001FeatureMaskEcdx);
5748 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyAesNiCtl);
5749 CPUM_ASSERT_RD_MSR_FN(IntelI7TurboRatioLimit);
5750 CPUM_ASSERT_RD_MSR_FN(IntelI7LbrSelect);
5751 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyErrorControl);
5752 CPUM_ASSERT_RD_MSR_FN(IntelI7VirtualLegacyWireCap);
5753 CPUM_ASSERT_RD_MSR_FN(IntelI7PowerCtl);
5754 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPebsNumAlt);
5755 CPUM_ASSERT_RD_MSR_FN(IntelI7PebsLdLat);
5756 CPUM_ASSERT_RD_MSR_FN(IntelI7PkgCnResidencyN);
5757 CPUM_ASSERT_RD_MSR_FN(IntelI7CoreCnResidencyN);
5758 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyVrCurrentConfig);
5759 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyVrMiscConfig);
5760 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyRaplPowerUnit);
5761 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPkgCnIrtlN);
5762 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPkgC2Residency);
5763 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPowerLimit);
5764 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgEnergyStatus);
5765 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPerfStatus);
5766 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPowerInfo);
5767 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPowerLimit);
5768 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramEnergyStatus);
5769 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPerfStatus);
5770 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPowerInfo);
5771 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0PowerLimit);
5772 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0EnergyStatus);
5773 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0Policy);
5774 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0PerfStatus);
5775 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1PowerLimit);
5776 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1EnergyStatus);
5777 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1Policy);
5778 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpNominal);
5779 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpLevel1);
5780 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpLevel2);
5781 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpControl);
5782 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyTurboActivationRatio);
5783 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalCtrl);
5784 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalStatus);
5785 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalOvfCtrl);
5786 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfFixedCtrCtrl);
5787 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfFixedCtr);
5788 CPUM_ASSERT_RD_MSR_FN(IntelI7UncCBoxConfig);
5789 CPUM_ASSERT_RD_MSR_FN(IntelI7UncArbPerfCtrN);
5790 CPUM_ASSERT_RD_MSR_FN(IntelI7UncArbPerfEvtSelN);
5791 CPUM_ASSERT_RD_MSR_FN(IntelI7SmiCount);
5792 CPUM_ASSERT_RD_MSR_FN(IntelCore2EmttmCrTablesN);
5793 CPUM_ASSERT_RD_MSR_FN(IntelCore2SmmCStMiscInfo);
5794 CPUM_ASSERT_RD_MSR_FN(IntelCore1ExtConfig);
5795 CPUM_ASSERT_RD_MSR_FN(IntelCore1DtsCalControl);
5796 CPUM_ASSERT_RD_MSR_FN(IntelCore2PeciControl);
5797 CPUM_ASSERT_RD_MSR_FN(IntelAtSilvCoreC1Recidency);
5798
5799 CPUM_ASSERT_RD_MSR_FN(P6LastBranchFromIp);
5800 CPUM_ASSERT_RD_MSR_FN(P6LastBranchToIp);
5801 CPUM_ASSERT_RD_MSR_FN(P6LastIntFromIp);
5802 CPUM_ASSERT_RD_MSR_FN(P6LastIntToIp);
5803
5804 CPUM_ASSERT_RD_MSR_FN(AmdFam15hTscRate);
5805 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLwpCfg);
5806 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLwpCbAddr);
5807 CPUM_ASSERT_RD_MSR_FN(AmdFam10hMc4MiscN);
5808 CPUM_ASSERT_RD_MSR_FN(AmdK8PerfCtlN);
5809 CPUM_ASSERT_RD_MSR_FN(AmdK8PerfCtrN);
5810 CPUM_ASSERT_RD_MSR_FN(AmdK8SysCfg);
5811 CPUM_ASSERT_RD_MSR_FN(AmdK8HwCr);
5812 CPUM_ASSERT_RD_MSR_FN(AmdK8IorrBaseN);
5813 CPUM_ASSERT_RD_MSR_FN(AmdK8IorrMaskN);
5814 CPUM_ASSERT_RD_MSR_FN(AmdK8TopOfMemN);
5815 CPUM_ASSERT_RD_MSR_FN(AmdK8NbCfg1);
5816 CPUM_ASSERT_RD_MSR_FN(AmdK8McXcptRedir);
5817 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuNameN);
5818 CPUM_ASSERT_RD_MSR_FN(AmdK8HwThermalCtrl);
5819 CPUM_ASSERT_RD_MSR_FN(AmdK8SwThermalCtrl);
5820 CPUM_ASSERT_RD_MSR_FN(AmdK8FidVidControl);
5821 CPUM_ASSERT_RD_MSR_FN(AmdK8FidVidStatus);
5822 CPUM_ASSERT_RD_MSR_FN(AmdK8McCtlMaskN);
5823 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiOnIoTrapN);
5824 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiOnIoTrapCtlSts);
5825 CPUM_ASSERT_RD_MSR_FN(AmdK8IntPendingMessage);
5826 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiTriggerIoCycle);
5827 CPUM_ASSERT_RD_MSR_FN(AmdFam10hMmioCfgBaseAddr);
5828 CPUM_ASSERT_RD_MSR_FN(AmdFam10hTrapCtlMaybe);
5829 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateCurLimit);
5830 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateControl);
5831 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateStatus);
5832 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateN);
5833 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCofVidControl);
5834 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCofVidStatus);
5835 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCStateIoBaseAddr);
5836 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCpuWatchdogTimer);
5837 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmBase);
5838 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmAddr);
5839 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmMask);
5840 CPUM_ASSERT_RD_MSR_FN(AmdK8VmCr);
5841 CPUM_ASSERT_RD_MSR_FN(AmdK8IgnNe);
5842 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmCtl);
5843 CPUM_ASSERT_RD_MSR_FN(AmdK8VmHSavePa);
5844 CPUM_ASSERT_RD_MSR_FN(AmdFam10hVmLockKey);
5845 CPUM_ASSERT_RD_MSR_FN(AmdFam10hSmmLockKey);
5846 CPUM_ASSERT_RD_MSR_FN(AmdFam10hLocalSmiStatus);
5847 CPUM_ASSERT_RD_MSR_FN(AmdFam10hOsVisWrkIdLength);
5848 CPUM_ASSERT_RD_MSR_FN(AmdFam10hOsVisWrkStatus);
5849 CPUM_ASSERT_RD_MSR_FN(AmdFam16hL2IPerfCtlN);
5850 CPUM_ASSERT_RD_MSR_FN(AmdFam16hL2IPerfCtrN);
5851 CPUM_ASSERT_RD_MSR_FN(AmdFam15hNorthbridgePerfCtlN);
5852 CPUM_ASSERT_RD_MSR_FN(AmdFam15hNorthbridgePerfCtrN);
5853 CPUM_ASSERT_RD_MSR_FN(AmdK7MicrocodeCtl);
5854 CPUM_ASSERT_RD_MSR_FN(AmdK7ClusterIdMaybe);
5855 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd07hEbax);
5856 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd06hEcx);
5857 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd01hEdcx);
5858 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlExt01hEdcx);
5859 CPUM_ASSERT_RD_MSR_FN(AmdK8PatchLevel);
5860 CPUM_ASSERT_RD_MSR_FN(AmdK7DebugStatusMaybe);
5861 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTraceBaseMaybe);
5862 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTracePtrMaybe);
5863 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTraceLimitMaybe);
5864 CPUM_ASSERT_RD_MSR_FN(AmdK7HardwareDebugToolCfgMaybe);
5865 CPUM_ASSERT_RD_MSR_FN(AmdK7FastFlushCountMaybe);
5866 CPUM_ASSERT_RD_MSR_FN(AmdK7NodeId);
5867 CPUM_ASSERT_RD_MSR_FN(AmdK7DrXAddrMaskN);
5868 CPUM_ASSERT_RD_MSR_FN(AmdK7Dr0DataMatchMaybe);
5869 CPUM_ASSERT_RD_MSR_FN(AmdK7Dr0DataMaskMaybe);
5870 CPUM_ASSERT_RD_MSR_FN(AmdK7LoadStoreCfg);
5871 CPUM_ASSERT_RD_MSR_FN(AmdK7InstrCacheCfg);
5872 CPUM_ASSERT_RD_MSR_FN(AmdK7DataCacheCfg);
5873 CPUM_ASSERT_RD_MSR_FN(AmdK7BusUnitCfg);
5874 CPUM_ASSERT_RD_MSR_FN(AmdK7DebugCtl2Maybe);
5875 CPUM_ASSERT_RD_MSR_FN(AmdFam15hFpuCfg);
5876 CPUM_ASSERT_RD_MSR_FN(AmdFam15hDecoderCfg);
5877 CPUM_ASSERT_RD_MSR_FN(AmdFam10hBusUnitCfg2);
5878 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg);
5879 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg2);
5880 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg3);
5881 CPUM_ASSERT_RD_MSR_FN(AmdFam15hExecUnitCfg);
5882 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLoadStoreCfg2);
5883 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchCtl);
5884 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchLinAddr);
5885 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchPhysAddr);
5886 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpExecCtl);
5887 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpRip);
5888 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData);
5889 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData2);
5890 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData3);
5891 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsDcLinAddr);
5892 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsDcPhysAddr);
5893 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsCtl);
5894 CPUM_ASSERT_RD_MSR_FN(AmdFam14hIbsBrTarget);
5895
5896 CPUM_ASSERT_RD_MSR_FN(Gim)
5897
5898 AssertReturn(g_aCpumWrMsrFns[kCpumMsrWrFn_Invalid] == NULL, VERR_CPUM_IPE_2);
5899 CPUM_ASSERT_WR_MSR_FN(Ia32P5McAddr);
5900 CPUM_ASSERT_WR_MSR_FN(Ia32P5McType);
5901 CPUM_ASSERT_WR_MSR_FN(Ia32TimestampCounter);
5902 CPUM_ASSERT_WR_MSR_FN(Ia32ApicBase);
5903 CPUM_ASSERT_WR_MSR_FN(Ia32FeatureControl);
5904 CPUM_ASSERT_WR_MSR_FN(Ia32BiosSignId);
5905 CPUM_ASSERT_WR_MSR_FN(Ia32BiosUpdateTrigger);
5906 CPUM_ASSERT_WR_MSR_FN(Ia32SmmMonitorCtl);
5907 CPUM_ASSERT_WR_MSR_FN(Ia32PmcN);
5908 CPUM_ASSERT_WR_MSR_FN(Ia32MonitorFilterLineSize);
5909 CPUM_ASSERT_WR_MSR_FN(Ia32MPerf);
5910 CPUM_ASSERT_WR_MSR_FN(Ia32APerf);
5911 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrPhysBaseN);
5912 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrPhysMaskN);
5913 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrFixed);
5914 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrDefType);
5915 CPUM_ASSERT_WR_MSR_FN(Ia32Pat);
5916 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterCs);
5917 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterEsp);
5918 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterEip);
5919 CPUM_ASSERT_WR_MSR_FN(Ia32McgStatus);
5920 CPUM_ASSERT_WR_MSR_FN(Ia32McgCtl);
5921 CPUM_ASSERT_WR_MSR_FN(Ia32DebugCtl);
5922 CPUM_ASSERT_WR_MSR_FN(Ia32SmrrPhysBase);
5923 CPUM_ASSERT_WR_MSR_FN(Ia32SmrrPhysMask);
5924 CPUM_ASSERT_WR_MSR_FN(Ia32PlatformDcaCap);
5925 CPUM_ASSERT_WR_MSR_FN(Ia32Dca0Cap);
5926 CPUM_ASSERT_WR_MSR_FN(Ia32PerfEvtSelN);
5927 CPUM_ASSERT_WR_MSR_FN(Ia32PerfStatus);
5928 CPUM_ASSERT_WR_MSR_FN(Ia32PerfCtl);
5929 CPUM_ASSERT_WR_MSR_FN(Ia32FixedCtrN);
5930 CPUM_ASSERT_WR_MSR_FN(Ia32PerfCapabilities);
5931 CPUM_ASSERT_WR_MSR_FN(Ia32FixedCtrCtrl);
5932 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalStatus);
5933 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalCtrl);
5934 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalOvfCtrl);
5935 CPUM_ASSERT_WR_MSR_FN(Ia32PebsEnable);
5936 CPUM_ASSERT_WR_MSR_FN(Ia32ClockModulation);
5937 CPUM_ASSERT_WR_MSR_FN(Ia32ThermInterrupt);
5938 CPUM_ASSERT_WR_MSR_FN(Ia32ThermStatus);
5939 CPUM_ASSERT_WR_MSR_FN(Ia32MiscEnable);
5940 CPUM_ASSERT_WR_MSR_FN(Ia32McCtlStatusAddrMiscN);
5941 CPUM_ASSERT_WR_MSR_FN(Ia32McNCtl2);
5942 CPUM_ASSERT_WR_MSR_FN(Ia32DsArea);
5943 CPUM_ASSERT_WR_MSR_FN(Ia32TscDeadline);
5944 CPUM_ASSERT_WR_MSR_FN(Ia32X2ApicN);
5945 CPUM_ASSERT_WR_MSR_FN(Ia32DebugInterface);
5946
5947 CPUM_ASSERT_WR_MSR_FN(Amd64Efer);
5948 CPUM_ASSERT_WR_MSR_FN(Amd64SyscallTarget);
5949 CPUM_ASSERT_WR_MSR_FN(Amd64LongSyscallTarget);
5950 CPUM_ASSERT_WR_MSR_FN(Amd64CompSyscallTarget);
5951 CPUM_ASSERT_WR_MSR_FN(Amd64SyscallFlagMask);
5952 CPUM_ASSERT_WR_MSR_FN(Amd64FsBase);
5953 CPUM_ASSERT_WR_MSR_FN(Amd64GsBase);
5954 CPUM_ASSERT_WR_MSR_FN(Amd64KernelGsBase);
5955 CPUM_ASSERT_WR_MSR_FN(Amd64TscAux);
5956
5957 CPUM_ASSERT_WR_MSR_FN(IntelEblCrPowerOn);
5958 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcHardPowerOn);
5959 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcSoftPowerOn);
5960 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcFrequencyId);
5961 CPUM_ASSERT_WR_MSR_FN(IntelFlexRatio);
5962 CPUM_ASSERT_WR_MSR_FN(IntelPkgCStConfigControl);
5963 CPUM_ASSERT_WR_MSR_FN(IntelPmgIoCaptureBase);
5964 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchFromToN);
5965 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchFromN);
5966 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchToN);
5967 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchTos);
5968 CPUM_ASSERT_WR_MSR_FN(IntelBblCrCtl);
5969 CPUM_ASSERT_WR_MSR_FN(IntelBblCrCtl3);
5970 CPUM_ASSERT_WR_MSR_FN(IntelI7TemperatureTarget);
5971 CPUM_ASSERT_WR_MSR_FN(IntelI7MsrOffCoreResponseN);
5972 CPUM_ASSERT_WR_MSR_FN(IntelI7MiscPwrMgmt);
5973 CPUM_ASSERT_WR_MSR_FN(IntelP6CrN);
5974 CPUM_ASSERT_WR_MSR_FN(IntelCpuId1FeatureMaskEcdx);
5975 CPUM_ASSERT_WR_MSR_FN(IntelCpuId1FeatureMaskEax);
5976 CPUM_ASSERT_WR_MSR_FN(IntelCpuId80000001FeatureMaskEcdx);
5977 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyAesNiCtl);
5978 CPUM_ASSERT_WR_MSR_FN(IntelI7TurboRatioLimit);
5979 CPUM_ASSERT_WR_MSR_FN(IntelI7LbrSelect);
5980 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyErrorControl);
5981 CPUM_ASSERT_WR_MSR_FN(IntelI7PowerCtl);
5982 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPebsNumAlt);
5983 CPUM_ASSERT_WR_MSR_FN(IntelI7PebsLdLat);
5984 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyVrCurrentConfig);
5985 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyVrMiscConfig);
5986 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPkgCnIrtlN);
5987 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPkgC2Residency);
5988 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPkgPowerLimit);
5989 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplDramPowerLimit);
5990 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp0PowerLimit);
5991 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp0Policy);
5992 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp1PowerLimit);
5993 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp1Policy);
5994 CPUM_ASSERT_WR_MSR_FN(IntelI7IvyConfigTdpControl);
5995 CPUM_ASSERT_WR_MSR_FN(IntelI7IvyTurboActivationRatio);
5996 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalCtrl);
5997 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalStatus);
5998 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalOvfCtrl);
5999 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfFixedCtrCtrl);
6000 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfFixedCtr);
6001 CPUM_ASSERT_WR_MSR_FN(IntelI7UncArbPerfCtrN);
6002 CPUM_ASSERT_WR_MSR_FN(IntelI7UncArbPerfEvtSelN);
6003 CPUM_ASSERT_WR_MSR_FN(IntelCore2EmttmCrTablesN);
6004 CPUM_ASSERT_WR_MSR_FN(IntelCore2SmmCStMiscInfo);
6005 CPUM_ASSERT_WR_MSR_FN(IntelCore1ExtConfig);
6006 CPUM_ASSERT_WR_MSR_FN(IntelCore1DtsCalControl);
6007 CPUM_ASSERT_WR_MSR_FN(IntelCore2PeciControl);
6008
6009 CPUM_ASSERT_WR_MSR_FN(P6LastIntFromIp);
6010 CPUM_ASSERT_WR_MSR_FN(P6LastIntToIp);
6011
6012 CPUM_ASSERT_WR_MSR_FN(AmdFam15hTscRate);
6013 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLwpCfg);
6014 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLwpCbAddr);
6015 CPUM_ASSERT_WR_MSR_FN(AmdFam10hMc4MiscN);
6016 CPUM_ASSERT_WR_MSR_FN(AmdK8PerfCtlN);
6017 CPUM_ASSERT_WR_MSR_FN(AmdK8PerfCtrN);
6018 CPUM_ASSERT_WR_MSR_FN(AmdK8SysCfg);
6019 CPUM_ASSERT_WR_MSR_FN(AmdK8HwCr);
6020 CPUM_ASSERT_WR_MSR_FN(AmdK8IorrBaseN);
6021 CPUM_ASSERT_WR_MSR_FN(AmdK8IorrMaskN);
6022 CPUM_ASSERT_WR_MSR_FN(AmdK8TopOfMemN);
6023 CPUM_ASSERT_WR_MSR_FN(AmdK8NbCfg1);
6024 CPUM_ASSERT_WR_MSR_FN(AmdK8McXcptRedir);
6025 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuNameN);
6026 CPUM_ASSERT_WR_MSR_FN(AmdK8HwThermalCtrl);
6027 CPUM_ASSERT_WR_MSR_FN(AmdK8SwThermalCtrl);
6028 CPUM_ASSERT_WR_MSR_FN(AmdK8FidVidControl);
6029 CPUM_ASSERT_WR_MSR_FN(AmdK8McCtlMaskN);
6030 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiOnIoTrapN);
6031 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiOnIoTrapCtlSts);
6032 CPUM_ASSERT_WR_MSR_FN(AmdK8IntPendingMessage);
6033 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiTriggerIoCycle);
6034 CPUM_ASSERT_WR_MSR_FN(AmdFam10hMmioCfgBaseAddr);
6035 CPUM_ASSERT_WR_MSR_FN(AmdFam10hTrapCtlMaybe);
6036 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateControl);
6037 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateStatus);
6038 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateN);
6039 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCofVidControl);
6040 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCofVidStatus);
6041 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCStateIoBaseAddr);
6042 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCpuWatchdogTimer);
6043 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmBase);
6044 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmAddr);
6045 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmMask);
6046 CPUM_ASSERT_WR_MSR_FN(AmdK8VmCr);
6047 CPUM_ASSERT_WR_MSR_FN(AmdK8IgnNe);
6048 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmCtl);
6049 CPUM_ASSERT_WR_MSR_FN(AmdK8VmHSavePa);
6050 CPUM_ASSERT_WR_MSR_FN(AmdFam10hVmLockKey);
6051 CPUM_ASSERT_WR_MSR_FN(AmdFam10hSmmLockKey);
6052 CPUM_ASSERT_WR_MSR_FN(AmdFam10hLocalSmiStatus);
6053 CPUM_ASSERT_WR_MSR_FN(AmdFam10hOsVisWrkIdLength);
6054 CPUM_ASSERT_WR_MSR_FN(AmdFam10hOsVisWrkStatus);
6055 CPUM_ASSERT_WR_MSR_FN(AmdFam16hL2IPerfCtlN);
6056 CPUM_ASSERT_WR_MSR_FN(AmdFam16hL2IPerfCtrN);
6057 CPUM_ASSERT_WR_MSR_FN(AmdFam15hNorthbridgePerfCtlN);
6058 CPUM_ASSERT_WR_MSR_FN(AmdFam15hNorthbridgePerfCtrN);
6059 CPUM_ASSERT_WR_MSR_FN(AmdK7MicrocodeCtl);
6060 CPUM_ASSERT_WR_MSR_FN(AmdK7ClusterIdMaybe);
6061 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd07hEbax);
6062 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd06hEcx);
6063 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd01hEdcx);
6064 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlExt01hEdcx);
6065 CPUM_ASSERT_WR_MSR_FN(AmdK8PatchLoader);
6066 CPUM_ASSERT_WR_MSR_FN(AmdK7DebugStatusMaybe);
6067 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTraceBaseMaybe);
6068 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTracePtrMaybe);
6069 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTraceLimitMaybe);
6070 CPUM_ASSERT_WR_MSR_FN(AmdK7HardwareDebugToolCfgMaybe);
6071 CPUM_ASSERT_WR_MSR_FN(AmdK7FastFlushCountMaybe);
6072 CPUM_ASSERT_WR_MSR_FN(AmdK7NodeId);
6073 CPUM_ASSERT_WR_MSR_FN(AmdK7DrXAddrMaskN);
6074 CPUM_ASSERT_WR_MSR_FN(AmdK7Dr0DataMatchMaybe);
6075 CPUM_ASSERT_WR_MSR_FN(AmdK7Dr0DataMaskMaybe);
6076 CPUM_ASSERT_WR_MSR_FN(AmdK7LoadStoreCfg);
6077 CPUM_ASSERT_WR_MSR_FN(AmdK7InstrCacheCfg);
6078 CPUM_ASSERT_WR_MSR_FN(AmdK7DataCacheCfg);
6079 CPUM_ASSERT_WR_MSR_FN(AmdK7BusUnitCfg);
6080 CPUM_ASSERT_WR_MSR_FN(AmdK7DebugCtl2Maybe);
6081 CPUM_ASSERT_WR_MSR_FN(AmdFam15hFpuCfg);
6082 CPUM_ASSERT_WR_MSR_FN(AmdFam15hDecoderCfg);
6083 CPUM_ASSERT_WR_MSR_FN(AmdFam10hBusUnitCfg2);
6084 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg);
6085 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg2);
6086 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg3);
6087 CPUM_ASSERT_WR_MSR_FN(AmdFam15hExecUnitCfg);
6088 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLoadStoreCfg2);
6089 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchCtl);
6090 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchLinAddr);
6091 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchPhysAddr);
6092 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpExecCtl);
6093 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpRip);
6094 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData);
6095 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData2);
6096 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData3);
6097 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsDcLinAddr);
6098 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsDcPhysAddr);
6099 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsCtl);
6100 CPUM_ASSERT_WR_MSR_FN(AmdFam14hIbsBrTarget);
6101
6102 CPUM_ASSERT_WR_MSR_FN(Gim);
6103
6104 return VINF_SUCCESS;
6105}
6106#endif /* VBOX_STRICT && IN_RING3 */
6107
6108
6109/**
6110 * Gets the scalable bus frequency.
6111 *
6112 * The bus frequency is used as a base in several MSRs that gives the CPU and
6113 * other frequency ratios.
6114 *
6115 * @returns Scalable bus frequency in Hz. Will not return CPUM_SBUSFREQ_UNKNOWN.
6116 * @param pVM The cross context VM structure.
6117 */
6118VMMDECL(uint64_t) CPUMGetGuestScalableBusFrequency(PVM pVM)
6119{
6120 uint64_t uFreq = pVM->cpum.s.GuestInfo.uScalableBusFreq;
6121 if (uFreq == CPUM_SBUSFREQ_UNKNOWN)
6122 uFreq = CPUM_SBUSFREQ_100MHZ;
6123 return uFreq;
6124}
6125
6126
6127/**
6128 * Sets the guest EFER MSR without performing any additional checks.
6129 *
6130 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
6131 * @param uOldEfer The previous EFER MSR value.
6132 * @param uValidEfer The new, validated EFER MSR value.
6133 *
6134 * @remarks One would normally call CPUMQueryValidatedGuestEfer before calling this
6135 * function to change the EFER in order to perform an EFER transition.
6136 */
6137VMMDECL(void) CPUMSetGuestMsrEferNoCheck(PVMCPU pVCpu, uint64_t uOldEfer, uint64_t uValidEfer)
6138{
6139 pVCpu->cpum.s.Guest.msrEFER = uValidEfer;
6140
6141 /* AMD64 Architecture Programmer's Manual: 15.15 TLB Control; flush the TLB
6142 if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
6143 if ( (uOldEfer & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA))
6144 != (pVCpu->cpum.s.Guest.msrEFER & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA)))
6145 {
6146 /// @todo PGMFlushTLB(pVCpu, cr3, true /*fGlobal*/);
6147 HMFlushTLB(pVCpu);
6148
6149 /* Notify PGM about NXE changes. */
6150 if ( (uOldEfer & MSR_K6_EFER_NXE)
6151 != (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE))
6152 PGMNotifyNxeChanged(pVCpu, !(uOldEfer & MSR_K6_EFER_NXE));
6153 }
6154}
6155
6156
6157/**
6158 * Validates an EFER MSR write.
6159 *
6160 * @returns VBox status code.
6161 * @param pVM The cross context VM structure.
6162 * @param uCr0 The CR0 of the CPU corresponding to the EFER MSR.
6163 * @param uOldEfer Value of the previous EFER MSR on the CPU if any.
6164 * @param uNewEfer The new EFER MSR value being written.
6165 * @param puValidEfer Where to store the validated EFER (only updated if
6166 * this function returns VINF_SUCCESS).
6167 */
6168VMMDECL(int) CPUMQueryValidatedGuestEfer(PVM pVM, uint64_t uCr0, uint64_t uOldEfer, uint64_t uNewEfer, uint64_t *puValidEfer)
6169{
6170 uint32_t const fExtFeatures = pVM->cpum.s.aGuestCpuIdPatmExt[0].uEax >= 0x80000001
6171 ? pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx
6172 : 0;
6173 uint64_t fMask = 0;
6174 uint64_t const fIgnoreMask = MSR_K6_EFER_LMA;
6175
6176 /* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
6177 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_NX)
6178 fMask |= MSR_K6_EFER_NXE;
6179 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
6180 fMask |= MSR_K6_EFER_LME;
6181 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
6182 fMask |= MSR_K6_EFER_SCE;
6183 if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
6184 fMask |= MSR_K6_EFER_FFXSR;
6185 if (pVM->cpum.s.GuestFeatures.fSvm)
6186 fMask |= MSR_K6_EFER_SVME;
6187
6188 /* #GP(0) If anything outside the allowed bits is set. */
6189 if (uNewEfer & ~(fIgnoreMask | fMask))
6190 {
6191 Log(("CPUM: Settings disallowed EFER bit. uNewEfer=%#RX64 fAllowed=%#RX64 -> #GP(0)\n", uNewEfer, fMask));
6192 return VERR_CPUM_RAISE_GP_0;
6193 }
6194
6195 /* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if
6196 paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
6197 if ( (uOldEfer & MSR_K6_EFER_LME) != (uNewEfer & fMask & MSR_K6_EFER_LME)
6198 && (uCr0 & X86_CR0_PG))
6199 {
6200 Log(("CPUM: Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
6201 return VERR_CPUM_RAISE_GP_0;
6202 }
6203
6204 /* There are a few more: e.g. MSR_K6_EFER_LMSLE */
6205 AssertMsg(!(uNewEfer & ~( MSR_K6_EFER_NXE
6206 | MSR_K6_EFER_LME
6207 | MSR_K6_EFER_LMA /* ignored anyway */
6208 | MSR_K6_EFER_SCE
6209 | MSR_K6_EFER_FFXSR
6210 | MSR_K6_EFER_SVME)),
6211 ("Unexpected value %#RX64\n", uNewEfer));
6212
6213 *puValidEfer = (uOldEfer & ~fMask) | (uNewEfer & fMask);
6214 return VINF_SUCCESS;
6215}
6216
6217#ifdef IN_RING0
6218
6219/**
6220 * Fast way for HM to access the MSR_K8_TSC_AUX register.
6221 *
6222 * @returns The register value.
6223 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
6224 * @thread EMT(pVCpu)
6225 */
6226VMMR0_INT_DECL(uint64_t) CPUMR0GetGuestTscAux(PVMCPU pVCpu)
6227{
6228 return pVCpu->cpum.s.GuestMsrs.msr.TscAux;
6229}
6230
6231
6232/**
6233 * Fast way for HM to access the MSR_K8_TSC_AUX register.
6234 *
6235 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
6236 * @param uValue The new value.
6237 * @thread EMT(pVCpu)
6238 */
6239VMMR0_INT_DECL(void) CPUMR0SetGuestTscAux(PVMCPU pVCpu, uint64_t uValue)
6240{
6241 pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
6242}
6243
6244#endif /* IN_RING0 */
6245
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