VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp@ 99654

Last change on this file since 99654 was 98103, checked in by vboxsync, 2 years ago

Copyright year updates by scm.
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1/* $Id: CPUMAllRegs.cpp 98103 2023-01-17 14:15:46Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor(/Manager) - Getters and Setters.
4 */
5
6/*
7 * Copyright (C) 2006-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_CPUM
33#include <VBox/vmm/cpum.h>
34#include <VBox/vmm/dbgf.h>
35#include <VBox/vmm/apic.h>
36#include <VBox/vmm/pgm.h>
37#include <VBox/vmm/mm.h>
38#include <VBox/vmm/em.h>
39#include <VBox/vmm/nem.h>
40#include <VBox/vmm/hm.h>
41#include "CPUMInternal.h"
42#include <VBox/vmm/vmcc.h>
43#include <VBox/err.h>
44#include <VBox/dis.h>
45#include <VBox/log.h>
46#include <VBox/vmm/hm.h>
47#include <VBox/vmm/tm.h>
48#include <iprt/assert.h>
49#include <iprt/asm.h>
50#if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86)
51# include <iprt/asm-amd64-x86.h>
52#endif
53#ifdef IN_RING3
54# include <iprt/thread.h>
55#endif
56
57/** Disable stack frame pointer generation here. */
58#if defined(_MSC_VER) && !defined(DEBUG) && defined(RT_ARCH_X86)
59# pragma optimize("y", off)
60#endif
61
62AssertCompile2MemberOffsets(VM, cpum.s.GuestFeatures, cpum.ro.GuestFeatures);
63
64
65/*********************************************************************************************************************************
66* Defined Constants And Macros *
67*********************************************************************************************************************************/
68/**
69 * Converts a CPUMCPU::Guest pointer into a VMCPU pointer.
70 *
71 * @returns Pointer to the Virtual CPU.
72 * @param a_pGuestCtx Pointer to the guest context.
73 */
74#define CPUM_GUEST_CTX_TO_VMCPU(a_pGuestCtx) RT_FROM_MEMBER(a_pGuestCtx, VMCPU, cpum.s.Guest)
75
76/**
77 * Lazily loads the hidden parts of a selector register when using raw-mode.
78 */
79#define CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(a_pVCpu, a_pSReg) \
80 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(a_pVCpu, a_pSReg))
81
82/** @def CPUM_INT_ASSERT_NOT_EXTRN
83 * Macro for asserting that @a a_fNotExtrn are present.
84 *
85 * @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
86 * @param a_fNotExtrn Mask of CPUMCTX_EXTRN_XXX bits to check.
87 */
88#define CPUM_INT_ASSERT_NOT_EXTRN(a_pVCpu, a_fNotExtrn) \
89 AssertMsg(!((a_pVCpu)->cpum.s.Guest.fExtrn & (a_fNotExtrn)), \
90 ("%#RX64; a_fNotExtrn=%#RX64\n", (a_pVCpu)->cpum.s.Guest.fExtrn, (a_fNotExtrn)))
91
92
93VMMDECL(void) CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3)
94{
95 pVCpu->cpum.s.Hyper.cr3 = cr3;
96}
97
98VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu)
99{
100 return pVCpu->cpum.s.Hyper.cr3;
101}
102
103
104/** @def MAYBE_LOAD_DRx
105 * Macro for updating DRx values in raw-mode and ring-0 contexts.
106 */
107#ifdef IN_RING0
108# define MAYBE_LOAD_DRx(a_pVCpu, a_fnLoad, a_uValue) do { a_fnLoad(a_uValue); } while (0)
109#else
110# define MAYBE_LOAD_DRx(a_pVCpu, a_fnLoad, a_uValue) do { } while (0)
111#endif
112
113VMMDECL(void) CPUMSetHyperDR0(PVMCPU pVCpu, RTGCUINTREG uDr0)
114{
115 pVCpu->cpum.s.Hyper.dr[0] = uDr0;
116 MAYBE_LOAD_DRx(pVCpu, ASMSetDR0, uDr0);
117}
118
119
120VMMDECL(void) CPUMSetHyperDR1(PVMCPU pVCpu, RTGCUINTREG uDr1)
121{
122 pVCpu->cpum.s.Hyper.dr[1] = uDr1;
123 MAYBE_LOAD_DRx(pVCpu, ASMSetDR1, uDr1);
124}
125
126
127VMMDECL(void) CPUMSetHyperDR2(PVMCPU pVCpu, RTGCUINTREG uDr2)
128{
129 pVCpu->cpum.s.Hyper.dr[2] = uDr2;
130 MAYBE_LOAD_DRx(pVCpu, ASMSetDR2, uDr2);
131}
132
133
134VMMDECL(void) CPUMSetHyperDR3(PVMCPU pVCpu, RTGCUINTREG uDr3)
135{
136 pVCpu->cpum.s.Hyper.dr[3] = uDr3;
137 MAYBE_LOAD_DRx(pVCpu, ASMSetDR3, uDr3);
138}
139
140
141VMMDECL(void) CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6)
142{
143 pVCpu->cpum.s.Hyper.dr[6] = uDr6;
144}
145
146
147VMMDECL(void) CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7)
148{
149 pVCpu->cpum.s.Hyper.dr[7] = uDr7;
150}
151
152
153VMMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVMCPU pVCpu)
154{
155 return pVCpu->cpum.s.Hyper.dr[0];
156}
157
158
159VMMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVMCPU pVCpu)
160{
161 return pVCpu->cpum.s.Hyper.dr[1];
162}
163
164
165VMMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVMCPU pVCpu)
166{
167 return pVCpu->cpum.s.Hyper.dr[2];
168}
169
170
171VMMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVMCPU pVCpu)
172{
173 return pVCpu->cpum.s.Hyper.dr[3];
174}
175
176
177VMMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVMCPU pVCpu)
178{
179 return pVCpu->cpum.s.Hyper.dr[6];
180}
181
182
183VMMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVMCPU pVCpu)
184{
185 return pVCpu->cpum.s.Hyper.dr[7];
186}
187
188
189/**
190 * Checks that the special cookie stored in unused reserved RFLAGS bits
191 *
192 * @retval true if cookie is ok.
193 * @retval false if cookie is not ok.
194 * @param pVM The cross context VM structure.
195 * @param pVCpu The cross context virtual CPU structure.
196 */
197VMM_INT_DECL(bool) CPUMAssertGuestRFlagsCookie(PVM pVM, PVMCPU pVCpu)
198{
199 AssertLogRelMsgReturn( ( pVCpu->cpum.s.Guest.rflags.uBoth
200 & ~(uint64_t)(CPUMX86EFLAGS_HW_MASK_64 | CPUMX86EFLAGS_INT_MASK_64))
201 == pVM->cpum.s.fReservedRFlagsCookie
202 && (pVCpu->cpum.s.Guest.rflags.uBoth & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK
203 && (pVCpu->cpum.s.Guest.rflags.uBoth & X86_EFL_RAZ_MASK & CPUMX86EFLAGS_HW_MASK_64) == 0,
204 ("rflags=%#RX64 vs fReservedRFlagsCookie=%#RX64\n",
205 pVCpu->cpum.s.Guest.rflags.uBoth, pVM->cpum.s.fReservedRFlagsCookie),
206 false);
207 return true;
208}
209
210
211/**
212 * Queries the pointer to the internal CPUMCTX structure.
213 *
214 * @returns The CPUMCTX pointer.
215 * @param pVCpu The cross context virtual CPU structure.
216 */
217VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu)
218{
219 return &pVCpu->cpum.s.Guest;
220}
221
222
223/**
224 * Queries the pointer to the internal CPUMCTXMSRS structure.
225 *
226 * This is for NEM only.
227 *
228 * @returns The CPUMCTX pointer.
229 * @param pVCpu The cross context virtual CPU structure.
230 */
231VMM_INT_DECL(PCPUMCTXMSRS) CPUMQueryGuestCtxMsrsPtr(PVMCPU pVCpu)
232{
233 return &pVCpu->cpum.s.GuestMsrs;
234}
235
236
237VMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit)
238{
239 pVCpu->cpum.s.Guest.gdtr.cbGdt = cbLimit;
240 pVCpu->cpum.s.Guest.gdtr.pGdt = GCPtrBase;
241 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_GDTR;
242 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GDTR;
243 return VINF_SUCCESS; /* formality, consider it void. */
244}
245
246
247VMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit)
248{
249 pVCpu->cpum.s.Guest.idtr.cbIdt = cbLimit;
250 pVCpu->cpum.s.Guest.idtr.pIdt = GCPtrBase;
251 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_IDTR;
252 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_IDTR;
253 return VINF_SUCCESS; /* formality, consider it void. */
254}
255
256
257VMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr)
258{
259 pVCpu->cpum.s.Guest.tr.Sel = tr;
260 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_TR;
261 return VINF_SUCCESS; /* formality, consider it void. */
262}
263
264
265VMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr)
266{
267 pVCpu->cpum.s.Guest.ldtr.Sel = ldtr;
268 /* The caller will set more hidden bits if it has them. */
269 pVCpu->cpum.s.Guest.ldtr.ValidSel = 0;
270 pVCpu->cpum.s.Guest.ldtr.fFlags = 0;
271 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_LDTR;
272 return VINF_SUCCESS; /* formality, consider it void. */
273}
274
275
276/**
277 * Set the guest CR0.
278 *
279 * When called in GC, the hyper CR0 may be updated if that is
280 * required. The caller only has to take special action if AM,
281 * WP, PG or PE changes.
282 *
283 * @returns VINF_SUCCESS (consider it void).
284 * @param pVCpu The cross context virtual CPU structure.
285 * @param cr0 The new CR0 value.
286 */
287VMMDECL(int) CPUMSetGuestCR0(PVMCPUCC pVCpu, uint64_t cr0)
288{
289 /*
290 * Check for changes causing TLB flushes (for REM).
291 * The caller is responsible for calling PGM when appropriate.
292 */
293 if ( (cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE))
294 != (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)))
295 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
296 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR0;
297
298 /*
299 * Let PGM know if the WP goes from 0 to 1 (netware WP0+RO+US hack)
300 */
301 if (((cr0 ^ pVCpu->cpum.s.Guest.cr0) & X86_CR0_WP) && (cr0 & X86_CR0_WP))
302 PGMCr0WpEnabled(pVCpu);
303
304 /* The ET flag is settable on a 386 and hardwired on 486+. */
305 if ( !(cr0 & X86_CR0_ET)
306 && pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.enmMicroarch != kCpumMicroarch_Intel_80386)
307 cr0 |= X86_CR0_ET;
308
309 pVCpu->cpum.s.Guest.cr0 = cr0;
310 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_CR0;
311 return VINF_SUCCESS;
312}
313
314
315VMMDECL(int) CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2)
316{
317 pVCpu->cpum.s.Guest.cr2 = cr2;
318 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_CR2;
319 return VINF_SUCCESS;
320}
321
322
323VMMDECL(int) CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3)
324{
325 pVCpu->cpum.s.Guest.cr3 = cr3;
326 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR3;
327 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_CR3;
328 return VINF_SUCCESS;
329}
330
331
332VMMDECL(int) CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4)
333{
334 /* Note! We don't bother with OSXSAVE and legacy CPUID patches. */
335
336 if ( (cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE))
337 != (pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE)))
338 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
339
340 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR4;
341 pVCpu->cpum.s.Guest.cr4 = cr4;
342 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_CR4;
343 return VINF_SUCCESS;
344}
345
346
347VMMDECL(int) CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags)
348{
349 pVCpu->cpum.s.Guest.eflags.u = eflags;
350 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_RFLAGS;
351 return VINF_SUCCESS;
352}
353
354
355VMMDECL(int) CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip)
356{
357 pVCpu->cpum.s.Guest.eip = eip;
358 return VINF_SUCCESS;
359}
360
361
362VMMDECL(int) CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax)
363{
364 pVCpu->cpum.s.Guest.eax = eax;
365 return VINF_SUCCESS;
366}
367
368
369VMMDECL(int) CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx)
370{
371 pVCpu->cpum.s.Guest.ebx = ebx;
372 return VINF_SUCCESS;
373}
374
375
376VMMDECL(int) CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx)
377{
378 pVCpu->cpum.s.Guest.ecx = ecx;
379 return VINF_SUCCESS;
380}
381
382
383VMMDECL(int) CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx)
384{
385 pVCpu->cpum.s.Guest.edx = edx;
386 return VINF_SUCCESS;
387}
388
389
390VMMDECL(int) CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp)
391{
392 pVCpu->cpum.s.Guest.esp = esp;
393 return VINF_SUCCESS;
394}
395
396
397VMMDECL(int) CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp)
398{
399 pVCpu->cpum.s.Guest.ebp = ebp;
400 return VINF_SUCCESS;
401}
402
403
404VMMDECL(int) CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi)
405{
406 pVCpu->cpum.s.Guest.esi = esi;
407 return VINF_SUCCESS;
408}
409
410
411VMMDECL(int) CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi)
412{
413 pVCpu->cpum.s.Guest.edi = edi;
414 return VINF_SUCCESS;
415}
416
417
418VMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss)
419{
420 pVCpu->cpum.s.Guest.ss.Sel = ss;
421 return VINF_SUCCESS;
422}
423
424
425VMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs)
426{
427 pVCpu->cpum.s.Guest.cs.Sel = cs;
428 return VINF_SUCCESS;
429}
430
431
432VMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds)
433{
434 pVCpu->cpum.s.Guest.ds.Sel = ds;
435 return VINF_SUCCESS;
436}
437
438
439VMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es)
440{
441 pVCpu->cpum.s.Guest.es.Sel = es;
442 return VINF_SUCCESS;
443}
444
445
446VMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs)
447{
448 pVCpu->cpum.s.Guest.fs.Sel = fs;
449 return VINF_SUCCESS;
450}
451
452
453VMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs)
454{
455 pVCpu->cpum.s.Guest.gs.Sel = gs;
456 return VINF_SUCCESS;
457}
458
459
460VMMDECL(void) CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val)
461{
462 pVCpu->cpum.s.Guest.msrEFER = val;
463 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_EFER;
464}
465
466
467VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PCVMCPU pVCpu, uint16_t *pcbLimit)
468{
469 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_IDTR);
470 if (pcbLimit)
471 *pcbLimit = pVCpu->cpum.s.Guest.idtr.cbIdt;
472 return pVCpu->cpum.s.Guest.idtr.pIdt;
473}
474
475
476VMMDECL(RTSEL) CPUMGetGuestTR(PCVMCPU pVCpu, PCPUMSELREGHID pHidden)
477{
478 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_TR);
479 if (pHidden)
480 *pHidden = pVCpu->cpum.s.Guest.tr;
481 return pVCpu->cpum.s.Guest.tr.Sel;
482}
483
484
485VMMDECL(RTSEL) CPUMGetGuestCS(PCVMCPU pVCpu)
486{
487 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CS);
488 return pVCpu->cpum.s.Guest.cs.Sel;
489}
490
491
492VMMDECL(RTSEL) CPUMGetGuestDS(PCVMCPU pVCpu)
493{
494 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DS);
495 return pVCpu->cpum.s.Guest.ds.Sel;
496}
497
498
499VMMDECL(RTSEL) CPUMGetGuestES(PCVMCPU pVCpu)
500{
501 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_ES);
502 return pVCpu->cpum.s.Guest.es.Sel;
503}
504
505
506VMMDECL(RTSEL) CPUMGetGuestFS(PCVMCPU pVCpu)
507{
508 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_FS);
509 return pVCpu->cpum.s.Guest.fs.Sel;
510}
511
512
513VMMDECL(RTSEL) CPUMGetGuestGS(PCVMCPU pVCpu)
514{
515 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_GS);
516 return pVCpu->cpum.s.Guest.gs.Sel;
517}
518
519
520VMMDECL(RTSEL) CPUMGetGuestSS(PCVMCPU pVCpu)
521{
522 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_SS);
523 return pVCpu->cpum.s.Guest.ss.Sel;
524}
525
526
527VMMDECL(uint64_t) CPUMGetGuestFlatPC(PVMCPU pVCpu)
528{
529 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_EFER);
530 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
531 if ( !CPUMIsGuestInLongMode(pVCpu)
532 || !pVCpu->cpum.s.Guest.cs.Attr.n.u1Long)
533 return pVCpu->cpum.s.Guest.eip + (uint32_t)pVCpu->cpum.s.Guest.cs.u64Base;
534 return pVCpu->cpum.s.Guest.rip + pVCpu->cpum.s.Guest.cs.u64Base;
535}
536
537
538VMMDECL(uint64_t) CPUMGetGuestFlatSP(PVMCPU pVCpu)
539{
540 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_SS | CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_EFER);
541 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.ss);
542 if ( !CPUMIsGuestInLongMode(pVCpu)
543 || !pVCpu->cpum.s.Guest.cs.Attr.n.u1Long)
544 return pVCpu->cpum.s.Guest.eip + (uint32_t)pVCpu->cpum.s.Guest.ss.u64Base;
545 return pVCpu->cpum.s.Guest.rip + pVCpu->cpum.s.Guest.ss.u64Base;
546}
547
548
549VMMDECL(RTSEL) CPUMGetGuestLDTR(PCVMCPU pVCpu)
550{
551 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_LDTR);
552 return pVCpu->cpum.s.Guest.ldtr.Sel;
553}
554
555
556VMMDECL(RTSEL) CPUMGetGuestLdtrEx(PCVMCPU pVCpu, uint64_t *pGCPtrBase, uint32_t *pcbLimit)
557{
558 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_LDTR);
559 *pGCPtrBase = pVCpu->cpum.s.Guest.ldtr.u64Base;
560 *pcbLimit = pVCpu->cpum.s.Guest.ldtr.u32Limit;
561 return pVCpu->cpum.s.Guest.ldtr.Sel;
562}
563
564
565VMMDECL(uint64_t) CPUMGetGuestCR0(PCVMCPU pVCpu)
566{
567 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0);
568 return pVCpu->cpum.s.Guest.cr0;
569}
570
571
572VMMDECL(uint64_t) CPUMGetGuestCR2(PCVMCPU pVCpu)
573{
574 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR2);
575 return pVCpu->cpum.s.Guest.cr2;
576}
577
578
579VMMDECL(uint64_t) CPUMGetGuestCR3(PCVMCPU pVCpu)
580{
581 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR3);
582 return pVCpu->cpum.s.Guest.cr3;
583}
584
585
586VMMDECL(uint64_t) CPUMGetGuestCR4(PCVMCPU pVCpu)
587{
588 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR4);
589 return pVCpu->cpum.s.Guest.cr4;
590}
591
592
593VMMDECL(uint64_t) CPUMGetGuestCR8(PCVMCPUCC pVCpu)
594{
595 uint64_t u64;
596 int rc = CPUMGetGuestCRx(pVCpu, DISCREG_CR8, &u64);
597 if (RT_FAILURE(rc))
598 u64 = 0;
599 return u64;
600}
601
602
603VMMDECL(void) CPUMGetGuestGDTR(PCVMCPU pVCpu, PVBOXGDTR pGDTR)
604{
605 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_GDTR);
606 *pGDTR = pVCpu->cpum.s.Guest.gdtr;
607}
608
609
610VMMDECL(uint32_t) CPUMGetGuestEIP(PCVMCPU pVCpu)
611{
612 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RIP);
613 return pVCpu->cpum.s.Guest.eip;
614}
615
616
617VMMDECL(uint64_t) CPUMGetGuestRIP(PCVMCPU pVCpu)
618{
619 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RIP);
620 return pVCpu->cpum.s.Guest.rip;
621}
622
623
624VMMDECL(uint32_t) CPUMGetGuestEAX(PCVMCPU pVCpu)
625{
626 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RAX);
627 return pVCpu->cpum.s.Guest.eax;
628}
629
630
631VMMDECL(uint32_t) CPUMGetGuestEBX(PCVMCPU pVCpu)
632{
633 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RBX);
634 return pVCpu->cpum.s.Guest.ebx;
635}
636
637
638VMMDECL(uint32_t) CPUMGetGuestECX(PCVMCPU pVCpu)
639{
640 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RCX);
641 return pVCpu->cpum.s.Guest.ecx;
642}
643
644
645VMMDECL(uint32_t) CPUMGetGuestEDX(PCVMCPU pVCpu)
646{
647 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RDX);
648 return pVCpu->cpum.s.Guest.edx;
649}
650
651
652VMMDECL(uint32_t) CPUMGetGuestESI(PCVMCPU pVCpu)
653{
654 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RSI);
655 return pVCpu->cpum.s.Guest.esi;
656}
657
658
659VMMDECL(uint32_t) CPUMGetGuestEDI(PCVMCPU pVCpu)
660{
661 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RDI);
662 return pVCpu->cpum.s.Guest.edi;
663}
664
665
666VMMDECL(uint32_t) CPUMGetGuestESP(PCVMCPU pVCpu)
667{
668 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RSP);
669 return pVCpu->cpum.s.Guest.esp;
670}
671
672
673VMMDECL(uint32_t) CPUMGetGuestEBP(PCVMCPU pVCpu)
674{
675 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RBP);
676 return pVCpu->cpum.s.Guest.ebp;
677}
678
679
680VMMDECL(uint32_t) CPUMGetGuestEFlags(PCVMCPU pVCpu)
681{
682 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RFLAGS);
683 return pVCpu->cpum.s.Guest.eflags.u;
684}
685
686
687VMMDECL(int) CPUMGetGuestCRx(PCVMCPUCC pVCpu, unsigned iReg, uint64_t *pValue)
688{
689 switch (iReg)
690 {
691 case DISCREG_CR0:
692 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0);
693 *pValue = pVCpu->cpum.s.Guest.cr0;
694 break;
695
696 case DISCREG_CR2:
697 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR2);
698 *pValue = pVCpu->cpum.s.Guest.cr2;
699 break;
700
701 case DISCREG_CR3:
702 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR3);
703 *pValue = pVCpu->cpum.s.Guest.cr3;
704 break;
705
706 case DISCREG_CR4:
707 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR4);
708 *pValue = pVCpu->cpum.s.Guest.cr4;
709 break;
710
711 case DISCREG_CR8:
712 {
713 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_APIC_TPR);
714 uint8_t u8Tpr;
715 int rc = APICGetTpr(pVCpu, &u8Tpr, NULL /* pfPending */, NULL /* pu8PendingIrq */);
716 if (RT_FAILURE(rc))
717 {
718 AssertMsg(rc == VERR_PDM_NO_APIC_INSTANCE, ("%Rrc\n", rc));
719 *pValue = 0;
720 return rc;
721 }
722 *pValue = u8Tpr >> 4; /* bits 7-4 contain the task priority that go in cr8, bits 3-0 */
723 break;
724 }
725
726 default:
727 return VERR_INVALID_PARAMETER;
728 }
729 return VINF_SUCCESS;
730}
731
732
733VMMDECL(uint64_t) CPUMGetGuestDR0(PCVMCPU pVCpu)
734{
735 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
736 return pVCpu->cpum.s.Guest.dr[0];
737}
738
739
740VMMDECL(uint64_t) CPUMGetGuestDR1(PCVMCPU pVCpu)
741{
742 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
743 return pVCpu->cpum.s.Guest.dr[1];
744}
745
746
747VMMDECL(uint64_t) CPUMGetGuestDR2(PCVMCPU pVCpu)
748{
749 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
750 return pVCpu->cpum.s.Guest.dr[2];
751}
752
753
754VMMDECL(uint64_t) CPUMGetGuestDR3(PCVMCPU pVCpu)
755{
756 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
757 return pVCpu->cpum.s.Guest.dr[3];
758}
759
760
761VMMDECL(uint64_t) CPUMGetGuestDR6(PCVMCPU pVCpu)
762{
763 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DR6);
764 return pVCpu->cpum.s.Guest.dr[6];
765}
766
767
768VMMDECL(uint64_t) CPUMGetGuestDR7(PCVMCPU pVCpu)
769{
770 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DR7);
771 return pVCpu->cpum.s.Guest.dr[7];
772}
773
774
775VMMDECL(int) CPUMGetGuestDRx(PCVMCPU pVCpu, uint32_t iReg, uint64_t *pValue)
776{
777 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DR_MASK);
778 AssertReturn(iReg <= DISDREG_DR7, VERR_INVALID_PARAMETER);
779 /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
780 if (iReg == 4 || iReg == 5)
781 iReg += 2;
782 *pValue = pVCpu->cpum.s.Guest.dr[iReg];
783 return VINF_SUCCESS;
784}
785
786
787VMMDECL(uint64_t) CPUMGetGuestEFER(PCVMCPU pVCpu)
788{
789 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_EFER);
790 return pVCpu->cpum.s.Guest.msrEFER;
791}
792
793
794/**
795 * Looks up a CPUID leaf in the CPUID leaf array, no subleaf.
796 *
797 * @returns Pointer to the leaf if found, NULL if not.
798 *
799 * @param pVM The cross context VM structure.
800 * @param uLeaf The leaf to get.
801 */
802PCPUMCPUIDLEAF cpumCpuIdGetLeaf(PVM pVM, uint32_t uLeaf)
803{
804 unsigned iEnd = RT_MIN(pVM->cpum.s.GuestInfo.cCpuIdLeaves, RT_ELEMENTS(pVM->cpum.s.GuestInfo.aCpuIdLeaves));
805 if (iEnd)
806 {
807 unsigned iStart = 0;
808 PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.aCpuIdLeaves;
809 for (;;)
810 {
811 unsigned i = iStart + (iEnd - iStart) / 2U;
812 if (uLeaf < paLeaves[i].uLeaf)
813 {
814 if (i <= iStart)
815 return NULL;
816 iEnd = i;
817 }
818 else if (uLeaf > paLeaves[i].uLeaf)
819 {
820 i += 1;
821 if (i >= iEnd)
822 return NULL;
823 iStart = i;
824 }
825 else
826 {
827 if (RT_LIKELY(paLeaves[i].fSubLeafMask == 0 && paLeaves[i].uSubLeaf == 0))
828 return &paLeaves[i];
829
830 /* This shouldn't normally happen. But in case the it does due
831 to user configuration overrids or something, just return the
832 first sub-leaf. */
833 AssertMsgFailed(("uLeaf=%#x fSubLeafMask=%#x uSubLeaf=%#x\n",
834 uLeaf, paLeaves[i].fSubLeafMask, paLeaves[i].uSubLeaf));
835 while ( paLeaves[i].uSubLeaf != 0
836 && i > 0
837 && uLeaf == paLeaves[i - 1].uLeaf)
838 i--;
839 return &paLeaves[i];
840 }
841 }
842 }
843
844 return NULL;
845}
846
847
848/**
849 * Looks up a CPUID leaf in the CPUID leaf array.
850 *
851 * @returns Pointer to the leaf if found, NULL if not.
852 *
853 * @param pVM The cross context VM structure.
854 * @param uLeaf The leaf to get.
855 * @param uSubLeaf The subleaf, if applicable. Just pass 0 if it
856 * isn't.
857 * @param pfExactSubLeafHit Whether we've got an exact subleaf hit or not.
858 */
859PCPUMCPUIDLEAF cpumCpuIdGetLeafEx(PVM pVM, uint32_t uLeaf, uint32_t uSubLeaf, bool *pfExactSubLeafHit)
860{
861 unsigned iEnd = RT_MIN(pVM->cpum.s.GuestInfo.cCpuIdLeaves, RT_ELEMENTS(pVM->cpum.s.GuestInfo.aCpuIdLeaves));
862 if (iEnd)
863 {
864 unsigned iStart = 0;
865 PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.aCpuIdLeaves;
866 for (;;)
867 {
868 unsigned i = iStart + (iEnd - iStart) / 2U;
869 if (uLeaf < paLeaves[i].uLeaf)
870 {
871 if (i <= iStart)
872 return NULL;
873 iEnd = i;
874 }
875 else if (uLeaf > paLeaves[i].uLeaf)
876 {
877 i += 1;
878 if (i >= iEnd)
879 return NULL;
880 iStart = i;
881 }
882 else
883 {
884 uSubLeaf &= paLeaves[i].fSubLeafMask;
885 if (uSubLeaf == paLeaves[i].uSubLeaf)
886 *pfExactSubLeafHit = true;
887 else
888 {
889 /* Find the right subleaf. We return the last one before
890 uSubLeaf if we don't find an exact match. */
891 if (uSubLeaf < paLeaves[i].uSubLeaf)
892 while ( i > 0
893 && uLeaf == paLeaves[i - 1].uLeaf
894 && uSubLeaf <= paLeaves[i - 1].uSubLeaf)
895 i--;
896 else
897 while ( i + 1 < pVM->cpum.s.GuestInfo.cCpuIdLeaves
898 && uLeaf == paLeaves[i + 1].uLeaf
899 && uSubLeaf >= paLeaves[i + 1].uSubLeaf)
900 i++;
901 *pfExactSubLeafHit = uSubLeaf == paLeaves[i].uSubLeaf;
902 }
903 return &paLeaves[i];
904 }
905 }
906 }
907
908 *pfExactSubLeafHit = false;
909 return NULL;
910}
911
912
913/**
914 * Gets a CPUID leaf.
915 *
916 * @param pVCpu The cross context virtual CPU structure.
917 * @param uLeaf The CPUID leaf to get.
918 * @param uSubLeaf The CPUID sub-leaf to get, if applicable.
919 * @param f64BitMode A tristate indicate if the caller is in 64-bit mode or
920 * not: 1=true, 0=false, 1=whatever. This affect how the
921 * X86_CPUID_EXT_FEATURE_EDX_SYSCALL flag is returned on
922 * Intel CPUs, where it's only returned in 64-bit mode.
923 * @param pEax Where to store the EAX value.
924 * @param pEbx Where to store the EBX value.
925 * @param pEcx Where to store the ECX value.
926 * @param pEdx Where to store the EDX value.
927 */
928VMMDECL(void) CPUMGetGuestCpuId(PVMCPUCC pVCpu, uint32_t uLeaf, uint32_t uSubLeaf, int f64BitMode,
929 uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx)
930{
931 bool fExactSubLeafHit;
932 PVM pVM = pVCpu->CTX_SUFF(pVM);
933 PCCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafEx(pVM, uLeaf, uSubLeaf, &fExactSubLeafHit);
934 if (pLeaf)
935 {
936 AssertMsg(pLeaf->uLeaf == uLeaf, ("%#x %#x\n", pLeaf->uLeaf, uLeaf));
937 if (fExactSubLeafHit)
938 {
939 *pEax = pLeaf->uEax;
940 *pEbx = pLeaf->uEbx;
941 *pEcx = pLeaf->uEcx;
942 *pEdx = pLeaf->uEdx;
943
944 /*
945 * Deal with CPU specific information.
946 */
947 if (pLeaf->fFlags & ( CPUMCPUIDLEAF_F_CONTAINS_APIC_ID
948 | CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE
949 | CPUMCPUIDLEAF_F_CONTAINS_APIC ))
950 {
951 if (uLeaf == 1)
952 {
953 /* EBX: Bits 31-24: Initial APIC ID. */
954 Assert(pVCpu->idCpu <= 255);
955 AssertMsg((pLeaf->uEbx >> 24) == 0, ("%#x\n", pLeaf->uEbx)); /* raw-mode assumption */
956 *pEbx = (pLeaf->uEbx & UINT32_C(0x00ffffff)) | (pVCpu->idCpu << 24);
957
958 /* EDX: Bit 9: AND with APICBASE.EN. */
959 if (!pVCpu->cpum.s.fCpuIdApicFeatureVisible && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
960 *pEdx &= ~X86_CPUID_FEATURE_EDX_APIC;
961
962 /* ECX: Bit 27: CR4.OSXSAVE mirror. */
963 *pEcx = (pLeaf->uEcx & ~X86_CPUID_FEATURE_ECX_OSXSAVE)
964 | (pVCpu->cpum.s.Guest.cr4 & X86_CR4_OSXSAVE ? X86_CPUID_FEATURE_ECX_OSXSAVE : 0);
965 }
966 else if (uLeaf == 0xb)
967 {
968 /* EDX: Initial extended APIC ID. */
969 AssertMsg(pLeaf->uEdx == 0, ("%#x\n", pLeaf->uEdx)); /* raw-mode assumption */
970 *pEdx = pVCpu->idCpu;
971 Assert(!(pLeaf->fFlags & ~(CPUMCPUIDLEAF_F_CONTAINS_APIC_ID | CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES)));
972 }
973 else if (uLeaf == UINT32_C(0x8000001e))
974 {
975 /* EAX: Initial extended APIC ID. */
976 AssertMsg(pLeaf->uEax == 0, ("%#x\n", pLeaf->uEax)); /* raw-mode assumption */
977 *pEax = pVCpu->idCpu;
978 Assert(!(pLeaf->fFlags & ~CPUMCPUIDLEAF_F_CONTAINS_APIC_ID));
979 }
980 else if (uLeaf == UINT32_C(0x80000001))
981 {
982 /* EDX: Bit 9: AND with APICBASE.EN. */
983 if (!pVCpu->cpum.s.fCpuIdApicFeatureVisible)
984 *pEdx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
985 Assert(!(pLeaf->fFlags & ~CPUMCPUIDLEAF_F_CONTAINS_APIC));
986 }
987 else
988 AssertMsgFailed(("uLeaf=%#x\n", uLeaf));
989 }
990
991 /* Intel CPUs supresses the SYSCALL bit when not executing in 64-bit mode: */
992 if ( uLeaf == UINT32_C(0x80000001)
993 && f64BitMode == false
994 && (*pEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
995 && ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL
996 || pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_VIA /*?*/
997 || pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_SHANGHAI /*?*/ ) )
998 *pEdx &= ~X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
999
1000 }
1001 /*
1002 * Out of range sub-leaves aren't quite as easy and pretty as we emulate
1003 * them here, but we do the best we can here...
1004 */
1005 else
1006 {
1007 *pEax = *pEbx = *pEcx = *pEdx = 0;
1008 if (pLeaf->fFlags & CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES)
1009 {
1010 *pEcx = uSubLeaf & 0xff;
1011 *pEdx = pVCpu->idCpu;
1012 }
1013 }
1014 }
1015 else
1016 {
1017 /*
1018 * Different CPUs have different ways of dealing with unknown CPUID leaves.
1019 */
1020 switch (pVM->cpum.s.GuestInfo.enmUnknownCpuIdMethod)
1021 {
1022 default:
1023 AssertFailed();
1024 RT_FALL_THRU();
1025 case CPUMUNKNOWNCPUID_DEFAULTS:
1026 case CPUMUNKNOWNCPUID_LAST_STD_LEAF: /* ASSUME this is executed */
1027 case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: /** @todo Implement CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX */
1028 *pEax = pVM->cpum.s.GuestInfo.DefCpuId.uEax;
1029 *pEbx = pVM->cpum.s.GuestInfo.DefCpuId.uEbx;
1030 *pEcx = pVM->cpum.s.GuestInfo.DefCpuId.uEcx;
1031 *pEdx = pVM->cpum.s.GuestInfo.DefCpuId.uEdx;
1032 break;
1033 case CPUMUNKNOWNCPUID_PASSTHRU:
1034 *pEax = uLeaf;
1035 *pEbx = 0;
1036 *pEcx = uSubLeaf;
1037 *pEdx = 0;
1038 break;
1039 }
1040 }
1041 Log2(("CPUMGetGuestCpuId: uLeaf=%#010x/%#010x %RX32 %RX32 %RX32 %RX32\n", uLeaf, uSubLeaf, *pEax, *pEbx, *pEcx, *pEdx));
1042}
1043
1044
1045/**
1046 * Sets the visibility of the X86_CPUID_FEATURE_EDX_APIC and
1047 * X86_CPUID_AMD_FEATURE_EDX_APIC CPUID bits.
1048 *
1049 * @returns Previous value.
1050 * @param pVCpu The cross context virtual CPU structure to make the
1051 * change on. Usually the calling EMT.
1052 * @param fVisible Whether to make it visible (true) or hide it (false).
1053 *
1054 * @remarks This is "VMMDECL" so that it still links with
1055 * the old APIC code which is in VBoxDD2 and not in
1056 * the VMM module.
1057 */
1058VMMDECL(bool) CPUMSetGuestCpuIdPerCpuApicFeature(PVMCPU pVCpu, bool fVisible)
1059{
1060 bool fOld = pVCpu->cpum.s.fCpuIdApicFeatureVisible;
1061 pVCpu->cpum.s.fCpuIdApicFeatureVisible = fVisible;
1062 return fOld;
1063}
1064
1065
1066/**
1067 * Gets the host CPU vendor.
1068 *
1069 * @returns CPU vendor.
1070 * @param pVM The cross context VM structure.
1071 */
1072VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM)
1073{
1074 return (CPUMCPUVENDOR)pVM->cpum.s.HostFeatures.enmCpuVendor;
1075}
1076
1077
1078/**
1079 * Gets the host CPU microarchitecture.
1080 *
1081 * @returns CPU microarchitecture.
1082 * @param pVM The cross context VM structure.
1083 */
1084VMMDECL(CPUMMICROARCH) CPUMGetHostMicroarch(PCVM pVM)
1085{
1086 return pVM->cpum.s.HostFeatures.enmMicroarch;
1087}
1088
1089
1090/**
1091 * Gets the guest CPU vendor.
1092 *
1093 * @returns CPU vendor.
1094 * @param pVM The cross context VM structure.
1095 */
1096VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM)
1097{
1098 return (CPUMCPUVENDOR)pVM->cpum.s.GuestFeatures.enmCpuVendor;
1099}
1100
1101
1102/**
1103 * Gets the guest CPU microarchitecture.
1104 *
1105 * @returns CPU microarchitecture.
1106 * @param pVM The cross context VM structure.
1107 */
1108VMMDECL(CPUMMICROARCH) CPUMGetGuestMicroarch(PCVM pVM)
1109{
1110 return pVM->cpum.s.GuestFeatures.enmMicroarch;
1111}
1112
1113
1114/**
1115 * Gets the maximum number of physical and linear address bits supported by the
1116 * guest.
1117 *
1118 * @param pVM The cross context VM structure.
1119 * @param pcPhysAddrWidth Where to store the physical address width.
1120 * @param pcLinearAddrWidth Where to store the linear address width.
1121 */
1122VMMDECL(void) CPUMGetGuestAddrWidths(PCVM pVM, uint8_t *pcPhysAddrWidth, uint8_t *pcLinearAddrWidth)
1123{
1124 AssertPtr(pVM);
1125 AssertReturnVoid(pcPhysAddrWidth);
1126 AssertReturnVoid(pcLinearAddrWidth);
1127 *pcPhysAddrWidth = pVM->cpum.s.GuestFeatures.cMaxPhysAddrWidth;
1128 *pcLinearAddrWidth = pVM->cpum.s.GuestFeatures.cMaxLinearAddrWidth;
1129}
1130
1131
1132VMMDECL(int) CPUMSetGuestDR0(PVMCPUCC pVCpu, uint64_t uDr0)
1133{
1134 pVCpu->cpum.s.Guest.dr[0] = uDr0;
1135 return CPUMRecalcHyperDRx(pVCpu, 0);
1136}
1137
1138
1139VMMDECL(int) CPUMSetGuestDR1(PVMCPUCC pVCpu, uint64_t uDr1)
1140{
1141 pVCpu->cpum.s.Guest.dr[1] = uDr1;
1142 return CPUMRecalcHyperDRx(pVCpu, 1);
1143}
1144
1145
1146VMMDECL(int) CPUMSetGuestDR2(PVMCPUCC pVCpu, uint64_t uDr2)
1147{
1148 pVCpu->cpum.s.Guest.dr[2] = uDr2;
1149 return CPUMRecalcHyperDRx(pVCpu, 2);
1150}
1151
1152
1153VMMDECL(int) CPUMSetGuestDR3(PVMCPUCC pVCpu, uint64_t uDr3)
1154{
1155 pVCpu->cpum.s.Guest.dr[3] = uDr3;
1156 return CPUMRecalcHyperDRx(pVCpu, 3);
1157}
1158
1159
1160VMMDECL(int) CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6)
1161{
1162 pVCpu->cpum.s.Guest.dr[6] = uDr6;
1163 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_DR6;
1164 return VINF_SUCCESS; /* No need to recalc. */
1165}
1166
1167
1168VMMDECL(int) CPUMSetGuestDR7(PVMCPUCC pVCpu, uint64_t uDr7)
1169{
1170 pVCpu->cpum.s.Guest.dr[7] = uDr7;
1171 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_DR7;
1172 return CPUMRecalcHyperDRx(pVCpu, 7);
1173}
1174
1175
1176VMMDECL(int) CPUMSetGuestDRx(PVMCPUCC pVCpu, uint32_t iReg, uint64_t Value)
1177{
1178 AssertReturn(iReg <= DISDREG_DR7, VERR_INVALID_PARAMETER);
1179 /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
1180 if (iReg == 4 || iReg == 5)
1181 iReg += 2;
1182 pVCpu->cpum.s.Guest.dr[iReg] = Value;
1183 return CPUMRecalcHyperDRx(pVCpu, iReg);
1184}
1185
1186
1187/**
1188 * Recalculates the hypervisor DRx register values based on current guest
1189 * registers and DBGF breakpoints, updating changed registers depending on the
1190 * context.
1191 *
1192 * This is called whenever a guest DRx register is modified (any context) and
1193 * when DBGF sets a hardware breakpoint (ring-3 only, rendezvous).
1194 *
1195 * In raw-mode context this function will reload any (hyper) DRx registers which
1196 * comes out with a different value. It may also have to save the host debug
1197 * registers if that haven't been done already. In this context though, we'll
1198 * be intercepting and emulating all DRx accesses, so the hypervisor DRx values
1199 * are only important when breakpoints are actually enabled.
1200 *
1201 * In ring-0 (HM) context DR0-3 will be relocated by us, while DR7 will be
1202 * reloaded by the HM code if it changes. Further more, we will only use the
1203 * combined register set when the VBox debugger is actually using hardware BPs,
1204 * when it isn't we'll keep the guest DR0-3 + (maybe) DR6 loaded (DR6 doesn't
1205 * concern us here).
1206 *
1207 * In ring-3 we won't be loading anything, so well calculate hypervisor values
1208 * all the time.
1209 *
1210 * @returns VINF_SUCCESS.
1211 * @param pVCpu The cross context virtual CPU structure.
1212 * @param iGstReg The guest debug register number that was modified.
1213 * UINT8_MAX if not guest register.
1214 */
1215VMMDECL(int) CPUMRecalcHyperDRx(PVMCPUCC pVCpu, uint8_t iGstReg)
1216{
1217 PVM pVM = pVCpu->CTX_SUFF(pVM);
1218#ifndef IN_RING0
1219 RT_NOREF_PV(iGstReg);
1220#endif
1221
1222 /*
1223 * Compare the DR7s first.
1224 *
1225 * We only care about the enabled flags. GD is virtualized when we
1226 * dispatch the #DB, we never enable it. The DBGF DR7 value is will
1227 * always have the LE and GE bits set, so no need to check and disable
1228 * stuff if they're cleared like we have to for the guest DR7.
1229 */
1230 RTGCUINTREG uGstDr7 = CPUMGetGuestDR7(pVCpu);
1231 /** @todo This isn't correct. BPs work without setting LE and GE under AMD-V. They are also documented as unsupported by P6+. */
1232 if (!(uGstDr7 & (X86_DR7_LE | X86_DR7_GE)))
1233 uGstDr7 = 0;
1234 else if (!(uGstDr7 & X86_DR7_LE))
1235 uGstDr7 &= ~X86_DR7_LE_ALL;
1236 else if (!(uGstDr7 & X86_DR7_GE))
1237 uGstDr7 &= ~X86_DR7_GE_ALL;
1238
1239 const RTGCUINTREG uDbgfDr7 = DBGFBpGetDR7(pVM);
1240 if ((uGstDr7 | uDbgfDr7) & X86_DR7_ENABLED_MASK)
1241 {
1242 Assert(!CPUMIsGuestDebugStateActive(pVCpu));
1243
1244 /*
1245 * Ok, something is enabled. Recalc each of the breakpoints, taking
1246 * the VM debugger ones of the guest ones. In raw-mode context we will
1247 * not allow breakpoints with values inside the hypervisor area.
1248 */
1249 RTGCUINTREG uNewDr7 = X86_DR7_GE | X86_DR7_LE | X86_DR7_RA1_MASK;
1250
1251 /* bp 0 */
1252 RTGCUINTREG uNewDr0;
1253 if (uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0))
1254 {
1255 uNewDr7 |= uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
1256 uNewDr0 = DBGFBpGetDR0(pVM);
1257 }
1258 else if (uGstDr7 & (X86_DR7_L0 | X86_DR7_G0))
1259 {
1260 uNewDr0 = CPUMGetGuestDR0(pVCpu);
1261 uNewDr7 |= uGstDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
1262 }
1263 else
1264 uNewDr0 = 0;
1265
1266 /* bp 1 */
1267 RTGCUINTREG uNewDr1;
1268 if (uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1))
1269 {
1270 uNewDr7 |= uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
1271 uNewDr1 = DBGFBpGetDR1(pVM);
1272 }
1273 else if (uGstDr7 & (X86_DR7_L1 | X86_DR7_G1))
1274 {
1275 uNewDr1 = CPUMGetGuestDR1(pVCpu);
1276 uNewDr7 |= uGstDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
1277 }
1278 else
1279 uNewDr1 = 0;
1280
1281 /* bp 2 */
1282 RTGCUINTREG uNewDr2;
1283 if (uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2))
1284 {
1285 uNewDr7 |= uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
1286 uNewDr2 = DBGFBpGetDR2(pVM);
1287 }
1288 else if (uGstDr7 & (X86_DR7_L2 | X86_DR7_G2))
1289 {
1290 uNewDr2 = CPUMGetGuestDR2(pVCpu);
1291 uNewDr7 |= uGstDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
1292 }
1293 else
1294 uNewDr2 = 0;
1295
1296 /* bp 3 */
1297 RTGCUINTREG uNewDr3;
1298 if (uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3))
1299 {
1300 uNewDr7 |= uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
1301 uNewDr3 = DBGFBpGetDR3(pVM);
1302 }
1303 else if (uGstDr7 & (X86_DR7_L3 | X86_DR7_G3))
1304 {
1305 uNewDr3 = CPUMGetGuestDR3(pVCpu);
1306 uNewDr7 |= uGstDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
1307 }
1308 else
1309 uNewDr3 = 0;
1310
1311 /*
1312 * Apply the updates.
1313 */
1314 pVCpu->cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS_HYPER;
1315 if (uNewDr3 != pVCpu->cpum.s.Hyper.dr[3])
1316 CPUMSetHyperDR3(pVCpu, uNewDr3);
1317 if (uNewDr2 != pVCpu->cpum.s.Hyper.dr[2])
1318 CPUMSetHyperDR2(pVCpu, uNewDr2);
1319 if (uNewDr1 != pVCpu->cpum.s.Hyper.dr[1])
1320 CPUMSetHyperDR1(pVCpu, uNewDr1);
1321 if (uNewDr0 != pVCpu->cpum.s.Hyper.dr[0])
1322 CPUMSetHyperDR0(pVCpu, uNewDr0);
1323 if (uNewDr7 != pVCpu->cpum.s.Hyper.dr[7])
1324 CPUMSetHyperDR7(pVCpu, uNewDr7);
1325 }
1326#ifdef IN_RING0
1327 else if (CPUMIsGuestDebugStateActive(pVCpu))
1328 {
1329 /*
1330 * Reload the register that was modified. Normally this won't happen
1331 * as we won't intercept DRx writes when not having the hyper debug
1332 * state loaded, but in case we do for some reason we'll simply deal
1333 * with it.
1334 */
1335 switch (iGstReg)
1336 {
1337 case 0: ASMSetDR0(CPUMGetGuestDR0(pVCpu)); break;
1338 case 1: ASMSetDR1(CPUMGetGuestDR1(pVCpu)); break;
1339 case 2: ASMSetDR2(CPUMGetGuestDR2(pVCpu)); break;
1340 case 3: ASMSetDR3(CPUMGetGuestDR3(pVCpu)); break;
1341 default:
1342 AssertReturn(iGstReg != UINT8_MAX, VERR_INTERNAL_ERROR_3);
1343 }
1344 }
1345#endif
1346 else
1347 {
1348 /*
1349 * No active debug state any more. In raw-mode this means we have to
1350 * make sure DR7 has everything disabled now, if we armed it already.
1351 * In ring-0 we might end up here when just single stepping.
1352 */
1353#ifdef IN_RING0
1354 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HYPER)
1355 {
1356 if (pVCpu->cpum.s.Hyper.dr[0])
1357 ASMSetDR0(0);
1358 if (pVCpu->cpum.s.Hyper.dr[1])
1359 ASMSetDR1(0);
1360 if (pVCpu->cpum.s.Hyper.dr[2])
1361 ASMSetDR2(0);
1362 if (pVCpu->cpum.s.Hyper.dr[3])
1363 ASMSetDR3(0);
1364 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_DEBUG_REGS_HYPER;
1365 }
1366#endif
1367 pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS_HYPER;
1368
1369 /* Clear all the registers. */
1370 pVCpu->cpum.s.Hyper.dr[7] = X86_DR7_RA1_MASK;
1371 pVCpu->cpum.s.Hyper.dr[3] = 0;
1372 pVCpu->cpum.s.Hyper.dr[2] = 0;
1373 pVCpu->cpum.s.Hyper.dr[1] = 0;
1374 pVCpu->cpum.s.Hyper.dr[0] = 0;
1375
1376 }
1377 Log2(("CPUMRecalcHyperDRx: fUseFlags=%#x %RGr %RGr %RGr %RGr %RGr %RGr\n",
1378 pVCpu->cpum.s.fUseFlags, pVCpu->cpum.s.Hyper.dr[0], pVCpu->cpum.s.Hyper.dr[1],
1379 pVCpu->cpum.s.Hyper.dr[2], pVCpu->cpum.s.Hyper.dr[3], pVCpu->cpum.s.Hyper.dr[6],
1380 pVCpu->cpum.s.Hyper.dr[7]));
1381
1382 return VINF_SUCCESS;
1383}
1384
1385
1386/**
1387 * Set the guest XCR0 register.
1388 *
1389 * Will load additional state if the FPU state is already loaded (in ring-0 &
1390 * raw-mode context).
1391 *
1392 * @returns VINF_SUCCESS on success, VERR_CPUM_RAISE_GP_0 on invalid input
1393 * value.
1394 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1395 * @param uNewValue The new value.
1396 * @thread EMT(pVCpu)
1397 */
1398VMM_INT_DECL(int) CPUMSetGuestXcr0(PVMCPUCC pVCpu, uint64_t uNewValue)
1399{
1400 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_XCRx);
1401 if ( (uNewValue & ~pVCpu->CTX_SUFF(pVM)->cpum.s.fXStateGuestMask) == 0
1402 /* The X87 bit cannot be cleared. */
1403 && (uNewValue & XSAVE_C_X87)
1404 /* AVX requires SSE. */
1405 && (uNewValue & (XSAVE_C_SSE | XSAVE_C_YMM)) != XSAVE_C_YMM
1406 /* AVX-512 requires YMM, SSE and all of its three components to be enabled. */
1407 && ( (uNewValue & (XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI)) == 0
1408 || (uNewValue & (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI))
1409 == (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI) )
1410 )
1411 {
1412 pVCpu->cpum.s.Guest.aXcr[0] = uNewValue;
1413
1414 /* If more state components are enabled, we need to take care to load
1415 them if the FPU/SSE state is already loaded. May otherwise leak
1416 host state to the guest. */
1417 uint64_t fNewComponents = ~pVCpu->cpum.s.Guest.fXStateMask & uNewValue;
1418 if (fNewComponents)
1419 {
1420#ifdef IN_RING0
1421 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST)
1422 {
1423 if (pVCpu->cpum.s.Guest.fXStateMask != 0)
1424 /* Adding more components. */
1425 ASMXRstor(&pVCpu->cpum.s.Guest.XState, fNewComponents);
1426 else
1427 {
1428 /* We're switching from FXSAVE/FXRSTOR to XSAVE/XRSTOR. */
1429 pVCpu->cpum.s.Guest.fXStateMask |= XSAVE_C_X87 | XSAVE_C_SSE;
1430 if (uNewValue & ~(XSAVE_C_X87 | XSAVE_C_SSE))
1431 ASMXRstor(&pVCpu->cpum.s.Guest.XState, uNewValue & ~(XSAVE_C_X87 | XSAVE_C_SSE));
1432 }
1433 }
1434#endif
1435 pVCpu->cpum.s.Guest.fXStateMask |= uNewValue;
1436 }
1437 return VINF_SUCCESS;
1438 }
1439 return VERR_CPUM_RAISE_GP_0;
1440}
1441
1442
1443/**
1444 * Tests if the guest has No-Execute Page Protection Enabled (NXE).
1445 *
1446 * @returns true if in real mode, otherwise false.
1447 * @param pVCpu The cross context virtual CPU structure.
1448 */
1449VMMDECL(bool) CPUMIsGuestNXEnabled(PCVMCPU pVCpu)
1450{
1451 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_EFER);
1452 return !!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE);
1453}
1454
1455
1456/**
1457 * Tests if the guest has the Page Size Extension enabled (PSE).
1458 *
1459 * @returns true if in real mode, otherwise false.
1460 * @param pVCpu The cross context virtual CPU structure.
1461 */
1462VMMDECL(bool) CPUMIsGuestPageSizeExtEnabled(PCVMCPU pVCpu)
1463{
1464 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR4);
1465 /* PAE or AMD64 implies support for big pages regardless of CR4.PSE */
1466 return !!(pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PSE | X86_CR4_PAE));
1467}
1468
1469
1470/**
1471 * Tests if the guest has the paging enabled (PG).
1472 *
1473 * @returns true if in real mode, otherwise false.
1474 * @param pVCpu The cross context virtual CPU structure.
1475 */
1476VMMDECL(bool) CPUMIsGuestPagingEnabled(PCVMCPU pVCpu)
1477{
1478 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0);
1479 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG);
1480}
1481
1482
1483/**
1484 * Tests if the guest has the paging enabled (PG).
1485 *
1486 * @returns true if in real mode, otherwise false.
1487 * @param pVCpu The cross context virtual CPU structure.
1488 */
1489VMMDECL(bool) CPUMIsGuestR0WriteProtEnabled(PCVMCPU pVCpu)
1490{
1491 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0);
1492 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_WP);
1493}
1494
1495
1496/**
1497 * Tests if the guest is running in real mode or not.
1498 *
1499 * @returns true if in real mode, otherwise false.
1500 * @param pVCpu The cross context virtual CPU structure.
1501 */
1502VMMDECL(bool) CPUMIsGuestInRealMode(PCVMCPU pVCpu)
1503{
1504 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0);
1505 return !(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
1506}
1507
1508
1509/**
1510 * Tests if the guest is running in real or virtual 8086 mode.
1511 *
1512 * @returns @c true if it is, @c false if not.
1513 * @param pVCpu The cross context virtual CPU structure.
1514 */
1515VMMDECL(bool) CPUMIsGuestInRealOrV86Mode(PCVMCPU pVCpu)
1516{
1517 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_RFLAGS);
1518 return !(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE)
1519 || pVCpu->cpum.s.Guest.eflags.Bits.u1VM; /** @todo verify that this cannot be set in long mode. */
1520}
1521
1522
1523/**
1524 * Tests if the guest is running in protected or not.
1525 *
1526 * @returns true if in protected mode, otherwise false.
1527 * @param pVCpu The cross context virtual CPU structure.
1528 */
1529VMMDECL(bool) CPUMIsGuestInProtectedMode(PCVMCPU pVCpu)
1530{
1531 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0);
1532 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
1533}
1534
1535
1536/**
1537 * Tests if the guest is running in paged protected or not.
1538 *
1539 * @returns true if in paged protected mode, otherwise false.
1540 * @param pVCpu The cross context virtual CPU structure.
1541 */
1542VMMDECL(bool) CPUMIsGuestInPagedProtectedMode(PCVMCPU pVCpu)
1543{
1544 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0);
1545 return (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
1546}
1547
1548
1549/**
1550 * Tests if the guest is running in long mode or not.
1551 *
1552 * @returns true if in long mode, otherwise false.
1553 * @param pVCpu The cross context virtual CPU structure.
1554 */
1555VMMDECL(bool) CPUMIsGuestInLongMode(PCVMCPU pVCpu)
1556{
1557 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_EFER);
1558 return (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
1559}
1560
1561
1562/**
1563 * Tests if the guest is running in PAE mode or not.
1564 *
1565 * @returns true if in PAE mode, otherwise false.
1566 * @param pVCpu The cross context virtual CPU structure.
1567 */
1568VMMDECL(bool) CPUMIsGuestInPAEMode(PCVMCPU pVCpu)
1569{
1570 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR4 | CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_EFER);
1571 /* Intel mentions EFER.LMA and EFER.LME in different parts of their spec. We shall use EFER.LMA rather
1572 than EFER.LME as it reflects if the CPU has entered paging with EFER.LME set. */
1573 return (pVCpu->cpum.s.Guest.cr4 & X86_CR4_PAE)
1574 && (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG)
1575 && !(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA);
1576}
1577
1578
1579/**
1580 * Tests if the guest is running in 64 bits mode or not.
1581 *
1582 * @returns true if in 64 bits protected mode, otherwise false.
1583 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1584 */
1585VMMDECL(bool) CPUMIsGuestIn64BitCode(PVMCPU pVCpu)
1586{
1587 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_EFER);
1588 if (!CPUMIsGuestInLongMode(pVCpu))
1589 return false;
1590 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
1591 return pVCpu->cpum.s.Guest.cs.Attr.n.u1Long;
1592}
1593
1594
1595/**
1596 * Helper for CPUMIsGuestIn64BitCodeEx that handles lazy resolving of hidden CS
1597 * registers.
1598 *
1599 * @returns true if in 64 bits protected mode, otherwise false.
1600 * @param pCtx Pointer to the current guest CPU context.
1601 */
1602VMM_INT_DECL(bool) CPUMIsGuestIn64BitCodeSlow(PCPUMCTX pCtx)
1603{
1604 return CPUMIsGuestIn64BitCode(CPUM_GUEST_CTX_TO_VMCPU(pCtx));
1605}
1606
1607
1608/**
1609 * Sets the specified changed flags (CPUM_CHANGED_*).
1610 *
1611 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1612 * @param fChangedAdd The changed flags to add.
1613 */
1614VMMDECL(void) CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedAdd)
1615{
1616 pVCpu->cpum.s.fChanged |= fChangedAdd;
1617}
1618
1619
1620/**
1621 * Checks if the CPU supports the XSAVE and XRSTOR instruction.
1622 *
1623 * @returns true if supported.
1624 * @returns false if not supported.
1625 * @param pVM The cross context VM structure.
1626 */
1627VMMDECL(bool) CPUMSupportsXSave(PVM pVM)
1628{
1629 return pVM->cpum.s.HostFeatures.fXSaveRstor != 0;
1630}
1631
1632
1633/**
1634 * Checks if the host OS uses the SYSENTER / SYSEXIT instructions.
1635 * @returns true if used.
1636 * @returns false if not used.
1637 * @param pVM The cross context VM structure.
1638 */
1639VMMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM)
1640{
1641 return RT_BOOL(pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSENTER);
1642}
1643
1644
1645/**
1646 * Checks if the host OS uses the SYSCALL / SYSRET instructions.
1647 * @returns true if used.
1648 * @returns false if not used.
1649 * @param pVM The cross context VM structure.
1650 */
1651VMMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM)
1652{
1653 return RT_BOOL(pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSCALL);
1654}
1655
1656
1657/**
1658 * Checks if we activated the FPU/XMM state of the guest OS.
1659 *
1660 * Obsolete: This differs from CPUMIsGuestFPUStateLoaded() in that it refers to
1661 * the next time we'll be executing guest code, so it may return true for
1662 * 64-on-32 when we still haven't actually loaded the FPU status, just scheduled
1663 * it to be loaded the next time we go thru the world switcher
1664 * (CPUM_SYNC_FPU_STATE).
1665 *
1666 * @returns true / false.
1667 * @param pVCpu The cross context virtual CPU structure.
1668 */
1669VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCpu)
1670{
1671 bool fRet = RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST);
1672 AssertMsg(fRet == pVCpu->cpum.s.Guest.fUsedFpuGuest, ("fRet=%d\n", fRet));
1673 return fRet;
1674}
1675
1676
1677/**
1678 * Checks if we've really loaded the FPU/XMM state of the guest OS.
1679 *
1680 * @returns true / false.
1681 * @param pVCpu The cross context virtual CPU structure.
1682 */
1683VMMDECL(bool) CPUMIsGuestFPUStateLoaded(PVMCPU pVCpu)
1684{
1685 bool fRet = RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST);
1686 AssertMsg(fRet == pVCpu->cpum.s.Guest.fUsedFpuGuest, ("fRet=%d\n", fRet));
1687 return fRet;
1688}
1689
1690
1691/**
1692 * Checks if we saved the FPU/XMM state of the host OS.
1693 *
1694 * @returns true / false.
1695 * @param pVCpu The cross context virtual CPU structure.
1696 */
1697VMMDECL(bool) CPUMIsHostFPUStateSaved(PVMCPU pVCpu)
1698{
1699 return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_HOST);
1700}
1701
1702
1703/**
1704 * Checks if the guest debug state is active.
1705 *
1706 * @returns boolean
1707 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1708 */
1709VMMDECL(bool) CPUMIsGuestDebugStateActive(PVMCPU pVCpu)
1710{
1711 return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST);
1712}
1713
1714
1715/**
1716 * Checks if the hyper debug state is active.
1717 *
1718 * @returns boolean
1719 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1720 */
1721VMMDECL(bool) CPUMIsHyperDebugStateActive(PVMCPU pVCpu)
1722{
1723 return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HYPER);
1724}
1725
1726
1727/**
1728 * Mark the guest's debug state as inactive.
1729 *
1730 * @returns boolean
1731 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1732 * @todo This API doesn't make sense any more.
1733 */
1734VMMDECL(void) CPUMDeactivateGuestDebugState(PVMCPU pVCpu)
1735{
1736 Assert(!(pVCpu->cpum.s.fUseFlags & (CPUM_USED_DEBUG_REGS_GUEST | CPUM_USED_DEBUG_REGS_HYPER | CPUM_USED_DEBUG_REGS_HOST)));
1737 NOREF(pVCpu);
1738}
1739
1740
1741/**
1742 * Get the current privilege level of the guest.
1743 *
1744 * @returns CPL
1745 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1746 */
1747VMMDECL(uint32_t) CPUMGetGuestCPL(PVMCPU pVCpu)
1748{
1749 /*
1750 * CPL can reliably be found in SS.DPL (hidden regs valid) or SS if not.
1751 *
1752 * Note! We used to check CS.DPL here, assuming it was always equal to
1753 * CPL even if a conforming segment was loaded. But this turned out to
1754 * only apply to older AMD-V. With VT-x we had an ACP2 regression
1755 * during install after a far call to ring 2 with VT-x. Then on newer
1756 * AMD-V CPUs we have to move the VMCB.guest.u8CPL into cs.Attr.n.u2Dpl
1757 * as well as ss.Attr.n.u2Dpl to make this (and other) code work right.
1758 *
1759 * So, forget CS.DPL, always use SS.DPL.
1760 *
1761 * Note! The SS RPL is always equal to the CPL, while the CS RPL
1762 * isn't necessarily equal if the segment is conforming.
1763 * See section 4.11.1 in the AMD manual.
1764 *
1765 * Update: Where the heck does it say CS.RPL can differ from CPL other than
1766 * right after real->prot mode switch and when in V8086 mode? That
1767 * section says the RPL specified in a direct transfere (call, jmp,
1768 * ret) is not the one loaded into CS. Besides, if CS.RPL != CPL
1769 * it would be impossible for an exception handle or the iret
1770 * instruction to figure out whether SS:ESP are part of the frame
1771 * or not. VBox or qemu bug must've lead to this misconception.
1772 *
1773 * Update2: On an AMD bulldozer system here, I've no trouble loading a null
1774 * selector into SS with an RPL other than the CPL when CPL != 3 and
1775 * we're in 64-bit mode. The intel dev box doesn't allow this, on
1776 * RPL = CPL. Weird.
1777 */
1778 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_SS);
1779 uint32_t uCpl;
1780 if (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE)
1781 {
1782 if (!pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
1783 {
1784 if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.s.Guest.ss))
1785 uCpl = pVCpu->cpum.s.Guest.ss.Attr.n.u2Dpl;
1786 else
1787 uCpl = (pVCpu->cpum.s.Guest.ss.Sel & X86_SEL_RPL);
1788 }
1789 else
1790 uCpl = 3; /* V86 has CPL=3; REM doesn't set DPL=3 in V8086 mode. See @bugref{5130}. */
1791 }
1792 else
1793 uCpl = 0; /* Real mode is zero; CPL set to 3 for VT-x real-mode emulation. */
1794 return uCpl;
1795}
1796
1797
1798/**
1799 * Gets the current guest CPU mode.
1800 *
1801 * If paging mode is what you need, check out PGMGetGuestMode().
1802 *
1803 * @returns The CPU mode.
1804 * @param pVCpu The cross context virtual CPU structure.
1805 */
1806VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu)
1807{
1808 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_EFER);
1809 CPUMMODE enmMode;
1810 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
1811 enmMode = CPUMMODE_REAL;
1812 else if (!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
1813 enmMode = CPUMMODE_PROTECTED;
1814 else
1815 enmMode = CPUMMODE_LONG;
1816
1817 return enmMode;
1818}
1819
1820
1821/**
1822 * Figure whether the CPU is currently executing 16, 32 or 64 bit code.
1823 *
1824 * @returns 16, 32 or 64.
1825 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1826 */
1827VMMDECL(uint32_t) CPUMGetGuestCodeBits(PVMCPU pVCpu)
1828{
1829 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_EFER | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_CS);
1830
1831 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
1832 return 16;
1833
1834 if (pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
1835 {
1836 Assert(!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA));
1837 return 16;
1838 }
1839
1840 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
1841 if ( pVCpu->cpum.s.Guest.cs.Attr.n.u1Long
1842 && (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
1843 return 64;
1844
1845 if (pVCpu->cpum.s.Guest.cs.Attr.n.u1DefBig)
1846 return 32;
1847
1848 return 16;
1849}
1850
1851
1852VMMDECL(DISCPUMODE) CPUMGetGuestDisMode(PVMCPU pVCpu)
1853{
1854 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_EFER | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_CS);
1855
1856 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
1857 return DISCPUMODE_16BIT;
1858
1859 if (pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
1860 {
1861 Assert(!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA));
1862 return DISCPUMODE_16BIT;
1863 }
1864
1865 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
1866 if ( pVCpu->cpum.s.Guest.cs.Attr.n.u1Long
1867 && (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
1868 return DISCPUMODE_64BIT;
1869
1870 if (pVCpu->cpum.s.Guest.cs.Attr.n.u1DefBig)
1871 return DISCPUMODE_32BIT;
1872
1873 return DISCPUMODE_16BIT;
1874}
1875
1876
1877/**
1878 * Gets the guest MXCSR_MASK value.
1879 *
1880 * This does not access the x87 state, but the value we determined at VM
1881 * initialization.
1882 *
1883 * @returns MXCSR mask.
1884 * @param pVM The cross context VM structure.
1885 */
1886VMMDECL(uint32_t) CPUMGetGuestMxCsrMask(PVM pVM)
1887{
1888 return pVM->cpum.s.GuestInfo.fMxCsrMask;
1889}
1890
1891
1892/**
1893 * Returns whether the guest has physical interrupts enabled.
1894 *
1895 * @returns @c true if interrupts are enabled, @c false otherwise.
1896 * @param pVCpu The cross context virtual CPU structure.
1897 *
1898 * @remarks Warning! This function does -not- take into account the global-interrupt
1899 * flag (GIF).
1900 */
1901VMM_INT_DECL(bool) CPUMIsGuestPhysIntrEnabled(PVMCPU pVCpu)
1902{
1903 switch (CPUMGetGuestInNestedHwvirtMode(&pVCpu->cpum.s.Guest))
1904 {
1905 case CPUMHWVIRT_NONE:
1906 default:
1907 return pVCpu->cpum.s.Guest.eflags.Bits.u1IF;
1908 case CPUMHWVIRT_VMX:
1909 return CPUMIsGuestVmxPhysIntrEnabled(&pVCpu->cpum.s.Guest);
1910 case CPUMHWVIRT_SVM:
1911 return CPUMIsGuestSvmPhysIntrEnabled(pVCpu, &pVCpu->cpum.s.Guest);
1912 }
1913}
1914
1915
1916/**
1917 * Returns whether the nested-guest has virtual interrupts enabled.
1918 *
1919 * @returns @c true if interrupts are enabled, @c false otherwise.
1920 * @param pVCpu The cross context virtual CPU structure.
1921 *
1922 * @remarks Warning! This function does -not- take into account the global-interrupt
1923 * flag (GIF).
1924 */
1925VMM_INT_DECL(bool) CPUMIsGuestVirtIntrEnabled(PVMCPU pVCpu)
1926{
1927 PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1928 Assert(CPUMIsGuestInNestedHwvirtMode(pCtx));
1929
1930 if (CPUMIsGuestInVmxNonRootMode(pCtx))
1931 return CPUMIsGuestVmxVirtIntrEnabled(pCtx);
1932
1933 Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
1934 return CPUMIsGuestSvmVirtIntrEnabled(pVCpu, pCtx);
1935}
1936
1937
1938/**
1939 * Calculates the interruptiblity of the guest.
1940 *
1941 * @returns Interruptibility level.
1942 * @param pVCpu The cross context virtual CPU structure.
1943 */
1944VMM_INT_DECL(CPUMINTERRUPTIBILITY) CPUMGetGuestInterruptibility(PVMCPU pVCpu)
1945{
1946#if 1
1947 /* Global-interrupt flag blocks pretty much everything we care about here. */
1948 if (CPUMGetGuestGif(&pVCpu->cpum.s.Guest))
1949 {
1950 /*
1951 * Physical interrupts are primarily blocked using EFLAGS. However, we cannot access
1952 * it directly here. If and how EFLAGS are used depends on the context (nested-guest
1953 * or raw-mode). Hence we use the function below which handles the details.
1954 */
1955 if ( !(pVCpu->cpum.s.Guest.eflags.uBoth & CPUMCTX_INHIBIT_ALL_MASK)
1956 || ( !(pVCpu->cpum.s.Guest.eflags.uBoth & CPUMCTX_INHIBIT_NMI)
1957 && pVCpu->cpum.s.Guest.uRipInhibitInt != pVCpu->cpum.s.Guest.rip))
1958 {
1959 /** @todo OPT: this next call should be inlined! */
1960 if (CPUMIsGuestPhysIntrEnabled(pVCpu))
1961 {
1962 /** @todo OPT: type this out as it repeats tests. */
1963 if ( !CPUMIsGuestInNestedHwvirtMode(&pVCpu->cpum.s.Guest)
1964 || CPUMIsGuestVirtIntrEnabled(pVCpu))
1965 return CPUMINTERRUPTIBILITY_UNRESTRAINED;
1966
1967 /* Physical interrupts are enabled, but nested-guest virtual interrupts are disabled. */
1968 return CPUMINTERRUPTIBILITY_VIRT_INT_DISABLED;
1969 }
1970 return CPUMINTERRUPTIBILITY_INT_DISABLED;
1971 }
1972
1973 /*
1974 * Blocking the delivery of NMIs during an interrupt shadow is CPU implementation
1975 * specific. Therefore, in practice, we can't deliver an NMI in an interrupt shadow.
1976 * However, there is some uncertainity regarding the converse, i.e. whether
1977 * NMI-blocking until IRET blocks delivery of physical interrupts.
1978 *
1979 * See Intel spec. 25.4.1 "Event Blocking".
1980 */
1981 /** @todo r=bird: The above comment mixes up VMX root-mode and non-root. Section
1982 * 25.4.1 is only applicable to VMX non-root mode. In root mode /
1983 * non-VMX mode, I have not see any evidence in the intel manuals that
1984 * NMIs are not blocked when in an interrupt shadow. Section "6.7
1985 * NONMASKABLE INTERRUPT (NMI)" in SDM 3A seems pretty clear to me.
1986 */
1987 if (!(pVCpu->cpum.s.Guest.eflags.uBoth & CPUMCTX_INHIBIT_NMI))
1988 return CPUMINTERRUPTIBILITY_INT_INHIBITED;
1989 return CPUMINTERRUPTIBILITY_NMI_INHIBIT;
1990 }
1991 return CPUMINTERRUPTIBILITY_GLOBAL_INHIBIT;
1992#else
1993 if (pVCpu->cpum.s.Guest.rflags.Bits.u1IF)
1994 {
1995 if (pVCpu->cpum.s.Guest.hwvirt.fGif)
1996 {
1997 if (!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_BLOCK_NMIS | VMCPU_FF_INHIBIT_INTERRUPTS))
1998 return CPUMINTERRUPTIBILITY_UNRESTRAINED;
1999
2000 /** @todo does blocking NMIs mean interrupts are also inhibited? */
2001 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2002 {
2003 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
2004 return CPUMINTERRUPTIBILITY_INT_INHIBITED;
2005 return CPUMINTERRUPTIBILITY_NMI_INHIBIT;
2006 }
2007 AssertFailed();
2008 return CPUMINTERRUPTIBILITY_NMI_INHIBIT;
2009 }
2010 return CPUMINTERRUPTIBILITY_GLOBAL_INHIBIT;
2011 }
2012 else
2013 {
2014 if (pVCpu->cpum.s.Guest.hwvirt.fGif)
2015 {
2016 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
2017 return CPUMINTERRUPTIBILITY_NMI_INHIBIT;
2018 return CPUMINTERRUPTIBILITY_INT_DISABLED;
2019 }
2020 return CPUMINTERRUPTIBILITY_GLOBAL_INHIBIT;
2021 }
2022#endif
2023}
2024
2025
2026/**
2027 * Checks whether the SVM nested-guest has physical interrupts enabled.
2028 *
2029 * @returns true if interrupts are enabled, false otherwise.
2030 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2031 * @param pCtx The guest-CPU context.
2032 *
2033 * @remarks This does -not- take into account the global-interrupt flag.
2034 */
2035VMM_INT_DECL(bool) CPUMIsGuestSvmPhysIntrEnabled(PCVMCPU pVCpu, PCCPUMCTX pCtx)
2036{
2037 /** @todo Optimization: Avoid this function call and use a pointer to the
2038 * relevant eflags instead (setup during VMRUN instruction emulation). */
2039 Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
2040
2041 X86EFLAGS fEFlags;
2042 if (CPUMIsGuestSvmVirtIntrMasking(pVCpu, pCtx))
2043 fEFlags.u = pCtx->hwvirt.svm.HostState.rflags.u;
2044 else
2045 fEFlags.u = pCtx->eflags.u;
2046
2047 return fEFlags.Bits.u1IF;
2048}
2049
2050
2051/**
2052 * Checks whether the SVM nested-guest is in a state to receive virtual (setup
2053 * for injection by VMRUN instruction) interrupts.
2054 *
2055 * @returns VBox status code.
2056 * @retval true if it's ready, false otherwise.
2057 *
2058 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2059 * @param pCtx The guest-CPU context.
2060 */
2061VMM_INT_DECL(bool) CPUMIsGuestSvmVirtIntrEnabled(PCVMCPU pVCpu, PCCPUMCTX pCtx)
2062{
2063 RT_NOREF(pVCpu);
2064 Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
2065
2066 PCSVMVMCBCTRL pVmcbCtrl = &pCtx->hwvirt.svm.Vmcb.ctrl;
2067 PCSVMINTCTRL pVmcbIntCtrl = &pVmcbCtrl->IntCtrl;
2068 Assert(!pVmcbIntCtrl->n.u1VGifEnable); /* We don't support passing virtual-GIF feature to the guest yet. */
2069 if ( !pVmcbIntCtrl->n.u1IgnoreTPR
2070 && pVmcbIntCtrl->n.u4VIntrPrio <= pVmcbIntCtrl->n.u8VTPR)
2071 return false;
2072
2073 return RT_BOOL(pCtx->eflags.u & X86_EFL_IF);
2074}
2075
2076
2077/**
2078 * Gets the pending SVM nested-guest interruptvector.
2079 *
2080 * @returns The nested-guest interrupt to inject.
2081 * @param pCtx The guest-CPU context.
2082 */
2083VMM_INT_DECL(uint8_t) CPUMGetGuestSvmVirtIntrVector(PCCPUMCTX pCtx)
2084{
2085 return pCtx->hwvirt.svm.Vmcb.ctrl.IntCtrl.n.u8VIntrVector;
2086}
2087
2088
2089/**
2090 * Restores the host-state from the host-state save area as part of a \#VMEXIT.
2091 *
2092 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2093 * @param pCtx The guest-CPU context.
2094 */
2095VMM_INT_DECL(void) CPUMSvmVmExitRestoreHostState(PVMCPUCC pVCpu, PCPUMCTX pCtx)
2096{
2097 /*
2098 * Reload the guest's "host state".
2099 */
2100 PSVMHOSTSTATE pHostState = &pCtx->hwvirt.svm.HostState;
2101 pCtx->es = pHostState->es;
2102 pCtx->cs = pHostState->cs;
2103 pCtx->ss = pHostState->ss;
2104 pCtx->ds = pHostState->ds;
2105 pCtx->gdtr = pHostState->gdtr;
2106 pCtx->idtr = pHostState->idtr;
2107 CPUMSetGuestEferMsrNoChecks(pVCpu, pCtx->msrEFER, pHostState->uEferMsr);
2108 CPUMSetGuestCR0(pVCpu, pHostState->uCr0 | X86_CR0_PE);
2109 pCtx->cr3 = pHostState->uCr3;
2110 CPUMSetGuestCR4(pVCpu, pHostState->uCr4);
2111 pCtx->rflags.u = pHostState->rflags.u;
2112 pCtx->rflags.Bits.u1VM = 0;
2113 pCtx->rip = pHostState->uRip;
2114 pCtx->rsp = pHostState->uRsp;
2115 pCtx->rax = pHostState->uRax;
2116 pCtx->dr[7] &= ~(X86_DR7_ENABLED_MASK | X86_DR7_RAZ_MASK | X86_DR7_MBZ_MASK);
2117 pCtx->dr[7] |= X86_DR7_RA1_MASK;
2118 Assert(pCtx->ss.Attr.n.u2Dpl == 0);
2119
2120 /** @todo if RIP is not canonical or outside the CS segment limit, we need to
2121 * raise \#GP(0) in the guest. */
2122
2123 /** @todo check the loaded host-state for consistency. Figure out what
2124 * exactly this involves? */
2125}
2126
2127
2128/**
2129 * Saves the host-state to the host-state save area as part of a VMRUN.
2130 *
2131 * @param pCtx The guest-CPU context.
2132 * @param cbInstr The length of the VMRUN instruction in bytes.
2133 */
2134VMM_INT_DECL(void) CPUMSvmVmRunSaveHostState(PCPUMCTX pCtx, uint8_t cbInstr)
2135{
2136 PSVMHOSTSTATE pHostState = &pCtx->hwvirt.svm.HostState;
2137 pHostState->es = pCtx->es;
2138 pHostState->cs = pCtx->cs;
2139 pHostState->ss = pCtx->ss;
2140 pHostState->ds = pCtx->ds;
2141 pHostState->gdtr = pCtx->gdtr;
2142 pHostState->idtr = pCtx->idtr;
2143 pHostState->uEferMsr = pCtx->msrEFER;
2144 pHostState->uCr0 = pCtx->cr0;
2145 pHostState->uCr3 = pCtx->cr3;
2146 pHostState->uCr4 = pCtx->cr4;
2147 pHostState->rflags.u = pCtx->rflags.u;
2148 pHostState->uRip = pCtx->rip + cbInstr;
2149 pHostState->uRsp = pCtx->rsp;
2150 pHostState->uRax = pCtx->rax;
2151}
2152
2153
2154/**
2155 * Applies the TSC offset of a nested-guest if any and returns the TSC value for the
2156 * nested-guest.
2157 *
2158 * @returns The TSC offset after applying any nested-guest TSC offset.
2159 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2160 * @param uTscValue The guest TSC.
2161 *
2162 * @sa CPUMRemoveNestedGuestTscOffset.
2163 */
2164VMM_INT_DECL(uint64_t) CPUMApplyNestedGuestTscOffset(PCVMCPU pVCpu, uint64_t uTscValue)
2165{
2166 PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2167 if (CPUMIsGuestInVmxNonRootMode(pCtx))
2168 {
2169 if (CPUMIsGuestVmxProcCtlsSet(pCtx, VMX_PROC_CTLS_USE_TSC_OFFSETTING))
2170 return uTscValue + pCtx->hwvirt.vmx.Vmcs.u64TscOffset.u;
2171 return uTscValue;
2172 }
2173
2174 if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
2175 {
2176 uint64_t offTsc;
2177 if (!HMGetGuestSvmTscOffset(pVCpu, &offTsc))
2178 offTsc = pCtx->hwvirt.svm.Vmcb.ctrl.u64TSCOffset;
2179 return uTscValue + offTsc;
2180 }
2181 return uTscValue;
2182}
2183
2184
2185/**
2186 * Removes the TSC offset of a nested-guest if any and returns the TSC value for the
2187 * guest.
2188 *
2189 * @returns The TSC offset after removing any nested-guest TSC offset.
2190 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2191 * @param uTscValue The nested-guest TSC.
2192 *
2193 * @sa CPUMApplyNestedGuestTscOffset.
2194 */
2195VMM_INT_DECL(uint64_t) CPUMRemoveNestedGuestTscOffset(PCVMCPU pVCpu, uint64_t uTscValue)
2196{
2197 PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2198 if (CPUMIsGuestInVmxNonRootMode(pCtx))
2199 {
2200 if (CPUMIsGuestVmxProcCtlsSet(pCtx, VMX_PROC_CTLS_USE_TSC_OFFSETTING))
2201 return uTscValue - pCtx->hwvirt.vmx.Vmcs.u64TscOffset.u;
2202 return uTscValue;
2203 }
2204
2205 if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
2206 {
2207 uint64_t offTsc;
2208 if (!HMGetGuestSvmTscOffset(pVCpu, &offTsc))
2209 offTsc = pCtx->hwvirt.svm.Vmcb.ctrl.u64TSCOffset;
2210 return uTscValue - offTsc;
2211 }
2212 return uTscValue;
2213}
2214
2215
2216/**
2217 * Used to dynamically imports state residing in NEM or HM.
2218 *
2219 * This is a worker for the CPUM_IMPORT_EXTRN_RET() macro and various IEM ones.
2220 *
2221 * @returns VBox status code.
2222 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2223 * @param fExtrnImport The fields to import.
2224 * @thread EMT(pVCpu)
2225 */
2226VMM_INT_DECL(int) CPUMImportGuestStateOnDemand(PVMCPUCC pVCpu, uint64_t fExtrnImport)
2227{
2228 VMCPU_ASSERT_EMT(pVCpu);
2229 if (pVCpu->cpum.s.Guest.fExtrn & fExtrnImport)
2230 {
2231 switch (pVCpu->cpum.s.Guest.fExtrn & CPUMCTX_EXTRN_KEEPER_MASK)
2232 {
2233 case CPUMCTX_EXTRN_KEEPER_NEM:
2234 {
2235 int rc = NEMImportStateOnDemand(pVCpu, fExtrnImport);
2236 Assert(rc == VINF_SUCCESS || RT_FAILURE_NP(rc));
2237 return rc;
2238 }
2239
2240 case CPUMCTX_EXTRN_KEEPER_HM:
2241 {
2242#ifdef IN_RING0
2243 int rc = HMR0ImportStateOnDemand(pVCpu, fExtrnImport);
2244 Assert(rc == VINF_SUCCESS || RT_FAILURE_NP(rc));
2245 return rc;
2246#else
2247 AssertLogRelMsgFailed(("TODO Fetch HM state: %#RX64 vs %#RX64\n", pVCpu->cpum.s.Guest.fExtrn, fExtrnImport));
2248 return VINF_SUCCESS;
2249#endif
2250 }
2251 default:
2252 AssertLogRelMsgFailedReturn(("%#RX64 vs %#RX64\n", pVCpu->cpum.s.Guest.fExtrn, fExtrnImport), VERR_CPUM_IPE_2);
2253 }
2254 }
2255 return VINF_SUCCESS;
2256}
2257
2258
2259/**
2260 * Gets valid CR4 bits for the guest.
2261 *
2262 * @returns Valid CR4 bits.
2263 * @param pVM The cross context VM structure.
2264 */
2265VMM_INT_DECL(uint64_t) CPUMGetGuestCR4ValidMask(PVM pVM)
2266{
2267 PCCPUMFEATURES pGuestFeatures = &pVM->cpum.s.GuestFeatures;
2268 uint64_t fMask = X86_CR4_VME | X86_CR4_PVI
2269 | X86_CR4_TSD | X86_CR4_DE
2270 | X86_CR4_MCE | X86_CR4_PCE;
2271 if (pGuestFeatures->fPae)
2272 fMask |= X86_CR4_PAE;
2273 if (pGuestFeatures->fPge)
2274 fMask |= X86_CR4_PGE;
2275 if (pGuestFeatures->fPse)
2276 fMask |= X86_CR4_PSE;
2277 if (pGuestFeatures->fFxSaveRstor)
2278 fMask |= X86_CR4_OSFXSR;
2279 if (pGuestFeatures->fVmx)
2280 fMask |= X86_CR4_VMXE;
2281 if (pGuestFeatures->fXSaveRstor)
2282 fMask |= X86_CR4_OSXSAVE;
2283 if (pGuestFeatures->fPcid)
2284 fMask |= X86_CR4_PCIDE;
2285 if (pGuestFeatures->fFsGsBase)
2286 fMask |= X86_CR4_FSGSBASE;
2287 if (pGuestFeatures->fSse)
2288 fMask |= X86_CR4_OSXMMEEXCPT;
2289 return fMask;
2290}
2291
2292
2293/**
2294 * Sets the PAE PDPEs for the guest.
2295 *
2296 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2297 * @param paPaePdpes The PAE PDPEs to set.
2298 */
2299VMM_INT_DECL(void) CPUMSetGuestPaePdpes(PVMCPU pVCpu, PCX86PDPE paPaePdpes)
2300{
2301 Assert(paPaePdpes);
2302 for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->cpum.s.Guest.aPaePdpes); i++)
2303 pVCpu->cpum.s.Guest.aPaePdpes[i].u = paPaePdpes[i].u;
2304 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_CR3;
2305}
2306
2307
2308/**
2309 * Gets the PAE PDPTEs for the guest.
2310 *
2311 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2312 * @param paPaePdpes Where to store the PAE PDPEs.
2313 */
2314VMM_INT_DECL(void) CPUMGetGuestPaePdpes(PVMCPU pVCpu, PX86PDPE paPaePdpes)
2315{
2316 Assert(paPaePdpes);
2317 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR3);
2318 for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->cpum.s.Guest.aPaePdpes); i++)
2319 paPaePdpes[i].u = pVCpu->cpum.s.Guest.aPaePdpes[i].u;
2320}
2321
2322
2323/**
2324 * Starts a VMX-preemption timer to expire as specified by the nested hypervisor.
2325 *
2326 * @returns VBox status code.
2327 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2328 * @param uTimer The VMCS preemption timer value.
2329 * @param cShift The VMX-preemption timer shift (usually based on guest
2330 * VMX MSR rate).
2331 * @param pu64EntryTick Where to store the current tick when the timer is
2332 * programmed.
2333 * @thread EMT(pVCpu)
2334 */
2335VMM_INT_DECL(int) CPUMStartGuestVmxPremptTimer(PVMCPUCC pVCpu, uint32_t uTimer, uint8_t cShift, uint64_t *pu64EntryTick)
2336{
2337 Assert(uTimer);
2338 Assert(cShift <= 31);
2339 Assert(pu64EntryTick);
2340 VMCPU_ASSERT_EMT(pVCpu);
2341 uint64_t const cTicksToNext = uTimer << cShift;
2342 return TMTimerSetRelative(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.s.hNestedVmxPreemptTimer, cTicksToNext, pu64EntryTick);
2343}
2344
2345
2346/**
2347 * Stops the VMX-preemption timer from firing.
2348 *
2349 * @returns VBox status code.
2350 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2351 * @thread EMT.
2352 *
2353 * @remarks This can be called during VM reset, so we cannot assume it will be on
2354 * the EMT corresponding to @c pVCpu.
2355 */
2356VMM_INT_DECL(int) CPUMStopGuestVmxPremptTimer(PVMCPUCC pVCpu)
2357{
2358 /*
2359 * CPUM gets initialized before TM, so we defer creation of timers till CPUMR3InitCompleted().
2360 * However, we still get called during CPUMR3Init() and hence we need to check if we have
2361 * a valid timer object before trying to stop it.
2362 */
2363 int rc;
2364 TMTIMERHANDLE hTimer = pVCpu->cpum.s.hNestedVmxPreemptTimer;
2365 if (hTimer != NIL_TMTIMERHANDLE)
2366 {
2367 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2368 rc = TMTimerLock(pVM, hTimer, VERR_IGNORED);
2369 if (rc == VINF_SUCCESS)
2370 {
2371 if (TMTimerIsActive(pVM, hTimer))
2372 TMTimerStop(pVM, hTimer);
2373 TMTimerUnlock(pVM, hTimer);
2374 }
2375 }
2376 else
2377 rc = VERR_NOT_FOUND;
2378 return rc;
2379}
2380
2381
2382/**
2383 * Gets the read and write permission bits for an MSR in an MSR bitmap.
2384 *
2385 * @returns VMXMSRPM_XXX - the MSR permission.
2386 * @param pvMsrBitmap Pointer to the MSR bitmap.
2387 * @param idMsr The MSR to get permissions for.
2388 *
2389 * @sa hmR0VmxSetMsrPermission.
2390 */
2391VMM_INT_DECL(uint32_t) CPUMGetVmxMsrPermission(void const *pvMsrBitmap, uint32_t idMsr)
2392{
2393 AssertPtrReturn(pvMsrBitmap, VMXMSRPM_EXIT_RD | VMXMSRPM_EXIT_WR);
2394
2395 uint8_t const * const pbMsrBitmap = (uint8_t const * const)pvMsrBitmap;
2396
2397 /*
2398 * MSR Layout:
2399 * Byte index MSR range Interpreted as
2400 * 0x000 - 0x3ff 0x00000000 - 0x00001fff Low MSR read bits.
2401 * 0x400 - 0x7ff 0xc0000000 - 0xc0001fff High MSR read bits.
2402 * 0x800 - 0xbff 0x00000000 - 0x00001fff Low MSR write bits.
2403 * 0xc00 - 0xfff 0xc0000000 - 0xc0001fff High MSR write bits.
2404 *
2405 * A bit corresponding to an MSR within the above range causes a VM-exit
2406 * if the bit is 1 on executions of RDMSR/WRMSR. If an MSR falls out of
2407 * the MSR range, it always cause a VM-exit.
2408 *
2409 * See Intel spec. 24.6.9 "MSR-Bitmap Address".
2410 */
2411 uint32_t const offBitmapRead = 0;
2412 uint32_t const offBitmapWrite = 0x800;
2413 uint32_t offMsr;
2414 uint32_t iBit;
2415 if (idMsr <= UINT32_C(0x00001fff))
2416 {
2417 offMsr = 0;
2418 iBit = idMsr;
2419 }
2420 else if (idMsr - UINT32_C(0xc0000000) <= UINT32_C(0x00001fff))
2421 {
2422 offMsr = 0x400;
2423 iBit = idMsr - UINT32_C(0xc0000000);
2424 }
2425 else
2426 {
2427 LogFunc(("Warning! Out of range MSR %#RX32\n", idMsr));
2428 return VMXMSRPM_EXIT_RD | VMXMSRPM_EXIT_WR;
2429 }
2430
2431 /*
2432 * Get the MSR read permissions.
2433 */
2434 uint32_t fRet;
2435 uint32_t const offMsrRead = offBitmapRead + offMsr;
2436 Assert(offMsrRead + (iBit >> 3) < offBitmapWrite);
2437 if (ASMBitTest(pbMsrBitmap, (offMsrRead << 3) + iBit))
2438 fRet = VMXMSRPM_EXIT_RD;
2439 else
2440 fRet = VMXMSRPM_ALLOW_RD;
2441
2442 /*
2443 * Get the MSR write permissions.
2444 */
2445 uint32_t const offMsrWrite = offBitmapWrite + offMsr;
2446 Assert(offMsrWrite + (iBit >> 3) < X86_PAGE_4K_SIZE);
2447 if (ASMBitTest(pbMsrBitmap, (offMsrWrite << 3) + iBit))
2448 fRet |= VMXMSRPM_EXIT_WR;
2449 else
2450 fRet |= VMXMSRPM_ALLOW_WR;
2451
2452 Assert(VMXMSRPM_IS_FLAG_VALID(fRet));
2453 return fRet;
2454}
2455
2456
2457/**
2458 * Checks the permission bits for the specified I/O port from the given I/O bitmap
2459 * to see if causes a VM-exit.
2460 *
2461 * @returns @c true if the I/O port access must cause a VM-exit, @c false otherwise.
2462 * @param pbIoBitmap Pointer to I/O bitmap.
2463 * @param uPort The I/O port being accessed.
2464 * @param cbAccess e size of the I/O access in bytes (1, 2 or 4 bytes).
2465 */
2466static bool cpumGetVmxIoBitmapPermission(uint8_t const *pbIoBitmap, uint16_t uPort, uint8_t cbAccess)
2467{
2468 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
2469
2470 /*
2471 * If the I/O port access wraps around the 16-bit port I/O space, we must cause a
2472 * VM-exit.
2473 *
2474 * Reading 1, 2, 4 bytes at ports 0xffff, 0xfffe and 0xfffc are valid and do not
2475 * constitute a wrap around. However, reading 2 bytes at port 0xffff or 4 bytes
2476 * from port 0xffff/0xfffe/0xfffd constitute a wrap around. In other words, any
2477 * access to -both- ports 0xffff and port 0 is a wrap around.
2478 *
2479 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2480 */
2481 uint32_t const uPortLast = uPort + cbAccess;
2482 if (uPortLast > 0x10000)
2483 return true;
2484
2485 /*
2486 * If any bit corresponding to the I/O access is set, we must cause a VM-exit.
2487 */
2488 uint16_t const offPerm = uPort >> 3; /* Byte offset of the port. */
2489 uint16_t const idxPermBit = uPort - (offPerm << 3); /* Bit offset within byte. */
2490 Assert(idxPermBit < 8);
2491 static const uint8_t s_afMask[] = { 0x0, 0x1, 0x3, 0x7, 0xf }; /* Bit-mask for all access sizes. */
2492 uint16_t const fMask = s_afMask[cbAccess] << idxPermBit; /* Bit-mask of the access. */
2493
2494 /* Fetch 8 or 16-bits depending on whether the access spans 8-bit boundary. */
2495 RTUINT16U uPerm;
2496 uPerm.s.Lo = pbIoBitmap[offPerm];
2497 if (idxPermBit + cbAccess > 8)
2498 uPerm.s.Hi = pbIoBitmap[offPerm + 1];
2499 else
2500 uPerm.s.Hi = 0;
2501
2502 /* If any bit for the access is 1, we must cause a VM-exit. */
2503 if (uPerm.u & fMask)
2504 return true;
2505
2506 return false;
2507}
2508
2509
2510/**
2511 * Returns whether the given VMCS field is valid and supported for the guest.
2512 *
2513 * @param pVM The cross context VM structure.
2514 * @param u64VmcsField The VMCS field.
2515 *
2516 * @remarks This takes into account the CPU features exposed to the guest.
2517 */
2518VMM_INT_DECL(bool) CPUMIsGuestVmxVmcsFieldValid(PVMCC pVM, uint64_t u64VmcsField)
2519{
2520 uint32_t const uFieldEncHi = RT_HI_U32(u64VmcsField);
2521 uint32_t const uFieldEncLo = RT_LO_U32(u64VmcsField);
2522 if (!uFieldEncHi)
2523 { /* likely */ }
2524 else
2525 return false;
2526
2527 PCCPUMFEATURES pFeat = &pVM->cpum.s.GuestFeatures;
2528 switch (uFieldEncLo)
2529 {
2530 /*
2531 * 16-bit fields.
2532 */
2533 /* Control fields. */
2534 case VMX_VMCS16_VPID: return pFeat->fVmxVpid;
2535 case VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR: return pFeat->fVmxPostedInt;
2536 case VMX_VMCS16_EPTP_INDEX: return pFeat->fVmxEptXcptVe;
2537
2538 /* Guest-state fields. */
2539 case VMX_VMCS16_GUEST_ES_SEL:
2540 case VMX_VMCS16_GUEST_CS_SEL:
2541 case VMX_VMCS16_GUEST_SS_SEL:
2542 case VMX_VMCS16_GUEST_DS_SEL:
2543 case VMX_VMCS16_GUEST_FS_SEL:
2544 case VMX_VMCS16_GUEST_GS_SEL:
2545 case VMX_VMCS16_GUEST_LDTR_SEL:
2546 case VMX_VMCS16_GUEST_TR_SEL: return true;
2547 case VMX_VMCS16_GUEST_INTR_STATUS: return pFeat->fVmxVirtIntDelivery;
2548 case VMX_VMCS16_GUEST_PML_INDEX: return pFeat->fVmxPml;
2549
2550 /* Host-state fields. */
2551 case VMX_VMCS16_HOST_ES_SEL:
2552 case VMX_VMCS16_HOST_CS_SEL:
2553 case VMX_VMCS16_HOST_SS_SEL:
2554 case VMX_VMCS16_HOST_DS_SEL:
2555 case VMX_VMCS16_HOST_FS_SEL:
2556 case VMX_VMCS16_HOST_GS_SEL:
2557 case VMX_VMCS16_HOST_TR_SEL: return true;
2558
2559 /*
2560 * 64-bit fields.
2561 */
2562 /* Control fields. */
2563 case VMX_VMCS64_CTRL_IO_BITMAP_A_FULL:
2564 case VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH:
2565 case VMX_VMCS64_CTRL_IO_BITMAP_B_FULL:
2566 case VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH: return pFeat->fVmxUseIoBitmaps;
2567 case VMX_VMCS64_CTRL_MSR_BITMAP_FULL:
2568 case VMX_VMCS64_CTRL_MSR_BITMAP_HIGH: return pFeat->fVmxUseMsrBitmaps;
2569 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL:
2570 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH:
2571 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL:
2572 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH:
2573 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL:
2574 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH:
2575 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL:
2576 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH: return true;
2577 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_FULL:
2578 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_HIGH: return pFeat->fVmxPml;
2579 case VMX_VMCS64_CTRL_TSC_OFFSET_FULL:
2580 case VMX_VMCS64_CTRL_TSC_OFFSET_HIGH: return true;
2581 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL:
2582 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_HIGH: return pFeat->fVmxUseTprShadow;
2583 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL:
2584 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH: return pFeat->fVmxVirtApicAccess;
2585 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL:
2586 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH: return pFeat->fVmxPostedInt;
2587 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL:
2588 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH: return pFeat->fVmxVmFunc;
2589 case VMX_VMCS64_CTRL_EPTP_FULL:
2590 case VMX_VMCS64_CTRL_EPTP_HIGH: return pFeat->fVmxEpt;
2591 case VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL:
2592 case VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH:
2593 case VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL:
2594 case VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH:
2595 case VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL:
2596 case VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH:
2597 case VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL:
2598 case VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH: return pFeat->fVmxVirtIntDelivery;
2599 case VMX_VMCS64_CTRL_EPTP_LIST_FULL:
2600 case VMX_VMCS64_CTRL_EPTP_LIST_HIGH:
2601 {
2602 PCVMCPU pVCpu = pVM->CTX_SUFF(apCpus)[0];
2603 uint64_t const uVmFuncMsr = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64VmFunc;
2604 return RT_BOOL(RT_BF_GET(uVmFuncMsr, VMX_BF_VMFUNC_EPTP_SWITCHING));
2605 }
2606 case VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL:
2607 case VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH:
2608 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL:
2609 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH: return pFeat->fVmxVmcsShadowing;
2610 case VMX_VMCS64_CTRL_VE_XCPT_INFO_ADDR_FULL:
2611 case VMX_VMCS64_CTRL_VE_XCPT_INFO_ADDR_HIGH: return pFeat->fVmxEptXcptVe;
2612 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL:
2613 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH: return pFeat->fVmxXsavesXrstors;
2614 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL:
2615 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH: return pFeat->fVmxUseTscScaling;
2616 case VMX_VMCS64_CTRL_PROC_EXEC3_FULL:
2617 case VMX_VMCS64_CTRL_PROC_EXEC3_HIGH: return pFeat->fVmxTertiaryExecCtls;
2618
2619 /* Read-only data fields. */
2620 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL:
2621 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_HIGH: return pFeat->fVmxEpt;
2622
2623 /* Guest-state fields. */
2624 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL:
2625 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH:
2626 case VMX_VMCS64_GUEST_DEBUGCTL_FULL:
2627 case VMX_VMCS64_GUEST_DEBUGCTL_HIGH: return true;
2628 case VMX_VMCS64_GUEST_PAT_FULL:
2629 case VMX_VMCS64_GUEST_PAT_HIGH: return pFeat->fVmxEntryLoadPatMsr || pFeat->fVmxExitSavePatMsr;
2630 case VMX_VMCS64_GUEST_EFER_FULL:
2631 case VMX_VMCS64_GUEST_EFER_HIGH: return pFeat->fVmxEntryLoadEferMsr || pFeat->fVmxExitSaveEferMsr;
2632 case VMX_VMCS64_GUEST_PDPTE0_FULL:
2633 case VMX_VMCS64_GUEST_PDPTE0_HIGH:
2634 case VMX_VMCS64_GUEST_PDPTE1_FULL:
2635 case VMX_VMCS64_GUEST_PDPTE1_HIGH:
2636 case VMX_VMCS64_GUEST_PDPTE2_FULL:
2637 case VMX_VMCS64_GUEST_PDPTE2_HIGH:
2638 case VMX_VMCS64_GUEST_PDPTE3_FULL:
2639 case VMX_VMCS64_GUEST_PDPTE3_HIGH: return pFeat->fVmxEpt;
2640
2641 /* Host-state fields. */
2642 case VMX_VMCS64_HOST_PAT_FULL:
2643 case VMX_VMCS64_HOST_PAT_HIGH: return pFeat->fVmxExitLoadPatMsr;
2644 case VMX_VMCS64_HOST_EFER_FULL:
2645 case VMX_VMCS64_HOST_EFER_HIGH: return pFeat->fVmxExitLoadEferMsr;
2646
2647 /*
2648 * 32-bit fields.
2649 */
2650 /* Control fields. */
2651 case VMX_VMCS32_CTRL_PIN_EXEC:
2652 case VMX_VMCS32_CTRL_PROC_EXEC:
2653 case VMX_VMCS32_CTRL_EXCEPTION_BITMAP:
2654 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK:
2655 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH:
2656 case VMX_VMCS32_CTRL_CR3_TARGET_COUNT:
2657 case VMX_VMCS32_CTRL_EXIT:
2658 case VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT:
2659 case VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT:
2660 case VMX_VMCS32_CTRL_ENTRY:
2661 case VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT:
2662 case VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO:
2663 case VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE:
2664 case VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH: return true;
2665 case VMX_VMCS32_CTRL_TPR_THRESHOLD: return pFeat->fVmxUseTprShadow;
2666 case VMX_VMCS32_CTRL_PROC_EXEC2: return pFeat->fVmxSecondaryExecCtls;
2667 case VMX_VMCS32_CTRL_PLE_GAP:
2668 case VMX_VMCS32_CTRL_PLE_WINDOW: return pFeat->fVmxPauseLoopExit;
2669
2670 /* Read-only data fields. */
2671 case VMX_VMCS32_RO_VM_INSTR_ERROR:
2672 case VMX_VMCS32_RO_EXIT_REASON:
2673 case VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO:
2674 case VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE:
2675 case VMX_VMCS32_RO_IDT_VECTORING_INFO:
2676 case VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE:
2677 case VMX_VMCS32_RO_EXIT_INSTR_LENGTH:
2678 case VMX_VMCS32_RO_EXIT_INSTR_INFO: return true;
2679
2680 /* Guest-state fields. */
2681 case VMX_VMCS32_GUEST_ES_LIMIT:
2682 case VMX_VMCS32_GUEST_CS_LIMIT:
2683 case VMX_VMCS32_GUEST_SS_LIMIT:
2684 case VMX_VMCS32_GUEST_DS_LIMIT:
2685 case VMX_VMCS32_GUEST_FS_LIMIT:
2686 case VMX_VMCS32_GUEST_GS_LIMIT:
2687 case VMX_VMCS32_GUEST_LDTR_LIMIT:
2688 case VMX_VMCS32_GUEST_TR_LIMIT:
2689 case VMX_VMCS32_GUEST_GDTR_LIMIT:
2690 case VMX_VMCS32_GUEST_IDTR_LIMIT:
2691 case VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS:
2692 case VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS:
2693 case VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS:
2694 case VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS:
2695 case VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS:
2696 case VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS:
2697 case VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS:
2698 case VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS:
2699 case VMX_VMCS32_GUEST_INT_STATE:
2700 case VMX_VMCS32_GUEST_ACTIVITY_STATE:
2701 case VMX_VMCS32_GUEST_SMBASE:
2702 case VMX_VMCS32_GUEST_SYSENTER_CS: return true;
2703 case VMX_VMCS32_PREEMPT_TIMER_VALUE: return pFeat->fVmxPreemptTimer;
2704
2705 /* Host-state fields. */
2706 case VMX_VMCS32_HOST_SYSENTER_CS: return true;
2707
2708 /*
2709 * Natural-width fields.
2710 */
2711 /* Control fields. */
2712 case VMX_VMCS_CTRL_CR0_MASK:
2713 case VMX_VMCS_CTRL_CR4_MASK:
2714 case VMX_VMCS_CTRL_CR0_READ_SHADOW:
2715 case VMX_VMCS_CTRL_CR4_READ_SHADOW:
2716 case VMX_VMCS_CTRL_CR3_TARGET_VAL0:
2717 case VMX_VMCS_CTRL_CR3_TARGET_VAL1:
2718 case VMX_VMCS_CTRL_CR3_TARGET_VAL2:
2719 case VMX_VMCS_CTRL_CR3_TARGET_VAL3: return true;
2720
2721 /* Read-only data fields. */
2722 case VMX_VMCS_RO_EXIT_QUALIFICATION:
2723 case VMX_VMCS_RO_IO_RCX:
2724 case VMX_VMCS_RO_IO_RSI:
2725 case VMX_VMCS_RO_IO_RDI:
2726 case VMX_VMCS_RO_IO_RIP:
2727 case VMX_VMCS_RO_GUEST_LINEAR_ADDR: return true;
2728
2729 /* Guest-state fields. */
2730 case VMX_VMCS_GUEST_CR0:
2731 case VMX_VMCS_GUEST_CR3:
2732 case VMX_VMCS_GUEST_CR4:
2733 case VMX_VMCS_GUEST_ES_BASE:
2734 case VMX_VMCS_GUEST_CS_BASE:
2735 case VMX_VMCS_GUEST_SS_BASE:
2736 case VMX_VMCS_GUEST_DS_BASE:
2737 case VMX_VMCS_GUEST_FS_BASE:
2738 case VMX_VMCS_GUEST_GS_BASE:
2739 case VMX_VMCS_GUEST_LDTR_BASE:
2740 case VMX_VMCS_GUEST_TR_BASE:
2741 case VMX_VMCS_GUEST_GDTR_BASE:
2742 case VMX_VMCS_GUEST_IDTR_BASE:
2743 case VMX_VMCS_GUEST_DR7:
2744 case VMX_VMCS_GUEST_RSP:
2745 case VMX_VMCS_GUEST_RIP:
2746 case VMX_VMCS_GUEST_RFLAGS:
2747 case VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS:
2748 case VMX_VMCS_GUEST_SYSENTER_ESP:
2749 case VMX_VMCS_GUEST_SYSENTER_EIP: return true;
2750
2751 /* Host-state fields. */
2752 case VMX_VMCS_HOST_CR0:
2753 case VMX_VMCS_HOST_CR3:
2754 case VMX_VMCS_HOST_CR4:
2755 case VMX_VMCS_HOST_FS_BASE:
2756 case VMX_VMCS_HOST_GS_BASE:
2757 case VMX_VMCS_HOST_TR_BASE:
2758 case VMX_VMCS_HOST_GDTR_BASE:
2759 case VMX_VMCS_HOST_IDTR_BASE:
2760 case VMX_VMCS_HOST_SYSENTER_ESP:
2761 case VMX_VMCS_HOST_SYSENTER_EIP:
2762 case VMX_VMCS_HOST_RSP:
2763 case VMX_VMCS_HOST_RIP: return true;
2764 }
2765
2766 return false;
2767}
2768
2769
2770/**
2771 * Checks whether the given I/O access should cause a nested-guest VM-exit.
2772 *
2773 * @returns @c true if it causes a VM-exit, @c false otherwise.
2774 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2775 * @param u16Port The I/O port being accessed.
2776 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
2777 */
2778VMM_INT_DECL(bool) CPUMIsGuestVmxIoInterceptSet(PCVMCPU pVCpu, uint16_t u16Port, uint8_t cbAccess)
2779{
2780 PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2781 if (CPUMIsGuestVmxProcCtlsSet(pCtx, VMX_PROC_CTLS_UNCOND_IO_EXIT))
2782 return true;
2783
2784 if (CPUMIsGuestVmxProcCtlsSet(pCtx, VMX_PROC_CTLS_USE_IO_BITMAPS))
2785 return cpumGetVmxIoBitmapPermission(pCtx->hwvirt.vmx.abIoBitmap, u16Port, cbAccess);
2786
2787 return false;
2788}
2789
2790
2791/**
2792 * Checks whether the Mov-to-CR3 instruction causes a nested-guest VM-exit.
2793 *
2794 * @returns @c true if it causes a VM-exit, @c false otherwise.
2795 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2796 * @param uNewCr3 The CR3 value being written.
2797 */
2798VMM_INT_DECL(bool) CPUMIsGuestVmxMovToCr3InterceptSet(PVMCPU pVCpu, uint64_t uNewCr3)
2799{
2800 /*
2801 * If the CR3-load exiting control is set and the new CR3 value does not
2802 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
2803 *
2804 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2805 */
2806 PCCPUMCTX const pCtx = &pVCpu->cpum.s.Guest;
2807 if (CPUMIsGuestVmxProcCtlsSet(pCtx, VMX_PROC_CTLS_CR3_LOAD_EXIT))
2808 {
2809 uint32_t const uCr3TargetCount = pCtx->hwvirt.vmx.Vmcs.u32Cr3TargetCount;
2810 Assert(uCr3TargetCount <= VMX_V_CR3_TARGET_COUNT);
2811
2812 /* If the CR3-target count is 0, cause a VM-exit. */
2813 if (uCr3TargetCount == 0)
2814 return true;
2815
2816 /* If the CR3 being written doesn't match any of the target values, cause a VM-exit. */
2817 AssertCompile(VMX_V_CR3_TARGET_COUNT == 4);
2818 if ( uNewCr3 != pCtx->hwvirt.vmx.Vmcs.u64Cr3Target0.u
2819 && uNewCr3 != pCtx->hwvirt.vmx.Vmcs.u64Cr3Target1.u
2820 && uNewCr3 != pCtx->hwvirt.vmx.Vmcs.u64Cr3Target2.u
2821 && uNewCr3 != pCtx->hwvirt.vmx.Vmcs.u64Cr3Target3.u)
2822 return true;
2823 }
2824 return false;
2825}
2826
2827
2828/**
2829 * Checks whether a VMREAD or VMWRITE instruction for the given VMCS field causes a
2830 * VM-exit or not.
2831 *
2832 * @returns @c true if the VMREAD/VMWRITE is intercepted, @c false otherwise.
2833 * @param pVCpu The cross context virtual CPU structure.
2834 * @param uExitReason The VM-exit reason (VMX_EXIT_VMREAD or
2835 * VMX_EXIT_VMREAD).
2836 * @param u64VmcsField The VMCS field.
2837 */
2838VMM_INT_DECL(bool) CPUMIsGuestVmxVmreadVmwriteInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint64_t u64VmcsField)
2839{
2840 Assert(CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.s.Guest));
2841 Assert( uExitReason == VMX_EXIT_VMREAD
2842 || uExitReason == VMX_EXIT_VMWRITE);
2843
2844 /*
2845 * Without VMCS shadowing, all VMREAD and VMWRITE instructions are intercepted.
2846 */
2847 if (!CPUMIsGuestVmxProcCtls2Set(&pVCpu->cpum.s.Guest, VMX_PROC_CTLS2_VMCS_SHADOWING))
2848 return true;
2849
2850 /*
2851 * If any reserved bit in the 64-bit VMCS field encoding is set, the VMREAD/VMWRITE
2852 * is intercepted. This excludes any reserved bits in the valid parts of the field
2853 * encoding (i.e. bit 12).
2854 */
2855 if (u64VmcsField & VMX_VMCSFIELD_RSVD_MASK)
2856 return true;
2857
2858 /*
2859 * Finally, consult the VMREAD/VMWRITE bitmap whether to intercept the instruction or not.
2860 */
2861 uint32_t const u32VmcsField = RT_LO_U32(u64VmcsField);
2862 uint8_t const * const pbBitmap = uExitReason == VMX_EXIT_VMREAD
2863 ? &pVCpu->cpum.s.Guest.hwvirt.vmx.abVmreadBitmap[0]
2864 : &pVCpu->cpum.s.Guest.hwvirt.vmx.abVmwriteBitmap[0];
2865 Assert(pbBitmap);
2866 Assert(u32VmcsField >> 3 < VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
2867 return ASMBitTest(pbBitmap, (u32VmcsField << 3) + (u32VmcsField & 7));
2868}
2869
2870
2871
2872/**
2873 * Determines whether the given I/O access should cause a nested-guest \#VMEXIT.
2874 *
2875 * @param pvIoBitmap Pointer to the nested-guest IO bitmap.
2876 * @param u16Port The IO port being accessed.
2877 * @param enmIoType The type of IO access.
2878 * @param cbReg The IO operand size in bytes.
2879 * @param cAddrSizeBits The address size bits (for 16, 32 or 64).
2880 * @param iEffSeg The effective segment number.
2881 * @param fRep Whether this is a repeating IO instruction (REP prefix).
2882 * @param fStrIo Whether this is a string IO instruction.
2883 * @param pIoExitInfo Pointer to the SVMIOIOEXITINFO struct to be filled.
2884 * Optional, can be NULL.
2885 */
2886VMM_INT_DECL(bool) CPUMIsSvmIoInterceptSet(void *pvIoBitmap, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
2887 uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo,
2888 PSVMIOIOEXITINFO pIoExitInfo)
2889{
2890 Assert(cAddrSizeBits == 16 || cAddrSizeBits == 32 || cAddrSizeBits == 64);
2891 Assert(cbReg == 1 || cbReg == 2 || cbReg == 4 || cbReg == 8);
2892
2893 /*
2894 * The IOPM layout:
2895 * Each bit represents one 8-bit port. That makes a total of 0..65535 bits or
2896 * two 4K pages.
2897 *
2898 * For IO instructions that access more than a single byte, the permission bits
2899 * for all bytes are checked; if any bit is set to 1, the IO access is intercepted.
2900 *
2901 * Since it's possible to do a 32-bit IO access at port 65534 (accessing 4 bytes),
2902 * we need 3 extra bits beyond the second 4K page.
2903 */
2904 static const uint16_t s_auSizeMasks[] = { 0, 1, 3, 0, 0xf, 0, 0, 0 };
2905
2906 uint16_t const offIopm = u16Port >> 3;
2907 uint16_t const fSizeMask = s_auSizeMasks[(cAddrSizeBits >> SVM_IOIO_OP_SIZE_SHIFT) & 7];
2908 uint8_t const cShift = u16Port - (offIopm << 3);
2909 uint16_t const fIopmMask = (1 << cShift) | (fSizeMask << cShift);
2910
2911 uint8_t const *pbIopm = (uint8_t *)pvIoBitmap;
2912 Assert(pbIopm);
2913 pbIopm += offIopm;
2914 uint16_t const u16Iopm = *(uint16_t *)pbIopm;
2915 if (u16Iopm & fIopmMask)
2916 {
2917 if (pIoExitInfo)
2918 {
2919 static const uint32_t s_auIoOpSize[] =
2920 { SVM_IOIO_32_BIT_OP, SVM_IOIO_8_BIT_OP, SVM_IOIO_16_BIT_OP, 0, SVM_IOIO_32_BIT_OP, 0, 0, 0 };
2921
2922 static const uint32_t s_auIoAddrSize[] =
2923 { 0, SVM_IOIO_16_BIT_ADDR, SVM_IOIO_32_BIT_ADDR, 0, SVM_IOIO_64_BIT_ADDR, 0, 0, 0 };
2924
2925 pIoExitInfo->u = s_auIoOpSize[cbReg & 7];
2926 pIoExitInfo->u |= s_auIoAddrSize[(cAddrSizeBits >> 4) & 7];
2927 pIoExitInfo->n.u1Str = fStrIo;
2928 pIoExitInfo->n.u1Rep = fRep;
2929 pIoExitInfo->n.u3Seg = iEffSeg & 7;
2930 pIoExitInfo->n.u1Type = enmIoType;
2931 pIoExitInfo->n.u16Port = u16Port;
2932 }
2933 return true;
2934 }
2935
2936 /** @todo remove later (for debugging as VirtualBox always traps all IO
2937 * intercepts). */
2938 AssertMsgFailed(("CPUMSvmIsIOInterceptActive: We expect an IO intercept here!\n"));
2939 return false;
2940}
2941
2942
2943/**
2944 * Gets the MSR permission bitmap byte and bit offset for the specified MSR.
2945 *
2946 * @returns VBox status code.
2947 * @param idMsr The MSR being requested.
2948 * @param pbOffMsrpm Where to store the byte offset in the MSR permission
2949 * bitmap for @a idMsr.
2950 * @param puMsrpmBit Where to store the bit offset starting at the byte
2951 * returned in @a pbOffMsrpm.
2952 */
2953VMM_INT_DECL(int) CPUMGetSvmMsrpmOffsetAndBit(uint32_t idMsr, uint16_t *pbOffMsrpm, uint8_t *puMsrpmBit)
2954{
2955 Assert(pbOffMsrpm);
2956 Assert(puMsrpmBit);
2957
2958 /*
2959 * MSRPM Layout:
2960 * Byte offset MSR range
2961 * 0x000 - 0x7ff 0x00000000 - 0x00001fff
2962 * 0x800 - 0xfff 0xc0000000 - 0xc0001fff
2963 * 0x1000 - 0x17ff 0xc0010000 - 0xc0011fff
2964 * 0x1800 - 0x1fff Reserved
2965 *
2966 * Each MSR is represented by 2 permission bits (read and write).
2967 */
2968 if (idMsr <= 0x00001fff)
2969 {
2970 /* Pentium-compatible MSRs. */
2971 uint32_t const bitoffMsr = idMsr << 1;
2972 *pbOffMsrpm = bitoffMsr >> 3;
2973 *puMsrpmBit = bitoffMsr & 7;
2974 return VINF_SUCCESS;
2975 }
2976
2977 if ( idMsr >= 0xc0000000
2978 && idMsr <= 0xc0001fff)
2979 {
2980 /* AMD Sixth Generation x86 Processor MSRs. */
2981 uint32_t const bitoffMsr = (idMsr - 0xc0000000) << 1;
2982 *pbOffMsrpm = 0x800 + (bitoffMsr >> 3);
2983 *puMsrpmBit = bitoffMsr & 7;
2984 return VINF_SUCCESS;
2985 }
2986
2987 if ( idMsr >= 0xc0010000
2988 && idMsr <= 0xc0011fff)
2989 {
2990 /* AMD Seventh and Eighth Generation Processor MSRs. */
2991 uint32_t const bitoffMsr = (idMsr - 0xc0010000) << 1;
2992 *pbOffMsrpm = 0x1000 + (bitoffMsr >> 3);
2993 *puMsrpmBit = bitoffMsr & 7;
2994 return VINF_SUCCESS;
2995 }
2996
2997 *pbOffMsrpm = 0;
2998 *puMsrpmBit = 0;
2999 return VERR_OUT_OF_RANGE;
3000}
3001
3002
3003/**
3004 * Checks whether the guest is in VMX non-root mode and using EPT paging.
3005 *
3006 * @returns @c true if in VMX non-root operation with EPT, @c false otherwise.
3007 * @param pVCpu The cross context virtual CPU structure.
3008 */
3009VMM_INT_DECL(bool) CPUMIsGuestVmxEptPagingEnabled(PCVMCPUCC pVCpu)
3010{
3011 return CPUMIsGuestVmxEptPagingEnabledEx(&pVCpu->cpum.s.Guest);
3012}
3013
3014
3015/**
3016 * Checks whether the guest is in VMX non-root mode and using EPT paging and the
3017 * nested-guest is in PAE mode.
3018 *
3019 * @returns @c true if in VMX non-root operation with EPT, @c false otherwise.
3020 * @param pVCpu The cross context virtual CPU structure.
3021 */
3022VMM_INT_DECL(bool) CPUMIsGuestVmxEptPaePagingEnabled(PCVMCPUCC pVCpu)
3023{
3024 return CPUMIsGuestVmxEptPagingEnabledEx(&pVCpu->cpum.s.Guest)
3025 && CPUMIsGuestInPAEModeEx(&pVCpu->cpum.s.Guest);
3026}
3027
3028
3029/**
3030 * Returns the guest-physical address of the APIC-access page when executing a
3031 * nested-guest.
3032 *
3033 * @returns The APIC-access page guest-physical address.
3034 * @param pVCpu The cross context virtual CPU structure.
3035 */
3036VMM_INT_DECL(uint64_t) CPUMGetGuestVmxApicAccessPageAddr(PCVMCPUCC pVCpu)
3037{
3038 return CPUMGetGuestVmxApicAccessPageAddrEx(&pVCpu->cpum.s.Guest);
3039}
3040
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