VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp@ 25803

Last change on this file since 25803 was 25803, checked in by vboxsync, 15 years ago

VMM: provide reasonable cache info for Intel CPUs in leaf 4 of CPUID
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1/* $Id: CPUMAllRegs.cpp 25803 2010-01-13 14:16:12Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor(/Manager) - Getters and Setters.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_CPUM
27#include <VBox/cpum.h>
28#include <VBox/patm.h>
29#include <VBox/dbgf.h>
30#include <VBox/mm.h>
31#include "CPUMInternal.h"
32#include <VBox/vm.h>
33#include <VBox/err.h>
34#include <VBox/dis.h>
35#include <VBox/log.h>
36#include <VBox/hwaccm.h>
37#include <VBox/tm.h>
38#include <iprt/assert.h>
39#include <iprt/asm.h>
40#ifdef IN_RING3
41#include <iprt/thread.h>
42#endif
43
44/** Disable stack frame pointer generation here. */
45#if defined(_MSC_VER) && !defined(DEBUG)
46# pragma optimize("y", off)
47#endif
48
49
50/**
51 * Sets or resets an alternative hypervisor context core.
52 *
53 * This is called when we get a hypervisor trap set switch the context
54 * core with the trap frame on the stack. It is called again to reset
55 * back to the default context core when resuming hypervisor execution.
56 *
57 * @param pVCpu The VMCPU handle.
58 * @param pCtxCore Pointer to the alternative context core or NULL
59 * to go back to the default context core.
60 */
61VMMDECL(void) CPUMHyperSetCtxCore(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
62{
63 PVM pVM = pVCpu->CTX_SUFF(pVM);
64
65 LogFlow(("CPUMHyperSetCtxCore: %p/%p/%p -> %p\n", pVCpu->cpum.s.CTX_SUFF(pHyperCore), pCtxCore));
66 if (!pCtxCore)
67 {
68 pCtxCore = CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
69 pVCpu->cpum.s.pHyperCoreR3 = (R3PTRTYPE(PCPUMCTXCORE))VM_R3_ADDR(pVM, pCtxCore);
70 pVCpu->cpum.s.pHyperCoreR0 = (R0PTRTYPE(PCPUMCTXCORE))VM_R0_ADDR(pVM, pCtxCore);
71 pVCpu->cpum.s.pHyperCoreRC = (RCPTRTYPE(PCPUMCTXCORE))VM_RC_ADDR(pVM, pCtxCore);
72 }
73 else
74 {
75 pVCpu->cpum.s.pHyperCoreR3 = (R3PTRTYPE(PCPUMCTXCORE))MMHyperCCToR3(pVM, pCtxCore);
76 pVCpu->cpum.s.pHyperCoreR0 = (R0PTRTYPE(PCPUMCTXCORE))MMHyperCCToR0(pVM, pCtxCore);
77 pVCpu->cpum.s.pHyperCoreRC = (RCPTRTYPE(PCPUMCTXCORE))MMHyperCCToRC(pVM, pCtxCore);
78 }
79}
80
81
82/**
83 * Gets the pointer to the internal CPUMCTXCORE structure for the hypervisor.
84 * This is only for reading in order to save a few calls.
85 *
86 * @param pVM Handle to the virtual machine.
87 */
88VMMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVMCPU pVCpu)
89{
90 return pVCpu->cpum.s.CTX_SUFF(pHyperCore);
91}
92
93
94/**
95 * Queries the pointer to the internal CPUMCTX structure for the hypervisor.
96 *
97 * @returns VBox status code.
98 * @param pVM Handle to the virtual machine.
99 * @param ppCtx Receives the hyper CPUMCTX pointer when successful.
100 *
101 * @deprecated This will *not* (and has never) given the right picture of the
102 * hypervisor register state. With CPUMHyperSetCtxCore() this is
103 * getting much worse. So, use the individual functions for getting
104 * and esp. setting the hypervisor registers.
105 */
106VMMDECL(int) CPUMQueryHyperCtxPtr(PVMCPU pVCpu, PCPUMCTX *ppCtx)
107{
108 *ppCtx = &pVCpu->cpum.s.Hyper;
109 return VINF_SUCCESS;
110}
111
112
113VMMDECL(void) CPUMSetHyperGDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
114{
115 pVCpu->cpum.s.Hyper.gdtr.cbGdt = limit;
116 pVCpu->cpum.s.Hyper.gdtr.pGdt = addr;
117 pVCpu->cpum.s.Hyper.gdtrPadding = 0;
118}
119
120
121VMMDECL(void) CPUMSetHyperIDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
122{
123 pVCpu->cpum.s.Hyper.idtr.cbIdt = limit;
124 pVCpu->cpum.s.Hyper.idtr.pIdt = addr;
125 pVCpu->cpum.s.Hyper.idtrPadding = 0;
126}
127
128
129VMMDECL(void) CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3)
130{
131 pVCpu->cpum.s.Hyper.cr3 = cr3;
132
133#ifdef IN_RC
134 /* Update the current CR3. */
135 ASMSetCR3(cr3);
136#endif
137}
138
139VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu)
140{
141 return pVCpu->cpum.s.Hyper.cr3;
142}
143
144
145VMMDECL(void) CPUMSetHyperCS(PVMCPU pVCpu, RTSEL SelCS)
146{
147 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->cs = SelCS;
148}
149
150
151VMMDECL(void) CPUMSetHyperDS(PVMCPU pVCpu, RTSEL SelDS)
152{
153 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ds = SelDS;
154}
155
156
157VMMDECL(void) CPUMSetHyperES(PVMCPU pVCpu, RTSEL SelES)
158{
159 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->es = SelES;
160}
161
162
163VMMDECL(void) CPUMSetHyperFS(PVMCPU pVCpu, RTSEL SelFS)
164{
165 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->fs = SelFS;
166}
167
168
169VMMDECL(void) CPUMSetHyperGS(PVMCPU pVCpu, RTSEL SelGS)
170{
171 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->gs = SelGS;
172}
173
174
175VMMDECL(void) CPUMSetHyperSS(PVMCPU pVCpu, RTSEL SelSS)
176{
177 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ss = SelSS;
178}
179
180
181VMMDECL(void) CPUMSetHyperESP(PVMCPU pVCpu, uint32_t u32ESP)
182{
183 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->esp = u32ESP;
184}
185
186
187VMMDECL(int) CPUMSetHyperEFlags(PVMCPU pVCpu, uint32_t Efl)
188{
189 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->eflags.u32 = Efl;
190 return VINF_SUCCESS;
191}
192
193
194VMMDECL(void) CPUMSetHyperEIP(PVMCPU pVCpu, uint32_t u32EIP)
195{
196 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->eip = u32EIP;
197}
198
199
200VMMDECL(void) CPUMSetHyperTR(PVMCPU pVCpu, RTSEL SelTR)
201{
202 pVCpu->cpum.s.Hyper.tr = SelTR;
203}
204
205
206VMMDECL(void) CPUMSetHyperLDTR(PVMCPU pVCpu, RTSEL SelLDTR)
207{
208 pVCpu->cpum.s.Hyper.ldtr = SelLDTR;
209}
210
211
212VMMDECL(void) CPUMSetHyperDR0(PVMCPU pVCpu, RTGCUINTREG uDr0)
213{
214 pVCpu->cpum.s.Hyper.dr[0] = uDr0;
215 /** @todo in GC we must load it! */
216}
217
218
219VMMDECL(void) CPUMSetHyperDR1(PVMCPU pVCpu, RTGCUINTREG uDr1)
220{
221 pVCpu->cpum.s.Hyper.dr[1] = uDr1;
222 /** @todo in GC we must load it! */
223}
224
225
226VMMDECL(void) CPUMSetHyperDR2(PVMCPU pVCpu, RTGCUINTREG uDr2)
227{
228 pVCpu->cpum.s.Hyper.dr[2] = uDr2;
229 /** @todo in GC we must load it! */
230}
231
232
233VMMDECL(void) CPUMSetHyperDR3(PVMCPU pVCpu, RTGCUINTREG uDr3)
234{
235 pVCpu->cpum.s.Hyper.dr[3] = uDr3;
236 /** @todo in GC we must load it! */
237}
238
239
240VMMDECL(void) CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6)
241{
242 pVCpu->cpum.s.Hyper.dr[6] = uDr6;
243 /** @todo in GC we must load it! */
244}
245
246
247VMMDECL(void) CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7)
248{
249 pVCpu->cpum.s.Hyper.dr[7] = uDr7;
250 /** @todo in GC we must load it! */
251}
252
253
254VMMDECL(RTSEL) CPUMGetHyperCS(PVMCPU pVCpu)
255{
256 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->cs;
257}
258
259
260VMMDECL(RTSEL) CPUMGetHyperDS(PVMCPU pVCpu)
261{
262 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ds;
263}
264
265
266VMMDECL(RTSEL) CPUMGetHyperES(PVMCPU pVCpu)
267{
268 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->es;
269}
270
271
272VMMDECL(RTSEL) CPUMGetHyperFS(PVMCPU pVCpu)
273{
274 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->fs;
275}
276
277
278VMMDECL(RTSEL) CPUMGetHyperGS(PVMCPU pVCpu)
279{
280 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->gs;
281}
282
283
284VMMDECL(RTSEL) CPUMGetHyperSS(PVMCPU pVCpu)
285{
286 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ss;
287}
288
289
290VMMDECL(uint32_t) CPUMGetHyperEAX(PVMCPU pVCpu)
291{
292 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->eax;
293}
294
295
296VMMDECL(uint32_t) CPUMGetHyperEBX(PVMCPU pVCpu)
297{
298 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ebx;
299}
300
301
302VMMDECL(uint32_t) CPUMGetHyperECX(PVMCPU pVCpu)
303{
304 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ecx;
305}
306
307
308VMMDECL(uint32_t) CPUMGetHyperEDX(PVMCPU pVCpu)
309{
310 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->edx;
311}
312
313
314VMMDECL(uint32_t) CPUMGetHyperESI(PVMCPU pVCpu)
315{
316 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->esi;
317}
318
319
320VMMDECL(uint32_t) CPUMGetHyperEDI(PVMCPU pVCpu)
321{
322 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->edi;
323}
324
325
326VMMDECL(uint32_t) CPUMGetHyperEBP(PVMCPU pVCpu)
327{
328 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ebp;
329}
330
331
332VMMDECL(uint32_t) CPUMGetHyperESP(PVMCPU pVCpu)
333{
334 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->esp;
335}
336
337
338VMMDECL(uint32_t) CPUMGetHyperEFlags(PVMCPU pVCpu)
339{
340 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->eflags.u32;
341}
342
343
344VMMDECL(uint32_t) CPUMGetHyperEIP(PVMCPU pVCpu)
345{
346 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->eip;
347}
348
349
350VMMDECL(uint64_t) CPUMGetHyperRIP(PVMCPU pVCpu)
351{
352 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->rip;
353}
354
355
356VMMDECL(uint32_t) CPUMGetHyperIDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
357{
358 if (pcbLimit)
359 *pcbLimit = pVCpu->cpum.s.Hyper.idtr.cbIdt;
360 return pVCpu->cpum.s.Hyper.idtr.pIdt;
361}
362
363
364VMMDECL(uint32_t) CPUMGetHyperGDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
365{
366 if (pcbLimit)
367 *pcbLimit = pVCpu->cpum.s.Hyper.gdtr.cbGdt;
368 return pVCpu->cpum.s.Hyper.gdtr.pGdt;
369}
370
371
372VMMDECL(RTSEL) CPUMGetHyperLDTR(PVMCPU pVCpu)
373{
374 return pVCpu->cpum.s.Hyper.ldtr;
375}
376
377
378VMMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVMCPU pVCpu)
379{
380 return pVCpu->cpum.s.Hyper.dr[0];
381}
382
383
384VMMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVMCPU pVCpu)
385{
386 return pVCpu->cpum.s.Hyper.dr[1];
387}
388
389
390VMMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVMCPU pVCpu)
391{
392 return pVCpu->cpum.s.Hyper.dr[2];
393}
394
395
396VMMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVMCPU pVCpu)
397{
398 return pVCpu->cpum.s.Hyper.dr[3];
399}
400
401
402VMMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVMCPU pVCpu)
403{
404 return pVCpu->cpum.s.Hyper.dr[6];
405}
406
407
408VMMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVMCPU pVCpu)
409{
410 return pVCpu->cpum.s.Hyper.dr[7];
411}
412
413
414/**
415 * Gets the pointer to the internal CPUMCTXCORE structure.
416 * This is only for reading in order to save a few calls.
417 *
418 * @param pVCpu Handle to the virtual cpu.
419 */
420VMMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVMCPU pVCpu)
421{
422 return CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
423}
424
425
426/**
427 * Sets the guest context core registers.
428 *
429 * @param pVCpu Handle to the virtual cpu.
430 * @param pCtxCore The new context core values.
431 */
432VMMDECL(void) CPUMSetGuestCtxCore(PVMCPU pVCpu, PCCPUMCTXCORE pCtxCore)
433{
434 /** @todo #1410 requires selectors to be checked. (huh? 1410?) */
435
436 PCPUMCTXCORE pCtxCoreDst = CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
437 *pCtxCoreDst = *pCtxCore;
438
439 /* Mask away invalid parts of the cpu context. */
440 if (!CPUMIsGuestInLongMode(pVCpu))
441 {
442 uint64_t u64Mask = UINT64_C(0xffffffff);
443
444 pCtxCoreDst->rip &= u64Mask;
445 pCtxCoreDst->rax &= u64Mask;
446 pCtxCoreDst->rbx &= u64Mask;
447 pCtxCoreDst->rcx &= u64Mask;
448 pCtxCoreDst->rdx &= u64Mask;
449 pCtxCoreDst->rsi &= u64Mask;
450 pCtxCoreDst->rdi &= u64Mask;
451 pCtxCoreDst->rbp &= u64Mask;
452 pCtxCoreDst->rsp &= u64Mask;
453 pCtxCoreDst->rflags.u &= u64Mask;
454
455 pCtxCoreDst->r8 = 0;
456 pCtxCoreDst->r9 = 0;
457 pCtxCoreDst->r10 = 0;
458 pCtxCoreDst->r11 = 0;
459 pCtxCoreDst->r12 = 0;
460 pCtxCoreDst->r13 = 0;
461 pCtxCoreDst->r14 = 0;
462 pCtxCoreDst->r15 = 0;
463 }
464}
465
466
467/**
468 * Queries the pointer to the internal CPUMCTX structure
469 *
470 * @returns The CPUMCTX pointer.
471 * @param pVCpu Handle to the virtual cpu.
472 */
473VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu)
474{
475 return &pVCpu->cpum.s.Guest;
476}
477
478VMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
479{
480 pVCpu->cpum.s.Guest.gdtr.cbGdt = limit;
481 pVCpu->cpum.s.Guest.gdtr.pGdt = addr;
482 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GDTR;
483 return VINF_SUCCESS;
484}
485
486VMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
487{
488 pVCpu->cpum.s.Guest.idtr.cbIdt = limit;
489 pVCpu->cpum.s.Guest.idtr.pIdt = addr;
490 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_IDTR;
491 return VINF_SUCCESS;
492}
493
494VMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr)
495{
496 AssertMsgFailed(("Need to load the hidden bits too!\n"));
497
498 pVCpu->cpum.s.Guest.tr = tr;
499 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_TR;
500 return VINF_SUCCESS;
501}
502
503VMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr)
504{
505 pVCpu->cpum.s.Guest.ldtr = ldtr;
506 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_LDTR;
507 return VINF_SUCCESS;
508}
509
510
511/**
512 * Set the guest CR0.
513 *
514 * When called in GC, the hyper CR0 may be updated if that is
515 * required. The caller only has to take special action if AM,
516 * WP, PG or PE changes.
517 *
518 * @returns VINF_SUCCESS (consider it void).
519 * @param pVCpu Handle to the virtual cpu.
520 * @param cr0 The new CR0 value.
521 */
522VMMDECL(int) CPUMSetGuestCR0(PVMCPU pVCpu, uint64_t cr0)
523{
524#ifdef IN_RC
525 /*
526 * Check if we need to change hypervisor CR0 because
527 * of math stuff.
528 */
529 if ( (cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP))
530 != (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP)))
531 {
532 if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU))
533 {
534 /*
535 * We haven't saved the host FPU state yet, so TS and MT are both set
536 * and EM should be reflecting the guest EM (it always does this).
537 */
538 if ((cr0 & X86_CR0_EM) != (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM))
539 {
540 uint32_t HyperCR0 = ASMGetCR0();
541 AssertMsg((HyperCR0 & (X86_CR0_TS | X86_CR0_MP)) == (X86_CR0_TS | X86_CR0_MP), ("%#x\n", HyperCR0));
542 AssertMsg((HyperCR0 & X86_CR0_EM) == (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM), ("%#x\n", HyperCR0));
543 HyperCR0 &= ~X86_CR0_EM;
544 HyperCR0 |= cr0 & X86_CR0_EM;
545 Log(("CPUM New HyperCR0=%#x\n", HyperCR0));
546 ASMSetCR0(HyperCR0);
547 }
548# ifdef VBOX_STRICT
549 else
550 {
551 uint32_t HyperCR0 = ASMGetCR0();
552 AssertMsg((HyperCR0 & (X86_CR0_TS | X86_CR0_MP)) == (X86_CR0_TS | X86_CR0_MP), ("%#x\n", HyperCR0));
553 AssertMsg((HyperCR0 & X86_CR0_EM) == (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM), ("%#x\n", HyperCR0));
554 }
555# endif
556 }
557 else
558 {
559 /*
560 * Already saved the state, so we're just mirroring
561 * the guest flags.
562 */
563 uint32_t HyperCR0 = ASMGetCR0();
564 AssertMsg( (HyperCR0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP))
565 == (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP)),
566 ("%#x %#x\n", HyperCR0, pVCpu->cpum.s.Guest.cr0));
567 HyperCR0 &= ~(X86_CR0_TS | X86_CR0_EM | X86_CR0_MP);
568 HyperCR0 |= cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP);
569 Log(("CPUM New HyperCR0=%#x\n", HyperCR0));
570 ASMSetCR0(HyperCR0);
571 }
572 }
573#endif /* IN_RC */
574
575 /*
576 * Check for changes causing TLB flushes (for REM).
577 * The caller is responsible for calling PGM when appropriate.
578 */
579 if ( (cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE))
580 != (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)))
581 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
582 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR0;
583
584 pVCpu->cpum.s.Guest.cr0 = cr0 | X86_CR0_ET;
585 return VINF_SUCCESS;
586}
587
588
589VMMDECL(int) CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2)
590{
591 pVCpu->cpum.s.Guest.cr2 = cr2;
592 return VINF_SUCCESS;
593}
594
595
596VMMDECL(int) CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3)
597{
598 pVCpu->cpum.s.Guest.cr3 = cr3;
599 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR3;
600 return VINF_SUCCESS;
601}
602
603
604VMMDECL(int) CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4)
605{
606 if ( (cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE))
607 != (pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE)))
608 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
609 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR4;
610 if (!CPUMSupportsFXSR(pVCpu->CTX_SUFF(pVM)))
611 cr4 &= ~X86_CR4_OSFSXR;
612 pVCpu->cpum.s.Guest.cr4 = cr4;
613 return VINF_SUCCESS;
614}
615
616
617VMMDECL(int) CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags)
618{
619 pVCpu->cpum.s.Guest.eflags.u32 = eflags;
620 return VINF_SUCCESS;
621}
622
623
624VMMDECL(int) CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip)
625{
626 pVCpu->cpum.s.Guest.eip = eip;
627 return VINF_SUCCESS;
628}
629
630
631VMMDECL(int) CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax)
632{
633 pVCpu->cpum.s.Guest.eax = eax;
634 return VINF_SUCCESS;
635}
636
637
638VMMDECL(int) CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx)
639{
640 pVCpu->cpum.s.Guest.ebx = ebx;
641 return VINF_SUCCESS;
642}
643
644
645VMMDECL(int) CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx)
646{
647 pVCpu->cpum.s.Guest.ecx = ecx;
648 return VINF_SUCCESS;
649}
650
651
652VMMDECL(int) CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx)
653{
654 pVCpu->cpum.s.Guest.edx = edx;
655 return VINF_SUCCESS;
656}
657
658
659VMMDECL(int) CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp)
660{
661 pVCpu->cpum.s.Guest.esp = esp;
662 return VINF_SUCCESS;
663}
664
665
666VMMDECL(int) CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp)
667{
668 pVCpu->cpum.s.Guest.ebp = ebp;
669 return VINF_SUCCESS;
670}
671
672
673VMMDECL(int) CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi)
674{
675 pVCpu->cpum.s.Guest.esi = esi;
676 return VINF_SUCCESS;
677}
678
679
680VMMDECL(int) CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi)
681{
682 pVCpu->cpum.s.Guest.edi = edi;
683 return VINF_SUCCESS;
684}
685
686
687VMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss)
688{
689 pVCpu->cpum.s.Guest.ss = ss;
690 return VINF_SUCCESS;
691}
692
693
694VMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs)
695{
696 pVCpu->cpum.s.Guest.cs = cs;
697 return VINF_SUCCESS;
698}
699
700
701VMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds)
702{
703 pVCpu->cpum.s.Guest.ds = ds;
704 return VINF_SUCCESS;
705}
706
707
708VMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es)
709{
710 pVCpu->cpum.s.Guest.es = es;
711 return VINF_SUCCESS;
712}
713
714
715VMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs)
716{
717 pVCpu->cpum.s.Guest.fs = fs;
718 return VINF_SUCCESS;
719}
720
721
722VMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs)
723{
724 pVCpu->cpum.s.Guest.gs = gs;
725 return VINF_SUCCESS;
726}
727
728
729VMMDECL(void) CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val)
730{
731 pVCpu->cpum.s.Guest.msrEFER = val;
732}
733
734
735VMMDECL(uint64_t) CPUMGetGuestMsr(PVMCPU pVCpu, unsigned idMsr)
736{
737 uint64_t u64 = 0;
738
739 switch (idMsr)
740 {
741 case MSR_IA32_TSC:
742 u64 = TMCpuTickGet(pVCpu);
743 break;
744
745 case MSR_IA32_CR_PAT:
746 u64 = pVCpu->cpum.s.Guest.msrPAT;
747 break;
748
749 case MSR_IA32_SYSENTER_CS:
750 u64 = pVCpu->cpum.s.Guest.SysEnter.cs;
751 break;
752
753 case MSR_IA32_SYSENTER_EIP:
754 u64 = pVCpu->cpum.s.Guest.SysEnter.eip;
755 break;
756
757 case MSR_IA32_SYSENTER_ESP:
758 u64 = pVCpu->cpum.s.Guest.SysEnter.esp;
759 break;
760
761 case MSR_K6_EFER:
762 u64 = pVCpu->cpum.s.Guest.msrEFER;
763 break;
764
765 case MSR_K8_SF_MASK:
766 u64 = pVCpu->cpum.s.Guest.msrSFMASK;
767 break;
768
769 case MSR_K6_STAR:
770 u64 = pVCpu->cpum.s.Guest.msrSTAR;
771 break;
772
773 case MSR_K8_LSTAR:
774 u64 = pVCpu->cpum.s.Guest.msrLSTAR;
775 break;
776
777 case MSR_K8_CSTAR:
778 u64 = pVCpu->cpum.s.Guest.msrCSTAR;
779 break;
780
781 case MSR_K8_KERNEL_GS_BASE:
782 u64 = pVCpu->cpum.s.Guest.msrKERNELGSBASE;
783 break;
784
785 case MSR_K8_TSC_AUX:
786 u64 = pVCpu->cpum.s.GuestMsr.msr.tscAux;
787 break;
788
789 case MSR_IA32_PERF_STATUS:
790 /** @todo: could really be not exactly correct, maybe use host's values */
791 /* Keep consistent with helper_rdmsr() in REM */
792 u64 = (1000ULL /* TSC increment by tick */)
793 | (((uint64_t)4ULL) << 40 /* CPU multiplier */ );
794 break;
795
796 /* fs & gs base skipped on purpose as the current context might not be up-to-date. */
797 default:
798 AssertFailed();
799 break;
800 }
801 return u64;
802}
803
804VMMDECL(void) CPUMSetGuestMsr(PVMCPU pVCpu, unsigned idMsr, uint64_t valMsr)
805{
806 /* On purpose only a limited number of MSRs; use the emulation function to update the others. */
807 switch (idMsr)
808 {
809 case MSR_K8_TSC_AUX:
810 pVCpu->cpum.s.GuestMsr.msr.tscAux = valMsr;
811 break;
812
813 default:
814 AssertFailed();
815 break;
816 }
817}
818
819VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
820{
821 if (pcbLimit)
822 *pcbLimit = pVCpu->cpum.s.Guest.idtr.cbIdt;
823 return pVCpu->cpum.s.Guest.idtr.pIdt;
824}
825
826
827VMMDECL(RTSEL) CPUMGetGuestTR(PVMCPU pVCpu, PCPUMSELREGHID pHidden)
828{
829 if (pHidden)
830 *pHidden = pVCpu->cpum.s.Guest.trHid;
831 return pVCpu->cpum.s.Guest.tr;
832}
833
834
835VMMDECL(RTSEL) CPUMGetGuestCS(PVMCPU pVCpu)
836{
837 return pVCpu->cpum.s.Guest.cs;
838}
839
840
841VMMDECL(RTSEL) CPUMGetGuestDS(PVMCPU pVCpu)
842{
843 return pVCpu->cpum.s.Guest.ds;
844}
845
846
847VMMDECL(RTSEL) CPUMGetGuestES(PVMCPU pVCpu)
848{
849 return pVCpu->cpum.s.Guest.es;
850}
851
852
853VMMDECL(RTSEL) CPUMGetGuestFS(PVMCPU pVCpu)
854{
855 return pVCpu->cpum.s.Guest.fs;
856}
857
858
859VMMDECL(RTSEL) CPUMGetGuestGS(PVMCPU pVCpu)
860{
861 return pVCpu->cpum.s.Guest.gs;
862}
863
864
865VMMDECL(RTSEL) CPUMGetGuestSS(PVMCPU pVCpu)
866{
867 return pVCpu->cpum.s.Guest.ss;
868}
869
870
871VMMDECL(RTSEL) CPUMGetGuestLDTR(PVMCPU pVCpu)
872{
873 return pVCpu->cpum.s.Guest.ldtr;
874}
875
876
877VMMDECL(uint64_t) CPUMGetGuestCR0(PVMCPU pVCpu)
878{
879 return pVCpu->cpum.s.Guest.cr0;
880}
881
882
883VMMDECL(uint64_t) CPUMGetGuestCR2(PVMCPU pVCpu)
884{
885 return pVCpu->cpum.s.Guest.cr2;
886}
887
888
889VMMDECL(uint64_t) CPUMGetGuestCR3(PVMCPU pVCpu)
890{
891 return pVCpu->cpum.s.Guest.cr3;
892}
893
894
895VMMDECL(uint64_t) CPUMGetGuestCR4(PVMCPU pVCpu)
896{
897 return pVCpu->cpum.s.Guest.cr4;
898}
899
900
901VMMDECL(void) CPUMGetGuestGDTR(PVMCPU pVCpu, PVBOXGDTR pGDTR)
902{
903 *pGDTR = pVCpu->cpum.s.Guest.gdtr;
904}
905
906
907VMMDECL(uint32_t) CPUMGetGuestEIP(PVMCPU pVCpu)
908{
909 return pVCpu->cpum.s.Guest.eip;
910}
911
912
913VMMDECL(uint64_t) CPUMGetGuestRIP(PVMCPU pVCpu)
914{
915 return pVCpu->cpum.s.Guest.rip;
916}
917
918
919VMMDECL(uint32_t) CPUMGetGuestEAX(PVMCPU pVCpu)
920{
921 return pVCpu->cpum.s.Guest.eax;
922}
923
924
925VMMDECL(uint32_t) CPUMGetGuestEBX(PVMCPU pVCpu)
926{
927 return pVCpu->cpum.s.Guest.ebx;
928}
929
930
931VMMDECL(uint32_t) CPUMGetGuestECX(PVMCPU pVCpu)
932{
933 return pVCpu->cpum.s.Guest.ecx;
934}
935
936
937VMMDECL(uint32_t) CPUMGetGuestEDX(PVMCPU pVCpu)
938{
939 return pVCpu->cpum.s.Guest.edx;
940}
941
942
943VMMDECL(uint32_t) CPUMGetGuestESI(PVMCPU pVCpu)
944{
945 return pVCpu->cpum.s.Guest.esi;
946}
947
948
949VMMDECL(uint32_t) CPUMGetGuestEDI(PVMCPU pVCpu)
950{
951 return pVCpu->cpum.s.Guest.edi;
952}
953
954
955VMMDECL(uint32_t) CPUMGetGuestESP(PVMCPU pVCpu)
956{
957 return pVCpu->cpum.s.Guest.esp;
958}
959
960
961VMMDECL(uint32_t) CPUMGetGuestEBP(PVMCPU pVCpu)
962{
963 return pVCpu->cpum.s.Guest.ebp;
964}
965
966
967VMMDECL(uint32_t) CPUMGetGuestEFlags(PVMCPU pVCpu)
968{
969 return pVCpu->cpum.s.Guest.eflags.u32;
970}
971
972
973///@todo: crx should be an array
974VMMDECL(int) CPUMGetGuestCRx(PVMCPU pVCpu, unsigned iReg, uint64_t *pValue)
975{
976 switch (iReg)
977 {
978 case USE_REG_CR0:
979 *pValue = pVCpu->cpum.s.Guest.cr0;
980 break;
981 case USE_REG_CR2:
982 *pValue = pVCpu->cpum.s.Guest.cr2;
983 break;
984 case USE_REG_CR3:
985 *pValue = pVCpu->cpum.s.Guest.cr3;
986 break;
987 case USE_REG_CR4:
988 *pValue = pVCpu->cpum.s.Guest.cr4;
989 break;
990 default:
991 return VERR_INVALID_PARAMETER;
992 }
993 return VINF_SUCCESS;
994}
995
996
997VMMDECL(uint64_t) CPUMGetGuestDR0(PVMCPU pVCpu)
998{
999 return pVCpu->cpum.s.Guest.dr[0];
1000}
1001
1002
1003VMMDECL(uint64_t) CPUMGetGuestDR1(PVMCPU pVCpu)
1004{
1005 return pVCpu->cpum.s.Guest.dr[1];
1006}
1007
1008
1009VMMDECL(uint64_t) CPUMGetGuestDR2(PVMCPU pVCpu)
1010{
1011 return pVCpu->cpum.s.Guest.dr[2];
1012}
1013
1014
1015VMMDECL(uint64_t) CPUMGetGuestDR3(PVMCPU pVCpu)
1016{
1017 return pVCpu->cpum.s.Guest.dr[3];
1018}
1019
1020
1021VMMDECL(uint64_t) CPUMGetGuestDR6(PVMCPU pVCpu)
1022{
1023 return pVCpu->cpum.s.Guest.dr[6];
1024}
1025
1026
1027VMMDECL(uint64_t) CPUMGetGuestDR7(PVMCPU pVCpu)
1028{
1029 return pVCpu->cpum.s.Guest.dr[7];
1030}
1031
1032
1033VMMDECL(int) CPUMGetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t *pValue)
1034{
1035 AssertReturn(iReg <= USE_REG_DR7, VERR_INVALID_PARAMETER);
1036 /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
1037 if (iReg == 4 || iReg == 5)
1038 iReg += 2;
1039 *pValue = pVCpu->cpum.s.Guest.dr[iReg];
1040 return VINF_SUCCESS;
1041}
1042
1043
1044VMMDECL(uint64_t) CPUMGetGuestEFER(PVMCPU pVCpu)
1045{
1046 return pVCpu->cpum.s.Guest.msrEFER;
1047}
1048
1049
1050/**
1051 * Gets a CpuId leaf.
1052 *
1053 * @param pVCpu The VMCPU handle.
1054 * @param iLeaf The CPUID leaf to get.
1055 * @param pEax Where to store the EAX value.
1056 * @param pEbx Where to store the EBX value.
1057 * @param pEcx Where to store the ECX value.
1058 * @param pEdx Where to store the EDX value.
1059 */
1060VMMDECL(void) CPUMGetGuestCpuId(PVMCPU pVCpu, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx)
1061{
1062 PVM pVM = pVCpu->CTX_SUFF(pVM);
1063
1064 PCCPUMCPUID pCpuId;
1065 if (iLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
1066 pCpuId = &pVM->cpum.s.aGuestCpuIdStd[iLeaf];
1067 else if (iLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
1068 pCpuId = &pVM->cpum.s.aGuestCpuIdExt[iLeaf - UINT32_C(0x80000000)];
1069 else if (iLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
1070 pCpuId = &pVM->cpum.s.aGuestCpuIdCentaur[iLeaf - UINT32_C(0xc0000000)];
1071 else
1072 pCpuId = &pVM->cpum.s.GuestCpuIdDef;
1073
1074 uint32_t cCurrentCacheIndex = *pEcx;
1075
1076 *pEax = pCpuId->eax;
1077 *pEbx = pCpuId->ebx;
1078 *pEcx = pCpuId->ecx;
1079 *pEdx = pCpuId->edx;
1080
1081 if ( iLeaf == 1
1082 && pVM->cCpus > 1)
1083 {
1084 /* Bits 31-24: Initial APIC ID */
1085 Assert(pVCpu->idCpu <= 255);
1086 *pEbx |= (pVCpu->idCpu << 24);
1087 }
1088
1089 if ( iLeaf == 4
1090 && cCurrentCacheIndex < 3
1091 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
1092 {
1093 uint32_t type, level, sharing, linesize,
1094 partitions, associativity, sets, cores;
1095
1096 /* For type: 1 - data cache, 2 - i-cache, 3 - unified */
1097 partitions = 1;
1098 /* Those are only to shut up compiler, as they will always
1099 get overwritten, and compiler should be able to figure that out */
1100 sets = associativity = sharing = level = 1;
1101 cores = pVM->cCpus > 32 ? 32 : pVM->cCpus;
1102 switch (cCurrentCacheIndex)
1103 {
1104 case 0:
1105 type = 1;
1106 level = 1;
1107 sharing = 1;
1108 linesize = 64;
1109 associativity = 8;
1110 sets = 64;
1111 break;
1112 case 1:
1113 level = 1;
1114 type = 2;
1115 sharing = 1;
1116 linesize = 64;
1117 associativity = 8;
1118 sets = 64;
1119 break;
1120 case 2:
1121 level = 2;
1122 type = 3;
1123 sharing = 2;
1124 linesize = 64;
1125 associativity = 24;
1126 sets = 4096;
1127 break;
1128 }
1129
1130 *pEax |= ((cores - 1) << 26) |
1131 ((sharing - 1) << 14) |
1132 (level << 5) |
1133 1;
1134 *pEbx = (linesize - 1) |
1135 ((partitions - 1) << 12) |
1136 ((associativity - 1) << 22); /* -1 encoding */
1137 *pEcx = sets - 1;
1138 }
1139
1140 Log2(("CPUMGetGuestCpuId: iLeaf=%#010x %RX32 %RX32 %RX32 %RX32\n", iLeaf, *pEax, *pEbx, *pEcx, *pEdx));
1141}
1142
1143/**
1144 * Gets a number of standard CPUID leafs.
1145 *
1146 * @returns Number of leafs.
1147 * @param pVM The VM handle.
1148 * @remark Intended for PATM.
1149 */
1150VMMDECL(uint32_t) CPUMGetGuestCpuIdStdMax(PVM pVM)
1151{
1152 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd);
1153}
1154
1155
1156/**
1157 * Gets a number of extended CPUID leafs.
1158 *
1159 * @returns Number of leafs.
1160 * @param pVM The VM handle.
1161 * @remark Intended for PATM.
1162 */
1163VMMDECL(uint32_t) CPUMGetGuestCpuIdExtMax(PVM pVM)
1164{
1165 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt);
1166}
1167
1168
1169/**
1170 * Gets a number of centaur CPUID leafs.
1171 *
1172 * @returns Number of leafs.
1173 * @param pVM The VM handle.
1174 * @remark Intended for PATM.
1175 */
1176VMMDECL(uint32_t) CPUMGetGuestCpuIdCentaurMax(PVM pVM)
1177{
1178 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur);
1179}
1180
1181
1182/**
1183 * Sets a CPUID feature bit.
1184 *
1185 * @param pVM The VM Handle.
1186 * @param enmFeature The feature to set.
1187 */
1188VMMDECL(void) CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
1189{
1190 switch (enmFeature)
1191 {
1192 /*
1193 * Set the APIC bit in both feature masks.
1194 */
1195 case CPUMCPUIDFEATURE_APIC:
1196 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1197 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_APIC;
1198 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1199 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1200 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_APIC;
1201 LogRel(("CPUMSetGuestCpuIdFeature: Enabled APIC\n"));
1202 break;
1203
1204 /*
1205 * Set the x2APIC bit in the standard feature mask.
1206 */
1207 case CPUMCPUIDFEATURE_X2APIC:
1208 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1209 pVM->cpum.s.aGuestCpuIdStd[1].ecx |= X86_CPUID_FEATURE_ECX_X2APIC;
1210 LogRel(("CPUMSetGuestCpuIdFeature: Enabled x2APIC\n"));
1211 break;
1212
1213 /*
1214 * Set the sysenter/sysexit bit in the standard feature mask.
1215 * Assumes the caller knows what it's doing! (host must support these)
1216 */
1217 case CPUMCPUIDFEATURE_SEP:
1218 {
1219 if (!(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_SEP))
1220 {
1221 AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
1222 return;
1223 }
1224
1225 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1226 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_SEP;
1227 LogRel(("CPUMSetGuestCpuIdFeature: Enabled sysenter/exit\n"));
1228 break;
1229 }
1230
1231 /*
1232 * Set the syscall/sysret bit in the extended feature mask.
1233 * Assumes the caller knows what it's doing! (host must support these)
1234 */
1235 case CPUMCPUIDFEATURE_SYSCALL:
1236 {
1237 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1238 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_SEP))
1239 {
1240#if HC_ARCH_BITS == 32
1241 /* X86_CPUID_AMD_FEATURE_EDX_SEP not set it seems in 32 bits mode.
1242 * Even when the cpu is capable of doing so in 64 bits mode.
1243 */
1244 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1245 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE)
1246 || !(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_SEP))
1247#endif
1248 {
1249 LogRel(("WARNING: Can't turn on SYSCALL/SYSRET when the host doesn't support it!!\n"));
1250 return;
1251 }
1252 }
1253 /* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
1254 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_SEP;
1255 LogRel(("CPUMSetGuestCpuIdFeature: Enabled syscall/ret\n"));
1256 break;
1257 }
1258
1259 /*
1260 * Set the PAE bit in both feature masks.
1261 * Assumes the caller knows what it's doing! (host must support these)
1262 */
1263 case CPUMCPUIDFEATURE_PAE:
1264 {
1265 if (!(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_PAE))
1266 {
1267 LogRel(("WARNING: Can't turn on PAE when the host doesn't support it!!\n"));
1268 return;
1269 }
1270
1271 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1272 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_PAE;
1273 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1274 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1275 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_PAE;
1276 LogRel(("CPUMSetGuestCpuIdFeature: Enabled PAE\n"));
1277 break;
1278 }
1279
1280 /*
1281 * Set the LONG MODE bit in the extended feature mask.
1282 * Assumes the caller knows what it's doing! (host must support these)
1283 */
1284 case CPUMCPUIDFEATURE_LONG_MODE:
1285 {
1286 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1287 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE))
1288 {
1289 LogRel(("WARNING: Can't turn on LONG MODE when the host doesn't support it!!\n"));
1290 return;
1291 }
1292
1293 /* Valid for both Intel and AMD. */
1294 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_LONG_MODE;
1295 LogRel(("CPUMSetGuestCpuIdFeature: Enabled LONG MODE\n"));
1296 break;
1297 }
1298
1299 /*
1300 * Set the NXE bit in the extended feature mask.
1301 * Assumes the caller knows what it's doing! (host must support these)
1302 */
1303 case CPUMCPUIDFEATURE_NXE:
1304 {
1305 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1306 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_NX))
1307 {
1308 LogRel(("WARNING: Can't turn on NXE when the host doesn't support it!!\n"));
1309 return;
1310 }
1311
1312 /* Valid for both Intel and AMD. */
1313 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_NX;
1314 LogRel(("CPUMSetGuestCpuIdFeature: Enabled NXE\n"));
1315 break;
1316 }
1317
1318 case CPUMCPUIDFEATURE_LAHF:
1319 {
1320 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1321 || !(ASMCpuId_ECX(0x80000001) & X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF))
1322 {
1323 LogRel(("WARNING: Can't turn on LAHF/SAHF when the host doesn't support it!!\n"));
1324 return;
1325 }
1326
1327 pVM->cpum.s.aGuestCpuIdExt[1].ecx |= X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF;
1328 LogRel(("CPUMSetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
1329 break;
1330 }
1331
1332 case CPUMCPUIDFEATURE_PAT:
1333 {
1334 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1335 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_PAT;
1336 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1337 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1338 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_PAT;
1339 LogRel(("CPUMClearGuestCpuIdFeature: Enabled PAT\n"));
1340 break;
1341 }
1342
1343 case CPUMCPUIDFEATURE_RDTSCP:
1344 {
1345 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1346 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_RDTSCP))
1347 {
1348 LogRel(("WARNING: Can't turn on RDTSCP when the host doesn't support it!!\n"));
1349 return;
1350 }
1351
1352 /* Valid for AMD only (for now). */
1353 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_RDTSCP;
1354 LogRel(("CPUMSetGuestCpuIdFeature: Enabled RDTSCP.\n"));
1355 break;
1356 }
1357
1358 default:
1359 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
1360 break;
1361 }
1362 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1363 {
1364 PVMCPU pVCpu = &pVM->aCpus[i];
1365 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CPUID;
1366 }
1367}
1368
1369
1370/**
1371 * Queries a CPUID feature bit.
1372 *
1373 * @returns boolean for feature presence
1374 * @param pVM The VM Handle.
1375 * @param enmFeature The feature to query.
1376 */
1377VMMDECL(bool) CPUMGetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
1378{
1379 switch (enmFeature)
1380 {
1381 case CPUMCPUIDFEATURE_PAE:
1382 {
1383 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1384 return !!(pVM->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PAE);
1385 break;
1386 }
1387
1388 case CPUMCPUIDFEATURE_RDTSCP:
1389 {
1390 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1391 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
1392 break;
1393 }
1394
1395 case CPUMCPUIDFEATURE_LONG_MODE:
1396 {
1397 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1398 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE);
1399 break;
1400 }
1401
1402 default:
1403 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
1404 break;
1405 }
1406 return false;
1407}
1408
1409
1410/**
1411 * Clears a CPUID feature bit.
1412 *
1413 * @param pVM The VM Handle.
1414 * @param enmFeature The feature to clear.
1415 */
1416VMMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
1417{
1418 switch (enmFeature)
1419 {
1420 /*
1421 * Set the APIC bit in both feature masks.
1422 */
1423 case CPUMCPUIDFEATURE_APIC:
1424 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1425 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_APIC;
1426 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1427 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1428 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
1429 Log(("CPUMSetGuestCpuIdFeature: Disabled APIC\n"));
1430 break;
1431
1432 /*
1433 * Clear the x2APIC bit in the standard feature mask.
1434 */
1435 case CPUMCPUIDFEATURE_X2APIC:
1436 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1437 pVM->cpum.s.aGuestCpuIdStd[1].ecx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
1438 LogRel(("CPUMSetGuestCpuIdFeature: Disabled x2APIC\n"));
1439 break;
1440
1441 case CPUMCPUIDFEATURE_PAE:
1442 {
1443 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1444 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_PAE;
1445 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1446 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1447 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
1448 LogRel(("CPUMClearGuestCpuIdFeature: Disabled PAE!\n"));
1449 break;
1450 }
1451
1452 case CPUMCPUIDFEATURE_PAT:
1453 {
1454 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1455 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_PAT;
1456 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1457 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1458 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_PAT;
1459 LogRel(("CPUMClearGuestCpuIdFeature: Disabled PAT!\n"));
1460 break;
1461 }
1462
1463 case CPUMCPUIDFEATURE_LONG_MODE:
1464 {
1465 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1466 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_LONG_MODE;
1467 break;
1468 }
1469
1470 case CPUMCPUIDFEATURE_LAHF:
1471 {
1472 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1473 pVM->cpum.s.aGuestCpuIdExt[1].ecx &= ~X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF;
1474 break;
1475 }
1476
1477 default:
1478 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
1479 break;
1480 }
1481 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1482 {
1483 PVMCPU pVCpu = &pVM->aCpus[i];
1484 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CPUID;
1485 }
1486}
1487
1488
1489/**
1490 * Gets the host CPU vendor
1491 *
1492 * @returns CPU vendor
1493 * @param pVM The VM handle.
1494 */
1495VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM)
1496{
1497 return pVM->cpum.s.enmHostCpuVendor;
1498}
1499
1500/**
1501 * Gets the CPU vendor
1502 *
1503 * @returns CPU vendor
1504 * @param pVM The VM handle.
1505 */
1506VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM)
1507{
1508 return pVM->cpum.s.enmGuestCpuVendor;
1509}
1510
1511
1512VMMDECL(int) CPUMSetGuestDR0(PVMCPU pVCpu, uint64_t uDr0)
1513{
1514 pVCpu->cpum.s.Guest.dr[0] = uDr0;
1515 return CPUMRecalcHyperDRx(pVCpu);
1516}
1517
1518
1519VMMDECL(int) CPUMSetGuestDR1(PVMCPU pVCpu, uint64_t uDr1)
1520{
1521 pVCpu->cpum.s.Guest.dr[1] = uDr1;
1522 return CPUMRecalcHyperDRx(pVCpu);
1523}
1524
1525
1526VMMDECL(int) CPUMSetGuestDR2(PVMCPU pVCpu, uint64_t uDr2)
1527{
1528 pVCpu->cpum.s.Guest.dr[2] = uDr2;
1529 return CPUMRecalcHyperDRx(pVCpu);
1530}
1531
1532
1533VMMDECL(int) CPUMSetGuestDR3(PVMCPU pVCpu, uint64_t uDr3)
1534{
1535 pVCpu->cpum.s.Guest.dr[3] = uDr3;
1536 return CPUMRecalcHyperDRx(pVCpu);
1537}
1538
1539
1540VMMDECL(int) CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6)
1541{
1542 pVCpu->cpum.s.Guest.dr[6] = uDr6;
1543 return CPUMRecalcHyperDRx(pVCpu);
1544}
1545
1546
1547VMMDECL(int) CPUMSetGuestDR7(PVMCPU pVCpu, uint64_t uDr7)
1548{
1549 pVCpu->cpum.s.Guest.dr[7] = uDr7;
1550 return CPUMRecalcHyperDRx(pVCpu);
1551}
1552
1553
1554VMMDECL(int) CPUMSetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t Value)
1555{
1556 AssertReturn(iReg <= USE_REG_DR7, VERR_INVALID_PARAMETER);
1557 /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
1558 if (iReg == 4 || iReg == 5)
1559 iReg += 2;
1560 pVCpu->cpum.s.Guest.dr[iReg] = Value;
1561 return CPUMRecalcHyperDRx(pVCpu);
1562}
1563
1564
1565/**
1566 * Recalculates the hypvervisor DRx register values based on
1567 * current guest registers and DBGF breakpoints.
1568 *
1569 * This is called whenever a guest DRx register is modified and when DBGF
1570 * sets a hardware breakpoint. In guest context this function will reload
1571 * any (hyper) DRx registers which comes out with a different value.
1572 *
1573 * @returns VINF_SUCCESS.
1574 * @param pVCpu The VMCPU handle.
1575 */
1576VMMDECL(int) CPUMRecalcHyperDRx(PVMCPU pVCpu)
1577{
1578 PVM pVM = pVCpu->CTX_SUFF(pVM);
1579
1580 /*
1581 * Compare the DR7s first.
1582 *
1583 * We only care about the enabled flags. The GE and LE flags are always
1584 * set and we don't care if the guest doesn't set them. GD is virtualized
1585 * when we dispatch #DB, we never enable it.
1586 */
1587 const RTGCUINTREG uDbgfDr7 = DBGFBpGetDR7(pVM);
1588#ifdef CPUM_VIRTUALIZE_DRX
1589 const RTGCUINTREG uGstDr7 = CPUMGetGuestDR7(pVCpu);
1590#else
1591 const RTGCUINTREG uGstDr7 = 0;
1592#endif
1593 if ((uGstDr7 | uDbgfDr7) & X86_DR7_ENABLED_MASK)
1594 {
1595 /*
1596 * Ok, something is enabled. Recalc each of the breakpoints.
1597 * Straight forward code, not optimized/minimized in any way.
1598 */
1599 RTGCUINTREG uNewDr7 = X86_DR7_GE | X86_DR7_LE | X86_DR7_MB1_MASK;
1600
1601 /* bp 0 */
1602 RTGCUINTREG uNewDr0;
1603 if (uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0))
1604 {
1605 uNewDr7 |= uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
1606 uNewDr0 = DBGFBpGetDR0(pVM);
1607 }
1608 else if (uGstDr7 & (X86_DR7_L0 | X86_DR7_G0))
1609 {
1610 uNewDr7 |= uGstDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
1611 uNewDr0 = CPUMGetGuestDR0(pVCpu);
1612 }
1613 else
1614 uNewDr0 = pVCpu->cpum.s.Hyper.dr[0];
1615
1616 /* bp 1 */
1617 RTGCUINTREG uNewDr1;
1618 if (uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1))
1619 {
1620 uNewDr7 |= uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
1621 uNewDr1 = DBGFBpGetDR1(pVM);
1622 }
1623 else if (uGstDr7 & (X86_DR7_L1 | X86_DR7_G1))
1624 {
1625 uNewDr7 |= uGstDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
1626 uNewDr1 = CPUMGetGuestDR1(pVCpu);
1627 }
1628 else
1629 uNewDr1 = pVCpu->cpum.s.Hyper.dr[1];
1630
1631 /* bp 2 */
1632 RTGCUINTREG uNewDr2;
1633 if (uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2))
1634 {
1635 uNewDr7 |= uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
1636 uNewDr2 = DBGFBpGetDR2(pVM);
1637 }
1638 else if (uGstDr7 & (X86_DR7_L2 | X86_DR7_G2))
1639 {
1640 uNewDr7 |= uGstDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
1641 uNewDr2 = CPUMGetGuestDR2(pVCpu);
1642 }
1643 else
1644 uNewDr2 = pVCpu->cpum.s.Hyper.dr[2];
1645
1646 /* bp 3 */
1647 RTGCUINTREG uNewDr3;
1648 if (uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3))
1649 {
1650 uNewDr7 |= uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
1651 uNewDr3 = DBGFBpGetDR3(pVM);
1652 }
1653 else if (uGstDr7 & (X86_DR7_L3 | X86_DR7_G3))
1654 {
1655 uNewDr7 |= uGstDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
1656 uNewDr3 = CPUMGetGuestDR3(pVCpu);
1657 }
1658 else
1659 uNewDr3 = pVCpu->cpum.s.Hyper.dr[3];
1660
1661 /*
1662 * Apply the updates.
1663 */
1664#ifdef IN_RC
1665 if (!(pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS))
1666 {
1667 /** @todo save host DBx registers. */
1668 }
1669#endif
1670 pVCpu->cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS;
1671 if (uNewDr3 != pVCpu->cpum.s.Hyper.dr[3])
1672 CPUMSetHyperDR3(pVCpu, uNewDr3);
1673 if (uNewDr2 != pVCpu->cpum.s.Hyper.dr[2])
1674 CPUMSetHyperDR2(pVCpu, uNewDr2);
1675 if (uNewDr1 != pVCpu->cpum.s.Hyper.dr[1])
1676 CPUMSetHyperDR1(pVCpu, uNewDr1);
1677 if (uNewDr0 != pVCpu->cpum.s.Hyper.dr[0])
1678 CPUMSetHyperDR0(pVCpu, uNewDr0);
1679 if (uNewDr7 != pVCpu->cpum.s.Hyper.dr[7])
1680 CPUMSetHyperDR7(pVCpu, uNewDr7);
1681 }
1682 else
1683 {
1684#ifdef IN_RC
1685 if (pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS)
1686 {
1687 /** @todo restore host DBx registers. */
1688 }
1689#endif
1690 pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS;
1691 }
1692 Log2(("CPUMRecalcHyperDRx: fUseFlags=%#x %RGr %RGr %RGr %RGr %RGr %RGr\n",
1693 pVCpu->cpum.s.fUseFlags, pVCpu->cpum.s.Hyper.dr[0], pVCpu->cpum.s.Hyper.dr[1],
1694 pVCpu->cpum.s.Hyper.dr[2], pVCpu->cpum.s.Hyper.dr[3], pVCpu->cpum.s.Hyper.dr[6],
1695 pVCpu->cpum.s.Hyper.dr[7]));
1696
1697 return VINF_SUCCESS;
1698}
1699
1700#ifndef IN_RING0 /** @todo I don't think we need this in R0, so move it to CPUMAll.cpp? */
1701
1702/**
1703 * Transforms the guest CPU state to raw-ring mode.
1704 *
1705 * This function will change the any of the cs and ss register with DPL=0 to DPL=1.
1706 *
1707 * @returns VBox status. (recompiler failure)
1708 * @param pVCpu The VMCPU handle.
1709 * @param pCtxCore The context core (for trap usage).
1710 * @see @ref pg_raw
1711 */
1712VMMDECL(int) CPUMRawEnter(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
1713{
1714 PVM pVM = pVCpu->CTX_SUFF(pVM);
1715
1716 Assert(!pVM->cpum.s.fRawEntered);
1717 if (!pCtxCore)
1718 pCtxCore = CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
1719
1720 /*
1721 * Are we in Ring-0?
1722 */
1723 if ( pCtxCore->ss && (pCtxCore->ss & X86_SEL_RPL) == 0
1724 && !pCtxCore->eflags.Bits.u1VM)
1725 {
1726 /*
1727 * Enter execution mode.
1728 */
1729 PATMRawEnter(pVM, pCtxCore);
1730
1731 /*
1732 * Set CPL to Ring-1.
1733 */
1734 pCtxCore->ss |= 1;
1735 if (pCtxCore->cs && (pCtxCore->cs & X86_SEL_RPL) == 0)
1736 pCtxCore->cs |= 1;
1737 }
1738 else
1739 {
1740 AssertMsg((pCtxCore->ss & X86_SEL_RPL) >= 2 || pCtxCore->eflags.Bits.u1VM,
1741 ("ring-1 code not supported\n"));
1742 /*
1743 * PATM takes care of IOPL and IF flags for Ring-3 and Ring-2 code as well.
1744 */
1745 PATMRawEnter(pVM, pCtxCore);
1746 }
1747
1748 /*
1749 * Assert sanity.
1750 */
1751 AssertMsg((pCtxCore->eflags.u32 & X86_EFL_IF), ("X86_EFL_IF is clear\n"));
1752 AssertReleaseMsg( pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss & X86_SEL_RPL)
1753 || pCtxCore->eflags.Bits.u1VM,
1754 ("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss & X86_SEL_RPL));
1755 Assert((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)) == (X86_CR0_PG | X86_CR0_PE | X86_CR0_WP));
1756 pCtxCore->eflags.u32 |= X86_EFL_IF; /* paranoia */
1757
1758 pVM->cpum.s.fRawEntered = true;
1759 return VINF_SUCCESS;
1760}
1761
1762
1763/**
1764 * Transforms the guest CPU state from raw-ring mode to correct values.
1765 *
1766 * This function will change any selector registers with DPL=1 to DPL=0.
1767 *
1768 * @returns Adjusted rc.
1769 * @param pVCpu The VMCPU handle.
1770 * @param rc Raw mode return code
1771 * @param pCtxCore The context core (for trap usage).
1772 * @see @ref pg_raw
1773 */
1774VMMDECL(int) CPUMRawLeave(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, int rc)
1775{
1776 PVM pVM = pVCpu->CTX_SUFF(pVM);
1777
1778 /*
1779 * Don't leave if we've already left (in GC).
1780 */
1781 Assert(pVM->cpum.s.fRawEntered);
1782 if (!pVM->cpum.s.fRawEntered)
1783 return rc;
1784 pVM->cpum.s.fRawEntered = false;
1785
1786 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1787 if (!pCtxCore)
1788 pCtxCore = CPUMCTX2CORE(pCtx);
1789 Assert(pCtxCore->eflags.Bits.u1VM || (pCtxCore->ss & X86_SEL_RPL));
1790 AssertMsg(pCtxCore->eflags.Bits.u1VM || pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss & X86_SEL_RPL),
1791 ("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss & X86_SEL_RPL));
1792
1793 /*
1794 * Are we executing in raw ring-1?
1795 */
1796 if ( (pCtxCore->ss & X86_SEL_RPL) == 1
1797 && !pCtxCore->eflags.Bits.u1VM)
1798 {
1799 /*
1800 * Leave execution mode.
1801 */
1802 PATMRawLeave(pVM, pCtxCore, rc);
1803 /* Not quite sure if this is really required, but shouldn't harm (too much anyways). */
1804 /** @todo See what happens if we remove this. */
1805 if ((pCtxCore->ds & X86_SEL_RPL) == 1)
1806 pCtxCore->ds &= ~X86_SEL_RPL;
1807 if ((pCtxCore->es & X86_SEL_RPL) == 1)
1808 pCtxCore->es &= ~X86_SEL_RPL;
1809 if ((pCtxCore->fs & X86_SEL_RPL) == 1)
1810 pCtxCore->fs &= ~X86_SEL_RPL;
1811 if ((pCtxCore->gs & X86_SEL_RPL) == 1)
1812 pCtxCore->gs &= ~X86_SEL_RPL;
1813
1814 /*
1815 * Ring-1 selector => Ring-0.
1816 */
1817 pCtxCore->ss &= ~X86_SEL_RPL;
1818 if ((pCtxCore->cs & X86_SEL_RPL) == 1)
1819 pCtxCore->cs &= ~X86_SEL_RPL;
1820 }
1821 else
1822 {
1823 /*
1824 * PATM is taking care of the IOPL and IF flags for us.
1825 */
1826 PATMRawLeave(pVM, pCtxCore, rc);
1827 if (!pCtxCore->eflags.Bits.u1VM)
1828 {
1829 /** @todo See what happens if we remove this. */
1830 if ((pCtxCore->ds & X86_SEL_RPL) == 1)
1831 pCtxCore->ds &= ~X86_SEL_RPL;
1832 if ((pCtxCore->es & X86_SEL_RPL) == 1)
1833 pCtxCore->es &= ~X86_SEL_RPL;
1834 if ((pCtxCore->fs & X86_SEL_RPL) == 1)
1835 pCtxCore->fs &= ~X86_SEL_RPL;
1836 if ((pCtxCore->gs & X86_SEL_RPL) == 1)
1837 pCtxCore->gs &= ~X86_SEL_RPL;
1838 }
1839 }
1840
1841 return rc;
1842}
1843
1844/**
1845 * Updates the EFLAGS while we're in raw-mode.
1846 *
1847 * @param pVCpu The VMCPU handle.
1848 * @param pCtxCore The context core.
1849 * @param eflags The new EFLAGS value.
1850 */
1851VMMDECL(void) CPUMRawSetEFlags(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, uint32_t eflags)
1852{
1853 PVM pVM = pVCpu->CTX_SUFF(pVM);
1854
1855 if (!pVM->cpum.s.fRawEntered)
1856 {
1857 pCtxCore->eflags.u32 = eflags;
1858 return;
1859 }
1860 PATMRawSetEFlags(pVM, pCtxCore, eflags);
1861}
1862
1863#endif /* !IN_RING0 */
1864
1865/**
1866 * Gets the EFLAGS while we're in raw-mode.
1867 *
1868 * @returns The eflags.
1869 * @param pVCpu The VMCPU handle.
1870 * @param pCtxCore The context core.
1871 */
1872VMMDECL(uint32_t) CPUMRawGetEFlags(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
1873{
1874#ifdef IN_RING0
1875 return pCtxCore->eflags.u32;
1876#else
1877 PVM pVM = pVCpu->CTX_SUFF(pVM);
1878
1879 if (!pVM->cpum.s.fRawEntered)
1880 return pCtxCore->eflags.u32;
1881 return PATMRawGetEFlags(pVM, pCtxCore);
1882#endif
1883}
1884
1885
1886/**
1887 * Gets and resets the changed flags (CPUM_CHANGED_*).
1888 * Only REM should call this function.
1889 *
1890 * @returns The changed flags.
1891 * @param pVCpu The VMCPU handle.
1892 */
1893VMMDECL(unsigned) CPUMGetAndClearChangedFlagsREM(PVMCPU pVCpu)
1894{
1895 unsigned fFlags = pVCpu->cpum.s.fChanged;
1896 pVCpu->cpum.s.fChanged = 0;
1897 /** @todo change the switcher to use the fChanged flags. */
1898 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
1899 {
1900 fFlags |= CPUM_CHANGED_FPU_REM;
1901 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
1902 }
1903 return fFlags;
1904}
1905
1906
1907/**
1908 * Sets the specified changed flags (CPUM_CHANGED_*).
1909 *
1910 * @param pVCpu The VMCPU handle.
1911 */
1912VMMDECL(void) CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedFlags)
1913{
1914 pVCpu->cpum.s.fChanged |= fChangedFlags;
1915}
1916
1917
1918/**
1919 * Checks if the CPU supports the FXSAVE and FXRSTOR instruction.
1920 * @returns true if supported.
1921 * @returns false if not supported.
1922 * @param pVM The VM handle.
1923 */
1924VMMDECL(bool) CPUMSupportsFXSR(PVM pVM)
1925{
1926 return pVM->cpum.s.CPUFeatures.edx.u1FXSR != 0;
1927}
1928
1929
1930/**
1931 * Checks if the host OS uses the SYSENTER / SYSEXIT instructions.
1932 * @returns true if used.
1933 * @returns false if not used.
1934 * @param pVM The VM handle.
1935 */
1936VMMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM)
1937{
1938 return (pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSENTER) != 0;
1939}
1940
1941
1942/**
1943 * Checks if the host OS uses the SYSCALL / SYSRET instructions.
1944 * @returns true if used.
1945 * @returns false if not used.
1946 * @param pVM The VM handle.
1947 */
1948VMMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM)
1949{
1950 return (pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSCALL) != 0;
1951}
1952
1953#ifndef IN_RING3
1954
1955/**
1956 * Lazily sync in the FPU/XMM state
1957 *
1958 * @returns VBox status code.
1959 * @param pVCpu VMCPU handle
1960 */
1961VMMDECL(int) CPUMHandleLazyFPU(PVMCPU pVCpu)
1962{
1963 return cpumHandleLazyFPUAsm(&pVCpu->cpum.s);
1964}
1965
1966#endif /* !IN_RING3 */
1967
1968/**
1969 * Checks if we activated the FPU/XMM state of the guest OS
1970 * @returns true if we did.
1971 * @returns false if not.
1972 * @param pVCpu The VMCPU handle.
1973 */
1974VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCpu)
1975{
1976 return (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU) != 0;
1977}
1978
1979
1980/**
1981 * Deactivate the FPU/XMM state of the guest OS
1982 * @param pVCpu The VMCPU handle.
1983 */
1984VMMDECL(void) CPUMDeactivateGuestFPUState(PVMCPU pVCpu)
1985{
1986 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU;
1987}
1988
1989
1990/**
1991 * Checks if the guest debug state is active
1992 *
1993 * @returns boolean
1994 * @param pVM VM handle.
1995 */
1996VMMDECL(bool) CPUMIsGuestDebugStateActive(PVMCPU pVCpu)
1997{
1998 return (pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS) != 0;
1999}
2000
2001/**
2002 * Checks if the hyper debug state is active
2003 *
2004 * @returns boolean
2005 * @param pVM VM handle.
2006 */
2007VMMDECL(bool) CPUMIsHyperDebugStateActive(PVMCPU pVCpu)
2008{
2009 return (pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS_HYPER) != 0;
2010}
2011
2012
2013/**
2014 * Mark the guest's debug state as inactive
2015 *
2016 * @returns boolean
2017 * @param pVM VM handle.
2018 */
2019VMMDECL(void) CPUMDeactivateGuestDebugState(PVMCPU pVCpu)
2020{
2021 pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS;
2022}
2023
2024
2025/**
2026 * Mark the hypervisor's debug state as inactive
2027 *
2028 * @returns boolean
2029 * @param pVM VM handle.
2030 */
2031VMMDECL(void) CPUMDeactivateHyperDebugState(PVMCPU pVCpu)
2032{
2033 pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS_HYPER;
2034}
2035
2036/**
2037 * Checks if the hidden selector registers are valid
2038 * @returns true if they are.
2039 * @returns false if not.
2040 * @param pVM The VM handle.
2041 */
2042VMMDECL(bool) CPUMAreHiddenSelRegsValid(PVM pVM)
2043{
2044 return HWACCMIsEnabled(pVM);
2045}
2046
2047
2048
2049/**
2050 * Get the current privilege level of the guest.
2051 *
2052 * @returns cpl
2053 * @param pVM VM Handle.
2054 * @param pRegFrame Trap register frame.
2055 */
2056VMMDECL(uint32_t) CPUMGetGuestCPL(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
2057{
2058 uint32_t cpl;
2059
2060 if (CPUMAreHiddenSelRegsValid(pVCpu->CTX_SUFF(pVM)))
2061 {
2062 /*
2063 * The hidden CS.DPL register is always equal to the CPL, it is
2064 * not affected by loading a conforming coding segment.
2065 *
2066 * This only seems to apply to AMD-V; in the VT-x case we *do* need to look
2067 * at SS. (ACP2 regression during install after a far call to ring 2)
2068 */
2069 if (RT_LIKELY(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
2070 cpl = pCtxCore->ssHid.Attr.n.u2Dpl;
2071 else
2072 cpl = 0; /* CPL set to 3 for VT-x real-mode emulation. */
2073 }
2074 else if (RT_LIKELY(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
2075 {
2076 if (RT_LIKELY(!pCtxCore->eflags.Bits.u1VM))
2077 {
2078 /*
2079 * The SS RPL is always equal to the CPL, while the CS RPL
2080 * isn't necessarily equal if the segment is conforming.
2081 * See section 4.11.1 in the AMD manual.
2082 */
2083 cpl = (pCtxCore->ss & X86_SEL_RPL);
2084#ifndef IN_RING0
2085 if (cpl == 1)
2086 cpl = 0;
2087#endif
2088 }
2089 else
2090 cpl = 3;
2091 }
2092 else
2093 cpl = 0; /* real mode; cpl is zero */
2094
2095 return cpl;
2096}
2097
2098
2099/**
2100 * Gets the current guest CPU mode.
2101 *
2102 * If paging mode is what you need, check out PGMGetGuestMode().
2103 *
2104 * @returns The CPU mode.
2105 * @param pVCpu The VMCPU handle.
2106 */
2107VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu)
2108{
2109 CPUMMODE enmMode;
2110 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
2111 enmMode = CPUMMODE_REAL;
2112 else if (!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
2113 enmMode = CPUMMODE_PROTECTED;
2114 else
2115 enmMode = CPUMMODE_LONG;
2116
2117 return enmMode;
2118}
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