VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp@ 27489

Last change on this file since 27489 was 27331, checked in by vboxsync, 15 years ago

MSR_IA32_MISC_ENABLE test code
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1/* $Id: CPUMAllRegs.cpp 27331 2010-03-12 14:12:55Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor(/Manager) - Getters and Setters.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_CPUM
27#include <VBox/cpum.h>
28#include <VBox/patm.h>
29#include <VBox/dbgf.h>
30#include <VBox/mm.h>
31#include "CPUMInternal.h"
32#include <VBox/vm.h>
33#include <VBox/err.h>
34#include <VBox/dis.h>
35#include <VBox/log.h>
36#include <VBox/hwaccm.h>
37#include <VBox/tm.h>
38#include <iprt/assert.h>
39#include <iprt/asm.h>
40#ifdef IN_RING3
41#include <iprt/thread.h>
42#endif
43
44/** Disable stack frame pointer generation here. */
45#if defined(_MSC_VER) && !defined(DEBUG)
46# pragma optimize("y", off)
47#endif
48
49
50/**
51 * Sets or resets an alternative hypervisor context core.
52 *
53 * This is called when we get a hypervisor trap set switch the context
54 * core with the trap frame on the stack. It is called again to reset
55 * back to the default context core when resuming hypervisor execution.
56 *
57 * @param pVCpu The VMCPU handle.
58 * @param pCtxCore Pointer to the alternative context core or NULL
59 * to go back to the default context core.
60 */
61VMMDECL(void) CPUMHyperSetCtxCore(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
62{
63 PVM pVM = pVCpu->CTX_SUFF(pVM);
64
65 LogFlow(("CPUMHyperSetCtxCore: %p/%p/%p -> %p\n", pVCpu->cpum.s.CTX_SUFF(pHyperCore), pCtxCore));
66 if (!pCtxCore)
67 {
68 pCtxCore = CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
69 pVCpu->cpum.s.pHyperCoreR3 = (R3PTRTYPE(PCPUMCTXCORE))VM_R3_ADDR(pVM, pCtxCore);
70 pVCpu->cpum.s.pHyperCoreR0 = (R0PTRTYPE(PCPUMCTXCORE))VM_R0_ADDR(pVM, pCtxCore);
71 pVCpu->cpum.s.pHyperCoreRC = (RCPTRTYPE(PCPUMCTXCORE))VM_RC_ADDR(pVM, pCtxCore);
72 }
73 else
74 {
75 pVCpu->cpum.s.pHyperCoreR3 = (R3PTRTYPE(PCPUMCTXCORE))MMHyperCCToR3(pVM, pCtxCore);
76 pVCpu->cpum.s.pHyperCoreR0 = (R0PTRTYPE(PCPUMCTXCORE))MMHyperCCToR0(pVM, pCtxCore);
77 pVCpu->cpum.s.pHyperCoreRC = (RCPTRTYPE(PCPUMCTXCORE))MMHyperCCToRC(pVM, pCtxCore);
78 }
79}
80
81
82/**
83 * Gets the pointer to the internal CPUMCTXCORE structure for the hypervisor.
84 * This is only for reading in order to save a few calls.
85 *
86 * @param pVM Handle to the virtual machine.
87 */
88VMMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVMCPU pVCpu)
89{
90 return pVCpu->cpum.s.CTX_SUFF(pHyperCore);
91}
92
93
94/**
95 * Queries the pointer to the internal CPUMCTX structure for the hypervisor.
96 *
97 * @returns VBox status code.
98 * @param pVM Handle to the virtual machine.
99 * @param ppCtx Receives the hyper CPUMCTX pointer when successful.
100 *
101 * @deprecated This will *not* (and has never) given the right picture of the
102 * hypervisor register state. With CPUMHyperSetCtxCore() this is
103 * getting much worse. So, use the individual functions for getting
104 * and esp. setting the hypervisor registers.
105 */
106VMMDECL(int) CPUMQueryHyperCtxPtr(PVMCPU pVCpu, PCPUMCTX *ppCtx)
107{
108 *ppCtx = &pVCpu->cpum.s.Hyper;
109 return VINF_SUCCESS;
110}
111
112
113VMMDECL(void) CPUMSetHyperGDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
114{
115 pVCpu->cpum.s.Hyper.gdtr.cbGdt = limit;
116 pVCpu->cpum.s.Hyper.gdtr.pGdt = addr;
117 pVCpu->cpum.s.Hyper.gdtrPadding = 0;
118}
119
120
121VMMDECL(void) CPUMSetHyperIDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
122{
123 pVCpu->cpum.s.Hyper.idtr.cbIdt = limit;
124 pVCpu->cpum.s.Hyper.idtr.pIdt = addr;
125 pVCpu->cpum.s.Hyper.idtrPadding = 0;
126}
127
128
129VMMDECL(void) CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3)
130{
131 pVCpu->cpum.s.Hyper.cr3 = cr3;
132
133#ifdef IN_RC
134 /* Update the current CR3. */
135 ASMSetCR3(cr3);
136#endif
137}
138
139VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu)
140{
141 return pVCpu->cpum.s.Hyper.cr3;
142}
143
144
145VMMDECL(void) CPUMSetHyperCS(PVMCPU pVCpu, RTSEL SelCS)
146{
147 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->cs = SelCS;
148}
149
150
151VMMDECL(void) CPUMSetHyperDS(PVMCPU pVCpu, RTSEL SelDS)
152{
153 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ds = SelDS;
154}
155
156
157VMMDECL(void) CPUMSetHyperES(PVMCPU pVCpu, RTSEL SelES)
158{
159 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->es = SelES;
160}
161
162
163VMMDECL(void) CPUMSetHyperFS(PVMCPU pVCpu, RTSEL SelFS)
164{
165 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->fs = SelFS;
166}
167
168
169VMMDECL(void) CPUMSetHyperGS(PVMCPU pVCpu, RTSEL SelGS)
170{
171 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->gs = SelGS;
172}
173
174
175VMMDECL(void) CPUMSetHyperSS(PVMCPU pVCpu, RTSEL SelSS)
176{
177 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ss = SelSS;
178}
179
180
181VMMDECL(void) CPUMSetHyperESP(PVMCPU pVCpu, uint32_t u32ESP)
182{
183 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->esp = u32ESP;
184}
185
186
187VMMDECL(int) CPUMSetHyperEFlags(PVMCPU pVCpu, uint32_t Efl)
188{
189 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->eflags.u32 = Efl;
190 return VINF_SUCCESS;
191}
192
193
194VMMDECL(void) CPUMSetHyperEIP(PVMCPU pVCpu, uint32_t u32EIP)
195{
196 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->eip = u32EIP;
197}
198
199
200VMMDECL(void) CPUMSetHyperTR(PVMCPU pVCpu, RTSEL SelTR)
201{
202 pVCpu->cpum.s.Hyper.tr = SelTR;
203}
204
205
206VMMDECL(void) CPUMSetHyperLDTR(PVMCPU pVCpu, RTSEL SelLDTR)
207{
208 pVCpu->cpum.s.Hyper.ldtr = SelLDTR;
209}
210
211
212VMMDECL(void) CPUMSetHyperDR0(PVMCPU pVCpu, RTGCUINTREG uDr0)
213{
214 pVCpu->cpum.s.Hyper.dr[0] = uDr0;
215 /** @todo in GC we must load it! */
216}
217
218
219VMMDECL(void) CPUMSetHyperDR1(PVMCPU pVCpu, RTGCUINTREG uDr1)
220{
221 pVCpu->cpum.s.Hyper.dr[1] = uDr1;
222 /** @todo in GC we must load it! */
223}
224
225
226VMMDECL(void) CPUMSetHyperDR2(PVMCPU pVCpu, RTGCUINTREG uDr2)
227{
228 pVCpu->cpum.s.Hyper.dr[2] = uDr2;
229 /** @todo in GC we must load it! */
230}
231
232
233VMMDECL(void) CPUMSetHyperDR3(PVMCPU pVCpu, RTGCUINTREG uDr3)
234{
235 pVCpu->cpum.s.Hyper.dr[3] = uDr3;
236 /** @todo in GC we must load it! */
237}
238
239
240VMMDECL(void) CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6)
241{
242 pVCpu->cpum.s.Hyper.dr[6] = uDr6;
243 /** @todo in GC we must load it! */
244}
245
246
247VMMDECL(void) CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7)
248{
249 pVCpu->cpum.s.Hyper.dr[7] = uDr7;
250 /** @todo in GC we must load it! */
251}
252
253
254VMMDECL(RTSEL) CPUMGetHyperCS(PVMCPU pVCpu)
255{
256 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->cs;
257}
258
259
260VMMDECL(RTSEL) CPUMGetHyperDS(PVMCPU pVCpu)
261{
262 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ds;
263}
264
265
266VMMDECL(RTSEL) CPUMGetHyperES(PVMCPU pVCpu)
267{
268 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->es;
269}
270
271
272VMMDECL(RTSEL) CPUMGetHyperFS(PVMCPU pVCpu)
273{
274 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->fs;
275}
276
277
278VMMDECL(RTSEL) CPUMGetHyperGS(PVMCPU pVCpu)
279{
280 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->gs;
281}
282
283
284VMMDECL(RTSEL) CPUMGetHyperSS(PVMCPU pVCpu)
285{
286 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ss;
287}
288
289
290VMMDECL(uint32_t) CPUMGetHyperEAX(PVMCPU pVCpu)
291{
292 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->eax;
293}
294
295
296VMMDECL(uint32_t) CPUMGetHyperEBX(PVMCPU pVCpu)
297{
298 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ebx;
299}
300
301
302VMMDECL(uint32_t) CPUMGetHyperECX(PVMCPU pVCpu)
303{
304 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ecx;
305}
306
307
308VMMDECL(uint32_t) CPUMGetHyperEDX(PVMCPU pVCpu)
309{
310 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->edx;
311}
312
313
314VMMDECL(uint32_t) CPUMGetHyperESI(PVMCPU pVCpu)
315{
316 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->esi;
317}
318
319
320VMMDECL(uint32_t) CPUMGetHyperEDI(PVMCPU pVCpu)
321{
322 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->edi;
323}
324
325
326VMMDECL(uint32_t) CPUMGetHyperEBP(PVMCPU pVCpu)
327{
328 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ebp;
329}
330
331
332VMMDECL(uint32_t) CPUMGetHyperESP(PVMCPU pVCpu)
333{
334 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->esp;
335}
336
337
338VMMDECL(uint32_t) CPUMGetHyperEFlags(PVMCPU pVCpu)
339{
340 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->eflags.u32;
341}
342
343
344VMMDECL(uint32_t) CPUMGetHyperEIP(PVMCPU pVCpu)
345{
346 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->eip;
347}
348
349
350VMMDECL(uint64_t) CPUMGetHyperRIP(PVMCPU pVCpu)
351{
352 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->rip;
353}
354
355
356VMMDECL(uint32_t) CPUMGetHyperIDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
357{
358 if (pcbLimit)
359 *pcbLimit = pVCpu->cpum.s.Hyper.idtr.cbIdt;
360 return pVCpu->cpum.s.Hyper.idtr.pIdt;
361}
362
363
364VMMDECL(uint32_t) CPUMGetHyperGDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
365{
366 if (pcbLimit)
367 *pcbLimit = pVCpu->cpum.s.Hyper.gdtr.cbGdt;
368 return pVCpu->cpum.s.Hyper.gdtr.pGdt;
369}
370
371
372VMMDECL(RTSEL) CPUMGetHyperLDTR(PVMCPU pVCpu)
373{
374 return pVCpu->cpum.s.Hyper.ldtr;
375}
376
377
378VMMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVMCPU pVCpu)
379{
380 return pVCpu->cpum.s.Hyper.dr[0];
381}
382
383
384VMMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVMCPU pVCpu)
385{
386 return pVCpu->cpum.s.Hyper.dr[1];
387}
388
389
390VMMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVMCPU pVCpu)
391{
392 return pVCpu->cpum.s.Hyper.dr[2];
393}
394
395
396VMMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVMCPU pVCpu)
397{
398 return pVCpu->cpum.s.Hyper.dr[3];
399}
400
401
402VMMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVMCPU pVCpu)
403{
404 return pVCpu->cpum.s.Hyper.dr[6];
405}
406
407
408VMMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVMCPU pVCpu)
409{
410 return pVCpu->cpum.s.Hyper.dr[7];
411}
412
413
414/**
415 * Gets the pointer to the internal CPUMCTXCORE structure.
416 * This is only for reading in order to save a few calls.
417 *
418 * @param pVCpu Handle to the virtual cpu.
419 */
420VMMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVMCPU pVCpu)
421{
422 return CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
423}
424
425
426/**
427 * Sets the guest context core registers.
428 *
429 * @param pVCpu Handle to the virtual cpu.
430 * @param pCtxCore The new context core values.
431 */
432VMMDECL(void) CPUMSetGuestCtxCore(PVMCPU pVCpu, PCCPUMCTXCORE pCtxCore)
433{
434 /** @todo #1410 requires selectors to be checked. (huh? 1410?) */
435
436 PCPUMCTXCORE pCtxCoreDst = CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
437 *pCtxCoreDst = *pCtxCore;
438
439 /* Mask away invalid parts of the cpu context. */
440 if (!CPUMIsGuestInLongMode(pVCpu))
441 {
442 uint64_t u64Mask = UINT64_C(0xffffffff);
443
444 pCtxCoreDst->rip &= u64Mask;
445 pCtxCoreDst->rax &= u64Mask;
446 pCtxCoreDst->rbx &= u64Mask;
447 pCtxCoreDst->rcx &= u64Mask;
448 pCtxCoreDst->rdx &= u64Mask;
449 pCtxCoreDst->rsi &= u64Mask;
450 pCtxCoreDst->rdi &= u64Mask;
451 pCtxCoreDst->rbp &= u64Mask;
452 pCtxCoreDst->rsp &= u64Mask;
453 pCtxCoreDst->rflags.u &= u64Mask;
454
455 pCtxCoreDst->r8 = 0;
456 pCtxCoreDst->r9 = 0;
457 pCtxCoreDst->r10 = 0;
458 pCtxCoreDst->r11 = 0;
459 pCtxCoreDst->r12 = 0;
460 pCtxCoreDst->r13 = 0;
461 pCtxCoreDst->r14 = 0;
462 pCtxCoreDst->r15 = 0;
463 }
464}
465
466
467/**
468 * Queries the pointer to the internal CPUMCTX structure
469 *
470 * @returns The CPUMCTX pointer.
471 * @param pVCpu Handle to the virtual cpu.
472 */
473VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu)
474{
475 return &pVCpu->cpum.s.Guest;
476}
477
478VMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
479{
480 pVCpu->cpum.s.Guest.gdtr.cbGdt = limit;
481 pVCpu->cpum.s.Guest.gdtr.pGdt = addr;
482 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GDTR;
483 return VINF_SUCCESS;
484}
485
486VMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
487{
488 pVCpu->cpum.s.Guest.idtr.cbIdt = limit;
489 pVCpu->cpum.s.Guest.idtr.pIdt = addr;
490 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_IDTR;
491 return VINF_SUCCESS;
492}
493
494VMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr)
495{
496 AssertMsgFailed(("Need to load the hidden bits too!\n"));
497
498 pVCpu->cpum.s.Guest.tr = tr;
499 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_TR;
500 return VINF_SUCCESS;
501}
502
503VMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr)
504{
505 pVCpu->cpum.s.Guest.ldtr = ldtr;
506 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_LDTR;
507 return VINF_SUCCESS;
508}
509
510
511/**
512 * Set the guest CR0.
513 *
514 * When called in GC, the hyper CR0 may be updated if that is
515 * required. The caller only has to take special action if AM,
516 * WP, PG or PE changes.
517 *
518 * @returns VINF_SUCCESS (consider it void).
519 * @param pVCpu Handle to the virtual cpu.
520 * @param cr0 The new CR0 value.
521 */
522VMMDECL(int) CPUMSetGuestCR0(PVMCPU pVCpu, uint64_t cr0)
523{
524#ifdef IN_RC
525 /*
526 * Check if we need to change hypervisor CR0 because
527 * of math stuff.
528 */
529 if ( (cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP))
530 != (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP)))
531 {
532 if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU))
533 {
534 /*
535 * We haven't saved the host FPU state yet, so TS and MT are both set
536 * and EM should be reflecting the guest EM (it always does this).
537 */
538 if ((cr0 & X86_CR0_EM) != (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM))
539 {
540 uint32_t HyperCR0 = ASMGetCR0();
541 AssertMsg((HyperCR0 & (X86_CR0_TS | X86_CR0_MP)) == (X86_CR0_TS | X86_CR0_MP), ("%#x\n", HyperCR0));
542 AssertMsg((HyperCR0 & X86_CR0_EM) == (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM), ("%#x\n", HyperCR0));
543 HyperCR0 &= ~X86_CR0_EM;
544 HyperCR0 |= cr0 & X86_CR0_EM;
545 Log(("CPUM New HyperCR0=%#x\n", HyperCR0));
546 ASMSetCR0(HyperCR0);
547 }
548# ifdef VBOX_STRICT
549 else
550 {
551 uint32_t HyperCR0 = ASMGetCR0();
552 AssertMsg((HyperCR0 & (X86_CR0_TS | X86_CR0_MP)) == (X86_CR0_TS | X86_CR0_MP), ("%#x\n", HyperCR0));
553 AssertMsg((HyperCR0 & X86_CR0_EM) == (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM), ("%#x\n", HyperCR0));
554 }
555# endif
556 }
557 else
558 {
559 /*
560 * Already saved the state, so we're just mirroring
561 * the guest flags.
562 */
563 uint32_t HyperCR0 = ASMGetCR0();
564 AssertMsg( (HyperCR0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP))
565 == (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP)),
566 ("%#x %#x\n", HyperCR0, pVCpu->cpum.s.Guest.cr0));
567 HyperCR0 &= ~(X86_CR0_TS | X86_CR0_EM | X86_CR0_MP);
568 HyperCR0 |= cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP);
569 Log(("CPUM New HyperCR0=%#x\n", HyperCR0));
570 ASMSetCR0(HyperCR0);
571 }
572 }
573#endif /* IN_RC */
574
575 /*
576 * Check for changes causing TLB flushes (for REM).
577 * The caller is responsible for calling PGM when appropriate.
578 */
579 if ( (cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE))
580 != (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)))
581 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
582 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR0;
583
584 pVCpu->cpum.s.Guest.cr0 = cr0 | X86_CR0_ET;
585 return VINF_SUCCESS;
586}
587
588
589VMMDECL(int) CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2)
590{
591 pVCpu->cpum.s.Guest.cr2 = cr2;
592 return VINF_SUCCESS;
593}
594
595
596VMMDECL(int) CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3)
597{
598 pVCpu->cpum.s.Guest.cr3 = cr3;
599 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR3;
600 return VINF_SUCCESS;
601}
602
603
604VMMDECL(int) CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4)
605{
606 if ( (cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE))
607 != (pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE)))
608 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
609 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR4;
610 if (!CPUMSupportsFXSR(pVCpu->CTX_SUFF(pVM)))
611 cr4 &= ~X86_CR4_OSFSXR;
612 pVCpu->cpum.s.Guest.cr4 = cr4;
613 return VINF_SUCCESS;
614}
615
616
617VMMDECL(int) CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags)
618{
619 pVCpu->cpum.s.Guest.eflags.u32 = eflags;
620 return VINF_SUCCESS;
621}
622
623
624VMMDECL(int) CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip)
625{
626 pVCpu->cpum.s.Guest.eip = eip;
627 return VINF_SUCCESS;
628}
629
630
631VMMDECL(int) CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax)
632{
633 pVCpu->cpum.s.Guest.eax = eax;
634 return VINF_SUCCESS;
635}
636
637
638VMMDECL(int) CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx)
639{
640 pVCpu->cpum.s.Guest.ebx = ebx;
641 return VINF_SUCCESS;
642}
643
644
645VMMDECL(int) CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx)
646{
647 pVCpu->cpum.s.Guest.ecx = ecx;
648 return VINF_SUCCESS;
649}
650
651
652VMMDECL(int) CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx)
653{
654 pVCpu->cpum.s.Guest.edx = edx;
655 return VINF_SUCCESS;
656}
657
658
659VMMDECL(int) CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp)
660{
661 pVCpu->cpum.s.Guest.esp = esp;
662 return VINF_SUCCESS;
663}
664
665
666VMMDECL(int) CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp)
667{
668 pVCpu->cpum.s.Guest.ebp = ebp;
669 return VINF_SUCCESS;
670}
671
672
673VMMDECL(int) CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi)
674{
675 pVCpu->cpum.s.Guest.esi = esi;
676 return VINF_SUCCESS;
677}
678
679
680VMMDECL(int) CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi)
681{
682 pVCpu->cpum.s.Guest.edi = edi;
683 return VINF_SUCCESS;
684}
685
686
687VMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss)
688{
689 pVCpu->cpum.s.Guest.ss = ss;
690 return VINF_SUCCESS;
691}
692
693
694VMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs)
695{
696 pVCpu->cpum.s.Guest.cs = cs;
697 return VINF_SUCCESS;
698}
699
700
701VMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds)
702{
703 pVCpu->cpum.s.Guest.ds = ds;
704 return VINF_SUCCESS;
705}
706
707
708VMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es)
709{
710 pVCpu->cpum.s.Guest.es = es;
711 return VINF_SUCCESS;
712}
713
714
715VMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs)
716{
717 pVCpu->cpum.s.Guest.fs = fs;
718 return VINF_SUCCESS;
719}
720
721
722VMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs)
723{
724 pVCpu->cpum.s.Guest.gs = gs;
725 return VINF_SUCCESS;
726}
727
728
729VMMDECL(void) CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val)
730{
731 pVCpu->cpum.s.Guest.msrEFER = val;
732}
733
734
735VMMDECL(uint64_t) CPUMGetGuestMsr(PVMCPU pVCpu, unsigned idMsr)
736{
737 uint64_t u64 = 0;
738 uint8_t u8Multiplier = 4;
739
740 switch (idMsr)
741 {
742 case MSR_IA32_TSC:
743 u64 = TMCpuTickGet(pVCpu);
744 break;
745
746 case MSR_IA32_CR_PAT:
747 u64 = pVCpu->cpum.s.Guest.msrPAT;
748 break;
749
750 case MSR_IA32_SYSENTER_CS:
751 u64 = pVCpu->cpum.s.Guest.SysEnter.cs;
752 break;
753
754 case MSR_IA32_SYSENTER_EIP:
755 u64 = pVCpu->cpum.s.Guest.SysEnter.eip;
756 break;
757
758 case MSR_IA32_SYSENTER_ESP:
759 u64 = pVCpu->cpum.s.Guest.SysEnter.esp;
760 break;
761
762 case MSR_K6_EFER:
763 u64 = pVCpu->cpum.s.Guest.msrEFER;
764 break;
765
766 case MSR_K8_SF_MASK:
767 u64 = pVCpu->cpum.s.Guest.msrSFMASK;
768 break;
769
770 case MSR_K6_STAR:
771 u64 = pVCpu->cpum.s.Guest.msrSTAR;
772 break;
773
774 case MSR_K8_LSTAR:
775 u64 = pVCpu->cpum.s.Guest.msrLSTAR;
776 break;
777
778 case MSR_K8_CSTAR:
779 u64 = pVCpu->cpum.s.Guest.msrCSTAR;
780 break;
781
782 case MSR_K8_KERNEL_GS_BASE:
783 u64 = pVCpu->cpum.s.Guest.msrKERNELGSBASE;
784 break;
785
786 case MSR_K8_TSC_AUX:
787 u64 = pVCpu->cpum.s.GuestMsr.msr.tscAux;
788 break;
789
790 case MSR_IA32_PERF_STATUS:
791 /** @todo: could really be not exactly correct, maybe use host's values */
792 /* Keep consistent with helper_rdmsr() in REM */
793 u64 = (1000ULL /* TSC increment by tick */)
794 | ((uint64_t)u8Multiplier << 40 /* CPU multiplier */ );
795 break;
796
797 case MSR_IA32_PLATFORM_INFO:
798 u64 = ((u8Multiplier)<<8 /* Flex ratio max */)
799 | ((uint64_t)u8Multiplier << 40 /* Flex ratio min */ );
800 break;
801
802 case MSR_IA32_MISC_ENABLE:
803#if 0
804 /* Needs to be tested more before enabling. */
805 u64 = pVCpu->cpum.s.GuestMsr.msr.miscEnable;
806#else
807 u64 = 0;
808#endif
809 break;
810
811 /* fs & gs base skipped on purpose as the current context might not be up-to-date. */
812 default:
813 AssertFailed();
814 break;
815 }
816 return u64;
817}
818
819VMMDECL(void) CPUMSetGuestMsr(PVMCPU pVCpu, unsigned idMsr, uint64_t valMsr)
820{
821 /* On purpose only a limited number of MSRs; use the emulation function to update the others. */
822 switch (idMsr)
823 {
824 case MSR_K8_TSC_AUX:
825 pVCpu->cpum.s.GuestMsr.msr.tscAux = valMsr;
826 break;
827
828 case MSR_IA32_MISC_ENABLE:
829 pVCpu->cpum.s.GuestMsr.msr.miscEnable = valMsr;
830 break;
831
832 default:
833 AssertFailed();
834 break;
835 }
836}
837
838VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
839{
840 if (pcbLimit)
841 *pcbLimit = pVCpu->cpum.s.Guest.idtr.cbIdt;
842 return pVCpu->cpum.s.Guest.idtr.pIdt;
843}
844
845
846VMMDECL(RTSEL) CPUMGetGuestTR(PVMCPU pVCpu, PCPUMSELREGHID pHidden)
847{
848 if (pHidden)
849 *pHidden = pVCpu->cpum.s.Guest.trHid;
850 return pVCpu->cpum.s.Guest.tr;
851}
852
853
854VMMDECL(RTSEL) CPUMGetGuestCS(PVMCPU pVCpu)
855{
856 return pVCpu->cpum.s.Guest.cs;
857}
858
859
860VMMDECL(RTSEL) CPUMGetGuestDS(PVMCPU pVCpu)
861{
862 return pVCpu->cpum.s.Guest.ds;
863}
864
865
866VMMDECL(RTSEL) CPUMGetGuestES(PVMCPU pVCpu)
867{
868 return pVCpu->cpum.s.Guest.es;
869}
870
871
872VMMDECL(RTSEL) CPUMGetGuestFS(PVMCPU pVCpu)
873{
874 return pVCpu->cpum.s.Guest.fs;
875}
876
877
878VMMDECL(RTSEL) CPUMGetGuestGS(PVMCPU pVCpu)
879{
880 return pVCpu->cpum.s.Guest.gs;
881}
882
883
884VMMDECL(RTSEL) CPUMGetGuestSS(PVMCPU pVCpu)
885{
886 return pVCpu->cpum.s.Guest.ss;
887}
888
889
890VMMDECL(RTSEL) CPUMGetGuestLDTR(PVMCPU pVCpu)
891{
892 return pVCpu->cpum.s.Guest.ldtr;
893}
894
895
896VMMDECL(uint64_t) CPUMGetGuestCR0(PVMCPU pVCpu)
897{
898 return pVCpu->cpum.s.Guest.cr0;
899}
900
901
902VMMDECL(uint64_t) CPUMGetGuestCR2(PVMCPU pVCpu)
903{
904 return pVCpu->cpum.s.Guest.cr2;
905}
906
907
908VMMDECL(uint64_t) CPUMGetGuestCR3(PVMCPU pVCpu)
909{
910 return pVCpu->cpum.s.Guest.cr3;
911}
912
913
914VMMDECL(uint64_t) CPUMGetGuestCR4(PVMCPU pVCpu)
915{
916 return pVCpu->cpum.s.Guest.cr4;
917}
918
919
920VMMDECL(void) CPUMGetGuestGDTR(PVMCPU pVCpu, PVBOXGDTR pGDTR)
921{
922 *pGDTR = pVCpu->cpum.s.Guest.gdtr;
923}
924
925
926VMMDECL(uint32_t) CPUMGetGuestEIP(PVMCPU pVCpu)
927{
928 return pVCpu->cpum.s.Guest.eip;
929}
930
931
932VMMDECL(uint64_t) CPUMGetGuestRIP(PVMCPU pVCpu)
933{
934 return pVCpu->cpum.s.Guest.rip;
935}
936
937
938VMMDECL(uint32_t) CPUMGetGuestEAX(PVMCPU pVCpu)
939{
940 return pVCpu->cpum.s.Guest.eax;
941}
942
943
944VMMDECL(uint32_t) CPUMGetGuestEBX(PVMCPU pVCpu)
945{
946 return pVCpu->cpum.s.Guest.ebx;
947}
948
949
950VMMDECL(uint32_t) CPUMGetGuestECX(PVMCPU pVCpu)
951{
952 return pVCpu->cpum.s.Guest.ecx;
953}
954
955
956VMMDECL(uint32_t) CPUMGetGuestEDX(PVMCPU pVCpu)
957{
958 return pVCpu->cpum.s.Guest.edx;
959}
960
961
962VMMDECL(uint32_t) CPUMGetGuestESI(PVMCPU pVCpu)
963{
964 return pVCpu->cpum.s.Guest.esi;
965}
966
967
968VMMDECL(uint32_t) CPUMGetGuestEDI(PVMCPU pVCpu)
969{
970 return pVCpu->cpum.s.Guest.edi;
971}
972
973
974VMMDECL(uint32_t) CPUMGetGuestESP(PVMCPU pVCpu)
975{
976 return pVCpu->cpum.s.Guest.esp;
977}
978
979
980VMMDECL(uint32_t) CPUMGetGuestEBP(PVMCPU pVCpu)
981{
982 return pVCpu->cpum.s.Guest.ebp;
983}
984
985
986VMMDECL(uint32_t) CPUMGetGuestEFlags(PVMCPU pVCpu)
987{
988 return pVCpu->cpum.s.Guest.eflags.u32;
989}
990
991
992///@todo: crx should be an array
993VMMDECL(int) CPUMGetGuestCRx(PVMCPU pVCpu, unsigned iReg, uint64_t *pValue)
994{
995 switch (iReg)
996 {
997 case USE_REG_CR0:
998 *pValue = pVCpu->cpum.s.Guest.cr0;
999 break;
1000 case USE_REG_CR2:
1001 *pValue = pVCpu->cpum.s.Guest.cr2;
1002 break;
1003 case USE_REG_CR3:
1004 *pValue = pVCpu->cpum.s.Guest.cr3;
1005 break;
1006 case USE_REG_CR4:
1007 *pValue = pVCpu->cpum.s.Guest.cr4;
1008 break;
1009 default:
1010 return VERR_INVALID_PARAMETER;
1011 }
1012 return VINF_SUCCESS;
1013}
1014
1015
1016VMMDECL(uint64_t) CPUMGetGuestDR0(PVMCPU pVCpu)
1017{
1018 return pVCpu->cpum.s.Guest.dr[0];
1019}
1020
1021
1022VMMDECL(uint64_t) CPUMGetGuestDR1(PVMCPU pVCpu)
1023{
1024 return pVCpu->cpum.s.Guest.dr[1];
1025}
1026
1027
1028VMMDECL(uint64_t) CPUMGetGuestDR2(PVMCPU pVCpu)
1029{
1030 return pVCpu->cpum.s.Guest.dr[2];
1031}
1032
1033
1034VMMDECL(uint64_t) CPUMGetGuestDR3(PVMCPU pVCpu)
1035{
1036 return pVCpu->cpum.s.Guest.dr[3];
1037}
1038
1039
1040VMMDECL(uint64_t) CPUMGetGuestDR6(PVMCPU pVCpu)
1041{
1042 return pVCpu->cpum.s.Guest.dr[6];
1043}
1044
1045
1046VMMDECL(uint64_t) CPUMGetGuestDR7(PVMCPU pVCpu)
1047{
1048 return pVCpu->cpum.s.Guest.dr[7];
1049}
1050
1051
1052VMMDECL(int) CPUMGetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t *pValue)
1053{
1054 AssertReturn(iReg <= USE_REG_DR7, VERR_INVALID_PARAMETER);
1055 /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
1056 if (iReg == 4 || iReg == 5)
1057 iReg += 2;
1058 *pValue = pVCpu->cpum.s.Guest.dr[iReg];
1059 return VINF_SUCCESS;
1060}
1061
1062
1063VMMDECL(uint64_t) CPUMGetGuestEFER(PVMCPU pVCpu)
1064{
1065 return pVCpu->cpum.s.Guest.msrEFER;
1066}
1067
1068
1069/**
1070 * Gets a CpuId leaf.
1071 *
1072 * @param pVCpu The VMCPU handle.
1073 * @param iLeaf The CPUID leaf to get.
1074 * @param pEax Where to store the EAX value.
1075 * @param pEbx Where to store the EBX value.
1076 * @param pEcx Where to store the ECX value.
1077 * @param pEdx Where to store the EDX value.
1078 */
1079VMMDECL(void) CPUMGetGuestCpuId(PVMCPU pVCpu, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx)
1080{
1081 PVM pVM = pVCpu->CTX_SUFF(pVM);
1082
1083 PCCPUMCPUID pCpuId;
1084 if (iLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
1085 pCpuId = &pVM->cpum.s.aGuestCpuIdStd[iLeaf];
1086 else if (iLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
1087 pCpuId = &pVM->cpum.s.aGuestCpuIdExt[iLeaf - UINT32_C(0x80000000)];
1088 else if (iLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
1089 pCpuId = &pVM->cpum.s.aGuestCpuIdCentaur[iLeaf - UINT32_C(0xc0000000)];
1090 else
1091 pCpuId = &pVM->cpum.s.GuestCpuIdDef;
1092
1093 uint32_t cCurrentCacheIndex = *pEcx;
1094
1095 *pEax = pCpuId->eax;
1096 *pEbx = pCpuId->ebx;
1097 *pEcx = pCpuId->ecx;
1098 *pEdx = pCpuId->edx;
1099
1100 if ( iLeaf == 1)
1101 {
1102 /* Bits 31-24: Initial APIC ID */
1103 Assert(pVCpu->idCpu <= 255);
1104 *pEbx |= (pVCpu->idCpu << 24);
1105 }
1106
1107 if ( iLeaf == 4
1108 && cCurrentCacheIndex < 3
1109 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
1110 {
1111 uint32_t type, level, sharing, linesize,
1112 partitions, associativity, sets, cores;
1113
1114 /* For type: 1 - data cache, 2 - i-cache, 3 - unified */
1115 partitions = 1;
1116 /* Those are only to shut up compiler, as they will always
1117 get overwritten, and compiler should be able to figure that out */
1118 sets = associativity = sharing = level = 1;
1119 cores = pVM->cCpus > 32 ? 32 : pVM->cCpus;
1120 switch (cCurrentCacheIndex)
1121 {
1122 case 0:
1123 type = 1;
1124 level = 1;
1125 sharing = 1;
1126 linesize = 64;
1127 associativity = 8;
1128 sets = 64;
1129 break;
1130 case 1:
1131 level = 1;
1132 type = 2;
1133 sharing = 1;
1134 linesize = 64;
1135 associativity = 8;
1136 sets = 64;
1137 break;
1138 default: /* shut up gcc.*/
1139 AssertFailed();
1140 case 2:
1141 level = 2;
1142 type = 3;
1143 sharing = cores; /* our L2 cache is modelled as shared between all cores */
1144 linesize = 64;
1145 associativity = 24;
1146 sets = 4096;
1147 break;
1148 }
1149
1150 *pEax |= ((cores - 1) << 26) |
1151 ((sharing - 1) << 14) |
1152 (level << 5) |
1153 1;
1154 *pEbx = (linesize - 1) |
1155 ((partitions - 1) << 12) |
1156 ((associativity - 1) << 22); /* -1 encoding */
1157 *pEcx = sets - 1;
1158 }
1159
1160 Log2(("CPUMGetGuestCpuId: iLeaf=%#010x %RX32 %RX32 %RX32 %RX32\n", iLeaf, *pEax, *pEbx, *pEcx, *pEdx));
1161}
1162
1163/**
1164 * Gets a number of standard CPUID leafs.
1165 *
1166 * @returns Number of leafs.
1167 * @param pVM The VM handle.
1168 * @remark Intended for PATM.
1169 */
1170VMMDECL(uint32_t) CPUMGetGuestCpuIdStdMax(PVM pVM)
1171{
1172 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd);
1173}
1174
1175
1176/**
1177 * Gets a number of extended CPUID leafs.
1178 *
1179 * @returns Number of leafs.
1180 * @param pVM The VM handle.
1181 * @remark Intended for PATM.
1182 */
1183VMMDECL(uint32_t) CPUMGetGuestCpuIdExtMax(PVM pVM)
1184{
1185 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt);
1186}
1187
1188
1189/**
1190 * Gets a number of centaur CPUID leafs.
1191 *
1192 * @returns Number of leafs.
1193 * @param pVM The VM handle.
1194 * @remark Intended for PATM.
1195 */
1196VMMDECL(uint32_t) CPUMGetGuestCpuIdCentaurMax(PVM pVM)
1197{
1198 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur);
1199}
1200
1201
1202/**
1203 * Sets a CPUID feature bit.
1204 *
1205 * @param pVM The VM Handle.
1206 * @param enmFeature The feature to set.
1207 */
1208VMMDECL(void) CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
1209{
1210 switch (enmFeature)
1211 {
1212 /*
1213 * Set the APIC bit in both feature masks.
1214 */
1215 case CPUMCPUIDFEATURE_APIC:
1216 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1217 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_APIC;
1218 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1219 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1220 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_APIC;
1221 LogRel(("CPUMSetGuestCpuIdFeature: Enabled APIC\n"));
1222 break;
1223
1224 /*
1225 * Set the x2APIC bit in the standard feature mask.
1226 */
1227 case CPUMCPUIDFEATURE_X2APIC:
1228 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1229 pVM->cpum.s.aGuestCpuIdStd[1].ecx |= X86_CPUID_FEATURE_ECX_X2APIC;
1230 LogRel(("CPUMSetGuestCpuIdFeature: Enabled x2APIC\n"));
1231 break;
1232
1233 /*
1234 * Set the sysenter/sysexit bit in the standard feature mask.
1235 * Assumes the caller knows what it's doing! (host must support these)
1236 */
1237 case CPUMCPUIDFEATURE_SEP:
1238 {
1239 if (!(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_SEP))
1240 {
1241 AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
1242 return;
1243 }
1244
1245 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1246 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_SEP;
1247 LogRel(("CPUMSetGuestCpuIdFeature: Enabled sysenter/exit\n"));
1248 break;
1249 }
1250
1251 /*
1252 * Set the syscall/sysret bit in the extended feature mask.
1253 * Assumes the caller knows what it's doing! (host must support these)
1254 */
1255 case CPUMCPUIDFEATURE_SYSCALL:
1256 {
1257 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1258 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_SEP))
1259 {
1260#if HC_ARCH_BITS == 32
1261 /* X86_CPUID_AMD_FEATURE_EDX_SEP not set it seems in 32 bits mode.
1262 * Even when the cpu is capable of doing so in 64 bits mode.
1263 */
1264 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1265 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE)
1266 || !(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_SEP))
1267#endif
1268 {
1269 LogRel(("WARNING: Can't turn on SYSCALL/SYSRET when the host doesn't support it!!\n"));
1270 return;
1271 }
1272 }
1273 /* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
1274 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_SEP;
1275 LogRel(("CPUMSetGuestCpuIdFeature: Enabled syscall/ret\n"));
1276 break;
1277 }
1278
1279 /*
1280 * Set the PAE bit in both feature masks.
1281 * Assumes the caller knows what it's doing! (host must support these)
1282 */
1283 case CPUMCPUIDFEATURE_PAE:
1284 {
1285 if (!(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_PAE))
1286 {
1287 LogRel(("WARNING: Can't turn on PAE when the host doesn't support it!!\n"));
1288 return;
1289 }
1290
1291 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1292 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_PAE;
1293 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1294 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1295 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_PAE;
1296 LogRel(("CPUMSetGuestCpuIdFeature: Enabled PAE\n"));
1297 break;
1298 }
1299
1300 /*
1301 * Set the LONG MODE bit in the extended feature mask.
1302 * Assumes the caller knows what it's doing! (host must support these)
1303 */
1304 case CPUMCPUIDFEATURE_LONG_MODE:
1305 {
1306 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1307 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE))
1308 {
1309 LogRel(("WARNING: Can't turn on LONG MODE when the host doesn't support it!!\n"));
1310 return;
1311 }
1312
1313 /* Valid for both Intel and AMD. */
1314 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_LONG_MODE;
1315 LogRel(("CPUMSetGuestCpuIdFeature: Enabled LONG MODE\n"));
1316 break;
1317 }
1318
1319 /*
1320 * Set the NXE bit in the extended feature mask.
1321 * Assumes the caller knows what it's doing! (host must support these)
1322 */
1323 case CPUMCPUIDFEATURE_NXE:
1324 {
1325 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1326 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_NX))
1327 {
1328 LogRel(("WARNING: Can't turn on NXE when the host doesn't support it!!\n"));
1329 return;
1330 }
1331
1332 /* Valid for both Intel and AMD. */
1333 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_NX;
1334 LogRel(("CPUMSetGuestCpuIdFeature: Enabled NXE\n"));
1335 break;
1336 }
1337
1338 case CPUMCPUIDFEATURE_LAHF:
1339 {
1340 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1341 || !(ASMCpuId_ECX(0x80000001) & X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF))
1342 {
1343 LogRel(("WARNING: Can't turn on LAHF/SAHF when the host doesn't support it!!\n"));
1344 return;
1345 }
1346
1347 pVM->cpum.s.aGuestCpuIdExt[1].ecx |= X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF;
1348 LogRel(("CPUMSetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
1349 break;
1350 }
1351
1352 case CPUMCPUIDFEATURE_PAT:
1353 {
1354 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1355 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_PAT;
1356 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1357 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1358 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_PAT;
1359 LogRel(("CPUMClearGuestCpuIdFeature: Enabled PAT\n"));
1360 break;
1361 }
1362
1363 case CPUMCPUIDFEATURE_RDTSCP:
1364 {
1365 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1366 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_RDTSCP))
1367 {
1368 LogRel(("WARNING: Can't turn on RDTSCP when the host doesn't support it!!\n"));
1369 return;
1370 }
1371
1372 /* Valid for AMD only (for now). */
1373 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_RDTSCP;
1374 LogRel(("CPUMSetGuestCpuIdFeature: Enabled RDTSCP.\n"));
1375 break;
1376 }
1377
1378 default:
1379 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
1380 break;
1381 }
1382 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1383 {
1384 PVMCPU pVCpu = &pVM->aCpus[i];
1385 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CPUID;
1386 }
1387}
1388
1389
1390/**
1391 * Queries a CPUID feature bit.
1392 *
1393 * @returns boolean for feature presence
1394 * @param pVM The VM Handle.
1395 * @param enmFeature The feature to query.
1396 */
1397VMMDECL(bool) CPUMGetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
1398{
1399 switch (enmFeature)
1400 {
1401 case CPUMCPUIDFEATURE_PAE:
1402 {
1403 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1404 return !!(pVM->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PAE);
1405 break;
1406 }
1407
1408 case CPUMCPUIDFEATURE_RDTSCP:
1409 {
1410 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1411 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
1412 break;
1413 }
1414
1415 case CPUMCPUIDFEATURE_LONG_MODE:
1416 {
1417 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1418 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE);
1419 break;
1420 }
1421
1422 default:
1423 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
1424 break;
1425 }
1426 return false;
1427}
1428
1429
1430/**
1431 * Clears a CPUID feature bit.
1432 *
1433 * @param pVM The VM Handle.
1434 * @param enmFeature The feature to clear.
1435 */
1436VMMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
1437{
1438 switch (enmFeature)
1439 {
1440 /*
1441 * Set the APIC bit in both feature masks.
1442 */
1443 case CPUMCPUIDFEATURE_APIC:
1444 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1445 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_APIC;
1446 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1447 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1448 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
1449 Log(("CPUMSetGuestCpuIdFeature: Disabled APIC\n"));
1450 break;
1451
1452 /*
1453 * Clear the x2APIC bit in the standard feature mask.
1454 */
1455 case CPUMCPUIDFEATURE_X2APIC:
1456 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1457 pVM->cpum.s.aGuestCpuIdStd[1].ecx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
1458 LogRel(("CPUMSetGuestCpuIdFeature: Disabled x2APIC\n"));
1459 break;
1460
1461 case CPUMCPUIDFEATURE_PAE:
1462 {
1463 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1464 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_PAE;
1465 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1466 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1467 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
1468 LogRel(("CPUMClearGuestCpuIdFeature: Disabled PAE!\n"));
1469 break;
1470 }
1471
1472 case CPUMCPUIDFEATURE_PAT:
1473 {
1474 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1475 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_PAT;
1476 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1477 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1478 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_PAT;
1479 LogRel(("CPUMClearGuestCpuIdFeature: Disabled PAT!\n"));
1480 break;
1481 }
1482
1483 case CPUMCPUIDFEATURE_LONG_MODE:
1484 {
1485 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1486 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_LONG_MODE;
1487 break;
1488 }
1489
1490 case CPUMCPUIDFEATURE_LAHF:
1491 {
1492 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1493 pVM->cpum.s.aGuestCpuIdExt[1].ecx &= ~X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF;
1494 break;
1495 }
1496
1497 default:
1498 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
1499 break;
1500 }
1501 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1502 {
1503 PVMCPU pVCpu = &pVM->aCpus[i];
1504 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CPUID;
1505 }
1506}
1507
1508
1509/**
1510 * Gets the host CPU vendor
1511 *
1512 * @returns CPU vendor
1513 * @param pVM The VM handle.
1514 */
1515VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM)
1516{
1517 return pVM->cpum.s.enmHostCpuVendor;
1518}
1519
1520/**
1521 * Gets the CPU vendor
1522 *
1523 * @returns CPU vendor
1524 * @param pVM The VM handle.
1525 */
1526VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM)
1527{
1528 return pVM->cpum.s.enmGuestCpuVendor;
1529}
1530
1531
1532VMMDECL(int) CPUMSetGuestDR0(PVMCPU pVCpu, uint64_t uDr0)
1533{
1534 pVCpu->cpum.s.Guest.dr[0] = uDr0;
1535 return CPUMRecalcHyperDRx(pVCpu);
1536}
1537
1538
1539VMMDECL(int) CPUMSetGuestDR1(PVMCPU pVCpu, uint64_t uDr1)
1540{
1541 pVCpu->cpum.s.Guest.dr[1] = uDr1;
1542 return CPUMRecalcHyperDRx(pVCpu);
1543}
1544
1545
1546VMMDECL(int) CPUMSetGuestDR2(PVMCPU pVCpu, uint64_t uDr2)
1547{
1548 pVCpu->cpum.s.Guest.dr[2] = uDr2;
1549 return CPUMRecalcHyperDRx(pVCpu);
1550}
1551
1552
1553VMMDECL(int) CPUMSetGuestDR3(PVMCPU pVCpu, uint64_t uDr3)
1554{
1555 pVCpu->cpum.s.Guest.dr[3] = uDr3;
1556 return CPUMRecalcHyperDRx(pVCpu);
1557}
1558
1559
1560VMMDECL(int) CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6)
1561{
1562 pVCpu->cpum.s.Guest.dr[6] = uDr6;
1563 return CPUMRecalcHyperDRx(pVCpu);
1564}
1565
1566
1567VMMDECL(int) CPUMSetGuestDR7(PVMCPU pVCpu, uint64_t uDr7)
1568{
1569 pVCpu->cpum.s.Guest.dr[7] = uDr7;
1570 return CPUMRecalcHyperDRx(pVCpu);
1571}
1572
1573
1574VMMDECL(int) CPUMSetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t Value)
1575{
1576 AssertReturn(iReg <= USE_REG_DR7, VERR_INVALID_PARAMETER);
1577 /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
1578 if (iReg == 4 || iReg == 5)
1579 iReg += 2;
1580 pVCpu->cpum.s.Guest.dr[iReg] = Value;
1581 return CPUMRecalcHyperDRx(pVCpu);
1582}
1583
1584
1585/**
1586 * Recalculates the hypvervisor DRx register values based on
1587 * current guest registers and DBGF breakpoints.
1588 *
1589 * This is called whenever a guest DRx register is modified and when DBGF
1590 * sets a hardware breakpoint. In guest context this function will reload
1591 * any (hyper) DRx registers which comes out with a different value.
1592 *
1593 * @returns VINF_SUCCESS.
1594 * @param pVCpu The VMCPU handle.
1595 */
1596VMMDECL(int) CPUMRecalcHyperDRx(PVMCPU pVCpu)
1597{
1598 PVM pVM = pVCpu->CTX_SUFF(pVM);
1599
1600 /*
1601 * Compare the DR7s first.
1602 *
1603 * We only care about the enabled flags. The GE and LE flags are always
1604 * set and we don't care if the guest doesn't set them. GD is virtualized
1605 * when we dispatch #DB, we never enable it.
1606 */
1607 const RTGCUINTREG uDbgfDr7 = DBGFBpGetDR7(pVM);
1608#ifdef CPUM_VIRTUALIZE_DRX
1609 const RTGCUINTREG uGstDr7 = CPUMGetGuestDR7(pVCpu);
1610#else
1611 const RTGCUINTREG uGstDr7 = 0;
1612#endif
1613 if ((uGstDr7 | uDbgfDr7) & X86_DR7_ENABLED_MASK)
1614 {
1615 /*
1616 * Ok, something is enabled. Recalc each of the breakpoints.
1617 * Straight forward code, not optimized/minimized in any way.
1618 */
1619 RTGCUINTREG uNewDr7 = X86_DR7_GE | X86_DR7_LE | X86_DR7_MB1_MASK;
1620
1621 /* bp 0 */
1622 RTGCUINTREG uNewDr0;
1623 if (uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0))
1624 {
1625 uNewDr7 |= uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
1626 uNewDr0 = DBGFBpGetDR0(pVM);
1627 }
1628 else if (uGstDr7 & (X86_DR7_L0 | X86_DR7_G0))
1629 {
1630 uNewDr7 |= uGstDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
1631 uNewDr0 = CPUMGetGuestDR0(pVCpu);
1632 }
1633 else
1634 uNewDr0 = pVCpu->cpum.s.Hyper.dr[0];
1635
1636 /* bp 1 */
1637 RTGCUINTREG uNewDr1;
1638 if (uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1))
1639 {
1640 uNewDr7 |= uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
1641 uNewDr1 = DBGFBpGetDR1(pVM);
1642 }
1643 else if (uGstDr7 & (X86_DR7_L1 | X86_DR7_G1))
1644 {
1645 uNewDr7 |= uGstDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
1646 uNewDr1 = CPUMGetGuestDR1(pVCpu);
1647 }
1648 else
1649 uNewDr1 = pVCpu->cpum.s.Hyper.dr[1];
1650
1651 /* bp 2 */
1652 RTGCUINTREG uNewDr2;
1653 if (uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2))
1654 {
1655 uNewDr7 |= uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
1656 uNewDr2 = DBGFBpGetDR2(pVM);
1657 }
1658 else if (uGstDr7 & (X86_DR7_L2 | X86_DR7_G2))
1659 {
1660 uNewDr7 |= uGstDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
1661 uNewDr2 = CPUMGetGuestDR2(pVCpu);
1662 }
1663 else
1664 uNewDr2 = pVCpu->cpum.s.Hyper.dr[2];
1665
1666 /* bp 3 */
1667 RTGCUINTREG uNewDr3;
1668 if (uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3))
1669 {
1670 uNewDr7 |= uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
1671 uNewDr3 = DBGFBpGetDR3(pVM);
1672 }
1673 else if (uGstDr7 & (X86_DR7_L3 | X86_DR7_G3))
1674 {
1675 uNewDr7 |= uGstDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
1676 uNewDr3 = CPUMGetGuestDR3(pVCpu);
1677 }
1678 else
1679 uNewDr3 = pVCpu->cpum.s.Hyper.dr[3];
1680
1681 /*
1682 * Apply the updates.
1683 */
1684#ifdef IN_RC
1685 if (!(pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS))
1686 {
1687 /** @todo save host DBx registers. */
1688 }
1689#endif
1690 pVCpu->cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS;
1691 if (uNewDr3 != pVCpu->cpum.s.Hyper.dr[3])
1692 CPUMSetHyperDR3(pVCpu, uNewDr3);
1693 if (uNewDr2 != pVCpu->cpum.s.Hyper.dr[2])
1694 CPUMSetHyperDR2(pVCpu, uNewDr2);
1695 if (uNewDr1 != pVCpu->cpum.s.Hyper.dr[1])
1696 CPUMSetHyperDR1(pVCpu, uNewDr1);
1697 if (uNewDr0 != pVCpu->cpum.s.Hyper.dr[0])
1698 CPUMSetHyperDR0(pVCpu, uNewDr0);
1699 if (uNewDr7 != pVCpu->cpum.s.Hyper.dr[7])
1700 CPUMSetHyperDR7(pVCpu, uNewDr7);
1701 }
1702 else
1703 {
1704#ifdef IN_RC
1705 if (pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS)
1706 {
1707 /** @todo restore host DBx registers. */
1708 }
1709#endif
1710 pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS;
1711 }
1712 Log2(("CPUMRecalcHyperDRx: fUseFlags=%#x %RGr %RGr %RGr %RGr %RGr %RGr\n",
1713 pVCpu->cpum.s.fUseFlags, pVCpu->cpum.s.Hyper.dr[0], pVCpu->cpum.s.Hyper.dr[1],
1714 pVCpu->cpum.s.Hyper.dr[2], pVCpu->cpum.s.Hyper.dr[3], pVCpu->cpum.s.Hyper.dr[6],
1715 pVCpu->cpum.s.Hyper.dr[7]));
1716
1717 return VINF_SUCCESS;
1718}
1719
1720
1721/**
1722 * Tests if the guest has No-Execute Page Protection Enabled (NXE).
1723 *
1724 * @returns true if in real mode, otherwise false.
1725 * @param pVCpu The virtual CPU handle.
1726 */
1727VMMDECL(bool) CPUMIsGuestNXEnabled(PVMCPU pVCpu)
1728{
1729 return !!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE);
1730}
1731
1732
1733/**
1734 * Tests if the guest has the Page Size Extension enabled (PSE).
1735 *
1736 * @returns true if in real mode, otherwise false.
1737 * @param pVCpu The virtual CPU handle.
1738 */
1739VMMDECL(bool) CPUMIsGuestPageSizeExtEnabled(PVMCPU pVCpu)
1740{
1741 /* PAE or AMD64 implies support for big pages regardless of CR4.PSE */
1742 return !!(pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PSE | X86_CR4_PAE));
1743}
1744
1745
1746/**
1747 * Tests if the guest has the paging enabled (PG).
1748 *
1749 * @returns true if in real mode, otherwise false.
1750 * @param pVCpu The virtual CPU handle.
1751 */
1752VMMDECL(bool) CPUMIsGuestPagingEnabled(PVMCPU pVCpu)
1753{
1754 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG);
1755}
1756
1757
1758/**
1759 * Tests if the guest has the paging enabled (PG).
1760 *
1761 * @returns true if in real mode, otherwise false.
1762 * @param pVCpu The virtual CPU handle.
1763 */
1764VMMDECL(bool) CPUMIsGuestR0WriteProtEnabled(PVMCPU pVCpu)
1765{
1766 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_WP);
1767}
1768
1769
1770/**
1771 * Tests if the guest is running in real mode or not.
1772 *
1773 * @returns true if in real mode, otherwise false.
1774 * @param pVCpu The virtual CPU handle.
1775 */
1776VMMDECL(bool) CPUMIsGuestInRealMode(PVMCPU pVCpu)
1777{
1778 return !(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
1779}
1780
1781
1782/**
1783 * Tests if the guest is running in protected or not.
1784 *
1785 * @returns true if in protected mode, otherwise false.
1786 * @param pVCpu The virtual CPU handle.
1787 */
1788VMMDECL(bool) CPUMIsGuestInProtectedMode(PVMCPU pVCpu)
1789{
1790 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
1791}
1792
1793
1794/**
1795 * Tests if the guest is running in paged protected or not.
1796 *
1797 * @returns true if in paged protected mode, otherwise false.
1798 * @param pVCpu The virtual CPU handle.
1799 */
1800VMMDECL(bool) CPUMIsGuestInPagedProtectedMode(PVMCPU pVCpu)
1801{
1802 return (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
1803}
1804
1805
1806/**
1807 * Tests if the guest is running in long mode or not.
1808 *
1809 * @returns true if in long mode, otherwise false.
1810 * @param pVCpu The virtual CPU handle.
1811 */
1812VMMDECL(bool) CPUMIsGuestInLongMode(PVMCPU pVCpu)
1813{
1814 return (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
1815}
1816
1817
1818/**
1819 * Tests if the guest is running in PAE mode or not.
1820 *
1821 * @returns true if in PAE mode, otherwise false.
1822 * @param pVCpu The virtual CPU handle.
1823 */
1824VMMDECL(bool) CPUMIsGuestInPAEMode(PVMCPU pVCpu)
1825{
1826 return (pVCpu->cpum.s.Guest.cr4 & X86_CR4_PAE)
1827 && (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG)
1828 && !(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA);
1829}
1830
1831
1832
1833#ifndef IN_RING0 /** @todo I don't think we need this in R0, so move it to CPUMAll.cpp? */
1834
1835/**
1836 * Transforms the guest CPU state to raw-ring mode.
1837 *
1838 * This function will change the any of the cs and ss register with DPL=0 to DPL=1.
1839 *
1840 * @returns VBox status. (recompiler failure)
1841 * @param pVCpu The VMCPU handle.
1842 * @param pCtxCore The context core (for trap usage).
1843 * @see @ref pg_raw
1844 */
1845VMMDECL(int) CPUMRawEnter(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
1846{
1847 PVM pVM = pVCpu->CTX_SUFF(pVM);
1848
1849 Assert(!pVM->cpum.s.fRawEntered);
1850 if (!pCtxCore)
1851 pCtxCore = CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
1852
1853 /*
1854 * Are we in Ring-0?
1855 */
1856 if ( pCtxCore->ss && (pCtxCore->ss & X86_SEL_RPL) == 0
1857 && !pCtxCore->eflags.Bits.u1VM)
1858 {
1859 /*
1860 * Enter execution mode.
1861 */
1862 PATMRawEnter(pVM, pCtxCore);
1863
1864 /*
1865 * Set CPL to Ring-1.
1866 */
1867 pCtxCore->ss |= 1;
1868 if (pCtxCore->cs && (pCtxCore->cs & X86_SEL_RPL) == 0)
1869 pCtxCore->cs |= 1;
1870 }
1871 else
1872 {
1873 AssertMsg((pCtxCore->ss & X86_SEL_RPL) >= 2 || pCtxCore->eflags.Bits.u1VM,
1874 ("ring-1 code not supported\n"));
1875 /*
1876 * PATM takes care of IOPL and IF flags for Ring-3 and Ring-2 code as well.
1877 */
1878 PATMRawEnter(pVM, pCtxCore);
1879 }
1880
1881 /*
1882 * Assert sanity.
1883 */
1884 AssertMsg((pCtxCore->eflags.u32 & X86_EFL_IF), ("X86_EFL_IF is clear\n"));
1885 AssertReleaseMsg( pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss & X86_SEL_RPL)
1886 || pCtxCore->eflags.Bits.u1VM,
1887 ("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss & X86_SEL_RPL));
1888 Assert((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)) == (X86_CR0_PG | X86_CR0_PE | X86_CR0_WP));
1889 pCtxCore->eflags.u32 |= X86_EFL_IF; /* paranoia */
1890
1891 pVM->cpum.s.fRawEntered = true;
1892 return VINF_SUCCESS;
1893}
1894
1895
1896/**
1897 * Transforms the guest CPU state from raw-ring mode to correct values.
1898 *
1899 * This function will change any selector registers with DPL=1 to DPL=0.
1900 *
1901 * @returns Adjusted rc.
1902 * @param pVCpu The VMCPU handle.
1903 * @param rc Raw mode return code
1904 * @param pCtxCore The context core (for trap usage).
1905 * @see @ref pg_raw
1906 */
1907VMMDECL(int) CPUMRawLeave(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, int rc)
1908{
1909 PVM pVM = pVCpu->CTX_SUFF(pVM);
1910
1911 /*
1912 * Don't leave if we've already left (in GC).
1913 */
1914 Assert(pVM->cpum.s.fRawEntered);
1915 if (!pVM->cpum.s.fRawEntered)
1916 return rc;
1917 pVM->cpum.s.fRawEntered = false;
1918
1919 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1920 if (!pCtxCore)
1921 pCtxCore = CPUMCTX2CORE(pCtx);
1922 Assert(pCtxCore->eflags.Bits.u1VM || (pCtxCore->ss & X86_SEL_RPL));
1923 AssertMsg(pCtxCore->eflags.Bits.u1VM || pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss & X86_SEL_RPL),
1924 ("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss & X86_SEL_RPL));
1925
1926 /*
1927 * Are we executing in raw ring-1?
1928 */
1929 if ( (pCtxCore->ss & X86_SEL_RPL) == 1
1930 && !pCtxCore->eflags.Bits.u1VM)
1931 {
1932 /*
1933 * Leave execution mode.
1934 */
1935 PATMRawLeave(pVM, pCtxCore, rc);
1936 /* Not quite sure if this is really required, but shouldn't harm (too much anyways). */
1937 /** @todo See what happens if we remove this. */
1938 if ((pCtxCore->ds & X86_SEL_RPL) == 1)
1939 pCtxCore->ds &= ~X86_SEL_RPL;
1940 if ((pCtxCore->es & X86_SEL_RPL) == 1)
1941 pCtxCore->es &= ~X86_SEL_RPL;
1942 if ((pCtxCore->fs & X86_SEL_RPL) == 1)
1943 pCtxCore->fs &= ~X86_SEL_RPL;
1944 if ((pCtxCore->gs & X86_SEL_RPL) == 1)
1945 pCtxCore->gs &= ~X86_SEL_RPL;
1946
1947 /*
1948 * Ring-1 selector => Ring-0.
1949 */
1950 pCtxCore->ss &= ~X86_SEL_RPL;
1951 if ((pCtxCore->cs & X86_SEL_RPL) == 1)
1952 pCtxCore->cs &= ~X86_SEL_RPL;
1953 }
1954 else
1955 {
1956 /*
1957 * PATM is taking care of the IOPL and IF flags for us.
1958 */
1959 PATMRawLeave(pVM, pCtxCore, rc);
1960 if (!pCtxCore->eflags.Bits.u1VM)
1961 {
1962 /** @todo See what happens if we remove this. */
1963 if ((pCtxCore->ds & X86_SEL_RPL) == 1)
1964 pCtxCore->ds &= ~X86_SEL_RPL;
1965 if ((pCtxCore->es & X86_SEL_RPL) == 1)
1966 pCtxCore->es &= ~X86_SEL_RPL;
1967 if ((pCtxCore->fs & X86_SEL_RPL) == 1)
1968 pCtxCore->fs &= ~X86_SEL_RPL;
1969 if ((pCtxCore->gs & X86_SEL_RPL) == 1)
1970 pCtxCore->gs &= ~X86_SEL_RPL;
1971 }
1972 }
1973
1974 return rc;
1975}
1976
1977/**
1978 * Updates the EFLAGS while we're in raw-mode.
1979 *
1980 * @param pVCpu The VMCPU handle.
1981 * @param pCtxCore The context core.
1982 * @param eflags The new EFLAGS value.
1983 */
1984VMMDECL(void) CPUMRawSetEFlags(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, uint32_t eflags)
1985{
1986 PVM pVM = pVCpu->CTX_SUFF(pVM);
1987
1988 if (!pVM->cpum.s.fRawEntered)
1989 {
1990 pCtxCore->eflags.u32 = eflags;
1991 return;
1992 }
1993 PATMRawSetEFlags(pVM, pCtxCore, eflags);
1994}
1995
1996#endif /* !IN_RING0 */
1997
1998/**
1999 * Gets the EFLAGS while we're in raw-mode.
2000 *
2001 * @returns The eflags.
2002 * @param pVCpu The VMCPU handle.
2003 * @param pCtxCore The context core.
2004 */
2005VMMDECL(uint32_t) CPUMRawGetEFlags(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
2006{
2007#ifdef IN_RING0
2008 return pCtxCore->eflags.u32;
2009#else
2010 PVM pVM = pVCpu->CTX_SUFF(pVM);
2011
2012 if (!pVM->cpum.s.fRawEntered)
2013 return pCtxCore->eflags.u32;
2014 return PATMRawGetEFlags(pVM, pCtxCore);
2015#endif
2016}
2017
2018
2019/**
2020 * Gets and resets the changed flags (CPUM_CHANGED_*).
2021 * Only REM should call this function.
2022 *
2023 * @returns The changed flags.
2024 * @param pVCpu The VMCPU handle.
2025 */
2026VMMDECL(unsigned) CPUMGetAndClearChangedFlagsREM(PVMCPU pVCpu)
2027{
2028 unsigned fFlags = pVCpu->cpum.s.fChanged;
2029 pVCpu->cpum.s.fChanged = 0;
2030 /** @todo change the switcher to use the fChanged flags. */
2031 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
2032 {
2033 fFlags |= CPUM_CHANGED_FPU_REM;
2034 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
2035 }
2036 return fFlags;
2037}
2038
2039
2040/**
2041 * Sets the specified changed flags (CPUM_CHANGED_*).
2042 *
2043 * @param pVCpu The VMCPU handle.
2044 */
2045VMMDECL(void) CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedFlags)
2046{
2047 pVCpu->cpum.s.fChanged |= fChangedFlags;
2048}
2049
2050
2051/**
2052 * Checks if the CPU supports the FXSAVE and FXRSTOR instruction.
2053 * @returns true if supported.
2054 * @returns false if not supported.
2055 * @param pVM The VM handle.
2056 */
2057VMMDECL(bool) CPUMSupportsFXSR(PVM pVM)
2058{
2059 return pVM->cpum.s.CPUFeatures.edx.u1FXSR != 0;
2060}
2061
2062
2063/**
2064 * Checks if the host OS uses the SYSENTER / SYSEXIT instructions.
2065 * @returns true if used.
2066 * @returns false if not used.
2067 * @param pVM The VM handle.
2068 */
2069VMMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM)
2070{
2071 return (pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSENTER) != 0;
2072}
2073
2074
2075/**
2076 * Checks if the host OS uses the SYSCALL / SYSRET instructions.
2077 * @returns true if used.
2078 * @returns false if not used.
2079 * @param pVM The VM handle.
2080 */
2081VMMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM)
2082{
2083 return (pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSCALL) != 0;
2084}
2085
2086#ifndef IN_RING3
2087
2088/**
2089 * Lazily sync in the FPU/XMM state
2090 *
2091 * @returns VBox status code.
2092 * @param pVCpu VMCPU handle
2093 */
2094VMMDECL(int) CPUMHandleLazyFPU(PVMCPU pVCpu)
2095{
2096 return cpumHandleLazyFPUAsm(&pVCpu->cpum.s);
2097}
2098
2099#endif /* !IN_RING3 */
2100
2101/**
2102 * Checks if we activated the FPU/XMM state of the guest OS
2103 * @returns true if we did.
2104 * @returns false if not.
2105 * @param pVCpu The VMCPU handle.
2106 */
2107VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCpu)
2108{
2109 return (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU) != 0;
2110}
2111
2112
2113/**
2114 * Deactivate the FPU/XMM state of the guest OS
2115 * @param pVCpu The VMCPU handle.
2116 */
2117VMMDECL(void) CPUMDeactivateGuestFPUState(PVMCPU pVCpu)
2118{
2119 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU;
2120}
2121
2122
2123/**
2124 * Checks if the guest debug state is active
2125 *
2126 * @returns boolean
2127 * @param pVM VM handle.
2128 */
2129VMMDECL(bool) CPUMIsGuestDebugStateActive(PVMCPU pVCpu)
2130{
2131 return (pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS) != 0;
2132}
2133
2134/**
2135 * Checks if the hyper debug state is active
2136 *
2137 * @returns boolean
2138 * @param pVM VM handle.
2139 */
2140VMMDECL(bool) CPUMIsHyperDebugStateActive(PVMCPU pVCpu)
2141{
2142 return (pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS_HYPER) != 0;
2143}
2144
2145
2146/**
2147 * Mark the guest's debug state as inactive
2148 *
2149 * @returns boolean
2150 * @param pVM VM handle.
2151 */
2152VMMDECL(void) CPUMDeactivateGuestDebugState(PVMCPU pVCpu)
2153{
2154 pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS;
2155}
2156
2157
2158/**
2159 * Mark the hypervisor's debug state as inactive
2160 *
2161 * @returns boolean
2162 * @param pVM VM handle.
2163 */
2164VMMDECL(void) CPUMDeactivateHyperDebugState(PVMCPU pVCpu)
2165{
2166 pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS_HYPER;
2167}
2168
2169/**
2170 * Checks if the hidden selector registers are valid
2171 * @returns true if they are.
2172 * @returns false if not.
2173 * @param pVM The VM handle.
2174 */
2175VMMDECL(bool) CPUMAreHiddenSelRegsValid(PVM pVM)
2176{
2177 return HWACCMIsEnabled(pVM);
2178}
2179
2180
2181
2182/**
2183 * Get the current privilege level of the guest.
2184 *
2185 * @returns cpl
2186 * @param pVM VM Handle.
2187 * @param pRegFrame Trap register frame.
2188 */
2189VMMDECL(uint32_t) CPUMGetGuestCPL(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
2190{
2191 uint32_t cpl;
2192
2193 if (CPUMAreHiddenSelRegsValid(pVCpu->CTX_SUFF(pVM)))
2194 {
2195 /*
2196 * The hidden CS.DPL register is always equal to the CPL, it is
2197 * not affected by loading a conforming coding segment.
2198 *
2199 * This only seems to apply to AMD-V; in the VT-x case we *do* need to look
2200 * at SS. (ACP2 regression during install after a far call to ring 2)
2201 */
2202 if (RT_LIKELY(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
2203 cpl = pCtxCore->ssHid.Attr.n.u2Dpl;
2204 else
2205 cpl = 0; /* CPL set to 3 for VT-x real-mode emulation. */
2206 }
2207 else if (RT_LIKELY(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
2208 {
2209 if (RT_LIKELY(!pCtxCore->eflags.Bits.u1VM))
2210 {
2211 /*
2212 * The SS RPL is always equal to the CPL, while the CS RPL
2213 * isn't necessarily equal if the segment is conforming.
2214 * See section 4.11.1 in the AMD manual.
2215 */
2216 cpl = (pCtxCore->ss & X86_SEL_RPL);
2217#ifndef IN_RING0
2218 if (cpl == 1)
2219 cpl = 0;
2220#endif
2221 }
2222 else
2223 cpl = 3;
2224 }
2225 else
2226 cpl = 0; /* real mode; cpl is zero */
2227
2228 return cpl;
2229}
2230
2231
2232/**
2233 * Gets the current guest CPU mode.
2234 *
2235 * If paging mode is what you need, check out PGMGetGuestMode().
2236 *
2237 * @returns The CPU mode.
2238 * @param pVCpu The VMCPU handle.
2239 */
2240VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu)
2241{
2242 CPUMMODE enmMode;
2243 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
2244 enmMode = CPUMMODE_REAL;
2245 else if (!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
2246 enmMode = CPUMMODE_PROTECTED;
2247 else
2248 enmMode = CPUMMODE_LONG;
2249
2250 return enmMode;
2251}
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