VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp@ 32963

Last change on this file since 32963 was 31512, checked in by vboxsync, 14 years ago

CPUMGetGuestCPL: Don't trust ssHid.Attr.n.u2Dpl to hold the CPL when we're in V8086 mode (REM).
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1/* $Id: CPUMAllRegs.cpp 31512 2010-08-10 09:06:28Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor(/Manager) - Getters and Setters.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_CPUM
23#include <VBox/cpum.h>
24#include <VBox/patm.h>
25#include <VBox/dbgf.h>
26#include <VBox/pdm.h>
27#include <VBox/pgm.h>
28#include <VBox/mm.h>
29#include "CPUMInternal.h"
30#include <VBox/vm.h>
31#include <VBox/err.h>
32#include <VBox/dis.h>
33#include <VBox/log.h>
34#include <VBox/hwaccm.h>
35#include <VBox/tm.h>
36#include <iprt/assert.h>
37#include <iprt/asm.h>
38#include <iprt/asm-amd64-x86.h>
39#ifdef IN_RING3
40#include <iprt/thread.h>
41#endif
42
43/** Disable stack frame pointer generation here. */
44#if defined(_MSC_VER) && !defined(DEBUG)
45# pragma optimize("y", off)
46#endif
47
48
49/**
50 * Sets or resets an alternative hypervisor context core.
51 *
52 * This is called when we get a hypervisor trap set switch the context
53 * core with the trap frame on the stack. It is called again to reset
54 * back to the default context core when resuming hypervisor execution.
55 *
56 * @param pVCpu The VMCPU handle.
57 * @param pCtxCore Pointer to the alternative context core or NULL
58 * to go back to the default context core.
59 */
60VMMDECL(void) CPUMHyperSetCtxCore(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
61{
62 PVM pVM = pVCpu->CTX_SUFF(pVM);
63
64 LogFlow(("CPUMHyperSetCtxCore: %p/%p/%p -> %p\n", pVCpu->cpum.s.CTX_SUFF(pHyperCore), pCtxCore));
65 if (!pCtxCore)
66 {
67 pCtxCore = CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
68 pVCpu->cpum.s.pHyperCoreR3 = (R3PTRTYPE(PCPUMCTXCORE))VM_R3_ADDR(pVM, pCtxCore);
69 pVCpu->cpum.s.pHyperCoreR0 = (R0PTRTYPE(PCPUMCTXCORE))VM_R0_ADDR(pVM, pCtxCore);
70 pVCpu->cpum.s.pHyperCoreRC = (RCPTRTYPE(PCPUMCTXCORE))VM_RC_ADDR(pVM, pCtxCore);
71 }
72 else
73 {
74 pVCpu->cpum.s.pHyperCoreR3 = (R3PTRTYPE(PCPUMCTXCORE))MMHyperCCToR3(pVM, pCtxCore);
75 pVCpu->cpum.s.pHyperCoreR0 = (R0PTRTYPE(PCPUMCTXCORE))MMHyperCCToR0(pVM, pCtxCore);
76 pVCpu->cpum.s.pHyperCoreRC = (RCPTRTYPE(PCPUMCTXCORE))MMHyperCCToRC(pVM, pCtxCore);
77 }
78}
79
80
81/**
82 * Gets the pointer to the internal CPUMCTXCORE structure for the hypervisor.
83 * This is only for reading in order to save a few calls.
84 *
85 * @param pVM Handle to the virtual machine.
86 */
87VMMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVMCPU pVCpu)
88{
89 return pVCpu->cpum.s.CTX_SUFF(pHyperCore);
90}
91
92
93/**
94 * Queries the pointer to the internal CPUMCTX structure for the hypervisor.
95 *
96 * @returns VBox status code.
97 * @param pVM Handle to the virtual machine.
98 * @param ppCtx Receives the hyper CPUMCTX pointer when successful.
99 *
100 * @deprecated This will *not* (and has never) given the right picture of the
101 * hypervisor register state. With CPUMHyperSetCtxCore() this is
102 * getting much worse. So, use the individual functions for getting
103 * and esp. setting the hypervisor registers.
104 */
105VMMDECL(int) CPUMQueryHyperCtxPtr(PVMCPU pVCpu, PCPUMCTX *ppCtx)
106{
107 *ppCtx = &pVCpu->cpum.s.Hyper;
108 return VINF_SUCCESS;
109}
110
111
112VMMDECL(void) CPUMSetHyperGDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
113{
114 pVCpu->cpum.s.Hyper.gdtr.cbGdt = limit;
115 pVCpu->cpum.s.Hyper.gdtr.pGdt = addr;
116 pVCpu->cpum.s.Hyper.gdtrPadding = 0;
117}
118
119
120VMMDECL(void) CPUMSetHyperIDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
121{
122 pVCpu->cpum.s.Hyper.idtr.cbIdt = limit;
123 pVCpu->cpum.s.Hyper.idtr.pIdt = addr;
124 pVCpu->cpum.s.Hyper.idtrPadding = 0;
125}
126
127
128VMMDECL(void) CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3)
129{
130 pVCpu->cpum.s.Hyper.cr3 = cr3;
131
132#ifdef IN_RC
133 /* Update the current CR3. */
134 ASMSetCR3(cr3);
135#endif
136}
137
138VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu)
139{
140 return pVCpu->cpum.s.Hyper.cr3;
141}
142
143
144VMMDECL(void) CPUMSetHyperCS(PVMCPU pVCpu, RTSEL SelCS)
145{
146 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->cs = SelCS;
147}
148
149
150VMMDECL(void) CPUMSetHyperDS(PVMCPU pVCpu, RTSEL SelDS)
151{
152 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ds = SelDS;
153}
154
155
156VMMDECL(void) CPUMSetHyperES(PVMCPU pVCpu, RTSEL SelES)
157{
158 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->es = SelES;
159}
160
161
162VMMDECL(void) CPUMSetHyperFS(PVMCPU pVCpu, RTSEL SelFS)
163{
164 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->fs = SelFS;
165}
166
167
168VMMDECL(void) CPUMSetHyperGS(PVMCPU pVCpu, RTSEL SelGS)
169{
170 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->gs = SelGS;
171}
172
173
174VMMDECL(void) CPUMSetHyperSS(PVMCPU pVCpu, RTSEL SelSS)
175{
176 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ss = SelSS;
177}
178
179
180VMMDECL(void) CPUMSetHyperESP(PVMCPU pVCpu, uint32_t u32ESP)
181{
182 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->esp = u32ESP;
183}
184
185
186VMMDECL(int) CPUMSetHyperEFlags(PVMCPU pVCpu, uint32_t Efl)
187{
188 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->eflags.u32 = Efl;
189 return VINF_SUCCESS;
190}
191
192
193VMMDECL(void) CPUMSetHyperEIP(PVMCPU pVCpu, uint32_t u32EIP)
194{
195 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->eip = u32EIP;
196}
197
198
199VMMDECL(void) CPUMSetHyperTR(PVMCPU pVCpu, RTSEL SelTR)
200{
201 pVCpu->cpum.s.Hyper.tr = SelTR;
202}
203
204
205VMMDECL(void) CPUMSetHyperLDTR(PVMCPU pVCpu, RTSEL SelLDTR)
206{
207 pVCpu->cpum.s.Hyper.ldtr = SelLDTR;
208}
209
210
211VMMDECL(void) CPUMSetHyperDR0(PVMCPU pVCpu, RTGCUINTREG uDr0)
212{
213 pVCpu->cpum.s.Hyper.dr[0] = uDr0;
214 /** @todo in GC we must load it! */
215}
216
217
218VMMDECL(void) CPUMSetHyperDR1(PVMCPU pVCpu, RTGCUINTREG uDr1)
219{
220 pVCpu->cpum.s.Hyper.dr[1] = uDr1;
221 /** @todo in GC we must load it! */
222}
223
224
225VMMDECL(void) CPUMSetHyperDR2(PVMCPU pVCpu, RTGCUINTREG uDr2)
226{
227 pVCpu->cpum.s.Hyper.dr[2] = uDr2;
228 /** @todo in GC we must load it! */
229}
230
231
232VMMDECL(void) CPUMSetHyperDR3(PVMCPU pVCpu, RTGCUINTREG uDr3)
233{
234 pVCpu->cpum.s.Hyper.dr[3] = uDr3;
235 /** @todo in GC we must load it! */
236}
237
238
239VMMDECL(void) CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6)
240{
241 pVCpu->cpum.s.Hyper.dr[6] = uDr6;
242 /** @todo in GC we must load it! */
243}
244
245
246VMMDECL(void) CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7)
247{
248 pVCpu->cpum.s.Hyper.dr[7] = uDr7;
249 /** @todo in GC we must load it! */
250}
251
252
253VMMDECL(RTSEL) CPUMGetHyperCS(PVMCPU pVCpu)
254{
255 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->cs;
256}
257
258
259VMMDECL(RTSEL) CPUMGetHyperDS(PVMCPU pVCpu)
260{
261 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ds;
262}
263
264
265VMMDECL(RTSEL) CPUMGetHyperES(PVMCPU pVCpu)
266{
267 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->es;
268}
269
270
271VMMDECL(RTSEL) CPUMGetHyperFS(PVMCPU pVCpu)
272{
273 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->fs;
274}
275
276
277VMMDECL(RTSEL) CPUMGetHyperGS(PVMCPU pVCpu)
278{
279 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->gs;
280}
281
282
283VMMDECL(RTSEL) CPUMGetHyperSS(PVMCPU pVCpu)
284{
285 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ss;
286}
287
288
289VMMDECL(uint32_t) CPUMGetHyperEAX(PVMCPU pVCpu)
290{
291 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->eax;
292}
293
294
295VMMDECL(uint32_t) CPUMGetHyperEBX(PVMCPU pVCpu)
296{
297 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ebx;
298}
299
300
301VMMDECL(uint32_t) CPUMGetHyperECX(PVMCPU pVCpu)
302{
303 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ecx;
304}
305
306
307VMMDECL(uint32_t) CPUMGetHyperEDX(PVMCPU pVCpu)
308{
309 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->edx;
310}
311
312
313VMMDECL(uint32_t) CPUMGetHyperESI(PVMCPU pVCpu)
314{
315 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->esi;
316}
317
318
319VMMDECL(uint32_t) CPUMGetHyperEDI(PVMCPU pVCpu)
320{
321 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->edi;
322}
323
324
325VMMDECL(uint32_t) CPUMGetHyperEBP(PVMCPU pVCpu)
326{
327 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ebp;
328}
329
330
331VMMDECL(uint32_t) CPUMGetHyperESP(PVMCPU pVCpu)
332{
333 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->esp;
334}
335
336
337VMMDECL(uint32_t) CPUMGetHyperEFlags(PVMCPU pVCpu)
338{
339 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->eflags.u32;
340}
341
342
343VMMDECL(uint32_t) CPUMGetHyperEIP(PVMCPU pVCpu)
344{
345 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->eip;
346}
347
348
349VMMDECL(uint64_t) CPUMGetHyperRIP(PVMCPU pVCpu)
350{
351 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->rip;
352}
353
354
355VMMDECL(uint32_t) CPUMGetHyperIDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
356{
357 if (pcbLimit)
358 *pcbLimit = pVCpu->cpum.s.Hyper.idtr.cbIdt;
359 return pVCpu->cpum.s.Hyper.idtr.pIdt;
360}
361
362
363VMMDECL(uint32_t) CPUMGetHyperGDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
364{
365 if (pcbLimit)
366 *pcbLimit = pVCpu->cpum.s.Hyper.gdtr.cbGdt;
367 return pVCpu->cpum.s.Hyper.gdtr.pGdt;
368}
369
370
371VMMDECL(RTSEL) CPUMGetHyperLDTR(PVMCPU pVCpu)
372{
373 return pVCpu->cpum.s.Hyper.ldtr;
374}
375
376
377VMMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVMCPU pVCpu)
378{
379 return pVCpu->cpum.s.Hyper.dr[0];
380}
381
382
383VMMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVMCPU pVCpu)
384{
385 return pVCpu->cpum.s.Hyper.dr[1];
386}
387
388
389VMMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVMCPU pVCpu)
390{
391 return pVCpu->cpum.s.Hyper.dr[2];
392}
393
394
395VMMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVMCPU pVCpu)
396{
397 return pVCpu->cpum.s.Hyper.dr[3];
398}
399
400
401VMMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVMCPU pVCpu)
402{
403 return pVCpu->cpum.s.Hyper.dr[6];
404}
405
406
407VMMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVMCPU pVCpu)
408{
409 return pVCpu->cpum.s.Hyper.dr[7];
410}
411
412
413/**
414 * Gets the pointer to the internal CPUMCTXCORE structure.
415 * This is only for reading in order to save a few calls.
416 *
417 * @param pVCpu Handle to the virtual cpu.
418 */
419VMMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVMCPU pVCpu)
420{
421 return CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
422}
423
424
425/**
426 * Sets the guest context core registers.
427 *
428 * @param pVCpu Handle to the virtual cpu.
429 * @param pCtxCore The new context core values.
430 */
431VMMDECL(void) CPUMSetGuestCtxCore(PVMCPU pVCpu, PCCPUMCTXCORE pCtxCore)
432{
433 /** @todo #1410 requires selectors to be checked. (huh? 1410?) */
434
435 PCPUMCTXCORE pCtxCoreDst = CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
436 *pCtxCoreDst = *pCtxCore;
437
438 /* Mask away invalid parts of the cpu context. */
439 if (!CPUMIsGuestInLongMode(pVCpu))
440 {
441 uint64_t u64Mask = UINT64_C(0xffffffff);
442
443 pCtxCoreDst->rip &= u64Mask;
444 pCtxCoreDst->rax &= u64Mask;
445 pCtxCoreDst->rbx &= u64Mask;
446 pCtxCoreDst->rcx &= u64Mask;
447 pCtxCoreDst->rdx &= u64Mask;
448 pCtxCoreDst->rsi &= u64Mask;
449 pCtxCoreDst->rdi &= u64Mask;
450 pCtxCoreDst->rbp &= u64Mask;
451 pCtxCoreDst->rsp &= u64Mask;
452 pCtxCoreDst->rflags.u &= u64Mask;
453
454 pCtxCoreDst->r8 = 0;
455 pCtxCoreDst->r9 = 0;
456 pCtxCoreDst->r10 = 0;
457 pCtxCoreDst->r11 = 0;
458 pCtxCoreDst->r12 = 0;
459 pCtxCoreDst->r13 = 0;
460 pCtxCoreDst->r14 = 0;
461 pCtxCoreDst->r15 = 0;
462 }
463}
464
465
466/**
467 * Queries the pointer to the internal CPUMCTX structure
468 *
469 * @returns The CPUMCTX pointer.
470 * @param pVCpu Handle to the virtual cpu.
471 */
472VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu)
473{
474 return &pVCpu->cpum.s.Guest;
475}
476
477VMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
478{
479 pVCpu->cpum.s.Guest.gdtr.cbGdt = limit;
480 pVCpu->cpum.s.Guest.gdtr.pGdt = addr;
481 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GDTR;
482 return VINF_SUCCESS;
483}
484
485VMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
486{
487 pVCpu->cpum.s.Guest.idtr.cbIdt = limit;
488 pVCpu->cpum.s.Guest.idtr.pIdt = addr;
489 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_IDTR;
490 return VINF_SUCCESS;
491}
492
493VMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr)
494{
495 AssertMsgFailed(("Need to load the hidden bits too!\n"));
496
497 pVCpu->cpum.s.Guest.tr = tr;
498 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_TR;
499 return VINF_SUCCESS;
500}
501
502VMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr)
503{
504 pVCpu->cpum.s.Guest.ldtr = ldtr;
505 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_LDTR;
506 return VINF_SUCCESS;
507}
508
509
510/**
511 * Set the guest CR0.
512 *
513 * When called in GC, the hyper CR0 may be updated if that is
514 * required. The caller only has to take special action if AM,
515 * WP, PG or PE changes.
516 *
517 * @returns VINF_SUCCESS (consider it void).
518 * @param pVCpu Handle to the virtual cpu.
519 * @param cr0 The new CR0 value.
520 */
521VMMDECL(int) CPUMSetGuestCR0(PVMCPU pVCpu, uint64_t cr0)
522{
523#ifdef IN_RC
524 /*
525 * Check if we need to change hypervisor CR0 because
526 * of math stuff.
527 */
528 if ( (cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP))
529 != (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP)))
530 {
531 if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU))
532 {
533 /*
534 * We haven't saved the host FPU state yet, so TS and MT are both set
535 * and EM should be reflecting the guest EM (it always does this).
536 */
537 if ((cr0 & X86_CR0_EM) != (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM))
538 {
539 uint32_t HyperCR0 = ASMGetCR0();
540 AssertMsg((HyperCR0 & (X86_CR0_TS | X86_CR0_MP)) == (X86_CR0_TS | X86_CR0_MP), ("%#x\n", HyperCR0));
541 AssertMsg((HyperCR0 & X86_CR0_EM) == (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM), ("%#x\n", HyperCR0));
542 HyperCR0 &= ~X86_CR0_EM;
543 HyperCR0 |= cr0 & X86_CR0_EM;
544 Log(("CPUM New HyperCR0=%#x\n", HyperCR0));
545 ASMSetCR0(HyperCR0);
546 }
547# ifdef VBOX_STRICT
548 else
549 {
550 uint32_t HyperCR0 = ASMGetCR0();
551 AssertMsg((HyperCR0 & (X86_CR0_TS | X86_CR0_MP)) == (X86_CR0_TS | X86_CR0_MP), ("%#x\n", HyperCR0));
552 AssertMsg((HyperCR0 & X86_CR0_EM) == (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM), ("%#x\n", HyperCR0));
553 }
554# endif
555 }
556 else
557 {
558 /*
559 * Already saved the state, so we're just mirroring
560 * the guest flags.
561 */
562 uint32_t HyperCR0 = ASMGetCR0();
563 AssertMsg( (HyperCR0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP))
564 == (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP)),
565 ("%#x %#x\n", HyperCR0, pVCpu->cpum.s.Guest.cr0));
566 HyperCR0 &= ~(X86_CR0_TS | X86_CR0_EM | X86_CR0_MP);
567 HyperCR0 |= cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP);
568 Log(("CPUM New HyperCR0=%#x\n", HyperCR0));
569 ASMSetCR0(HyperCR0);
570 }
571 }
572#endif /* IN_RC */
573
574 /*
575 * Check for changes causing TLB flushes (for REM).
576 * The caller is responsible for calling PGM when appropriate.
577 */
578 if ( (cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE))
579 != (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)))
580 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
581 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR0;
582
583 pVCpu->cpum.s.Guest.cr0 = cr0 | X86_CR0_ET;
584 return VINF_SUCCESS;
585}
586
587
588VMMDECL(int) CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2)
589{
590 pVCpu->cpum.s.Guest.cr2 = cr2;
591 return VINF_SUCCESS;
592}
593
594
595VMMDECL(int) CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3)
596{
597 pVCpu->cpum.s.Guest.cr3 = cr3;
598 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR3;
599 return VINF_SUCCESS;
600}
601
602
603VMMDECL(int) CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4)
604{
605 if ( (cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE))
606 != (pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE)))
607 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
608 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR4;
609 if (!CPUMSupportsFXSR(pVCpu->CTX_SUFF(pVM)))
610 cr4 &= ~X86_CR4_OSFSXR;
611 pVCpu->cpum.s.Guest.cr4 = cr4;
612 return VINF_SUCCESS;
613}
614
615
616VMMDECL(int) CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags)
617{
618 pVCpu->cpum.s.Guest.eflags.u32 = eflags;
619 return VINF_SUCCESS;
620}
621
622
623VMMDECL(int) CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip)
624{
625 pVCpu->cpum.s.Guest.eip = eip;
626 return VINF_SUCCESS;
627}
628
629
630VMMDECL(int) CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax)
631{
632 pVCpu->cpum.s.Guest.eax = eax;
633 return VINF_SUCCESS;
634}
635
636
637VMMDECL(int) CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx)
638{
639 pVCpu->cpum.s.Guest.ebx = ebx;
640 return VINF_SUCCESS;
641}
642
643
644VMMDECL(int) CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx)
645{
646 pVCpu->cpum.s.Guest.ecx = ecx;
647 return VINF_SUCCESS;
648}
649
650
651VMMDECL(int) CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx)
652{
653 pVCpu->cpum.s.Guest.edx = edx;
654 return VINF_SUCCESS;
655}
656
657
658VMMDECL(int) CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp)
659{
660 pVCpu->cpum.s.Guest.esp = esp;
661 return VINF_SUCCESS;
662}
663
664
665VMMDECL(int) CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp)
666{
667 pVCpu->cpum.s.Guest.ebp = ebp;
668 return VINF_SUCCESS;
669}
670
671
672VMMDECL(int) CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi)
673{
674 pVCpu->cpum.s.Guest.esi = esi;
675 return VINF_SUCCESS;
676}
677
678
679VMMDECL(int) CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi)
680{
681 pVCpu->cpum.s.Guest.edi = edi;
682 return VINF_SUCCESS;
683}
684
685
686VMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss)
687{
688 pVCpu->cpum.s.Guest.ss = ss;
689 return VINF_SUCCESS;
690}
691
692
693VMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs)
694{
695 pVCpu->cpum.s.Guest.cs = cs;
696 return VINF_SUCCESS;
697}
698
699
700VMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds)
701{
702 pVCpu->cpum.s.Guest.ds = ds;
703 return VINF_SUCCESS;
704}
705
706
707VMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es)
708{
709 pVCpu->cpum.s.Guest.es = es;
710 return VINF_SUCCESS;
711}
712
713
714VMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs)
715{
716 pVCpu->cpum.s.Guest.fs = fs;
717 return VINF_SUCCESS;
718}
719
720
721VMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs)
722{
723 pVCpu->cpum.s.Guest.gs = gs;
724 return VINF_SUCCESS;
725}
726
727
728VMMDECL(void) CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val)
729{
730 pVCpu->cpum.s.Guest.msrEFER = val;
731}
732
733
734/**
735 * Query an MSR.
736 *
737 * The caller is responsible for checking privilege if the call is the result
738 * of a RDMSR instruction. We'll do the rest.
739 *
740 * @retval VINF_SUCCESS on success.
741 * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR), the caller is
742 * expected to take the appropriate actions. @a *puValue is set to 0.
743 * @param pVCpu The virtual CPU to operate on.
744 * @param idMsr The MSR.
745 * @param puValue Where to return the value..
746 *
747 * @remarks This will always return the right values, even when we're in the
748 * recompiler.
749 */
750VMMDECL(int) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue)
751{
752 /*
753 * If we don't indicate MSR support in the CPUID feature bits, indicate
754 * that a #GP(0) should be raised.
755 */
756 if (!(pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_MSR))
757 {
758 *puValue = 0;
759 return VERR_CPUM_RAISE_GP_0;
760 }
761
762 int rc = VINF_SUCCESS;
763 uint8_t const u8Multiplier = 4;
764 switch (idMsr)
765 {
766 case MSR_IA32_TSC:
767 *puValue = TMCpuTickGet(pVCpu);
768 break;
769
770 case MSR_IA32_APICBASE:
771 rc = PDMApicGetBase(pVCpu->CTX_SUFF(pVM), puValue);
772 if (RT_SUCCESS(rc))
773 rc = VINF_SUCCESS;
774 else
775 {
776 *puValue = 0;
777 rc = VERR_CPUM_RAISE_GP_0;
778 }
779 break;
780
781 case MSR_IA32_CR_PAT:
782 *puValue = pVCpu->cpum.s.Guest.msrPAT;
783 break;
784
785 case MSR_IA32_SYSENTER_CS:
786 *puValue = pVCpu->cpum.s.Guest.SysEnter.cs;
787 break;
788
789 case MSR_IA32_SYSENTER_EIP:
790 *puValue = pVCpu->cpum.s.Guest.SysEnter.eip;
791 break;
792
793 case MSR_IA32_SYSENTER_ESP:
794 *puValue = pVCpu->cpum.s.Guest.SysEnter.esp;
795 break;
796
797 case MSR_K6_EFER:
798 *puValue = pVCpu->cpum.s.Guest.msrEFER;
799 break;
800
801 case MSR_K8_SF_MASK:
802 *puValue = pVCpu->cpum.s.Guest.msrSFMASK;
803 break;
804
805 case MSR_K6_STAR:
806 *puValue = pVCpu->cpum.s.Guest.msrSTAR;
807 break;
808
809 case MSR_K8_LSTAR:
810 *puValue = pVCpu->cpum.s.Guest.msrLSTAR;
811 break;
812
813 case MSR_K8_CSTAR:
814 *puValue = pVCpu->cpum.s.Guest.msrCSTAR;
815 break;
816
817 case MSR_K8_FS_BASE:
818 *puValue = pVCpu->cpum.s.Guest.fsHid.u64Base;
819 break;
820
821 case MSR_K8_GS_BASE:
822 *puValue = pVCpu->cpum.s.Guest.gsHid.u64Base;
823 break;
824
825 case MSR_K8_KERNEL_GS_BASE:
826 *puValue = pVCpu->cpum.s.Guest.msrKERNELGSBASE;
827 break;
828
829 case MSR_K8_TSC_AUX:
830 *puValue = pVCpu->cpum.s.GuestMsr.msr.tscAux;
831 break;
832
833 case MSR_IA32_PERF_STATUS:
834 /** @todo could really be not exactly correct, maybe use host's values */
835 *puValue = UINT64_C(1000) /* TSC increment by tick */
836 | ((uint64_t)u8Multiplier << 24) /* CPU multiplier (aka bus ratio) min */
837 | ((uint64_t)u8Multiplier << 40) /* CPU multiplier (aka bus ratio) max */;
838 break;
839
840 case MSR_IA32_FSB_CLOCK_STS:
841 /*
842 * Encoded as:
843 * 0 - 266
844 * 1 - 133
845 * 2 - 200
846 * 3 - return 166
847 * 5 - return 100
848 */
849 *puValue = (2 << 4);
850 break;
851
852 case MSR_IA32_PLATFORM_INFO:
853 *puValue = (u8Multiplier << 8) /* Flex ratio max */
854 | ((uint64_t)u8Multiplier << 40) /* Flex ratio min */;
855 break;
856
857 case MSR_IA32_THERM_STATUS:
858 /* CPU temperature reltive to TCC, to actually activate, CPUID leaf 6 EAX[0] must be set */
859 *puValue = ( 1 << 31) /* validity bit */
860 | (20 << 16) /* degrees till TCC */;
861 break;
862
863 case MSR_IA32_MISC_ENABLE:
864#if 0
865 /* Needs to be tested more before enabling. */
866 *puValue = pVCpu->cpum.s.GuestMsr.msr.miscEnable;
867#else
868 *puValue = 0;
869#endif
870 break;
871
872#if 0 /*def IN_RING0 */
873 case MSR_IA32_PLATFORM_ID:
874 case MSR_IA32_BIOS_SIGN_ID:
875 if (CPUMGetCPUVendor(pVM) == CPUMCPUVENDOR_INTEL)
876 {
877 /* Available since the P6 family. VT-x implies that this feature is present. */
878 if (idMsr == MSR_IA32_PLATFORM_ID)
879 *puValue = ASMRdMsr(MSR_IA32_PLATFORM_ID);
880 else if (idMsr == MSR_IA32_BIOS_SIGN_ID)
881 *puValue = ASMRdMsr(MSR_IA32_BIOS_SIGN_ID);
882 break;
883 }
884 /* no break */
885#endif
886
887 default:
888 /* In X2APIC specification this range is reserved for APIC control. */
889 if ( idMsr >= MSR_IA32_APIC_START
890 && idMsr < MSR_IA32_APIC_END)
891 {
892 rc = PDMApicReadMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, puValue);
893 if (RT_SUCCESS(rc))
894 rc = VINF_SUCCESS;
895 else
896 {
897 *puValue = 0;
898 rc = VERR_CPUM_RAISE_GP_0;
899 }
900 }
901 else
902 {
903 *puValue = 0;
904 rc = VERR_CPUM_RAISE_GP_0;
905 }
906 break;
907 }
908
909 return rc;
910}
911
912
913/**
914 * Sets the MSR.
915 *
916 * The caller is responsible for checking privilege if the call is the result
917 * of a WRMSR instruction. We'll do the rest.
918 *
919 * @retval VINF_SUCCESS on success.
920 * @retval VERR_CPUM_RAISE_GP_0 on failure, the caller is expected to take the
921 * appropriate actions.
922 *
923 * @param pVCpu The virtual CPU to operate on.
924 * @param idMsr The MSR id.
925 * @param uValue The value to set.
926 *
927 * @remarks Everyone changing MSR values, including the recompiler, shall do it
928 * by calling this method. This makes sure we have current values and
929 * that we trigger all the right actions when something changes.
930 */
931VMMDECL(int) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue)
932{
933 /*
934 * If we don't indicate MSR support in the CPUID feature bits, indicate
935 * that a #GP(0) should be raised.
936 */
937 if (!(pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_MSR))
938 return VERR_CPUM_RAISE_GP_0;
939
940 int rc = VINF_SUCCESS;
941 switch (idMsr)
942 {
943 case MSR_IA32_MISC_ENABLE:
944 pVCpu->cpum.s.GuestMsr.msr.miscEnable = uValue;
945 break;
946
947 case MSR_IA32_TSC:
948 TMCpuTickSet(pVCpu->CTX_SUFF(pVM), pVCpu, uValue);
949 break;
950
951 case MSR_IA32_APICBASE:
952 rc = PDMApicSetBase(pVCpu->CTX_SUFF(pVM), uValue);
953 if (rc != VINF_SUCCESS)
954 rc = VERR_CPUM_RAISE_GP_0;
955 break;
956
957 case MSR_IA32_CR_PAT:
958 pVCpu->cpum.s.Guest.msrPAT = uValue;
959 break;
960
961 case MSR_IA32_SYSENTER_CS:
962 pVCpu->cpum.s.Guest.SysEnter.cs = uValue & 0xffff; /* 16 bits selector */
963 break;
964
965 case MSR_IA32_SYSENTER_EIP:
966 pVCpu->cpum.s.Guest.SysEnter.eip = uValue;
967 break;
968
969 case MSR_IA32_SYSENTER_ESP:
970 pVCpu->cpum.s.Guest.SysEnter.esp = uValue;
971 break;
972
973 case MSR_K6_EFER:
974 {
975 PVM pVM = pVCpu->CTX_SUFF(pVM);
976 uint64_t const uOldEFER = pVCpu->cpum.s.Guest.msrEFER;
977 uint32_t const fExtFeatures = pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
978 ? pVM->cpum.s.aGuestCpuIdExt[1].edx
979 : 0;
980 uint64_t fMask = 0;
981
982 /* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
983 if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_NX)
984 fMask |= MSR_K6_EFER_NXE;
985 if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE)
986 fMask |= MSR_K6_EFER_LME;
987 if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_SEP)
988 fMask |= MSR_K6_EFER_SCE;
989 if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
990 fMask |= MSR_K6_EFER_FFXSR;
991
992 /* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if
993 paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
994 if ( (uOldEFER & MSR_K6_EFER_LME) != (uValue & fMask & MSR_K6_EFER_LME)
995 && (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG))
996 {
997 Log(("Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
998 return VERR_CPUM_RAISE_GP_0;
999 }
1000
1001 /* There are a few more: e.g. MSR_K6_EFER_LMSLE */
1002 AssertMsg(!(uValue & ~(MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA /* ignored anyway */ | MSR_K6_EFER_SCE | MSR_K6_EFER_FFXSR)),
1003 ("Unexpected value %RX64\n", uValue));
1004 pVCpu->cpum.s.Guest.msrEFER = (uOldEFER & ~fMask) | (uValue & fMask);
1005
1006 /* AMD64 Architecture Programmer's Manual: 15.15 TLB Control; flush the TLB
1007 if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
1008 if ( (uOldEFER & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA))
1009 != (pVCpu->cpum.s.Guest.msrEFER & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA)))
1010 {
1011 /// @todo PGMFlushTLB(pVCpu, cr3, true /*fGlobal*/);
1012 HWACCMFlushTLB(pVCpu);
1013
1014 /* Notify PGM about NXE changes. */
1015 if ( (uOldEFER & MSR_K6_EFER_NXE)
1016 != (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE))
1017 PGMNotifyNxeChanged(pVCpu, !(uOldEFER & MSR_K6_EFER_NXE));
1018 }
1019 break;
1020 }
1021
1022 case MSR_K8_SF_MASK:
1023 pVCpu->cpum.s.Guest.msrSFMASK = uValue;
1024 break;
1025
1026 case MSR_K6_STAR:
1027 pVCpu->cpum.s.Guest.msrSTAR = uValue;
1028 break;
1029
1030 case MSR_K8_LSTAR:
1031 pVCpu->cpum.s.Guest.msrLSTAR = uValue;
1032 break;
1033
1034 case MSR_K8_CSTAR:
1035 pVCpu->cpum.s.Guest.msrCSTAR = uValue;
1036 break;
1037
1038 case MSR_K8_FS_BASE:
1039 pVCpu->cpum.s.Guest.fsHid.u64Base = uValue;
1040 break;
1041
1042 case MSR_K8_GS_BASE:
1043 pVCpu->cpum.s.Guest.gsHid.u64Base = uValue;
1044 break;
1045
1046 case MSR_K8_KERNEL_GS_BASE:
1047 pVCpu->cpum.s.Guest.msrKERNELGSBASE = uValue;
1048 break;
1049
1050 case MSR_K8_TSC_AUX:
1051 pVCpu->cpum.s.GuestMsr.msr.tscAux = uValue;
1052 break;
1053
1054 default:
1055 /* In X2APIC specification this range is reserved for APIC control. */
1056 if ( idMsr >= MSR_IA32_APIC_START
1057 && idMsr < MSR_IA32_APIC_END)
1058 {
1059 rc = PDMApicWriteMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, uValue);
1060 if (rc != VINF_SUCCESS)
1061 rc = VERR_CPUM_RAISE_GP_0;
1062 }
1063 else
1064 {
1065 /* We should actually trigger a #GP here, but don't as that might cause more trouble. */
1066 /** @todo rc = VERR_CPUM_RAISE_GP_0 */
1067 Log(("CPUMSetGuestMsr: Unknown MSR %#x attempted set to %#llx\n", idMsr, uValue));
1068 }
1069 break;
1070 }
1071 return rc;
1072}
1073
1074
1075VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
1076{
1077 if (pcbLimit)
1078 *pcbLimit = pVCpu->cpum.s.Guest.idtr.cbIdt;
1079 return pVCpu->cpum.s.Guest.idtr.pIdt;
1080}
1081
1082
1083VMMDECL(RTSEL) CPUMGetGuestTR(PVMCPU pVCpu, PCPUMSELREGHID pHidden)
1084{
1085 if (pHidden)
1086 *pHidden = pVCpu->cpum.s.Guest.trHid;
1087 return pVCpu->cpum.s.Guest.tr;
1088}
1089
1090
1091VMMDECL(RTSEL) CPUMGetGuestCS(PVMCPU pVCpu)
1092{
1093 return pVCpu->cpum.s.Guest.cs;
1094}
1095
1096
1097VMMDECL(RTSEL) CPUMGetGuestDS(PVMCPU pVCpu)
1098{
1099 return pVCpu->cpum.s.Guest.ds;
1100}
1101
1102
1103VMMDECL(RTSEL) CPUMGetGuestES(PVMCPU pVCpu)
1104{
1105 return pVCpu->cpum.s.Guest.es;
1106}
1107
1108
1109VMMDECL(RTSEL) CPUMGetGuestFS(PVMCPU pVCpu)
1110{
1111 return pVCpu->cpum.s.Guest.fs;
1112}
1113
1114
1115VMMDECL(RTSEL) CPUMGetGuestGS(PVMCPU pVCpu)
1116{
1117 return pVCpu->cpum.s.Guest.gs;
1118}
1119
1120
1121VMMDECL(RTSEL) CPUMGetGuestSS(PVMCPU pVCpu)
1122{
1123 return pVCpu->cpum.s.Guest.ss;
1124}
1125
1126
1127VMMDECL(RTSEL) CPUMGetGuestLDTR(PVMCPU pVCpu)
1128{
1129 return pVCpu->cpum.s.Guest.ldtr;
1130}
1131
1132
1133VMMDECL(uint64_t) CPUMGetGuestCR0(PVMCPU pVCpu)
1134{
1135 return pVCpu->cpum.s.Guest.cr0;
1136}
1137
1138
1139VMMDECL(uint64_t) CPUMGetGuestCR2(PVMCPU pVCpu)
1140{
1141 return pVCpu->cpum.s.Guest.cr2;
1142}
1143
1144
1145VMMDECL(uint64_t) CPUMGetGuestCR3(PVMCPU pVCpu)
1146{
1147 return pVCpu->cpum.s.Guest.cr3;
1148}
1149
1150
1151VMMDECL(uint64_t) CPUMGetGuestCR4(PVMCPU pVCpu)
1152{
1153 return pVCpu->cpum.s.Guest.cr4;
1154}
1155
1156
1157VMMDECL(uint64_t) CPUMGetGuestCR8(PVMCPU pVCpu)
1158{
1159 uint64_t u64;
1160 int rc = CPUMGetGuestCRx(pVCpu, USE_REG_CR8, &u64);
1161 if (RT_FAILURE(rc))
1162 u64 = 0;
1163 return u64;
1164}
1165
1166
1167VMMDECL(void) CPUMGetGuestGDTR(PVMCPU pVCpu, PVBOXGDTR pGDTR)
1168{
1169 *pGDTR = pVCpu->cpum.s.Guest.gdtr;
1170}
1171
1172
1173VMMDECL(uint32_t) CPUMGetGuestEIP(PVMCPU pVCpu)
1174{
1175 return pVCpu->cpum.s.Guest.eip;
1176}
1177
1178
1179VMMDECL(uint64_t) CPUMGetGuestRIP(PVMCPU pVCpu)
1180{
1181 return pVCpu->cpum.s.Guest.rip;
1182}
1183
1184
1185VMMDECL(uint32_t) CPUMGetGuestEAX(PVMCPU pVCpu)
1186{
1187 return pVCpu->cpum.s.Guest.eax;
1188}
1189
1190
1191VMMDECL(uint32_t) CPUMGetGuestEBX(PVMCPU pVCpu)
1192{
1193 return pVCpu->cpum.s.Guest.ebx;
1194}
1195
1196
1197VMMDECL(uint32_t) CPUMGetGuestECX(PVMCPU pVCpu)
1198{
1199 return pVCpu->cpum.s.Guest.ecx;
1200}
1201
1202
1203VMMDECL(uint32_t) CPUMGetGuestEDX(PVMCPU pVCpu)
1204{
1205 return pVCpu->cpum.s.Guest.edx;
1206}
1207
1208
1209VMMDECL(uint32_t) CPUMGetGuestESI(PVMCPU pVCpu)
1210{
1211 return pVCpu->cpum.s.Guest.esi;
1212}
1213
1214
1215VMMDECL(uint32_t) CPUMGetGuestEDI(PVMCPU pVCpu)
1216{
1217 return pVCpu->cpum.s.Guest.edi;
1218}
1219
1220
1221VMMDECL(uint32_t) CPUMGetGuestESP(PVMCPU pVCpu)
1222{
1223 return pVCpu->cpum.s.Guest.esp;
1224}
1225
1226
1227VMMDECL(uint32_t) CPUMGetGuestEBP(PVMCPU pVCpu)
1228{
1229 return pVCpu->cpum.s.Guest.ebp;
1230}
1231
1232
1233VMMDECL(uint32_t) CPUMGetGuestEFlags(PVMCPU pVCpu)
1234{
1235 return pVCpu->cpum.s.Guest.eflags.u32;
1236}
1237
1238
1239VMMDECL(int) CPUMGetGuestCRx(PVMCPU pVCpu, unsigned iReg, uint64_t *pValue)
1240{
1241 switch (iReg)
1242 {
1243 case USE_REG_CR0:
1244 *pValue = pVCpu->cpum.s.Guest.cr0;
1245 break;
1246
1247 case USE_REG_CR2:
1248 *pValue = pVCpu->cpum.s.Guest.cr2;
1249 break;
1250
1251 case USE_REG_CR3:
1252 *pValue = pVCpu->cpum.s.Guest.cr3;
1253 break;
1254
1255 case USE_REG_CR4:
1256 *pValue = pVCpu->cpum.s.Guest.cr4;
1257 break;
1258
1259 case USE_REG_CR8:
1260 {
1261 uint8_t u8Tpr;
1262 int rc = PDMApicGetTPR(pVCpu, &u8Tpr, NULL /*pfPending*/);
1263 if (RT_FAILURE(rc))
1264 {
1265 AssertMsg(rc == VERR_PDM_NO_APIC_INSTANCE, ("%Rrc\n", rc));
1266 *pValue = 0;
1267 return rc;
1268 }
1269 *pValue = u8Tpr >> 4; /* bits 7-4 contain the task priority that go in cr8, bits 3-0*/
1270 break;
1271 }
1272
1273 default:
1274 return VERR_INVALID_PARAMETER;
1275 }
1276 return VINF_SUCCESS;
1277}
1278
1279
1280VMMDECL(uint64_t) CPUMGetGuestDR0(PVMCPU pVCpu)
1281{
1282 return pVCpu->cpum.s.Guest.dr[0];
1283}
1284
1285
1286VMMDECL(uint64_t) CPUMGetGuestDR1(PVMCPU pVCpu)
1287{
1288 return pVCpu->cpum.s.Guest.dr[1];
1289}
1290
1291
1292VMMDECL(uint64_t) CPUMGetGuestDR2(PVMCPU pVCpu)
1293{
1294 return pVCpu->cpum.s.Guest.dr[2];
1295}
1296
1297
1298VMMDECL(uint64_t) CPUMGetGuestDR3(PVMCPU pVCpu)
1299{
1300 return pVCpu->cpum.s.Guest.dr[3];
1301}
1302
1303
1304VMMDECL(uint64_t) CPUMGetGuestDR6(PVMCPU pVCpu)
1305{
1306 return pVCpu->cpum.s.Guest.dr[6];
1307}
1308
1309
1310VMMDECL(uint64_t) CPUMGetGuestDR7(PVMCPU pVCpu)
1311{
1312 return pVCpu->cpum.s.Guest.dr[7];
1313}
1314
1315
1316VMMDECL(int) CPUMGetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t *pValue)
1317{
1318 AssertReturn(iReg <= USE_REG_DR7, VERR_INVALID_PARAMETER);
1319 /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
1320 if (iReg == 4 || iReg == 5)
1321 iReg += 2;
1322 *pValue = pVCpu->cpum.s.Guest.dr[iReg];
1323 return VINF_SUCCESS;
1324}
1325
1326
1327VMMDECL(uint64_t) CPUMGetGuestEFER(PVMCPU pVCpu)
1328{
1329 return pVCpu->cpum.s.Guest.msrEFER;
1330}
1331
1332
1333/**
1334 * Gets a CpuId leaf.
1335 *
1336 * @param pVCpu The VMCPU handle.
1337 * @param iLeaf The CPUID leaf to get.
1338 * @param pEax Where to store the EAX value.
1339 * @param pEbx Where to store the EBX value.
1340 * @param pEcx Where to store the ECX value.
1341 * @param pEdx Where to store the EDX value.
1342 */
1343VMMDECL(void) CPUMGetGuestCpuId(PVMCPU pVCpu, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx)
1344{
1345 PVM pVM = pVCpu->CTX_SUFF(pVM);
1346
1347 PCCPUMCPUID pCpuId;
1348 if (iLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
1349 pCpuId = &pVM->cpum.s.aGuestCpuIdStd[iLeaf];
1350 else if (iLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
1351 pCpuId = &pVM->cpum.s.aGuestCpuIdExt[iLeaf - UINT32_C(0x80000000)];
1352 else if (iLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
1353 pCpuId = &pVM->cpum.s.aGuestCpuIdCentaur[iLeaf - UINT32_C(0xc0000000)];
1354 else
1355 pCpuId = &pVM->cpum.s.GuestCpuIdDef;
1356
1357 uint32_t cCurrentCacheIndex = *pEcx;
1358
1359 *pEax = pCpuId->eax;
1360 *pEbx = pCpuId->ebx;
1361 *pEcx = pCpuId->ecx;
1362 *pEdx = pCpuId->edx;
1363
1364 if ( iLeaf == 1)
1365 {
1366 /* Bits 31-24: Initial APIC ID */
1367 Assert(pVCpu->idCpu <= 255);
1368 *pEbx |= (pVCpu->idCpu << 24);
1369 }
1370
1371 if ( iLeaf == 4
1372 && cCurrentCacheIndex < 3
1373 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
1374 {
1375 uint32_t type, level, sharing, linesize,
1376 partitions, associativity, sets, cores;
1377
1378 /* For type: 1 - data cache, 2 - i-cache, 3 - unified */
1379 partitions = 1;
1380 /* Those are only to shut up compiler, as they will always
1381 get overwritten, and compiler should be able to figure that out */
1382 sets = associativity = sharing = level = 1;
1383 cores = pVM->cCpus > 32 ? 32 : pVM->cCpus;
1384 switch (cCurrentCacheIndex)
1385 {
1386 case 0:
1387 type = 1;
1388 level = 1;
1389 sharing = 1;
1390 linesize = 64;
1391 associativity = 8;
1392 sets = 64;
1393 break;
1394 case 1:
1395 level = 1;
1396 type = 2;
1397 sharing = 1;
1398 linesize = 64;
1399 associativity = 8;
1400 sets = 64;
1401 break;
1402 default: /* shut up gcc.*/
1403 AssertFailed();
1404 case 2:
1405 level = 2;
1406 type = 3;
1407 sharing = cores; /* our L2 cache is modelled as shared between all cores */
1408 linesize = 64;
1409 associativity = 24;
1410 sets = 4096;
1411 break;
1412 }
1413
1414 *pEax |= ((cores - 1) << 26) |
1415 ((sharing - 1) << 14) |
1416 (level << 5) |
1417 1;
1418 *pEbx = (linesize - 1) |
1419 ((partitions - 1) << 12) |
1420 ((associativity - 1) << 22); /* -1 encoding */
1421 *pEcx = sets - 1;
1422 }
1423
1424 Log2(("CPUMGetGuestCpuId: iLeaf=%#010x %RX32 %RX32 %RX32 %RX32\n", iLeaf, *pEax, *pEbx, *pEcx, *pEdx));
1425}
1426
1427/**
1428 * Gets a number of standard CPUID leafs.
1429 *
1430 * @returns Number of leafs.
1431 * @param pVM The VM handle.
1432 * @remark Intended for PATM.
1433 */
1434VMMDECL(uint32_t) CPUMGetGuestCpuIdStdMax(PVM pVM)
1435{
1436 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd);
1437}
1438
1439
1440/**
1441 * Gets a number of extended CPUID leafs.
1442 *
1443 * @returns Number of leafs.
1444 * @param pVM The VM handle.
1445 * @remark Intended for PATM.
1446 */
1447VMMDECL(uint32_t) CPUMGetGuestCpuIdExtMax(PVM pVM)
1448{
1449 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt);
1450}
1451
1452
1453/**
1454 * Gets a number of centaur CPUID leafs.
1455 *
1456 * @returns Number of leafs.
1457 * @param pVM The VM handle.
1458 * @remark Intended for PATM.
1459 */
1460VMMDECL(uint32_t) CPUMGetGuestCpuIdCentaurMax(PVM pVM)
1461{
1462 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur);
1463}
1464
1465
1466/**
1467 * Sets a CPUID feature bit.
1468 *
1469 * @param pVM The VM Handle.
1470 * @param enmFeature The feature to set.
1471 */
1472VMMDECL(void) CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
1473{
1474 switch (enmFeature)
1475 {
1476 /*
1477 * Set the APIC bit in both feature masks.
1478 */
1479 case CPUMCPUIDFEATURE_APIC:
1480 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1481 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_APIC;
1482 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1483 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1484 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_APIC;
1485 LogRel(("CPUMSetGuestCpuIdFeature: Enabled APIC\n"));
1486 break;
1487
1488 /*
1489 * Set the x2APIC bit in the standard feature mask.
1490 */
1491 case CPUMCPUIDFEATURE_X2APIC:
1492 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1493 pVM->cpum.s.aGuestCpuIdStd[1].ecx |= X86_CPUID_FEATURE_ECX_X2APIC;
1494 LogRel(("CPUMSetGuestCpuIdFeature: Enabled x2APIC\n"));
1495 break;
1496
1497 /*
1498 * Set the sysenter/sysexit bit in the standard feature mask.
1499 * Assumes the caller knows what it's doing! (host must support these)
1500 */
1501 case CPUMCPUIDFEATURE_SEP:
1502 {
1503 if (!(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_SEP))
1504 {
1505 AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
1506 return;
1507 }
1508
1509 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1510 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_SEP;
1511 LogRel(("CPUMSetGuestCpuIdFeature: Enabled sysenter/exit\n"));
1512 break;
1513 }
1514
1515 /*
1516 * Set the syscall/sysret bit in the extended feature mask.
1517 * Assumes the caller knows what it's doing! (host must support these)
1518 */
1519 case CPUMCPUIDFEATURE_SYSCALL:
1520 {
1521 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1522 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_SEP))
1523 {
1524#if HC_ARCH_BITS == 32
1525 /* X86_CPUID_AMD_FEATURE_EDX_SEP not set it seems in 32 bits mode.
1526 * Even when the cpu is capable of doing so in 64 bits mode.
1527 */
1528 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1529 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE)
1530 || !(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_SEP))
1531#endif
1532 {
1533 LogRel(("WARNING: Can't turn on SYSCALL/SYSRET when the host doesn't support it!!\n"));
1534 return;
1535 }
1536 }
1537 /* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
1538 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_SEP;
1539 LogRel(("CPUMSetGuestCpuIdFeature: Enabled syscall/ret\n"));
1540 break;
1541 }
1542
1543 /*
1544 * Set the PAE bit in both feature masks.
1545 * Assumes the caller knows what it's doing! (host must support these)
1546 */
1547 case CPUMCPUIDFEATURE_PAE:
1548 {
1549 if (!(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_PAE))
1550 {
1551 LogRel(("WARNING: Can't turn on PAE when the host doesn't support it!!\n"));
1552 return;
1553 }
1554
1555 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1556 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_PAE;
1557 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1558 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1559 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_PAE;
1560 LogRel(("CPUMSetGuestCpuIdFeature: Enabled PAE\n"));
1561 break;
1562 }
1563
1564 /*
1565 * Set the LONG MODE bit in the extended feature mask.
1566 * Assumes the caller knows what it's doing! (host must support these)
1567 */
1568 case CPUMCPUIDFEATURE_LONG_MODE:
1569 {
1570 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1571 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE))
1572 {
1573 LogRel(("WARNING: Can't turn on LONG MODE when the host doesn't support it!!\n"));
1574 return;
1575 }
1576
1577 /* Valid for both Intel and AMD. */
1578 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_LONG_MODE;
1579 LogRel(("CPUMSetGuestCpuIdFeature: Enabled LONG MODE\n"));
1580 break;
1581 }
1582
1583 /*
1584 * Set the NXE bit in the extended feature mask.
1585 * Assumes the caller knows what it's doing! (host must support these)
1586 */
1587 case CPUMCPUIDFEATURE_NXE:
1588 {
1589 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1590 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_NX))
1591 {
1592 LogRel(("WARNING: Can't turn on NXE when the host doesn't support it!!\n"));
1593 return;
1594 }
1595
1596 /* Valid for both Intel and AMD. */
1597 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_NX;
1598 LogRel(("CPUMSetGuestCpuIdFeature: Enabled NXE\n"));
1599 break;
1600 }
1601
1602 case CPUMCPUIDFEATURE_LAHF:
1603 {
1604 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1605 || !(ASMCpuId_ECX(0x80000001) & X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF))
1606 {
1607 LogRel(("WARNING: Can't turn on LAHF/SAHF when the host doesn't support it!!\n"));
1608 return;
1609 }
1610
1611 pVM->cpum.s.aGuestCpuIdExt[1].ecx |= X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF;
1612 LogRel(("CPUMSetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
1613 break;
1614 }
1615
1616 case CPUMCPUIDFEATURE_PAT:
1617 {
1618 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1619 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_PAT;
1620 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1621 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1622 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_PAT;
1623 LogRel(("CPUMClearGuestCpuIdFeature: Enabled PAT\n"));
1624 break;
1625 }
1626
1627 case CPUMCPUIDFEATURE_RDTSCP:
1628 {
1629 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1630 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_RDTSCP)
1631 || pVM->cpum.s.u8PortableCpuIdLevel > 0)
1632 {
1633 if (!pVM->cpum.s.u8PortableCpuIdLevel)
1634 LogRel(("WARNING: Can't turn on RDTSCP when the host doesn't support it!!\n"));
1635 return;
1636 }
1637
1638 /* Valid for AMD only (for now). */
1639 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_RDTSCP;
1640 LogRel(("CPUMSetGuestCpuIdFeature: Enabled RDTSCP.\n"));
1641 break;
1642 }
1643
1644 default:
1645 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
1646 break;
1647 }
1648 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1649 {
1650 PVMCPU pVCpu = &pVM->aCpus[i];
1651 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CPUID;
1652 }
1653}
1654
1655
1656/**
1657 * Queries a CPUID feature bit.
1658 *
1659 * @returns boolean for feature presence
1660 * @param pVM The VM Handle.
1661 * @param enmFeature The feature to query.
1662 */
1663VMMDECL(bool) CPUMGetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
1664{
1665 switch (enmFeature)
1666 {
1667 case CPUMCPUIDFEATURE_PAE:
1668 {
1669 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1670 return !!(pVM->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PAE);
1671 break;
1672 }
1673
1674 case CPUMCPUIDFEATURE_NXE:
1675 {
1676 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1677 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_AMD_FEATURE_EDX_NX);
1678 }
1679
1680 case CPUMCPUIDFEATURE_RDTSCP:
1681 {
1682 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1683 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
1684 break;
1685 }
1686
1687 case CPUMCPUIDFEATURE_LONG_MODE:
1688 {
1689 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1690 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE);
1691 break;
1692 }
1693
1694 default:
1695 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
1696 break;
1697 }
1698 return false;
1699}
1700
1701
1702/**
1703 * Clears a CPUID feature bit.
1704 *
1705 * @param pVM The VM Handle.
1706 * @param enmFeature The feature to clear.
1707 */
1708VMMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
1709{
1710 switch (enmFeature)
1711 {
1712 /*
1713 * Set the APIC bit in both feature masks.
1714 */
1715 case CPUMCPUIDFEATURE_APIC:
1716 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1717 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_APIC;
1718 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1719 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1720 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
1721 Log(("CPUMSetGuestCpuIdFeature: Disabled APIC\n"));
1722 break;
1723
1724 /*
1725 * Clear the x2APIC bit in the standard feature mask.
1726 */
1727 case CPUMCPUIDFEATURE_X2APIC:
1728 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1729 pVM->cpum.s.aGuestCpuIdStd[1].ecx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
1730 LogRel(("CPUMSetGuestCpuIdFeature: Disabled x2APIC\n"));
1731 break;
1732
1733 case CPUMCPUIDFEATURE_PAE:
1734 {
1735 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1736 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_PAE;
1737 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1738 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1739 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
1740 LogRel(("CPUMClearGuestCpuIdFeature: Disabled PAE!\n"));
1741 break;
1742 }
1743
1744 case CPUMCPUIDFEATURE_PAT:
1745 {
1746 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1747 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_PAT;
1748 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1749 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1750 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_PAT;
1751 LogRel(("CPUMClearGuestCpuIdFeature: Disabled PAT!\n"));
1752 break;
1753 }
1754
1755 case CPUMCPUIDFEATURE_LONG_MODE:
1756 {
1757 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1758 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_LONG_MODE;
1759 break;
1760 }
1761
1762 case CPUMCPUIDFEATURE_LAHF:
1763 {
1764 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1765 pVM->cpum.s.aGuestCpuIdExt[1].ecx &= ~X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF;
1766 break;
1767 }
1768
1769 default:
1770 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
1771 break;
1772 }
1773 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1774 {
1775 PVMCPU pVCpu = &pVM->aCpus[i];
1776 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CPUID;
1777 }
1778}
1779
1780
1781/**
1782 * Gets the host CPU vendor
1783 *
1784 * @returns CPU vendor
1785 * @param pVM The VM handle.
1786 */
1787VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM)
1788{
1789 return pVM->cpum.s.enmHostCpuVendor;
1790}
1791
1792/**
1793 * Gets the CPU vendor
1794 *
1795 * @returns CPU vendor
1796 * @param pVM The VM handle.
1797 */
1798VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM)
1799{
1800 return pVM->cpum.s.enmGuestCpuVendor;
1801}
1802
1803
1804VMMDECL(int) CPUMSetGuestDR0(PVMCPU pVCpu, uint64_t uDr0)
1805{
1806 pVCpu->cpum.s.Guest.dr[0] = uDr0;
1807 return CPUMRecalcHyperDRx(pVCpu);
1808}
1809
1810
1811VMMDECL(int) CPUMSetGuestDR1(PVMCPU pVCpu, uint64_t uDr1)
1812{
1813 pVCpu->cpum.s.Guest.dr[1] = uDr1;
1814 return CPUMRecalcHyperDRx(pVCpu);
1815}
1816
1817
1818VMMDECL(int) CPUMSetGuestDR2(PVMCPU pVCpu, uint64_t uDr2)
1819{
1820 pVCpu->cpum.s.Guest.dr[2] = uDr2;
1821 return CPUMRecalcHyperDRx(pVCpu);
1822}
1823
1824
1825VMMDECL(int) CPUMSetGuestDR3(PVMCPU pVCpu, uint64_t uDr3)
1826{
1827 pVCpu->cpum.s.Guest.dr[3] = uDr3;
1828 return CPUMRecalcHyperDRx(pVCpu);
1829}
1830
1831
1832VMMDECL(int) CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6)
1833{
1834 pVCpu->cpum.s.Guest.dr[6] = uDr6;
1835 return CPUMRecalcHyperDRx(pVCpu);
1836}
1837
1838
1839VMMDECL(int) CPUMSetGuestDR7(PVMCPU pVCpu, uint64_t uDr7)
1840{
1841 pVCpu->cpum.s.Guest.dr[7] = uDr7;
1842 return CPUMRecalcHyperDRx(pVCpu);
1843}
1844
1845
1846VMMDECL(int) CPUMSetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t Value)
1847{
1848 AssertReturn(iReg <= USE_REG_DR7, VERR_INVALID_PARAMETER);
1849 /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
1850 if (iReg == 4 || iReg == 5)
1851 iReg += 2;
1852 pVCpu->cpum.s.Guest.dr[iReg] = Value;
1853 return CPUMRecalcHyperDRx(pVCpu);
1854}
1855
1856
1857/**
1858 * Recalculates the hypvervisor DRx register values based on
1859 * current guest registers and DBGF breakpoints.
1860 *
1861 * This is called whenever a guest DRx register is modified and when DBGF
1862 * sets a hardware breakpoint. In guest context this function will reload
1863 * any (hyper) DRx registers which comes out with a different value.
1864 *
1865 * @returns VINF_SUCCESS.
1866 * @param pVCpu The VMCPU handle.
1867 */
1868VMMDECL(int) CPUMRecalcHyperDRx(PVMCPU pVCpu)
1869{
1870 PVM pVM = pVCpu->CTX_SUFF(pVM);
1871
1872 /*
1873 * Compare the DR7s first.
1874 *
1875 * We only care about the enabled flags. The GE and LE flags are always
1876 * set and we don't care if the guest doesn't set them. GD is virtualized
1877 * when we dispatch #DB, we never enable it.
1878 */
1879 const RTGCUINTREG uDbgfDr7 = DBGFBpGetDR7(pVM);
1880#ifdef CPUM_VIRTUALIZE_DRX
1881 const RTGCUINTREG uGstDr7 = CPUMGetGuestDR7(pVCpu);
1882#else
1883 const RTGCUINTREG uGstDr7 = 0;
1884#endif
1885 if ((uGstDr7 | uDbgfDr7) & X86_DR7_ENABLED_MASK)
1886 {
1887 /*
1888 * Ok, something is enabled. Recalc each of the breakpoints.
1889 * Straight forward code, not optimized/minimized in any way.
1890 */
1891 RTGCUINTREG uNewDr7 = X86_DR7_GE | X86_DR7_LE | X86_DR7_MB1_MASK;
1892
1893 /* bp 0 */
1894 RTGCUINTREG uNewDr0;
1895 if (uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0))
1896 {
1897 uNewDr7 |= uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
1898 uNewDr0 = DBGFBpGetDR0(pVM);
1899 }
1900 else if (uGstDr7 & (X86_DR7_L0 | X86_DR7_G0))
1901 {
1902 uNewDr7 |= uGstDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
1903 uNewDr0 = CPUMGetGuestDR0(pVCpu);
1904 }
1905 else
1906 uNewDr0 = pVCpu->cpum.s.Hyper.dr[0];
1907
1908 /* bp 1 */
1909 RTGCUINTREG uNewDr1;
1910 if (uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1))
1911 {
1912 uNewDr7 |= uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
1913 uNewDr1 = DBGFBpGetDR1(pVM);
1914 }
1915 else if (uGstDr7 & (X86_DR7_L1 | X86_DR7_G1))
1916 {
1917 uNewDr7 |= uGstDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
1918 uNewDr1 = CPUMGetGuestDR1(pVCpu);
1919 }
1920 else
1921 uNewDr1 = pVCpu->cpum.s.Hyper.dr[1];
1922
1923 /* bp 2 */
1924 RTGCUINTREG uNewDr2;
1925 if (uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2))
1926 {
1927 uNewDr7 |= uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
1928 uNewDr2 = DBGFBpGetDR2(pVM);
1929 }
1930 else if (uGstDr7 & (X86_DR7_L2 | X86_DR7_G2))
1931 {
1932 uNewDr7 |= uGstDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
1933 uNewDr2 = CPUMGetGuestDR2(pVCpu);
1934 }
1935 else
1936 uNewDr2 = pVCpu->cpum.s.Hyper.dr[2];
1937
1938 /* bp 3 */
1939 RTGCUINTREG uNewDr3;
1940 if (uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3))
1941 {
1942 uNewDr7 |= uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
1943 uNewDr3 = DBGFBpGetDR3(pVM);
1944 }
1945 else if (uGstDr7 & (X86_DR7_L3 | X86_DR7_G3))
1946 {
1947 uNewDr7 |= uGstDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
1948 uNewDr3 = CPUMGetGuestDR3(pVCpu);
1949 }
1950 else
1951 uNewDr3 = pVCpu->cpum.s.Hyper.dr[3];
1952
1953 /*
1954 * Apply the updates.
1955 */
1956#ifdef IN_RC
1957 if (!(pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS))
1958 {
1959 /** @todo save host DBx registers. */
1960 }
1961#endif
1962 pVCpu->cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS;
1963 if (uNewDr3 != pVCpu->cpum.s.Hyper.dr[3])
1964 CPUMSetHyperDR3(pVCpu, uNewDr3);
1965 if (uNewDr2 != pVCpu->cpum.s.Hyper.dr[2])
1966 CPUMSetHyperDR2(pVCpu, uNewDr2);
1967 if (uNewDr1 != pVCpu->cpum.s.Hyper.dr[1])
1968 CPUMSetHyperDR1(pVCpu, uNewDr1);
1969 if (uNewDr0 != pVCpu->cpum.s.Hyper.dr[0])
1970 CPUMSetHyperDR0(pVCpu, uNewDr0);
1971 if (uNewDr7 != pVCpu->cpum.s.Hyper.dr[7])
1972 CPUMSetHyperDR7(pVCpu, uNewDr7);
1973 }
1974 else
1975 {
1976#ifdef IN_RC
1977 if (pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS)
1978 {
1979 /** @todo restore host DBx registers. */
1980 }
1981#endif
1982 pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS;
1983 }
1984 Log2(("CPUMRecalcHyperDRx: fUseFlags=%#x %RGr %RGr %RGr %RGr %RGr %RGr\n",
1985 pVCpu->cpum.s.fUseFlags, pVCpu->cpum.s.Hyper.dr[0], pVCpu->cpum.s.Hyper.dr[1],
1986 pVCpu->cpum.s.Hyper.dr[2], pVCpu->cpum.s.Hyper.dr[3], pVCpu->cpum.s.Hyper.dr[6],
1987 pVCpu->cpum.s.Hyper.dr[7]));
1988
1989 return VINF_SUCCESS;
1990}
1991
1992
1993/**
1994 * Tests if the guest has No-Execute Page Protection Enabled (NXE).
1995 *
1996 * @returns true if in real mode, otherwise false.
1997 * @param pVCpu The virtual CPU handle.
1998 */
1999VMMDECL(bool) CPUMIsGuestNXEnabled(PVMCPU pVCpu)
2000{
2001 return !!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE);
2002}
2003
2004
2005/**
2006 * Tests if the guest has the Page Size Extension enabled (PSE).
2007 *
2008 * @returns true if in real mode, otherwise false.
2009 * @param pVCpu The virtual CPU handle.
2010 */
2011VMMDECL(bool) CPUMIsGuestPageSizeExtEnabled(PVMCPU pVCpu)
2012{
2013 /* PAE or AMD64 implies support for big pages regardless of CR4.PSE */
2014 return !!(pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PSE | X86_CR4_PAE));
2015}
2016
2017
2018/**
2019 * Tests if the guest has the paging enabled (PG).
2020 *
2021 * @returns true if in real mode, otherwise false.
2022 * @param pVCpu The virtual CPU handle.
2023 */
2024VMMDECL(bool) CPUMIsGuestPagingEnabled(PVMCPU pVCpu)
2025{
2026 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG);
2027}
2028
2029
2030/**
2031 * Tests if the guest has the paging enabled (PG).
2032 *
2033 * @returns true if in real mode, otherwise false.
2034 * @param pVCpu The virtual CPU handle.
2035 */
2036VMMDECL(bool) CPUMIsGuestR0WriteProtEnabled(PVMCPU pVCpu)
2037{
2038 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_WP);
2039}
2040
2041
2042/**
2043 * Tests if the guest is running in real mode or not.
2044 *
2045 * @returns true if in real mode, otherwise false.
2046 * @param pVCpu The virtual CPU handle.
2047 */
2048VMMDECL(bool) CPUMIsGuestInRealMode(PVMCPU pVCpu)
2049{
2050 return !(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
2051}
2052
2053
2054/**
2055 * Tests if the guest is running in protected or not.
2056 *
2057 * @returns true if in protected mode, otherwise false.
2058 * @param pVCpu The virtual CPU handle.
2059 */
2060VMMDECL(bool) CPUMIsGuestInProtectedMode(PVMCPU pVCpu)
2061{
2062 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
2063}
2064
2065
2066/**
2067 * Tests if the guest is running in paged protected or not.
2068 *
2069 * @returns true if in paged protected mode, otherwise false.
2070 * @param pVCpu The virtual CPU handle.
2071 */
2072VMMDECL(bool) CPUMIsGuestInPagedProtectedMode(PVMCPU pVCpu)
2073{
2074 return (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
2075}
2076
2077
2078/**
2079 * Tests if the guest is running in long mode or not.
2080 *
2081 * @returns true if in long mode, otherwise false.
2082 * @param pVCpu The virtual CPU handle.
2083 */
2084VMMDECL(bool) CPUMIsGuestInLongMode(PVMCPU pVCpu)
2085{
2086 return (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
2087}
2088
2089
2090/**
2091 * Tests if the guest is running in PAE mode or not.
2092 *
2093 * @returns true if in PAE mode, otherwise false.
2094 * @param pVCpu The virtual CPU handle.
2095 */
2096VMMDECL(bool) CPUMIsGuestInPAEMode(PVMCPU pVCpu)
2097{
2098 return (pVCpu->cpum.s.Guest.cr4 & X86_CR4_PAE)
2099 && (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG)
2100 && !(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA);
2101}
2102
2103
2104#ifndef IN_RING0
2105/**
2106 * Updates the EFLAGS while we're in raw-mode.
2107 *
2108 * @param pVCpu The VMCPU handle.
2109 * @param pCtxCore The context core.
2110 * @param eflags The new EFLAGS value.
2111 */
2112VMMDECL(void) CPUMRawSetEFlags(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, uint32_t eflags)
2113{
2114 PVM pVM = pVCpu->CTX_SUFF(pVM);
2115
2116 if (!pVCpu->cpum.s.fRawEntered)
2117 {
2118 pCtxCore->eflags.u32 = eflags;
2119 return;
2120 }
2121 PATMRawSetEFlags(pVM, pCtxCore, eflags);
2122}
2123#endif /* !IN_RING0 */
2124
2125
2126/**
2127 * Gets the EFLAGS while we're in raw-mode.
2128 *
2129 * @returns The eflags.
2130 * @param pVCpu The VMCPU handle.
2131 * @param pCtxCore The context core.
2132 */
2133VMMDECL(uint32_t) CPUMRawGetEFlags(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
2134{
2135#ifdef IN_RING0
2136 return pCtxCore->eflags.u32;
2137#else
2138 PVM pVM = pVCpu->CTX_SUFF(pVM);
2139
2140 if (!pVCpu->cpum.s.fRawEntered)
2141 return pCtxCore->eflags.u32;
2142 return PATMRawGetEFlags(pVM, pCtxCore);
2143#endif
2144}
2145
2146
2147/**
2148 * Sets the specified changed flags (CPUM_CHANGED_*).
2149 *
2150 * @param pVCpu The VMCPU handle.
2151 */
2152VMMDECL(void) CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedFlags)
2153{
2154 pVCpu->cpum.s.fChanged |= fChangedFlags;
2155}
2156
2157
2158/**
2159 * Checks if the CPU supports the FXSAVE and FXRSTOR instruction.
2160 * @returns true if supported.
2161 * @returns false if not supported.
2162 * @param pVM The VM handle.
2163 */
2164VMMDECL(bool) CPUMSupportsFXSR(PVM pVM)
2165{
2166 return pVM->cpum.s.CPUFeatures.edx.u1FXSR != 0;
2167}
2168
2169
2170/**
2171 * Checks if the host OS uses the SYSENTER / SYSEXIT instructions.
2172 * @returns true if used.
2173 * @returns false if not used.
2174 * @param pVM The VM handle.
2175 */
2176VMMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM)
2177{
2178 return (pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSENTER) != 0;
2179}
2180
2181
2182/**
2183 * Checks if the host OS uses the SYSCALL / SYSRET instructions.
2184 * @returns true if used.
2185 * @returns false if not used.
2186 * @param pVM The VM handle.
2187 */
2188VMMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM)
2189{
2190 return (pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSCALL) != 0;
2191}
2192
2193#ifndef IN_RING3
2194
2195/**
2196 * Lazily sync in the FPU/XMM state
2197 *
2198 * @returns VBox status code.
2199 * @param pVCpu VMCPU handle
2200 */
2201VMMDECL(int) CPUMHandleLazyFPU(PVMCPU pVCpu)
2202{
2203 return cpumHandleLazyFPUAsm(&pVCpu->cpum.s);
2204}
2205
2206#endif /* !IN_RING3 */
2207
2208/**
2209 * Checks if we activated the FPU/XMM state of the guest OS
2210 * @returns true if we did.
2211 * @returns false if not.
2212 * @param pVCpu The VMCPU handle.
2213 */
2214VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCpu)
2215{
2216 return (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU) != 0;
2217}
2218
2219
2220/**
2221 * Deactivate the FPU/XMM state of the guest OS
2222 * @param pVCpu The VMCPU handle.
2223 */
2224VMMDECL(void) CPUMDeactivateGuestFPUState(PVMCPU pVCpu)
2225{
2226 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU;
2227}
2228
2229
2230/**
2231 * Checks if the guest debug state is active
2232 *
2233 * @returns boolean
2234 * @param pVM VM handle.
2235 */
2236VMMDECL(bool) CPUMIsGuestDebugStateActive(PVMCPU pVCpu)
2237{
2238 return (pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS) != 0;
2239}
2240
2241/**
2242 * Checks if the hyper debug state is active
2243 *
2244 * @returns boolean
2245 * @param pVM VM handle.
2246 */
2247VMMDECL(bool) CPUMIsHyperDebugStateActive(PVMCPU pVCpu)
2248{
2249 return (pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS_HYPER) != 0;
2250}
2251
2252
2253/**
2254 * Mark the guest's debug state as inactive.
2255 *
2256 * @returns boolean
2257 * @param pVM VM handle.
2258 */
2259VMMDECL(void) CPUMDeactivateGuestDebugState(PVMCPU pVCpu)
2260{
2261 pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS;
2262}
2263
2264
2265/**
2266 * Mark the hypervisor's debug state as inactive.
2267 *
2268 * @returns boolean
2269 * @param pVM VM handle.
2270 */
2271VMMDECL(void) CPUMDeactivateHyperDebugState(PVMCPU pVCpu)
2272{
2273 pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS_HYPER;
2274}
2275
2276/**
2277 * Checks if the hidden selector registers are valid for the specified CPU.
2278 *
2279 * @returns true if they are.
2280 * @returns false if not.
2281 * @param pVCpu The VM handle.
2282 */
2283VMMDECL(bool) CPUMAreHiddenSelRegsValid(PVMCPU pVCpu)
2284{
2285 bool const fRc = !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID);
2286 Assert(fRc || !HWACCMIsEnabled(pVCpu->CTX_SUFF(pVM)));
2287 Assert(!pVCpu->cpum.s.fRemEntered);
2288 return fRc;
2289}
2290
2291
2292
2293/**
2294 * Get the current privilege level of the guest.
2295 *
2296 * @returns cpl
2297 * @param pVM VM Handle.
2298 * @param pRegFrame Trap register frame.
2299 */
2300VMMDECL(uint32_t) CPUMGetGuestCPL(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
2301{
2302 uint32_t cpl;
2303
2304 if (CPUMAreHiddenSelRegsValid(pVCpu))
2305 {
2306 /*
2307 * The hidden CS.DPL register is always equal to the CPL, it is
2308 * not affected by loading a conforming coding segment.
2309 *
2310 * This only seems to apply to AMD-V; in the VT-x case we *do* need to look
2311 * at SS. (ACP2 regression during install after a far call to ring 2)
2312 */
2313 if (RT_LIKELY(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
2314 {
2315 if (!pCtxCore->eflags.Bits.u1VM)
2316 cpl = pCtxCore->ssHid.Attr.n.u2Dpl;
2317 else
2318 cpl = 3; /* REM doesn't set DPL=3 in V8086 mode. See #5130. */
2319 }
2320 else
2321 cpl = 0; /* CPL set to 3 for VT-x real-mode emulation. */
2322 }
2323 else if (RT_LIKELY(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
2324 {
2325 if (RT_LIKELY(!pCtxCore->eflags.Bits.u1VM))
2326 {
2327 /*
2328 * The SS RPL is always equal to the CPL, while the CS RPL
2329 * isn't necessarily equal if the segment is conforming.
2330 * See section 4.11.1 in the AMD manual.
2331 */
2332 cpl = (pCtxCore->ss & X86_SEL_RPL);
2333#ifndef IN_RING0
2334 if (cpl == 1)
2335 cpl = 0;
2336#endif
2337 }
2338 else
2339 cpl = 3;
2340 }
2341 else
2342 cpl = 0; /* real mode; cpl is zero */
2343
2344 return cpl;
2345}
2346
2347
2348/**
2349 * Gets the current guest CPU mode.
2350 *
2351 * If paging mode is what you need, check out PGMGetGuestMode().
2352 *
2353 * @returns The CPU mode.
2354 * @param pVCpu The VMCPU handle.
2355 */
2356VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu)
2357{
2358 CPUMMODE enmMode;
2359 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
2360 enmMode = CPUMMODE_REAL;
2361 else if (!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
2362 enmMode = CPUMMODE_PROTECTED;
2363 else
2364 enmMode = CPUMMODE_LONG;
2365
2366 return enmMode;
2367}
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