VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp@ 36762

Last change on this file since 36762 was 36762, checked in by vboxsync, 14 years ago

CPUM: CPUMSetGuestGDTR and CPUMSetGuestIDTR should take 64-bit base value.
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1/* $Id: CPUMAllRegs.cpp 36762 2011-04-20 16:52:26Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor(/Manager) - Getters and Setters.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_CPUM
23#include <VBox/vmm/cpum.h>
24#include <VBox/vmm/patm.h>
25#include <VBox/vmm/dbgf.h>
26#include <VBox/vmm/pdm.h>
27#include <VBox/vmm/pgm.h>
28#include <VBox/vmm/mm.h>
29#include "CPUMInternal.h"
30#include <VBox/vmm/vm.h>
31#include <VBox/err.h>
32#include <VBox/dis.h>
33#include <VBox/log.h>
34#include <VBox/vmm/hwaccm.h>
35#include <VBox/vmm/tm.h>
36#include <iprt/assert.h>
37#include <iprt/asm.h>
38#include <iprt/asm-amd64-x86.h>
39#ifdef IN_RING3
40#include <iprt/thread.h>
41#endif
42
43/** Disable stack frame pointer generation here. */
44#if defined(_MSC_VER) && !defined(DEBUG)
45# pragma optimize("y", off)
46#endif
47
48
49/**
50 * Sets or resets an alternative hypervisor context core.
51 *
52 * This is called when we get a hypervisor trap set switch the context
53 * core with the trap frame on the stack. It is called again to reset
54 * back to the default context core when resuming hypervisor execution.
55 *
56 * @param pVCpu The VMCPU handle.
57 * @param pCtxCore Pointer to the alternative context core or NULL
58 * to go back to the default context core.
59 */
60VMMDECL(void) CPUMHyperSetCtxCore(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
61{
62 PVM pVM = pVCpu->CTX_SUFF(pVM);
63
64 LogFlow(("CPUMHyperSetCtxCore: %p/%p/%p -> %p\n", pVCpu->cpum.s.CTX_SUFF(pHyperCore), pCtxCore));
65 if (!pCtxCore)
66 {
67 pCtxCore = CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
68 pVCpu->cpum.s.pHyperCoreR3 = (R3PTRTYPE(PCPUMCTXCORE))VM_R3_ADDR(pVM, pCtxCore);
69 pVCpu->cpum.s.pHyperCoreR0 = (R0PTRTYPE(PCPUMCTXCORE))VM_R0_ADDR(pVM, pCtxCore);
70 pVCpu->cpum.s.pHyperCoreRC = (RCPTRTYPE(PCPUMCTXCORE))VM_RC_ADDR(pVM, pCtxCore);
71 }
72 else
73 {
74 pVCpu->cpum.s.pHyperCoreR3 = (R3PTRTYPE(PCPUMCTXCORE))MMHyperCCToR3(pVM, pCtxCore);
75 pVCpu->cpum.s.pHyperCoreR0 = (R0PTRTYPE(PCPUMCTXCORE))MMHyperCCToR0(pVM, pCtxCore);
76 pVCpu->cpum.s.pHyperCoreRC = (RCPTRTYPE(PCPUMCTXCORE))MMHyperCCToRC(pVM, pCtxCore);
77 }
78}
79
80
81/**
82 * Gets the pointer to the internal CPUMCTXCORE structure for the hypervisor.
83 * This is only for reading in order to save a few calls.
84 *
85 * @param pVM Handle to the virtual machine.
86 */
87VMMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVMCPU pVCpu)
88{
89 return pVCpu->cpum.s.CTX_SUFF(pHyperCore);
90}
91
92
93/**
94 * Queries the pointer to the internal CPUMCTX structure for the hypervisor.
95 *
96 * @returns VBox status code.
97 * @param pVM Handle to the virtual machine.
98 * @param ppCtx Receives the hyper CPUMCTX pointer when successful.
99 *
100 * @deprecated This will *not* (and has never) given the right picture of the
101 * hypervisor register state. With CPUMHyperSetCtxCore() this is
102 * getting much worse. So, use the individual functions for getting
103 * and esp. setting the hypervisor registers.
104 */
105VMMDECL(int) CPUMQueryHyperCtxPtr(PVMCPU pVCpu, PCPUMCTX *ppCtx)
106{
107 *ppCtx = &pVCpu->cpum.s.Hyper;
108 return VINF_SUCCESS;
109}
110
111
112VMMDECL(void) CPUMSetHyperGDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
113{
114 pVCpu->cpum.s.Hyper.gdtr.cbGdt = limit;
115 pVCpu->cpum.s.Hyper.gdtr.pGdt = addr;
116 pVCpu->cpum.s.Hyper.gdtrPadding = 0;
117}
118
119
120VMMDECL(void) CPUMSetHyperIDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
121{
122 pVCpu->cpum.s.Hyper.idtr.cbIdt = limit;
123 pVCpu->cpum.s.Hyper.idtr.pIdt = addr;
124 pVCpu->cpum.s.Hyper.idtrPadding = 0;
125}
126
127
128VMMDECL(void) CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3)
129{
130 pVCpu->cpum.s.Hyper.cr3 = cr3;
131
132#ifdef IN_RC
133 /* Update the current CR3. */
134 ASMSetCR3(cr3);
135#endif
136}
137
138VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu)
139{
140 return pVCpu->cpum.s.Hyper.cr3;
141}
142
143
144VMMDECL(void) CPUMSetHyperCS(PVMCPU pVCpu, RTSEL SelCS)
145{
146 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->cs = SelCS;
147}
148
149
150VMMDECL(void) CPUMSetHyperDS(PVMCPU pVCpu, RTSEL SelDS)
151{
152 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ds = SelDS;
153}
154
155
156VMMDECL(void) CPUMSetHyperES(PVMCPU pVCpu, RTSEL SelES)
157{
158 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->es = SelES;
159}
160
161
162VMMDECL(void) CPUMSetHyperFS(PVMCPU pVCpu, RTSEL SelFS)
163{
164 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->fs = SelFS;
165}
166
167
168VMMDECL(void) CPUMSetHyperGS(PVMCPU pVCpu, RTSEL SelGS)
169{
170 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->gs = SelGS;
171}
172
173
174VMMDECL(void) CPUMSetHyperSS(PVMCPU pVCpu, RTSEL SelSS)
175{
176 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ss = SelSS;
177}
178
179
180VMMDECL(void) CPUMSetHyperESP(PVMCPU pVCpu, uint32_t u32ESP)
181{
182 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->esp = u32ESP;
183}
184
185
186VMMDECL(int) CPUMSetHyperEFlags(PVMCPU pVCpu, uint32_t Efl)
187{
188 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->eflags.u32 = Efl;
189 return VINF_SUCCESS;
190}
191
192
193VMMDECL(void) CPUMSetHyperEIP(PVMCPU pVCpu, uint32_t u32EIP)
194{
195 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->eip = u32EIP;
196}
197
198
199VMMDECL(void) CPUMSetHyperTR(PVMCPU pVCpu, RTSEL SelTR)
200{
201 pVCpu->cpum.s.Hyper.tr = SelTR;
202}
203
204
205VMMDECL(void) CPUMSetHyperLDTR(PVMCPU pVCpu, RTSEL SelLDTR)
206{
207 pVCpu->cpum.s.Hyper.ldtr = SelLDTR;
208}
209
210
211VMMDECL(void) CPUMSetHyperDR0(PVMCPU pVCpu, RTGCUINTREG uDr0)
212{
213 pVCpu->cpum.s.Hyper.dr[0] = uDr0;
214 /** @todo in GC we must load it! */
215}
216
217
218VMMDECL(void) CPUMSetHyperDR1(PVMCPU pVCpu, RTGCUINTREG uDr1)
219{
220 pVCpu->cpum.s.Hyper.dr[1] = uDr1;
221 /** @todo in GC we must load it! */
222}
223
224
225VMMDECL(void) CPUMSetHyperDR2(PVMCPU pVCpu, RTGCUINTREG uDr2)
226{
227 pVCpu->cpum.s.Hyper.dr[2] = uDr2;
228 /** @todo in GC we must load it! */
229}
230
231
232VMMDECL(void) CPUMSetHyperDR3(PVMCPU pVCpu, RTGCUINTREG uDr3)
233{
234 pVCpu->cpum.s.Hyper.dr[3] = uDr3;
235 /** @todo in GC we must load it! */
236}
237
238
239VMMDECL(void) CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6)
240{
241 pVCpu->cpum.s.Hyper.dr[6] = uDr6;
242 /** @todo in GC we must load it! */
243}
244
245
246VMMDECL(void) CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7)
247{
248 pVCpu->cpum.s.Hyper.dr[7] = uDr7;
249 /** @todo in GC we must load it! */
250}
251
252
253VMMDECL(RTSEL) CPUMGetHyperCS(PVMCPU pVCpu)
254{
255 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->cs;
256}
257
258
259VMMDECL(RTSEL) CPUMGetHyperDS(PVMCPU pVCpu)
260{
261 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ds;
262}
263
264
265VMMDECL(RTSEL) CPUMGetHyperES(PVMCPU pVCpu)
266{
267 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->es;
268}
269
270
271VMMDECL(RTSEL) CPUMGetHyperFS(PVMCPU pVCpu)
272{
273 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->fs;
274}
275
276
277VMMDECL(RTSEL) CPUMGetHyperGS(PVMCPU pVCpu)
278{
279 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->gs;
280}
281
282
283VMMDECL(RTSEL) CPUMGetHyperSS(PVMCPU pVCpu)
284{
285 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ss;
286}
287
288
289VMMDECL(uint32_t) CPUMGetHyperEAX(PVMCPU pVCpu)
290{
291 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->eax;
292}
293
294
295VMMDECL(uint32_t) CPUMGetHyperEBX(PVMCPU pVCpu)
296{
297 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ebx;
298}
299
300
301VMMDECL(uint32_t) CPUMGetHyperECX(PVMCPU pVCpu)
302{
303 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ecx;
304}
305
306
307VMMDECL(uint32_t) CPUMGetHyperEDX(PVMCPU pVCpu)
308{
309 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->edx;
310}
311
312
313VMMDECL(uint32_t) CPUMGetHyperESI(PVMCPU pVCpu)
314{
315 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->esi;
316}
317
318
319VMMDECL(uint32_t) CPUMGetHyperEDI(PVMCPU pVCpu)
320{
321 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->edi;
322}
323
324
325VMMDECL(uint32_t) CPUMGetHyperEBP(PVMCPU pVCpu)
326{
327 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ebp;
328}
329
330
331VMMDECL(uint32_t) CPUMGetHyperESP(PVMCPU pVCpu)
332{
333 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->esp;
334}
335
336
337VMMDECL(uint32_t) CPUMGetHyperEFlags(PVMCPU pVCpu)
338{
339 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->eflags.u32;
340}
341
342
343VMMDECL(uint32_t) CPUMGetHyperEIP(PVMCPU pVCpu)
344{
345 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->eip;
346}
347
348
349VMMDECL(uint64_t) CPUMGetHyperRIP(PVMCPU pVCpu)
350{
351 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->rip;
352}
353
354
355VMMDECL(uint32_t) CPUMGetHyperIDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
356{
357 if (pcbLimit)
358 *pcbLimit = pVCpu->cpum.s.Hyper.idtr.cbIdt;
359 return pVCpu->cpum.s.Hyper.idtr.pIdt;
360}
361
362
363VMMDECL(uint32_t) CPUMGetHyperGDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
364{
365 if (pcbLimit)
366 *pcbLimit = pVCpu->cpum.s.Hyper.gdtr.cbGdt;
367 return pVCpu->cpum.s.Hyper.gdtr.pGdt;
368}
369
370
371VMMDECL(RTSEL) CPUMGetHyperLDTR(PVMCPU pVCpu)
372{
373 return pVCpu->cpum.s.Hyper.ldtr;
374}
375
376
377VMMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVMCPU pVCpu)
378{
379 return pVCpu->cpum.s.Hyper.dr[0];
380}
381
382
383VMMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVMCPU pVCpu)
384{
385 return pVCpu->cpum.s.Hyper.dr[1];
386}
387
388
389VMMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVMCPU pVCpu)
390{
391 return pVCpu->cpum.s.Hyper.dr[2];
392}
393
394
395VMMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVMCPU pVCpu)
396{
397 return pVCpu->cpum.s.Hyper.dr[3];
398}
399
400
401VMMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVMCPU pVCpu)
402{
403 return pVCpu->cpum.s.Hyper.dr[6];
404}
405
406
407VMMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVMCPU pVCpu)
408{
409 return pVCpu->cpum.s.Hyper.dr[7];
410}
411
412
413/**
414 * Gets the pointer to the internal CPUMCTXCORE structure.
415 * This is only for reading in order to save a few calls.
416 *
417 * @param pVCpu Handle to the virtual cpu.
418 */
419VMMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVMCPU pVCpu)
420{
421 return CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
422}
423
424
425/**
426 * Sets the guest context core registers.
427 *
428 * @param pVCpu Handle to the virtual cpu.
429 * @param pCtxCore The new context core values.
430 */
431VMMDECL(void) CPUMSetGuestCtxCore(PVMCPU pVCpu, PCCPUMCTXCORE pCtxCore)
432{
433 /** @todo #1410 requires selectors to be checked. (huh? 1410?) */
434
435 PCPUMCTXCORE pCtxCoreDst = CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
436 *pCtxCoreDst = *pCtxCore;
437
438 /* Mask away invalid parts of the cpu context. */
439 if (!CPUMIsGuestInLongMode(pVCpu))
440 {
441 uint64_t u64Mask = UINT64_C(0xffffffff);
442
443 pCtxCoreDst->rip &= u64Mask;
444 pCtxCoreDst->rax &= u64Mask;
445 pCtxCoreDst->rbx &= u64Mask;
446 pCtxCoreDst->rcx &= u64Mask;
447 pCtxCoreDst->rdx &= u64Mask;
448 pCtxCoreDst->rsi &= u64Mask;
449 pCtxCoreDst->rdi &= u64Mask;
450 pCtxCoreDst->rbp &= u64Mask;
451 pCtxCoreDst->rsp &= u64Mask;
452 pCtxCoreDst->rflags.u &= u64Mask;
453
454 pCtxCoreDst->r8 = 0;
455 pCtxCoreDst->r9 = 0;
456 pCtxCoreDst->r10 = 0;
457 pCtxCoreDst->r11 = 0;
458 pCtxCoreDst->r12 = 0;
459 pCtxCoreDst->r13 = 0;
460 pCtxCoreDst->r14 = 0;
461 pCtxCoreDst->r15 = 0;
462 }
463}
464
465
466/**
467 * Queries the pointer to the internal CPUMCTX structure
468 *
469 * @returns The CPUMCTX pointer.
470 * @param pVCpu Handle to the virtual cpu.
471 */
472VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu)
473{
474 return &pVCpu->cpum.s.Guest;
475}
476
477VMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit)
478{
479 pVCpu->cpum.s.Guest.gdtr.cbGdt = cbLimit;
480 pVCpu->cpum.s.Guest.gdtr.pGdt = GCPtrBase;
481 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GDTR;
482 return VINF_SUCCESS;
483}
484
485VMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit)
486{
487 pVCpu->cpum.s.Guest.idtr.cbIdt = cbLimit;
488 pVCpu->cpum.s.Guest.idtr.pIdt = GCPtrBase;
489 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_IDTR;
490 return VINF_SUCCESS;
491}
492
493VMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr)
494{
495 AssertMsgFailed(("Need to load the hidden bits too!\n"));
496
497 pVCpu->cpum.s.Guest.tr = tr;
498 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_TR;
499 return VINF_SUCCESS;
500}
501
502VMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr)
503{
504 pVCpu->cpum.s.Guest.ldtr = ldtr;
505 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_LDTR;
506 return VINF_SUCCESS;
507}
508
509
510/**
511 * Set the guest CR0.
512 *
513 * When called in GC, the hyper CR0 may be updated if that is
514 * required. The caller only has to take special action if AM,
515 * WP, PG or PE changes.
516 *
517 * @returns VINF_SUCCESS (consider it void).
518 * @param pVCpu Handle to the virtual cpu.
519 * @param cr0 The new CR0 value.
520 */
521VMMDECL(int) CPUMSetGuestCR0(PVMCPU pVCpu, uint64_t cr0)
522{
523#ifdef IN_RC
524 /*
525 * Check if we need to change hypervisor CR0 because
526 * of math stuff.
527 */
528 if ( (cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP))
529 != (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP)))
530 {
531 if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU))
532 {
533 /*
534 * We haven't saved the host FPU state yet, so TS and MT are both set
535 * and EM should be reflecting the guest EM (it always does this).
536 */
537 if ((cr0 & X86_CR0_EM) != (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM))
538 {
539 uint32_t HyperCR0 = ASMGetCR0();
540 AssertMsg((HyperCR0 & (X86_CR0_TS | X86_CR0_MP)) == (X86_CR0_TS | X86_CR0_MP), ("%#x\n", HyperCR0));
541 AssertMsg((HyperCR0 & X86_CR0_EM) == (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM), ("%#x\n", HyperCR0));
542 HyperCR0 &= ~X86_CR0_EM;
543 HyperCR0 |= cr0 & X86_CR0_EM;
544 Log(("CPUM New HyperCR0=%#x\n", HyperCR0));
545 ASMSetCR0(HyperCR0);
546 }
547# ifdef VBOX_STRICT
548 else
549 {
550 uint32_t HyperCR0 = ASMGetCR0();
551 AssertMsg((HyperCR0 & (X86_CR0_TS | X86_CR0_MP)) == (X86_CR0_TS | X86_CR0_MP), ("%#x\n", HyperCR0));
552 AssertMsg((HyperCR0 & X86_CR0_EM) == (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM), ("%#x\n", HyperCR0));
553 }
554# endif
555 }
556 else
557 {
558 /*
559 * Already saved the state, so we're just mirroring
560 * the guest flags.
561 */
562 uint32_t HyperCR0 = ASMGetCR0();
563 AssertMsg( (HyperCR0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP))
564 == (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP)),
565 ("%#x %#x\n", HyperCR0, pVCpu->cpum.s.Guest.cr0));
566 HyperCR0 &= ~(X86_CR0_TS | X86_CR0_EM | X86_CR0_MP);
567 HyperCR0 |= cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP);
568 Log(("CPUM New HyperCR0=%#x\n", HyperCR0));
569 ASMSetCR0(HyperCR0);
570 }
571 }
572#endif /* IN_RC */
573
574 /*
575 * Check for changes causing TLB flushes (for REM).
576 * The caller is responsible for calling PGM when appropriate.
577 */
578 if ( (cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE))
579 != (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)))
580 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
581 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR0;
582
583 pVCpu->cpum.s.Guest.cr0 = cr0 | X86_CR0_ET;
584 return VINF_SUCCESS;
585}
586
587
588VMMDECL(int) CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2)
589{
590 pVCpu->cpum.s.Guest.cr2 = cr2;
591 return VINF_SUCCESS;
592}
593
594
595VMMDECL(int) CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3)
596{
597 pVCpu->cpum.s.Guest.cr3 = cr3;
598 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR3;
599 return VINF_SUCCESS;
600}
601
602
603VMMDECL(int) CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4)
604{
605 if ( (cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE))
606 != (pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE)))
607 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
608 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR4;
609 if (!CPUMSupportsFXSR(pVCpu->CTX_SUFF(pVM)))
610 cr4 &= ~X86_CR4_OSFSXR;
611 pVCpu->cpum.s.Guest.cr4 = cr4;
612 return VINF_SUCCESS;
613}
614
615
616VMMDECL(int) CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags)
617{
618 pVCpu->cpum.s.Guest.eflags.u32 = eflags;
619 return VINF_SUCCESS;
620}
621
622
623VMMDECL(int) CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip)
624{
625 pVCpu->cpum.s.Guest.eip = eip;
626 return VINF_SUCCESS;
627}
628
629
630VMMDECL(int) CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax)
631{
632 pVCpu->cpum.s.Guest.eax = eax;
633 return VINF_SUCCESS;
634}
635
636
637VMMDECL(int) CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx)
638{
639 pVCpu->cpum.s.Guest.ebx = ebx;
640 return VINF_SUCCESS;
641}
642
643
644VMMDECL(int) CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx)
645{
646 pVCpu->cpum.s.Guest.ecx = ecx;
647 return VINF_SUCCESS;
648}
649
650
651VMMDECL(int) CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx)
652{
653 pVCpu->cpum.s.Guest.edx = edx;
654 return VINF_SUCCESS;
655}
656
657
658VMMDECL(int) CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp)
659{
660 pVCpu->cpum.s.Guest.esp = esp;
661 return VINF_SUCCESS;
662}
663
664
665VMMDECL(int) CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp)
666{
667 pVCpu->cpum.s.Guest.ebp = ebp;
668 return VINF_SUCCESS;
669}
670
671
672VMMDECL(int) CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi)
673{
674 pVCpu->cpum.s.Guest.esi = esi;
675 return VINF_SUCCESS;
676}
677
678
679VMMDECL(int) CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi)
680{
681 pVCpu->cpum.s.Guest.edi = edi;
682 return VINF_SUCCESS;
683}
684
685
686VMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss)
687{
688 pVCpu->cpum.s.Guest.ss = ss;
689 return VINF_SUCCESS;
690}
691
692
693VMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs)
694{
695 pVCpu->cpum.s.Guest.cs = cs;
696 return VINF_SUCCESS;
697}
698
699
700VMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds)
701{
702 pVCpu->cpum.s.Guest.ds = ds;
703 return VINF_SUCCESS;
704}
705
706
707VMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es)
708{
709 pVCpu->cpum.s.Guest.es = es;
710 return VINF_SUCCESS;
711}
712
713
714VMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs)
715{
716 pVCpu->cpum.s.Guest.fs = fs;
717 return VINF_SUCCESS;
718}
719
720
721VMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs)
722{
723 pVCpu->cpum.s.Guest.gs = gs;
724 return VINF_SUCCESS;
725}
726
727
728VMMDECL(void) CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val)
729{
730 pVCpu->cpum.s.Guest.msrEFER = val;
731}
732
733
734/**
735 * Query an MSR.
736 *
737 * The caller is responsible for checking privilege if the call is the result
738 * of a RDMSR instruction. We'll do the rest.
739 *
740 * @retval VINF_SUCCESS on success.
741 * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR), the caller is
742 * expected to take the appropriate actions. @a *puValue is set to 0.
743 * @param pVCpu The virtual CPU to operate on.
744 * @param idMsr The MSR.
745 * @param puValue Where to return the value..
746 *
747 * @remarks This will always return the right values, even when we're in the
748 * recompiler.
749 */
750VMMDECL(int) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue)
751{
752 /*
753 * If we don't indicate MSR support in the CPUID feature bits, indicate
754 * that a #GP(0) should be raised.
755 */
756 if (!(pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_MSR))
757 {
758 *puValue = 0;
759 return VERR_CPUM_RAISE_GP_0;
760 }
761
762 int rc = VINF_SUCCESS;
763 uint8_t const u8Multiplier = 4;
764 switch (idMsr)
765 {
766 case MSR_IA32_TSC:
767 *puValue = TMCpuTickGet(pVCpu);
768 break;
769
770 case MSR_IA32_APICBASE:
771 rc = PDMApicGetBase(pVCpu->CTX_SUFF(pVM), puValue);
772 if (RT_SUCCESS(rc))
773 rc = VINF_SUCCESS;
774 else
775 {
776 *puValue = 0;
777 rc = VERR_CPUM_RAISE_GP_0;
778 }
779 break;
780
781 case MSR_IA32_CR_PAT:
782 *puValue = pVCpu->cpum.s.Guest.msrPAT;
783 break;
784
785 case MSR_IA32_SYSENTER_CS:
786 *puValue = pVCpu->cpum.s.Guest.SysEnter.cs;
787 break;
788
789 case MSR_IA32_SYSENTER_EIP:
790 *puValue = pVCpu->cpum.s.Guest.SysEnter.eip;
791 break;
792
793 case MSR_IA32_SYSENTER_ESP:
794 *puValue = pVCpu->cpum.s.Guest.SysEnter.esp;
795 break;
796
797 case MSR_K6_EFER:
798 *puValue = pVCpu->cpum.s.Guest.msrEFER;
799 break;
800
801 case MSR_K8_SF_MASK:
802 *puValue = pVCpu->cpum.s.Guest.msrSFMASK;
803 break;
804
805 case MSR_K6_STAR:
806 *puValue = pVCpu->cpum.s.Guest.msrSTAR;
807 break;
808
809 case MSR_K8_LSTAR:
810 *puValue = pVCpu->cpum.s.Guest.msrLSTAR;
811 break;
812
813 case MSR_K8_CSTAR:
814 *puValue = pVCpu->cpum.s.Guest.msrCSTAR;
815 break;
816
817 case MSR_K8_FS_BASE:
818 *puValue = pVCpu->cpum.s.Guest.fsHid.u64Base;
819 break;
820
821 case MSR_K8_GS_BASE:
822 *puValue = pVCpu->cpum.s.Guest.gsHid.u64Base;
823 break;
824
825 case MSR_K8_KERNEL_GS_BASE:
826 *puValue = pVCpu->cpum.s.Guest.msrKERNELGSBASE;
827 break;
828
829 case MSR_K8_TSC_AUX:
830 *puValue = pVCpu->cpum.s.GuestMsr.msr.tscAux;
831 break;
832
833 case MSR_IA32_PERF_STATUS:
834 /** @todo could really be not exactly correct, maybe use host's values */
835 *puValue = UINT64_C(1000) /* TSC increment by tick */
836 | ((uint64_t)u8Multiplier << 24) /* CPU multiplier (aka bus ratio) min */
837 | ((uint64_t)u8Multiplier << 40) /* CPU multiplier (aka bus ratio) max */;
838 break;
839
840 case MSR_IA32_FSB_CLOCK_STS:
841 /*
842 * Encoded as:
843 * 0 - 266
844 * 1 - 133
845 * 2 - 200
846 * 3 - return 166
847 * 5 - return 100
848 */
849 *puValue = (2 << 4);
850 break;
851
852 case MSR_IA32_PLATFORM_INFO:
853 *puValue = (u8Multiplier << 8) /* Flex ratio max */
854 | ((uint64_t)u8Multiplier << 40) /* Flex ratio min */;
855 break;
856
857 case MSR_IA32_THERM_STATUS:
858 /* CPU temperature relative to TCC, to actually activate, CPUID leaf 6 EAX[0] must be set */
859 *puValue = ( 1 << 31) /* validity bit */
860 | (20 << 16) /* degrees till TCC */;
861 break;
862
863 case MSR_IA32_MISC_ENABLE:
864#if 0
865 /* Needs to be tested more before enabling. */
866 *puValue = pVCpu->cpum.s.GuestMsr.msr.miscEnable;
867#else
868 /* Currenty we don't allow guests to modify enable MSRs. */
869 *puValue = MSR_IA32_MISC_ENABLE_FAST_STRINGS /* by default */;
870
871 if ((pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR) != 0)
872
873 *puValue |= MSR_IA32_MISC_ENABLE_MONITOR /* if mwait/monitor available */;
874 /** @todo: add more cpuid-controlled features this way. */
875#endif
876 break;
877
878#if 0 /*def IN_RING0 */
879 case MSR_IA32_PLATFORM_ID:
880 case MSR_IA32_BIOS_SIGN_ID:
881 if (CPUMGetCPUVendor(pVM) == CPUMCPUVENDOR_INTEL)
882 {
883 /* Available since the P6 family. VT-x implies that this feature is present. */
884 if (idMsr == MSR_IA32_PLATFORM_ID)
885 *puValue = ASMRdMsr(MSR_IA32_PLATFORM_ID);
886 else if (idMsr == MSR_IA32_BIOS_SIGN_ID)
887 *puValue = ASMRdMsr(MSR_IA32_BIOS_SIGN_ID);
888 break;
889 }
890 /* no break */
891#endif
892
893 default:
894 /* In X2APIC specification this range is reserved for APIC control. */
895 if ( idMsr >= MSR_IA32_APIC_START
896 && idMsr < MSR_IA32_APIC_END)
897 {
898 rc = PDMApicReadMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, puValue);
899 if (RT_SUCCESS(rc))
900 rc = VINF_SUCCESS;
901 else
902 {
903 *puValue = 0;
904 rc = VERR_CPUM_RAISE_GP_0;
905 }
906 }
907 else
908 {
909 *puValue = 0;
910 rc = VERR_CPUM_RAISE_GP_0;
911 }
912 break;
913 }
914
915 return rc;
916}
917
918
919/**
920 * Sets the MSR.
921 *
922 * The caller is responsible for checking privilege if the call is the result
923 * of a WRMSR instruction. We'll do the rest.
924 *
925 * @retval VINF_SUCCESS on success.
926 * @retval VERR_CPUM_RAISE_GP_0 on failure, the caller is expected to take the
927 * appropriate actions.
928 *
929 * @param pVCpu The virtual CPU to operate on.
930 * @param idMsr The MSR id.
931 * @param uValue The value to set.
932 *
933 * @remarks Everyone changing MSR values, including the recompiler, shall do it
934 * by calling this method. This makes sure we have current values and
935 * that we trigger all the right actions when something changes.
936 */
937VMMDECL(int) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue)
938{
939 /*
940 * If we don't indicate MSR support in the CPUID feature bits, indicate
941 * that a #GP(0) should be raised.
942 */
943 if (!(pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_MSR))
944 return VERR_CPUM_RAISE_GP_0;
945
946 int rc = VINF_SUCCESS;
947 switch (idMsr)
948 {
949 case MSR_IA32_MISC_ENABLE:
950 pVCpu->cpum.s.GuestMsr.msr.miscEnable = uValue;
951 break;
952
953 case MSR_IA32_TSC:
954 TMCpuTickSet(pVCpu->CTX_SUFF(pVM), pVCpu, uValue);
955 break;
956
957 case MSR_IA32_APICBASE:
958 rc = PDMApicSetBase(pVCpu->CTX_SUFF(pVM), uValue);
959 if (rc != VINF_SUCCESS)
960 rc = VERR_CPUM_RAISE_GP_0;
961 break;
962
963 case MSR_IA32_CR_PAT:
964 pVCpu->cpum.s.Guest.msrPAT = uValue;
965 break;
966
967 case MSR_IA32_SYSENTER_CS:
968 pVCpu->cpum.s.Guest.SysEnter.cs = uValue & 0xffff; /* 16 bits selector */
969 break;
970
971 case MSR_IA32_SYSENTER_EIP:
972 pVCpu->cpum.s.Guest.SysEnter.eip = uValue;
973 break;
974
975 case MSR_IA32_SYSENTER_ESP:
976 pVCpu->cpum.s.Guest.SysEnter.esp = uValue;
977 break;
978
979 case MSR_K6_EFER:
980 {
981 PVM pVM = pVCpu->CTX_SUFF(pVM);
982 uint64_t const uOldEFER = pVCpu->cpum.s.Guest.msrEFER;
983 uint32_t const fExtFeatures = pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
984 ? pVM->cpum.s.aGuestCpuIdExt[1].edx
985 : 0;
986 uint64_t fMask = 0;
987
988 /* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
989 if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_NX)
990 fMask |= MSR_K6_EFER_NXE;
991 if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE)
992 fMask |= MSR_K6_EFER_LME;
993 if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_SEP)
994 fMask |= MSR_K6_EFER_SCE;
995 if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
996 fMask |= MSR_K6_EFER_FFXSR;
997
998 /* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if
999 paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1000 if ( (uOldEFER & MSR_K6_EFER_LME) != (uValue & fMask & MSR_K6_EFER_LME)
1001 && (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG))
1002 {
1003 Log(("Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
1004 return VERR_CPUM_RAISE_GP_0;
1005 }
1006
1007 /* There are a few more: e.g. MSR_K6_EFER_LMSLE */
1008 AssertMsg(!(uValue & ~(MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA /* ignored anyway */ | MSR_K6_EFER_SCE | MSR_K6_EFER_FFXSR)),
1009 ("Unexpected value %RX64\n", uValue));
1010 pVCpu->cpum.s.Guest.msrEFER = (uOldEFER & ~fMask) | (uValue & fMask);
1011
1012 /* AMD64 Architecture Programmer's Manual: 15.15 TLB Control; flush the TLB
1013 if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
1014 if ( (uOldEFER & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA))
1015 != (pVCpu->cpum.s.Guest.msrEFER & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA)))
1016 {
1017 /// @todo PGMFlushTLB(pVCpu, cr3, true /*fGlobal*/);
1018 HWACCMFlushTLB(pVCpu);
1019
1020 /* Notify PGM about NXE changes. */
1021 if ( (uOldEFER & MSR_K6_EFER_NXE)
1022 != (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE))
1023 PGMNotifyNxeChanged(pVCpu, !(uOldEFER & MSR_K6_EFER_NXE));
1024 }
1025 break;
1026 }
1027
1028 case MSR_K8_SF_MASK:
1029 pVCpu->cpum.s.Guest.msrSFMASK = uValue;
1030 break;
1031
1032 case MSR_K6_STAR:
1033 pVCpu->cpum.s.Guest.msrSTAR = uValue;
1034 break;
1035
1036 case MSR_K8_LSTAR:
1037 pVCpu->cpum.s.Guest.msrLSTAR = uValue;
1038 break;
1039
1040 case MSR_K8_CSTAR:
1041 pVCpu->cpum.s.Guest.msrCSTAR = uValue;
1042 break;
1043
1044 case MSR_K8_FS_BASE:
1045 pVCpu->cpum.s.Guest.fsHid.u64Base = uValue;
1046 break;
1047
1048 case MSR_K8_GS_BASE:
1049 pVCpu->cpum.s.Guest.gsHid.u64Base = uValue;
1050 break;
1051
1052 case MSR_K8_KERNEL_GS_BASE:
1053 pVCpu->cpum.s.Guest.msrKERNELGSBASE = uValue;
1054 break;
1055
1056 case MSR_K8_TSC_AUX:
1057 pVCpu->cpum.s.GuestMsr.msr.tscAux = uValue;
1058 break;
1059
1060 default:
1061 /* In X2APIC specification this range is reserved for APIC control. */
1062 if ( idMsr >= MSR_IA32_APIC_START
1063 && idMsr < MSR_IA32_APIC_END)
1064 {
1065 rc = PDMApicWriteMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, uValue);
1066 if (rc != VINF_SUCCESS)
1067 rc = VERR_CPUM_RAISE_GP_0;
1068 }
1069 else
1070 {
1071 /* We should actually trigger a #GP here, but don't as that might cause more trouble. */
1072 /** @todo rc = VERR_CPUM_RAISE_GP_0 */
1073 Log(("CPUMSetGuestMsr: Unknown MSR %#x attempted set to %#llx\n", idMsr, uValue));
1074 }
1075 break;
1076 }
1077 return rc;
1078}
1079
1080
1081VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
1082{
1083 if (pcbLimit)
1084 *pcbLimit = pVCpu->cpum.s.Guest.idtr.cbIdt;
1085 return pVCpu->cpum.s.Guest.idtr.pIdt;
1086}
1087
1088
1089VMMDECL(RTSEL) CPUMGetGuestTR(PVMCPU pVCpu, PCPUMSELREGHID pHidden)
1090{
1091 if (pHidden)
1092 *pHidden = pVCpu->cpum.s.Guest.trHid;
1093 return pVCpu->cpum.s.Guest.tr;
1094}
1095
1096
1097VMMDECL(RTSEL) CPUMGetGuestCS(PVMCPU pVCpu)
1098{
1099 return pVCpu->cpum.s.Guest.cs;
1100}
1101
1102
1103VMMDECL(RTSEL) CPUMGetGuestDS(PVMCPU pVCpu)
1104{
1105 return pVCpu->cpum.s.Guest.ds;
1106}
1107
1108
1109VMMDECL(RTSEL) CPUMGetGuestES(PVMCPU pVCpu)
1110{
1111 return pVCpu->cpum.s.Guest.es;
1112}
1113
1114
1115VMMDECL(RTSEL) CPUMGetGuestFS(PVMCPU pVCpu)
1116{
1117 return pVCpu->cpum.s.Guest.fs;
1118}
1119
1120
1121VMMDECL(RTSEL) CPUMGetGuestGS(PVMCPU pVCpu)
1122{
1123 return pVCpu->cpum.s.Guest.gs;
1124}
1125
1126
1127VMMDECL(RTSEL) CPUMGetGuestSS(PVMCPU pVCpu)
1128{
1129 return pVCpu->cpum.s.Guest.ss;
1130}
1131
1132
1133VMMDECL(RTSEL) CPUMGetGuestLDTR(PVMCPU pVCpu)
1134{
1135 return pVCpu->cpum.s.Guest.ldtr;
1136}
1137
1138
1139VMMDECL(uint64_t) CPUMGetGuestCR0(PVMCPU pVCpu)
1140{
1141 return pVCpu->cpum.s.Guest.cr0;
1142}
1143
1144
1145VMMDECL(uint64_t) CPUMGetGuestCR2(PVMCPU pVCpu)
1146{
1147 return pVCpu->cpum.s.Guest.cr2;
1148}
1149
1150
1151VMMDECL(uint64_t) CPUMGetGuestCR3(PVMCPU pVCpu)
1152{
1153 return pVCpu->cpum.s.Guest.cr3;
1154}
1155
1156
1157VMMDECL(uint64_t) CPUMGetGuestCR4(PVMCPU pVCpu)
1158{
1159 return pVCpu->cpum.s.Guest.cr4;
1160}
1161
1162
1163VMMDECL(uint64_t) CPUMGetGuestCR8(PVMCPU pVCpu)
1164{
1165 uint64_t u64;
1166 int rc = CPUMGetGuestCRx(pVCpu, USE_REG_CR8, &u64);
1167 if (RT_FAILURE(rc))
1168 u64 = 0;
1169 return u64;
1170}
1171
1172
1173VMMDECL(void) CPUMGetGuestGDTR(PVMCPU pVCpu, PVBOXGDTR pGDTR)
1174{
1175 *pGDTR = pVCpu->cpum.s.Guest.gdtr;
1176}
1177
1178
1179VMMDECL(uint32_t) CPUMGetGuestEIP(PVMCPU pVCpu)
1180{
1181 return pVCpu->cpum.s.Guest.eip;
1182}
1183
1184
1185VMMDECL(uint64_t) CPUMGetGuestRIP(PVMCPU pVCpu)
1186{
1187 return pVCpu->cpum.s.Guest.rip;
1188}
1189
1190
1191VMMDECL(uint32_t) CPUMGetGuestEAX(PVMCPU pVCpu)
1192{
1193 return pVCpu->cpum.s.Guest.eax;
1194}
1195
1196
1197VMMDECL(uint32_t) CPUMGetGuestEBX(PVMCPU pVCpu)
1198{
1199 return pVCpu->cpum.s.Guest.ebx;
1200}
1201
1202
1203VMMDECL(uint32_t) CPUMGetGuestECX(PVMCPU pVCpu)
1204{
1205 return pVCpu->cpum.s.Guest.ecx;
1206}
1207
1208
1209VMMDECL(uint32_t) CPUMGetGuestEDX(PVMCPU pVCpu)
1210{
1211 return pVCpu->cpum.s.Guest.edx;
1212}
1213
1214
1215VMMDECL(uint32_t) CPUMGetGuestESI(PVMCPU pVCpu)
1216{
1217 return pVCpu->cpum.s.Guest.esi;
1218}
1219
1220
1221VMMDECL(uint32_t) CPUMGetGuestEDI(PVMCPU pVCpu)
1222{
1223 return pVCpu->cpum.s.Guest.edi;
1224}
1225
1226
1227VMMDECL(uint32_t) CPUMGetGuestESP(PVMCPU pVCpu)
1228{
1229 return pVCpu->cpum.s.Guest.esp;
1230}
1231
1232
1233VMMDECL(uint32_t) CPUMGetGuestEBP(PVMCPU pVCpu)
1234{
1235 return pVCpu->cpum.s.Guest.ebp;
1236}
1237
1238
1239VMMDECL(uint32_t) CPUMGetGuestEFlags(PVMCPU pVCpu)
1240{
1241 return pVCpu->cpum.s.Guest.eflags.u32;
1242}
1243
1244
1245VMMDECL(int) CPUMGetGuestCRx(PVMCPU pVCpu, unsigned iReg, uint64_t *pValue)
1246{
1247 switch (iReg)
1248 {
1249 case USE_REG_CR0:
1250 *pValue = pVCpu->cpum.s.Guest.cr0;
1251 break;
1252
1253 case USE_REG_CR2:
1254 *pValue = pVCpu->cpum.s.Guest.cr2;
1255 break;
1256
1257 case USE_REG_CR3:
1258 *pValue = pVCpu->cpum.s.Guest.cr3;
1259 break;
1260
1261 case USE_REG_CR4:
1262 *pValue = pVCpu->cpum.s.Guest.cr4;
1263 break;
1264
1265 case USE_REG_CR8:
1266 {
1267 uint8_t u8Tpr;
1268 int rc = PDMApicGetTPR(pVCpu, &u8Tpr, NULL /*pfPending*/);
1269 if (RT_FAILURE(rc))
1270 {
1271 AssertMsg(rc == VERR_PDM_NO_APIC_INSTANCE, ("%Rrc\n", rc));
1272 *pValue = 0;
1273 return rc;
1274 }
1275 *pValue = u8Tpr >> 4; /* bits 7-4 contain the task priority that go in cr8, bits 3-0*/
1276 break;
1277 }
1278
1279 default:
1280 return VERR_INVALID_PARAMETER;
1281 }
1282 return VINF_SUCCESS;
1283}
1284
1285
1286VMMDECL(uint64_t) CPUMGetGuestDR0(PVMCPU pVCpu)
1287{
1288 return pVCpu->cpum.s.Guest.dr[0];
1289}
1290
1291
1292VMMDECL(uint64_t) CPUMGetGuestDR1(PVMCPU pVCpu)
1293{
1294 return pVCpu->cpum.s.Guest.dr[1];
1295}
1296
1297
1298VMMDECL(uint64_t) CPUMGetGuestDR2(PVMCPU pVCpu)
1299{
1300 return pVCpu->cpum.s.Guest.dr[2];
1301}
1302
1303
1304VMMDECL(uint64_t) CPUMGetGuestDR3(PVMCPU pVCpu)
1305{
1306 return pVCpu->cpum.s.Guest.dr[3];
1307}
1308
1309
1310VMMDECL(uint64_t) CPUMGetGuestDR6(PVMCPU pVCpu)
1311{
1312 return pVCpu->cpum.s.Guest.dr[6];
1313}
1314
1315
1316VMMDECL(uint64_t) CPUMGetGuestDR7(PVMCPU pVCpu)
1317{
1318 return pVCpu->cpum.s.Guest.dr[7];
1319}
1320
1321
1322VMMDECL(int) CPUMGetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t *pValue)
1323{
1324 AssertReturn(iReg <= USE_REG_DR7, VERR_INVALID_PARAMETER);
1325 /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
1326 if (iReg == 4 || iReg == 5)
1327 iReg += 2;
1328 *pValue = pVCpu->cpum.s.Guest.dr[iReg];
1329 return VINF_SUCCESS;
1330}
1331
1332
1333VMMDECL(uint64_t) CPUMGetGuestEFER(PVMCPU pVCpu)
1334{
1335 return pVCpu->cpum.s.Guest.msrEFER;
1336}
1337
1338
1339/**
1340 * Gets a CpuId leaf.
1341 *
1342 * @param pVCpu The VMCPU handle.
1343 * @param iLeaf The CPUID leaf to get.
1344 * @param pEax Where to store the EAX value.
1345 * @param pEbx Where to store the EBX value.
1346 * @param pEcx Where to store the ECX value.
1347 * @param pEdx Where to store the EDX value.
1348 */
1349VMMDECL(void) CPUMGetGuestCpuId(PVMCPU pVCpu, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx)
1350{
1351 PVM pVM = pVCpu->CTX_SUFF(pVM);
1352
1353 PCCPUMCPUID pCpuId;
1354 if (iLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
1355 pCpuId = &pVM->cpum.s.aGuestCpuIdStd[iLeaf];
1356 else if (iLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
1357 pCpuId = &pVM->cpum.s.aGuestCpuIdExt[iLeaf - UINT32_C(0x80000000)];
1358 else if (iLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
1359 pCpuId = &pVM->cpum.s.aGuestCpuIdCentaur[iLeaf - UINT32_C(0xc0000000)];
1360 else
1361 pCpuId = &pVM->cpum.s.GuestCpuIdDef;
1362
1363 uint32_t cCurrentCacheIndex = *pEcx;
1364
1365 *pEax = pCpuId->eax;
1366 *pEbx = pCpuId->ebx;
1367 *pEcx = pCpuId->ecx;
1368 *pEdx = pCpuId->edx;
1369
1370 if ( iLeaf == 1)
1371 {
1372 /* Bits 31-24: Initial APIC ID */
1373 Assert(pVCpu->idCpu <= 255);
1374 *pEbx |= (pVCpu->idCpu << 24);
1375 }
1376
1377 if ( iLeaf == 4
1378 && cCurrentCacheIndex < 3
1379 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
1380 {
1381 uint32_t type, level, sharing, linesize,
1382 partitions, associativity, sets, cores;
1383
1384 /* For type: 1 - data cache, 2 - i-cache, 3 - unified */
1385 partitions = 1;
1386 /* Those are only to shut up compiler, as they will always
1387 get overwritten, and compiler should be able to figure that out */
1388 sets = associativity = sharing = level = 1;
1389 cores = pVM->cCpus > 32 ? 32 : pVM->cCpus;
1390 switch (cCurrentCacheIndex)
1391 {
1392 case 0:
1393 type = 1;
1394 level = 1;
1395 sharing = 1;
1396 linesize = 64;
1397 associativity = 8;
1398 sets = 64;
1399 break;
1400 case 1:
1401 level = 1;
1402 type = 2;
1403 sharing = 1;
1404 linesize = 64;
1405 associativity = 8;
1406 sets = 64;
1407 break;
1408 default: /* shut up gcc.*/
1409 AssertFailed();
1410 case 2:
1411 level = 2;
1412 type = 3;
1413 sharing = cores; /* our L2 cache is modelled as shared between all cores */
1414 linesize = 64;
1415 associativity = 24;
1416 sets = 4096;
1417 break;
1418 }
1419
1420 *pEax |= ((cores - 1) << 26) |
1421 ((sharing - 1) << 14) |
1422 (level << 5) |
1423 1;
1424 *pEbx = (linesize - 1) |
1425 ((partitions - 1) << 12) |
1426 ((associativity - 1) << 22); /* -1 encoding */
1427 *pEcx = sets - 1;
1428 }
1429
1430 Log2(("CPUMGetGuestCpuId: iLeaf=%#010x %RX32 %RX32 %RX32 %RX32\n", iLeaf, *pEax, *pEbx, *pEcx, *pEdx));
1431}
1432
1433/**
1434 * Gets a number of standard CPUID leafs.
1435 *
1436 * @returns Number of leafs.
1437 * @param pVM The VM handle.
1438 * @remark Intended for PATM.
1439 */
1440VMMDECL(uint32_t) CPUMGetGuestCpuIdStdMax(PVM pVM)
1441{
1442 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd);
1443}
1444
1445
1446/**
1447 * Gets a number of extended CPUID leafs.
1448 *
1449 * @returns Number of leafs.
1450 * @param pVM The VM handle.
1451 * @remark Intended for PATM.
1452 */
1453VMMDECL(uint32_t) CPUMGetGuestCpuIdExtMax(PVM pVM)
1454{
1455 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt);
1456}
1457
1458
1459/**
1460 * Gets a number of centaur CPUID leafs.
1461 *
1462 * @returns Number of leafs.
1463 * @param pVM The VM handle.
1464 * @remark Intended for PATM.
1465 */
1466VMMDECL(uint32_t) CPUMGetGuestCpuIdCentaurMax(PVM pVM)
1467{
1468 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur);
1469}
1470
1471
1472/**
1473 * Sets a CPUID feature bit.
1474 *
1475 * @param pVM The VM Handle.
1476 * @param enmFeature The feature to set.
1477 */
1478VMMDECL(void) CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
1479{
1480 switch (enmFeature)
1481 {
1482 /*
1483 * Set the APIC bit in both feature masks.
1484 */
1485 case CPUMCPUIDFEATURE_APIC:
1486 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1487 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_APIC;
1488 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1489 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1490 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_APIC;
1491 LogRel(("CPUMSetGuestCpuIdFeature: Enabled APIC\n"));
1492 break;
1493
1494 /*
1495 * Set the x2APIC bit in the standard feature mask.
1496 */
1497 case CPUMCPUIDFEATURE_X2APIC:
1498 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1499 pVM->cpum.s.aGuestCpuIdStd[1].ecx |= X86_CPUID_FEATURE_ECX_X2APIC;
1500 LogRel(("CPUMSetGuestCpuIdFeature: Enabled x2APIC\n"));
1501 break;
1502
1503 /*
1504 * Set the sysenter/sysexit bit in the standard feature mask.
1505 * Assumes the caller knows what it's doing! (host must support these)
1506 */
1507 case CPUMCPUIDFEATURE_SEP:
1508 {
1509 if (!(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_SEP))
1510 {
1511 AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
1512 return;
1513 }
1514
1515 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1516 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_SEP;
1517 LogRel(("CPUMSetGuestCpuIdFeature: Enabled sysenter/exit\n"));
1518 break;
1519 }
1520
1521 /*
1522 * Set the syscall/sysret bit in the extended feature mask.
1523 * Assumes the caller knows what it's doing! (host must support these)
1524 */
1525 case CPUMCPUIDFEATURE_SYSCALL:
1526 {
1527 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1528 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_SEP))
1529 {
1530#if HC_ARCH_BITS == 32
1531 /* X86_CPUID_AMD_FEATURE_EDX_SEP not set it seems in 32 bits mode.
1532 * Even when the cpu is capable of doing so in 64 bits mode.
1533 */
1534 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1535 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE)
1536 || !(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_SEP))
1537#endif
1538 {
1539 LogRel(("WARNING: Can't turn on SYSCALL/SYSRET when the host doesn't support it!!\n"));
1540 return;
1541 }
1542 }
1543 /* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
1544 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_SEP;
1545 LogRel(("CPUMSetGuestCpuIdFeature: Enabled syscall/ret\n"));
1546 break;
1547 }
1548
1549 /*
1550 * Set the PAE bit in both feature masks.
1551 * Assumes the caller knows what it's doing! (host must support these)
1552 */
1553 case CPUMCPUIDFEATURE_PAE:
1554 {
1555 if (!(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_PAE))
1556 {
1557 LogRel(("WARNING: Can't turn on PAE when the host doesn't support it!!\n"));
1558 return;
1559 }
1560
1561 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1562 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_PAE;
1563 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1564 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1565 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_PAE;
1566 LogRel(("CPUMSetGuestCpuIdFeature: Enabled PAE\n"));
1567 break;
1568 }
1569
1570 /*
1571 * Set the LONG MODE bit in the extended feature mask.
1572 * Assumes the caller knows what it's doing! (host must support these)
1573 */
1574 case CPUMCPUIDFEATURE_LONG_MODE:
1575 {
1576 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1577 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE))
1578 {
1579 LogRel(("WARNING: Can't turn on LONG MODE when the host doesn't support it!!\n"));
1580 return;
1581 }
1582
1583 /* Valid for both Intel and AMD. */
1584 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_LONG_MODE;
1585 LogRel(("CPUMSetGuestCpuIdFeature: Enabled LONG MODE\n"));
1586 break;
1587 }
1588
1589 /*
1590 * Set the NXE bit in the extended feature mask.
1591 * Assumes the caller knows what it's doing! (host must support these)
1592 */
1593 case CPUMCPUIDFEATURE_NXE:
1594 {
1595 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1596 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_NX))
1597 {
1598 LogRel(("WARNING: Can't turn on NXE when the host doesn't support it!!\n"));
1599 return;
1600 }
1601
1602 /* Valid for both Intel and AMD. */
1603 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_NX;
1604 LogRel(("CPUMSetGuestCpuIdFeature: Enabled NXE\n"));
1605 break;
1606 }
1607
1608 case CPUMCPUIDFEATURE_LAHF:
1609 {
1610 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1611 || !(ASMCpuId_ECX(0x80000001) & X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF))
1612 {
1613 LogRel(("WARNING: Can't turn on LAHF/SAHF when the host doesn't support it!!\n"));
1614 return;
1615 }
1616
1617 pVM->cpum.s.aGuestCpuIdExt[1].ecx |= X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF;
1618 LogRel(("CPUMSetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
1619 break;
1620 }
1621
1622 case CPUMCPUIDFEATURE_PAT:
1623 {
1624 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1625 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_PAT;
1626 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1627 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1628 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_PAT;
1629 LogRel(("CPUMClearGuestCpuIdFeature: Enabled PAT\n"));
1630 break;
1631 }
1632
1633 case CPUMCPUIDFEATURE_RDTSCP:
1634 {
1635 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1636 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_RDTSCP)
1637 || pVM->cpum.s.u8PortableCpuIdLevel > 0)
1638 {
1639 if (!pVM->cpum.s.u8PortableCpuIdLevel)
1640 LogRel(("WARNING: Can't turn on RDTSCP when the host doesn't support it!!\n"));
1641 return;
1642 }
1643
1644 /* Valid for AMD only (for now). */
1645 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_RDTSCP;
1646 LogRel(("CPUMSetGuestCpuIdFeature: Enabled RDTSCP.\n"));
1647 break;
1648 }
1649
1650 default:
1651 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
1652 break;
1653 }
1654 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1655 {
1656 PVMCPU pVCpu = &pVM->aCpus[i];
1657 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CPUID;
1658 }
1659}
1660
1661
1662/**
1663 * Queries a CPUID feature bit.
1664 *
1665 * @returns boolean for feature presence
1666 * @param pVM The VM Handle.
1667 * @param enmFeature The feature to query.
1668 */
1669VMMDECL(bool) CPUMGetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
1670{
1671 switch (enmFeature)
1672 {
1673 case CPUMCPUIDFEATURE_PAE:
1674 {
1675 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1676 return !!(pVM->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PAE);
1677 break;
1678 }
1679
1680 case CPUMCPUIDFEATURE_NXE:
1681 {
1682 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1683 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_AMD_FEATURE_EDX_NX);
1684 }
1685
1686 case CPUMCPUIDFEATURE_RDTSCP:
1687 {
1688 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1689 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
1690 break;
1691 }
1692
1693 case CPUMCPUIDFEATURE_LONG_MODE:
1694 {
1695 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1696 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE);
1697 break;
1698 }
1699
1700 default:
1701 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
1702 break;
1703 }
1704 return false;
1705}
1706
1707
1708/**
1709 * Clears a CPUID feature bit.
1710 *
1711 * @param pVM The VM Handle.
1712 * @param enmFeature The feature to clear.
1713 */
1714VMMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
1715{
1716 switch (enmFeature)
1717 {
1718 /*
1719 * Set the APIC bit in both feature masks.
1720 */
1721 case CPUMCPUIDFEATURE_APIC:
1722 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1723 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_APIC;
1724 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1725 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1726 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
1727 Log(("CPUMSetGuestCpuIdFeature: Disabled APIC\n"));
1728 break;
1729
1730 /*
1731 * Clear the x2APIC bit in the standard feature mask.
1732 */
1733 case CPUMCPUIDFEATURE_X2APIC:
1734 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1735 pVM->cpum.s.aGuestCpuIdStd[1].ecx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
1736 LogRel(("CPUMSetGuestCpuIdFeature: Disabled x2APIC\n"));
1737 break;
1738
1739 case CPUMCPUIDFEATURE_PAE:
1740 {
1741 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1742 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_PAE;
1743 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1744 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1745 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
1746 LogRel(("CPUMClearGuestCpuIdFeature: Disabled PAE!\n"));
1747 break;
1748 }
1749
1750 case CPUMCPUIDFEATURE_PAT:
1751 {
1752 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1753 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_PAT;
1754 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1755 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1756 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_PAT;
1757 LogRel(("CPUMClearGuestCpuIdFeature: Disabled PAT!\n"));
1758 break;
1759 }
1760
1761 case CPUMCPUIDFEATURE_LONG_MODE:
1762 {
1763 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1764 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_LONG_MODE;
1765 break;
1766 }
1767
1768 case CPUMCPUIDFEATURE_LAHF:
1769 {
1770 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1771 pVM->cpum.s.aGuestCpuIdExt[1].ecx &= ~X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF;
1772 break;
1773 }
1774
1775 default:
1776 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
1777 break;
1778 }
1779 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1780 {
1781 PVMCPU pVCpu = &pVM->aCpus[i];
1782 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CPUID;
1783 }
1784}
1785
1786
1787/**
1788 * Gets the host CPU vendor
1789 *
1790 * @returns CPU vendor
1791 * @param pVM The VM handle.
1792 */
1793VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM)
1794{
1795 return pVM->cpum.s.enmHostCpuVendor;
1796}
1797
1798/**
1799 * Gets the CPU vendor
1800 *
1801 * @returns CPU vendor
1802 * @param pVM The VM handle.
1803 */
1804VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM)
1805{
1806 return pVM->cpum.s.enmGuestCpuVendor;
1807}
1808
1809
1810VMMDECL(int) CPUMSetGuestDR0(PVMCPU pVCpu, uint64_t uDr0)
1811{
1812 pVCpu->cpum.s.Guest.dr[0] = uDr0;
1813 return CPUMRecalcHyperDRx(pVCpu);
1814}
1815
1816
1817VMMDECL(int) CPUMSetGuestDR1(PVMCPU pVCpu, uint64_t uDr1)
1818{
1819 pVCpu->cpum.s.Guest.dr[1] = uDr1;
1820 return CPUMRecalcHyperDRx(pVCpu);
1821}
1822
1823
1824VMMDECL(int) CPUMSetGuestDR2(PVMCPU pVCpu, uint64_t uDr2)
1825{
1826 pVCpu->cpum.s.Guest.dr[2] = uDr2;
1827 return CPUMRecalcHyperDRx(pVCpu);
1828}
1829
1830
1831VMMDECL(int) CPUMSetGuestDR3(PVMCPU pVCpu, uint64_t uDr3)
1832{
1833 pVCpu->cpum.s.Guest.dr[3] = uDr3;
1834 return CPUMRecalcHyperDRx(pVCpu);
1835}
1836
1837
1838VMMDECL(int) CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6)
1839{
1840 pVCpu->cpum.s.Guest.dr[6] = uDr6;
1841 return CPUMRecalcHyperDRx(pVCpu);
1842}
1843
1844
1845VMMDECL(int) CPUMSetGuestDR7(PVMCPU pVCpu, uint64_t uDr7)
1846{
1847 pVCpu->cpum.s.Guest.dr[7] = uDr7;
1848 return CPUMRecalcHyperDRx(pVCpu);
1849}
1850
1851
1852VMMDECL(int) CPUMSetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t Value)
1853{
1854 AssertReturn(iReg <= USE_REG_DR7, VERR_INVALID_PARAMETER);
1855 /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
1856 if (iReg == 4 || iReg == 5)
1857 iReg += 2;
1858 pVCpu->cpum.s.Guest.dr[iReg] = Value;
1859 return CPUMRecalcHyperDRx(pVCpu);
1860}
1861
1862
1863/**
1864 * Recalculates the hypervisor DRx register values based on
1865 * current guest registers and DBGF breakpoints.
1866 *
1867 * This is called whenever a guest DRx register is modified and when DBGF
1868 * sets a hardware breakpoint. In guest context this function will reload
1869 * any (hyper) DRx registers which comes out with a different value.
1870 *
1871 * @returns VINF_SUCCESS.
1872 * @param pVCpu The VMCPU handle.
1873 */
1874VMMDECL(int) CPUMRecalcHyperDRx(PVMCPU pVCpu)
1875{
1876 PVM pVM = pVCpu->CTX_SUFF(pVM);
1877
1878 /*
1879 * Compare the DR7s first.
1880 *
1881 * We only care about the enabled flags. The GE and LE flags are always
1882 * set and we don't care if the guest doesn't set them. GD is virtualized
1883 * when we dispatch #DB, we never enable it.
1884 */
1885 const RTGCUINTREG uDbgfDr7 = DBGFBpGetDR7(pVM);
1886#ifdef CPUM_VIRTUALIZE_DRX
1887 const RTGCUINTREG uGstDr7 = CPUMGetGuestDR7(pVCpu);
1888#else
1889 const RTGCUINTREG uGstDr7 = 0;
1890#endif
1891 if ((uGstDr7 | uDbgfDr7) & X86_DR7_ENABLED_MASK)
1892 {
1893 /*
1894 * Ok, something is enabled. Recalc each of the breakpoints.
1895 * Straight forward code, not optimized/minimized in any way.
1896 */
1897 RTGCUINTREG uNewDr7 = X86_DR7_GE | X86_DR7_LE | X86_DR7_MB1_MASK;
1898
1899 /* bp 0 */
1900 RTGCUINTREG uNewDr0;
1901 if (uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0))
1902 {
1903 uNewDr7 |= uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
1904 uNewDr0 = DBGFBpGetDR0(pVM);
1905 }
1906 else if (uGstDr7 & (X86_DR7_L0 | X86_DR7_G0))
1907 {
1908 uNewDr7 |= uGstDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
1909 uNewDr0 = CPUMGetGuestDR0(pVCpu);
1910 }
1911 else
1912 uNewDr0 = pVCpu->cpum.s.Hyper.dr[0];
1913
1914 /* bp 1 */
1915 RTGCUINTREG uNewDr1;
1916 if (uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1))
1917 {
1918 uNewDr7 |= uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
1919 uNewDr1 = DBGFBpGetDR1(pVM);
1920 }
1921 else if (uGstDr7 & (X86_DR7_L1 | X86_DR7_G1))
1922 {
1923 uNewDr7 |= uGstDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
1924 uNewDr1 = CPUMGetGuestDR1(pVCpu);
1925 }
1926 else
1927 uNewDr1 = pVCpu->cpum.s.Hyper.dr[1];
1928
1929 /* bp 2 */
1930 RTGCUINTREG uNewDr2;
1931 if (uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2))
1932 {
1933 uNewDr7 |= uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
1934 uNewDr2 = DBGFBpGetDR2(pVM);
1935 }
1936 else if (uGstDr7 & (X86_DR7_L2 | X86_DR7_G2))
1937 {
1938 uNewDr7 |= uGstDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
1939 uNewDr2 = CPUMGetGuestDR2(pVCpu);
1940 }
1941 else
1942 uNewDr2 = pVCpu->cpum.s.Hyper.dr[2];
1943
1944 /* bp 3 */
1945 RTGCUINTREG uNewDr3;
1946 if (uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3))
1947 {
1948 uNewDr7 |= uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
1949 uNewDr3 = DBGFBpGetDR3(pVM);
1950 }
1951 else if (uGstDr7 & (X86_DR7_L3 | X86_DR7_G3))
1952 {
1953 uNewDr7 |= uGstDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
1954 uNewDr3 = CPUMGetGuestDR3(pVCpu);
1955 }
1956 else
1957 uNewDr3 = pVCpu->cpum.s.Hyper.dr[3];
1958
1959 /*
1960 * Apply the updates.
1961 */
1962#ifdef IN_RC
1963 if (!(pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS))
1964 {
1965 /** @todo save host DBx registers. */
1966 }
1967#endif
1968 pVCpu->cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS;
1969 if (uNewDr3 != pVCpu->cpum.s.Hyper.dr[3])
1970 CPUMSetHyperDR3(pVCpu, uNewDr3);
1971 if (uNewDr2 != pVCpu->cpum.s.Hyper.dr[2])
1972 CPUMSetHyperDR2(pVCpu, uNewDr2);
1973 if (uNewDr1 != pVCpu->cpum.s.Hyper.dr[1])
1974 CPUMSetHyperDR1(pVCpu, uNewDr1);
1975 if (uNewDr0 != pVCpu->cpum.s.Hyper.dr[0])
1976 CPUMSetHyperDR0(pVCpu, uNewDr0);
1977 if (uNewDr7 != pVCpu->cpum.s.Hyper.dr[7])
1978 CPUMSetHyperDR7(pVCpu, uNewDr7);
1979 }
1980 else
1981 {
1982#ifdef IN_RC
1983 if (pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS)
1984 {
1985 /** @todo restore host DBx registers. */
1986 }
1987#endif
1988 pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS;
1989 }
1990 Log2(("CPUMRecalcHyperDRx: fUseFlags=%#x %RGr %RGr %RGr %RGr %RGr %RGr\n",
1991 pVCpu->cpum.s.fUseFlags, pVCpu->cpum.s.Hyper.dr[0], pVCpu->cpum.s.Hyper.dr[1],
1992 pVCpu->cpum.s.Hyper.dr[2], pVCpu->cpum.s.Hyper.dr[3], pVCpu->cpum.s.Hyper.dr[6],
1993 pVCpu->cpum.s.Hyper.dr[7]));
1994
1995 return VINF_SUCCESS;
1996}
1997
1998
1999/**
2000 * Tests if the guest has No-Execute Page Protection Enabled (NXE).
2001 *
2002 * @returns true if in real mode, otherwise false.
2003 * @param pVCpu The virtual CPU handle.
2004 */
2005VMMDECL(bool) CPUMIsGuestNXEnabled(PVMCPU pVCpu)
2006{
2007 return !!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE);
2008}
2009
2010
2011/**
2012 * Tests if the guest has the Page Size Extension enabled (PSE).
2013 *
2014 * @returns true if in real mode, otherwise false.
2015 * @param pVCpu The virtual CPU handle.
2016 */
2017VMMDECL(bool) CPUMIsGuestPageSizeExtEnabled(PVMCPU pVCpu)
2018{
2019 /* PAE or AMD64 implies support for big pages regardless of CR4.PSE */
2020 return !!(pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PSE | X86_CR4_PAE));
2021}
2022
2023
2024/**
2025 * Tests if the guest has the paging enabled (PG).
2026 *
2027 * @returns true if in real mode, otherwise false.
2028 * @param pVCpu The virtual CPU handle.
2029 */
2030VMMDECL(bool) CPUMIsGuestPagingEnabled(PVMCPU pVCpu)
2031{
2032 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG);
2033}
2034
2035
2036/**
2037 * Tests if the guest has the paging enabled (PG).
2038 *
2039 * @returns true if in real mode, otherwise false.
2040 * @param pVCpu The virtual CPU handle.
2041 */
2042VMMDECL(bool) CPUMIsGuestR0WriteProtEnabled(PVMCPU pVCpu)
2043{
2044 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_WP);
2045}
2046
2047
2048/**
2049 * Tests if the guest is running in real mode or not.
2050 *
2051 * @returns true if in real mode, otherwise false.
2052 * @param pVCpu The virtual CPU handle.
2053 */
2054VMMDECL(bool) CPUMIsGuestInRealMode(PVMCPU pVCpu)
2055{
2056 return !(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
2057}
2058
2059
2060/**
2061 * Tests if the guest is running in real or virtual 8086 mode.
2062 *
2063 * @returns @c true if it is, @c false if not.
2064 * @param pVCpu The virtual CPU handle.
2065 */
2066VMMDECL(bool) CPUMIsGuestInRealOrV86Mode(PVMCPU pVCpu)
2067{
2068 return !(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE)
2069 || pVCpu->cpum.s.Guest.eflags.Bits.u1VM; /** @todo verify that this cannot be set in long mode. */
2070}
2071
2072
2073/**
2074 * Tests if the guest is running in protected or not.
2075 *
2076 * @returns true if in protected mode, otherwise false.
2077 * @param pVCpu The virtual CPU handle.
2078 */
2079VMMDECL(bool) CPUMIsGuestInProtectedMode(PVMCPU pVCpu)
2080{
2081 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
2082}
2083
2084
2085/**
2086 * Tests if the guest is running in paged protected or not.
2087 *
2088 * @returns true if in paged protected mode, otherwise false.
2089 * @param pVCpu The virtual CPU handle.
2090 */
2091VMMDECL(bool) CPUMIsGuestInPagedProtectedMode(PVMCPU pVCpu)
2092{
2093 return (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
2094}
2095
2096
2097/**
2098 * Tests if the guest is running in long mode or not.
2099 *
2100 * @returns true if in long mode, otherwise false.
2101 * @param pVCpu The virtual CPU handle.
2102 */
2103VMMDECL(bool) CPUMIsGuestInLongMode(PVMCPU pVCpu)
2104{
2105 return (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
2106}
2107
2108
2109/**
2110 * Tests if the guest is running in PAE mode or not.
2111 *
2112 * @returns true if in PAE mode, otherwise false.
2113 * @param pVCpu The virtual CPU handle.
2114 */
2115VMMDECL(bool) CPUMIsGuestInPAEMode(PVMCPU pVCpu)
2116{
2117 return (pVCpu->cpum.s.Guest.cr4 & X86_CR4_PAE)
2118 && (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG)
2119 && !(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA);
2120}
2121
2122
2123#ifndef IN_RING0
2124/**
2125 * Updates the EFLAGS while we're in raw-mode.
2126 *
2127 * @param pVCpu The VMCPU handle.
2128 * @param pCtxCore The context core.
2129 * @param eflags The new EFLAGS value.
2130 */
2131VMMDECL(void) CPUMRawSetEFlags(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, uint32_t eflags)
2132{
2133 PVM pVM = pVCpu->CTX_SUFF(pVM);
2134
2135 if (!pVCpu->cpum.s.fRawEntered)
2136 {
2137 pCtxCore->eflags.u32 = eflags;
2138 return;
2139 }
2140 PATMRawSetEFlags(pVM, pCtxCore, eflags);
2141}
2142#endif /* !IN_RING0 */
2143
2144
2145/**
2146 * Gets the EFLAGS while we're in raw-mode.
2147 *
2148 * @returns The eflags.
2149 * @param pVCpu The VMCPU handle.
2150 * @param pCtxCore The context core.
2151 */
2152VMMDECL(uint32_t) CPUMRawGetEFlags(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
2153{
2154#ifdef IN_RING0
2155 return pCtxCore->eflags.u32;
2156#else
2157 PVM pVM = pVCpu->CTX_SUFF(pVM);
2158
2159 if (!pVCpu->cpum.s.fRawEntered)
2160 return pCtxCore->eflags.u32;
2161 return PATMRawGetEFlags(pVM, pCtxCore);
2162#endif
2163}
2164
2165
2166/**
2167 * Sets the specified changed flags (CPUM_CHANGED_*).
2168 *
2169 * @param pVCpu The VMCPU handle.
2170 */
2171VMMDECL(void) CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedFlags)
2172{
2173 pVCpu->cpum.s.fChanged |= fChangedFlags;
2174}
2175
2176
2177/**
2178 * Checks if the CPU supports the FXSAVE and FXRSTOR instruction.
2179 * @returns true if supported.
2180 * @returns false if not supported.
2181 * @param pVM The VM handle.
2182 */
2183VMMDECL(bool) CPUMSupportsFXSR(PVM pVM)
2184{
2185 return pVM->cpum.s.CPUFeatures.edx.u1FXSR != 0;
2186}
2187
2188
2189/**
2190 * Checks if the host OS uses the SYSENTER / SYSEXIT instructions.
2191 * @returns true if used.
2192 * @returns false if not used.
2193 * @param pVM The VM handle.
2194 */
2195VMMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM)
2196{
2197 return (pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSENTER) != 0;
2198}
2199
2200
2201/**
2202 * Checks if the host OS uses the SYSCALL / SYSRET instructions.
2203 * @returns true if used.
2204 * @returns false if not used.
2205 * @param pVM The VM handle.
2206 */
2207VMMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM)
2208{
2209 return (pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSCALL) != 0;
2210}
2211
2212#ifndef IN_RING3
2213
2214/**
2215 * Lazily sync in the FPU/XMM state
2216 *
2217 * @returns VBox status code.
2218 * @param pVCpu VMCPU handle
2219 */
2220VMMDECL(int) CPUMHandleLazyFPU(PVMCPU pVCpu)
2221{
2222 return cpumHandleLazyFPUAsm(&pVCpu->cpum.s);
2223}
2224
2225#endif /* !IN_RING3 */
2226
2227/**
2228 * Checks if we activated the FPU/XMM state of the guest OS
2229 * @returns true if we did.
2230 * @returns false if not.
2231 * @param pVCpu The VMCPU handle.
2232 */
2233VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCpu)
2234{
2235 return (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU) != 0;
2236}
2237
2238
2239/**
2240 * Deactivate the FPU/XMM state of the guest OS
2241 * @param pVCpu The VMCPU handle.
2242 */
2243VMMDECL(void) CPUMDeactivateGuestFPUState(PVMCPU pVCpu)
2244{
2245 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU;
2246}
2247
2248
2249/**
2250 * Checks if the guest debug state is active
2251 *
2252 * @returns boolean
2253 * @param pVM VM handle.
2254 */
2255VMMDECL(bool) CPUMIsGuestDebugStateActive(PVMCPU pVCpu)
2256{
2257 return (pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS) != 0;
2258}
2259
2260/**
2261 * Checks if the hyper debug state is active
2262 *
2263 * @returns boolean
2264 * @param pVM VM handle.
2265 */
2266VMMDECL(bool) CPUMIsHyperDebugStateActive(PVMCPU pVCpu)
2267{
2268 return (pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS_HYPER) != 0;
2269}
2270
2271
2272/**
2273 * Mark the guest's debug state as inactive.
2274 *
2275 * @returns boolean
2276 * @param pVM VM handle.
2277 */
2278VMMDECL(void) CPUMDeactivateGuestDebugState(PVMCPU pVCpu)
2279{
2280 pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS;
2281}
2282
2283
2284/**
2285 * Mark the hypervisor's debug state as inactive.
2286 *
2287 * @returns boolean
2288 * @param pVM VM handle.
2289 */
2290VMMDECL(void) CPUMDeactivateHyperDebugState(PVMCPU pVCpu)
2291{
2292 pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS_HYPER;
2293}
2294
2295/**
2296 * Checks if the hidden selector registers are valid for the specified CPU.
2297 *
2298 * @returns true if they are.
2299 * @returns false if not.
2300 * @param pVCpu The VM handle.
2301 */
2302VMMDECL(bool) CPUMAreHiddenSelRegsValid(PVMCPU pVCpu)
2303{
2304 bool const fRc = !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID);
2305 Assert(fRc || !HWACCMIsEnabled(pVCpu->CTX_SUFF(pVM)));
2306 Assert(!pVCpu->cpum.s.fRemEntered);
2307 return fRc;
2308}
2309
2310
2311
2312/**
2313 * Get the current privilege level of the guest.
2314 *
2315 * @returns cpl
2316 * @param pVM VM Handle.
2317 * @param pRegFrame Trap register frame.
2318 */
2319VMMDECL(uint32_t) CPUMGetGuestCPL(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
2320{
2321 uint32_t cpl;
2322
2323 if (CPUMAreHiddenSelRegsValid(pVCpu))
2324 {
2325 /*
2326 * The hidden CS.DPL register is always equal to the CPL, it is
2327 * not affected by loading a conforming coding segment.
2328 *
2329 * This only seems to apply to AMD-V; in the VT-x case we *do* need to look
2330 * at SS. (ACP2 regression during install after a far call to ring 2)
2331 */
2332 if (RT_LIKELY(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
2333 {
2334 if (!pCtxCore->eflags.Bits.u1VM)
2335 cpl = pCtxCore->ssHid.Attr.n.u2Dpl;
2336 else
2337 cpl = 3; /* REM doesn't set DPL=3 in V8086 mode. See #5130. */
2338 }
2339 else
2340 cpl = 0; /* CPL set to 3 for VT-x real-mode emulation. */
2341 }
2342 else if (RT_LIKELY(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
2343 {
2344 if (RT_LIKELY(!pCtxCore->eflags.Bits.u1VM))
2345 {
2346 /*
2347 * The SS RPL is always equal to the CPL, while the CS RPL
2348 * isn't necessarily equal if the segment is conforming.
2349 * See section 4.11.1 in the AMD manual.
2350 */
2351 cpl = (pCtxCore->ss & X86_SEL_RPL);
2352#ifndef IN_RING0
2353 if (cpl == 1)
2354 cpl = 0;
2355#endif
2356 }
2357 else
2358 cpl = 3;
2359 }
2360 else
2361 cpl = 0; /* real mode; cpl is zero */
2362
2363 return cpl;
2364}
2365
2366
2367/**
2368 * Gets the current guest CPU mode.
2369 *
2370 * If paging mode is what you need, check out PGMGetGuestMode().
2371 *
2372 * @returns The CPU mode.
2373 * @param pVCpu The VMCPU handle.
2374 */
2375VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu)
2376{
2377 CPUMMODE enmMode;
2378 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
2379 enmMode = CPUMMODE_REAL;
2380 else if (!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
2381 enmMode = CPUMMODE_PROTECTED;
2382 else
2383 enmMode = CPUMMODE_LONG;
2384
2385 return enmMode;
2386}
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