VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp@ 36861

Last change on this file since 36861 was 36861, checked in by vboxsync, 14 years ago

CPUMSetGuestTR: Awww, shut up.
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1/* $Id: CPUMAllRegs.cpp 36861 2011-04-27 17:38:26Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor(/Manager) - Getters and Setters.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_CPUM
23#include <VBox/vmm/cpum.h>
24#include <VBox/vmm/patm.h>
25#include <VBox/vmm/dbgf.h>
26#include <VBox/vmm/pdm.h>
27#include <VBox/vmm/pgm.h>
28#include <VBox/vmm/mm.h>
29#include "CPUMInternal.h"
30#include <VBox/vmm/vm.h>
31#include <VBox/err.h>
32#include <VBox/dis.h>
33#include <VBox/log.h>
34#include <VBox/vmm/hwaccm.h>
35#include <VBox/vmm/tm.h>
36#include <iprt/assert.h>
37#include <iprt/asm.h>
38#include <iprt/asm-amd64-x86.h>
39#ifdef IN_RING3
40#include <iprt/thread.h>
41#endif
42
43/** Disable stack frame pointer generation here. */
44#if defined(_MSC_VER) && !defined(DEBUG)
45# pragma optimize("y", off)
46#endif
47
48
49/**
50 * Sets or resets an alternative hypervisor context core.
51 *
52 * This is called when we get a hypervisor trap set switch the context
53 * core with the trap frame on the stack. It is called again to reset
54 * back to the default context core when resuming hypervisor execution.
55 *
56 * @param pVCpu The VMCPU handle.
57 * @param pCtxCore Pointer to the alternative context core or NULL
58 * to go back to the default context core.
59 */
60VMMDECL(void) CPUMHyperSetCtxCore(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
61{
62 PVM pVM = pVCpu->CTX_SUFF(pVM);
63
64 LogFlow(("CPUMHyperSetCtxCore: %p/%p/%p -> %p\n", pVCpu->cpum.s.CTX_SUFF(pHyperCore), pCtxCore));
65 if (!pCtxCore)
66 {
67 pCtxCore = CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
68 pVCpu->cpum.s.pHyperCoreR3 = (R3PTRTYPE(PCPUMCTXCORE))VM_R3_ADDR(pVM, pCtxCore);
69 pVCpu->cpum.s.pHyperCoreR0 = (R0PTRTYPE(PCPUMCTXCORE))VM_R0_ADDR(pVM, pCtxCore);
70 pVCpu->cpum.s.pHyperCoreRC = (RCPTRTYPE(PCPUMCTXCORE))VM_RC_ADDR(pVM, pCtxCore);
71 }
72 else
73 {
74 pVCpu->cpum.s.pHyperCoreR3 = (R3PTRTYPE(PCPUMCTXCORE))MMHyperCCToR3(pVM, pCtxCore);
75 pVCpu->cpum.s.pHyperCoreR0 = (R0PTRTYPE(PCPUMCTXCORE))MMHyperCCToR0(pVM, pCtxCore);
76 pVCpu->cpum.s.pHyperCoreRC = (RCPTRTYPE(PCPUMCTXCORE))MMHyperCCToRC(pVM, pCtxCore);
77 }
78}
79
80
81/**
82 * Gets the pointer to the internal CPUMCTXCORE structure for the hypervisor.
83 * This is only for reading in order to save a few calls.
84 *
85 * @param pVM Handle to the virtual machine.
86 */
87VMMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVMCPU pVCpu)
88{
89 return pVCpu->cpum.s.CTX_SUFF(pHyperCore);
90}
91
92
93/**
94 * Queries the pointer to the internal CPUMCTX structure for the hypervisor.
95 *
96 * @returns VBox status code.
97 * @param pVM Handle to the virtual machine.
98 * @param ppCtx Receives the hyper CPUMCTX pointer when successful.
99 *
100 * @deprecated This will *not* (and has never) given the right picture of the
101 * hypervisor register state. With CPUMHyperSetCtxCore() this is
102 * getting much worse. So, use the individual functions for getting
103 * and esp. setting the hypervisor registers.
104 */
105VMMDECL(int) CPUMQueryHyperCtxPtr(PVMCPU pVCpu, PCPUMCTX *ppCtx)
106{
107 *ppCtx = &pVCpu->cpum.s.Hyper;
108 return VINF_SUCCESS;
109}
110
111
112VMMDECL(void) CPUMSetHyperGDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
113{
114 pVCpu->cpum.s.Hyper.gdtr.cbGdt = limit;
115 pVCpu->cpum.s.Hyper.gdtr.pGdt = addr;
116 pVCpu->cpum.s.Hyper.gdtrPadding = 0;
117}
118
119
120VMMDECL(void) CPUMSetHyperIDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
121{
122 pVCpu->cpum.s.Hyper.idtr.cbIdt = limit;
123 pVCpu->cpum.s.Hyper.idtr.pIdt = addr;
124 pVCpu->cpum.s.Hyper.idtrPadding = 0;
125}
126
127
128VMMDECL(void) CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3)
129{
130 pVCpu->cpum.s.Hyper.cr3 = cr3;
131
132#ifdef IN_RC
133 /* Update the current CR3. */
134 ASMSetCR3(cr3);
135#endif
136}
137
138VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu)
139{
140 return pVCpu->cpum.s.Hyper.cr3;
141}
142
143
144VMMDECL(void) CPUMSetHyperCS(PVMCPU pVCpu, RTSEL SelCS)
145{
146 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->cs = SelCS;
147}
148
149
150VMMDECL(void) CPUMSetHyperDS(PVMCPU pVCpu, RTSEL SelDS)
151{
152 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ds = SelDS;
153}
154
155
156VMMDECL(void) CPUMSetHyperES(PVMCPU pVCpu, RTSEL SelES)
157{
158 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->es = SelES;
159}
160
161
162VMMDECL(void) CPUMSetHyperFS(PVMCPU pVCpu, RTSEL SelFS)
163{
164 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->fs = SelFS;
165}
166
167
168VMMDECL(void) CPUMSetHyperGS(PVMCPU pVCpu, RTSEL SelGS)
169{
170 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->gs = SelGS;
171}
172
173
174VMMDECL(void) CPUMSetHyperSS(PVMCPU pVCpu, RTSEL SelSS)
175{
176 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ss = SelSS;
177}
178
179
180VMMDECL(void) CPUMSetHyperESP(PVMCPU pVCpu, uint32_t u32ESP)
181{
182 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->esp = u32ESP;
183}
184
185
186VMMDECL(int) CPUMSetHyperEFlags(PVMCPU pVCpu, uint32_t Efl)
187{
188 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->eflags.u32 = Efl;
189 return VINF_SUCCESS;
190}
191
192
193VMMDECL(void) CPUMSetHyperEIP(PVMCPU pVCpu, uint32_t u32EIP)
194{
195 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->eip = u32EIP;
196}
197
198
199VMMDECL(void) CPUMSetHyperTR(PVMCPU pVCpu, RTSEL SelTR)
200{
201 pVCpu->cpum.s.Hyper.tr = SelTR;
202}
203
204
205VMMDECL(void) CPUMSetHyperLDTR(PVMCPU pVCpu, RTSEL SelLDTR)
206{
207 pVCpu->cpum.s.Hyper.ldtr = SelLDTR;
208}
209
210
211VMMDECL(void) CPUMSetHyperDR0(PVMCPU pVCpu, RTGCUINTREG uDr0)
212{
213 pVCpu->cpum.s.Hyper.dr[0] = uDr0;
214 /** @todo in GC we must load it! */
215}
216
217
218VMMDECL(void) CPUMSetHyperDR1(PVMCPU pVCpu, RTGCUINTREG uDr1)
219{
220 pVCpu->cpum.s.Hyper.dr[1] = uDr1;
221 /** @todo in GC we must load it! */
222}
223
224
225VMMDECL(void) CPUMSetHyperDR2(PVMCPU pVCpu, RTGCUINTREG uDr2)
226{
227 pVCpu->cpum.s.Hyper.dr[2] = uDr2;
228 /** @todo in GC we must load it! */
229}
230
231
232VMMDECL(void) CPUMSetHyperDR3(PVMCPU pVCpu, RTGCUINTREG uDr3)
233{
234 pVCpu->cpum.s.Hyper.dr[3] = uDr3;
235 /** @todo in GC we must load it! */
236}
237
238
239VMMDECL(void) CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6)
240{
241 pVCpu->cpum.s.Hyper.dr[6] = uDr6;
242 /** @todo in GC we must load it! */
243}
244
245
246VMMDECL(void) CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7)
247{
248 pVCpu->cpum.s.Hyper.dr[7] = uDr7;
249 /** @todo in GC we must load it! */
250}
251
252
253VMMDECL(RTSEL) CPUMGetHyperCS(PVMCPU pVCpu)
254{
255 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->cs;
256}
257
258
259VMMDECL(RTSEL) CPUMGetHyperDS(PVMCPU pVCpu)
260{
261 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ds;
262}
263
264
265VMMDECL(RTSEL) CPUMGetHyperES(PVMCPU pVCpu)
266{
267 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->es;
268}
269
270
271VMMDECL(RTSEL) CPUMGetHyperFS(PVMCPU pVCpu)
272{
273 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->fs;
274}
275
276
277VMMDECL(RTSEL) CPUMGetHyperGS(PVMCPU pVCpu)
278{
279 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->gs;
280}
281
282
283VMMDECL(RTSEL) CPUMGetHyperSS(PVMCPU pVCpu)
284{
285 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ss;
286}
287
288
289VMMDECL(uint32_t) CPUMGetHyperEAX(PVMCPU pVCpu)
290{
291 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->eax;
292}
293
294
295VMMDECL(uint32_t) CPUMGetHyperEBX(PVMCPU pVCpu)
296{
297 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ebx;
298}
299
300
301VMMDECL(uint32_t) CPUMGetHyperECX(PVMCPU pVCpu)
302{
303 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ecx;
304}
305
306
307VMMDECL(uint32_t) CPUMGetHyperEDX(PVMCPU pVCpu)
308{
309 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->edx;
310}
311
312
313VMMDECL(uint32_t) CPUMGetHyperESI(PVMCPU pVCpu)
314{
315 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->esi;
316}
317
318
319VMMDECL(uint32_t) CPUMGetHyperEDI(PVMCPU pVCpu)
320{
321 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->edi;
322}
323
324
325VMMDECL(uint32_t) CPUMGetHyperEBP(PVMCPU pVCpu)
326{
327 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ebp;
328}
329
330
331VMMDECL(uint32_t) CPUMGetHyperESP(PVMCPU pVCpu)
332{
333 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->esp;
334}
335
336
337VMMDECL(uint32_t) CPUMGetHyperEFlags(PVMCPU pVCpu)
338{
339 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->eflags.u32;
340}
341
342
343VMMDECL(uint32_t) CPUMGetHyperEIP(PVMCPU pVCpu)
344{
345 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->eip;
346}
347
348
349VMMDECL(uint64_t) CPUMGetHyperRIP(PVMCPU pVCpu)
350{
351 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->rip;
352}
353
354
355VMMDECL(uint32_t) CPUMGetHyperIDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
356{
357 if (pcbLimit)
358 *pcbLimit = pVCpu->cpum.s.Hyper.idtr.cbIdt;
359 return pVCpu->cpum.s.Hyper.idtr.pIdt;
360}
361
362
363VMMDECL(uint32_t) CPUMGetHyperGDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
364{
365 if (pcbLimit)
366 *pcbLimit = pVCpu->cpum.s.Hyper.gdtr.cbGdt;
367 return pVCpu->cpum.s.Hyper.gdtr.pGdt;
368}
369
370
371VMMDECL(RTSEL) CPUMGetHyperLDTR(PVMCPU pVCpu)
372{
373 return pVCpu->cpum.s.Hyper.ldtr;
374}
375
376
377VMMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVMCPU pVCpu)
378{
379 return pVCpu->cpum.s.Hyper.dr[0];
380}
381
382
383VMMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVMCPU pVCpu)
384{
385 return pVCpu->cpum.s.Hyper.dr[1];
386}
387
388
389VMMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVMCPU pVCpu)
390{
391 return pVCpu->cpum.s.Hyper.dr[2];
392}
393
394
395VMMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVMCPU pVCpu)
396{
397 return pVCpu->cpum.s.Hyper.dr[3];
398}
399
400
401VMMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVMCPU pVCpu)
402{
403 return pVCpu->cpum.s.Hyper.dr[6];
404}
405
406
407VMMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVMCPU pVCpu)
408{
409 return pVCpu->cpum.s.Hyper.dr[7];
410}
411
412
413/**
414 * Gets the pointer to the internal CPUMCTXCORE structure.
415 * This is only for reading in order to save a few calls.
416 *
417 * @param pVCpu Handle to the virtual cpu.
418 */
419VMMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVMCPU pVCpu)
420{
421 return CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
422}
423
424
425/**
426 * Sets the guest context core registers.
427 *
428 * @param pVCpu Handle to the virtual cpu.
429 * @param pCtxCore The new context core values.
430 */
431VMMDECL(void) CPUMSetGuestCtxCore(PVMCPU pVCpu, PCCPUMCTXCORE pCtxCore)
432{
433 /** @todo #1410 requires selectors to be checked. (huh? 1410?) */
434
435 PCPUMCTXCORE pCtxCoreDst = CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
436 *pCtxCoreDst = *pCtxCore;
437
438 /* Mask away invalid parts of the cpu context. */
439 if (!CPUMIsGuestInLongMode(pVCpu))
440 {
441 uint64_t u64Mask = UINT64_C(0xffffffff);
442
443 pCtxCoreDst->rip &= u64Mask;
444 pCtxCoreDst->rax &= u64Mask;
445 pCtxCoreDst->rbx &= u64Mask;
446 pCtxCoreDst->rcx &= u64Mask;
447 pCtxCoreDst->rdx &= u64Mask;
448 pCtxCoreDst->rsi &= u64Mask;
449 pCtxCoreDst->rdi &= u64Mask;
450 pCtxCoreDst->rbp &= u64Mask;
451 pCtxCoreDst->rsp &= u64Mask;
452 pCtxCoreDst->rflags.u &= u64Mask;
453
454 pCtxCoreDst->r8 = 0;
455 pCtxCoreDst->r9 = 0;
456 pCtxCoreDst->r10 = 0;
457 pCtxCoreDst->r11 = 0;
458 pCtxCoreDst->r12 = 0;
459 pCtxCoreDst->r13 = 0;
460 pCtxCoreDst->r14 = 0;
461 pCtxCoreDst->r15 = 0;
462 }
463}
464
465
466/**
467 * Queries the pointer to the internal CPUMCTX structure
468 *
469 * @returns The CPUMCTX pointer.
470 * @param pVCpu Handle to the virtual cpu.
471 */
472VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu)
473{
474 return &pVCpu->cpum.s.Guest;
475}
476
477VMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit)
478{
479 pVCpu->cpum.s.Guest.gdtr.cbGdt = cbLimit;
480 pVCpu->cpum.s.Guest.gdtr.pGdt = GCPtrBase;
481 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GDTR;
482 return VINF_SUCCESS;
483}
484
485VMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit)
486{
487 pVCpu->cpum.s.Guest.idtr.cbIdt = cbLimit;
488 pVCpu->cpum.s.Guest.idtr.pIdt = GCPtrBase;
489 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_IDTR;
490 return VINF_SUCCESS;
491}
492
493VMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr)
494{
495 pVCpu->cpum.s.Guest.tr = tr;
496 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_TR;
497 return VINF_SUCCESS;
498}
499
500VMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr)
501{
502 pVCpu->cpum.s.Guest.ldtr = ldtr;
503 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_LDTR;
504 return VINF_SUCCESS;
505}
506
507
508/**
509 * Set the guest CR0.
510 *
511 * When called in GC, the hyper CR0 may be updated if that is
512 * required. The caller only has to take special action if AM,
513 * WP, PG or PE changes.
514 *
515 * @returns VINF_SUCCESS (consider it void).
516 * @param pVCpu Handle to the virtual cpu.
517 * @param cr0 The new CR0 value.
518 */
519VMMDECL(int) CPUMSetGuestCR0(PVMCPU pVCpu, uint64_t cr0)
520{
521#ifdef IN_RC
522 /*
523 * Check if we need to change hypervisor CR0 because
524 * of math stuff.
525 */
526 if ( (cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP))
527 != (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP)))
528 {
529 if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU))
530 {
531 /*
532 * We haven't saved the host FPU state yet, so TS and MT are both set
533 * and EM should be reflecting the guest EM (it always does this).
534 */
535 if ((cr0 & X86_CR0_EM) != (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM))
536 {
537 uint32_t HyperCR0 = ASMGetCR0();
538 AssertMsg((HyperCR0 & (X86_CR0_TS | X86_CR0_MP)) == (X86_CR0_TS | X86_CR0_MP), ("%#x\n", HyperCR0));
539 AssertMsg((HyperCR0 & X86_CR0_EM) == (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM), ("%#x\n", HyperCR0));
540 HyperCR0 &= ~X86_CR0_EM;
541 HyperCR0 |= cr0 & X86_CR0_EM;
542 Log(("CPUM New HyperCR0=%#x\n", HyperCR0));
543 ASMSetCR0(HyperCR0);
544 }
545# ifdef VBOX_STRICT
546 else
547 {
548 uint32_t HyperCR0 = ASMGetCR0();
549 AssertMsg((HyperCR0 & (X86_CR0_TS | X86_CR0_MP)) == (X86_CR0_TS | X86_CR0_MP), ("%#x\n", HyperCR0));
550 AssertMsg((HyperCR0 & X86_CR0_EM) == (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM), ("%#x\n", HyperCR0));
551 }
552# endif
553 }
554 else
555 {
556 /*
557 * Already saved the state, so we're just mirroring
558 * the guest flags.
559 */
560 uint32_t HyperCR0 = ASMGetCR0();
561 AssertMsg( (HyperCR0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP))
562 == (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP)),
563 ("%#x %#x\n", HyperCR0, pVCpu->cpum.s.Guest.cr0));
564 HyperCR0 &= ~(X86_CR0_TS | X86_CR0_EM | X86_CR0_MP);
565 HyperCR0 |= cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP);
566 Log(("CPUM New HyperCR0=%#x\n", HyperCR0));
567 ASMSetCR0(HyperCR0);
568 }
569 }
570#endif /* IN_RC */
571
572 /*
573 * Check for changes causing TLB flushes (for REM).
574 * The caller is responsible for calling PGM when appropriate.
575 */
576 if ( (cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE))
577 != (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)))
578 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
579 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR0;
580
581 pVCpu->cpum.s.Guest.cr0 = cr0 | X86_CR0_ET;
582 return VINF_SUCCESS;
583}
584
585
586VMMDECL(int) CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2)
587{
588 pVCpu->cpum.s.Guest.cr2 = cr2;
589 return VINF_SUCCESS;
590}
591
592
593VMMDECL(int) CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3)
594{
595 pVCpu->cpum.s.Guest.cr3 = cr3;
596 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR3;
597 return VINF_SUCCESS;
598}
599
600
601VMMDECL(int) CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4)
602{
603 if ( (cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE))
604 != (pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE)))
605 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
606 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR4;
607 if (!CPUMSupportsFXSR(pVCpu->CTX_SUFF(pVM)))
608 cr4 &= ~X86_CR4_OSFSXR;
609 pVCpu->cpum.s.Guest.cr4 = cr4;
610 return VINF_SUCCESS;
611}
612
613
614VMMDECL(int) CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags)
615{
616 pVCpu->cpum.s.Guest.eflags.u32 = eflags;
617 return VINF_SUCCESS;
618}
619
620
621VMMDECL(int) CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip)
622{
623 pVCpu->cpum.s.Guest.eip = eip;
624 return VINF_SUCCESS;
625}
626
627
628VMMDECL(int) CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax)
629{
630 pVCpu->cpum.s.Guest.eax = eax;
631 return VINF_SUCCESS;
632}
633
634
635VMMDECL(int) CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx)
636{
637 pVCpu->cpum.s.Guest.ebx = ebx;
638 return VINF_SUCCESS;
639}
640
641
642VMMDECL(int) CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx)
643{
644 pVCpu->cpum.s.Guest.ecx = ecx;
645 return VINF_SUCCESS;
646}
647
648
649VMMDECL(int) CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx)
650{
651 pVCpu->cpum.s.Guest.edx = edx;
652 return VINF_SUCCESS;
653}
654
655
656VMMDECL(int) CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp)
657{
658 pVCpu->cpum.s.Guest.esp = esp;
659 return VINF_SUCCESS;
660}
661
662
663VMMDECL(int) CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp)
664{
665 pVCpu->cpum.s.Guest.ebp = ebp;
666 return VINF_SUCCESS;
667}
668
669
670VMMDECL(int) CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi)
671{
672 pVCpu->cpum.s.Guest.esi = esi;
673 return VINF_SUCCESS;
674}
675
676
677VMMDECL(int) CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi)
678{
679 pVCpu->cpum.s.Guest.edi = edi;
680 return VINF_SUCCESS;
681}
682
683
684VMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss)
685{
686 pVCpu->cpum.s.Guest.ss = ss;
687 return VINF_SUCCESS;
688}
689
690
691VMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs)
692{
693 pVCpu->cpum.s.Guest.cs = cs;
694 return VINF_SUCCESS;
695}
696
697
698VMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds)
699{
700 pVCpu->cpum.s.Guest.ds = ds;
701 return VINF_SUCCESS;
702}
703
704
705VMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es)
706{
707 pVCpu->cpum.s.Guest.es = es;
708 return VINF_SUCCESS;
709}
710
711
712VMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs)
713{
714 pVCpu->cpum.s.Guest.fs = fs;
715 return VINF_SUCCESS;
716}
717
718
719VMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs)
720{
721 pVCpu->cpum.s.Guest.gs = gs;
722 return VINF_SUCCESS;
723}
724
725
726VMMDECL(void) CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val)
727{
728 pVCpu->cpum.s.Guest.msrEFER = val;
729}
730
731
732/**
733 * Query an MSR.
734 *
735 * The caller is responsible for checking privilege if the call is the result
736 * of a RDMSR instruction. We'll do the rest.
737 *
738 * @retval VINF_SUCCESS on success.
739 * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR), the caller is
740 * expected to take the appropriate actions. @a *puValue is set to 0.
741 * @param pVCpu The virtual CPU to operate on.
742 * @param idMsr The MSR.
743 * @param puValue Where to return the value..
744 *
745 * @remarks This will always return the right values, even when we're in the
746 * recompiler.
747 */
748VMMDECL(int) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue)
749{
750 /*
751 * If we don't indicate MSR support in the CPUID feature bits, indicate
752 * that a #GP(0) should be raised.
753 */
754 if (!(pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_MSR))
755 {
756 *puValue = 0;
757 return VERR_CPUM_RAISE_GP_0;
758 }
759
760 int rc = VINF_SUCCESS;
761 uint8_t const u8Multiplier = 4;
762 switch (idMsr)
763 {
764 case MSR_IA32_TSC:
765 *puValue = TMCpuTickGet(pVCpu);
766 break;
767
768 case MSR_IA32_APICBASE:
769 rc = PDMApicGetBase(pVCpu->CTX_SUFF(pVM), puValue);
770 if (RT_SUCCESS(rc))
771 rc = VINF_SUCCESS;
772 else
773 {
774 *puValue = 0;
775 rc = VERR_CPUM_RAISE_GP_0;
776 }
777 break;
778
779 case MSR_IA32_CR_PAT:
780 *puValue = pVCpu->cpum.s.Guest.msrPAT;
781 break;
782
783 case MSR_IA32_SYSENTER_CS:
784 *puValue = pVCpu->cpum.s.Guest.SysEnter.cs;
785 break;
786
787 case MSR_IA32_SYSENTER_EIP:
788 *puValue = pVCpu->cpum.s.Guest.SysEnter.eip;
789 break;
790
791 case MSR_IA32_SYSENTER_ESP:
792 *puValue = pVCpu->cpum.s.Guest.SysEnter.esp;
793 break;
794
795 case MSR_K6_EFER:
796 *puValue = pVCpu->cpum.s.Guest.msrEFER;
797 break;
798
799 case MSR_K8_SF_MASK:
800 *puValue = pVCpu->cpum.s.Guest.msrSFMASK;
801 break;
802
803 case MSR_K6_STAR:
804 *puValue = pVCpu->cpum.s.Guest.msrSTAR;
805 break;
806
807 case MSR_K8_LSTAR:
808 *puValue = pVCpu->cpum.s.Guest.msrLSTAR;
809 break;
810
811 case MSR_K8_CSTAR:
812 *puValue = pVCpu->cpum.s.Guest.msrCSTAR;
813 break;
814
815 case MSR_K8_FS_BASE:
816 *puValue = pVCpu->cpum.s.Guest.fsHid.u64Base;
817 break;
818
819 case MSR_K8_GS_BASE:
820 *puValue = pVCpu->cpum.s.Guest.gsHid.u64Base;
821 break;
822
823 case MSR_K8_KERNEL_GS_BASE:
824 *puValue = pVCpu->cpum.s.Guest.msrKERNELGSBASE;
825 break;
826
827 case MSR_K8_TSC_AUX:
828 *puValue = pVCpu->cpum.s.GuestMsr.msr.tscAux;
829 break;
830
831 case MSR_IA32_PERF_STATUS:
832 /** @todo could really be not exactly correct, maybe use host's values */
833 *puValue = UINT64_C(1000) /* TSC increment by tick */
834 | ((uint64_t)u8Multiplier << 24) /* CPU multiplier (aka bus ratio) min */
835 | ((uint64_t)u8Multiplier << 40) /* CPU multiplier (aka bus ratio) max */;
836 break;
837
838 case MSR_IA32_FSB_CLOCK_STS:
839 /*
840 * Encoded as:
841 * 0 - 266
842 * 1 - 133
843 * 2 - 200
844 * 3 - return 166
845 * 5 - return 100
846 */
847 *puValue = (2 << 4);
848 break;
849
850 case MSR_IA32_PLATFORM_INFO:
851 *puValue = (u8Multiplier << 8) /* Flex ratio max */
852 | ((uint64_t)u8Multiplier << 40) /* Flex ratio min */;
853 break;
854
855 case MSR_IA32_THERM_STATUS:
856 /* CPU temperature relative to TCC, to actually activate, CPUID leaf 6 EAX[0] must be set */
857 *puValue = ( 1 << 31) /* validity bit */
858 | (20 << 16) /* degrees till TCC */;
859 break;
860
861 case MSR_IA32_MISC_ENABLE:
862#if 0
863 /* Needs to be tested more before enabling. */
864 *puValue = pVCpu->cpum.s.GuestMsr.msr.miscEnable;
865#else
866 /* Currenty we don't allow guests to modify enable MSRs. */
867 *puValue = MSR_IA32_MISC_ENABLE_FAST_STRINGS /* by default */;
868
869 if ((pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR) != 0)
870
871 *puValue |= MSR_IA32_MISC_ENABLE_MONITOR /* if mwait/monitor available */;
872 /** @todo: add more cpuid-controlled features this way. */
873#endif
874 break;
875
876#if 0 /*def IN_RING0 */
877 case MSR_IA32_PLATFORM_ID:
878 case MSR_IA32_BIOS_SIGN_ID:
879 if (CPUMGetCPUVendor(pVM) == CPUMCPUVENDOR_INTEL)
880 {
881 /* Available since the P6 family. VT-x implies that this feature is present. */
882 if (idMsr == MSR_IA32_PLATFORM_ID)
883 *puValue = ASMRdMsr(MSR_IA32_PLATFORM_ID);
884 else if (idMsr == MSR_IA32_BIOS_SIGN_ID)
885 *puValue = ASMRdMsr(MSR_IA32_BIOS_SIGN_ID);
886 break;
887 }
888 /* no break */
889#endif
890
891 default:
892 /* In X2APIC specification this range is reserved for APIC control. */
893 if ( idMsr >= MSR_IA32_APIC_START
894 && idMsr < MSR_IA32_APIC_END)
895 {
896 rc = PDMApicReadMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, puValue);
897 if (RT_SUCCESS(rc))
898 rc = VINF_SUCCESS;
899 else
900 {
901 *puValue = 0;
902 rc = VERR_CPUM_RAISE_GP_0;
903 }
904 }
905 else
906 {
907 *puValue = 0;
908 rc = VERR_CPUM_RAISE_GP_0;
909 }
910 break;
911 }
912
913 return rc;
914}
915
916
917/**
918 * Sets the MSR.
919 *
920 * The caller is responsible for checking privilege if the call is the result
921 * of a WRMSR instruction. We'll do the rest.
922 *
923 * @retval VINF_SUCCESS on success.
924 * @retval VERR_CPUM_RAISE_GP_0 on failure, the caller is expected to take the
925 * appropriate actions.
926 *
927 * @param pVCpu The virtual CPU to operate on.
928 * @param idMsr The MSR id.
929 * @param uValue The value to set.
930 *
931 * @remarks Everyone changing MSR values, including the recompiler, shall do it
932 * by calling this method. This makes sure we have current values and
933 * that we trigger all the right actions when something changes.
934 */
935VMMDECL(int) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue)
936{
937 /*
938 * If we don't indicate MSR support in the CPUID feature bits, indicate
939 * that a #GP(0) should be raised.
940 */
941 if (!(pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_MSR))
942 return VERR_CPUM_RAISE_GP_0;
943
944 int rc = VINF_SUCCESS;
945 switch (idMsr)
946 {
947 case MSR_IA32_MISC_ENABLE:
948 pVCpu->cpum.s.GuestMsr.msr.miscEnable = uValue;
949 break;
950
951 case MSR_IA32_TSC:
952 TMCpuTickSet(pVCpu->CTX_SUFF(pVM), pVCpu, uValue);
953 break;
954
955 case MSR_IA32_APICBASE:
956 rc = PDMApicSetBase(pVCpu->CTX_SUFF(pVM), uValue);
957 if (rc != VINF_SUCCESS)
958 rc = VERR_CPUM_RAISE_GP_0;
959 break;
960
961 case MSR_IA32_CR_PAT:
962 pVCpu->cpum.s.Guest.msrPAT = uValue;
963 break;
964
965 case MSR_IA32_SYSENTER_CS:
966 pVCpu->cpum.s.Guest.SysEnter.cs = uValue & 0xffff; /* 16 bits selector */
967 break;
968
969 case MSR_IA32_SYSENTER_EIP:
970 pVCpu->cpum.s.Guest.SysEnter.eip = uValue;
971 break;
972
973 case MSR_IA32_SYSENTER_ESP:
974 pVCpu->cpum.s.Guest.SysEnter.esp = uValue;
975 break;
976
977 case MSR_K6_EFER:
978 {
979 PVM pVM = pVCpu->CTX_SUFF(pVM);
980 uint64_t const uOldEFER = pVCpu->cpum.s.Guest.msrEFER;
981 uint32_t const fExtFeatures = pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
982 ? pVM->cpum.s.aGuestCpuIdExt[1].edx
983 : 0;
984 uint64_t fMask = 0;
985
986 /* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
987 if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_NX)
988 fMask |= MSR_K6_EFER_NXE;
989 if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE)
990 fMask |= MSR_K6_EFER_LME;
991 if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_SEP)
992 fMask |= MSR_K6_EFER_SCE;
993 if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
994 fMask |= MSR_K6_EFER_FFXSR;
995
996 /* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if
997 paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
998 if ( (uOldEFER & MSR_K6_EFER_LME) != (uValue & fMask & MSR_K6_EFER_LME)
999 && (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG))
1000 {
1001 Log(("Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
1002 return VERR_CPUM_RAISE_GP_0;
1003 }
1004
1005 /* There are a few more: e.g. MSR_K6_EFER_LMSLE */
1006 AssertMsg(!(uValue & ~(MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA /* ignored anyway */ | MSR_K6_EFER_SCE | MSR_K6_EFER_FFXSR)),
1007 ("Unexpected value %RX64\n", uValue));
1008 pVCpu->cpum.s.Guest.msrEFER = (uOldEFER & ~fMask) | (uValue & fMask);
1009
1010 /* AMD64 Architecture Programmer's Manual: 15.15 TLB Control; flush the TLB
1011 if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
1012 if ( (uOldEFER & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA))
1013 != (pVCpu->cpum.s.Guest.msrEFER & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA)))
1014 {
1015 /// @todo PGMFlushTLB(pVCpu, cr3, true /*fGlobal*/);
1016 HWACCMFlushTLB(pVCpu);
1017
1018 /* Notify PGM about NXE changes. */
1019 if ( (uOldEFER & MSR_K6_EFER_NXE)
1020 != (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE))
1021 PGMNotifyNxeChanged(pVCpu, !(uOldEFER & MSR_K6_EFER_NXE));
1022 }
1023 break;
1024 }
1025
1026 case MSR_K8_SF_MASK:
1027 pVCpu->cpum.s.Guest.msrSFMASK = uValue;
1028 break;
1029
1030 case MSR_K6_STAR:
1031 pVCpu->cpum.s.Guest.msrSTAR = uValue;
1032 break;
1033
1034 case MSR_K8_LSTAR:
1035 pVCpu->cpum.s.Guest.msrLSTAR = uValue;
1036 break;
1037
1038 case MSR_K8_CSTAR:
1039 pVCpu->cpum.s.Guest.msrCSTAR = uValue;
1040 break;
1041
1042 case MSR_K8_FS_BASE:
1043 pVCpu->cpum.s.Guest.fsHid.u64Base = uValue;
1044 break;
1045
1046 case MSR_K8_GS_BASE:
1047 pVCpu->cpum.s.Guest.gsHid.u64Base = uValue;
1048 break;
1049
1050 case MSR_K8_KERNEL_GS_BASE:
1051 pVCpu->cpum.s.Guest.msrKERNELGSBASE = uValue;
1052 break;
1053
1054 case MSR_K8_TSC_AUX:
1055 pVCpu->cpum.s.GuestMsr.msr.tscAux = uValue;
1056 break;
1057
1058 default:
1059 /* In X2APIC specification this range is reserved for APIC control. */
1060 if ( idMsr >= MSR_IA32_APIC_START
1061 && idMsr < MSR_IA32_APIC_END)
1062 {
1063 rc = PDMApicWriteMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, uValue);
1064 if (rc != VINF_SUCCESS)
1065 rc = VERR_CPUM_RAISE_GP_0;
1066 }
1067 else
1068 {
1069 /* We should actually trigger a #GP here, but don't as that might cause more trouble. */
1070 /** @todo rc = VERR_CPUM_RAISE_GP_0 */
1071 Log(("CPUMSetGuestMsr: Unknown MSR %#x attempted set to %#llx\n", idMsr, uValue));
1072 }
1073 break;
1074 }
1075 return rc;
1076}
1077
1078
1079VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
1080{
1081 if (pcbLimit)
1082 *pcbLimit = pVCpu->cpum.s.Guest.idtr.cbIdt;
1083 return pVCpu->cpum.s.Guest.idtr.pIdt;
1084}
1085
1086
1087VMMDECL(RTSEL) CPUMGetGuestTR(PVMCPU pVCpu, PCPUMSELREGHID pHidden)
1088{
1089 if (pHidden)
1090 *pHidden = pVCpu->cpum.s.Guest.trHid;
1091 return pVCpu->cpum.s.Guest.tr;
1092}
1093
1094
1095VMMDECL(RTSEL) CPUMGetGuestCS(PVMCPU pVCpu)
1096{
1097 return pVCpu->cpum.s.Guest.cs;
1098}
1099
1100
1101VMMDECL(RTSEL) CPUMGetGuestDS(PVMCPU pVCpu)
1102{
1103 return pVCpu->cpum.s.Guest.ds;
1104}
1105
1106
1107VMMDECL(RTSEL) CPUMGetGuestES(PVMCPU pVCpu)
1108{
1109 return pVCpu->cpum.s.Guest.es;
1110}
1111
1112
1113VMMDECL(RTSEL) CPUMGetGuestFS(PVMCPU pVCpu)
1114{
1115 return pVCpu->cpum.s.Guest.fs;
1116}
1117
1118
1119VMMDECL(RTSEL) CPUMGetGuestGS(PVMCPU pVCpu)
1120{
1121 return pVCpu->cpum.s.Guest.gs;
1122}
1123
1124
1125VMMDECL(RTSEL) CPUMGetGuestSS(PVMCPU pVCpu)
1126{
1127 return pVCpu->cpum.s.Guest.ss;
1128}
1129
1130
1131VMMDECL(RTSEL) CPUMGetGuestLDTR(PVMCPU pVCpu)
1132{
1133 return pVCpu->cpum.s.Guest.ldtr;
1134}
1135
1136
1137VMMDECL(uint64_t) CPUMGetGuestCR0(PVMCPU pVCpu)
1138{
1139 return pVCpu->cpum.s.Guest.cr0;
1140}
1141
1142
1143VMMDECL(uint64_t) CPUMGetGuestCR2(PVMCPU pVCpu)
1144{
1145 return pVCpu->cpum.s.Guest.cr2;
1146}
1147
1148
1149VMMDECL(uint64_t) CPUMGetGuestCR3(PVMCPU pVCpu)
1150{
1151 return pVCpu->cpum.s.Guest.cr3;
1152}
1153
1154
1155VMMDECL(uint64_t) CPUMGetGuestCR4(PVMCPU pVCpu)
1156{
1157 return pVCpu->cpum.s.Guest.cr4;
1158}
1159
1160
1161VMMDECL(uint64_t) CPUMGetGuestCR8(PVMCPU pVCpu)
1162{
1163 uint64_t u64;
1164 int rc = CPUMGetGuestCRx(pVCpu, USE_REG_CR8, &u64);
1165 if (RT_FAILURE(rc))
1166 u64 = 0;
1167 return u64;
1168}
1169
1170
1171VMMDECL(void) CPUMGetGuestGDTR(PVMCPU pVCpu, PVBOXGDTR pGDTR)
1172{
1173 *pGDTR = pVCpu->cpum.s.Guest.gdtr;
1174}
1175
1176
1177VMMDECL(uint32_t) CPUMGetGuestEIP(PVMCPU pVCpu)
1178{
1179 return pVCpu->cpum.s.Guest.eip;
1180}
1181
1182
1183VMMDECL(uint64_t) CPUMGetGuestRIP(PVMCPU pVCpu)
1184{
1185 return pVCpu->cpum.s.Guest.rip;
1186}
1187
1188
1189VMMDECL(uint32_t) CPUMGetGuestEAX(PVMCPU pVCpu)
1190{
1191 return pVCpu->cpum.s.Guest.eax;
1192}
1193
1194
1195VMMDECL(uint32_t) CPUMGetGuestEBX(PVMCPU pVCpu)
1196{
1197 return pVCpu->cpum.s.Guest.ebx;
1198}
1199
1200
1201VMMDECL(uint32_t) CPUMGetGuestECX(PVMCPU pVCpu)
1202{
1203 return pVCpu->cpum.s.Guest.ecx;
1204}
1205
1206
1207VMMDECL(uint32_t) CPUMGetGuestEDX(PVMCPU pVCpu)
1208{
1209 return pVCpu->cpum.s.Guest.edx;
1210}
1211
1212
1213VMMDECL(uint32_t) CPUMGetGuestESI(PVMCPU pVCpu)
1214{
1215 return pVCpu->cpum.s.Guest.esi;
1216}
1217
1218
1219VMMDECL(uint32_t) CPUMGetGuestEDI(PVMCPU pVCpu)
1220{
1221 return pVCpu->cpum.s.Guest.edi;
1222}
1223
1224
1225VMMDECL(uint32_t) CPUMGetGuestESP(PVMCPU pVCpu)
1226{
1227 return pVCpu->cpum.s.Guest.esp;
1228}
1229
1230
1231VMMDECL(uint32_t) CPUMGetGuestEBP(PVMCPU pVCpu)
1232{
1233 return pVCpu->cpum.s.Guest.ebp;
1234}
1235
1236
1237VMMDECL(uint32_t) CPUMGetGuestEFlags(PVMCPU pVCpu)
1238{
1239 return pVCpu->cpum.s.Guest.eflags.u32;
1240}
1241
1242
1243VMMDECL(int) CPUMGetGuestCRx(PVMCPU pVCpu, unsigned iReg, uint64_t *pValue)
1244{
1245 switch (iReg)
1246 {
1247 case USE_REG_CR0:
1248 *pValue = pVCpu->cpum.s.Guest.cr0;
1249 break;
1250
1251 case USE_REG_CR2:
1252 *pValue = pVCpu->cpum.s.Guest.cr2;
1253 break;
1254
1255 case USE_REG_CR3:
1256 *pValue = pVCpu->cpum.s.Guest.cr3;
1257 break;
1258
1259 case USE_REG_CR4:
1260 *pValue = pVCpu->cpum.s.Guest.cr4;
1261 break;
1262
1263 case USE_REG_CR8:
1264 {
1265 uint8_t u8Tpr;
1266 int rc = PDMApicGetTPR(pVCpu, &u8Tpr, NULL /*pfPending*/);
1267 if (RT_FAILURE(rc))
1268 {
1269 AssertMsg(rc == VERR_PDM_NO_APIC_INSTANCE, ("%Rrc\n", rc));
1270 *pValue = 0;
1271 return rc;
1272 }
1273 *pValue = u8Tpr >> 4; /* bits 7-4 contain the task priority that go in cr8, bits 3-0*/
1274 break;
1275 }
1276
1277 default:
1278 return VERR_INVALID_PARAMETER;
1279 }
1280 return VINF_SUCCESS;
1281}
1282
1283
1284VMMDECL(uint64_t) CPUMGetGuestDR0(PVMCPU pVCpu)
1285{
1286 return pVCpu->cpum.s.Guest.dr[0];
1287}
1288
1289
1290VMMDECL(uint64_t) CPUMGetGuestDR1(PVMCPU pVCpu)
1291{
1292 return pVCpu->cpum.s.Guest.dr[1];
1293}
1294
1295
1296VMMDECL(uint64_t) CPUMGetGuestDR2(PVMCPU pVCpu)
1297{
1298 return pVCpu->cpum.s.Guest.dr[2];
1299}
1300
1301
1302VMMDECL(uint64_t) CPUMGetGuestDR3(PVMCPU pVCpu)
1303{
1304 return pVCpu->cpum.s.Guest.dr[3];
1305}
1306
1307
1308VMMDECL(uint64_t) CPUMGetGuestDR6(PVMCPU pVCpu)
1309{
1310 return pVCpu->cpum.s.Guest.dr[6];
1311}
1312
1313
1314VMMDECL(uint64_t) CPUMGetGuestDR7(PVMCPU pVCpu)
1315{
1316 return pVCpu->cpum.s.Guest.dr[7];
1317}
1318
1319
1320VMMDECL(int) CPUMGetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t *pValue)
1321{
1322 AssertReturn(iReg <= USE_REG_DR7, VERR_INVALID_PARAMETER);
1323 /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
1324 if (iReg == 4 || iReg == 5)
1325 iReg += 2;
1326 *pValue = pVCpu->cpum.s.Guest.dr[iReg];
1327 return VINF_SUCCESS;
1328}
1329
1330
1331VMMDECL(uint64_t) CPUMGetGuestEFER(PVMCPU pVCpu)
1332{
1333 return pVCpu->cpum.s.Guest.msrEFER;
1334}
1335
1336
1337/**
1338 * Gets a CpuId leaf.
1339 *
1340 * @param pVCpu The VMCPU handle.
1341 * @param iLeaf The CPUID leaf to get.
1342 * @param pEax Where to store the EAX value.
1343 * @param pEbx Where to store the EBX value.
1344 * @param pEcx Where to store the ECX value.
1345 * @param pEdx Where to store the EDX value.
1346 */
1347VMMDECL(void) CPUMGetGuestCpuId(PVMCPU pVCpu, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx)
1348{
1349 PVM pVM = pVCpu->CTX_SUFF(pVM);
1350
1351 PCCPUMCPUID pCpuId;
1352 if (iLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
1353 pCpuId = &pVM->cpum.s.aGuestCpuIdStd[iLeaf];
1354 else if (iLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
1355 pCpuId = &pVM->cpum.s.aGuestCpuIdExt[iLeaf - UINT32_C(0x80000000)];
1356 else if (iLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
1357 pCpuId = &pVM->cpum.s.aGuestCpuIdCentaur[iLeaf - UINT32_C(0xc0000000)];
1358 else
1359 pCpuId = &pVM->cpum.s.GuestCpuIdDef;
1360
1361 uint32_t cCurrentCacheIndex = *pEcx;
1362
1363 *pEax = pCpuId->eax;
1364 *pEbx = pCpuId->ebx;
1365 *pEcx = pCpuId->ecx;
1366 *pEdx = pCpuId->edx;
1367
1368 if ( iLeaf == 1)
1369 {
1370 /* Bits 31-24: Initial APIC ID */
1371 Assert(pVCpu->idCpu <= 255);
1372 *pEbx |= (pVCpu->idCpu << 24);
1373 }
1374
1375 if ( iLeaf == 4
1376 && cCurrentCacheIndex < 3
1377 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
1378 {
1379 uint32_t type, level, sharing, linesize,
1380 partitions, associativity, sets, cores;
1381
1382 /* For type: 1 - data cache, 2 - i-cache, 3 - unified */
1383 partitions = 1;
1384 /* Those are only to shut up compiler, as they will always
1385 get overwritten, and compiler should be able to figure that out */
1386 sets = associativity = sharing = level = 1;
1387 cores = pVM->cCpus > 32 ? 32 : pVM->cCpus;
1388 switch (cCurrentCacheIndex)
1389 {
1390 case 0:
1391 type = 1;
1392 level = 1;
1393 sharing = 1;
1394 linesize = 64;
1395 associativity = 8;
1396 sets = 64;
1397 break;
1398 case 1:
1399 level = 1;
1400 type = 2;
1401 sharing = 1;
1402 linesize = 64;
1403 associativity = 8;
1404 sets = 64;
1405 break;
1406 default: /* shut up gcc.*/
1407 AssertFailed();
1408 case 2:
1409 level = 2;
1410 type = 3;
1411 sharing = cores; /* our L2 cache is modelled as shared between all cores */
1412 linesize = 64;
1413 associativity = 24;
1414 sets = 4096;
1415 break;
1416 }
1417
1418 *pEax |= ((cores - 1) << 26) |
1419 ((sharing - 1) << 14) |
1420 (level << 5) |
1421 1;
1422 *pEbx = (linesize - 1) |
1423 ((partitions - 1) << 12) |
1424 ((associativity - 1) << 22); /* -1 encoding */
1425 *pEcx = sets - 1;
1426 }
1427
1428 Log2(("CPUMGetGuestCpuId: iLeaf=%#010x %RX32 %RX32 %RX32 %RX32\n", iLeaf, *pEax, *pEbx, *pEcx, *pEdx));
1429}
1430
1431/**
1432 * Gets a number of standard CPUID leafs.
1433 *
1434 * @returns Number of leafs.
1435 * @param pVM The VM handle.
1436 * @remark Intended for PATM.
1437 */
1438VMMDECL(uint32_t) CPUMGetGuestCpuIdStdMax(PVM pVM)
1439{
1440 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd);
1441}
1442
1443
1444/**
1445 * Gets a number of extended CPUID leafs.
1446 *
1447 * @returns Number of leafs.
1448 * @param pVM The VM handle.
1449 * @remark Intended for PATM.
1450 */
1451VMMDECL(uint32_t) CPUMGetGuestCpuIdExtMax(PVM pVM)
1452{
1453 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt);
1454}
1455
1456
1457/**
1458 * Gets a number of centaur CPUID leafs.
1459 *
1460 * @returns Number of leafs.
1461 * @param pVM The VM handle.
1462 * @remark Intended for PATM.
1463 */
1464VMMDECL(uint32_t) CPUMGetGuestCpuIdCentaurMax(PVM pVM)
1465{
1466 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur);
1467}
1468
1469
1470/**
1471 * Sets a CPUID feature bit.
1472 *
1473 * @param pVM The VM Handle.
1474 * @param enmFeature The feature to set.
1475 */
1476VMMDECL(void) CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
1477{
1478 switch (enmFeature)
1479 {
1480 /*
1481 * Set the APIC bit in both feature masks.
1482 */
1483 case CPUMCPUIDFEATURE_APIC:
1484 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1485 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_APIC;
1486 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1487 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1488 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_APIC;
1489 LogRel(("CPUMSetGuestCpuIdFeature: Enabled APIC\n"));
1490 break;
1491
1492 /*
1493 * Set the x2APIC bit in the standard feature mask.
1494 */
1495 case CPUMCPUIDFEATURE_X2APIC:
1496 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1497 pVM->cpum.s.aGuestCpuIdStd[1].ecx |= X86_CPUID_FEATURE_ECX_X2APIC;
1498 LogRel(("CPUMSetGuestCpuIdFeature: Enabled x2APIC\n"));
1499 break;
1500
1501 /*
1502 * Set the sysenter/sysexit bit in the standard feature mask.
1503 * Assumes the caller knows what it's doing! (host must support these)
1504 */
1505 case CPUMCPUIDFEATURE_SEP:
1506 {
1507 if (!(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_SEP))
1508 {
1509 AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
1510 return;
1511 }
1512
1513 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1514 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_SEP;
1515 LogRel(("CPUMSetGuestCpuIdFeature: Enabled sysenter/exit\n"));
1516 break;
1517 }
1518
1519 /*
1520 * Set the syscall/sysret bit in the extended feature mask.
1521 * Assumes the caller knows what it's doing! (host must support these)
1522 */
1523 case CPUMCPUIDFEATURE_SYSCALL:
1524 {
1525 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1526 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_SEP))
1527 {
1528#if HC_ARCH_BITS == 32
1529 /* X86_CPUID_AMD_FEATURE_EDX_SEP not set it seems in 32 bits mode.
1530 * Even when the cpu is capable of doing so in 64 bits mode.
1531 */
1532 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1533 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE)
1534 || !(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_SEP))
1535#endif
1536 {
1537 LogRel(("WARNING: Can't turn on SYSCALL/SYSRET when the host doesn't support it!!\n"));
1538 return;
1539 }
1540 }
1541 /* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
1542 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_SEP;
1543 LogRel(("CPUMSetGuestCpuIdFeature: Enabled syscall/ret\n"));
1544 break;
1545 }
1546
1547 /*
1548 * Set the PAE bit in both feature masks.
1549 * Assumes the caller knows what it's doing! (host must support these)
1550 */
1551 case CPUMCPUIDFEATURE_PAE:
1552 {
1553 if (!(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_PAE))
1554 {
1555 LogRel(("WARNING: Can't turn on PAE when the host doesn't support it!!\n"));
1556 return;
1557 }
1558
1559 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1560 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_PAE;
1561 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1562 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1563 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_PAE;
1564 LogRel(("CPUMSetGuestCpuIdFeature: Enabled PAE\n"));
1565 break;
1566 }
1567
1568 /*
1569 * Set the LONG MODE bit in the extended feature mask.
1570 * Assumes the caller knows what it's doing! (host must support these)
1571 */
1572 case CPUMCPUIDFEATURE_LONG_MODE:
1573 {
1574 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1575 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE))
1576 {
1577 LogRel(("WARNING: Can't turn on LONG MODE when the host doesn't support it!!\n"));
1578 return;
1579 }
1580
1581 /* Valid for both Intel and AMD. */
1582 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_LONG_MODE;
1583 LogRel(("CPUMSetGuestCpuIdFeature: Enabled LONG MODE\n"));
1584 break;
1585 }
1586
1587 /*
1588 * Set the NXE bit in the extended feature mask.
1589 * Assumes the caller knows what it's doing! (host must support these)
1590 */
1591 case CPUMCPUIDFEATURE_NXE:
1592 {
1593 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1594 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_NX))
1595 {
1596 LogRel(("WARNING: Can't turn on NXE when the host doesn't support it!!\n"));
1597 return;
1598 }
1599
1600 /* Valid for both Intel and AMD. */
1601 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_NX;
1602 LogRel(("CPUMSetGuestCpuIdFeature: Enabled NXE\n"));
1603 break;
1604 }
1605
1606 case CPUMCPUIDFEATURE_LAHF:
1607 {
1608 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1609 || !(ASMCpuId_ECX(0x80000001) & X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF))
1610 {
1611 LogRel(("WARNING: Can't turn on LAHF/SAHF when the host doesn't support it!!\n"));
1612 return;
1613 }
1614
1615 pVM->cpum.s.aGuestCpuIdExt[1].ecx |= X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF;
1616 LogRel(("CPUMSetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
1617 break;
1618 }
1619
1620 case CPUMCPUIDFEATURE_PAT:
1621 {
1622 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1623 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_PAT;
1624 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1625 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1626 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_PAT;
1627 LogRel(("CPUMClearGuestCpuIdFeature: Enabled PAT\n"));
1628 break;
1629 }
1630
1631 case CPUMCPUIDFEATURE_RDTSCP:
1632 {
1633 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1634 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_RDTSCP)
1635 || pVM->cpum.s.u8PortableCpuIdLevel > 0)
1636 {
1637 if (!pVM->cpum.s.u8PortableCpuIdLevel)
1638 LogRel(("WARNING: Can't turn on RDTSCP when the host doesn't support it!!\n"));
1639 return;
1640 }
1641
1642 /* Valid for AMD only (for now). */
1643 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_RDTSCP;
1644 LogRel(("CPUMSetGuestCpuIdFeature: Enabled RDTSCP.\n"));
1645 break;
1646 }
1647
1648 default:
1649 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
1650 break;
1651 }
1652 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1653 {
1654 PVMCPU pVCpu = &pVM->aCpus[i];
1655 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CPUID;
1656 }
1657}
1658
1659
1660/**
1661 * Queries a CPUID feature bit.
1662 *
1663 * @returns boolean for feature presence
1664 * @param pVM The VM Handle.
1665 * @param enmFeature The feature to query.
1666 */
1667VMMDECL(bool) CPUMGetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
1668{
1669 switch (enmFeature)
1670 {
1671 case CPUMCPUIDFEATURE_PAE:
1672 {
1673 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1674 return !!(pVM->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PAE);
1675 break;
1676 }
1677
1678 case CPUMCPUIDFEATURE_NXE:
1679 {
1680 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1681 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_AMD_FEATURE_EDX_NX);
1682 }
1683
1684 case CPUMCPUIDFEATURE_RDTSCP:
1685 {
1686 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1687 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
1688 break;
1689 }
1690
1691 case CPUMCPUIDFEATURE_LONG_MODE:
1692 {
1693 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1694 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE);
1695 break;
1696 }
1697
1698 default:
1699 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
1700 break;
1701 }
1702 return false;
1703}
1704
1705
1706/**
1707 * Clears a CPUID feature bit.
1708 *
1709 * @param pVM The VM Handle.
1710 * @param enmFeature The feature to clear.
1711 */
1712VMMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
1713{
1714 switch (enmFeature)
1715 {
1716 /*
1717 * Set the APIC bit in both feature masks.
1718 */
1719 case CPUMCPUIDFEATURE_APIC:
1720 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1721 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_APIC;
1722 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1723 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1724 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
1725 Log(("CPUMSetGuestCpuIdFeature: Disabled APIC\n"));
1726 break;
1727
1728 /*
1729 * Clear the x2APIC bit in the standard feature mask.
1730 */
1731 case CPUMCPUIDFEATURE_X2APIC:
1732 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1733 pVM->cpum.s.aGuestCpuIdStd[1].ecx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
1734 LogRel(("CPUMSetGuestCpuIdFeature: Disabled x2APIC\n"));
1735 break;
1736
1737 case CPUMCPUIDFEATURE_PAE:
1738 {
1739 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1740 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_PAE;
1741 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1742 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1743 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
1744 LogRel(("CPUMClearGuestCpuIdFeature: Disabled PAE!\n"));
1745 break;
1746 }
1747
1748 case CPUMCPUIDFEATURE_PAT:
1749 {
1750 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1751 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_PAT;
1752 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1753 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1754 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_PAT;
1755 LogRel(("CPUMClearGuestCpuIdFeature: Disabled PAT!\n"));
1756 break;
1757 }
1758
1759 case CPUMCPUIDFEATURE_LONG_MODE:
1760 {
1761 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1762 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_LONG_MODE;
1763 break;
1764 }
1765
1766 case CPUMCPUIDFEATURE_LAHF:
1767 {
1768 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1769 pVM->cpum.s.aGuestCpuIdExt[1].ecx &= ~X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF;
1770 break;
1771 }
1772
1773 default:
1774 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
1775 break;
1776 }
1777 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1778 {
1779 PVMCPU pVCpu = &pVM->aCpus[i];
1780 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CPUID;
1781 }
1782}
1783
1784
1785/**
1786 * Gets the host CPU vendor
1787 *
1788 * @returns CPU vendor
1789 * @param pVM The VM handle.
1790 */
1791VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM)
1792{
1793 return pVM->cpum.s.enmHostCpuVendor;
1794}
1795
1796/**
1797 * Gets the CPU vendor
1798 *
1799 * @returns CPU vendor
1800 * @param pVM The VM handle.
1801 */
1802VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM)
1803{
1804 return pVM->cpum.s.enmGuestCpuVendor;
1805}
1806
1807
1808VMMDECL(int) CPUMSetGuestDR0(PVMCPU pVCpu, uint64_t uDr0)
1809{
1810 pVCpu->cpum.s.Guest.dr[0] = uDr0;
1811 return CPUMRecalcHyperDRx(pVCpu);
1812}
1813
1814
1815VMMDECL(int) CPUMSetGuestDR1(PVMCPU pVCpu, uint64_t uDr1)
1816{
1817 pVCpu->cpum.s.Guest.dr[1] = uDr1;
1818 return CPUMRecalcHyperDRx(pVCpu);
1819}
1820
1821
1822VMMDECL(int) CPUMSetGuestDR2(PVMCPU pVCpu, uint64_t uDr2)
1823{
1824 pVCpu->cpum.s.Guest.dr[2] = uDr2;
1825 return CPUMRecalcHyperDRx(pVCpu);
1826}
1827
1828
1829VMMDECL(int) CPUMSetGuestDR3(PVMCPU pVCpu, uint64_t uDr3)
1830{
1831 pVCpu->cpum.s.Guest.dr[3] = uDr3;
1832 return CPUMRecalcHyperDRx(pVCpu);
1833}
1834
1835
1836VMMDECL(int) CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6)
1837{
1838 pVCpu->cpum.s.Guest.dr[6] = uDr6;
1839 return CPUMRecalcHyperDRx(pVCpu);
1840}
1841
1842
1843VMMDECL(int) CPUMSetGuestDR7(PVMCPU pVCpu, uint64_t uDr7)
1844{
1845 pVCpu->cpum.s.Guest.dr[7] = uDr7;
1846 return CPUMRecalcHyperDRx(pVCpu);
1847}
1848
1849
1850VMMDECL(int) CPUMSetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t Value)
1851{
1852 AssertReturn(iReg <= USE_REG_DR7, VERR_INVALID_PARAMETER);
1853 /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
1854 if (iReg == 4 || iReg == 5)
1855 iReg += 2;
1856 pVCpu->cpum.s.Guest.dr[iReg] = Value;
1857 return CPUMRecalcHyperDRx(pVCpu);
1858}
1859
1860
1861/**
1862 * Recalculates the hypervisor DRx register values based on
1863 * current guest registers and DBGF breakpoints.
1864 *
1865 * This is called whenever a guest DRx register is modified and when DBGF
1866 * sets a hardware breakpoint. In guest context this function will reload
1867 * any (hyper) DRx registers which comes out with a different value.
1868 *
1869 * @returns VINF_SUCCESS.
1870 * @param pVCpu The VMCPU handle.
1871 */
1872VMMDECL(int) CPUMRecalcHyperDRx(PVMCPU pVCpu)
1873{
1874 PVM pVM = pVCpu->CTX_SUFF(pVM);
1875
1876 /*
1877 * Compare the DR7s first.
1878 *
1879 * We only care about the enabled flags. The GE and LE flags are always
1880 * set and we don't care if the guest doesn't set them. GD is virtualized
1881 * when we dispatch #DB, we never enable it.
1882 */
1883 const RTGCUINTREG uDbgfDr7 = DBGFBpGetDR7(pVM);
1884#ifdef CPUM_VIRTUALIZE_DRX
1885 const RTGCUINTREG uGstDr7 = CPUMGetGuestDR7(pVCpu);
1886#else
1887 const RTGCUINTREG uGstDr7 = 0;
1888#endif
1889 if ((uGstDr7 | uDbgfDr7) & X86_DR7_ENABLED_MASK)
1890 {
1891 /*
1892 * Ok, something is enabled. Recalc each of the breakpoints.
1893 * Straight forward code, not optimized/minimized in any way.
1894 */
1895 RTGCUINTREG uNewDr7 = X86_DR7_GE | X86_DR7_LE | X86_DR7_MB1_MASK;
1896
1897 /* bp 0 */
1898 RTGCUINTREG uNewDr0;
1899 if (uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0))
1900 {
1901 uNewDr7 |= uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
1902 uNewDr0 = DBGFBpGetDR0(pVM);
1903 }
1904 else if (uGstDr7 & (X86_DR7_L0 | X86_DR7_G0))
1905 {
1906 uNewDr7 |= uGstDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
1907 uNewDr0 = CPUMGetGuestDR0(pVCpu);
1908 }
1909 else
1910 uNewDr0 = pVCpu->cpum.s.Hyper.dr[0];
1911
1912 /* bp 1 */
1913 RTGCUINTREG uNewDr1;
1914 if (uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1))
1915 {
1916 uNewDr7 |= uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
1917 uNewDr1 = DBGFBpGetDR1(pVM);
1918 }
1919 else if (uGstDr7 & (X86_DR7_L1 | X86_DR7_G1))
1920 {
1921 uNewDr7 |= uGstDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
1922 uNewDr1 = CPUMGetGuestDR1(pVCpu);
1923 }
1924 else
1925 uNewDr1 = pVCpu->cpum.s.Hyper.dr[1];
1926
1927 /* bp 2 */
1928 RTGCUINTREG uNewDr2;
1929 if (uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2))
1930 {
1931 uNewDr7 |= uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
1932 uNewDr2 = DBGFBpGetDR2(pVM);
1933 }
1934 else if (uGstDr7 & (X86_DR7_L2 | X86_DR7_G2))
1935 {
1936 uNewDr7 |= uGstDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
1937 uNewDr2 = CPUMGetGuestDR2(pVCpu);
1938 }
1939 else
1940 uNewDr2 = pVCpu->cpum.s.Hyper.dr[2];
1941
1942 /* bp 3 */
1943 RTGCUINTREG uNewDr3;
1944 if (uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3))
1945 {
1946 uNewDr7 |= uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
1947 uNewDr3 = DBGFBpGetDR3(pVM);
1948 }
1949 else if (uGstDr7 & (X86_DR7_L3 | X86_DR7_G3))
1950 {
1951 uNewDr7 |= uGstDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
1952 uNewDr3 = CPUMGetGuestDR3(pVCpu);
1953 }
1954 else
1955 uNewDr3 = pVCpu->cpum.s.Hyper.dr[3];
1956
1957 /*
1958 * Apply the updates.
1959 */
1960#ifdef IN_RC
1961 if (!(pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS))
1962 {
1963 /** @todo save host DBx registers. */
1964 }
1965#endif
1966 pVCpu->cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS;
1967 if (uNewDr3 != pVCpu->cpum.s.Hyper.dr[3])
1968 CPUMSetHyperDR3(pVCpu, uNewDr3);
1969 if (uNewDr2 != pVCpu->cpum.s.Hyper.dr[2])
1970 CPUMSetHyperDR2(pVCpu, uNewDr2);
1971 if (uNewDr1 != pVCpu->cpum.s.Hyper.dr[1])
1972 CPUMSetHyperDR1(pVCpu, uNewDr1);
1973 if (uNewDr0 != pVCpu->cpum.s.Hyper.dr[0])
1974 CPUMSetHyperDR0(pVCpu, uNewDr0);
1975 if (uNewDr7 != pVCpu->cpum.s.Hyper.dr[7])
1976 CPUMSetHyperDR7(pVCpu, uNewDr7);
1977 }
1978 else
1979 {
1980#ifdef IN_RC
1981 if (pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS)
1982 {
1983 /** @todo restore host DBx registers. */
1984 }
1985#endif
1986 pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS;
1987 }
1988 Log2(("CPUMRecalcHyperDRx: fUseFlags=%#x %RGr %RGr %RGr %RGr %RGr %RGr\n",
1989 pVCpu->cpum.s.fUseFlags, pVCpu->cpum.s.Hyper.dr[0], pVCpu->cpum.s.Hyper.dr[1],
1990 pVCpu->cpum.s.Hyper.dr[2], pVCpu->cpum.s.Hyper.dr[3], pVCpu->cpum.s.Hyper.dr[6],
1991 pVCpu->cpum.s.Hyper.dr[7]));
1992
1993 return VINF_SUCCESS;
1994}
1995
1996
1997/**
1998 * Tests if the guest has No-Execute Page Protection Enabled (NXE).
1999 *
2000 * @returns true if in real mode, otherwise false.
2001 * @param pVCpu The virtual CPU handle.
2002 */
2003VMMDECL(bool) CPUMIsGuestNXEnabled(PVMCPU pVCpu)
2004{
2005 return !!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE);
2006}
2007
2008
2009/**
2010 * Tests if the guest has the Page Size Extension enabled (PSE).
2011 *
2012 * @returns true if in real mode, otherwise false.
2013 * @param pVCpu The virtual CPU handle.
2014 */
2015VMMDECL(bool) CPUMIsGuestPageSizeExtEnabled(PVMCPU pVCpu)
2016{
2017 /* PAE or AMD64 implies support for big pages regardless of CR4.PSE */
2018 return !!(pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PSE | X86_CR4_PAE));
2019}
2020
2021
2022/**
2023 * Tests if the guest has the paging enabled (PG).
2024 *
2025 * @returns true if in real mode, otherwise false.
2026 * @param pVCpu The virtual CPU handle.
2027 */
2028VMMDECL(bool) CPUMIsGuestPagingEnabled(PVMCPU pVCpu)
2029{
2030 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG);
2031}
2032
2033
2034/**
2035 * Tests if the guest has the paging enabled (PG).
2036 *
2037 * @returns true if in real mode, otherwise false.
2038 * @param pVCpu The virtual CPU handle.
2039 */
2040VMMDECL(bool) CPUMIsGuestR0WriteProtEnabled(PVMCPU pVCpu)
2041{
2042 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_WP);
2043}
2044
2045
2046/**
2047 * Tests if the guest is running in real mode or not.
2048 *
2049 * @returns true if in real mode, otherwise false.
2050 * @param pVCpu The virtual CPU handle.
2051 */
2052VMMDECL(bool) CPUMIsGuestInRealMode(PVMCPU pVCpu)
2053{
2054 return !(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
2055}
2056
2057
2058/**
2059 * Tests if the guest is running in real or virtual 8086 mode.
2060 *
2061 * @returns @c true if it is, @c false if not.
2062 * @param pVCpu The virtual CPU handle.
2063 */
2064VMMDECL(bool) CPUMIsGuestInRealOrV86Mode(PVMCPU pVCpu)
2065{
2066 return !(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE)
2067 || pVCpu->cpum.s.Guest.eflags.Bits.u1VM; /** @todo verify that this cannot be set in long mode. */
2068}
2069
2070
2071/**
2072 * Tests if the guest is running in protected or not.
2073 *
2074 * @returns true if in protected mode, otherwise false.
2075 * @param pVCpu The virtual CPU handle.
2076 */
2077VMMDECL(bool) CPUMIsGuestInProtectedMode(PVMCPU pVCpu)
2078{
2079 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
2080}
2081
2082
2083/**
2084 * Tests if the guest is running in paged protected or not.
2085 *
2086 * @returns true if in paged protected mode, otherwise false.
2087 * @param pVCpu The virtual CPU handle.
2088 */
2089VMMDECL(bool) CPUMIsGuestInPagedProtectedMode(PVMCPU pVCpu)
2090{
2091 return (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
2092}
2093
2094
2095/**
2096 * Tests if the guest is running in long mode or not.
2097 *
2098 * @returns true if in long mode, otherwise false.
2099 * @param pVCpu The virtual CPU handle.
2100 */
2101VMMDECL(bool) CPUMIsGuestInLongMode(PVMCPU pVCpu)
2102{
2103 return (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
2104}
2105
2106
2107/**
2108 * Tests if the guest is running in PAE mode or not.
2109 *
2110 * @returns true if in PAE mode, otherwise false.
2111 * @param pVCpu The virtual CPU handle.
2112 */
2113VMMDECL(bool) CPUMIsGuestInPAEMode(PVMCPU pVCpu)
2114{
2115 return (pVCpu->cpum.s.Guest.cr4 & X86_CR4_PAE)
2116 && (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG)
2117 && !(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA);
2118}
2119
2120
2121#ifndef IN_RING0
2122/**
2123 * Updates the EFLAGS while we're in raw-mode.
2124 *
2125 * @param pVCpu The VMCPU handle.
2126 * @param pCtxCore The context core.
2127 * @param eflags The new EFLAGS value.
2128 */
2129VMMDECL(void) CPUMRawSetEFlags(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, uint32_t eflags)
2130{
2131 PVM pVM = pVCpu->CTX_SUFF(pVM);
2132
2133 if (!pVCpu->cpum.s.fRawEntered)
2134 {
2135 pCtxCore->eflags.u32 = eflags;
2136 return;
2137 }
2138 PATMRawSetEFlags(pVM, pCtxCore, eflags);
2139}
2140#endif /* !IN_RING0 */
2141
2142
2143/**
2144 * Gets the EFLAGS while we're in raw-mode.
2145 *
2146 * @returns The eflags.
2147 * @param pVCpu The VMCPU handle.
2148 * @param pCtxCore The context core.
2149 */
2150VMMDECL(uint32_t) CPUMRawGetEFlags(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
2151{
2152#ifdef IN_RING0
2153 return pCtxCore->eflags.u32;
2154#else
2155 PVM pVM = pVCpu->CTX_SUFF(pVM);
2156
2157 if (!pVCpu->cpum.s.fRawEntered)
2158 return pCtxCore->eflags.u32;
2159 return PATMRawGetEFlags(pVM, pCtxCore);
2160#endif
2161}
2162
2163
2164/**
2165 * Sets the specified changed flags (CPUM_CHANGED_*).
2166 *
2167 * @param pVCpu The VMCPU handle.
2168 */
2169VMMDECL(void) CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedFlags)
2170{
2171 pVCpu->cpum.s.fChanged |= fChangedFlags;
2172}
2173
2174
2175/**
2176 * Checks if the CPU supports the FXSAVE and FXRSTOR instruction.
2177 * @returns true if supported.
2178 * @returns false if not supported.
2179 * @param pVM The VM handle.
2180 */
2181VMMDECL(bool) CPUMSupportsFXSR(PVM pVM)
2182{
2183 return pVM->cpum.s.CPUFeatures.edx.u1FXSR != 0;
2184}
2185
2186
2187/**
2188 * Checks if the host OS uses the SYSENTER / SYSEXIT instructions.
2189 * @returns true if used.
2190 * @returns false if not used.
2191 * @param pVM The VM handle.
2192 */
2193VMMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM)
2194{
2195 return (pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSENTER) != 0;
2196}
2197
2198
2199/**
2200 * Checks if the host OS uses the SYSCALL / SYSRET instructions.
2201 * @returns true if used.
2202 * @returns false if not used.
2203 * @param pVM The VM handle.
2204 */
2205VMMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM)
2206{
2207 return (pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSCALL) != 0;
2208}
2209
2210#ifndef IN_RING3
2211
2212/**
2213 * Lazily sync in the FPU/XMM state
2214 *
2215 * @returns VBox status code.
2216 * @param pVCpu VMCPU handle
2217 */
2218VMMDECL(int) CPUMHandleLazyFPU(PVMCPU pVCpu)
2219{
2220 return cpumHandleLazyFPUAsm(&pVCpu->cpum.s);
2221}
2222
2223#endif /* !IN_RING3 */
2224
2225/**
2226 * Checks if we activated the FPU/XMM state of the guest OS
2227 * @returns true if we did.
2228 * @returns false if not.
2229 * @param pVCpu The VMCPU handle.
2230 */
2231VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCpu)
2232{
2233 return (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU) != 0;
2234}
2235
2236
2237/**
2238 * Deactivate the FPU/XMM state of the guest OS
2239 * @param pVCpu The VMCPU handle.
2240 */
2241VMMDECL(void) CPUMDeactivateGuestFPUState(PVMCPU pVCpu)
2242{
2243 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU;
2244}
2245
2246
2247/**
2248 * Checks if the guest debug state is active
2249 *
2250 * @returns boolean
2251 * @param pVM VM handle.
2252 */
2253VMMDECL(bool) CPUMIsGuestDebugStateActive(PVMCPU pVCpu)
2254{
2255 return (pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS) != 0;
2256}
2257
2258/**
2259 * Checks if the hyper debug state is active
2260 *
2261 * @returns boolean
2262 * @param pVM VM handle.
2263 */
2264VMMDECL(bool) CPUMIsHyperDebugStateActive(PVMCPU pVCpu)
2265{
2266 return (pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS_HYPER) != 0;
2267}
2268
2269
2270/**
2271 * Mark the guest's debug state as inactive.
2272 *
2273 * @returns boolean
2274 * @param pVM VM handle.
2275 */
2276VMMDECL(void) CPUMDeactivateGuestDebugState(PVMCPU pVCpu)
2277{
2278 pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS;
2279}
2280
2281
2282/**
2283 * Mark the hypervisor's debug state as inactive.
2284 *
2285 * @returns boolean
2286 * @param pVM VM handle.
2287 */
2288VMMDECL(void) CPUMDeactivateHyperDebugState(PVMCPU pVCpu)
2289{
2290 pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS_HYPER;
2291}
2292
2293/**
2294 * Checks if the hidden selector registers are valid for the specified CPU.
2295 *
2296 * @returns true if they are.
2297 * @returns false if not.
2298 * @param pVCpu The VM handle.
2299 */
2300VMMDECL(bool) CPUMAreHiddenSelRegsValid(PVMCPU pVCpu)
2301{
2302 bool const fRc = !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID);
2303 Assert(fRc || !HWACCMIsEnabled(pVCpu->CTX_SUFF(pVM)));
2304 Assert(!pVCpu->cpum.s.fRemEntered);
2305 return fRc;
2306}
2307
2308
2309
2310/**
2311 * Get the current privilege level of the guest.
2312 *
2313 * @returns cpl
2314 * @param pVM VM Handle.
2315 * @param pRegFrame Trap register frame.
2316 */
2317VMMDECL(uint32_t) CPUMGetGuestCPL(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
2318{
2319 uint32_t cpl;
2320
2321 if (CPUMAreHiddenSelRegsValid(pVCpu))
2322 {
2323 /*
2324 * The hidden CS.DPL register is always equal to the CPL, it is
2325 * not affected by loading a conforming coding segment.
2326 *
2327 * This only seems to apply to AMD-V; in the VT-x case we *do* need to look
2328 * at SS. (ACP2 regression during install after a far call to ring 2)
2329 */
2330 if (RT_LIKELY(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
2331 {
2332 if (!pCtxCore->eflags.Bits.u1VM)
2333 cpl = pCtxCore->ssHid.Attr.n.u2Dpl;
2334 else
2335 cpl = 3; /* REM doesn't set DPL=3 in V8086 mode. See #5130. */
2336 }
2337 else
2338 cpl = 0; /* CPL set to 3 for VT-x real-mode emulation. */
2339 }
2340 else if (RT_LIKELY(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
2341 {
2342 if (RT_LIKELY(!pCtxCore->eflags.Bits.u1VM))
2343 {
2344 /*
2345 * The SS RPL is always equal to the CPL, while the CS RPL
2346 * isn't necessarily equal if the segment is conforming.
2347 * See section 4.11.1 in the AMD manual.
2348 */
2349 cpl = (pCtxCore->ss & X86_SEL_RPL);
2350#ifndef IN_RING0
2351 if (cpl == 1)
2352 cpl = 0;
2353#endif
2354 }
2355 else
2356 cpl = 3;
2357 }
2358 else
2359 cpl = 0; /* real mode; cpl is zero */
2360
2361 return cpl;
2362}
2363
2364
2365/**
2366 * Gets the current guest CPU mode.
2367 *
2368 * If paging mode is what you need, check out PGMGetGuestMode().
2369 *
2370 * @returns The CPU mode.
2371 * @param pVCpu The VMCPU handle.
2372 */
2373VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu)
2374{
2375 CPUMMODE enmMode;
2376 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
2377 enmMode = CPUMMODE_REAL;
2378 else if (!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
2379 enmMode = CPUMMODE_PROTECTED;
2380 else
2381 enmMode = CPUMMODE_LONG;
2382
2383 return enmMode;
2384}
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