VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp@ 42536

Last change on this file since 42536 was 42452, checked in by vboxsync, 12 years ago

CPUMAllRegs.cpp: Documented some return values on a few CPUMSetGuest* methods.

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1/* $Id: CPUMAllRegs.cpp 42452 2012-07-30 15:16:36Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor(/Manager) - Getters and Setters.
4 */
5
6/*
7 * Copyright (C) 2006-2012 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_CPUM
23#include <VBox/vmm/cpum.h>
24#include <VBox/vmm/patm.h>
25#include <VBox/vmm/dbgf.h>
26#include <VBox/vmm/pdm.h>
27#include <VBox/vmm/pgm.h>
28#include <VBox/vmm/mm.h>
29#if defined(VBOX_WITH_RAW_MODE) && !defined(IN_RING0)
30# include <VBox/vmm/selm.h>
31#endif
32#include "CPUMInternal.h"
33#include <VBox/vmm/vm.h>
34#include <VBox/err.h>
35#include <VBox/dis.h>
36#include <VBox/log.h>
37#include <VBox/vmm/hwaccm.h>
38#include <VBox/vmm/tm.h>
39#include <iprt/assert.h>
40#include <iprt/asm.h>
41#include <iprt/asm-amd64-x86.h>
42#ifdef IN_RING3
43#include <iprt/thread.h>
44#endif
45
46/** Disable stack frame pointer generation here. */
47#if defined(_MSC_VER) && !defined(DEBUG)
48# pragma optimize("y", off)
49#endif
50
51
52/*******************************************************************************
53* Defined Constants And Macros *
54*******************************************************************************/
55/**
56 * Converts a CPUMCPU::Guest pointer into a VMCPU pointer.
57 *
58 * @returns Pointer to the Virtual CPU.
59 * @param a_pGuestCtx Pointer to the guest context.
60 */
61#define CPUM_GUEST_CTX_TO_VMCPU(a_pGuestCtx) RT_FROM_MEMBER(a_pGuestCtx, VMCPU, cpum.s.Guest)
62
63/**
64 * Lazily loads the hidden parts of a selector register when using raw-mode.
65 */
66#if defined(VBOX_WITH_RAW_MODE) && !defined(IN_RING0)
67# define CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(a_pVCpu, a_pSReg) \
68 do \
69 { \
70 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(a_pVCpu, a_pSReg)) \
71 cpumGuestLazyLoadHiddenSelectorReg(a_pVCpu, a_pSReg); \
72 } while (0)
73#else
74# define CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(a_pVCpu, a_pSReg) \
75 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(a_pVCpu, a_pSReg));
76#endif
77
78
79
80#ifdef VBOX_WITH_RAW_MODE_NOT_R0
81
82/**
83 * Does the lazy hidden selector register loading.
84 *
85 * @param pVCpu The current Virtual CPU.
86 * @param pSReg The selector register to lazily load hidden parts of.
87 */
88static void cpumGuestLazyLoadHiddenSelectorReg(PVMCPU pVCpu, PCPUMSELREG pSReg)
89{
90 Assert(!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSReg));
91 Assert(!HWACCMIsEnabled(pVCpu->CTX_SUFF(pVM)));
92 Assert((uintptr_t)(pSReg - &pVCpu->cpum.s.Guest.es) < X86_SREG_COUNT);
93
94 if (pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
95 {
96 /* V8086 mode - Tightly controlled environment, no question about the limit or flags. */
97 pSReg->Attr.u = 0;
98 pSReg->Attr.n.u4Type = pSReg == &pVCpu->cpum.s.Guest.cs ? X86_SEL_TYPE_ER_ACC : X86_SEL_TYPE_RW_ACC;
99 pSReg->Attr.n.u1DescType = 1; /* code/data segment */
100 pSReg->Attr.n.u2Dpl = 3;
101 pSReg->Attr.n.u1Present = 1;
102 pSReg->u32Limit = 0x0000ffff;
103 pSReg->u64Base = (uint32_t)pSReg->Sel << 4;
104 pSReg->ValidSel = pSReg->Sel;
105 pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
106 /** @todo Check what the accessed bit should be (VT-x and AMD-V). */
107 }
108 else if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
109 {
110 /* Real mode - leave the limit and flags alone here, at least for now. */
111 pSReg->u64Base = (uint32_t)pSReg->Sel << 4;
112 pSReg->ValidSel = pSReg->Sel;
113 pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
114 }
115 else
116 {
117 /* Protected mode - get it from the selector descriptor tables. */
118 if (!(pSReg->Sel & X86_SEL_MASK_OFF_RPL))
119 {
120 Assert(!CPUMIsGuestInLongMode(pVCpu));
121 pSReg->Sel = 0;
122 pSReg->u64Base = 0;
123 pSReg->u32Limit = 0;
124 pSReg->Attr.u = 0;
125 pSReg->ValidSel = 0;
126 pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
127 /** @todo see todo in iemHlpLoadNullDataSelectorProt. */
128 }
129 else
130 SELMLoadHiddenSelectorReg(pVCpu, &pVCpu->cpum.s.Guest, pSReg);
131 }
132}
133
134
135/**
136 * Makes sure the hidden CS and SS selector registers are valid, loading them if
137 * necessary.
138 *
139 * @param pVCpu The current virtual CPU.
140 */
141VMM_INT_DECL(void) CPUMGuestLazyLoadHiddenCsAndSs(PVMCPU pVCpu)
142{
143 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
144 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.ss);
145}
146
147
148/**
149 * Loads a the hidden parts of a selector register.
150 *
151 * @param pVCpu The current virtual CPU.
152 */
153VMM_INT_DECL(void) CPUMGuestLazyLoadHiddenSelectorReg(PVMCPU pVCpu, PCPUMSELREG pSReg)
154{
155 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, pSReg);
156}
157
158#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
159
160
161/**
162 * Obsolete.
163 *
164 * We don't support nested hypervisor context interrupts or traps. Life is much
165 * simpler when we don't. It's also slightly faster at times.
166 *
167 * @param pVM Handle to the virtual machine.
168 */
169VMMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVMCPU pVCpu)
170{
171 return CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
172}
173
174
175/**
176 * Gets the pointer to the hypervisor CPU context structure of a virtual CPU.
177 *
178 * @param pVCpu Pointer to the VMCPU.
179 */
180VMMDECL(PCPUMCTX) CPUMGetHyperCtxPtr(PVMCPU pVCpu)
181{
182 return &pVCpu->cpum.s.Hyper;
183}
184
185
186VMMDECL(void) CPUMSetHyperGDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
187{
188 pVCpu->cpum.s.Hyper.gdtr.cbGdt = limit;
189 pVCpu->cpum.s.Hyper.gdtr.pGdt = addr;
190}
191
192
193VMMDECL(void) CPUMSetHyperIDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
194{
195 pVCpu->cpum.s.Hyper.idtr.cbIdt = limit;
196 pVCpu->cpum.s.Hyper.idtr.pIdt = addr;
197}
198
199
200VMMDECL(void) CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3)
201{
202 pVCpu->cpum.s.Hyper.cr3 = cr3;
203
204#ifdef IN_RC
205 /* Update the current CR3. */
206 ASMSetCR3(cr3);
207#endif
208}
209
210VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu)
211{
212 return pVCpu->cpum.s.Hyper.cr3;
213}
214
215
216VMMDECL(void) CPUMSetHyperCS(PVMCPU pVCpu, RTSEL SelCS)
217{
218 pVCpu->cpum.s.Hyper.cs.Sel = SelCS;
219}
220
221
222VMMDECL(void) CPUMSetHyperDS(PVMCPU pVCpu, RTSEL SelDS)
223{
224 pVCpu->cpum.s.Hyper.ds.Sel = SelDS;
225}
226
227
228VMMDECL(void) CPUMSetHyperES(PVMCPU pVCpu, RTSEL SelES)
229{
230 pVCpu->cpum.s.Hyper.es.Sel = SelES;
231}
232
233
234VMMDECL(void) CPUMSetHyperFS(PVMCPU pVCpu, RTSEL SelFS)
235{
236 pVCpu->cpum.s.Hyper.fs.Sel = SelFS;
237}
238
239
240VMMDECL(void) CPUMSetHyperGS(PVMCPU pVCpu, RTSEL SelGS)
241{
242 pVCpu->cpum.s.Hyper.gs.Sel = SelGS;
243}
244
245
246VMMDECL(void) CPUMSetHyperSS(PVMCPU pVCpu, RTSEL SelSS)
247{
248 pVCpu->cpum.s.Hyper.ss.Sel = SelSS;
249}
250
251
252VMMDECL(void) CPUMSetHyperESP(PVMCPU pVCpu, uint32_t u32ESP)
253{
254 pVCpu->cpum.s.Hyper.esp = u32ESP;
255}
256
257
258VMMDECL(void) CPUMSetHyperEDX(PVMCPU pVCpu, uint32_t u32ESP)
259{
260 pVCpu->cpum.s.Hyper.esp = u32ESP;
261}
262
263
264VMMDECL(int) CPUMSetHyperEFlags(PVMCPU pVCpu, uint32_t Efl)
265{
266 pVCpu->cpum.s.Hyper.eflags.u32 = Efl;
267 return VINF_SUCCESS;
268}
269
270
271VMMDECL(void) CPUMSetHyperEIP(PVMCPU pVCpu, uint32_t u32EIP)
272{
273 pVCpu->cpum.s.Hyper.eip = u32EIP;
274}
275
276
277/**
278 * Used by VMMR3RawRunGC to reinitialize the general raw-mode context registers,
279 * EFLAGS and EIP prior to resuming guest execution.
280 *
281 * All general register not given as a parameter will be set to 0. The EFLAGS
282 * register will be set to sane values for C/C++ code execution with interrupts
283 * disabled and IOPL 0.
284 *
285 * @param pVCpu The current virtual CPU.
286 * @param u32EIP The EIP value.
287 * @param u32ESP The ESP value.
288 * @param u32EAX The EAX value.
289 * @param u32EDX The EDX value.
290 */
291VMM_INT_DECL(void) CPUMSetHyperState(PVMCPU pVCpu, uint32_t u32EIP, uint32_t u32ESP, uint32_t u32EAX, uint32_t u32EDX)
292{
293 pVCpu->cpum.s.Hyper.eip = u32EIP;
294 pVCpu->cpum.s.Hyper.esp = u32ESP;
295 pVCpu->cpum.s.Hyper.eax = u32EAX;
296 pVCpu->cpum.s.Hyper.edx = u32EDX;
297 pVCpu->cpum.s.Hyper.ecx = 0;
298 pVCpu->cpum.s.Hyper.ebx = 0;
299 pVCpu->cpum.s.Hyper.ebp = 0;
300 pVCpu->cpum.s.Hyper.esi = 0;
301 pVCpu->cpum.s.Hyper.edi = 0;
302 pVCpu->cpum.s.Hyper.eflags.u = X86_EFL_1;
303}
304
305
306VMMDECL(void) CPUMSetHyperTR(PVMCPU pVCpu, RTSEL SelTR)
307{
308 pVCpu->cpum.s.Hyper.tr.Sel = SelTR;
309}
310
311
312VMMDECL(void) CPUMSetHyperLDTR(PVMCPU pVCpu, RTSEL SelLDTR)
313{
314 pVCpu->cpum.s.Hyper.ldtr.Sel = SelLDTR;
315}
316
317
318VMMDECL(void) CPUMSetHyperDR0(PVMCPU pVCpu, RTGCUINTREG uDr0)
319{
320 pVCpu->cpum.s.Hyper.dr[0] = uDr0;
321 /** @todo in GC we must load it! */
322}
323
324
325VMMDECL(void) CPUMSetHyperDR1(PVMCPU pVCpu, RTGCUINTREG uDr1)
326{
327 pVCpu->cpum.s.Hyper.dr[1] = uDr1;
328 /** @todo in GC we must load it! */
329}
330
331
332VMMDECL(void) CPUMSetHyperDR2(PVMCPU pVCpu, RTGCUINTREG uDr2)
333{
334 pVCpu->cpum.s.Hyper.dr[2] = uDr2;
335 /** @todo in GC we must load it! */
336}
337
338
339VMMDECL(void) CPUMSetHyperDR3(PVMCPU pVCpu, RTGCUINTREG uDr3)
340{
341 pVCpu->cpum.s.Hyper.dr[3] = uDr3;
342 /** @todo in GC we must load it! */
343}
344
345
346VMMDECL(void) CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6)
347{
348 pVCpu->cpum.s.Hyper.dr[6] = uDr6;
349 /** @todo in GC we must load it! */
350}
351
352
353VMMDECL(void) CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7)
354{
355 pVCpu->cpum.s.Hyper.dr[7] = uDr7;
356 /** @todo in GC we must load it! */
357}
358
359
360VMMDECL(RTSEL) CPUMGetHyperCS(PVMCPU pVCpu)
361{
362 return pVCpu->cpum.s.Hyper.cs.Sel;
363}
364
365
366VMMDECL(RTSEL) CPUMGetHyperDS(PVMCPU pVCpu)
367{
368 return pVCpu->cpum.s.Hyper.ds.Sel;
369}
370
371
372VMMDECL(RTSEL) CPUMGetHyperES(PVMCPU pVCpu)
373{
374 return pVCpu->cpum.s.Hyper.es.Sel;
375}
376
377
378VMMDECL(RTSEL) CPUMGetHyperFS(PVMCPU pVCpu)
379{
380 return pVCpu->cpum.s.Hyper.fs.Sel;
381}
382
383
384VMMDECL(RTSEL) CPUMGetHyperGS(PVMCPU pVCpu)
385{
386 return pVCpu->cpum.s.Hyper.gs.Sel;
387}
388
389
390VMMDECL(RTSEL) CPUMGetHyperSS(PVMCPU pVCpu)
391{
392 return pVCpu->cpum.s.Hyper.ss.Sel;
393}
394
395
396VMMDECL(uint32_t) CPUMGetHyperEAX(PVMCPU pVCpu)
397{
398 return pVCpu->cpum.s.Hyper.eax;
399}
400
401
402VMMDECL(uint32_t) CPUMGetHyperEBX(PVMCPU pVCpu)
403{
404 return pVCpu->cpum.s.Hyper.ebx;
405}
406
407
408VMMDECL(uint32_t) CPUMGetHyperECX(PVMCPU pVCpu)
409{
410 return pVCpu->cpum.s.Hyper.ecx;
411}
412
413
414VMMDECL(uint32_t) CPUMGetHyperEDX(PVMCPU pVCpu)
415{
416 return pVCpu->cpum.s.Hyper.edx;
417}
418
419
420VMMDECL(uint32_t) CPUMGetHyperESI(PVMCPU pVCpu)
421{
422 return pVCpu->cpum.s.Hyper.esi;
423}
424
425
426VMMDECL(uint32_t) CPUMGetHyperEDI(PVMCPU pVCpu)
427{
428 return pVCpu->cpum.s.Hyper.edi;
429}
430
431
432VMMDECL(uint32_t) CPUMGetHyperEBP(PVMCPU pVCpu)
433{
434 return pVCpu->cpum.s.Hyper.ebp;
435}
436
437
438VMMDECL(uint32_t) CPUMGetHyperESP(PVMCPU pVCpu)
439{
440 return pVCpu->cpum.s.Hyper.esp;
441}
442
443
444VMMDECL(uint32_t) CPUMGetHyperEFlags(PVMCPU pVCpu)
445{
446 return pVCpu->cpum.s.Hyper.eflags.u32;
447}
448
449
450VMMDECL(uint32_t) CPUMGetHyperEIP(PVMCPU pVCpu)
451{
452 return pVCpu->cpum.s.Hyper.eip;
453}
454
455
456VMMDECL(uint64_t) CPUMGetHyperRIP(PVMCPU pVCpu)
457{
458 return pVCpu->cpum.s.Hyper.rip;
459}
460
461
462VMMDECL(uint32_t) CPUMGetHyperIDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
463{
464 if (pcbLimit)
465 *pcbLimit = pVCpu->cpum.s.Hyper.idtr.cbIdt;
466 return pVCpu->cpum.s.Hyper.idtr.pIdt;
467}
468
469
470VMMDECL(uint32_t) CPUMGetHyperGDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
471{
472 if (pcbLimit)
473 *pcbLimit = pVCpu->cpum.s.Hyper.gdtr.cbGdt;
474 return pVCpu->cpum.s.Hyper.gdtr.pGdt;
475}
476
477
478VMMDECL(RTSEL) CPUMGetHyperLDTR(PVMCPU pVCpu)
479{
480 return pVCpu->cpum.s.Hyper.ldtr.Sel;
481}
482
483
484VMMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVMCPU pVCpu)
485{
486 return pVCpu->cpum.s.Hyper.dr[0];
487}
488
489
490VMMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVMCPU pVCpu)
491{
492 return pVCpu->cpum.s.Hyper.dr[1];
493}
494
495
496VMMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVMCPU pVCpu)
497{
498 return pVCpu->cpum.s.Hyper.dr[2];
499}
500
501
502VMMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVMCPU pVCpu)
503{
504 return pVCpu->cpum.s.Hyper.dr[3];
505}
506
507
508VMMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVMCPU pVCpu)
509{
510 return pVCpu->cpum.s.Hyper.dr[6];
511}
512
513
514VMMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVMCPU pVCpu)
515{
516 return pVCpu->cpum.s.Hyper.dr[7];
517}
518
519
520/**
521 * Gets the pointer to the internal CPUMCTXCORE structure.
522 * This is only for reading in order to save a few calls.
523 *
524 * @param pVCpu Handle to the virtual cpu.
525 */
526VMMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVMCPU pVCpu)
527{
528 return CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
529}
530
531
532/**
533 * Queries the pointer to the internal CPUMCTX structure.
534 *
535 * @returns The CPUMCTX pointer.
536 * @param pVCpu Handle to the virtual cpu.
537 */
538VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu)
539{
540 return &pVCpu->cpum.s.Guest;
541}
542
543VMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit)
544{
545 pVCpu->cpum.s.Guest.gdtr.cbGdt = cbLimit;
546 pVCpu->cpum.s.Guest.gdtr.pGdt = GCPtrBase;
547 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GDTR;
548 return VINF_SUCCESS; /* formality, consider it void. */
549}
550
551VMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit)
552{
553 pVCpu->cpum.s.Guest.idtr.cbIdt = cbLimit;
554 pVCpu->cpum.s.Guest.idtr.pIdt = GCPtrBase;
555 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_IDTR;
556 return VINF_SUCCESS; /* formality, consider it void. */
557}
558
559VMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr)
560{
561 pVCpu->cpum.s.Guest.tr.Sel = tr;
562 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_TR;
563 return VINF_SUCCESS; /* formality, consider it void. */
564}
565
566VMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr)
567{
568 pVCpu->cpum.s.Guest.ldtr.Sel = ldtr;
569 /* The caller will set more hidden bits if it has them. */
570 pVCpu->cpum.s.Guest.ldtr.ValidSel = 0;
571 pVCpu->cpum.s.Guest.ldtr.fFlags = 0;
572 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_LDTR;
573 return VINF_SUCCESS; /* formality, consider it void. */
574}
575
576
577/**
578 * Set the guest CR0.
579 *
580 * When called in GC, the hyper CR0 may be updated if that is
581 * required. The caller only has to take special action if AM,
582 * WP, PG or PE changes.
583 *
584 * @returns VINF_SUCCESS (consider it void).
585 * @param pVCpu Handle to the virtual cpu.
586 * @param cr0 The new CR0 value.
587 */
588VMMDECL(int) CPUMSetGuestCR0(PVMCPU pVCpu, uint64_t cr0)
589{
590#ifdef IN_RC
591 /*
592 * Check if we need to change hypervisor CR0 because
593 * of math stuff.
594 */
595 if ( (cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP))
596 != (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP)))
597 {
598 if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU))
599 {
600 /*
601 * We haven't saved the host FPU state yet, so TS and MT are both set
602 * and EM should be reflecting the guest EM (it always does this).
603 */
604 if ((cr0 & X86_CR0_EM) != (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM))
605 {
606 uint32_t HyperCR0 = ASMGetCR0();
607 AssertMsg((HyperCR0 & (X86_CR0_TS | X86_CR0_MP)) == (X86_CR0_TS | X86_CR0_MP), ("%#x\n", HyperCR0));
608 AssertMsg((HyperCR0 & X86_CR0_EM) == (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM), ("%#x\n", HyperCR0));
609 HyperCR0 &= ~X86_CR0_EM;
610 HyperCR0 |= cr0 & X86_CR0_EM;
611 Log(("CPUM New HyperCR0=%#x\n", HyperCR0));
612 ASMSetCR0(HyperCR0);
613 }
614# ifdef VBOX_STRICT
615 else
616 {
617 uint32_t HyperCR0 = ASMGetCR0();
618 AssertMsg((HyperCR0 & (X86_CR0_TS | X86_CR0_MP)) == (X86_CR0_TS | X86_CR0_MP), ("%#x\n", HyperCR0));
619 AssertMsg((HyperCR0 & X86_CR0_EM) == (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM), ("%#x\n", HyperCR0));
620 }
621# endif
622 }
623 else
624 {
625 /*
626 * Already saved the state, so we're just mirroring
627 * the guest flags.
628 */
629 uint32_t HyperCR0 = ASMGetCR0();
630 AssertMsg( (HyperCR0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP))
631 == (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP)),
632 ("%#x %#x\n", HyperCR0, pVCpu->cpum.s.Guest.cr0));
633 HyperCR0 &= ~(X86_CR0_TS | X86_CR0_EM | X86_CR0_MP);
634 HyperCR0 |= cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP);
635 Log(("CPUM New HyperCR0=%#x\n", HyperCR0));
636 ASMSetCR0(HyperCR0);
637 }
638 }
639#endif /* IN_RC */
640
641 /*
642 * Check for changes causing TLB flushes (for REM).
643 * The caller is responsible for calling PGM when appropriate.
644 */
645 if ( (cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE))
646 != (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)))
647 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
648 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR0;
649
650 pVCpu->cpum.s.Guest.cr0 = cr0 | X86_CR0_ET;
651 return VINF_SUCCESS;
652}
653
654
655VMMDECL(int) CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2)
656{
657 pVCpu->cpum.s.Guest.cr2 = cr2;
658 return VINF_SUCCESS;
659}
660
661
662VMMDECL(int) CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3)
663{
664 pVCpu->cpum.s.Guest.cr3 = cr3;
665 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR3;
666 return VINF_SUCCESS;
667}
668
669
670VMMDECL(int) CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4)
671{
672 if ( (cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE))
673 != (pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE)))
674 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
675 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR4;
676 if (!CPUMSupportsFXSR(pVCpu->CTX_SUFF(pVM)))
677 cr4 &= ~X86_CR4_OSFSXR;
678 pVCpu->cpum.s.Guest.cr4 = cr4;
679 return VINF_SUCCESS;
680}
681
682
683VMMDECL(int) CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags)
684{
685 pVCpu->cpum.s.Guest.eflags.u32 = eflags;
686 return VINF_SUCCESS;
687}
688
689
690VMMDECL(int) CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip)
691{
692 pVCpu->cpum.s.Guest.eip = eip;
693 return VINF_SUCCESS;
694}
695
696
697VMMDECL(int) CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax)
698{
699 pVCpu->cpum.s.Guest.eax = eax;
700 return VINF_SUCCESS;
701}
702
703
704VMMDECL(int) CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx)
705{
706 pVCpu->cpum.s.Guest.ebx = ebx;
707 return VINF_SUCCESS;
708}
709
710
711VMMDECL(int) CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx)
712{
713 pVCpu->cpum.s.Guest.ecx = ecx;
714 return VINF_SUCCESS;
715}
716
717
718VMMDECL(int) CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx)
719{
720 pVCpu->cpum.s.Guest.edx = edx;
721 return VINF_SUCCESS;
722}
723
724
725VMMDECL(int) CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp)
726{
727 pVCpu->cpum.s.Guest.esp = esp;
728 return VINF_SUCCESS;
729}
730
731
732VMMDECL(int) CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp)
733{
734 pVCpu->cpum.s.Guest.ebp = ebp;
735 return VINF_SUCCESS;
736}
737
738
739VMMDECL(int) CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi)
740{
741 pVCpu->cpum.s.Guest.esi = esi;
742 return VINF_SUCCESS;
743}
744
745
746VMMDECL(int) CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi)
747{
748 pVCpu->cpum.s.Guest.edi = edi;
749 return VINF_SUCCESS;
750}
751
752
753VMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss)
754{
755 pVCpu->cpum.s.Guest.ss.Sel = ss;
756 return VINF_SUCCESS;
757}
758
759
760VMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs)
761{
762 pVCpu->cpum.s.Guest.cs.Sel = cs;
763 return VINF_SUCCESS;
764}
765
766
767VMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds)
768{
769 pVCpu->cpum.s.Guest.ds.Sel = ds;
770 return VINF_SUCCESS;
771}
772
773
774VMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es)
775{
776 pVCpu->cpum.s.Guest.es.Sel = es;
777 return VINF_SUCCESS;
778}
779
780
781VMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs)
782{
783 pVCpu->cpum.s.Guest.fs.Sel = fs;
784 return VINF_SUCCESS;
785}
786
787
788VMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs)
789{
790 pVCpu->cpum.s.Guest.gs.Sel = gs;
791 return VINF_SUCCESS;
792}
793
794
795VMMDECL(void) CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val)
796{
797 pVCpu->cpum.s.Guest.msrEFER = val;
798}
799
800
801/**
802 * Query an MSR.
803 *
804 * The caller is responsible for checking privilege if the call is the result
805 * of a RDMSR instruction. We'll do the rest.
806 *
807 * @retval VINF_SUCCESS on success.
808 * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR), the caller is
809 * expected to take the appropriate actions. @a *puValue is set to 0.
810 * @param pVCpu Pointer to the VMCPU.
811 * @param idMsr The MSR.
812 * @param puValue Where to return the value.
813 *
814 * @remarks This will always return the right values, even when we're in the
815 * recompiler.
816 */
817VMMDECL(int) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue)
818{
819 /*
820 * If we don't indicate MSR support in the CPUID feature bits, indicate
821 * that a #GP(0) should be raised.
822 */
823 if (!(pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_MSR))
824 {
825 *puValue = 0;
826 return VERR_CPUM_RAISE_GP_0; /** @todo isn't \#UD more correct if not supported? */
827 }
828
829 int rc = VINF_SUCCESS;
830 uint8_t const u8Multiplier = 4;
831 switch (idMsr)
832 {
833 case MSR_IA32_TSC:
834 *puValue = TMCpuTickGet(pVCpu);
835 break;
836
837 case MSR_IA32_APICBASE:
838 rc = PDMApicGetBase(pVCpu->CTX_SUFF(pVM), puValue);
839 if (RT_SUCCESS(rc))
840 rc = VINF_SUCCESS;
841 else
842 {
843 *puValue = 0;
844 rc = VERR_CPUM_RAISE_GP_0;
845 }
846 break;
847
848 case MSR_IA32_CR_PAT:
849 *puValue = pVCpu->cpum.s.Guest.msrPAT;
850 break;
851
852 case MSR_IA32_SYSENTER_CS:
853 *puValue = pVCpu->cpum.s.Guest.SysEnter.cs;
854 break;
855
856 case MSR_IA32_SYSENTER_EIP:
857 *puValue = pVCpu->cpum.s.Guest.SysEnter.eip;
858 break;
859
860 case MSR_IA32_SYSENTER_ESP:
861 *puValue = pVCpu->cpum.s.Guest.SysEnter.esp;
862 break;
863
864 case MSR_IA32_MTRR_CAP:
865 {
866 /* This is currently a bit weird. :-) */
867 uint8_t const cVariableRangeRegs = 0;
868 bool const fSystemManagementRangeRegisters = false;
869 bool const fFixedRangeRegisters = false;
870 bool const fWriteCombiningType = false;
871 *puValue = cVariableRangeRegs
872 | (fFixedRangeRegisters ? RT_BIT_64(8) : 0)
873 | (fWriteCombiningType ? RT_BIT_64(10) : 0)
874 | (fSystemManagementRangeRegisters ? RT_BIT_64(11) : 0);
875 break;
876 }
877
878 case MSR_IA32_MTRR_DEF_TYPE:
879 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType;
880 break;
881
882 case IA32_MTRR_FIX64K_00000:
883 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix64K_00000;
884 break;
885 case IA32_MTRR_FIX16K_80000:
886 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_80000;
887 break;
888 case IA32_MTRR_FIX16K_A0000:
889 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_A0000;
890 break;
891 case IA32_MTRR_FIX4K_C0000:
892 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C0000;
893 break;
894 case IA32_MTRR_FIX4K_C8000:
895 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C8000;
896 break;
897 case IA32_MTRR_FIX4K_D0000:
898 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D0000;
899 break;
900 case IA32_MTRR_FIX4K_D8000:
901 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D8000;
902 break;
903 case IA32_MTRR_FIX4K_E0000:
904 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E0000;
905 break;
906 case IA32_MTRR_FIX4K_E8000:
907 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E8000;
908 break;
909 case IA32_MTRR_FIX4K_F0000:
910 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F0000;
911 break;
912 case IA32_MTRR_FIX4K_F8000:
913 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F8000;
914 break;
915
916 case MSR_K6_EFER:
917 *puValue = pVCpu->cpum.s.Guest.msrEFER;
918 break;
919
920 case MSR_K8_SF_MASK:
921 *puValue = pVCpu->cpum.s.Guest.msrSFMASK;
922 break;
923
924 case MSR_K6_STAR:
925 *puValue = pVCpu->cpum.s.Guest.msrSTAR;
926 break;
927
928 case MSR_K8_LSTAR:
929 *puValue = pVCpu->cpum.s.Guest.msrLSTAR;
930 break;
931
932 case MSR_K8_CSTAR:
933 *puValue = pVCpu->cpum.s.Guest.msrCSTAR;
934 break;
935
936 case MSR_K8_FS_BASE:
937 *puValue = pVCpu->cpum.s.Guest.fs.u64Base;
938 break;
939
940 case MSR_K8_GS_BASE:
941 *puValue = pVCpu->cpum.s.Guest.gs.u64Base;
942 break;
943
944 case MSR_K8_KERNEL_GS_BASE:
945 *puValue = pVCpu->cpum.s.Guest.msrKERNELGSBASE;
946 break;
947
948 case MSR_K8_TSC_AUX:
949 *puValue = pVCpu->cpum.s.GuestMsrs.msr.TscAux;
950 break;
951
952 case MSR_IA32_PERF_STATUS:
953 /** @todo could really be not exactly correct, maybe use host's values */
954 *puValue = UINT64_C(1000) /* TSC increment by tick */
955 | ((uint64_t)u8Multiplier << 24) /* CPU multiplier (aka bus ratio) min */
956 | ((uint64_t)u8Multiplier << 40) /* CPU multiplier (aka bus ratio) max */;
957 break;
958
959 case MSR_IA32_FSB_CLOCK_STS:
960 /*
961 * Encoded as:
962 * 0 - 266
963 * 1 - 133
964 * 2 - 200
965 * 3 - return 166
966 * 5 - return 100
967 */
968 *puValue = (2 << 4);
969 break;
970
971 case MSR_IA32_PLATFORM_INFO:
972 *puValue = (u8Multiplier << 8) /* Flex ratio max */
973 | ((uint64_t)u8Multiplier << 40) /* Flex ratio min */;
974 break;
975
976 case MSR_IA32_THERM_STATUS:
977 /* CPU temperature relative to TCC, to actually activate, CPUID leaf 6 EAX[0] must be set */
978 *puValue = RT_BIT(31) /* validity bit */
979 | (UINT64_C(20) << 16) /* degrees till TCC */;
980 break;
981
982 case MSR_IA32_MISC_ENABLE:
983#if 0
984 /* Needs to be tested more before enabling. */
985 *puValue = pVCpu->cpum.s.GuestMsr.msr.miscEnable;
986#else
987 /* Currenty we don't allow guests to modify enable MSRs. */
988 *puValue = MSR_IA32_MISC_ENABLE_FAST_STRINGS /* by default */;
989
990 if ((pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR) != 0)
991
992 *puValue |= MSR_IA32_MISC_ENABLE_MONITOR /* if mwait/monitor available */;
993 /** @todo: add more cpuid-controlled features this way. */
994#endif
995 break;
996
997#if 0 /*def IN_RING0 */
998 case MSR_IA32_PLATFORM_ID:
999 case MSR_IA32_BIOS_SIGN_ID:
1000 if (CPUMGetCPUVendor(pVM) == CPUMCPUVENDOR_INTEL)
1001 {
1002 /* Available since the P6 family. VT-x implies that this feature is present. */
1003 if (idMsr == MSR_IA32_PLATFORM_ID)
1004 *puValue = ASMRdMsr(MSR_IA32_PLATFORM_ID);
1005 else if (idMsr == MSR_IA32_BIOS_SIGN_ID)
1006 *puValue = ASMRdMsr(MSR_IA32_BIOS_SIGN_ID);
1007 break;
1008 }
1009 /* no break */
1010#endif
1011
1012 default:
1013 /* In X2APIC specification this range is reserved for APIC control. */
1014 if ( idMsr >= MSR_IA32_APIC_START
1015 && idMsr < MSR_IA32_APIC_END)
1016 {
1017 rc = PDMApicReadMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, puValue);
1018 if (RT_SUCCESS(rc))
1019 rc = VINF_SUCCESS;
1020 else
1021 {
1022 *puValue = 0;
1023 rc = VERR_CPUM_RAISE_GP_0;
1024 }
1025 }
1026 else
1027 {
1028 *puValue = 0;
1029 rc = VERR_CPUM_RAISE_GP_0;
1030 }
1031 break;
1032 }
1033
1034 return rc;
1035}
1036
1037
1038/**
1039 * Sets the MSR.
1040 *
1041 * The caller is responsible for checking privilege if the call is the result
1042 * of a WRMSR instruction. We'll do the rest.
1043 *
1044 * @retval VINF_SUCCESS on success.
1045 * @retval VERR_CPUM_RAISE_GP_0 on failure, the caller is expected to take the
1046 * appropriate actions.
1047 *
1048 * @param pVCpu Pointer to the VMCPU.
1049 * @param idMsr The MSR id.
1050 * @param uValue The value to set.
1051 *
1052 * @remarks Everyone changing MSR values, including the recompiler, shall do it
1053 * by calling this method. This makes sure we have current values and
1054 * that we trigger all the right actions when something changes.
1055 */
1056VMMDECL(int) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue)
1057{
1058 /*
1059 * If we don't indicate MSR support in the CPUID feature bits, indicate
1060 * that a #GP(0) should be raised.
1061 */
1062 if (!(pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_MSR))
1063 return VERR_CPUM_RAISE_GP_0; /** @todo isn't \#UD more correct if not supported? */
1064
1065 int rc = VINF_SUCCESS;
1066 switch (idMsr)
1067 {
1068 case MSR_IA32_MISC_ENABLE:
1069 pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = uValue;
1070 break;
1071
1072 case MSR_IA32_TSC:
1073 TMCpuTickSet(pVCpu->CTX_SUFF(pVM), pVCpu, uValue);
1074 break;
1075
1076 case MSR_IA32_APICBASE:
1077 rc = PDMApicSetBase(pVCpu->CTX_SUFF(pVM), uValue);
1078 if (rc != VINF_SUCCESS)
1079 rc = VERR_CPUM_RAISE_GP_0;
1080 break;
1081
1082 case MSR_IA32_CR_PAT:
1083 pVCpu->cpum.s.Guest.msrPAT = uValue;
1084 break;
1085
1086 case MSR_IA32_SYSENTER_CS:
1087 pVCpu->cpum.s.Guest.SysEnter.cs = uValue & 0xffff; /* 16 bits selector */
1088 break;
1089
1090 case MSR_IA32_SYSENTER_EIP:
1091 pVCpu->cpum.s.Guest.SysEnter.eip = uValue;
1092 break;
1093
1094 case MSR_IA32_SYSENTER_ESP:
1095 pVCpu->cpum.s.Guest.SysEnter.esp = uValue;
1096 break;
1097
1098 case MSR_IA32_MTRR_CAP:
1099 return VERR_CPUM_RAISE_GP_0;
1100
1101 case MSR_IA32_MTRR_DEF_TYPE:
1102 if ( (uValue & UINT64_C(0xfffffffffffff300))
1103 || ( (uValue & 0xff) != 0
1104 && (uValue & 0xff) != 1
1105 && (uValue & 0xff) != 4
1106 && (uValue & 0xff) != 5
1107 && (uValue & 0xff) != 6) )
1108 {
1109 Log(("MSR_IA32_MTRR_DEF_TYPE: #GP(0) - writing reserved value (%#llx)\n", uValue));
1110 return VERR_CPUM_RAISE_GP_0;
1111 }
1112 pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType = uValue;
1113 break;
1114
1115 case IA32_MTRR_FIX64K_00000:
1116 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix64K_00000 = uValue;
1117 break;
1118 case IA32_MTRR_FIX16K_80000:
1119 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_80000 = uValue;
1120 break;
1121 case IA32_MTRR_FIX16K_A0000:
1122 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_A0000 = uValue;
1123 break;
1124 case IA32_MTRR_FIX4K_C0000:
1125 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C0000 = uValue;
1126 break;
1127 case IA32_MTRR_FIX4K_C8000:
1128 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C8000 = uValue;
1129 break;
1130 case IA32_MTRR_FIX4K_D0000:
1131 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D0000 = uValue;
1132 break;
1133 case IA32_MTRR_FIX4K_D8000:
1134 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D8000 = uValue;
1135 break;
1136 case IA32_MTRR_FIX4K_E0000:
1137 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E0000 = uValue;
1138 break;
1139 case IA32_MTRR_FIX4K_E8000:
1140 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E8000 = uValue;
1141 break;
1142 case IA32_MTRR_FIX4K_F0000:
1143 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F0000 = uValue;
1144 break;
1145 case IA32_MTRR_FIX4K_F8000:
1146 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F8000 = uValue;
1147 break;
1148
1149 case MSR_K6_EFER:
1150 {
1151 PVM pVM = pVCpu->CTX_SUFF(pVM);
1152 uint64_t const uOldEFER = pVCpu->cpum.s.Guest.msrEFER;
1153 uint32_t const fExtFeatures = pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1154 ? pVM->cpum.s.aGuestCpuIdExt[1].edx
1155 : 0;
1156 uint64_t fMask = 0;
1157
1158 /* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
1159 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_NX)
1160 fMask |= MSR_K6_EFER_NXE;
1161 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
1162 fMask |= MSR_K6_EFER_LME;
1163 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
1164 fMask |= MSR_K6_EFER_SCE;
1165 if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1166 fMask |= MSR_K6_EFER_FFXSR;
1167
1168 /* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if
1169 paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1170 if ( (uOldEFER & MSR_K6_EFER_LME) != (uValue & fMask & MSR_K6_EFER_LME)
1171 && (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG))
1172 {
1173 Log(("Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
1174 return VERR_CPUM_RAISE_GP_0;
1175 }
1176
1177 /* There are a few more: e.g. MSR_K6_EFER_LMSLE */
1178 AssertMsg(!(uValue & ~(MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA /* ignored anyway */ | MSR_K6_EFER_SCE | MSR_K6_EFER_FFXSR)),
1179 ("Unexpected value %RX64\n", uValue));
1180 pVCpu->cpum.s.Guest.msrEFER = (uOldEFER & ~fMask) | (uValue & fMask);
1181
1182 /* AMD64 Architecture Programmer's Manual: 15.15 TLB Control; flush the TLB
1183 if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
1184 if ( (uOldEFER & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA))
1185 != (pVCpu->cpum.s.Guest.msrEFER & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA)))
1186 {
1187 /// @todo PGMFlushTLB(pVCpu, cr3, true /*fGlobal*/);
1188 HWACCMFlushTLB(pVCpu);
1189
1190 /* Notify PGM about NXE changes. */
1191 if ( (uOldEFER & MSR_K6_EFER_NXE)
1192 != (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE))
1193 PGMNotifyNxeChanged(pVCpu, !(uOldEFER & MSR_K6_EFER_NXE));
1194 }
1195 break;
1196 }
1197
1198 case MSR_K8_SF_MASK:
1199 pVCpu->cpum.s.Guest.msrSFMASK = uValue;
1200 break;
1201
1202 case MSR_K6_STAR:
1203 pVCpu->cpum.s.Guest.msrSTAR = uValue;
1204 break;
1205
1206 case MSR_K8_LSTAR:
1207 pVCpu->cpum.s.Guest.msrLSTAR = uValue;
1208 break;
1209
1210 case MSR_K8_CSTAR:
1211 pVCpu->cpum.s.Guest.msrCSTAR = uValue;
1212 break;
1213
1214 case MSR_K8_FS_BASE:
1215 pVCpu->cpum.s.Guest.fs.u64Base = uValue;
1216 break;
1217
1218 case MSR_K8_GS_BASE:
1219 pVCpu->cpum.s.Guest.gs.u64Base = uValue;
1220 break;
1221
1222 case MSR_K8_KERNEL_GS_BASE:
1223 pVCpu->cpum.s.Guest.msrKERNELGSBASE = uValue;
1224 break;
1225
1226 case MSR_K8_TSC_AUX:
1227 pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
1228 break;
1229
1230 default:
1231 /* In X2APIC specification this range is reserved for APIC control. */
1232 if ( idMsr >= MSR_IA32_APIC_START
1233 && idMsr < MSR_IA32_APIC_END)
1234 {
1235 rc = PDMApicWriteMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, uValue);
1236 if (rc != VINF_SUCCESS)
1237 rc = VERR_CPUM_RAISE_GP_0;
1238 }
1239 else
1240 {
1241 /* We should actually trigger a #GP here, but don't as that might cause more trouble. */
1242 /** @todo rc = VERR_CPUM_RAISE_GP_0 */
1243 Log(("CPUMSetGuestMsr: Unknown MSR %#x attempted set to %#llx\n", idMsr, uValue));
1244 }
1245 break;
1246 }
1247 return rc;
1248}
1249
1250
1251VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
1252{
1253 if (pcbLimit)
1254 *pcbLimit = pVCpu->cpum.s.Guest.idtr.cbIdt;
1255 return pVCpu->cpum.s.Guest.idtr.pIdt;
1256}
1257
1258
1259VMMDECL(RTSEL) CPUMGetGuestTR(PVMCPU pVCpu, PCPUMSELREGHID pHidden)
1260{
1261 if (pHidden)
1262 *pHidden = pVCpu->cpum.s.Guest.tr;
1263 return pVCpu->cpum.s.Guest.tr.Sel;
1264}
1265
1266
1267VMMDECL(RTSEL) CPUMGetGuestCS(PVMCPU pVCpu)
1268{
1269 return pVCpu->cpum.s.Guest.cs.Sel;
1270}
1271
1272
1273VMMDECL(RTSEL) CPUMGetGuestDS(PVMCPU pVCpu)
1274{
1275 return pVCpu->cpum.s.Guest.ds.Sel;
1276}
1277
1278
1279VMMDECL(RTSEL) CPUMGetGuestES(PVMCPU pVCpu)
1280{
1281 return pVCpu->cpum.s.Guest.es.Sel;
1282}
1283
1284
1285VMMDECL(RTSEL) CPUMGetGuestFS(PVMCPU pVCpu)
1286{
1287 return pVCpu->cpum.s.Guest.fs.Sel;
1288}
1289
1290
1291VMMDECL(RTSEL) CPUMGetGuestGS(PVMCPU pVCpu)
1292{
1293 return pVCpu->cpum.s.Guest.gs.Sel;
1294}
1295
1296
1297VMMDECL(RTSEL) CPUMGetGuestSS(PVMCPU pVCpu)
1298{
1299 return pVCpu->cpum.s.Guest.ss.Sel;
1300}
1301
1302
1303VMMDECL(RTSEL) CPUMGetGuestLDTR(PVMCPU pVCpu)
1304{
1305 return pVCpu->cpum.s.Guest.ldtr.Sel;
1306}
1307
1308
1309VMMDECL(RTSEL) CPUMGetGuestLdtrEx(PVMCPU pVCpu, uint64_t *pGCPtrBase, uint32_t *pcbLimit)
1310{
1311 *pGCPtrBase = pVCpu->cpum.s.Guest.ldtr.u64Base;
1312 *pcbLimit = pVCpu->cpum.s.Guest.ldtr.u32Limit;
1313 return pVCpu->cpum.s.Guest.ldtr.Sel;
1314}
1315
1316
1317VMMDECL(uint64_t) CPUMGetGuestCR0(PVMCPU pVCpu)
1318{
1319 return pVCpu->cpum.s.Guest.cr0;
1320}
1321
1322
1323VMMDECL(uint64_t) CPUMGetGuestCR2(PVMCPU pVCpu)
1324{
1325 return pVCpu->cpum.s.Guest.cr2;
1326}
1327
1328
1329VMMDECL(uint64_t) CPUMGetGuestCR3(PVMCPU pVCpu)
1330{
1331 return pVCpu->cpum.s.Guest.cr3;
1332}
1333
1334
1335VMMDECL(uint64_t) CPUMGetGuestCR4(PVMCPU pVCpu)
1336{
1337 return pVCpu->cpum.s.Guest.cr4;
1338}
1339
1340
1341VMMDECL(uint64_t) CPUMGetGuestCR8(PVMCPU pVCpu)
1342{
1343 uint64_t u64;
1344 int rc = CPUMGetGuestCRx(pVCpu, DISCREG_CR8, &u64);
1345 if (RT_FAILURE(rc))
1346 u64 = 0;
1347 return u64;
1348}
1349
1350
1351VMMDECL(void) CPUMGetGuestGDTR(PVMCPU pVCpu, PVBOXGDTR pGDTR)
1352{
1353 *pGDTR = pVCpu->cpum.s.Guest.gdtr;
1354}
1355
1356
1357VMMDECL(uint32_t) CPUMGetGuestEIP(PVMCPU pVCpu)
1358{
1359 return pVCpu->cpum.s.Guest.eip;
1360}
1361
1362
1363VMMDECL(uint64_t) CPUMGetGuestRIP(PVMCPU pVCpu)
1364{
1365 return pVCpu->cpum.s.Guest.rip;
1366}
1367
1368
1369VMMDECL(uint32_t) CPUMGetGuestEAX(PVMCPU pVCpu)
1370{
1371 return pVCpu->cpum.s.Guest.eax;
1372}
1373
1374
1375VMMDECL(uint32_t) CPUMGetGuestEBX(PVMCPU pVCpu)
1376{
1377 return pVCpu->cpum.s.Guest.ebx;
1378}
1379
1380
1381VMMDECL(uint32_t) CPUMGetGuestECX(PVMCPU pVCpu)
1382{
1383 return pVCpu->cpum.s.Guest.ecx;
1384}
1385
1386
1387VMMDECL(uint32_t) CPUMGetGuestEDX(PVMCPU pVCpu)
1388{
1389 return pVCpu->cpum.s.Guest.edx;
1390}
1391
1392
1393VMMDECL(uint32_t) CPUMGetGuestESI(PVMCPU pVCpu)
1394{
1395 return pVCpu->cpum.s.Guest.esi;
1396}
1397
1398
1399VMMDECL(uint32_t) CPUMGetGuestEDI(PVMCPU pVCpu)
1400{
1401 return pVCpu->cpum.s.Guest.edi;
1402}
1403
1404
1405VMMDECL(uint32_t) CPUMGetGuestESP(PVMCPU pVCpu)
1406{
1407 return pVCpu->cpum.s.Guest.esp;
1408}
1409
1410
1411VMMDECL(uint32_t) CPUMGetGuestEBP(PVMCPU pVCpu)
1412{
1413 return pVCpu->cpum.s.Guest.ebp;
1414}
1415
1416
1417VMMDECL(uint32_t) CPUMGetGuestEFlags(PVMCPU pVCpu)
1418{
1419 return pVCpu->cpum.s.Guest.eflags.u32;
1420}
1421
1422
1423VMMDECL(int) CPUMGetGuestCRx(PVMCPU pVCpu, unsigned iReg, uint64_t *pValue)
1424{
1425 switch (iReg)
1426 {
1427 case DISCREG_CR0:
1428 *pValue = pVCpu->cpum.s.Guest.cr0;
1429 break;
1430
1431 case DISCREG_CR2:
1432 *pValue = pVCpu->cpum.s.Guest.cr2;
1433 break;
1434
1435 case DISCREG_CR3:
1436 *pValue = pVCpu->cpum.s.Guest.cr3;
1437 break;
1438
1439 case DISCREG_CR4:
1440 *pValue = pVCpu->cpum.s.Guest.cr4;
1441 break;
1442
1443 case DISCREG_CR8:
1444 {
1445 uint8_t u8Tpr;
1446 int rc = PDMApicGetTPR(pVCpu, &u8Tpr, NULL /*pfPending*/);
1447 if (RT_FAILURE(rc))
1448 {
1449 AssertMsg(rc == VERR_PDM_NO_APIC_INSTANCE, ("%Rrc\n", rc));
1450 *pValue = 0;
1451 return rc;
1452 }
1453 *pValue = u8Tpr >> 4; /* bits 7-4 contain the task priority that go in cr8, bits 3-0*/
1454 break;
1455 }
1456
1457 default:
1458 return VERR_INVALID_PARAMETER;
1459 }
1460 return VINF_SUCCESS;
1461}
1462
1463
1464VMMDECL(uint64_t) CPUMGetGuestDR0(PVMCPU pVCpu)
1465{
1466 return pVCpu->cpum.s.Guest.dr[0];
1467}
1468
1469
1470VMMDECL(uint64_t) CPUMGetGuestDR1(PVMCPU pVCpu)
1471{
1472 return pVCpu->cpum.s.Guest.dr[1];
1473}
1474
1475
1476VMMDECL(uint64_t) CPUMGetGuestDR2(PVMCPU pVCpu)
1477{
1478 return pVCpu->cpum.s.Guest.dr[2];
1479}
1480
1481
1482VMMDECL(uint64_t) CPUMGetGuestDR3(PVMCPU pVCpu)
1483{
1484 return pVCpu->cpum.s.Guest.dr[3];
1485}
1486
1487
1488VMMDECL(uint64_t) CPUMGetGuestDR6(PVMCPU pVCpu)
1489{
1490 return pVCpu->cpum.s.Guest.dr[6];
1491}
1492
1493
1494VMMDECL(uint64_t) CPUMGetGuestDR7(PVMCPU pVCpu)
1495{
1496 return pVCpu->cpum.s.Guest.dr[7];
1497}
1498
1499
1500VMMDECL(int) CPUMGetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t *pValue)
1501{
1502 AssertReturn(iReg <= DISDREG_DR7, VERR_INVALID_PARAMETER);
1503 /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
1504 if (iReg == 4 || iReg == 5)
1505 iReg += 2;
1506 *pValue = pVCpu->cpum.s.Guest.dr[iReg];
1507 return VINF_SUCCESS;
1508}
1509
1510
1511VMMDECL(uint64_t) CPUMGetGuestEFER(PVMCPU pVCpu)
1512{
1513 return pVCpu->cpum.s.Guest.msrEFER;
1514}
1515
1516
1517/**
1518 * Gets a CPUID leaf.
1519 *
1520 * @param pVCpu Pointer to the VMCPU.
1521 * @param iLeaf The CPUID leaf to get.
1522 * @param pEax Where to store the EAX value.
1523 * @param pEbx Where to store the EBX value.
1524 * @param pEcx Where to store the ECX value.
1525 * @param pEdx Where to store the EDX value.
1526 */
1527VMMDECL(void) CPUMGetGuestCpuId(PVMCPU pVCpu, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx)
1528{
1529 PVM pVM = pVCpu->CTX_SUFF(pVM);
1530
1531 PCCPUMCPUID pCpuId;
1532 if (iLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
1533 pCpuId = &pVM->cpum.s.aGuestCpuIdStd[iLeaf];
1534 else if (iLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
1535 pCpuId = &pVM->cpum.s.aGuestCpuIdExt[iLeaf - UINT32_C(0x80000000)];
1536 else if ( iLeaf - UINT32_C(0x40000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdHyper)
1537 && (pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_HVP))
1538 pCpuId = &pVM->cpum.s.aGuestCpuIdHyper[iLeaf - UINT32_C(0x40000000)]; /* Only report if HVP bit set. */
1539 else if (iLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
1540 pCpuId = &pVM->cpum.s.aGuestCpuIdCentaur[iLeaf - UINT32_C(0xc0000000)];
1541 else
1542 pCpuId = &pVM->cpum.s.GuestCpuIdDef;
1543
1544 uint32_t cCurrentCacheIndex = *pEcx;
1545
1546 *pEax = pCpuId->eax;
1547 *pEbx = pCpuId->ebx;
1548 *pEcx = pCpuId->ecx;
1549 *pEdx = pCpuId->edx;
1550
1551 if ( iLeaf == 1)
1552 {
1553 /* Bits 31-24: Initial APIC ID */
1554 Assert(pVCpu->idCpu <= 255);
1555 *pEbx |= (pVCpu->idCpu << 24);
1556 }
1557
1558 if ( iLeaf == 4
1559 && cCurrentCacheIndex < 3
1560 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
1561 {
1562 uint32_t type, level, sharing, linesize,
1563 partitions, associativity, sets, cores;
1564
1565 /* For type: 1 - data cache, 2 - i-cache, 3 - unified */
1566 partitions = 1;
1567 /* Those are only to shut up compiler, as they will always
1568 get overwritten, and compiler should be able to figure that out */
1569 sets = associativity = sharing = level = 1;
1570 cores = pVM->cCpus > 32 ? 32 : pVM->cCpus;
1571 switch (cCurrentCacheIndex)
1572 {
1573 case 0:
1574 type = 1;
1575 level = 1;
1576 sharing = 1;
1577 linesize = 64;
1578 associativity = 8;
1579 sets = 64;
1580 break;
1581 case 1:
1582 level = 1;
1583 type = 2;
1584 sharing = 1;
1585 linesize = 64;
1586 associativity = 8;
1587 sets = 64;
1588 break;
1589 default: /* shut up gcc.*/
1590 AssertFailed();
1591 case 2:
1592 level = 2;
1593 type = 3;
1594 sharing = cores; /* our L2 cache is modelled as shared between all cores */
1595 linesize = 64;
1596 associativity = 24;
1597 sets = 4096;
1598 break;
1599 }
1600
1601 *pEax |= ((cores - 1) << 26) |
1602 ((sharing - 1) << 14) |
1603 (level << 5) |
1604 1;
1605 *pEbx = (linesize - 1) |
1606 ((partitions - 1) << 12) |
1607 ((associativity - 1) << 22); /* -1 encoding */
1608 *pEcx = sets - 1;
1609 }
1610
1611 Log2(("CPUMGetGuestCpuId: iLeaf=%#010x %RX32 %RX32 %RX32 %RX32\n", iLeaf, *pEax, *pEbx, *pEcx, *pEdx));
1612}
1613
1614/**
1615 * Gets a number of standard CPUID leafs.
1616 *
1617 * @returns Number of leafs.
1618 * @param pVM Pointer to the VM.
1619 * @remark Intended for PATM.
1620 */
1621VMMDECL(uint32_t) CPUMGetGuestCpuIdStdMax(PVM pVM)
1622{
1623 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd);
1624}
1625
1626
1627/**
1628 * Gets a number of extended CPUID leafs.
1629 *
1630 * @returns Number of leafs.
1631 * @param pVM Pointer to the VM.
1632 * @remark Intended for PATM.
1633 */
1634VMMDECL(uint32_t) CPUMGetGuestCpuIdExtMax(PVM pVM)
1635{
1636 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt);
1637}
1638
1639
1640/**
1641 * Gets a number of centaur CPUID leafs.
1642 *
1643 * @returns Number of leafs.
1644 * @param pVM Pointer to the VM.
1645 * @remark Intended for PATM.
1646 */
1647VMMDECL(uint32_t) CPUMGetGuestCpuIdCentaurMax(PVM pVM)
1648{
1649 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur);
1650}
1651
1652
1653/**
1654 * Sets a CPUID feature bit.
1655 *
1656 * @param pVM Pointer to the VM.
1657 * @param enmFeature The feature to set.
1658 */
1659VMMDECL(void) CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
1660{
1661 switch (enmFeature)
1662 {
1663 /*
1664 * Set the APIC bit in both feature masks.
1665 */
1666 case CPUMCPUIDFEATURE_APIC:
1667 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1668 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_APIC;
1669 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1670 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1671 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_APIC;
1672 LogRel(("CPUMSetGuestCpuIdFeature: Enabled APIC\n"));
1673 break;
1674
1675 /*
1676 * Set the x2APIC bit in the standard feature mask.
1677 */
1678 case CPUMCPUIDFEATURE_X2APIC:
1679 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1680 pVM->cpum.s.aGuestCpuIdStd[1].ecx |= X86_CPUID_FEATURE_ECX_X2APIC;
1681 LogRel(("CPUMSetGuestCpuIdFeature: Enabled x2APIC\n"));
1682 break;
1683
1684 /*
1685 * Set the sysenter/sysexit bit in the standard feature mask.
1686 * Assumes the caller knows what it's doing! (host must support these)
1687 */
1688 case CPUMCPUIDFEATURE_SEP:
1689 {
1690 if (!(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_SEP))
1691 {
1692 AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
1693 return;
1694 }
1695
1696 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1697 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_SEP;
1698 LogRel(("CPUMSetGuestCpuIdFeature: Enabled sysenter/exit\n"));
1699 break;
1700 }
1701
1702 /*
1703 * Set the syscall/sysret bit in the extended feature mask.
1704 * Assumes the caller knows what it's doing! (host must support these)
1705 */
1706 case CPUMCPUIDFEATURE_SYSCALL:
1707 {
1708 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1709 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_SYSCALL))
1710 {
1711#if HC_ARCH_BITS == 32
1712 /* X86_CPUID_EXT_FEATURE_EDX_SYSCALL not set it seems in 32 bits mode.
1713 * Even when the cpu is capable of doing so in 64 bits mode.
1714 */
1715 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1716 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
1717 || !(ASMCpuId_EDX(1) & X86_CPUID_EXT_FEATURE_EDX_SYSCALL))
1718#endif
1719 {
1720 LogRel(("WARNING: Can't turn on SYSCALL/SYSRET when the host doesn't support it!!\n"));
1721 return;
1722 }
1723 }
1724 /* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
1725 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
1726 LogRel(("CPUMSetGuestCpuIdFeature: Enabled syscall/ret\n"));
1727 break;
1728 }
1729
1730 /*
1731 * Set the PAE bit in both feature masks.
1732 * Assumes the caller knows what it's doing! (host must support these)
1733 */
1734 case CPUMCPUIDFEATURE_PAE:
1735 {
1736 if (!(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_PAE))
1737 {
1738 LogRel(("WARNING: Can't turn on PAE when the host doesn't support it!!\n"));
1739 return;
1740 }
1741
1742 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1743 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_PAE;
1744 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1745 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1746 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_PAE;
1747 LogRel(("CPUMSetGuestCpuIdFeature: Enabled PAE\n"));
1748 break;
1749 }
1750
1751 /*
1752 * Set the LONG MODE bit in the extended feature mask.
1753 * Assumes the caller knows what it's doing! (host must support these)
1754 */
1755 case CPUMCPUIDFEATURE_LONG_MODE:
1756 {
1757 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1758 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE))
1759 {
1760 LogRel(("WARNING: Can't turn on LONG MODE when the host doesn't support it!!\n"));
1761 return;
1762 }
1763
1764 /* Valid for both Intel and AMD. */
1765 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
1766 LogRel(("CPUMSetGuestCpuIdFeature: Enabled LONG MODE\n"));
1767 break;
1768 }
1769
1770 /*
1771 * Set the NX/XD bit in the extended feature mask.
1772 * Assumes the caller knows what it's doing! (host must support these)
1773 */
1774 case CPUMCPUIDFEATURE_NX:
1775 {
1776 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1777 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_NX))
1778 {
1779 LogRel(("WARNING: Can't turn on NX/XD when the host doesn't support it!!\n"));
1780 return;
1781 }
1782
1783 /* Valid for both Intel and AMD. */
1784 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_NX;
1785 LogRel(("CPUMSetGuestCpuIdFeature: Enabled NX\n"));
1786 break;
1787 }
1788
1789 /*
1790 * Set the LAHF/SAHF support in 64-bit mode.
1791 * Assumes the caller knows what it's doing! (host must support this)
1792 */
1793 case CPUMCPUIDFEATURE_LAHF:
1794 {
1795 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1796 || !(ASMCpuId_ECX(0x80000001) & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF))
1797 {
1798 LogRel(("WARNING: Can't turn on LAHF/SAHF when the host doesn't support it!!\n"));
1799 return;
1800 }
1801
1802 /* Valid for both Intel and AMD. */
1803 pVM->cpum.s.aGuestCpuIdExt[1].ecx |= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
1804 LogRel(("CPUMSetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
1805 break;
1806 }
1807
1808 case CPUMCPUIDFEATURE_PAT:
1809 {
1810 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1811 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_PAT;
1812 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1813 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1814 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_PAT;
1815 LogRel(("CPUMClearGuestCpuIdFeature: Enabled PAT\n"));
1816 break;
1817 }
1818
1819 /*
1820 * Set the RDTSCP support bit.
1821 * Assumes the caller knows what it's doing! (host must support this)
1822 */
1823 case CPUMCPUIDFEATURE_RDTSCP:
1824 {
1825 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1826 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
1827 || pVM->cpum.s.u8PortableCpuIdLevel > 0)
1828 {
1829 if (!pVM->cpum.s.u8PortableCpuIdLevel)
1830 LogRel(("WARNING: Can't turn on RDTSCP when the host doesn't support it!!\n"));
1831 return;
1832 }
1833
1834 /* Valid for both Intel and AMD. */
1835 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
1836 LogRel(("CPUMSetGuestCpuIdFeature: Enabled RDTSCP.\n"));
1837 break;
1838 }
1839
1840 /*
1841 * Set the Hypervisor Present bit in the standard feature mask.
1842 */
1843 case CPUMCPUIDFEATURE_HVP:
1844 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1845 pVM->cpum.s.aGuestCpuIdStd[1].ecx |= X86_CPUID_FEATURE_ECX_HVP;
1846 LogRel(("CPUMSetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
1847 break;
1848
1849 default:
1850 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
1851 break;
1852 }
1853 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1854 {
1855 PVMCPU pVCpu = &pVM->aCpus[i];
1856 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CPUID;
1857 }
1858}
1859
1860
1861/**
1862 * Queries a CPUID feature bit.
1863 *
1864 * @returns boolean for feature presence
1865 * @param pVM Pointer to the VM.
1866 * @param enmFeature The feature to query.
1867 */
1868VMMDECL(bool) CPUMGetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
1869{
1870 switch (enmFeature)
1871 {
1872 case CPUMCPUIDFEATURE_PAE:
1873 {
1874 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1875 return !!(pVM->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PAE);
1876 break;
1877 }
1878
1879 case CPUMCPUIDFEATURE_NX:
1880 {
1881 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1882 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_EXT_FEATURE_EDX_NX);
1883 }
1884
1885 case CPUMCPUIDFEATURE_RDTSCP:
1886 {
1887 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1888 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1889 break;
1890 }
1891
1892 case CPUMCPUIDFEATURE_LONG_MODE:
1893 {
1894 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1895 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1896 break;
1897 }
1898
1899 default:
1900 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
1901 break;
1902 }
1903 return false;
1904}
1905
1906
1907/**
1908 * Clears a CPUID feature bit.
1909 *
1910 * @param pVM Pointer to the VM.
1911 * @param enmFeature The feature to clear.
1912 */
1913VMMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
1914{
1915 switch (enmFeature)
1916 {
1917 /*
1918 * Set the APIC bit in both feature masks.
1919 */
1920 case CPUMCPUIDFEATURE_APIC:
1921 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1922 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_APIC;
1923 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1924 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1925 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
1926 Log(("CPUMSetGuestCpuIdFeature: Disabled APIC\n"));
1927 break;
1928
1929 /*
1930 * Clear the x2APIC bit in the standard feature mask.
1931 */
1932 case CPUMCPUIDFEATURE_X2APIC:
1933 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1934 pVM->cpum.s.aGuestCpuIdStd[1].ecx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
1935 LogRel(("CPUMSetGuestCpuIdFeature: Disabled x2APIC\n"));
1936 break;
1937
1938 case CPUMCPUIDFEATURE_PAE:
1939 {
1940 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1941 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_PAE;
1942 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1943 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1944 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
1945 LogRel(("CPUMClearGuestCpuIdFeature: Disabled PAE!\n"));
1946 break;
1947 }
1948
1949 case CPUMCPUIDFEATURE_PAT:
1950 {
1951 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1952 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_PAT;
1953 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1954 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1955 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_PAT;
1956 LogRel(("CPUMClearGuestCpuIdFeature: Disabled PAT!\n"));
1957 break;
1958 }
1959
1960 case CPUMCPUIDFEATURE_LONG_MODE:
1961 {
1962 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1963 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
1964 break;
1965 }
1966
1967 case CPUMCPUIDFEATURE_LAHF:
1968 {
1969 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1970 pVM->cpum.s.aGuestCpuIdExt[1].ecx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
1971 break;
1972 }
1973
1974 case CPUMCPUIDFEATURE_RDTSCP:
1975 {
1976 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1977 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
1978 LogRel(("CPUMClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
1979 break;
1980 }
1981
1982 case CPUMCPUIDFEATURE_HVP:
1983 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1984 pVM->cpum.s.aGuestCpuIdStd[1].ecx &= ~X86_CPUID_FEATURE_ECX_HVP;
1985 break;
1986
1987 default:
1988 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
1989 break;
1990 }
1991 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1992 {
1993 PVMCPU pVCpu = &pVM->aCpus[i];
1994 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CPUID;
1995 }
1996}
1997
1998
1999/**
2000 * Gets the host CPU vendor.
2001 *
2002 * @returns CPU vendor.
2003 * @param pVM Pointer to the VM.
2004 */
2005VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM)
2006{
2007 return pVM->cpum.s.enmHostCpuVendor;
2008}
2009
2010
2011/**
2012 * Gets the CPU vendor.
2013 *
2014 * @returns CPU vendor.
2015 * @param pVM Pointer to the VM.
2016 */
2017VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM)
2018{
2019 return pVM->cpum.s.enmGuestCpuVendor;
2020}
2021
2022
2023VMMDECL(int) CPUMSetGuestDR0(PVMCPU pVCpu, uint64_t uDr0)
2024{
2025 pVCpu->cpum.s.Guest.dr[0] = uDr0;
2026 return CPUMRecalcHyperDRx(pVCpu);
2027}
2028
2029
2030VMMDECL(int) CPUMSetGuestDR1(PVMCPU pVCpu, uint64_t uDr1)
2031{
2032 pVCpu->cpum.s.Guest.dr[1] = uDr1;
2033 return CPUMRecalcHyperDRx(pVCpu);
2034}
2035
2036
2037VMMDECL(int) CPUMSetGuestDR2(PVMCPU pVCpu, uint64_t uDr2)
2038{
2039 pVCpu->cpum.s.Guest.dr[2] = uDr2;
2040 return CPUMRecalcHyperDRx(pVCpu);
2041}
2042
2043
2044VMMDECL(int) CPUMSetGuestDR3(PVMCPU pVCpu, uint64_t uDr3)
2045{
2046 pVCpu->cpum.s.Guest.dr[3] = uDr3;
2047 return CPUMRecalcHyperDRx(pVCpu);
2048}
2049
2050
2051VMMDECL(int) CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6)
2052{
2053 pVCpu->cpum.s.Guest.dr[6] = uDr6;
2054 return CPUMRecalcHyperDRx(pVCpu);
2055}
2056
2057
2058VMMDECL(int) CPUMSetGuestDR7(PVMCPU pVCpu, uint64_t uDr7)
2059{
2060 pVCpu->cpum.s.Guest.dr[7] = uDr7;
2061 return CPUMRecalcHyperDRx(pVCpu);
2062}
2063
2064
2065VMMDECL(int) CPUMSetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t Value)
2066{
2067 AssertReturn(iReg <= DISDREG_DR7, VERR_INVALID_PARAMETER);
2068 /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
2069 if (iReg == 4 || iReg == 5)
2070 iReg += 2;
2071 pVCpu->cpum.s.Guest.dr[iReg] = Value;
2072 return CPUMRecalcHyperDRx(pVCpu);
2073}
2074
2075
2076/**
2077 * Recalculates the hypervisor DRx register values based on
2078 * current guest registers and DBGF breakpoints.
2079 *
2080 * This is called whenever a guest DRx register is modified and when DBGF
2081 * sets a hardware breakpoint. In guest context this function will reload
2082 * any (hyper) DRx registers which comes out with a different value.
2083 *
2084 * @returns VINF_SUCCESS.
2085 * @param pVCpu Pointer to the VMCPU.
2086 */
2087VMMDECL(int) CPUMRecalcHyperDRx(PVMCPU pVCpu)
2088{
2089 PVM pVM = pVCpu->CTX_SUFF(pVM);
2090
2091 /*
2092 * Compare the DR7s first.
2093 *
2094 * We only care about the enabled flags. The GE and LE flags are always
2095 * set and we don't care if the guest doesn't set them. GD is virtualized
2096 * when we dispatch #DB, we never enable it.
2097 */
2098 const RTGCUINTREG uDbgfDr7 = DBGFBpGetDR7(pVM);
2099#ifdef CPUM_VIRTUALIZE_DRX
2100 const RTGCUINTREG uGstDr7 = CPUMGetGuestDR7(pVCpu);
2101#else
2102 const RTGCUINTREG uGstDr7 = 0;
2103#endif
2104 if ((uGstDr7 | uDbgfDr7) & X86_DR7_ENABLED_MASK)
2105 {
2106 /*
2107 * Ok, something is enabled. Recalc each of the breakpoints.
2108 * Straight forward code, not optimized/minimized in any way.
2109 */
2110 RTGCUINTREG uNewDr7 = X86_DR7_GE | X86_DR7_LE | X86_DR7_MB1_MASK;
2111
2112 /* bp 0 */
2113 RTGCUINTREG uNewDr0;
2114 if (uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0))
2115 {
2116 uNewDr7 |= uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
2117 uNewDr0 = DBGFBpGetDR0(pVM);
2118 }
2119 else if (uGstDr7 & (X86_DR7_L0 | X86_DR7_G0))
2120 {
2121 uNewDr7 |= uGstDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
2122 uNewDr0 = CPUMGetGuestDR0(pVCpu);
2123 }
2124 else
2125 uNewDr0 = pVCpu->cpum.s.Hyper.dr[0];
2126
2127 /* bp 1 */
2128 RTGCUINTREG uNewDr1;
2129 if (uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1))
2130 {
2131 uNewDr7 |= uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
2132 uNewDr1 = DBGFBpGetDR1(pVM);
2133 }
2134 else if (uGstDr7 & (X86_DR7_L1 | X86_DR7_G1))
2135 {
2136 uNewDr7 |= uGstDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
2137 uNewDr1 = CPUMGetGuestDR1(pVCpu);
2138 }
2139 else
2140 uNewDr1 = pVCpu->cpum.s.Hyper.dr[1];
2141
2142 /* bp 2 */
2143 RTGCUINTREG uNewDr2;
2144 if (uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2))
2145 {
2146 uNewDr7 |= uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
2147 uNewDr2 = DBGFBpGetDR2(pVM);
2148 }
2149 else if (uGstDr7 & (X86_DR7_L2 | X86_DR7_G2))
2150 {
2151 uNewDr7 |= uGstDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
2152 uNewDr2 = CPUMGetGuestDR2(pVCpu);
2153 }
2154 else
2155 uNewDr2 = pVCpu->cpum.s.Hyper.dr[2];
2156
2157 /* bp 3 */
2158 RTGCUINTREG uNewDr3;
2159 if (uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3))
2160 {
2161 uNewDr7 |= uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
2162 uNewDr3 = DBGFBpGetDR3(pVM);
2163 }
2164 else if (uGstDr7 & (X86_DR7_L3 | X86_DR7_G3))
2165 {
2166 uNewDr7 |= uGstDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
2167 uNewDr3 = CPUMGetGuestDR3(pVCpu);
2168 }
2169 else
2170 uNewDr3 = pVCpu->cpum.s.Hyper.dr[3];
2171
2172 /*
2173 * Apply the updates.
2174 */
2175#ifdef IN_RC
2176 if (!(pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS))
2177 {
2178 /** @todo save host DBx registers. */
2179 }
2180#endif
2181 pVCpu->cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS;
2182 if (uNewDr3 != pVCpu->cpum.s.Hyper.dr[3])
2183 CPUMSetHyperDR3(pVCpu, uNewDr3);
2184 if (uNewDr2 != pVCpu->cpum.s.Hyper.dr[2])
2185 CPUMSetHyperDR2(pVCpu, uNewDr2);
2186 if (uNewDr1 != pVCpu->cpum.s.Hyper.dr[1])
2187 CPUMSetHyperDR1(pVCpu, uNewDr1);
2188 if (uNewDr0 != pVCpu->cpum.s.Hyper.dr[0])
2189 CPUMSetHyperDR0(pVCpu, uNewDr0);
2190 if (uNewDr7 != pVCpu->cpum.s.Hyper.dr[7])
2191 CPUMSetHyperDR7(pVCpu, uNewDr7);
2192 }
2193 else
2194 {
2195#ifdef IN_RC
2196 if (pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS)
2197 {
2198 /** @todo restore host DBx registers. */
2199 }
2200#endif
2201 pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS;
2202 }
2203 Log2(("CPUMRecalcHyperDRx: fUseFlags=%#x %RGr %RGr %RGr %RGr %RGr %RGr\n",
2204 pVCpu->cpum.s.fUseFlags, pVCpu->cpum.s.Hyper.dr[0], pVCpu->cpum.s.Hyper.dr[1],
2205 pVCpu->cpum.s.Hyper.dr[2], pVCpu->cpum.s.Hyper.dr[3], pVCpu->cpum.s.Hyper.dr[6],
2206 pVCpu->cpum.s.Hyper.dr[7]));
2207
2208 return VINF_SUCCESS;
2209}
2210
2211
2212/**
2213 * Tests if the guest has No-Execute Page Protection Enabled (NXE).
2214 *
2215 * @returns true if in real mode, otherwise false.
2216 * @param pVCpu Pointer to the VMCPU.
2217 */
2218VMMDECL(bool) CPUMIsGuestNXEnabled(PVMCPU pVCpu)
2219{
2220 return !!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE);
2221}
2222
2223
2224/**
2225 * Tests if the guest has the Page Size Extension enabled (PSE).
2226 *
2227 * @returns true if in real mode, otherwise false.
2228 * @param pVCpu Pointer to the VMCPU.
2229 */
2230VMMDECL(bool) CPUMIsGuestPageSizeExtEnabled(PVMCPU pVCpu)
2231{
2232 /* PAE or AMD64 implies support for big pages regardless of CR4.PSE */
2233 return !!(pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PSE | X86_CR4_PAE));
2234}
2235
2236
2237/**
2238 * Tests if the guest has the paging enabled (PG).
2239 *
2240 * @returns true if in real mode, otherwise false.
2241 * @param pVCpu Pointer to the VMCPU.
2242 */
2243VMMDECL(bool) CPUMIsGuestPagingEnabled(PVMCPU pVCpu)
2244{
2245 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG);
2246}
2247
2248
2249/**
2250 * Tests if the guest has the paging enabled (PG).
2251 *
2252 * @returns true if in real mode, otherwise false.
2253 * @param pVCpu Pointer to the VMCPU.
2254 */
2255VMMDECL(bool) CPUMIsGuestR0WriteProtEnabled(PVMCPU pVCpu)
2256{
2257 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_WP);
2258}
2259
2260
2261/**
2262 * Tests if the guest is running in real mode or not.
2263 *
2264 * @returns true if in real mode, otherwise false.
2265 * @param pVCpu Pointer to the VMCPU.
2266 */
2267VMMDECL(bool) CPUMIsGuestInRealMode(PVMCPU pVCpu)
2268{
2269 return !(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
2270}
2271
2272
2273/**
2274 * Tests if the guest is running in real or virtual 8086 mode.
2275 *
2276 * @returns @c true if it is, @c false if not.
2277 * @param pVCpu Pointer to the VMCPU.
2278 */
2279VMMDECL(bool) CPUMIsGuestInRealOrV86Mode(PVMCPU pVCpu)
2280{
2281 return !(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE)
2282 || pVCpu->cpum.s.Guest.eflags.Bits.u1VM; /** @todo verify that this cannot be set in long mode. */
2283}
2284
2285
2286/**
2287 * Tests if the guest is running in protected or not.
2288 *
2289 * @returns true if in protected mode, otherwise false.
2290 * @param pVCpu Pointer to the VMCPU.
2291 */
2292VMMDECL(bool) CPUMIsGuestInProtectedMode(PVMCPU pVCpu)
2293{
2294 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
2295}
2296
2297
2298/**
2299 * Tests if the guest is running in paged protected or not.
2300 *
2301 * @returns true if in paged protected mode, otherwise false.
2302 * @param pVCpu Pointer to the VMCPU.
2303 */
2304VMMDECL(bool) CPUMIsGuestInPagedProtectedMode(PVMCPU pVCpu)
2305{
2306 return (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
2307}
2308
2309
2310/**
2311 * Tests if the guest is running in long mode or not.
2312 *
2313 * @returns true if in long mode, otherwise false.
2314 * @param pVCpu Pointer to the VMCPU.
2315 */
2316VMMDECL(bool) CPUMIsGuestInLongMode(PVMCPU pVCpu)
2317{
2318 return (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
2319}
2320
2321
2322/**
2323 * Tests if the guest is running in PAE mode or not.
2324 *
2325 * @returns true if in PAE mode, otherwise false.
2326 * @param pVCpu Pointer to the VMCPU.
2327 */
2328VMMDECL(bool) CPUMIsGuestInPAEMode(PVMCPU pVCpu)
2329{
2330 return (pVCpu->cpum.s.Guest.cr4 & X86_CR4_PAE)
2331 && (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG)
2332 && !(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA);
2333}
2334
2335
2336/**
2337 * Tests if the guest is running in 64 bits mode or not.
2338 *
2339 * @returns true if in 64 bits protected mode, otherwise false.
2340 * @param pVCpu The current virtual CPU.
2341 */
2342VMMDECL(bool) CPUMIsGuestIn64BitCode(PVMCPU pVCpu)
2343{
2344 if (!CPUMIsGuestInLongMode(pVCpu))
2345 return false;
2346 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
2347 return pVCpu->cpum.s.Guest.cs.Attr.n.u1Long;
2348}
2349
2350
2351/**
2352 * Helper for CPUMIsGuestIn64BitCodeEx that handles lazy resolving of hidden CS
2353 * registers.
2354 *
2355 * @returns true if in 64 bits protected mode, otherwise false.
2356 * @param pCtx Pointer to the current guest CPU context.
2357 */
2358VMM_INT_DECL(bool) CPUMIsGuestIn64BitCodeSlow(PCPUMCTX pCtx)
2359{
2360 return CPUMIsGuestIn64BitCode(CPUM_GUEST_CTX_TO_VMCPU(pCtx));
2361}
2362
2363#ifdef VBOX_WITH_RAW_MODE_NOT_R0
2364/**
2365 *
2366 * @returns @c true if we've entered raw-mode and selectors with RPL=1 are
2367 * really RPL=0, @c false if we've not (RPL=1 really is RPL=1).
2368 * @param pVCpu The current virtual CPU.
2369 */
2370VMM_INT_DECL(bool) CPUMIsGuestInRawMode(PVMCPU pVCpu)
2371{
2372 return pVCpu->cpum.s.fRawEntered;
2373}
2374#endif
2375
2376#ifdef VBOX_WITH_RAW_MODE_NOT_R0
2377/**
2378 * Updates the EFLAGS while we're in raw-mode.
2379 *
2380 * @param pVCpu Pointer to the VMCPU.
2381 * @param fEfl The new EFLAGS value.
2382 */
2383VMMDECL(void) CPUMRawSetEFlags(PVMCPU pVCpu, uint32_t fEfl)
2384{
2385 if (!pVCpu->cpum.s.fRawEntered)
2386 pVCpu->cpum.s.Guest.eflags.u32 = fEfl;
2387 else
2388 PATMRawSetEFlags(pVCpu->CTX_SUFF(pVM), CPUMCTX2CORE(&pVCpu->cpum.s.Guest), fEfl);
2389}
2390#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
2391
2392
2393/**
2394 * Gets the EFLAGS while we're in raw-mode.
2395 *
2396 * @returns The eflags.
2397 * @param pVCpu Pointer to the current virtual CPU.
2398 */
2399VMMDECL(uint32_t) CPUMRawGetEFlags(PVMCPU pVCpu)
2400{
2401#ifdef IN_RING0
2402 return pVCpu->cpum.s.Guest.eflags.u32;
2403#else
2404
2405 if (!pVCpu->cpum.s.fRawEntered)
2406 return pVCpu->cpum.s.Guest.eflags.u32;
2407 return PATMRawGetEFlags(pVCpu->CTX_SUFF(pVM), CPUMCTX2CORE(&pVCpu->cpum.s.Guest));
2408#endif
2409}
2410
2411
2412/**
2413 * Sets the specified changed flags (CPUM_CHANGED_*).
2414 *
2415 * @param pVCpu Pointer to the current virtual CPU.
2416 */
2417VMMDECL(void) CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedFlags)
2418{
2419 pVCpu->cpum.s.fChanged |= fChangedFlags;
2420}
2421
2422
2423/**
2424 * Checks if the CPU supports the FXSAVE and FXRSTOR instruction.
2425 * @returns true if supported.
2426 * @returns false if not supported.
2427 * @param pVM Pointer to the VM.
2428 */
2429VMMDECL(bool) CPUMSupportsFXSR(PVM pVM)
2430{
2431 return pVM->cpum.s.CPUFeatures.edx.u1FXSR != 0;
2432}
2433
2434
2435/**
2436 * Checks if the host OS uses the SYSENTER / SYSEXIT instructions.
2437 * @returns true if used.
2438 * @returns false if not used.
2439 * @param pVM Pointer to the VM.
2440 */
2441VMMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM)
2442{
2443 return (pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSENTER) != 0;
2444}
2445
2446
2447/**
2448 * Checks if the host OS uses the SYSCALL / SYSRET instructions.
2449 * @returns true if used.
2450 * @returns false if not used.
2451 * @param pVM Pointer to the VM.
2452 */
2453VMMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM)
2454{
2455 return (pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSCALL) != 0;
2456}
2457
2458#ifndef IN_RING3
2459
2460/**
2461 * Lazily sync in the FPU/XMM state.
2462 *
2463 * @returns VBox status code.
2464 * @param pVCpu Pointer to the VMCPU.
2465 */
2466VMMDECL(int) CPUMHandleLazyFPU(PVMCPU pVCpu)
2467{
2468 return cpumHandleLazyFPUAsm(&pVCpu->cpum.s);
2469}
2470
2471#endif /* !IN_RING3 */
2472
2473/**
2474 * Checks if we activated the FPU/XMM state of the guest OS.
2475 * @returns true if we did.
2476 * @returns false if not.
2477 * @param pVCpu Pointer to the VMCPU.
2478 */
2479VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCpu)
2480{
2481 return (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU) != 0;
2482}
2483
2484
2485/**
2486 * Deactivate the FPU/XMM state of the guest OS.
2487 * @param pVCpu Pointer to the VMCPU.
2488 */
2489VMMDECL(void) CPUMDeactivateGuestFPUState(PVMCPU pVCpu)
2490{
2491 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU;
2492}
2493
2494
2495/**
2496 * Checks if the guest debug state is active.
2497 *
2498 * @returns boolean
2499 * @param pVM Pointer to the VM.
2500 */
2501VMMDECL(bool) CPUMIsGuestDebugStateActive(PVMCPU pVCpu)
2502{
2503 return (pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS) != 0;
2504}
2505
2506/**
2507 * Checks if the hyper debug state is active.
2508 *
2509 * @returns boolean
2510 * @param pVM Pointer to the VM.
2511 */
2512VMMDECL(bool) CPUMIsHyperDebugStateActive(PVMCPU pVCpu)
2513{
2514 return (pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS_HYPER) != 0;
2515}
2516
2517
2518/**
2519 * Mark the guest's debug state as inactive.
2520 *
2521 * @returns boolean
2522 * @param pVM Pointer to the VM.
2523 */
2524VMMDECL(void) CPUMDeactivateGuestDebugState(PVMCPU pVCpu)
2525{
2526 pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS;
2527}
2528
2529
2530/**
2531 * Mark the hypervisor's debug state as inactive.
2532 *
2533 * @returns boolean
2534 * @param pVM Pointer to the VM.
2535 */
2536VMMDECL(void) CPUMDeactivateHyperDebugState(PVMCPU pVCpu)
2537{
2538 pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS_HYPER;
2539}
2540
2541
2542/**
2543 * Get the current privilege level of the guest.
2544 *
2545 * @returns CPL
2546 * @param pVCpu Pointer to the current virtual CPU.
2547 */
2548VMMDECL(uint32_t) CPUMGetGuestCPL(PVMCPU pVCpu)
2549{
2550 /*
2551 * CPL can reliably be found in SS.DPL (hidden regs valid) or SS if not.
2552 *
2553 * Note! We used to check CS.DPL here, assuming it was always equal to
2554 * CPL even if a conforming segment was loaded. But this truned out to
2555 * only apply to older AMD-V. With VT-x we had an ACP2 regression
2556 * during install after a far call to ring 2 with VT-x. Then on newer
2557 * AMD-V CPUs we have to move the VMCB.guest.u8CPL into cs.Attr.n.u2Dpl
2558 * as well as ss.Attr.n.u2Dpl to make this (and other) code work right.
2559 *
2560 * So, forget CS.DPL, always use SS.DPL.
2561 *
2562 * Note! The SS RPL is always equal to the CPL, while the CS RPL
2563 * isn't necessarily equal if the segment is conforming.
2564 * See section 4.11.1 in the AMD manual.
2565 */
2566 uint32_t uCpl;
2567 if (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE)
2568 {
2569 if (!pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
2570 {
2571 if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.s.Guest.ss))
2572 uCpl = pVCpu->cpum.s.Guest.ss.Attr.n.u2Dpl;
2573 else
2574 {
2575 uCpl = (pVCpu->cpum.s.Guest.ss.Sel & X86_SEL_RPL);
2576#ifdef VBOX_WITH_RAW_MODE_NOT_R0
2577 if (uCpl == 1)
2578 uCpl = 0;
2579#endif
2580 }
2581 }
2582 else
2583 uCpl = 3; /* V86 has CPL=3; REM doesn't set DPL=3 in V8086 mode. See @bugref{5130}. */
2584 }
2585 else
2586 uCpl = 0; /* Real mode is zero; CPL set to 3 for VT-x real-mode emulation. */
2587 return uCpl;
2588}
2589
2590
2591/**
2592 * Gets the current guest CPU mode.
2593 *
2594 * If paging mode is what you need, check out PGMGetGuestMode().
2595 *
2596 * @returns The CPU mode.
2597 * @param pVCpu Pointer to the VMCPU.
2598 */
2599VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu)
2600{
2601 CPUMMODE enmMode;
2602 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
2603 enmMode = CPUMMODE_REAL;
2604 else if (!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
2605 enmMode = CPUMMODE_PROTECTED;
2606 else
2607 enmMode = CPUMMODE_LONG;
2608
2609 return enmMode;
2610}
2611
2612
2613/**
2614 * Figure whether the CPU is currently executing 16, 32 or 64 bit code.
2615 *
2616 * @returns 16, 32 or 64.
2617 * @param pVCpu The current virtual CPU.
2618 */
2619VMMDECL(uint32_t) CPUMGetGuestCodeBits(PVMCPU pVCpu)
2620{
2621 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
2622 return 16;
2623
2624 if (pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
2625 {
2626 Assert(!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA));
2627 return 16;
2628 }
2629
2630 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
2631 if ( pVCpu->cpum.s.Guest.cs.Attr.n.u1Long
2632 && (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
2633 return 64;
2634
2635 if (pVCpu->cpum.s.Guest.cs.Attr.n.u1DefBig)
2636 return 32;
2637
2638 return 16;
2639}
2640
2641
2642VMMDECL(DISCPUMODE) CPUMGetGuestDisMode(PVMCPU pVCpu)
2643{
2644 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
2645 return DISCPUMODE_16BIT;
2646
2647 if (pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
2648 {
2649 Assert(!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA));
2650 return DISCPUMODE_16BIT;
2651 }
2652
2653 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
2654 if ( pVCpu->cpum.s.Guest.cs.Attr.n.u1Long
2655 && (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
2656 return DISCPUMODE_64BIT;
2657
2658 if (pVCpu->cpum.s.Guest.cs.Attr.n.u1DefBig)
2659 return DISCPUMODE_32BIT;
2660
2661 return DISCPUMODE_16BIT;
2662}
2663
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