VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp@ 47939

Last change on this file since 47939 was 47939, checked in by vboxsync, 11 years ago

Ignore MSR_K8_SYSCFG on AMD64 like we used to do.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 92.6 KB
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1/* $Id: CPUMAllRegs.cpp 47939 2013-08-20 16:39:28Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor(/Manager) - Getters and Setters.
4 */
5
6/*
7 * Copyright (C) 2006-2012 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_CPUM
23#include <VBox/vmm/cpum.h>
24#include <VBox/vmm/patm.h>
25#include <VBox/vmm/dbgf.h>
26#include <VBox/vmm/pdm.h>
27#include <VBox/vmm/pgm.h>
28#include <VBox/vmm/mm.h>
29#include <VBox/vmm/em.h>
30#if defined(VBOX_WITH_RAW_MODE) && !defined(IN_RING0)
31# include <VBox/vmm/selm.h>
32#endif
33#include "CPUMInternal.h"
34#include <VBox/vmm/vm.h>
35#include <VBox/err.h>
36#include <VBox/dis.h>
37#include <VBox/log.h>
38#include <VBox/vmm/hm.h>
39#include <VBox/vmm/tm.h>
40#include <iprt/assert.h>
41#include <iprt/asm.h>
42#include <iprt/asm-amd64-x86.h>
43#ifdef IN_RING3
44#include <iprt/thread.h>
45#endif
46
47/** Disable stack frame pointer generation here. */
48#if defined(_MSC_VER) && !defined(DEBUG)
49# pragma optimize("y", off)
50#endif
51
52
53/*******************************************************************************
54* Defined Constants And Macros *
55*******************************************************************************/
56/**
57 * Converts a CPUMCPU::Guest pointer into a VMCPU pointer.
58 *
59 * @returns Pointer to the Virtual CPU.
60 * @param a_pGuestCtx Pointer to the guest context.
61 */
62#define CPUM_GUEST_CTX_TO_VMCPU(a_pGuestCtx) RT_FROM_MEMBER(a_pGuestCtx, VMCPU, cpum.s.Guest)
63
64/**
65 * Lazily loads the hidden parts of a selector register when using raw-mode.
66 */
67#if defined(VBOX_WITH_RAW_MODE) && !defined(IN_RING0)
68# define CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(a_pVCpu, a_pSReg) \
69 do \
70 { \
71 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(a_pVCpu, a_pSReg)) \
72 cpumGuestLazyLoadHiddenSelectorReg(a_pVCpu, a_pSReg); \
73 } while (0)
74#else
75# define CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(a_pVCpu, a_pSReg) \
76 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(a_pVCpu, a_pSReg));
77#endif
78
79
80
81#ifdef VBOX_WITH_RAW_MODE_NOT_R0
82
83/**
84 * Does the lazy hidden selector register loading.
85 *
86 * @param pVCpu The current Virtual CPU.
87 * @param pSReg The selector register to lazily load hidden parts of.
88 */
89static void cpumGuestLazyLoadHiddenSelectorReg(PVMCPU pVCpu, PCPUMSELREG pSReg)
90{
91 Assert(!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSReg));
92 Assert(!HMIsEnabled(pVCpu->CTX_SUFF(pVM)));
93 Assert((uintptr_t)(pSReg - &pVCpu->cpum.s.Guest.es) < X86_SREG_COUNT);
94
95 if (pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
96 {
97 /* V8086 mode - Tightly controlled environment, no question about the limit or flags. */
98 pSReg->Attr.u = 0;
99 pSReg->Attr.n.u4Type = pSReg == &pVCpu->cpum.s.Guest.cs ? X86_SEL_TYPE_ER_ACC : X86_SEL_TYPE_RW_ACC;
100 pSReg->Attr.n.u1DescType = 1; /* code/data segment */
101 pSReg->Attr.n.u2Dpl = 3;
102 pSReg->Attr.n.u1Present = 1;
103 pSReg->u32Limit = 0x0000ffff;
104 pSReg->u64Base = (uint32_t)pSReg->Sel << 4;
105 pSReg->ValidSel = pSReg->Sel;
106 pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
107 /** @todo Check what the accessed bit should be (VT-x and AMD-V). */
108 }
109 else if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
110 {
111 /* Real mode - leave the limit and flags alone here, at least for now. */
112 pSReg->u64Base = (uint32_t)pSReg->Sel << 4;
113 pSReg->ValidSel = pSReg->Sel;
114 pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
115 }
116 else
117 {
118 /* Protected mode - get it from the selector descriptor tables. */
119 if (!(pSReg->Sel & X86_SEL_MASK_OFF_RPL))
120 {
121 Assert(!CPUMIsGuestInLongMode(pVCpu));
122 pSReg->Sel = 0;
123 pSReg->u64Base = 0;
124 pSReg->u32Limit = 0;
125 pSReg->Attr.u = 0;
126 pSReg->ValidSel = 0;
127 pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
128 /** @todo see todo in iemHlpLoadNullDataSelectorProt. */
129 }
130 else
131 SELMLoadHiddenSelectorReg(pVCpu, &pVCpu->cpum.s.Guest, pSReg);
132 }
133}
134
135
136/**
137 * Makes sure the hidden CS and SS selector registers are valid, loading them if
138 * necessary.
139 *
140 * @param pVCpu The current virtual CPU.
141 */
142VMM_INT_DECL(void) CPUMGuestLazyLoadHiddenCsAndSs(PVMCPU pVCpu)
143{
144 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
145 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.ss);
146}
147
148
149/**
150 * Loads a the hidden parts of a selector register.
151 *
152 * @param pVCpu The current virtual CPU.
153 */
154VMM_INT_DECL(void) CPUMGuestLazyLoadHiddenSelectorReg(PVMCPU pVCpu, PCPUMSELREG pSReg)
155{
156 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, pSReg);
157}
158
159#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
160
161
162/**
163 * Obsolete.
164 *
165 * We don't support nested hypervisor context interrupts or traps. Life is much
166 * simpler when we don't. It's also slightly faster at times.
167 *
168 * @param pVM Handle to the virtual machine.
169 */
170VMMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVMCPU pVCpu)
171{
172 return CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
173}
174
175
176/**
177 * Gets the pointer to the hypervisor CPU context structure of a virtual CPU.
178 *
179 * @param pVCpu Pointer to the VMCPU.
180 */
181VMMDECL(PCPUMCTX) CPUMGetHyperCtxPtr(PVMCPU pVCpu)
182{
183 return &pVCpu->cpum.s.Hyper;
184}
185
186
187VMMDECL(void) CPUMSetHyperGDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
188{
189 pVCpu->cpum.s.Hyper.gdtr.cbGdt = limit;
190 pVCpu->cpum.s.Hyper.gdtr.pGdt = addr;
191}
192
193
194VMMDECL(void) CPUMSetHyperIDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
195{
196 pVCpu->cpum.s.Hyper.idtr.cbIdt = limit;
197 pVCpu->cpum.s.Hyper.idtr.pIdt = addr;
198}
199
200
201VMMDECL(void) CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3)
202{
203 pVCpu->cpum.s.Hyper.cr3 = cr3;
204
205#ifdef IN_RC
206 /* Update the current CR3. */
207 ASMSetCR3(cr3);
208#endif
209}
210
211VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu)
212{
213 return pVCpu->cpum.s.Hyper.cr3;
214}
215
216
217VMMDECL(void) CPUMSetHyperCS(PVMCPU pVCpu, RTSEL SelCS)
218{
219 pVCpu->cpum.s.Hyper.cs.Sel = SelCS;
220}
221
222
223VMMDECL(void) CPUMSetHyperDS(PVMCPU pVCpu, RTSEL SelDS)
224{
225 pVCpu->cpum.s.Hyper.ds.Sel = SelDS;
226}
227
228
229VMMDECL(void) CPUMSetHyperES(PVMCPU pVCpu, RTSEL SelES)
230{
231 pVCpu->cpum.s.Hyper.es.Sel = SelES;
232}
233
234
235VMMDECL(void) CPUMSetHyperFS(PVMCPU pVCpu, RTSEL SelFS)
236{
237 pVCpu->cpum.s.Hyper.fs.Sel = SelFS;
238}
239
240
241VMMDECL(void) CPUMSetHyperGS(PVMCPU pVCpu, RTSEL SelGS)
242{
243 pVCpu->cpum.s.Hyper.gs.Sel = SelGS;
244}
245
246
247VMMDECL(void) CPUMSetHyperSS(PVMCPU pVCpu, RTSEL SelSS)
248{
249 pVCpu->cpum.s.Hyper.ss.Sel = SelSS;
250}
251
252
253VMMDECL(void) CPUMSetHyperESP(PVMCPU pVCpu, uint32_t u32ESP)
254{
255 pVCpu->cpum.s.Hyper.esp = u32ESP;
256}
257
258
259VMMDECL(void) CPUMSetHyperEDX(PVMCPU pVCpu, uint32_t u32ESP)
260{
261 pVCpu->cpum.s.Hyper.esp = u32ESP;
262}
263
264
265VMMDECL(int) CPUMSetHyperEFlags(PVMCPU pVCpu, uint32_t Efl)
266{
267 pVCpu->cpum.s.Hyper.eflags.u32 = Efl;
268 return VINF_SUCCESS;
269}
270
271
272VMMDECL(void) CPUMSetHyperEIP(PVMCPU pVCpu, uint32_t u32EIP)
273{
274 pVCpu->cpum.s.Hyper.eip = u32EIP;
275}
276
277
278/**
279 * Used by VMMR3RawRunGC to reinitialize the general raw-mode context registers,
280 * EFLAGS and EIP prior to resuming guest execution.
281 *
282 * All general register not given as a parameter will be set to 0. The EFLAGS
283 * register will be set to sane values for C/C++ code execution with interrupts
284 * disabled and IOPL 0.
285 *
286 * @param pVCpu The current virtual CPU.
287 * @param u32EIP The EIP value.
288 * @param u32ESP The ESP value.
289 * @param u32EAX The EAX value.
290 * @param u32EDX The EDX value.
291 */
292VMM_INT_DECL(void) CPUMSetHyperState(PVMCPU pVCpu, uint32_t u32EIP, uint32_t u32ESP, uint32_t u32EAX, uint32_t u32EDX)
293{
294 pVCpu->cpum.s.Hyper.eip = u32EIP;
295 pVCpu->cpum.s.Hyper.esp = u32ESP;
296 pVCpu->cpum.s.Hyper.eax = u32EAX;
297 pVCpu->cpum.s.Hyper.edx = u32EDX;
298 pVCpu->cpum.s.Hyper.ecx = 0;
299 pVCpu->cpum.s.Hyper.ebx = 0;
300 pVCpu->cpum.s.Hyper.ebp = 0;
301 pVCpu->cpum.s.Hyper.esi = 0;
302 pVCpu->cpum.s.Hyper.edi = 0;
303 pVCpu->cpum.s.Hyper.eflags.u = X86_EFL_1;
304}
305
306
307VMMDECL(void) CPUMSetHyperTR(PVMCPU pVCpu, RTSEL SelTR)
308{
309 pVCpu->cpum.s.Hyper.tr.Sel = SelTR;
310}
311
312
313VMMDECL(void) CPUMSetHyperLDTR(PVMCPU pVCpu, RTSEL SelLDTR)
314{
315 pVCpu->cpum.s.Hyper.ldtr.Sel = SelLDTR;
316}
317
318
319/** @MAYBE_LOAD_DRx
320 * Macro for updating DRx values in raw-mode and ring-0 contexts.
321 */
322#ifdef IN_RING0
323# if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
324# ifndef VBOX_WITH_HYBRID_32BIT_KERNEL
325# define MAYBE_LOAD_DRx(a_pVCpu, a_fnLoad, a_uValue) \
326 do { \
327 if (!CPUMIsGuestInLongModeEx(&(a_pVCpu)->cpum.s.Guest)) \
328 a_fnLoad(a_uValue); \
329 else \
330 (a_pVCpu)->cpum.s.fUseFlags |= CPUM_SYNC_DEBUG_REGS_HYPER; \
331 } while (0)
332# else
333# define MAYBE_LOAD_DRx(a_pVCpu, a_fnLoad, a_uValue) \
334 do { \
335 /** @todo we're not loading the correct guest value here! */ \
336 a_fnLoad(a_uValue); \
337 } while (0)
338# endif
339# else
340# define MAYBE_LOAD_DRx(a_pVCpu, a_fnLoad, a_uValue) \
341 do { \
342 a_fnLoad(a_uValue); \
343 } while (0)
344# endif
345
346#elif defined(IN_RC)
347# define MAYBE_LOAD_DRx(a_pVCpu, a_fnLoad, a_uValue) \
348 do { \
349 if ((a_pVCpu)->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HYPER) \
350 { a_fnLoad(a_uValue); } \
351 } while (0)
352
353#else
354# define MAYBE_LOAD_DRx(a_pVCpu, a_fnLoad, a_uValue) do { } while (0)
355#endif
356
357VMMDECL(void) CPUMSetHyperDR0(PVMCPU pVCpu, RTGCUINTREG uDr0)
358{
359 pVCpu->cpum.s.Hyper.dr[0] = uDr0;
360 MAYBE_LOAD_DRx(pVCpu, ASMSetDR0, uDr0);
361}
362
363
364VMMDECL(void) CPUMSetHyperDR1(PVMCPU pVCpu, RTGCUINTREG uDr1)
365{
366 pVCpu->cpum.s.Hyper.dr[1] = uDr1;
367 MAYBE_LOAD_DRx(pVCpu, ASMSetDR1, uDr1);
368}
369
370
371VMMDECL(void) CPUMSetHyperDR2(PVMCPU pVCpu, RTGCUINTREG uDr2)
372{
373 pVCpu->cpum.s.Hyper.dr[2] = uDr2;
374 MAYBE_LOAD_DRx(pVCpu, ASMSetDR2, uDr2);
375}
376
377
378VMMDECL(void) CPUMSetHyperDR3(PVMCPU pVCpu, RTGCUINTREG uDr3)
379{
380 pVCpu->cpum.s.Hyper.dr[3] = uDr3;
381 MAYBE_LOAD_DRx(pVCpu, ASMSetDR3, uDr3);
382}
383
384
385VMMDECL(void) CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6)
386{
387 pVCpu->cpum.s.Hyper.dr[6] = uDr6;
388}
389
390
391VMMDECL(void) CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7)
392{
393 pVCpu->cpum.s.Hyper.dr[7] = uDr7;
394#ifdef IN_RC
395 MAYBE_LOAD_DRx(pVCpu, ASMSetDR7, uDr7);
396#endif
397}
398
399
400VMMDECL(RTSEL) CPUMGetHyperCS(PVMCPU pVCpu)
401{
402 return pVCpu->cpum.s.Hyper.cs.Sel;
403}
404
405
406VMMDECL(RTSEL) CPUMGetHyperDS(PVMCPU pVCpu)
407{
408 return pVCpu->cpum.s.Hyper.ds.Sel;
409}
410
411
412VMMDECL(RTSEL) CPUMGetHyperES(PVMCPU pVCpu)
413{
414 return pVCpu->cpum.s.Hyper.es.Sel;
415}
416
417
418VMMDECL(RTSEL) CPUMGetHyperFS(PVMCPU pVCpu)
419{
420 return pVCpu->cpum.s.Hyper.fs.Sel;
421}
422
423
424VMMDECL(RTSEL) CPUMGetHyperGS(PVMCPU pVCpu)
425{
426 return pVCpu->cpum.s.Hyper.gs.Sel;
427}
428
429
430VMMDECL(RTSEL) CPUMGetHyperSS(PVMCPU pVCpu)
431{
432 return pVCpu->cpum.s.Hyper.ss.Sel;
433}
434
435
436VMMDECL(uint32_t) CPUMGetHyperEAX(PVMCPU pVCpu)
437{
438 return pVCpu->cpum.s.Hyper.eax;
439}
440
441
442VMMDECL(uint32_t) CPUMGetHyperEBX(PVMCPU pVCpu)
443{
444 return pVCpu->cpum.s.Hyper.ebx;
445}
446
447
448VMMDECL(uint32_t) CPUMGetHyperECX(PVMCPU pVCpu)
449{
450 return pVCpu->cpum.s.Hyper.ecx;
451}
452
453
454VMMDECL(uint32_t) CPUMGetHyperEDX(PVMCPU pVCpu)
455{
456 return pVCpu->cpum.s.Hyper.edx;
457}
458
459
460VMMDECL(uint32_t) CPUMGetHyperESI(PVMCPU pVCpu)
461{
462 return pVCpu->cpum.s.Hyper.esi;
463}
464
465
466VMMDECL(uint32_t) CPUMGetHyperEDI(PVMCPU pVCpu)
467{
468 return pVCpu->cpum.s.Hyper.edi;
469}
470
471
472VMMDECL(uint32_t) CPUMGetHyperEBP(PVMCPU pVCpu)
473{
474 return pVCpu->cpum.s.Hyper.ebp;
475}
476
477
478VMMDECL(uint32_t) CPUMGetHyperESP(PVMCPU pVCpu)
479{
480 return pVCpu->cpum.s.Hyper.esp;
481}
482
483
484VMMDECL(uint32_t) CPUMGetHyperEFlags(PVMCPU pVCpu)
485{
486 return pVCpu->cpum.s.Hyper.eflags.u32;
487}
488
489
490VMMDECL(uint32_t) CPUMGetHyperEIP(PVMCPU pVCpu)
491{
492 return pVCpu->cpum.s.Hyper.eip;
493}
494
495
496VMMDECL(uint64_t) CPUMGetHyperRIP(PVMCPU pVCpu)
497{
498 return pVCpu->cpum.s.Hyper.rip;
499}
500
501
502VMMDECL(uint32_t) CPUMGetHyperIDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
503{
504 if (pcbLimit)
505 *pcbLimit = pVCpu->cpum.s.Hyper.idtr.cbIdt;
506 return pVCpu->cpum.s.Hyper.idtr.pIdt;
507}
508
509
510VMMDECL(uint32_t) CPUMGetHyperGDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
511{
512 if (pcbLimit)
513 *pcbLimit = pVCpu->cpum.s.Hyper.gdtr.cbGdt;
514 return pVCpu->cpum.s.Hyper.gdtr.pGdt;
515}
516
517
518VMMDECL(RTSEL) CPUMGetHyperLDTR(PVMCPU pVCpu)
519{
520 return pVCpu->cpum.s.Hyper.ldtr.Sel;
521}
522
523
524VMMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVMCPU pVCpu)
525{
526 return pVCpu->cpum.s.Hyper.dr[0];
527}
528
529
530VMMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVMCPU pVCpu)
531{
532 return pVCpu->cpum.s.Hyper.dr[1];
533}
534
535
536VMMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVMCPU pVCpu)
537{
538 return pVCpu->cpum.s.Hyper.dr[2];
539}
540
541
542VMMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVMCPU pVCpu)
543{
544 return pVCpu->cpum.s.Hyper.dr[3];
545}
546
547
548VMMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVMCPU pVCpu)
549{
550 return pVCpu->cpum.s.Hyper.dr[6];
551}
552
553
554VMMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVMCPU pVCpu)
555{
556 return pVCpu->cpum.s.Hyper.dr[7];
557}
558
559
560/**
561 * Gets the pointer to the internal CPUMCTXCORE structure.
562 * This is only for reading in order to save a few calls.
563 *
564 * @param pVCpu Handle to the virtual cpu.
565 */
566VMMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVMCPU pVCpu)
567{
568 return CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
569}
570
571
572/**
573 * Queries the pointer to the internal CPUMCTX structure.
574 *
575 * @returns The CPUMCTX pointer.
576 * @param pVCpu Handle to the virtual cpu.
577 */
578VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu)
579{
580 return &pVCpu->cpum.s.Guest;
581}
582
583VMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit)
584{
585#ifdef VBOX_WITH_IEM
586# ifdef VBOX_WITH_RAW_MODE_NOT_R0
587 if (!HMIsEnabled(pVCpu->CTX_SUFF(pVM)))
588 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
589# endif
590#endif
591 pVCpu->cpum.s.Guest.gdtr.cbGdt = cbLimit;
592 pVCpu->cpum.s.Guest.gdtr.pGdt = GCPtrBase;
593 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GDTR;
594 return VINF_SUCCESS; /* formality, consider it void. */
595}
596
597VMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit)
598{
599#ifdef VBOX_WITH_IEM
600# ifdef VBOX_WITH_RAW_MODE_NOT_R0
601 if (!HMIsEnabled(pVCpu->CTX_SUFF(pVM)))
602 VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
603# endif
604#endif
605 pVCpu->cpum.s.Guest.idtr.cbIdt = cbLimit;
606 pVCpu->cpum.s.Guest.idtr.pIdt = GCPtrBase;
607 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_IDTR;
608 return VINF_SUCCESS; /* formality, consider it void. */
609}
610
611VMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr)
612{
613#ifdef VBOX_WITH_IEM
614# ifdef VBOX_WITH_RAW_MODE_NOT_R0
615 if (!HMIsEnabled(pVCpu->CTX_SUFF(pVM)))
616 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
617# endif
618#endif
619 pVCpu->cpum.s.Guest.tr.Sel = tr;
620 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_TR;
621 return VINF_SUCCESS; /* formality, consider it void. */
622}
623
624VMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr)
625{
626#ifdef VBOX_WITH_IEM
627# ifdef VBOX_WITH_RAW_MODE_NOT_R0
628 if ( ( ldtr != 0
629 || pVCpu->cpum.s.Guest.ldtr.Sel != 0)
630 && !HMIsEnabled(pVCpu->CTX_SUFF(pVM)))
631 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
632# endif
633#endif
634 pVCpu->cpum.s.Guest.ldtr.Sel = ldtr;
635 /* The caller will set more hidden bits if it has them. */
636 pVCpu->cpum.s.Guest.ldtr.ValidSel = 0;
637 pVCpu->cpum.s.Guest.ldtr.fFlags = 0;
638 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_LDTR;
639 return VINF_SUCCESS; /* formality, consider it void. */
640}
641
642
643/**
644 * Set the guest CR0.
645 *
646 * When called in GC, the hyper CR0 may be updated if that is
647 * required. The caller only has to take special action if AM,
648 * WP, PG or PE changes.
649 *
650 * @returns VINF_SUCCESS (consider it void).
651 * @param pVCpu Handle to the virtual cpu.
652 * @param cr0 The new CR0 value.
653 */
654VMMDECL(int) CPUMSetGuestCR0(PVMCPU pVCpu, uint64_t cr0)
655{
656#ifdef IN_RC
657 /*
658 * Check if we need to change hypervisor CR0 because
659 * of math stuff.
660 */
661 if ( (cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP))
662 != (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP)))
663 {
664 if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU))
665 {
666 /*
667 * We haven't saved the host FPU state yet, so TS and MT are both set
668 * and EM should be reflecting the guest EM (it always does this).
669 */
670 if ((cr0 & X86_CR0_EM) != (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM))
671 {
672 uint32_t HyperCR0 = ASMGetCR0();
673 AssertMsg((HyperCR0 & (X86_CR0_TS | X86_CR0_MP)) == (X86_CR0_TS | X86_CR0_MP), ("%#x\n", HyperCR0));
674 AssertMsg((HyperCR0 & X86_CR0_EM) == (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM), ("%#x\n", HyperCR0));
675 HyperCR0 &= ~X86_CR0_EM;
676 HyperCR0 |= cr0 & X86_CR0_EM;
677 Log(("CPUM New HyperCR0=%#x\n", HyperCR0));
678 ASMSetCR0(HyperCR0);
679 }
680# ifdef VBOX_STRICT
681 else
682 {
683 uint32_t HyperCR0 = ASMGetCR0();
684 AssertMsg((HyperCR0 & (X86_CR0_TS | X86_CR0_MP)) == (X86_CR0_TS | X86_CR0_MP), ("%#x\n", HyperCR0));
685 AssertMsg((HyperCR0 & X86_CR0_EM) == (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM), ("%#x\n", HyperCR0));
686 }
687# endif
688 }
689 else
690 {
691 /*
692 * Already saved the state, so we're just mirroring
693 * the guest flags.
694 */
695 uint32_t HyperCR0 = ASMGetCR0();
696 AssertMsg( (HyperCR0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP))
697 == (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP)),
698 ("%#x %#x\n", HyperCR0, pVCpu->cpum.s.Guest.cr0));
699 HyperCR0 &= ~(X86_CR0_TS | X86_CR0_EM | X86_CR0_MP);
700 HyperCR0 |= cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP);
701 Log(("CPUM New HyperCR0=%#x\n", HyperCR0));
702 ASMSetCR0(HyperCR0);
703 }
704 }
705#endif /* IN_RC */
706
707 /*
708 * Check for changes causing TLB flushes (for REM).
709 * The caller is responsible for calling PGM when appropriate.
710 */
711 if ( (cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE))
712 != (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)))
713 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
714 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR0;
715
716 /*
717 * Let PGM know if the WP goes from 0 to 1 (netware WP0+RO+US hack)
718 */
719 if (((cr0 ^ pVCpu->cpum.s.Guest.cr0) & X86_CR0_WP) && (cr0 & X86_CR0_WP))
720 PGMCr0WpEnabled(pVCpu);
721
722 pVCpu->cpum.s.Guest.cr0 = cr0 | X86_CR0_ET;
723 return VINF_SUCCESS;
724}
725
726
727VMMDECL(int) CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2)
728{
729 pVCpu->cpum.s.Guest.cr2 = cr2;
730 return VINF_SUCCESS;
731}
732
733
734VMMDECL(int) CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3)
735{
736 pVCpu->cpum.s.Guest.cr3 = cr3;
737 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR3;
738 return VINF_SUCCESS;
739}
740
741
742VMMDECL(int) CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4)
743{
744 if ( (cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE))
745 != (pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE)))
746 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
747 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR4;
748 if (!CPUMSupportsFXSR(pVCpu->CTX_SUFF(pVM)))
749 cr4 &= ~X86_CR4_OSFSXR;
750 pVCpu->cpum.s.Guest.cr4 = cr4;
751 return VINF_SUCCESS;
752}
753
754
755VMMDECL(int) CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags)
756{
757 pVCpu->cpum.s.Guest.eflags.u32 = eflags;
758 return VINF_SUCCESS;
759}
760
761
762VMMDECL(int) CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip)
763{
764 pVCpu->cpum.s.Guest.eip = eip;
765 return VINF_SUCCESS;
766}
767
768
769VMMDECL(int) CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax)
770{
771 pVCpu->cpum.s.Guest.eax = eax;
772 return VINF_SUCCESS;
773}
774
775
776VMMDECL(int) CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx)
777{
778 pVCpu->cpum.s.Guest.ebx = ebx;
779 return VINF_SUCCESS;
780}
781
782
783VMMDECL(int) CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx)
784{
785 pVCpu->cpum.s.Guest.ecx = ecx;
786 return VINF_SUCCESS;
787}
788
789
790VMMDECL(int) CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx)
791{
792 pVCpu->cpum.s.Guest.edx = edx;
793 return VINF_SUCCESS;
794}
795
796
797VMMDECL(int) CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp)
798{
799 pVCpu->cpum.s.Guest.esp = esp;
800 return VINF_SUCCESS;
801}
802
803
804VMMDECL(int) CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp)
805{
806 pVCpu->cpum.s.Guest.ebp = ebp;
807 return VINF_SUCCESS;
808}
809
810
811VMMDECL(int) CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi)
812{
813 pVCpu->cpum.s.Guest.esi = esi;
814 return VINF_SUCCESS;
815}
816
817
818VMMDECL(int) CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi)
819{
820 pVCpu->cpum.s.Guest.edi = edi;
821 return VINF_SUCCESS;
822}
823
824
825VMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss)
826{
827 pVCpu->cpum.s.Guest.ss.Sel = ss;
828 return VINF_SUCCESS;
829}
830
831
832VMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs)
833{
834 pVCpu->cpum.s.Guest.cs.Sel = cs;
835 return VINF_SUCCESS;
836}
837
838
839VMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds)
840{
841 pVCpu->cpum.s.Guest.ds.Sel = ds;
842 return VINF_SUCCESS;
843}
844
845
846VMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es)
847{
848 pVCpu->cpum.s.Guest.es.Sel = es;
849 return VINF_SUCCESS;
850}
851
852
853VMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs)
854{
855 pVCpu->cpum.s.Guest.fs.Sel = fs;
856 return VINF_SUCCESS;
857}
858
859
860VMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs)
861{
862 pVCpu->cpum.s.Guest.gs.Sel = gs;
863 return VINF_SUCCESS;
864}
865
866
867VMMDECL(void) CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val)
868{
869 pVCpu->cpum.s.Guest.msrEFER = val;
870}
871
872
873/**
874 * Query an MSR.
875 *
876 * The caller is responsible for checking privilege if the call is the result
877 * of a RDMSR instruction. We'll do the rest.
878 *
879 * @retval VINF_SUCCESS on success.
880 * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR), the caller is
881 * expected to take the appropriate actions. @a *puValue is set to 0.
882 * @param pVCpu Pointer to the VMCPU.
883 * @param idMsr The MSR.
884 * @param puValue Where to return the value.
885 *
886 * @remarks This will always return the right values, even when we're in the
887 * recompiler.
888 */
889VMMDECL(int) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue)
890{
891 /*
892 * If we don't indicate MSR support in the CPUID feature bits, indicate
893 * that a #GP(0) should be raised.
894 */
895 if (!(pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_MSR))
896 {
897 *puValue = 0;
898 return VERR_CPUM_RAISE_GP_0; /** @todo isn't \#UD more correct if not supported? */
899 }
900
901 int rc = VINF_SUCCESS;
902 uint8_t const u8Multiplier = 4;
903 switch (idMsr)
904 {
905 case MSR_IA32_TSC:
906 *puValue = TMCpuTickGet(pVCpu);
907 break;
908
909 case MSR_IA32_APICBASE:
910 {
911 PVM pVM = pVCpu->CTX_SUFF(pVM);
912 if ( ( pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1 /* APIC Std feature */
913 && (pVM->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_APIC))
914 || ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001 /* APIC Ext feature (AMD) */
915 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD
916 && (pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_AMD_FEATURE_EDX_APIC))
917 || ( pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1 /* x2APIC */
918 && (pVM->cpum.s.aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_X2APIC)))
919 {
920 *puValue = pVCpu->cpum.s.Guest.msrApicBase;
921 }
922 else
923 {
924 *puValue = 0;
925 rc = VERR_CPUM_RAISE_GP_0;
926 }
927 break;
928 }
929
930 case MSR_IA32_CR_PAT:
931 *puValue = pVCpu->cpum.s.Guest.msrPAT;
932 break;
933
934 case MSR_IA32_SYSENTER_CS:
935 *puValue = pVCpu->cpum.s.Guest.SysEnter.cs;
936 break;
937
938 case MSR_IA32_SYSENTER_EIP:
939 *puValue = pVCpu->cpum.s.Guest.SysEnter.eip;
940 break;
941
942 case MSR_IA32_SYSENTER_ESP:
943 *puValue = pVCpu->cpum.s.Guest.SysEnter.esp;
944 break;
945
946 case MSR_IA32_MTRR_CAP:
947 {
948 /* This is currently a bit weird. :-) */
949 uint8_t const cVariableRangeRegs = 0;
950 bool const fSystemManagementRangeRegisters = false;
951 bool const fFixedRangeRegisters = false;
952 bool const fWriteCombiningType = false;
953 *puValue = cVariableRangeRegs
954 | (fFixedRangeRegisters ? RT_BIT_64(8) : 0)
955 | (fWriteCombiningType ? RT_BIT_64(10) : 0)
956 | (fSystemManagementRangeRegisters ? RT_BIT_64(11) : 0);
957 break;
958 }
959
960 case MSR_IA32_MTRR_DEF_TYPE:
961 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType;
962 break;
963
964 case IA32_MTRR_FIX64K_00000:
965 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix64K_00000;
966 break;
967 case IA32_MTRR_FIX16K_80000:
968 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_80000;
969 break;
970 case IA32_MTRR_FIX16K_A0000:
971 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_A0000;
972 break;
973 case IA32_MTRR_FIX4K_C0000:
974 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C0000;
975 break;
976 case IA32_MTRR_FIX4K_C8000:
977 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C8000;
978 break;
979 case IA32_MTRR_FIX4K_D0000:
980 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D0000;
981 break;
982 case IA32_MTRR_FIX4K_D8000:
983 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D8000;
984 break;
985 case IA32_MTRR_FIX4K_E0000:
986 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E0000;
987 break;
988 case IA32_MTRR_FIX4K_E8000:
989 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E8000;
990 break;
991 case IA32_MTRR_FIX4K_F0000:
992 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F0000;
993 break;
994 case IA32_MTRR_FIX4K_F8000:
995 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F8000;
996 break;
997
998 case MSR_K6_EFER:
999 *puValue = pVCpu->cpum.s.Guest.msrEFER;
1000 break;
1001
1002 case MSR_K8_SF_MASK:
1003 *puValue = pVCpu->cpum.s.Guest.msrSFMASK;
1004 break;
1005
1006 case MSR_K6_STAR:
1007 *puValue = pVCpu->cpum.s.Guest.msrSTAR;
1008 break;
1009
1010 case MSR_K8_LSTAR:
1011 *puValue = pVCpu->cpum.s.Guest.msrLSTAR;
1012 break;
1013
1014 case MSR_K8_CSTAR:
1015 *puValue = pVCpu->cpum.s.Guest.msrCSTAR;
1016 break;
1017
1018 case MSR_K8_FS_BASE:
1019 *puValue = pVCpu->cpum.s.Guest.fs.u64Base;
1020 break;
1021
1022 case MSR_K8_GS_BASE:
1023 *puValue = pVCpu->cpum.s.Guest.gs.u64Base;
1024 break;
1025
1026 case MSR_K8_KERNEL_GS_BASE:
1027 *puValue = pVCpu->cpum.s.Guest.msrKERNELGSBASE;
1028 break;
1029
1030 case MSR_K8_TSC_AUX:
1031 *puValue = pVCpu->cpum.s.GuestMsrs.msr.TscAux;
1032 break;
1033
1034 case MSR_IA32_PERF_STATUS:
1035 /** @todo could really be not exactly correct, maybe use host's values */
1036 *puValue = UINT64_C(1000) /* TSC increment by tick */
1037 | ((uint64_t)u8Multiplier << 24) /* CPU multiplier (aka bus ratio) min */
1038 | ((uint64_t)u8Multiplier << 40) /* CPU multiplier (aka bus ratio) max */;
1039 break;
1040
1041 case MSR_IA32_FSB_CLOCK_STS:
1042 /*
1043 * Encoded as:
1044 * 0 - 266
1045 * 1 - 133
1046 * 2 - 200
1047 * 3 - return 166
1048 * 5 - return 100
1049 */
1050 *puValue = (2 << 4);
1051 break;
1052
1053 case MSR_IA32_PLATFORM_INFO:
1054 *puValue = (u8Multiplier << 8) /* Flex ratio max */
1055 | ((uint64_t)u8Multiplier << 40) /* Flex ratio min */;
1056 break;
1057
1058 case MSR_IA32_THERM_STATUS:
1059 /* CPU temperature relative to TCC, to actually activate, CPUID leaf 6 EAX[0] must be set */
1060 *puValue = RT_BIT(31) /* validity bit */
1061 | (UINT64_C(20) << 16) /* degrees till TCC */;
1062 break;
1063
1064 case MSR_IA32_MISC_ENABLE:
1065#if 0
1066 /* Needs to be tested more before enabling. */
1067 *puValue = pVCpu->cpum.s.GuestMsr.msr.miscEnable;
1068#else
1069 /* Currenty we don't allow guests to modify enable MSRs. */
1070 *puValue = MSR_IA32_MISC_ENABLE_FAST_STRINGS /* by default */;
1071
1072 if ((pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR) != 0)
1073
1074 *puValue |= MSR_IA32_MISC_ENABLE_MONITOR /* if mwait/monitor available */;
1075 /** @todo: add more cpuid-controlled features this way. */
1076#endif
1077 break;
1078
1079#if 0 /*def IN_RING0 */
1080 case MSR_IA32_PLATFORM_ID:
1081 case MSR_IA32_BIOS_SIGN_ID:
1082 if (CPUMGetCPUVendor(pVM) == CPUMCPUVENDOR_INTEL)
1083 {
1084 /* Available since the P6 family. VT-x implies that this feature is present. */
1085 if (idMsr == MSR_IA32_PLATFORM_ID)
1086 *puValue = ASMRdMsr(MSR_IA32_PLATFORM_ID);
1087 else if (idMsr == MSR_IA32_BIOS_SIGN_ID)
1088 *puValue = ASMRdMsr(MSR_IA32_BIOS_SIGN_ID);
1089 break;
1090 }
1091 /* no break */
1092#endif
1093
1094 /*
1095 * Intel specifics MSRs:
1096 */
1097 case MSR_IA32_PLATFORM_ID: /* fam/mod >= 6_01 */
1098 case MSR_IA32_BIOS_SIGN_ID: /* fam/mod >= 6_01 */
1099 /*case MSR_IA32_BIOS_UPDT_TRIG: - write-only? */
1100 case MSR_IA32_MCP_CAP: /* fam/mod >= 6_01 */
1101 /*case MSR_IA32_MCP_STATUS: - indicated as not present in CAP */
1102 /*case MSR_IA32_MCP_CTRL: - indicated as not present in CAP */
1103 case MSR_IA32_MC0_CTL:
1104 case MSR_IA32_MC0_STATUS:
1105 *puValue = 0;
1106 if (CPUMGetGuestCpuVendor(pVCpu->CTX_SUFF(pVM)) != CPUMCPUVENDOR_INTEL)
1107 {
1108 Log(("MSR %#x is Intel, the virtual CPU isn't an Intel one -> #GP\n", idMsr));
1109 rc = VERR_CPUM_RAISE_GP_0;
1110 }
1111 break;
1112
1113
1114 /*
1115 * AMD specific MSRs:
1116 */
1117 case MSR_K8_SYSCFG: /** @todo can be written, but we ignore that for now. */
1118 *puValue = 0;
1119 if (CPUMGetGuestCpuVendor(pVCpu->CTX_SUFF(pVM)) != CPUMCPUVENDOR_AMD)
1120 {
1121 Log(("MSR %#x is AMD, the virtual CPU isn't an Intel one -> #GP\n", idMsr));
1122 return VERR_CPUM_RAISE_GP_0;
1123 }
1124 /* ignored */
1125 break;
1126
1127 default:
1128 /*
1129 * Hand the X2APIC range to PDM and the APIC.
1130 */
1131 if ( idMsr >= MSR_IA32_X2APIC_START
1132 && idMsr <= MSR_IA32_X2APIC_END)
1133 {
1134 rc = PDMApicReadMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, puValue);
1135 if (RT_SUCCESS(rc))
1136 rc = VINF_SUCCESS;
1137 else
1138 {
1139 *puValue = 0;
1140 rc = VERR_CPUM_RAISE_GP_0;
1141 }
1142 }
1143 else
1144 {
1145 *puValue = 0;
1146 rc = VERR_CPUM_RAISE_GP_0;
1147 }
1148 break;
1149 }
1150
1151 return rc;
1152}
1153
1154
1155/**
1156 * Sets the MSR.
1157 *
1158 * The caller is responsible for checking privilege if the call is the result
1159 * of a WRMSR instruction. We'll do the rest.
1160 *
1161 * @retval VINF_SUCCESS on success.
1162 * @retval VERR_CPUM_RAISE_GP_0 on failure, the caller is expected to take the
1163 * appropriate actions.
1164 *
1165 * @param pVCpu Pointer to the VMCPU.
1166 * @param idMsr The MSR id.
1167 * @param uValue The value to set.
1168 *
1169 * @remarks Everyone changing MSR values, including the recompiler, shall do it
1170 * by calling this method. This makes sure we have current values and
1171 * that we trigger all the right actions when something changes.
1172 */
1173VMMDECL(int) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue)
1174{
1175 /*
1176 * If we don't indicate MSR support in the CPUID feature bits, indicate
1177 * that a #GP(0) should be raised.
1178 */
1179 if (!(pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_MSR))
1180 return VERR_CPUM_RAISE_GP_0; /** @todo isn't \#UD more correct if not supported? */
1181
1182 int rc = VINF_SUCCESS;
1183 switch (idMsr)
1184 {
1185 case MSR_IA32_MISC_ENABLE:
1186 pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = uValue;
1187 break;
1188
1189 case MSR_IA32_TSC:
1190 TMCpuTickSet(pVCpu->CTX_SUFF(pVM), pVCpu, uValue);
1191 break;
1192
1193 case MSR_IA32_APICBASE:
1194 rc = PDMApicSetBase(pVCpu, uValue);
1195 if (rc != VINF_SUCCESS)
1196 rc = VERR_CPUM_RAISE_GP_0;
1197 break;
1198
1199 case MSR_IA32_CR_PAT:
1200 pVCpu->cpum.s.Guest.msrPAT = uValue;
1201 break;
1202
1203 case MSR_IA32_SYSENTER_CS:
1204 pVCpu->cpum.s.Guest.SysEnter.cs = uValue & 0xffff; /* 16 bits selector */
1205 break;
1206
1207 case MSR_IA32_SYSENTER_EIP:
1208 pVCpu->cpum.s.Guest.SysEnter.eip = uValue;
1209 break;
1210
1211 case MSR_IA32_SYSENTER_ESP:
1212 pVCpu->cpum.s.Guest.SysEnter.esp = uValue;
1213 break;
1214
1215 case MSR_IA32_MTRR_CAP:
1216 return VERR_CPUM_RAISE_GP_0;
1217
1218 case MSR_IA32_MTRR_DEF_TYPE:
1219 if ( (uValue & UINT64_C(0xfffffffffffff300))
1220 || ( (uValue & 0xff) != 0
1221 && (uValue & 0xff) != 1
1222 && (uValue & 0xff) != 4
1223 && (uValue & 0xff) != 5
1224 && (uValue & 0xff) != 6) )
1225 {
1226 Log(("MSR_IA32_MTRR_DEF_TYPE: #GP(0) - writing reserved value (%#llx)\n", uValue));
1227 return VERR_CPUM_RAISE_GP_0;
1228 }
1229 pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType = uValue;
1230 break;
1231
1232 case IA32_MTRR_FIX64K_00000:
1233 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix64K_00000 = uValue;
1234 break;
1235 case IA32_MTRR_FIX16K_80000:
1236 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_80000 = uValue;
1237 break;
1238 case IA32_MTRR_FIX16K_A0000:
1239 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_A0000 = uValue;
1240 break;
1241 case IA32_MTRR_FIX4K_C0000:
1242 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C0000 = uValue;
1243 break;
1244 case IA32_MTRR_FIX4K_C8000:
1245 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C8000 = uValue;
1246 break;
1247 case IA32_MTRR_FIX4K_D0000:
1248 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D0000 = uValue;
1249 break;
1250 case IA32_MTRR_FIX4K_D8000:
1251 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D8000 = uValue;
1252 break;
1253 case IA32_MTRR_FIX4K_E0000:
1254 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E0000 = uValue;
1255 break;
1256 case IA32_MTRR_FIX4K_E8000:
1257 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E8000 = uValue;
1258 break;
1259 case IA32_MTRR_FIX4K_F0000:
1260 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F0000 = uValue;
1261 break;
1262 case IA32_MTRR_FIX4K_F8000:
1263 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F8000 = uValue;
1264 break;
1265
1266 /*
1267 * AMD64 MSRs.
1268 */
1269 case MSR_K6_EFER:
1270 {
1271 PVM pVM = pVCpu->CTX_SUFF(pVM);
1272 uint64_t const uOldEFER = pVCpu->cpum.s.Guest.msrEFER;
1273 uint32_t const fExtFeatures = pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1274 ? pVM->cpum.s.aGuestCpuIdExt[1].edx
1275 : 0;
1276 uint64_t fMask = 0;
1277
1278 /* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
1279 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_NX)
1280 fMask |= MSR_K6_EFER_NXE;
1281 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
1282 fMask |= MSR_K6_EFER_LME;
1283 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
1284 fMask |= MSR_K6_EFER_SCE;
1285 if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1286 fMask |= MSR_K6_EFER_FFXSR;
1287
1288 /* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if
1289 paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1290 if ( (uOldEFER & MSR_K6_EFER_LME) != (uValue & fMask & MSR_K6_EFER_LME)
1291 && (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG))
1292 {
1293 Log(("Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
1294 return VERR_CPUM_RAISE_GP_0;
1295 }
1296
1297 /* There are a few more: e.g. MSR_K6_EFER_LMSLE */
1298 AssertMsg(!(uValue & ~(MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA /* ignored anyway */ | MSR_K6_EFER_SCE | MSR_K6_EFER_FFXSR)),
1299 ("Unexpected value %RX64\n", uValue));
1300 pVCpu->cpum.s.Guest.msrEFER = (uOldEFER & ~fMask) | (uValue & fMask);
1301
1302 /* AMD64 Architecture Programmer's Manual: 15.15 TLB Control; flush the TLB
1303 if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
1304 if ( (uOldEFER & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA))
1305 != (pVCpu->cpum.s.Guest.msrEFER & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA)))
1306 {
1307 /// @todo PGMFlushTLB(pVCpu, cr3, true /*fGlobal*/);
1308 HMFlushTLB(pVCpu);
1309
1310 /* Notify PGM about NXE changes. */
1311 if ( (uOldEFER & MSR_K6_EFER_NXE)
1312 != (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE))
1313 PGMNotifyNxeChanged(pVCpu, !(uOldEFER & MSR_K6_EFER_NXE));
1314 }
1315 break;
1316 }
1317
1318 case MSR_K8_SF_MASK:
1319 pVCpu->cpum.s.Guest.msrSFMASK = uValue;
1320 break;
1321
1322 case MSR_K6_STAR:
1323 pVCpu->cpum.s.Guest.msrSTAR = uValue;
1324 break;
1325
1326 case MSR_K8_LSTAR:
1327 pVCpu->cpum.s.Guest.msrLSTAR = uValue;
1328 break;
1329
1330 case MSR_K8_CSTAR:
1331 pVCpu->cpum.s.Guest.msrCSTAR = uValue;
1332 break;
1333
1334 case MSR_K8_FS_BASE:
1335 pVCpu->cpum.s.Guest.fs.u64Base = uValue;
1336 break;
1337
1338 case MSR_K8_GS_BASE:
1339 pVCpu->cpum.s.Guest.gs.u64Base = uValue;
1340 break;
1341
1342 case MSR_K8_KERNEL_GS_BASE:
1343 pVCpu->cpum.s.Guest.msrKERNELGSBASE = uValue;
1344 break;
1345
1346 case MSR_K8_TSC_AUX:
1347 pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
1348 break;
1349
1350
1351 /*
1352 * Intel specifics MSRs:
1353 */
1354 /*case MSR_IA32_PLATFORM_ID: - read-only */
1355 case MSR_IA32_BIOS_SIGN_ID: /* fam/mod >= 6_01 */
1356 case MSR_IA32_BIOS_UPDT_TRIG: /* fam/mod >= 6_01 */
1357 /*case MSR_IA32_MCP_CAP: - read-only */
1358 /*case MSR_IA32_MCP_STATUS: - read-only */
1359 /*case MSR_IA32_MCP_CTRL: - indicated as not present in CAP */
1360 /*case MSR_IA32_MC0_CTL: - read-only? */
1361 /*case MSR_IA32_MC0_STATUS: - read-only? */
1362 if (CPUMGetGuestCpuVendor(pVCpu->CTX_SUFF(pVM)) != CPUMCPUVENDOR_INTEL)
1363 {
1364 Log(("MSR %#x is Intel, the virtual CPU isn't an Intel one -> #GP\n", idMsr));
1365 return VERR_CPUM_RAISE_GP_0;
1366 }
1367 /* ignored */
1368 break;
1369
1370 /*
1371 * AMD specific MSRs:
1372 */
1373 case MSR_K8_SYSCFG: /** @todo can be written, but we ignore that for now. */
1374 if (CPUMGetGuestCpuVendor(pVCpu->CTX_SUFF(pVM)) != CPUMCPUVENDOR_AMD)
1375 {
1376 Log(("MSR %#x is AMD, the virtual CPU isn't an Intel one -> #GP\n", idMsr));
1377 return VERR_CPUM_RAISE_GP_0;
1378 }
1379 /* ignored */
1380 break;
1381
1382
1383 default:
1384 /*
1385 * Hand the X2APIC range to PDM and the APIC.
1386 */
1387 if ( idMsr >= MSR_IA32_X2APIC_START
1388 && idMsr <= MSR_IA32_X2APIC_END)
1389 {
1390 rc = PDMApicWriteMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, uValue);
1391 if (rc != VINF_SUCCESS)
1392 rc = VERR_CPUM_RAISE_GP_0;
1393 }
1394 else
1395 {
1396 /* We should actually trigger a #GP here, but don't as that might cause more trouble. */
1397 /** @todo rc = VERR_CPUM_RAISE_GP_0 */
1398 Log(("CPUMSetGuestMsr: Unknown MSR %#x attempted set to %#llx\n", idMsr, uValue));
1399 }
1400 break;
1401 }
1402 return rc;
1403}
1404
1405
1406VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
1407{
1408 if (pcbLimit)
1409 *pcbLimit = pVCpu->cpum.s.Guest.idtr.cbIdt;
1410 return pVCpu->cpum.s.Guest.idtr.pIdt;
1411}
1412
1413
1414VMMDECL(RTSEL) CPUMGetGuestTR(PVMCPU pVCpu, PCPUMSELREGHID pHidden)
1415{
1416 if (pHidden)
1417 *pHidden = pVCpu->cpum.s.Guest.tr;
1418 return pVCpu->cpum.s.Guest.tr.Sel;
1419}
1420
1421
1422VMMDECL(RTSEL) CPUMGetGuestCS(PVMCPU pVCpu)
1423{
1424 return pVCpu->cpum.s.Guest.cs.Sel;
1425}
1426
1427
1428VMMDECL(RTSEL) CPUMGetGuestDS(PVMCPU pVCpu)
1429{
1430 return pVCpu->cpum.s.Guest.ds.Sel;
1431}
1432
1433
1434VMMDECL(RTSEL) CPUMGetGuestES(PVMCPU pVCpu)
1435{
1436 return pVCpu->cpum.s.Guest.es.Sel;
1437}
1438
1439
1440VMMDECL(RTSEL) CPUMGetGuestFS(PVMCPU pVCpu)
1441{
1442 return pVCpu->cpum.s.Guest.fs.Sel;
1443}
1444
1445
1446VMMDECL(RTSEL) CPUMGetGuestGS(PVMCPU pVCpu)
1447{
1448 return pVCpu->cpum.s.Guest.gs.Sel;
1449}
1450
1451
1452VMMDECL(RTSEL) CPUMGetGuestSS(PVMCPU pVCpu)
1453{
1454 return pVCpu->cpum.s.Guest.ss.Sel;
1455}
1456
1457
1458VMMDECL(RTSEL) CPUMGetGuestLDTR(PVMCPU pVCpu)
1459{
1460 return pVCpu->cpum.s.Guest.ldtr.Sel;
1461}
1462
1463
1464VMMDECL(RTSEL) CPUMGetGuestLdtrEx(PVMCPU pVCpu, uint64_t *pGCPtrBase, uint32_t *pcbLimit)
1465{
1466 *pGCPtrBase = pVCpu->cpum.s.Guest.ldtr.u64Base;
1467 *pcbLimit = pVCpu->cpum.s.Guest.ldtr.u32Limit;
1468 return pVCpu->cpum.s.Guest.ldtr.Sel;
1469}
1470
1471
1472VMMDECL(uint64_t) CPUMGetGuestCR0(PVMCPU pVCpu)
1473{
1474 return pVCpu->cpum.s.Guest.cr0;
1475}
1476
1477
1478VMMDECL(uint64_t) CPUMGetGuestCR2(PVMCPU pVCpu)
1479{
1480 return pVCpu->cpum.s.Guest.cr2;
1481}
1482
1483
1484VMMDECL(uint64_t) CPUMGetGuestCR3(PVMCPU pVCpu)
1485{
1486 return pVCpu->cpum.s.Guest.cr3;
1487}
1488
1489
1490VMMDECL(uint64_t) CPUMGetGuestCR4(PVMCPU pVCpu)
1491{
1492 return pVCpu->cpum.s.Guest.cr4;
1493}
1494
1495
1496VMMDECL(uint64_t) CPUMGetGuestCR8(PVMCPU pVCpu)
1497{
1498 uint64_t u64;
1499 int rc = CPUMGetGuestCRx(pVCpu, DISCREG_CR8, &u64);
1500 if (RT_FAILURE(rc))
1501 u64 = 0;
1502 return u64;
1503}
1504
1505
1506VMMDECL(void) CPUMGetGuestGDTR(PVMCPU pVCpu, PVBOXGDTR pGDTR)
1507{
1508 *pGDTR = pVCpu->cpum.s.Guest.gdtr;
1509}
1510
1511
1512VMMDECL(uint32_t) CPUMGetGuestEIP(PVMCPU pVCpu)
1513{
1514 return pVCpu->cpum.s.Guest.eip;
1515}
1516
1517
1518VMMDECL(uint64_t) CPUMGetGuestRIP(PVMCPU pVCpu)
1519{
1520 return pVCpu->cpum.s.Guest.rip;
1521}
1522
1523
1524VMMDECL(uint32_t) CPUMGetGuestEAX(PVMCPU pVCpu)
1525{
1526 return pVCpu->cpum.s.Guest.eax;
1527}
1528
1529
1530VMMDECL(uint32_t) CPUMGetGuestEBX(PVMCPU pVCpu)
1531{
1532 return pVCpu->cpum.s.Guest.ebx;
1533}
1534
1535
1536VMMDECL(uint32_t) CPUMGetGuestECX(PVMCPU pVCpu)
1537{
1538 return pVCpu->cpum.s.Guest.ecx;
1539}
1540
1541
1542VMMDECL(uint32_t) CPUMGetGuestEDX(PVMCPU pVCpu)
1543{
1544 return pVCpu->cpum.s.Guest.edx;
1545}
1546
1547
1548VMMDECL(uint32_t) CPUMGetGuestESI(PVMCPU pVCpu)
1549{
1550 return pVCpu->cpum.s.Guest.esi;
1551}
1552
1553
1554VMMDECL(uint32_t) CPUMGetGuestEDI(PVMCPU pVCpu)
1555{
1556 return pVCpu->cpum.s.Guest.edi;
1557}
1558
1559
1560VMMDECL(uint32_t) CPUMGetGuestESP(PVMCPU pVCpu)
1561{
1562 return pVCpu->cpum.s.Guest.esp;
1563}
1564
1565
1566VMMDECL(uint32_t) CPUMGetGuestEBP(PVMCPU pVCpu)
1567{
1568 return pVCpu->cpum.s.Guest.ebp;
1569}
1570
1571
1572VMMDECL(uint32_t) CPUMGetGuestEFlags(PVMCPU pVCpu)
1573{
1574 return pVCpu->cpum.s.Guest.eflags.u32;
1575}
1576
1577
1578VMMDECL(int) CPUMGetGuestCRx(PVMCPU pVCpu, unsigned iReg, uint64_t *pValue)
1579{
1580 switch (iReg)
1581 {
1582 case DISCREG_CR0:
1583 *pValue = pVCpu->cpum.s.Guest.cr0;
1584 break;
1585
1586 case DISCREG_CR2:
1587 *pValue = pVCpu->cpum.s.Guest.cr2;
1588 break;
1589
1590 case DISCREG_CR3:
1591 *pValue = pVCpu->cpum.s.Guest.cr3;
1592 break;
1593
1594 case DISCREG_CR4:
1595 *pValue = pVCpu->cpum.s.Guest.cr4;
1596 break;
1597
1598 case DISCREG_CR8:
1599 {
1600 uint8_t u8Tpr;
1601 int rc = PDMApicGetTPR(pVCpu, &u8Tpr, NULL /* pfPending */, NULL /* pu8PendingIrq */);
1602 if (RT_FAILURE(rc))
1603 {
1604 AssertMsg(rc == VERR_PDM_NO_APIC_INSTANCE, ("%Rrc\n", rc));
1605 *pValue = 0;
1606 return rc;
1607 }
1608 *pValue = u8Tpr >> 4; /* bits 7-4 contain the task priority that go in cr8, bits 3-0*/
1609 break;
1610 }
1611
1612 default:
1613 return VERR_INVALID_PARAMETER;
1614 }
1615 return VINF_SUCCESS;
1616}
1617
1618
1619VMMDECL(uint64_t) CPUMGetGuestDR0(PVMCPU pVCpu)
1620{
1621 return pVCpu->cpum.s.Guest.dr[0];
1622}
1623
1624
1625VMMDECL(uint64_t) CPUMGetGuestDR1(PVMCPU pVCpu)
1626{
1627 return pVCpu->cpum.s.Guest.dr[1];
1628}
1629
1630
1631VMMDECL(uint64_t) CPUMGetGuestDR2(PVMCPU pVCpu)
1632{
1633 return pVCpu->cpum.s.Guest.dr[2];
1634}
1635
1636
1637VMMDECL(uint64_t) CPUMGetGuestDR3(PVMCPU pVCpu)
1638{
1639 return pVCpu->cpum.s.Guest.dr[3];
1640}
1641
1642
1643VMMDECL(uint64_t) CPUMGetGuestDR6(PVMCPU pVCpu)
1644{
1645 return pVCpu->cpum.s.Guest.dr[6];
1646}
1647
1648
1649VMMDECL(uint64_t) CPUMGetGuestDR7(PVMCPU pVCpu)
1650{
1651 return pVCpu->cpum.s.Guest.dr[7];
1652}
1653
1654
1655VMMDECL(int) CPUMGetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t *pValue)
1656{
1657 AssertReturn(iReg <= DISDREG_DR7, VERR_INVALID_PARAMETER);
1658 /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
1659 if (iReg == 4 || iReg == 5)
1660 iReg += 2;
1661 *pValue = pVCpu->cpum.s.Guest.dr[iReg];
1662 return VINF_SUCCESS;
1663}
1664
1665
1666VMMDECL(uint64_t) CPUMGetGuestEFER(PVMCPU pVCpu)
1667{
1668 return pVCpu->cpum.s.Guest.msrEFER;
1669}
1670
1671
1672/**
1673 * Gets a CPUID leaf.
1674 *
1675 * @param pVCpu Pointer to the VMCPU.
1676 * @param iLeaf The CPUID leaf to get.
1677 * @param pEax Where to store the EAX value.
1678 * @param pEbx Where to store the EBX value.
1679 * @param pEcx Where to store the ECX value.
1680 * @param pEdx Where to store the EDX value.
1681 */
1682VMMDECL(void) CPUMGetGuestCpuId(PVMCPU pVCpu, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx)
1683{
1684 PVM pVM = pVCpu->CTX_SUFF(pVM);
1685
1686 PCCPUMCPUID pCpuId;
1687 if (iLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
1688 pCpuId = &pVM->cpum.s.aGuestCpuIdStd[iLeaf];
1689 else if (iLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
1690 pCpuId = &pVM->cpum.s.aGuestCpuIdExt[iLeaf - UINT32_C(0x80000000)];
1691 else if ( iLeaf - UINT32_C(0x40000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdHyper)
1692 && (pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_HVP))
1693 pCpuId = &pVM->cpum.s.aGuestCpuIdHyper[iLeaf - UINT32_C(0x40000000)]; /* Only report if HVP bit set. */
1694 else if (iLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
1695 pCpuId = &pVM->cpum.s.aGuestCpuIdCentaur[iLeaf - UINT32_C(0xc0000000)];
1696 else
1697 pCpuId = &pVM->cpum.s.GuestCpuIdDef;
1698
1699 uint32_t cCurrentCacheIndex = *pEcx;
1700
1701 *pEax = pCpuId->eax;
1702 *pEbx = pCpuId->ebx;
1703 *pEcx = pCpuId->ecx;
1704 *pEdx = pCpuId->edx;
1705
1706 if ( iLeaf == 1)
1707 {
1708 /* Bits 31-24: Initial APIC ID */
1709 Assert(pVCpu->idCpu <= 255);
1710 *pEbx |= (pVCpu->idCpu << 24);
1711 }
1712
1713 if ( iLeaf == 4
1714 && cCurrentCacheIndex < 3
1715 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
1716 {
1717 uint32_t type, level, sharing, linesize,
1718 partitions, associativity, sets, cores;
1719
1720 /* For type: 1 - data cache, 2 - i-cache, 3 - unified */
1721 partitions = 1;
1722 /* Those are only to shut up compiler, as they will always
1723 get overwritten, and compiler should be able to figure that out */
1724 sets = associativity = sharing = level = 1;
1725 cores = pVM->cCpus > 32 ? 32 : pVM->cCpus;
1726 switch (cCurrentCacheIndex)
1727 {
1728 case 0:
1729 type = 1;
1730 level = 1;
1731 sharing = 1;
1732 linesize = 64;
1733 associativity = 8;
1734 sets = 64;
1735 break;
1736 case 1:
1737 level = 1;
1738 type = 2;
1739 sharing = 1;
1740 linesize = 64;
1741 associativity = 8;
1742 sets = 64;
1743 break;
1744 default: /* shut up gcc.*/
1745 AssertFailed();
1746 case 2:
1747 level = 2;
1748 type = 3;
1749 sharing = cores; /* our L2 cache is modelled as shared between all cores */
1750 linesize = 64;
1751 associativity = 24;
1752 sets = 4096;
1753 break;
1754 }
1755
1756 *pEax |= ((cores - 1) << 26) |
1757 ((sharing - 1) << 14) |
1758 (level << 5) |
1759 1;
1760 *pEbx = (linesize - 1) |
1761 ((partitions - 1) << 12) |
1762 ((associativity - 1) << 22); /* -1 encoding */
1763 *pEcx = sets - 1;
1764 }
1765
1766 Log2(("CPUMGetGuestCpuId: iLeaf=%#010x %RX32 %RX32 %RX32 %RX32\n", iLeaf, *pEax, *pEbx, *pEcx, *pEdx));
1767}
1768
1769/**
1770 * Gets a number of standard CPUID leafs.
1771 *
1772 * @returns Number of leafs.
1773 * @param pVM Pointer to the VM.
1774 * @remark Intended for PATM.
1775 */
1776VMMDECL(uint32_t) CPUMGetGuestCpuIdStdMax(PVM pVM)
1777{
1778 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd);
1779}
1780
1781
1782/**
1783 * Gets a number of extended CPUID leafs.
1784 *
1785 * @returns Number of leafs.
1786 * @param pVM Pointer to the VM.
1787 * @remark Intended for PATM.
1788 */
1789VMMDECL(uint32_t) CPUMGetGuestCpuIdExtMax(PVM pVM)
1790{
1791 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt);
1792}
1793
1794
1795/**
1796 * Gets a number of centaur CPUID leafs.
1797 *
1798 * @returns Number of leafs.
1799 * @param pVM Pointer to the VM.
1800 * @remark Intended for PATM.
1801 */
1802VMMDECL(uint32_t) CPUMGetGuestCpuIdCentaurMax(PVM pVM)
1803{
1804 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur);
1805}
1806
1807
1808/**
1809 * Sets a CPUID feature bit.
1810 *
1811 * @param pVM Pointer to the VM.
1812 * @param enmFeature The feature to set.
1813 */
1814VMMDECL(void) CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
1815{
1816 switch (enmFeature)
1817 {
1818 /*
1819 * Set the APIC bit in both feature masks.
1820 */
1821 case CPUMCPUIDFEATURE_APIC:
1822 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1823 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_APIC;
1824 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1825 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1826 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_APIC;
1827 LogRel(("CPUMSetGuestCpuIdFeature: Enabled APIC\n"));
1828 break;
1829
1830 /*
1831 * Set the x2APIC bit in the standard feature mask.
1832 */
1833 case CPUMCPUIDFEATURE_X2APIC:
1834 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1835 pVM->cpum.s.aGuestCpuIdStd[1].ecx |= X86_CPUID_FEATURE_ECX_X2APIC;
1836 LogRel(("CPUMSetGuestCpuIdFeature: Enabled x2APIC\n"));
1837 break;
1838
1839 /*
1840 * Set the sysenter/sysexit bit in the standard feature mask.
1841 * Assumes the caller knows what it's doing! (host must support these)
1842 */
1843 case CPUMCPUIDFEATURE_SEP:
1844 {
1845 if (!(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_SEP))
1846 {
1847 AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
1848 return;
1849 }
1850
1851 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1852 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_SEP;
1853 LogRel(("CPUMSetGuestCpuIdFeature: Enabled sysenter/exit\n"));
1854 break;
1855 }
1856
1857 /*
1858 * Set the syscall/sysret bit in the extended feature mask.
1859 * Assumes the caller knows what it's doing! (host must support these)
1860 */
1861 case CPUMCPUIDFEATURE_SYSCALL:
1862 {
1863 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1864 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_SYSCALL))
1865 {
1866#if HC_ARCH_BITS == 32
1867 /* X86_CPUID_EXT_FEATURE_EDX_SYSCALL not set it seems in 32 bits mode.
1868 * Even when the cpu is capable of doing so in 64 bits mode.
1869 */
1870 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1871 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
1872 || !(ASMCpuId_EDX(1) & X86_CPUID_EXT_FEATURE_EDX_SYSCALL))
1873#endif
1874 {
1875 LogRel(("WARNING: Can't turn on SYSCALL/SYSRET when the host doesn't support it!!\n"));
1876 return;
1877 }
1878 }
1879 /* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
1880 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
1881 LogRel(("CPUMSetGuestCpuIdFeature: Enabled syscall/ret\n"));
1882 break;
1883 }
1884
1885 /*
1886 * Set the PAE bit in both feature masks.
1887 * Assumes the caller knows what it's doing! (host must support these)
1888 */
1889 case CPUMCPUIDFEATURE_PAE:
1890 {
1891 if (!(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_PAE))
1892 {
1893 LogRel(("WARNING: Can't turn on PAE when the host doesn't support it!!\n"));
1894 return;
1895 }
1896
1897 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1898 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_PAE;
1899 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1900 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1901 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_PAE;
1902 LogRel(("CPUMSetGuestCpuIdFeature: Enabled PAE\n"));
1903 break;
1904 }
1905
1906 /*
1907 * Set the LONG MODE bit in the extended feature mask.
1908 * Assumes the caller knows what it's doing! (host must support these)
1909 */
1910 case CPUMCPUIDFEATURE_LONG_MODE:
1911 {
1912 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1913 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE))
1914 {
1915 LogRel(("WARNING: Can't turn on LONG MODE when the host doesn't support it!!\n"));
1916 return;
1917 }
1918
1919 /* Valid for both Intel and AMD. */
1920 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
1921 LogRel(("CPUMSetGuestCpuIdFeature: Enabled LONG MODE\n"));
1922 break;
1923 }
1924
1925 /*
1926 * Set the NX/XD bit in the extended feature mask.
1927 * Assumes the caller knows what it's doing! (host must support these)
1928 */
1929 case CPUMCPUIDFEATURE_NX:
1930 {
1931 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1932 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_NX))
1933 {
1934 LogRel(("WARNING: Can't turn on NX/XD when the host doesn't support it!!\n"));
1935 return;
1936 }
1937
1938 /* Valid for both Intel and AMD. */
1939 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_NX;
1940 LogRel(("CPUMSetGuestCpuIdFeature: Enabled NX\n"));
1941 break;
1942 }
1943
1944 /*
1945 * Set the LAHF/SAHF support in 64-bit mode.
1946 * Assumes the caller knows what it's doing! (host must support this)
1947 */
1948 case CPUMCPUIDFEATURE_LAHF:
1949 {
1950 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1951 || !(ASMCpuId_ECX(0x80000001) & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF))
1952 {
1953 LogRel(("WARNING: Can't turn on LAHF/SAHF when the host doesn't support it!!\n"));
1954 return;
1955 }
1956
1957 /* Valid for both Intel and AMD. */
1958 pVM->cpum.s.aGuestCpuIdExt[1].ecx |= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
1959 LogRel(("CPUMSetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
1960 break;
1961 }
1962
1963 case CPUMCPUIDFEATURE_PAT:
1964 {
1965 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1966 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_PAT;
1967 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1968 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1969 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_PAT;
1970 LogRel(("CPUMSetGuestCpuIdFeature: Enabled PAT\n"));
1971 break;
1972 }
1973
1974 /*
1975 * Set the RDTSCP support bit.
1976 * Assumes the caller knows what it's doing! (host must support this)
1977 */
1978 case CPUMCPUIDFEATURE_RDTSCP:
1979 {
1980 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1981 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
1982 || pVM->cpum.s.u8PortableCpuIdLevel > 0)
1983 {
1984 if (!pVM->cpum.s.u8PortableCpuIdLevel)
1985 LogRel(("WARNING: Can't turn on RDTSCP when the host doesn't support it!!\n"));
1986 return;
1987 }
1988
1989 /* Valid for both Intel and AMD. */
1990 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
1991 LogRel(("CPUMSetGuestCpuIdFeature: Enabled RDTSCP.\n"));
1992 break;
1993 }
1994
1995 /*
1996 * Set the Hypervisor Present bit in the standard feature mask.
1997 */
1998 case CPUMCPUIDFEATURE_HVP:
1999 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2000 pVM->cpum.s.aGuestCpuIdStd[1].ecx |= X86_CPUID_FEATURE_ECX_HVP;
2001 LogRel(("CPUMSetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
2002 break;
2003
2004 default:
2005 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
2006 break;
2007 }
2008 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2009 {
2010 PVMCPU pVCpu = &pVM->aCpus[i];
2011 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CPUID;
2012 }
2013}
2014
2015
2016/**
2017 * Queries a CPUID feature bit.
2018 *
2019 * @returns boolean for feature presence
2020 * @param pVM Pointer to the VM.
2021 * @param enmFeature The feature to query.
2022 */
2023VMMDECL(bool) CPUMGetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
2024{
2025 switch (enmFeature)
2026 {
2027 case CPUMCPUIDFEATURE_PAE:
2028 {
2029 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2030 return !!(pVM->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PAE);
2031 break;
2032 }
2033
2034 case CPUMCPUIDFEATURE_NX:
2035 {
2036 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
2037 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_EXT_FEATURE_EDX_NX);
2038 }
2039
2040 case CPUMCPUIDFEATURE_SYSCALL:
2041 {
2042 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
2043 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
2044 }
2045
2046 case CPUMCPUIDFEATURE_RDTSCP:
2047 {
2048 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
2049 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2050 break;
2051 }
2052
2053 case CPUMCPUIDFEATURE_LONG_MODE:
2054 {
2055 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
2056 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
2057 break;
2058 }
2059
2060 default:
2061 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
2062 break;
2063 }
2064 return false;
2065}
2066
2067
2068/**
2069 * Clears a CPUID feature bit.
2070 *
2071 * @param pVM Pointer to the VM.
2072 * @param enmFeature The feature to clear.
2073 */
2074VMMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
2075{
2076 switch (enmFeature)
2077 {
2078 /*
2079 * Set the APIC bit in both feature masks.
2080 */
2081 case CPUMCPUIDFEATURE_APIC:
2082 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2083 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_APIC;
2084 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
2085 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
2086 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
2087 Log(("CPUMClearGuestCpuIdFeature: Disabled APIC\n"));
2088 break;
2089
2090 /*
2091 * Clear the x2APIC bit in the standard feature mask.
2092 */
2093 case CPUMCPUIDFEATURE_X2APIC:
2094 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2095 pVM->cpum.s.aGuestCpuIdStd[1].ecx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
2096 Log(("CPUMClearGuestCpuIdFeature: Disabled x2APIC\n"));
2097 break;
2098
2099 case CPUMCPUIDFEATURE_PAE:
2100 {
2101 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2102 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_PAE;
2103 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
2104 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
2105 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
2106 Log(("CPUMClearGuestCpuIdFeature: Disabled PAE!\n"));
2107 break;
2108 }
2109
2110 case CPUMCPUIDFEATURE_PAT:
2111 {
2112 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2113 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_PAT;
2114 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
2115 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
2116 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_PAT;
2117 Log(("CPUMClearGuestCpuIdFeature: Disabled PAT!\n"));
2118 break;
2119 }
2120
2121 case CPUMCPUIDFEATURE_LONG_MODE:
2122 {
2123 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
2124 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
2125 break;
2126 }
2127
2128 case CPUMCPUIDFEATURE_LAHF:
2129 {
2130 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
2131 pVM->cpum.s.aGuestCpuIdExt[1].ecx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
2132 break;
2133 }
2134
2135 case CPUMCPUIDFEATURE_RDTSCP:
2136 {
2137 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
2138 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
2139 Log(("CPUMClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
2140 break;
2141 }
2142
2143 case CPUMCPUIDFEATURE_HVP:
2144 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2145 pVM->cpum.s.aGuestCpuIdStd[1].ecx &= ~X86_CPUID_FEATURE_ECX_HVP;
2146 break;
2147
2148 default:
2149 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
2150 break;
2151 }
2152 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2153 {
2154 PVMCPU pVCpu = &pVM->aCpus[i];
2155 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CPUID;
2156 }
2157}
2158
2159
2160/**
2161 * Gets the host CPU vendor.
2162 *
2163 * @returns CPU vendor.
2164 * @param pVM Pointer to the VM.
2165 */
2166VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM)
2167{
2168 return pVM->cpum.s.enmHostCpuVendor;
2169}
2170
2171
2172/**
2173 * Gets the CPU vendor.
2174 *
2175 * @returns CPU vendor.
2176 * @param pVM Pointer to the VM.
2177 */
2178VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM)
2179{
2180 return pVM->cpum.s.enmGuestCpuVendor;
2181}
2182
2183
2184VMMDECL(int) CPUMSetGuestDR0(PVMCPU pVCpu, uint64_t uDr0)
2185{
2186 pVCpu->cpum.s.Guest.dr[0] = uDr0;
2187 return CPUMRecalcHyperDRx(pVCpu, 0, false);
2188}
2189
2190
2191VMMDECL(int) CPUMSetGuestDR1(PVMCPU pVCpu, uint64_t uDr1)
2192{
2193 pVCpu->cpum.s.Guest.dr[1] = uDr1;
2194 return CPUMRecalcHyperDRx(pVCpu, 1, false);
2195}
2196
2197
2198VMMDECL(int) CPUMSetGuestDR2(PVMCPU pVCpu, uint64_t uDr2)
2199{
2200 pVCpu->cpum.s.Guest.dr[2] = uDr2;
2201 return CPUMRecalcHyperDRx(pVCpu, 2, false);
2202}
2203
2204
2205VMMDECL(int) CPUMSetGuestDR3(PVMCPU pVCpu, uint64_t uDr3)
2206{
2207 pVCpu->cpum.s.Guest.dr[3] = uDr3;
2208 return CPUMRecalcHyperDRx(pVCpu, 3, false);
2209}
2210
2211
2212VMMDECL(int) CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6)
2213{
2214 pVCpu->cpum.s.Guest.dr[6] = uDr6;
2215 return VINF_SUCCESS; /* No need to recalc. */
2216}
2217
2218
2219VMMDECL(int) CPUMSetGuestDR7(PVMCPU pVCpu, uint64_t uDr7)
2220{
2221 pVCpu->cpum.s.Guest.dr[7] = uDr7;
2222 return CPUMRecalcHyperDRx(pVCpu, 7, false);
2223}
2224
2225
2226VMMDECL(int) CPUMSetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t Value)
2227{
2228 AssertReturn(iReg <= DISDREG_DR7, VERR_INVALID_PARAMETER);
2229 /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
2230 if (iReg == 4 || iReg == 5)
2231 iReg += 2;
2232 pVCpu->cpum.s.Guest.dr[iReg] = Value;
2233 return CPUMRecalcHyperDRx(pVCpu, iReg, false);
2234}
2235
2236
2237/**
2238 * Recalculates the hypervisor DRx register values based on current guest
2239 * registers and DBGF breakpoints, updating changed registers depending on the
2240 * context.
2241 *
2242 * This is called whenever a guest DRx register is modified (any context) and
2243 * when DBGF sets a hardware breakpoint (ring-3 only, rendezvous).
2244 *
2245 * In raw-mode context this function will reload any (hyper) DRx registers which
2246 * comes out with a different value. It may also have to save the host debug
2247 * registers if that haven't been done already. In this context though, we'll
2248 * be intercepting and emulating all DRx accesses, so the hypervisor DRx values
2249 * are only important when breakpoints are actually enabled.
2250 *
2251 * In ring-0 (HM) context DR0-3 will be relocated by us, while DR7 will be
2252 * reloaded by the HM code if it changes. Further more, we will only use the
2253 * combined register set when the VBox debugger is actually using hardware BPs,
2254 * when it isn't we'll keep the guest DR0-3 + (maybe) DR6 loaded (DR6 doesn't
2255 * concern us here).
2256 *
2257 * In ring-3 we won't be loading anything, so well calculate hypervisor values
2258 * all the time.
2259 *
2260 * @returns VINF_SUCCESS.
2261 * @param pVCpu Pointer to the VMCPU.
2262 * @param iGstReg The guest debug register number that was modified.
2263 * UINT8_MAX if not guest register.
2264 * @param fForceHyper Used in HM to force hyper registers because of single
2265 * stepping.
2266 */
2267VMMDECL(int) CPUMRecalcHyperDRx(PVMCPU pVCpu, uint8_t iGstReg, bool fForceHyper)
2268{
2269 PVM pVM = pVCpu->CTX_SUFF(pVM);
2270
2271 /*
2272 * Compare the DR7s first.
2273 *
2274 * We only care about the enabled flags. GD is virtualized when we
2275 * dispatch the #DB, we never enable it. The DBGF DR7 value is will
2276 * always have the LE and GE bits set, so no need to check and disable
2277 * stuff if they're cleared like we have to for the guest DR7.
2278 */
2279 RTGCUINTREG uGstDr7 = CPUMGetGuestDR7(pVCpu);
2280 if (!(uGstDr7 & (X86_DR7_LE | X86_DR7_GE)))
2281 uGstDr7 = 0;
2282 else if (!(uGstDr7 & X86_DR7_LE))
2283 uGstDr7 &= ~X86_DR7_LE_ALL;
2284 else if (!(uGstDr7 & X86_DR7_GE))
2285 uGstDr7 &= ~X86_DR7_GE_ALL;
2286
2287 const RTGCUINTREG uDbgfDr7 = DBGFBpGetDR7(pVM);
2288
2289#ifdef IN_RING0
2290 if (!fForceHyper && (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HYPER))
2291 fForceHyper = true;
2292#endif
2293 if (( HMIsEnabled(pVCpu->CTX_SUFF(pVM)) && !fForceHyper ? uDbgfDr7 : (uGstDr7 | uDbgfDr7)) & X86_DR7_ENABLED_MASK)
2294 {
2295 Assert(!CPUMIsGuestDebugStateActive(pVCpu));
2296#ifdef IN_RC
2297 bool const fHmEnabled = false;
2298#elif defined(IN_RING3)
2299 bool const fHmEnabled = HMIsEnabled(pVM);
2300#endif
2301
2302 /*
2303 * Ok, something is enabled. Recalc each of the breakpoints, taking
2304 * the VM debugger ones of the guest ones. In raw-mode context we will
2305 * not allow breakpoints with values inside the hypervisor area.
2306 */
2307 RTGCUINTREG uNewDr7 = X86_DR7_GE | X86_DR7_LE | X86_DR7_RA1_MASK;
2308
2309 /* bp 0 */
2310 RTGCUINTREG uNewDr0;
2311 if (uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0))
2312 {
2313 uNewDr7 |= uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
2314 uNewDr0 = DBGFBpGetDR0(pVM);
2315 }
2316 else if (uGstDr7 & (X86_DR7_L0 | X86_DR7_G0))
2317 {
2318 uNewDr0 = CPUMGetGuestDR0(pVCpu);
2319#ifndef IN_RING0
2320 if (fHmEnabled && MMHyperIsInsideArea(pVM, uNewDr0))
2321 uNewDr0 = 0;
2322 else
2323#endif
2324 uNewDr7 |= uGstDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
2325 }
2326 else
2327 uNewDr0 = 0;
2328
2329 /* bp 1 */
2330 RTGCUINTREG uNewDr1;
2331 if (uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1))
2332 {
2333 uNewDr7 |= uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
2334 uNewDr1 = DBGFBpGetDR1(pVM);
2335 }
2336 else if (uGstDr7 & (X86_DR7_L1 | X86_DR7_G1))
2337 {
2338 uNewDr1 = CPUMGetGuestDR1(pVCpu);
2339#ifndef IN_RING0
2340 if (fHmEnabled && MMHyperIsInsideArea(pVM, uNewDr1))
2341 uNewDr1 = 0;
2342 else
2343#endif
2344 uNewDr7 |= uGstDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
2345 }
2346 else
2347 uNewDr1 = 0;
2348
2349 /* bp 2 */
2350 RTGCUINTREG uNewDr2;
2351 if (uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2))
2352 {
2353 uNewDr7 |= uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
2354 uNewDr2 = DBGFBpGetDR2(pVM);
2355 }
2356 else if (uGstDr7 & (X86_DR7_L2 | X86_DR7_G2))
2357 {
2358 uNewDr2 = CPUMGetGuestDR2(pVCpu);
2359#ifndef IN_RING0
2360 if (fHmEnabled && MMHyperIsInsideArea(pVM, uNewDr2))
2361 uNewDr2 = 0;
2362 else
2363#endif
2364 uNewDr7 |= uGstDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
2365 }
2366 else
2367 uNewDr2 = 0;
2368
2369 /* bp 3 */
2370 RTGCUINTREG uNewDr3;
2371 if (uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3))
2372 {
2373 uNewDr7 |= uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
2374 uNewDr3 = DBGFBpGetDR3(pVM);
2375 }
2376 else if (uGstDr7 & (X86_DR7_L3 | X86_DR7_G3))
2377 {
2378 uNewDr3 = CPUMGetGuestDR3(pVCpu);
2379#ifndef IN_RING0
2380 if (fHmEnabled && MMHyperIsInsideArea(pVM, uNewDr3))
2381 uNewDr3 = 0;
2382 else
2383#endif
2384 uNewDr7 |= uGstDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
2385 }
2386 else
2387 uNewDr3 = 0;
2388
2389 /*
2390 * Apply the updates.
2391 */
2392#ifdef IN_RC
2393 /* Make sure to save host registers first. */
2394 if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HOST))
2395 {
2396 if (!(pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS_HOST))
2397 {
2398 pVCpu->cpum.s.Host.dr6 = ASMGetDR6();
2399 pVCpu->cpum.s.Host.dr7 = ASMGetDR7();
2400 }
2401 pVCpu->cpum.s.Host.dr0 = ASMGetDR0();
2402 pVCpu->cpum.s.Host.dr1 = ASMGetDR1();
2403 pVCpu->cpum.s.Host.dr2 = ASMGetDR2();
2404 pVCpu->cpum.s.Host.dr3 = ASMGetDR3();
2405 pVCpu->cpum.s.fUseFlags |= CPUM_USED_DEBUG_REGS_HOST | CPUM_USE_DEBUG_REGS_HYPER | CPUM_USED_DEBUG_REGS_HYPER;
2406
2407 /* We haven't loaded any hyper DRxes yet, so we'll have to load them all now. */
2408 pVCpu->cpum.s.Hyper.dr[0] = uNewDr0;
2409 ASMSetDR0(uNewDr0);
2410 pVCpu->cpum.s.Hyper.dr[1] = uNewDr1;
2411 ASMSetDR1(uNewDr1);
2412 pVCpu->cpum.s.Hyper.dr[2] = uNewDr2;
2413 ASMSetDR2(uNewDr2);
2414 pVCpu->cpum.s.Hyper.dr[3] = uNewDr3;
2415 ASMSetDR3(uNewDr3);
2416 ASMSetDR6(X86_DR6_INIT_VAL);
2417 pVCpu->cpum.s.Hyper.dr[7] = uNewDr7;
2418 ASMSetDR7(uNewDr7);
2419 }
2420 else
2421#endif
2422 {
2423 pVCpu->cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS_HYPER;
2424 if (uNewDr3 != pVCpu->cpum.s.Hyper.dr[3])
2425 CPUMSetHyperDR3(pVCpu, uNewDr3);
2426 if (uNewDr2 != pVCpu->cpum.s.Hyper.dr[2])
2427 CPUMSetHyperDR2(pVCpu, uNewDr2);
2428 if (uNewDr1 != pVCpu->cpum.s.Hyper.dr[1])
2429 CPUMSetHyperDR1(pVCpu, uNewDr1);
2430 if (uNewDr0 != pVCpu->cpum.s.Hyper.dr[0])
2431 CPUMSetHyperDR0(pVCpu, uNewDr0);
2432 if (uNewDr7 != pVCpu->cpum.s.Hyper.dr[7])
2433 CPUMSetHyperDR7(pVCpu, uNewDr7);
2434 }
2435 }
2436#ifdef IN_RING0
2437 else if (CPUMIsGuestDebugStateActive(pVCpu))
2438 {
2439 /*
2440 * Reload the register that was modified. Normally this won't happen
2441 * as we won't intercept DRx writes when not having the hyper debug
2442 * state loaded, but in case we do for some reason we'll simply deal
2443 * with it.
2444 */
2445 switch (iGstReg)
2446 {
2447 case 0: ASMSetDR0(CPUMGetGuestDR0(pVCpu)); break;
2448 case 1: ASMSetDR1(CPUMGetGuestDR1(pVCpu)); break;
2449 case 2: ASMSetDR2(CPUMGetGuestDR2(pVCpu)); break;
2450 case 3: ASMSetDR3(CPUMGetGuestDR3(pVCpu)); break;
2451 default:
2452 AssertReturn(iGstReg != UINT8_MAX, VERR_INTERNAL_ERROR_3);
2453 }
2454 }
2455#endif
2456 else
2457 {
2458 /*
2459 * No active debug state any more. In raw-mode this means we have to
2460 * make sure DR7 has everything disabled now, if we armed it already.
2461 * In ring-0 we might end up here when just single stepping.
2462 */
2463#if defined(IN_RC) || defined(IN_RING0)
2464 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HYPER)
2465 {
2466# ifdef IN_RC
2467 ASMSetDR7(X86_DR7_INIT_VAL);
2468# endif
2469 if (pVCpu->cpum.s.Hyper.dr[0])
2470 ASMSetDR0(0);
2471 if (pVCpu->cpum.s.Hyper.dr[1])
2472 ASMSetDR1(0);
2473 if (pVCpu->cpum.s.Hyper.dr[2])
2474 ASMSetDR2(0);
2475 if (pVCpu->cpum.s.Hyper.dr[3])
2476 ASMSetDR3(0);
2477 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_DEBUG_REGS_HYPER;
2478 }
2479#endif
2480 pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS_HYPER;
2481
2482 /* Clear all the registers. */
2483 pVCpu->cpum.s.Hyper.dr[7] = X86_DR7_RA1_MASK;
2484 pVCpu->cpum.s.Hyper.dr[3] = 0;
2485 pVCpu->cpum.s.Hyper.dr[2] = 0;
2486 pVCpu->cpum.s.Hyper.dr[1] = 0;
2487 pVCpu->cpum.s.Hyper.dr[0] = 0;
2488
2489 }
2490 Log2(("CPUMRecalcHyperDRx: fUseFlags=%#x %RGr %RGr %RGr %RGr %RGr %RGr\n",
2491 pVCpu->cpum.s.fUseFlags, pVCpu->cpum.s.Hyper.dr[0], pVCpu->cpum.s.Hyper.dr[1],
2492 pVCpu->cpum.s.Hyper.dr[2], pVCpu->cpum.s.Hyper.dr[3], pVCpu->cpum.s.Hyper.dr[6],
2493 pVCpu->cpum.s.Hyper.dr[7]));
2494
2495 return VINF_SUCCESS;
2496}
2497
2498
2499/**
2500 * Tests if the guest has No-Execute Page Protection Enabled (NXE).
2501 *
2502 * @returns true if in real mode, otherwise false.
2503 * @param pVCpu Pointer to the VMCPU.
2504 */
2505VMMDECL(bool) CPUMIsGuestNXEnabled(PVMCPU pVCpu)
2506{
2507 return !!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE);
2508}
2509
2510
2511/**
2512 * Tests if the guest has the Page Size Extension enabled (PSE).
2513 *
2514 * @returns true if in real mode, otherwise false.
2515 * @param pVCpu Pointer to the VMCPU.
2516 */
2517VMMDECL(bool) CPUMIsGuestPageSizeExtEnabled(PVMCPU pVCpu)
2518{
2519 /* PAE or AMD64 implies support for big pages regardless of CR4.PSE */
2520 return !!(pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PSE | X86_CR4_PAE));
2521}
2522
2523
2524/**
2525 * Tests if the guest has the paging enabled (PG).
2526 *
2527 * @returns true if in real mode, otherwise false.
2528 * @param pVCpu Pointer to the VMCPU.
2529 */
2530VMMDECL(bool) CPUMIsGuestPagingEnabled(PVMCPU pVCpu)
2531{
2532 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG);
2533}
2534
2535
2536/**
2537 * Tests if the guest has the paging enabled (PG).
2538 *
2539 * @returns true if in real mode, otherwise false.
2540 * @param pVCpu Pointer to the VMCPU.
2541 */
2542VMMDECL(bool) CPUMIsGuestR0WriteProtEnabled(PVMCPU pVCpu)
2543{
2544 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_WP);
2545}
2546
2547
2548/**
2549 * Tests if the guest is running in real mode or not.
2550 *
2551 * @returns true if in real mode, otherwise false.
2552 * @param pVCpu Pointer to the VMCPU.
2553 */
2554VMMDECL(bool) CPUMIsGuestInRealMode(PVMCPU pVCpu)
2555{
2556 return !(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
2557}
2558
2559
2560/**
2561 * Tests if the guest is running in real or virtual 8086 mode.
2562 *
2563 * @returns @c true if it is, @c false if not.
2564 * @param pVCpu Pointer to the VMCPU.
2565 */
2566VMMDECL(bool) CPUMIsGuestInRealOrV86Mode(PVMCPU pVCpu)
2567{
2568 return !(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE)
2569 || pVCpu->cpum.s.Guest.eflags.Bits.u1VM; /** @todo verify that this cannot be set in long mode. */
2570}
2571
2572
2573/**
2574 * Tests if the guest is running in protected or not.
2575 *
2576 * @returns true if in protected mode, otherwise false.
2577 * @param pVCpu Pointer to the VMCPU.
2578 */
2579VMMDECL(bool) CPUMIsGuestInProtectedMode(PVMCPU pVCpu)
2580{
2581 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
2582}
2583
2584
2585/**
2586 * Tests if the guest is running in paged protected or not.
2587 *
2588 * @returns true if in paged protected mode, otherwise false.
2589 * @param pVCpu Pointer to the VMCPU.
2590 */
2591VMMDECL(bool) CPUMIsGuestInPagedProtectedMode(PVMCPU pVCpu)
2592{
2593 return (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
2594}
2595
2596
2597/**
2598 * Tests if the guest is running in long mode or not.
2599 *
2600 * @returns true if in long mode, otherwise false.
2601 * @param pVCpu Pointer to the VMCPU.
2602 */
2603VMMDECL(bool) CPUMIsGuestInLongMode(PVMCPU pVCpu)
2604{
2605 return (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
2606}
2607
2608
2609/**
2610 * Tests if the guest is running in PAE mode or not.
2611 *
2612 * @returns true if in PAE mode, otherwise false.
2613 * @param pVCpu Pointer to the VMCPU.
2614 */
2615VMMDECL(bool) CPUMIsGuestInPAEMode(PVMCPU pVCpu)
2616{
2617 return (pVCpu->cpum.s.Guest.cr4 & X86_CR4_PAE)
2618 && (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG)
2619 && !(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LME);
2620}
2621
2622
2623/**
2624 * Tests if the guest is running in 64 bits mode or not.
2625 *
2626 * @returns true if in 64 bits protected mode, otherwise false.
2627 * @param pVCpu The current virtual CPU.
2628 */
2629VMMDECL(bool) CPUMIsGuestIn64BitCode(PVMCPU pVCpu)
2630{
2631 if (!CPUMIsGuestInLongMode(pVCpu))
2632 return false;
2633 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
2634 return pVCpu->cpum.s.Guest.cs.Attr.n.u1Long;
2635}
2636
2637
2638/**
2639 * Helper for CPUMIsGuestIn64BitCodeEx that handles lazy resolving of hidden CS
2640 * registers.
2641 *
2642 * @returns true if in 64 bits protected mode, otherwise false.
2643 * @param pCtx Pointer to the current guest CPU context.
2644 */
2645VMM_INT_DECL(bool) CPUMIsGuestIn64BitCodeSlow(PCPUMCTX pCtx)
2646{
2647 return CPUMIsGuestIn64BitCode(CPUM_GUEST_CTX_TO_VMCPU(pCtx));
2648}
2649
2650#ifdef VBOX_WITH_RAW_MODE_NOT_R0
2651
2652/**
2653 *
2654 * @returns @c true if we've entered raw-mode and selectors with RPL=1 are
2655 * really RPL=0, @c false if we've not (RPL=1 really is RPL=1).
2656 * @param pVCpu The current virtual CPU.
2657 */
2658VMM_INT_DECL(bool) CPUMIsGuestInRawMode(PVMCPU pVCpu)
2659{
2660 return pVCpu->cpum.s.fRawEntered;
2661}
2662
2663/**
2664 * Transforms the guest CPU state to raw-ring mode.
2665 *
2666 * This function will change the any of the cs and ss register with DPL=0 to DPL=1.
2667 *
2668 * @returns VBox status. (recompiler failure)
2669 * @param pVCpu Pointer to the VMCPU.
2670 * @param pCtxCore The context core (for trap usage).
2671 * @see @ref pg_raw
2672 */
2673VMM_INT_DECL(int) CPUMRawEnter(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
2674{
2675 PVM pVM = pVCpu->CTX_SUFF(pVM);
2676
2677 Assert(!pVCpu->cpum.s.fRawEntered);
2678 Assert(!pVCpu->cpum.s.fRemEntered);
2679 if (!pCtxCore)
2680 pCtxCore = CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
2681
2682 /*
2683 * Are we in Ring-0?
2684 */
2685 if ( pCtxCore->ss.Sel
2686 && (pCtxCore->ss.Sel & X86_SEL_RPL) == 0
2687 && !pCtxCore->eflags.Bits.u1VM)
2688 {
2689 /*
2690 * Enter execution mode.
2691 */
2692 PATMRawEnter(pVM, pCtxCore);
2693
2694 /*
2695 * Set CPL to Ring-1.
2696 */
2697 pCtxCore->ss.Sel |= 1;
2698 if ( pCtxCore->cs.Sel
2699 && (pCtxCore->cs.Sel & X86_SEL_RPL) == 0)
2700 pCtxCore->cs.Sel |= 1;
2701 }
2702 else
2703 {
2704# ifdef VBOX_WITH_RAW_RING1
2705 if ( EMIsRawRing1Enabled(pVM)
2706 && !pCtxCore->eflags.Bits.u1VM
2707 && (pCtxCore->ss.Sel & X86_SEL_RPL) == 1)
2708 {
2709 /* Set CPL to Ring-2. */
2710 pCtxCore->ss.Sel = (pCtxCore->ss.Sel & ~X86_SEL_RPL) | 2;
2711 if (pCtxCore->cs.Sel && (pCtxCore->cs.Sel & X86_SEL_RPL) == 1)
2712 pCtxCore->cs.Sel = (pCtxCore->cs.Sel & ~X86_SEL_RPL) | 2;
2713 }
2714# else
2715 AssertMsg((pCtxCore->ss.Sel & X86_SEL_RPL) >= 2 || pCtxCore->eflags.Bits.u1VM,
2716 ("ring-1 code not supported\n"));
2717# endif
2718 /*
2719 * PATM takes care of IOPL and IF flags for Ring-3 and Ring-2 code as well.
2720 */
2721 PATMRawEnter(pVM, pCtxCore);
2722 }
2723
2724 /*
2725 * Assert sanity.
2726 */
2727 AssertMsg((pCtxCore->eflags.u32 & X86_EFL_IF), ("X86_EFL_IF is clear\n"));
2728 AssertReleaseMsg(pCtxCore->eflags.Bits.u2IOPL == 0,
2729 ("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss.Sel & X86_SEL_RPL));
2730 Assert((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)) == (X86_CR0_PG | X86_CR0_PE | X86_CR0_WP));
2731
2732 pCtxCore->eflags.u32 |= X86_EFL_IF; /* paranoia */
2733
2734 pVCpu->cpum.s.fRawEntered = true;
2735 return VINF_SUCCESS;
2736}
2737
2738
2739/**
2740 * Transforms the guest CPU state from raw-ring mode to correct values.
2741 *
2742 * This function will change any selector registers with DPL=1 to DPL=0.
2743 *
2744 * @returns Adjusted rc.
2745 * @param pVCpu Pointer to the VMCPU.
2746 * @param rc Raw mode return code
2747 * @param pCtxCore The context core (for trap usage).
2748 * @see @ref pg_raw
2749 */
2750VMM_INT_DECL(int) CPUMRawLeave(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, int rc)
2751{
2752 PVM pVM = pVCpu->CTX_SUFF(pVM);
2753
2754 /*
2755 * Don't leave if we've already left (in RC).
2756 */
2757 Assert(!pVCpu->cpum.s.fRemEntered);
2758 if (!pVCpu->cpum.s.fRawEntered)
2759 return rc;
2760 pVCpu->cpum.s.fRawEntered = false;
2761
2762 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2763 if (!pCtxCore)
2764 pCtxCore = CPUMCTX2CORE(pCtx);
2765 Assert(pCtxCore->eflags.Bits.u1VM || (pCtxCore->ss.Sel & X86_SEL_RPL));
2766 AssertMsg(pCtxCore->eflags.Bits.u1VM || pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss.Sel & X86_SEL_RPL),
2767 ("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss.Sel & X86_SEL_RPL));
2768
2769 /*
2770 * Are we executing in raw ring-1?
2771 */
2772 if ( (pCtxCore->ss.Sel & X86_SEL_RPL) == 1
2773 && !pCtxCore->eflags.Bits.u1VM)
2774 {
2775 /*
2776 * Leave execution mode.
2777 */
2778 PATMRawLeave(pVM, pCtxCore, rc);
2779 /* Not quite sure if this is really required, but shouldn't harm (too much anyways). */
2780 /** @todo See what happens if we remove this. */
2781 if ((pCtxCore->ds.Sel & X86_SEL_RPL) == 1)
2782 pCtxCore->ds.Sel &= ~X86_SEL_RPL;
2783 if ((pCtxCore->es.Sel & X86_SEL_RPL) == 1)
2784 pCtxCore->es.Sel &= ~X86_SEL_RPL;
2785 if ((pCtxCore->fs.Sel & X86_SEL_RPL) == 1)
2786 pCtxCore->fs.Sel &= ~X86_SEL_RPL;
2787 if ((pCtxCore->gs.Sel & X86_SEL_RPL) == 1)
2788 pCtxCore->gs.Sel &= ~X86_SEL_RPL;
2789
2790 /*
2791 * Ring-1 selector => Ring-0.
2792 */
2793 pCtxCore->ss.Sel &= ~X86_SEL_RPL;
2794 if ((pCtxCore->cs.Sel & X86_SEL_RPL) == 1)
2795 pCtxCore->cs.Sel &= ~X86_SEL_RPL;
2796 }
2797 else
2798 {
2799 /*
2800 * PATM is taking care of the IOPL and IF flags for us.
2801 */
2802 PATMRawLeave(pVM, pCtxCore, rc);
2803 if (!pCtxCore->eflags.Bits.u1VM)
2804 {
2805# ifdef VBOX_WITH_RAW_RING1
2806 if ( EMIsRawRing1Enabled(pVM)
2807 && (pCtxCore->ss.Sel & X86_SEL_RPL) == 2)
2808 {
2809 /* Not quite sure if this is really required, but shouldn't harm (too much anyways). */
2810 /** @todo See what happens if we remove this. */
2811 if ((pCtxCore->ds.Sel & X86_SEL_RPL) == 2)
2812 pCtxCore->ds.Sel = (pCtxCore->ds.Sel & ~X86_SEL_RPL) | 1;
2813 if ((pCtxCore->es.Sel & X86_SEL_RPL) == 2)
2814 pCtxCore->es.Sel = (pCtxCore->es.Sel & ~X86_SEL_RPL) | 1;
2815 if ((pCtxCore->fs.Sel & X86_SEL_RPL) == 2)
2816 pCtxCore->fs.Sel = (pCtxCore->fs.Sel & ~X86_SEL_RPL) | 1;
2817 if ((pCtxCore->gs.Sel & X86_SEL_RPL) == 2)
2818 pCtxCore->gs.Sel = (pCtxCore->gs.Sel & ~X86_SEL_RPL) | 1;
2819
2820 /*
2821 * Ring-2 selector => Ring-1.
2822 */
2823 pCtxCore->ss.Sel = (pCtxCore->ss.Sel & ~X86_SEL_RPL) | 1;
2824 if ((pCtxCore->cs.Sel & X86_SEL_RPL) == 2)
2825 pCtxCore->cs.Sel = (pCtxCore->cs.Sel & ~X86_SEL_RPL) | 1;
2826 }
2827 else
2828 {
2829# endif
2830 /** @todo See what happens if we remove this. */
2831 if ((pCtxCore->ds.Sel & X86_SEL_RPL) == 1)
2832 pCtxCore->ds.Sel &= ~X86_SEL_RPL;
2833 if ((pCtxCore->es.Sel & X86_SEL_RPL) == 1)
2834 pCtxCore->es.Sel &= ~X86_SEL_RPL;
2835 if ((pCtxCore->fs.Sel & X86_SEL_RPL) == 1)
2836 pCtxCore->fs.Sel &= ~X86_SEL_RPL;
2837 if ((pCtxCore->gs.Sel & X86_SEL_RPL) == 1)
2838 pCtxCore->gs.Sel &= ~X86_SEL_RPL;
2839# ifdef VBOX_WITH_RAW_RING1
2840 }
2841# endif
2842 }
2843 }
2844
2845 return rc;
2846}
2847
2848#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
2849
2850/**
2851 * Updates the EFLAGS while we're in raw-mode.
2852 *
2853 * @param pVCpu Pointer to the VMCPU.
2854 * @param fEfl The new EFLAGS value.
2855 */
2856VMMDECL(void) CPUMRawSetEFlags(PVMCPU pVCpu, uint32_t fEfl)
2857{
2858#ifdef VBOX_WITH_RAW_MODE_NOT_R0
2859 if (pVCpu->cpum.s.fRawEntered)
2860 PATMRawSetEFlags(pVCpu->CTX_SUFF(pVM), CPUMCTX2CORE(&pVCpu->cpum.s.Guest), fEfl);
2861 else
2862#endif
2863 pVCpu->cpum.s.Guest.eflags.u32 = fEfl;
2864}
2865
2866
2867/**
2868 * Gets the EFLAGS while we're in raw-mode.
2869 *
2870 * @returns The eflags.
2871 * @param pVCpu Pointer to the current virtual CPU.
2872 */
2873VMMDECL(uint32_t) CPUMRawGetEFlags(PVMCPU pVCpu)
2874{
2875#ifdef VBOX_WITH_RAW_MODE_NOT_R0
2876 if (pVCpu->cpum.s.fRawEntered)
2877 return PATMRawGetEFlags(pVCpu->CTX_SUFF(pVM), CPUMCTX2CORE(&pVCpu->cpum.s.Guest));
2878#endif
2879 return pVCpu->cpum.s.Guest.eflags.u32;
2880}
2881
2882
2883/**
2884 * Sets the specified changed flags (CPUM_CHANGED_*).
2885 *
2886 * @param pVCpu Pointer to the current virtual CPU.
2887 */
2888VMMDECL(void) CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedFlags)
2889{
2890 pVCpu->cpum.s.fChanged |= fChangedFlags;
2891}
2892
2893
2894/**
2895 * Checks if the CPU supports the FXSAVE and FXRSTOR instruction.
2896 * @returns true if supported.
2897 * @returns false if not supported.
2898 * @param pVM Pointer to the VM.
2899 */
2900VMMDECL(bool) CPUMSupportsFXSR(PVM pVM)
2901{
2902 return pVM->cpum.s.CPUFeatures.edx.u1FXSR != 0;
2903}
2904
2905
2906/**
2907 * Checks if the host OS uses the SYSENTER / SYSEXIT instructions.
2908 * @returns true if used.
2909 * @returns false if not used.
2910 * @param pVM Pointer to the VM.
2911 */
2912VMMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM)
2913{
2914 return RT_BOOL(pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSENTER);
2915}
2916
2917
2918/**
2919 * Checks if the host OS uses the SYSCALL / SYSRET instructions.
2920 * @returns true if used.
2921 * @returns false if not used.
2922 * @param pVM Pointer to the VM.
2923 */
2924VMMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM)
2925{
2926 return RT_BOOL(pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSCALL);
2927}
2928
2929#ifndef IN_RING3
2930
2931/**
2932 * Lazily sync in the FPU/XMM state.
2933 *
2934 * @returns VBox status code.
2935 * @param pVCpu Pointer to the VMCPU.
2936 */
2937VMMDECL(int) CPUMHandleLazyFPU(PVMCPU pVCpu)
2938{
2939 return cpumHandleLazyFPUAsm(&pVCpu->cpum.s);
2940}
2941
2942#endif /* !IN_RING3 */
2943
2944/**
2945 * Checks if we activated the FPU/XMM state of the guest OS.
2946 * @returns true if we did.
2947 * @returns false if not.
2948 * @param pVCpu Pointer to the VMCPU.
2949 */
2950VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCpu)
2951{
2952 return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU);
2953}
2954
2955
2956/**
2957 * Deactivate the FPU/XMM state of the guest OS.
2958 * @param pVCpu Pointer to the VMCPU.
2959 *
2960 * @todo r=bird: Why is this needed? Looks like a workaround for mishandled
2961 * FPU state management.
2962 */
2963VMMDECL(void) CPUMDeactivateGuestFPUState(PVMCPU pVCpu)
2964{
2965 Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU));
2966 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU;
2967}
2968
2969
2970/**
2971 * Checks if the guest debug state is active.
2972 *
2973 * @returns boolean
2974 * @param pVM Pointer to the VM.
2975 */
2976VMMDECL(bool) CPUMIsGuestDebugStateActive(PVMCPU pVCpu)
2977{
2978 return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST);
2979}
2980
2981/**
2982 * Checks if the hyper debug state is active.
2983 *
2984 * @returns boolean
2985 * @param pVM Pointer to the VM.
2986 */
2987VMMDECL(bool) CPUMIsHyperDebugStateActive(PVMCPU pVCpu)
2988{
2989 return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HYPER);
2990}
2991
2992
2993/**
2994 * Mark the guest's debug state as inactive.
2995 *
2996 * @returns boolean
2997 * @param pVM Pointer to the VM.
2998 * @todo This API doesn't make sense any more.
2999 */
3000VMMDECL(void) CPUMDeactivateGuestDebugState(PVMCPU pVCpu)
3001{
3002 Assert(!(pVCpu->cpum.s.fUseFlags & (CPUM_USED_DEBUG_REGS_GUEST | CPUM_USED_DEBUG_REGS_HYPER | CPUM_USED_DEBUG_REGS_HOST)));
3003}
3004
3005
3006/**
3007 * Get the current privilege level of the guest.
3008 *
3009 * @returns CPL
3010 * @param pVCpu Pointer to the current virtual CPU.
3011 */
3012VMMDECL(uint32_t) CPUMGetGuestCPL(PVMCPU pVCpu)
3013{
3014 /*
3015 * CPL can reliably be found in SS.DPL (hidden regs valid) or SS if not.
3016 *
3017 * Note! We used to check CS.DPL here, assuming it was always equal to
3018 * CPL even if a conforming segment was loaded. But this truned out to
3019 * only apply to older AMD-V. With VT-x we had an ACP2 regression
3020 * during install after a far call to ring 2 with VT-x. Then on newer
3021 * AMD-V CPUs we have to move the VMCB.guest.u8CPL into cs.Attr.n.u2Dpl
3022 * as well as ss.Attr.n.u2Dpl to make this (and other) code work right.
3023 *
3024 * So, forget CS.DPL, always use SS.DPL.
3025 *
3026 * Note! The SS RPL is always equal to the CPL, while the CS RPL
3027 * isn't necessarily equal if the segment is conforming.
3028 * See section 4.11.1 in the AMD manual.
3029 *
3030 * Update: Where the heck does it say CS.RPL can differ from CPL other than
3031 * right after real->prot mode switch and when in V8086 mode? That
3032 * section says the RPL specified in a direct transfere (call, jmp,
3033 * ret) is not the one loaded into CS. Besides, if CS.RPL != CPL
3034 * it would be impossible for an exception handle or the iret
3035 * instruction to figure out whether SS:ESP are part of the frame
3036 * or not. VBox or qemu bug must've lead to this misconception.
3037 *
3038 * Update2: On an AMD bulldozer system here, I've no trouble loading a null
3039 * selector into SS with an RPL other than the CPL when CPL != 3 and
3040 * we're in 64-bit mode. The intel dev box doesn't allow this, on
3041 * RPL = CPL. Weird.
3042 */
3043 uint32_t uCpl;
3044 if (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE)
3045 {
3046 if (!pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
3047 {
3048 if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.s.Guest.ss))
3049 uCpl = pVCpu->cpum.s.Guest.ss.Attr.n.u2Dpl;
3050 else
3051 {
3052 uCpl = (pVCpu->cpum.s.Guest.ss.Sel & X86_SEL_RPL);
3053#ifdef VBOX_WITH_RAW_MODE_NOT_R0
3054# ifdef VBOX_WITH_RAW_RING1
3055 if (pVCpu->cpum.s.fRawEntered)
3056 {
3057 if ( uCpl == 2
3058 && EMIsRawRing1Enabled(pVCpu->CTX_SUFF(pVM)))
3059 uCpl = 1;
3060 else if (uCpl == 1)
3061 uCpl = 0;
3062 }
3063 Assert(uCpl != 2); /* ring 2 support not allowed anymore. */
3064# else
3065 if (uCpl == 1)
3066 uCpl = 0;
3067# endif
3068#endif
3069 }
3070 }
3071 else
3072 uCpl = 3; /* V86 has CPL=3; REM doesn't set DPL=3 in V8086 mode. See @bugref{5130}. */
3073 }
3074 else
3075 uCpl = 0; /* Real mode is zero; CPL set to 3 for VT-x real-mode emulation. */
3076 return uCpl;
3077}
3078
3079
3080/**
3081 * Gets the current guest CPU mode.
3082 *
3083 * If paging mode is what you need, check out PGMGetGuestMode().
3084 *
3085 * @returns The CPU mode.
3086 * @param pVCpu Pointer to the VMCPU.
3087 */
3088VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu)
3089{
3090 CPUMMODE enmMode;
3091 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
3092 enmMode = CPUMMODE_REAL;
3093 else if (!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
3094 enmMode = CPUMMODE_PROTECTED;
3095 else
3096 enmMode = CPUMMODE_LONG;
3097
3098 return enmMode;
3099}
3100
3101
3102/**
3103 * Figure whether the CPU is currently executing 16, 32 or 64 bit code.
3104 *
3105 * @returns 16, 32 or 64.
3106 * @param pVCpu The current virtual CPU.
3107 */
3108VMMDECL(uint32_t) CPUMGetGuestCodeBits(PVMCPU pVCpu)
3109{
3110 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
3111 return 16;
3112
3113 if (pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
3114 {
3115 Assert(!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA));
3116 return 16;
3117 }
3118
3119 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
3120 if ( pVCpu->cpum.s.Guest.cs.Attr.n.u1Long
3121 && (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
3122 return 64;
3123
3124 if (pVCpu->cpum.s.Guest.cs.Attr.n.u1DefBig)
3125 return 32;
3126
3127 return 16;
3128}
3129
3130
3131VMMDECL(DISCPUMODE) CPUMGetGuestDisMode(PVMCPU pVCpu)
3132{
3133 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
3134 return DISCPUMODE_16BIT;
3135
3136 if (pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
3137 {
3138 Assert(!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA));
3139 return DISCPUMODE_16BIT;
3140 }
3141
3142 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
3143 if ( pVCpu->cpum.s.Guest.cs.Attr.n.u1Long
3144 && (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
3145 return DISCPUMODE_64BIT;
3146
3147 if (pVCpu->cpum.s.Guest.cs.Attr.n.u1DefBig)
3148 return DISCPUMODE_32BIT;
3149
3150 return DISCPUMODE_16BIT;
3151}
3152
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