VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp@ 48142

Last change on this file since 48142 was 48142, checked in by vboxsync, 11 years ago

intel manuals hints that there should be at least 8 variables one.
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1/* $Id: CPUMAllRegs.cpp 48142 2013-08-29 09:47:29Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor(/Manager) - Getters and Setters.
4 */
5
6/*
7 * Copyright (C) 2006-2012 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_CPUM
23#include <VBox/vmm/cpum.h>
24#include <VBox/vmm/patm.h>
25#include <VBox/vmm/dbgf.h>
26#include <VBox/vmm/pdm.h>
27#include <VBox/vmm/pgm.h>
28#include <VBox/vmm/mm.h>
29#include <VBox/vmm/em.h>
30#if defined(VBOX_WITH_RAW_MODE) && !defined(IN_RING0)
31# include <VBox/vmm/selm.h>
32#endif
33#include "CPUMInternal.h"
34#include <VBox/vmm/vm.h>
35#include <VBox/err.h>
36#include <VBox/dis.h>
37#include <VBox/log.h>
38#include <VBox/vmm/hm.h>
39#include <VBox/vmm/tm.h>
40#include <iprt/assert.h>
41#include <iprt/asm.h>
42#include <iprt/asm-amd64-x86.h>
43#ifdef IN_RING3
44#include <iprt/thread.h>
45#endif
46
47/** Disable stack frame pointer generation here. */
48#if defined(_MSC_VER) && !defined(DEBUG)
49# pragma optimize("y", off)
50#endif
51
52
53/*******************************************************************************
54* Defined Constants And Macros *
55*******************************************************************************/
56/**
57 * Converts a CPUMCPU::Guest pointer into a VMCPU pointer.
58 *
59 * @returns Pointer to the Virtual CPU.
60 * @param a_pGuestCtx Pointer to the guest context.
61 */
62#define CPUM_GUEST_CTX_TO_VMCPU(a_pGuestCtx) RT_FROM_MEMBER(a_pGuestCtx, VMCPU, cpum.s.Guest)
63
64/**
65 * Lazily loads the hidden parts of a selector register when using raw-mode.
66 */
67#if defined(VBOX_WITH_RAW_MODE) && !defined(IN_RING0)
68# define CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(a_pVCpu, a_pSReg) \
69 do \
70 { \
71 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(a_pVCpu, a_pSReg)) \
72 cpumGuestLazyLoadHiddenSelectorReg(a_pVCpu, a_pSReg); \
73 } while (0)
74#else
75# define CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(a_pVCpu, a_pSReg) \
76 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(a_pVCpu, a_pSReg));
77#endif
78
79
80
81#ifdef VBOX_WITH_RAW_MODE_NOT_R0
82
83/**
84 * Does the lazy hidden selector register loading.
85 *
86 * @param pVCpu The current Virtual CPU.
87 * @param pSReg The selector register to lazily load hidden parts of.
88 */
89static void cpumGuestLazyLoadHiddenSelectorReg(PVMCPU pVCpu, PCPUMSELREG pSReg)
90{
91 Assert(!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSReg));
92 Assert(!HMIsEnabled(pVCpu->CTX_SUFF(pVM)));
93 Assert((uintptr_t)(pSReg - &pVCpu->cpum.s.Guest.es) < X86_SREG_COUNT);
94
95 if (pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
96 {
97 /* V8086 mode - Tightly controlled environment, no question about the limit or flags. */
98 pSReg->Attr.u = 0;
99 pSReg->Attr.n.u4Type = pSReg == &pVCpu->cpum.s.Guest.cs ? X86_SEL_TYPE_ER_ACC : X86_SEL_TYPE_RW_ACC;
100 pSReg->Attr.n.u1DescType = 1; /* code/data segment */
101 pSReg->Attr.n.u2Dpl = 3;
102 pSReg->Attr.n.u1Present = 1;
103 pSReg->u32Limit = 0x0000ffff;
104 pSReg->u64Base = (uint32_t)pSReg->Sel << 4;
105 pSReg->ValidSel = pSReg->Sel;
106 pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
107 /** @todo Check what the accessed bit should be (VT-x and AMD-V). */
108 }
109 else if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
110 {
111 /* Real mode - leave the limit and flags alone here, at least for now. */
112 pSReg->u64Base = (uint32_t)pSReg->Sel << 4;
113 pSReg->ValidSel = pSReg->Sel;
114 pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
115 }
116 else
117 {
118 /* Protected mode - get it from the selector descriptor tables. */
119 if (!(pSReg->Sel & X86_SEL_MASK_OFF_RPL))
120 {
121 Assert(!CPUMIsGuestInLongMode(pVCpu));
122 pSReg->Sel = 0;
123 pSReg->u64Base = 0;
124 pSReg->u32Limit = 0;
125 pSReg->Attr.u = 0;
126 pSReg->ValidSel = 0;
127 pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
128 /** @todo see todo in iemHlpLoadNullDataSelectorProt. */
129 }
130 else
131 SELMLoadHiddenSelectorReg(pVCpu, &pVCpu->cpum.s.Guest, pSReg);
132 }
133}
134
135
136/**
137 * Makes sure the hidden CS and SS selector registers are valid, loading them if
138 * necessary.
139 *
140 * @param pVCpu The current virtual CPU.
141 */
142VMM_INT_DECL(void) CPUMGuestLazyLoadHiddenCsAndSs(PVMCPU pVCpu)
143{
144 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
145 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.ss);
146}
147
148
149/**
150 * Loads a the hidden parts of a selector register.
151 *
152 * @param pVCpu The current virtual CPU.
153 */
154VMM_INT_DECL(void) CPUMGuestLazyLoadHiddenSelectorReg(PVMCPU pVCpu, PCPUMSELREG pSReg)
155{
156 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, pSReg);
157}
158
159#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
160
161
162/**
163 * Obsolete.
164 *
165 * We don't support nested hypervisor context interrupts or traps. Life is much
166 * simpler when we don't. It's also slightly faster at times.
167 *
168 * @param pVM Handle to the virtual machine.
169 */
170VMMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVMCPU pVCpu)
171{
172 return CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
173}
174
175
176/**
177 * Gets the pointer to the hypervisor CPU context structure of a virtual CPU.
178 *
179 * @param pVCpu Pointer to the VMCPU.
180 */
181VMMDECL(PCPUMCTX) CPUMGetHyperCtxPtr(PVMCPU pVCpu)
182{
183 return &pVCpu->cpum.s.Hyper;
184}
185
186
187VMMDECL(void) CPUMSetHyperGDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
188{
189 pVCpu->cpum.s.Hyper.gdtr.cbGdt = limit;
190 pVCpu->cpum.s.Hyper.gdtr.pGdt = addr;
191}
192
193
194VMMDECL(void) CPUMSetHyperIDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
195{
196 pVCpu->cpum.s.Hyper.idtr.cbIdt = limit;
197 pVCpu->cpum.s.Hyper.idtr.pIdt = addr;
198}
199
200
201VMMDECL(void) CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3)
202{
203 pVCpu->cpum.s.Hyper.cr3 = cr3;
204
205#ifdef IN_RC
206 /* Update the current CR3. */
207 ASMSetCR3(cr3);
208#endif
209}
210
211VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu)
212{
213 return pVCpu->cpum.s.Hyper.cr3;
214}
215
216
217VMMDECL(void) CPUMSetHyperCS(PVMCPU pVCpu, RTSEL SelCS)
218{
219 pVCpu->cpum.s.Hyper.cs.Sel = SelCS;
220}
221
222
223VMMDECL(void) CPUMSetHyperDS(PVMCPU pVCpu, RTSEL SelDS)
224{
225 pVCpu->cpum.s.Hyper.ds.Sel = SelDS;
226}
227
228
229VMMDECL(void) CPUMSetHyperES(PVMCPU pVCpu, RTSEL SelES)
230{
231 pVCpu->cpum.s.Hyper.es.Sel = SelES;
232}
233
234
235VMMDECL(void) CPUMSetHyperFS(PVMCPU pVCpu, RTSEL SelFS)
236{
237 pVCpu->cpum.s.Hyper.fs.Sel = SelFS;
238}
239
240
241VMMDECL(void) CPUMSetHyperGS(PVMCPU pVCpu, RTSEL SelGS)
242{
243 pVCpu->cpum.s.Hyper.gs.Sel = SelGS;
244}
245
246
247VMMDECL(void) CPUMSetHyperSS(PVMCPU pVCpu, RTSEL SelSS)
248{
249 pVCpu->cpum.s.Hyper.ss.Sel = SelSS;
250}
251
252
253VMMDECL(void) CPUMSetHyperESP(PVMCPU pVCpu, uint32_t u32ESP)
254{
255 pVCpu->cpum.s.Hyper.esp = u32ESP;
256}
257
258
259VMMDECL(void) CPUMSetHyperEDX(PVMCPU pVCpu, uint32_t u32ESP)
260{
261 pVCpu->cpum.s.Hyper.esp = u32ESP;
262}
263
264
265VMMDECL(int) CPUMSetHyperEFlags(PVMCPU pVCpu, uint32_t Efl)
266{
267 pVCpu->cpum.s.Hyper.eflags.u32 = Efl;
268 return VINF_SUCCESS;
269}
270
271
272VMMDECL(void) CPUMSetHyperEIP(PVMCPU pVCpu, uint32_t u32EIP)
273{
274 pVCpu->cpum.s.Hyper.eip = u32EIP;
275}
276
277
278/**
279 * Used by VMMR3RawRunGC to reinitialize the general raw-mode context registers,
280 * EFLAGS and EIP prior to resuming guest execution.
281 *
282 * All general register not given as a parameter will be set to 0. The EFLAGS
283 * register will be set to sane values for C/C++ code execution with interrupts
284 * disabled and IOPL 0.
285 *
286 * @param pVCpu The current virtual CPU.
287 * @param u32EIP The EIP value.
288 * @param u32ESP The ESP value.
289 * @param u32EAX The EAX value.
290 * @param u32EDX The EDX value.
291 */
292VMM_INT_DECL(void) CPUMSetHyperState(PVMCPU pVCpu, uint32_t u32EIP, uint32_t u32ESP, uint32_t u32EAX, uint32_t u32EDX)
293{
294 pVCpu->cpum.s.Hyper.eip = u32EIP;
295 pVCpu->cpum.s.Hyper.esp = u32ESP;
296 pVCpu->cpum.s.Hyper.eax = u32EAX;
297 pVCpu->cpum.s.Hyper.edx = u32EDX;
298 pVCpu->cpum.s.Hyper.ecx = 0;
299 pVCpu->cpum.s.Hyper.ebx = 0;
300 pVCpu->cpum.s.Hyper.ebp = 0;
301 pVCpu->cpum.s.Hyper.esi = 0;
302 pVCpu->cpum.s.Hyper.edi = 0;
303 pVCpu->cpum.s.Hyper.eflags.u = X86_EFL_1;
304}
305
306
307VMMDECL(void) CPUMSetHyperTR(PVMCPU pVCpu, RTSEL SelTR)
308{
309 pVCpu->cpum.s.Hyper.tr.Sel = SelTR;
310}
311
312
313VMMDECL(void) CPUMSetHyperLDTR(PVMCPU pVCpu, RTSEL SelLDTR)
314{
315 pVCpu->cpum.s.Hyper.ldtr.Sel = SelLDTR;
316}
317
318
319/** @MAYBE_LOAD_DRx
320 * Macro for updating DRx values in raw-mode and ring-0 contexts.
321 */
322#ifdef IN_RING0
323# if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
324# ifndef VBOX_WITH_HYBRID_32BIT_KERNEL
325# define MAYBE_LOAD_DRx(a_pVCpu, a_fnLoad, a_uValue) \
326 do { \
327 if (!CPUMIsGuestInLongModeEx(&(a_pVCpu)->cpum.s.Guest)) \
328 a_fnLoad(a_uValue); \
329 else \
330 (a_pVCpu)->cpum.s.fUseFlags |= CPUM_SYNC_DEBUG_REGS_HYPER; \
331 } while (0)
332# else
333# define MAYBE_LOAD_DRx(a_pVCpu, a_fnLoad, a_uValue) \
334 do { \
335 /** @todo we're not loading the correct guest value here! */ \
336 a_fnLoad(a_uValue); \
337 } while (0)
338# endif
339# else
340# define MAYBE_LOAD_DRx(a_pVCpu, a_fnLoad, a_uValue) \
341 do { \
342 a_fnLoad(a_uValue); \
343 } while (0)
344# endif
345
346#elif defined(IN_RC)
347# define MAYBE_LOAD_DRx(a_pVCpu, a_fnLoad, a_uValue) \
348 do { \
349 if ((a_pVCpu)->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HYPER) \
350 { a_fnLoad(a_uValue); } \
351 } while (0)
352
353#else
354# define MAYBE_LOAD_DRx(a_pVCpu, a_fnLoad, a_uValue) do { } while (0)
355#endif
356
357VMMDECL(void) CPUMSetHyperDR0(PVMCPU pVCpu, RTGCUINTREG uDr0)
358{
359 pVCpu->cpum.s.Hyper.dr[0] = uDr0;
360 MAYBE_LOAD_DRx(pVCpu, ASMSetDR0, uDr0);
361}
362
363
364VMMDECL(void) CPUMSetHyperDR1(PVMCPU pVCpu, RTGCUINTREG uDr1)
365{
366 pVCpu->cpum.s.Hyper.dr[1] = uDr1;
367 MAYBE_LOAD_DRx(pVCpu, ASMSetDR1, uDr1);
368}
369
370
371VMMDECL(void) CPUMSetHyperDR2(PVMCPU pVCpu, RTGCUINTREG uDr2)
372{
373 pVCpu->cpum.s.Hyper.dr[2] = uDr2;
374 MAYBE_LOAD_DRx(pVCpu, ASMSetDR2, uDr2);
375}
376
377
378VMMDECL(void) CPUMSetHyperDR3(PVMCPU pVCpu, RTGCUINTREG uDr3)
379{
380 pVCpu->cpum.s.Hyper.dr[3] = uDr3;
381 MAYBE_LOAD_DRx(pVCpu, ASMSetDR3, uDr3);
382}
383
384
385VMMDECL(void) CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6)
386{
387 pVCpu->cpum.s.Hyper.dr[6] = uDr6;
388}
389
390
391VMMDECL(void) CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7)
392{
393 pVCpu->cpum.s.Hyper.dr[7] = uDr7;
394#ifdef IN_RC
395 MAYBE_LOAD_DRx(pVCpu, ASMSetDR7, uDr7);
396#endif
397}
398
399
400VMMDECL(RTSEL) CPUMGetHyperCS(PVMCPU pVCpu)
401{
402 return pVCpu->cpum.s.Hyper.cs.Sel;
403}
404
405
406VMMDECL(RTSEL) CPUMGetHyperDS(PVMCPU pVCpu)
407{
408 return pVCpu->cpum.s.Hyper.ds.Sel;
409}
410
411
412VMMDECL(RTSEL) CPUMGetHyperES(PVMCPU pVCpu)
413{
414 return pVCpu->cpum.s.Hyper.es.Sel;
415}
416
417
418VMMDECL(RTSEL) CPUMGetHyperFS(PVMCPU pVCpu)
419{
420 return pVCpu->cpum.s.Hyper.fs.Sel;
421}
422
423
424VMMDECL(RTSEL) CPUMGetHyperGS(PVMCPU pVCpu)
425{
426 return pVCpu->cpum.s.Hyper.gs.Sel;
427}
428
429
430VMMDECL(RTSEL) CPUMGetHyperSS(PVMCPU pVCpu)
431{
432 return pVCpu->cpum.s.Hyper.ss.Sel;
433}
434
435
436VMMDECL(uint32_t) CPUMGetHyperEAX(PVMCPU pVCpu)
437{
438 return pVCpu->cpum.s.Hyper.eax;
439}
440
441
442VMMDECL(uint32_t) CPUMGetHyperEBX(PVMCPU pVCpu)
443{
444 return pVCpu->cpum.s.Hyper.ebx;
445}
446
447
448VMMDECL(uint32_t) CPUMGetHyperECX(PVMCPU pVCpu)
449{
450 return pVCpu->cpum.s.Hyper.ecx;
451}
452
453
454VMMDECL(uint32_t) CPUMGetHyperEDX(PVMCPU pVCpu)
455{
456 return pVCpu->cpum.s.Hyper.edx;
457}
458
459
460VMMDECL(uint32_t) CPUMGetHyperESI(PVMCPU pVCpu)
461{
462 return pVCpu->cpum.s.Hyper.esi;
463}
464
465
466VMMDECL(uint32_t) CPUMGetHyperEDI(PVMCPU pVCpu)
467{
468 return pVCpu->cpum.s.Hyper.edi;
469}
470
471
472VMMDECL(uint32_t) CPUMGetHyperEBP(PVMCPU pVCpu)
473{
474 return pVCpu->cpum.s.Hyper.ebp;
475}
476
477
478VMMDECL(uint32_t) CPUMGetHyperESP(PVMCPU pVCpu)
479{
480 return pVCpu->cpum.s.Hyper.esp;
481}
482
483
484VMMDECL(uint32_t) CPUMGetHyperEFlags(PVMCPU pVCpu)
485{
486 return pVCpu->cpum.s.Hyper.eflags.u32;
487}
488
489
490VMMDECL(uint32_t) CPUMGetHyperEIP(PVMCPU pVCpu)
491{
492 return pVCpu->cpum.s.Hyper.eip;
493}
494
495
496VMMDECL(uint64_t) CPUMGetHyperRIP(PVMCPU pVCpu)
497{
498 return pVCpu->cpum.s.Hyper.rip;
499}
500
501
502VMMDECL(uint32_t) CPUMGetHyperIDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
503{
504 if (pcbLimit)
505 *pcbLimit = pVCpu->cpum.s.Hyper.idtr.cbIdt;
506 return pVCpu->cpum.s.Hyper.idtr.pIdt;
507}
508
509
510VMMDECL(uint32_t) CPUMGetHyperGDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
511{
512 if (pcbLimit)
513 *pcbLimit = pVCpu->cpum.s.Hyper.gdtr.cbGdt;
514 return pVCpu->cpum.s.Hyper.gdtr.pGdt;
515}
516
517
518VMMDECL(RTSEL) CPUMGetHyperLDTR(PVMCPU pVCpu)
519{
520 return pVCpu->cpum.s.Hyper.ldtr.Sel;
521}
522
523
524VMMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVMCPU pVCpu)
525{
526 return pVCpu->cpum.s.Hyper.dr[0];
527}
528
529
530VMMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVMCPU pVCpu)
531{
532 return pVCpu->cpum.s.Hyper.dr[1];
533}
534
535
536VMMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVMCPU pVCpu)
537{
538 return pVCpu->cpum.s.Hyper.dr[2];
539}
540
541
542VMMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVMCPU pVCpu)
543{
544 return pVCpu->cpum.s.Hyper.dr[3];
545}
546
547
548VMMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVMCPU pVCpu)
549{
550 return pVCpu->cpum.s.Hyper.dr[6];
551}
552
553
554VMMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVMCPU pVCpu)
555{
556 return pVCpu->cpum.s.Hyper.dr[7];
557}
558
559
560/**
561 * Gets the pointer to the internal CPUMCTXCORE structure.
562 * This is only for reading in order to save a few calls.
563 *
564 * @param pVCpu Handle to the virtual cpu.
565 */
566VMMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVMCPU pVCpu)
567{
568 return CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
569}
570
571
572/**
573 * Queries the pointer to the internal CPUMCTX structure.
574 *
575 * @returns The CPUMCTX pointer.
576 * @param pVCpu Handle to the virtual cpu.
577 */
578VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu)
579{
580 return &pVCpu->cpum.s.Guest;
581}
582
583VMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit)
584{
585#ifdef VBOX_WITH_IEM
586# ifdef VBOX_WITH_RAW_MODE_NOT_R0
587 if (!HMIsEnabled(pVCpu->CTX_SUFF(pVM)))
588 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
589# endif
590#endif
591 pVCpu->cpum.s.Guest.gdtr.cbGdt = cbLimit;
592 pVCpu->cpum.s.Guest.gdtr.pGdt = GCPtrBase;
593 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GDTR;
594 return VINF_SUCCESS; /* formality, consider it void. */
595}
596
597VMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit)
598{
599#ifdef VBOX_WITH_IEM
600# ifdef VBOX_WITH_RAW_MODE_NOT_R0
601 if (!HMIsEnabled(pVCpu->CTX_SUFF(pVM)))
602 VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
603# endif
604#endif
605 pVCpu->cpum.s.Guest.idtr.cbIdt = cbLimit;
606 pVCpu->cpum.s.Guest.idtr.pIdt = GCPtrBase;
607 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_IDTR;
608 return VINF_SUCCESS; /* formality, consider it void. */
609}
610
611VMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr)
612{
613#ifdef VBOX_WITH_IEM
614# ifdef VBOX_WITH_RAW_MODE_NOT_R0
615 if (!HMIsEnabled(pVCpu->CTX_SUFF(pVM)))
616 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
617# endif
618#endif
619 pVCpu->cpum.s.Guest.tr.Sel = tr;
620 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_TR;
621 return VINF_SUCCESS; /* formality, consider it void. */
622}
623
624VMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr)
625{
626#ifdef VBOX_WITH_IEM
627# ifdef VBOX_WITH_RAW_MODE_NOT_R0
628 if ( ( ldtr != 0
629 || pVCpu->cpum.s.Guest.ldtr.Sel != 0)
630 && !HMIsEnabled(pVCpu->CTX_SUFF(pVM)))
631 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
632# endif
633#endif
634 pVCpu->cpum.s.Guest.ldtr.Sel = ldtr;
635 /* The caller will set more hidden bits if it has them. */
636 pVCpu->cpum.s.Guest.ldtr.ValidSel = 0;
637 pVCpu->cpum.s.Guest.ldtr.fFlags = 0;
638 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_LDTR;
639 return VINF_SUCCESS; /* formality, consider it void. */
640}
641
642
643/**
644 * Set the guest CR0.
645 *
646 * When called in GC, the hyper CR0 may be updated if that is
647 * required. The caller only has to take special action if AM,
648 * WP, PG or PE changes.
649 *
650 * @returns VINF_SUCCESS (consider it void).
651 * @param pVCpu Handle to the virtual cpu.
652 * @param cr0 The new CR0 value.
653 */
654VMMDECL(int) CPUMSetGuestCR0(PVMCPU pVCpu, uint64_t cr0)
655{
656#ifdef IN_RC
657 /*
658 * Check if we need to change hypervisor CR0 because
659 * of math stuff.
660 */
661 if ( (cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP))
662 != (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP)))
663 {
664 if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU))
665 {
666 /*
667 * We haven't saved the host FPU state yet, so TS and MT are both set
668 * and EM should be reflecting the guest EM (it always does this).
669 */
670 if ((cr0 & X86_CR0_EM) != (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM))
671 {
672 uint32_t HyperCR0 = ASMGetCR0();
673 AssertMsg((HyperCR0 & (X86_CR0_TS | X86_CR0_MP)) == (X86_CR0_TS | X86_CR0_MP), ("%#x\n", HyperCR0));
674 AssertMsg((HyperCR0 & X86_CR0_EM) == (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM), ("%#x\n", HyperCR0));
675 HyperCR0 &= ~X86_CR0_EM;
676 HyperCR0 |= cr0 & X86_CR0_EM;
677 Log(("CPUM New HyperCR0=%#x\n", HyperCR0));
678 ASMSetCR0(HyperCR0);
679 }
680# ifdef VBOX_STRICT
681 else
682 {
683 uint32_t HyperCR0 = ASMGetCR0();
684 AssertMsg((HyperCR0 & (X86_CR0_TS | X86_CR0_MP)) == (X86_CR0_TS | X86_CR0_MP), ("%#x\n", HyperCR0));
685 AssertMsg((HyperCR0 & X86_CR0_EM) == (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM), ("%#x\n", HyperCR0));
686 }
687# endif
688 }
689 else
690 {
691 /*
692 * Already saved the state, so we're just mirroring
693 * the guest flags.
694 */
695 uint32_t HyperCR0 = ASMGetCR0();
696 AssertMsg( (HyperCR0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP))
697 == (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP)),
698 ("%#x %#x\n", HyperCR0, pVCpu->cpum.s.Guest.cr0));
699 HyperCR0 &= ~(X86_CR0_TS | X86_CR0_EM | X86_CR0_MP);
700 HyperCR0 |= cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP);
701 Log(("CPUM New HyperCR0=%#x\n", HyperCR0));
702 ASMSetCR0(HyperCR0);
703 }
704 }
705#endif /* IN_RC */
706
707 /*
708 * Check for changes causing TLB flushes (for REM).
709 * The caller is responsible for calling PGM when appropriate.
710 */
711 if ( (cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE))
712 != (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)))
713 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
714 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR0;
715
716 /*
717 * Let PGM know if the WP goes from 0 to 1 (netware WP0+RO+US hack)
718 */
719 if (((cr0 ^ pVCpu->cpum.s.Guest.cr0) & X86_CR0_WP) && (cr0 & X86_CR0_WP))
720 PGMCr0WpEnabled(pVCpu);
721
722 pVCpu->cpum.s.Guest.cr0 = cr0 | X86_CR0_ET;
723 return VINF_SUCCESS;
724}
725
726
727VMMDECL(int) CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2)
728{
729 pVCpu->cpum.s.Guest.cr2 = cr2;
730 return VINF_SUCCESS;
731}
732
733
734VMMDECL(int) CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3)
735{
736 pVCpu->cpum.s.Guest.cr3 = cr3;
737 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR3;
738 return VINF_SUCCESS;
739}
740
741
742VMMDECL(int) CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4)
743{
744 if ( (cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE))
745 != (pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE)))
746 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
747 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR4;
748 if (!CPUMSupportsFXSR(pVCpu->CTX_SUFF(pVM)))
749 cr4 &= ~X86_CR4_OSFSXR;
750 pVCpu->cpum.s.Guest.cr4 = cr4;
751 return VINF_SUCCESS;
752}
753
754
755VMMDECL(int) CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags)
756{
757 pVCpu->cpum.s.Guest.eflags.u32 = eflags;
758 return VINF_SUCCESS;
759}
760
761
762VMMDECL(int) CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip)
763{
764 pVCpu->cpum.s.Guest.eip = eip;
765 return VINF_SUCCESS;
766}
767
768
769VMMDECL(int) CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax)
770{
771 pVCpu->cpum.s.Guest.eax = eax;
772 return VINF_SUCCESS;
773}
774
775
776VMMDECL(int) CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx)
777{
778 pVCpu->cpum.s.Guest.ebx = ebx;
779 return VINF_SUCCESS;
780}
781
782
783VMMDECL(int) CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx)
784{
785 pVCpu->cpum.s.Guest.ecx = ecx;
786 return VINF_SUCCESS;
787}
788
789
790VMMDECL(int) CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx)
791{
792 pVCpu->cpum.s.Guest.edx = edx;
793 return VINF_SUCCESS;
794}
795
796
797VMMDECL(int) CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp)
798{
799 pVCpu->cpum.s.Guest.esp = esp;
800 return VINF_SUCCESS;
801}
802
803
804VMMDECL(int) CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp)
805{
806 pVCpu->cpum.s.Guest.ebp = ebp;
807 return VINF_SUCCESS;
808}
809
810
811VMMDECL(int) CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi)
812{
813 pVCpu->cpum.s.Guest.esi = esi;
814 return VINF_SUCCESS;
815}
816
817
818VMMDECL(int) CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi)
819{
820 pVCpu->cpum.s.Guest.edi = edi;
821 return VINF_SUCCESS;
822}
823
824
825VMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss)
826{
827 pVCpu->cpum.s.Guest.ss.Sel = ss;
828 return VINF_SUCCESS;
829}
830
831
832VMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs)
833{
834 pVCpu->cpum.s.Guest.cs.Sel = cs;
835 return VINF_SUCCESS;
836}
837
838
839VMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds)
840{
841 pVCpu->cpum.s.Guest.ds.Sel = ds;
842 return VINF_SUCCESS;
843}
844
845
846VMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es)
847{
848 pVCpu->cpum.s.Guest.es.Sel = es;
849 return VINF_SUCCESS;
850}
851
852
853VMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs)
854{
855 pVCpu->cpum.s.Guest.fs.Sel = fs;
856 return VINF_SUCCESS;
857}
858
859
860VMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs)
861{
862 pVCpu->cpum.s.Guest.gs.Sel = gs;
863 return VINF_SUCCESS;
864}
865
866
867VMMDECL(void) CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val)
868{
869 pVCpu->cpum.s.Guest.msrEFER = val;
870}
871
872
873/**
874 * Query an MSR.
875 *
876 * The caller is responsible for checking privilege if the call is the result
877 * of a RDMSR instruction. We'll do the rest.
878 *
879 * @retval VINF_SUCCESS on success.
880 * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR), the caller is
881 * expected to take the appropriate actions. @a *puValue is set to 0.
882 * @param pVCpu Pointer to the VMCPU.
883 * @param idMsr The MSR.
884 * @param puValue Where to return the value.
885 *
886 * @remarks This will always return the right values, even when we're in the
887 * recompiler.
888 */
889VMMDECL(int) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue)
890{
891 /*
892 * If we don't indicate MSR support in the CPUID feature bits, indicate
893 * that a #GP(0) should be raised.
894 */
895 if (!(pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_MSR))
896 {
897 *puValue = 0;
898 return VERR_CPUM_RAISE_GP_0; /** @todo isn't \#UD more correct if not supported? */
899 }
900
901 int rc = VINF_SUCCESS;
902 uint8_t const u8Multiplier = 4;
903 switch (idMsr)
904 {
905 case MSR_IA32_TSC:
906 *puValue = TMCpuTickGet(pVCpu);
907 break;
908
909 case MSR_IA32_APICBASE:
910 {
911 PVM pVM = pVCpu->CTX_SUFF(pVM);
912 if ( ( pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1 /* APIC Std feature */
913 && (pVM->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_APIC))
914 || ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001 /* APIC Ext feature (AMD) */
915 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD
916 && (pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_AMD_FEATURE_EDX_APIC))
917 || ( pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1 /* x2APIC */
918 && (pVM->cpum.s.aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_X2APIC)))
919 {
920 *puValue = pVCpu->cpum.s.Guest.msrApicBase;
921 }
922 else
923 {
924 *puValue = 0;
925 rc = VERR_CPUM_RAISE_GP_0;
926 }
927 break;
928 }
929
930 case MSR_IA32_CR_PAT:
931 *puValue = pVCpu->cpum.s.Guest.msrPAT;
932 break;
933
934 case MSR_IA32_SYSENTER_CS:
935 *puValue = pVCpu->cpum.s.Guest.SysEnter.cs;
936 break;
937
938 case MSR_IA32_SYSENTER_EIP:
939 *puValue = pVCpu->cpum.s.Guest.SysEnter.eip;
940 break;
941
942 case MSR_IA32_SYSENTER_ESP:
943 *puValue = pVCpu->cpum.s.Guest.SysEnter.esp;
944 break;
945
946 case MSR_IA32_MTRR_CAP:
947 {
948 /* This is currently a bit weird. :-) */
949 uint8_t const cVariableRangeRegs = 0;
950 bool const fSystemManagementRangeRegisters = false;
951 bool const fFixedRangeRegisters = false;
952 bool const fWriteCombiningType = false;
953 *puValue = cVariableRangeRegs
954 | (fFixedRangeRegisters ? RT_BIT_64(8) : 0)
955 | (fWriteCombiningType ? RT_BIT_64(10) : 0)
956 | (fSystemManagementRangeRegisters ? RT_BIT_64(11) : 0);
957 break;
958 }
959
960 case IA32_MTRR_PHYSBASE0: case IA32_MTRR_PHYSMASK0:
961 case IA32_MTRR_PHYSBASE1: case IA32_MTRR_PHYSMASK1:
962 case IA32_MTRR_PHYSBASE2: case IA32_MTRR_PHYSMASK2:
963 case IA32_MTRR_PHYSBASE3: case IA32_MTRR_PHYSMASK3:
964 case IA32_MTRR_PHYSBASE4: case IA32_MTRR_PHYSMASK4:
965 case IA32_MTRR_PHYSBASE5: case IA32_MTRR_PHYSMASK5:
966 case IA32_MTRR_PHYSBASE6: case IA32_MTRR_PHYSMASK6:
967 case IA32_MTRR_PHYSBASE7: case IA32_MTRR_PHYSMASK7:
968 /** @todo implement variable MTRRs. */
969 *puValue = 0;
970 break;
971#if 0 /** @todo newer CPUs have more, figure since when and do selective GP(). */
972 case IA32_MTRR_PHYSBASE8: case IA32_MTRR_PHYSMASK8:
973 case IA32_MTRR_PHYSBASE9: case IA32_MTRR_PHYSMASK9:
974 *puValue = 0;
975 break;
976#endif
977
978 case MSR_IA32_MTRR_DEF_TYPE:
979 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType;
980 break;
981
982 case IA32_MTRR_FIX64K_00000:
983 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix64K_00000;
984 break;
985 case IA32_MTRR_FIX16K_80000:
986 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_80000;
987 break;
988 case IA32_MTRR_FIX16K_A0000:
989 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_A0000;
990 break;
991 case IA32_MTRR_FIX4K_C0000:
992 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C0000;
993 break;
994 case IA32_MTRR_FIX4K_C8000:
995 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C8000;
996 break;
997 case IA32_MTRR_FIX4K_D0000:
998 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D0000;
999 break;
1000 case IA32_MTRR_FIX4K_D8000:
1001 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D8000;
1002 break;
1003 case IA32_MTRR_FIX4K_E0000:
1004 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E0000;
1005 break;
1006 case IA32_MTRR_FIX4K_E8000:
1007 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E8000;
1008 break;
1009 case IA32_MTRR_FIX4K_F0000:
1010 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F0000;
1011 break;
1012 case IA32_MTRR_FIX4K_F8000:
1013 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F8000;
1014 break;
1015
1016 case MSR_K6_EFER:
1017 *puValue = pVCpu->cpum.s.Guest.msrEFER;
1018 break;
1019
1020 case MSR_K8_SF_MASK:
1021 *puValue = pVCpu->cpum.s.Guest.msrSFMASK;
1022 break;
1023
1024 case MSR_K6_STAR:
1025 *puValue = pVCpu->cpum.s.Guest.msrSTAR;
1026 break;
1027
1028 case MSR_K8_LSTAR:
1029 *puValue = pVCpu->cpum.s.Guest.msrLSTAR;
1030 break;
1031
1032 case MSR_K8_CSTAR:
1033 *puValue = pVCpu->cpum.s.Guest.msrCSTAR;
1034 break;
1035
1036 case MSR_K8_FS_BASE:
1037 *puValue = pVCpu->cpum.s.Guest.fs.u64Base;
1038 break;
1039
1040 case MSR_K8_GS_BASE:
1041 *puValue = pVCpu->cpum.s.Guest.gs.u64Base;
1042 break;
1043
1044 case MSR_K8_KERNEL_GS_BASE:
1045 *puValue = pVCpu->cpum.s.Guest.msrKERNELGSBASE;
1046 break;
1047
1048 case MSR_K8_TSC_AUX:
1049 *puValue = pVCpu->cpum.s.GuestMsrs.msr.TscAux;
1050 break;
1051
1052 case MSR_IA32_PERF_STATUS:
1053 /** @todo could really be not exactly correct, maybe use host's values */
1054 *puValue = UINT64_C(1000) /* TSC increment by tick */
1055 | ((uint64_t)u8Multiplier << 24) /* CPU multiplier (aka bus ratio) min */
1056 | ((uint64_t)u8Multiplier << 40) /* CPU multiplier (aka bus ratio) max */;
1057 break;
1058
1059 case MSR_IA32_FSB_CLOCK_STS:
1060 /*
1061 * Encoded as:
1062 * 0 - 266
1063 * 1 - 133
1064 * 2 - 200
1065 * 3 - return 166
1066 * 5 - return 100
1067 */
1068 *puValue = (2 << 4);
1069 break;
1070
1071 case MSR_IA32_PLATFORM_INFO:
1072 *puValue = (u8Multiplier << 8) /* Flex ratio max */
1073 | ((uint64_t)u8Multiplier << 40) /* Flex ratio min */;
1074 break;
1075
1076 case MSR_IA32_THERM_STATUS:
1077 /* CPU temperature relative to TCC, to actually activate, CPUID leaf 6 EAX[0] must be set */
1078 *puValue = RT_BIT(31) /* validity bit */
1079 | (UINT64_C(20) << 16) /* degrees till TCC */;
1080 break;
1081
1082 case MSR_IA32_MISC_ENABLE:
1083#if 0
1084 /* Needs to be tested more before enabling. */
1085 *puValue = pVCpu->cpum.s.GuestMsr.msr.miscEnable;
1086#else
1087 /* Currenty we don't allow guests to modify enable MSRs. */
1088 *puValue = MSR_IA32_MISC_ENABLE_FAST_STRINGS /* by default */;
1089
1090 if ((pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR) != 0)
1091
1092 *puValue |= MSR_IA32_MISC_ENABLE_MONITOR /* if mwait/monitor available */;
1093 /** @todo: add more cpuid-controlled features this way. */
1094#endif
1095 break;
1096
1097 /** @todo virtualize DEBUGCTL and relatives */
1098 case MSR_IA32_DEBUGCTL:
1099 *puValue = 0;
1100 break;
1101
1102#if 0 /*def IN_RING0 */
1103 case MSR_IA32_PLATFORM_ID:
1104 case MSR_IA32_BIOS_SIGN_ID:
1105 if (CPUMGetCPUVendor(pVM) == CPUMCPUVENDOR_INTEL)
1106 {
1107 /* Available since the P6 family. VT-x implies that this feature is present. */
1108 if (idMsr == MSR_IA32_PLATFORM_ID)
1109 *puValue = ASMRdMsr(MSR_IA32_PLATFORM_ID);
1110 else if (idMsr == MSR_IA32_BIOS_SIGN_ID)
1111 *puValue = ASMRdMsr(MSR_IA32_BIOS_SIGN_ID);
1112 break;
1113 }
1114 /* no break */
1115#endif
1116 /*
1117 * The BIOS_SIGN_ID MSR and MSR_IA32_MCP_CAP et al exist on AMD64 as
1118 * well, at least bulldozer have them. Windows 7 is querying them.
1119 * XP has been observed querying MSR_IA32_MC0_CTL.
1120 */
1121 case MSR_IA32_BIOS_SIGN_ID: /* fam/mod >= 6_01 */
1122 case MSR_IA32_MCG_CAP: /* fam/mod >= 6_01 */
1123 case MSR_IA32_MCG_STATUS: /* indicated as not present in CAP */
1124 /*case MSR_IA32_MCG_CTRL: - indicated as not present in CAP */
1125 case MSR_IA32_MC0_CTL:
1126 case MSR_IA32_MC0_STATUS:
1127 *puValue = 0;
1128 break;
1129
1130
1131 /*
1132 * Intel specifics MSRs:
1133 */
1134 case MSR_IA32_PLATFORM_ID: /* fam/mod >= 6_01 */
1135 /*case MSR_IA32_BIOS_UPDT_TRIG: - write-only? */
1136 case MSR_RAPL_POWER_UNIT:
1137 case MSR_BBL_CR_CTL3: /* ca. core arch? */
1138 *puValue = 0;
1139 if (CPUMGetGuestCpuVendor(pVCpu->CTX_SUFF(pVM)) != CPUMCPUVENDOR_INTEL)
1140 {
1141 Log(("MSR %#x is Intel, the virtual CPU isn't an Intel one -> #GP\n", idMsr));
1142 rc = VERR_CPUM_RAISE_GP_0;
1143 break;
1144 }
1145
1146 /* Provide more plausive values for some of them. */
1147 switch (idMsr)
1148 {
1149 case MSR_RAPL_POWER_UNIT:
1150 *puValue = RT_MAKE_U32_FROM_U8(3 /* power units (1/8 W)*/,
1151 16 /* 15.3 micro-Joules */,
1152 10 /* 976 microseconds increments */,
1153 0);
1154 break;
1155 case MSR_BBL_CR_CTL3:
1156 *puValue = RT_MAKE_U32_FROM_U8(1, /* bit 0 - L2 Hardware Enabled. (RO) */
1157 1, /* bit 8 - L2 Enabled (R/W). */
1158 0, /* bit 23 - L2 Not Present (RO). */
1159 0);
1160 break;
1161 }
1162 break;
1163
1164
1165 /*
1166 * AMD specific MSRs:
1167 */
1168 case MSR_K8_SYSCFG:
1169 case MSR_K8_INT_PENDING:
1170 case MSR_K8_NB_CFG: /* (All known values are 0 on reset.) */
1171 case MSR_K8_HWCR: /* Very interesting bits here. :) */
1172 case MSR_K8_VM_CR: /* Windows 8 */
1173 *puValue = 0;
1174 if (CPUMGetGuestCpuVendor(pVCpu->CTX_SUFF(pVM)) != CPUMCPUVENDOR_AMD)
1175 {
1176 Log(("MSR %#x is AMD, the virtual CPU isn't an Intel one -> #GP\n", idMsr));
1177 return VERR_CPUM_RAISE_GP_0;
1178 }
1179 /* ignored */
1180 break;
1181
1182 default:
1183 /*
1184 * Hand the X2APIC range to PDM and the APIC.
1185 */
1186 if ( idMsr >= MSR_IA32_X2APIC_START
1187 && idMsr <= MSR_IA32_X2APIC_END)
1188 {
1189 rc = PDMApicReadMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, puValue);
1190 if (RT_SUCCESS(rc))
1191 rc = VINF_SUCCESS;
1192 else
1193 {
1194 *puValue = 0;
1195 rc = VERR_CPUM_RAISE_GP_0;
1196 }
1197 }
1198 else
1199 {
1200 *puValue = 0;
1201 rc = VERR_CPUM_RAISE_GP_0;
1202 }
1203 break;
1204 }
1205
1206 return rc;
1207}
1208
1209
1210/**
1211 * Sets the MSR.
1212 *
1213 * The caller is responsible for checking privilege if the call is the result
1214 * of a WRMSR instruction. We'll do the rest.
1215 *
1216 * @retval VINF_SUCCESS on success.
1217 * @retval VERR_CPUM_RAISE_GP_0 on failure, the caller is expected to take the
1218 * appropriate actions.
1219 *
1220 * @param pVCpu Pointer to the VMCPU.
1221 * @param idMsr The MSR id.
1222 * @param uValue The value to set.
1223 *
1224 * @remarks Everyone changing MSR values, including the recompiler, shall do it
1225 * by calling this method. This makes sure we have current values and
1226 * that we trigger all the right actions when something changes.
1227 */
1228VMMDECL(int) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue)
1229{
1230 /*
1231 * If we don't indicate MSR support in the CPUID feature bits, indicate
1232 * that a #GP(0) should be raised.
1233 */
1234 if (!(pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_MSR))
1235 return VERR_CPUM_RAISE_GP_0; /** @todo isn't \#UD more correct if not supported? */
1236
1237 int rc = VINF_SUCCESS;
1238 switch (idMsr)
1239 {
1240 case MSR_IA32_MISC_ENABLE:
1241 pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = uValue;
1242 break;
1243
1244 case MSR_IA32_TSC:
1245 TMCpuTickSet(pVCpu->CTX_SUFF(pVM), pVCpu, uValue);
1246 break;
1247
1248 case MSR_IA32_APICBASE:
1249 rc = PDMApicSetBase(pVCpu, uValue);
1250 if (rc != VINF_SUCCESS)
1251 rc = VERR_CPUM_RAISE_GP_0;
1252 break;
1253
1254 case MSR_IA32_CR_PAT:
1255 pVCpu->cpum.s.Guest.msrPAT = uValue;
1256 break;
1257
1258 case MSR_IA32_SYSENTER_CS:
1259 pVCpu->cpum.s.Guest.SysEnter.cs = uValue & 0xffff; /* 16 bits selector */
1260 break;
1261
1262 case MSR_IA32_SYSENTER_EIP:
1263 pVCpu->cpum.s.Guest.SysEnter.eip = uValue;
1264 break;
1265
1266 case MSR_IA32_SYSENTER_ESP:
1267 pVCpu->cpum.s.Guest.SysEnter.esp = uValue;
1268 break;
1269
1270 case MSR_IA32_MTRR_CAP:
1271 return VERR_CPUM_RAISE_GP_0;
1272
1273 case MSR_IA32_MTRR_DEF_TYPE:
1274 if ( (uValue & UINT64_C(0xfffffffffffff300))
1275 || ( (uValue & 0xff) != 0
1276 && (uValue & 0xff) != 1
1277 && (uValue & 0xff) != 4
1278 && (uValue & 0xff) != 5
1279 && (uValue & 0xff) != 6) )
1280 {
1281 Log(("MSR_IA32_MTRR_DEF_TYPE: #GP(0) - writing reserved value (%#llx)\n", uValue));
1282 return VERR_CPUM_RAISE_GP_0;
1283 }
1284 pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType = uValue;
1285 break;
1286
1287 case IA32_MTRR_PHYSBASE0: case IA32_MTRR_PHYSMASK0:
1288 case IA32_MTRR_PHYSBASE1: case IA32_MTRR_PHYSMASK1:
1289 case IA32_MTRR_PHYSBASE2: case IA32_MTRR_PHYSMASK2:
1290 case IA32_MTRR_PHYSBASE3: case IA32_MTRR_PHYSMASK3:
1291 case IA32_MTRR_PHYSBASE4: case IA32_MTRR_PHYSMASK4:
1292 case IA32_MTRR_PHYSBASE5: case IA32_MTRR_PHYSMASK5:
1293 case IA32_MTRR_PHYSBASE6: case IA32_MTRR_PHYSMASK6:
1294 case IA32_MTRR_PHYSBASE7: case IA32_MTRR_PHYSMASK7:
1295 /** @todo implement variable MTRRs. */
1296 break;
1297#if 0 /** @todo newer CPUs have more, figure since when and do selective GP(). */
1298 case IA32_MTRR_PHYSBASE8: case IA32_MTRR_PHYSMASK8:
1299 case IA32_MTRR_PHYSBASE9: case IA32_MTRR_PHYSMASK9:
1300 break;
1301#endif
1302
1303 case IA32_MTRR_FIX64K_00000:
1304 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix64K_00000 = uValue;
1305 break;
1306 case IA32_MTRR_FIX16K_80000:
1307 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_80000 = uValue;
1308 break;
1309 case IA32_MTRR_FIX16K_A0000:
1310 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_A0000 = uValue;
1311 break;
1312 case IA32_MTRR_FIX4K_C0000:
1313 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C0000 = uValue;
1314 break;
1315 case IA32_MTRR_FIX4K_C8000:
1316 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C8000 = uValue;
1317 break;
1318 case IA32_MTRR_FIX4K_D0000:
1319 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D0000 = uValue;
1320 break;
1321 case IA32_MTRR_FIX4K_D8000:
1322 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D8000 = uValue;
1323 break;
1324 case IA32_MTRR_FIX4K_E0000:
1325 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E0000 = uValue;
1326 break;
1327 case IA32_MTRR_FIX4K_E8000:
1328 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E8000 = uValue;
1329 break;
1330 case IA32_MTRR_FIX4K_F0000:
1331 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F0000 = uValue;
1332 break;
1333 case IA32_MTRR_FIX4K_F8000:
1334 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F8000 = uValue;
1335 break;
1336
1337 /*
1338 * AMD64 MSRs.
1339 */
1340 case MSR_K6_EFER:
1341 {
1342 PVM pVM = pVCpu->CTX_SUFF(pVM);
1343 uint64_t const uOldEFER = pVCpu->cpum.s.Guest.msrEFER;
1344 uint32_t const fExtFeatures = pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1345 ? pVM->cpum.s.aGuestCpuIdExt[1].edx
1346 : 0;
1347 uint64_t fMask = 0;
1348
1349 /* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
1350 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_NX)
1351 fMask |= MSR_K6_EFER_NXE;
1352 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
1353 fMask |= MSR_K6_EFER_LME;
1354 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
1355 fMask |= MSR_K6_EFER_SCE;
1356 if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1357 fMask |= MSR_K6_EFER_FFXSR;
1358
1359 /* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if
1360 paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1361 if ( (uOldEFER & MSR_K6_EFER_LME) != (uValue & fMask & MSR_K6_EFER_LME)
1362 && (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG))
1363 {
1364 Log(("Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
1365 return VERR_CPUM_RAISE_GP_0;
1366 }
1367
1368 /* There are a few more: e.g. MSR_K6_EFER_LMSLE */
1369 AssertMsg(!(uValue & ~(MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA /* ignored anyway */ | MSR_K6_EFER_SCE | MSR_K6_EFER_FFXSR)),
1370 ("Unexpected value %RX64\n", uValue));
1371 pVCpu->cpum.s.Guest.msrEFER = (uOldEFER & ~fMask) | (uValue & fMask);
1372
1373 /* AMD64 Architecture Programmer's Manual: 15.15 TLB Control; flush the TLB
1374 if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
1375 if ( (uOldEFER & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA))
1376 != (pVCpu->cpum.s.Guest.msrEFER & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA)))
1377 {
1378 /// @todo PGMFlushTLB(pVCpu, cr3, true /*fGlobal*/);
1379 HMFlushTLB(pVCpu);
1380
1381 /* Notify PGM about NXE changes. */
1382 if ( (uOldEFER & MSR_K6_EFER_NXE)
1383 != (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE))
1384 PGMNotifyNxeChanged(pVCpu, !(uOldEFER & MSR_K6_EFER_NXE));
1385 }
1386 break;
1387 }
1388
1389 case MSR_K8_SF_MASK:
1390 pVCpu->cpum.s.Guest.msrSFMASK = uValue;
1391 break;
1392
1393 case MSR_K6_STAR:
1394 pVCpu->cpum.s.Guest.msrSTAR = uValue;
1395 break;
1396
1397 case MSR_K8_LSTAR:
1398 pVCpu->cpum.s.Guest.msrLSTAR = uValue;
1399 break;
1400
1401 case MSR_K8_CSTAR:
1402 pVCpu->cpum.s.Guest.msrCSTAR = uValue;
1403 break;
1404
1405 case MSR_K8_FS_BASE:
1406 pVCpu->cpum.s.Guest.fs.u64Base = uValue;
1407 break;
1408
1409 case MSR_K8_GS_BASE:
1410 pVCpu->cpum.s.Guest.gs.u64Base = uValue;
1411 break;
1412
1413 case MSR_K8_KERNEL_GS_BASE:
1414 pVCpu->cpum.s.Guest.msrKERNELGSBASE = uValue;
1415 break;
1416
1417 case MSR_K8_TSC_AUX:
1418 pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
1419 break;
1420
1421 case MSR_IA32_DEBUGCTL:
1422 /** @todo virtualize DEBUGCTL and relatives */
1423 break;
1424
1425
1426 /*
1427 * Intel specifics MSRs:
1428 */
1429 /*case MSR_IA32_PLATFORM_ID: - read-only */
1430 case MSR_IA32_BIOS_SIGN_ID: /* fam/mod >= 6_01 */
1431 case MSR_IA32_BIOS_UPDT_TRIG: /* fam/mod >= 6_01 */
1432 /*case MSR_IA32_MCP_CAP: - read-only */
1433 /*case MSR_IA32_MCG_STATUS: - read-only */
1434 /*case MSR_IA32_MCG_CTRL: - indicated as not present in CAP */
1435 /*case MSR_IA32_MC0_CTL: - read-only? */
1436 /*case MSR_IA32_MC0_STATUS: - read-only? */
1437 if (CPUMGetGuestCpuVendor(pVCpu->CTX_SUFF(pVM)) != CPUMCPUVENDOR_INTEL)
1438 {
1439 Log(("MSR %#x is Intel, the virtual CPU isn't an Intel one -> #GP\n", idMsr));
1440 return VERR_CPUM_RAISE_GP_0;
1441 }
1442 /* ignored */
1443 break;
1444
1445 /*
1446 * AMD specific MSRs:
1447 */
1448 case MSR_K8_SYSCFG: /** @todo can be written, but we ignore that for now. */
1449 case MSR_K8_INT_PENDING: /** @todo can be written, but we ignore that for now. */
1450 case MSR_K8_NB_CFG: /** @todo can be written; the apicid swapping might be used and would need saving, but probably unnecessary. */
1451 if (CPUMGetGuestCpuVendor(pVCpu->CTX_SUFF(pVM)) != CPUMCPUVENDOR_AMD)
1452 {
1453 Log(("MSR %#x is AMD, the virtual CPU isn't an Intel one -> #GP\n", idMsr));
1454 return VERR_CPUM_RAISE_GP_0;
1455 }
1456 /* ignored */
1457 break;
1458
1459
1460 default:
1461 /*
1462 * Hand the X2APIC range to PDM and the APIC.
1463 */
1464 if ( idMsr >= MSR_IA32_X2APIC_START
1465 && idMsr <= MSR_IA32_X2APIC_END)
1466 {
1467 rc = PDMApicWriteMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, uValue);
1468 if (rc != VINF_SUCCESS)
1469 rc = VERR_CPUM_RAISE_GP_0;
1470 }
1471 else
1472 {
1473 /* We should actually trigger a #GP here, but don't as that might cause more trouble. */
1474 /** @todo rc = VERR_CPUM_RAISE_GP_0 */
1475 Log(("CPUMSetGuestMsr: Unknown MSR %#x attempted set to %#llx\n", idMsr, uValue));
1476 }
1477 break;
1478 }
1479 return rc;
1480}
1481
1482
1483VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
1484{
1485 if (pcbLimit)
1486 *pcbLimit = pVCpu->cpum.s.Guest.idtr.cbIdt;
1487 return pVCpu->cpum.s.Guest.idtr.pIdt;
1488}
1489
1490
1491VMMDECL(RTSEL) CPUMGetGuestTR(PVMCPU pVCpu, PCPUMSELREGHID pHidden)
1492{
1493 if (pHidden)
1494 *pHidden = pVCpu->cpum.s.Guest.tr;
1495 return pVCpu->cpum.s.Guest.tr.Sel;
1496}
1497
1498
1499VMMDECL(RTSEL) CPUMGetGuestCS(PVMCPU pVCpu)
1500{
1501 return pVCpu->cpum.s.Guest.cs.Sel;
1502}
1503
1504
1505VMMDECL(RTSEL) CPUMGetGuestDS(PVMCPU pVCpu)
1506{
1507 return pVCpu->cpum.s.Guest.ds.Sel;
1508}
1509
1510
1511VMMDECL(RTSEL) CPUMGetGuestES(PVMCPU pVCpu)
1512{
1513 return pVCpu->cpum.s.Guest.es.Sel;
1514}
1515
1516
1517VMMDECL(RTSEL) CPUMGetGuestFS(PVMCPU pVCpu)
1518{
1519 return pVCpu->cpum.s.Guest.fs.Sel;
1520}
1521
1522
1523VMMDECL(RTSEL) CPUMGetGuestGS(PVMCPU pVCpu)
1524{
1525 return pVCpu->cpum.s.Guest.gs.Sel;
1526}
1527
1528
1529VMMDECL(RTSEL) CPUMGetGuestSS(PVMCPU pVCpu)
1530{
1531 return pVCpu->cpum.s.Guest.ss.Sel;
1532}
1533
1534
1535VMMDECL(RTSEL) CPUMGetGuestLDTR(PVMCPU pVCpu)
1536{
1537 return pVCpu->cpum.s.Guest.ldtr.Sel;
1538}
1539
1540
1541VMMDECL(RTSEL) CPUMGetGuestLdtrEx(PVMCPU pVCpu, uint64_t *pGCPtrBase, uint32_t *pcbLimit)
1542{
1543 *pGCPtrBase = pVCpu->cpum.s.Guest.ldtr.u64Base;
1544 *pcbLimit = pVCpu->cpum.s.Guest.ldtr.u32Limit;
1545 return pVCpu->cpum.s.Guest.ldtr.Sel;
1546}
1547
1548
1549VMMDECL(uint64_t) CPUMGetGuestCR0(PVMCPU pVCpu)
1550{
1551 return pVCpu->cpum.s.Guest.cr0;
1552}
1553
1554
1555VMMDECL(uint64_t) CPUMGetGuestCR2(PVMCPU pVCpu)
1556{
1557 return pVCpu->cpum.s.Guest.cr2;
1558}
1559
1560
1561VMMDECL(uint64_t) CPUMGetGuestCR3(PVMCPU pVCpu)
1562{
1563 return pVCpu->cpum.s.Guest.cr3;
1564}
1565
1566
1567VMMDECL(uint64_t) CPUMGetGuestCR4(PVMCPU pVCpu)
1568{
1569 return pVCpu->cpum.s.Guest.cr4;
1570}
1571
1572
1573VMMDECL(uint64_t) CPUMGetGuestCR8(PVMCPU pVCpu)
1574{
1575 uint64_t u64;
1576 int rc = CPUMGetGuestCRx(pVCpu, DISCREG_CR8, &u64);
1577 if (RT_FAILURE(rc))
1578 u64 = 0;
1579 return u64;
1580}
1581
1582
1583VMMDECL(void) CPUMGetGuestGDTR(PVMCPU pVCpu, PVBOXGDTR pGDTR)
1584{
1585 *pGDTR = pVCpu->cpum.s.Guest.gdtr;
1586}
1587
1588
1589VMMDECL(uint32_t) CPUMGetGuestEIP(PVMCPU pVCpu)
1590{
1591 return pVCpu->cpum.s.Guest.eip;
1592}
1593
1594
1595VMMDECL(uint64_t) CPUMGetGuestRIP(PVMCPU pVCpu)
1596{
1597 return pVCpu->cpum.s.Guest.rip;
1598}
1599
1600
1601VMMDECL(uint32_t) CPUMGetGuestEAX(PVMCPU pVCpu)
1602{
1603 return pVCpu->cpum.s.Guest.eax;
1604}
1605
1606
1607VMMDECL(uint32_t) CPUMGetGuestEBX(PVMCPU pVCpu)
1608{
1609 return pVCpu->cpum.s.Guest.ebx;
1610}
1611
1612
1613VMMDECL(uint32_t) CPUMGetGuestECX(PVMCPU pVCpu)
1614{
1615 return pVCpu->cpum.s.Guest.ecx;
1616}
1617
1618
1619VMMDECL(uint32_t) CPUMGetGuestEDX(PVMCPU pVCpu)
1620{
1621 return pVCpu->cpum.s.Guest.edx;
1622}
1623
1624
1625VMMDECL(uint32_t) CPUMGetGuestESI(PVMCPU pVCpu)
1626{
1627 return pVCpu->cpum.s.Guest.esi;
1628}
1629
1630
1631VMMDECL(uint32_t) CPUMGetGuestEDI(PVMCPU pVCpu)
1632{
1633 return pVCpu->cpum.s.Guest.edi;
1634}
1635
1636
1637VMMDECL(uint32_t) CPUMGetGuestESP(PVMCPU pVCpu)
1638{
1639 return pVCpu->cpum.s.Guest.esp;
1640}
1641
1642
1643VMMDECL(uint32_t) CPUMGetGuestEBP(PVMCPU pVCpu)
1644{
1645 return pVCpu->cpum.s.Guest.ebp;
1646}
1647
1648
1649VMMDECL(uint32_t) CPUMGetGuestEFlags(PVMCPU pVCpu)
1650{
1651 return pVCpu->cpum.s.Guest.eflags.u32;
1652}
1653
1654
1655VMMDECL(int) CPUMGetGuestCRx(PVMCPU pVCpu, unsigned iReg, uint64_t *pValue)
1656{
1657 switch (iReg)
1658 {
1659 case DISCREG_CR0:
1660 *pValue = pVCpu->cpum.s.Guest.cr0;
1661 break;
1662
1663 case DISCREG_CR2:
1664 *pValue = pVCpu->cpum.s.Guest.cr2;
1665 break;
1666
1667 case DISCREG_CR3:
1668 *pValue = pVCpu->cpum.s.Guest.cr3;
1669 break;
1670
1671 case DISCREG_CR4:
1672 *pValue = pVCpu->cpum.s.Guest.cr4;
1673 break;
1674
1675 case DISCREG_CR8:
1676 {
1677 uint8_t u8Tpr;
1678 int rc = PDMApicGetTPR(pVCpu, &u8Tpr, NULL /* pfPending */, NULL /* pu8PendingIrq */);
1679 if (RT_FAILURE(rc))
1680 {
1681 AssertMsg(rc == VERR_PDM_NO_APIC_INSTANCE, ("%Rrc\n", rc));
1682 *pValue = 0;
1683 return rc;
1684 }
1685 *pValue = u8Tpr >> 4; /* bits 7-4 contain the task priority that go in cr8, bits 3-0*/
1686 break;
1687 }
1688
1689 default:
1690 return VERR_INVALID_PARAMETER;
1691 }
1692 return VINF_SUCCESS;
1693}
1694
1695
1696VMMDECL(uint64_t) CPUMGetGuestDR0(PVMCPU pVCpu)
1697{
1698 return pVCpu->cpum.s.Guest.dr[0];
1699}
1700
1701
1702VMMDECL(uint64_t) CPUMGetGuestDR1(PVMCPU pVCpu)
1703{
1704 return pVCpu->cpum.s.Guest.dr[1];
1705}
1706
1707
1708VMMDECL(uint64_t) CPUMGetGuestDR2(PVMCPU pVCpu)
1709{
1710 return pVCpu->cpum.s.Guest.dr[2];
1711}
1712
1713
1714VMMDECL(uint64_t) CPUMGetGuestDR3(PVMCPU pVCpu)
1715{
1716 return pVCpu->cpum.s.Guest.dr[3];
1717}
1718
1719
1720VMMDECL(uint64_t) CPUMGetGuestDR6(PVMCPU pVCpu)
1721{
1722 return pVCpu->cpum.s.Guest.dr[6];
1723}
1724
1725
1726VMMDECL(uint64_t) CPUMGetGuestDR7(PVMCPU pVCpu)
1727{
1728 return pVCpu->cpum.s.Guest.dr[7];
1729}
1730
1731
1732VMMDECL(int) CPUMGetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t *pValue)
1733{
1734 AssertReturn(iReg <= DISDREG_DR7, VERR_INVALID_PARAMETER);
1735 /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
1736 if (iReg == 4 || iReg == 5)
1737 iReg += 2;
1738 *pValue = pVCpu->cpum.s.Guest.dr[iReg];
1739 return VINF_SUCCESS;
1740}
1741
1742
1743VMMDECL(uint64_t) CPUMGetGuestEFER(PVMCPU pVCpu)
1744{
1745 return pVCpu->cpum.s.Guest.msrEFER;
1746}
1747
1748
1749/**
1750 * Gets a CPUID leaf.
1751 *
1752 * @param pVCpu Pointer to the VMCPU.
1753 * @param iLeaf The CPUID leaf to get.
1754 * @param pEax Where to store the EAX value.
1755 * @param pEbx Where to store the EBX value.
1756 * @param pEcx Where to store the ECX value.
1757 * @param pEdx Where to store the EDX value.
1758 */
1759VMMDECL(void) CPUMGetGuestCpuId(PVMCPU pVCpu, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx)
1760{
1761 PVM pVM = pVCpu->CTX_SUFF(pVM);
1762
1763 PCCPUMCPUID pCpuId;
1764 if (iLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
1765 pCpuId = &pVM->cpum.s.aGuestCpuIdStd[iLeaf];
1766 else if (iLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
1767 pCpuId = &pVM->cpum.s.aGuestCpuIdExt[iLeaf - UINT32_C(0x80000000)];
1768 else if ( iLeaf - UINT32_C(0x40000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdHyper)
1769 && (pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_HVP))
1770 pCpuId = &pVM->cpum.s.aGuestCpuIdHyper[iLeaf - UINT32_C(0x40000000)]; /* Only report if HVP bit set. */
1771 else if (iLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
1772 pCpuId = &pVM->cpum.s.aGuestCpuIdCentaur[iLeaf - UINT32_C(0xc0000000)];
1773 else
1774 pCpuId = &pVM->cpum.s.GuestCpuIdDef;
1775
1776 uint32_t cCurrentCacheIndex = *pEcx;
1777
1778 *pEax = pCpuId->eax;
1779 *pEbx = pCpuId->ebx;
1780 *pEcx = pCpuId->ecx;
1781 *pEdx = pCpuId->edx;
1782
1783 if ( iLeaf == 1)
1784 {
1785 /* Bits 31-24: Initial APIC ID */
1786 Assert(pVCpu->idCpu <= 255);
1787 *pEbx |= (pVCpu->idCpu << 24);
1788 }
1789
1790 if ( iLeaf == 4
1791 && cCurrentCacheIndex < 3
1792 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
1793 {
1794 uint32_t type, level, sharing, linesize,
1795 partitions, associativity, sets, cores;
1796
1797 /* For type: 1 - data cache, 2 - i-cache, 3 - unified */
1798 partitions = 1;
1799 /* Those are only to shut up compiler, as they will always
1800 get overwritten, and compiler should be able to figure that out */
1801 sets = associativity = sharing = level = 1;
1802 cores = pVM->cCpus > 32 ? 32 : pVM->cCpus;
1803 switch (cCurrentCacheIndex)
1804 {
1805 case 0:
1806 type = 1;
1807 level = 1;
1808 sharing = 1;
1809 linesize = 64;
1810 associativity = 8;
1811 sets = 64;
1812 break;
1813 case 1:
1814 level = 1;
1815 type = 2;
1816 sharing = 1;
1817 linesize = 64;
1818 associativity = 8;
1819 sets = 64;
1820 break;
1821 default: /* shut up gcc.*/
1822 AssertFailed();
1823 case 2:
1824 level = 2;
1825 type = 3;
1826 sharing = cores; /* our L2 cache is modelled as shared between all cores */
1827 linesize = 64;
1828 associativity = 24;
1829 sets = 4096;
1830 break;
1831 }
1832
1833 *pEax |= ((cores - 1) << 26) |
1834 ((sharing - 1) << 14) |
1835 (level << 5) |
1836 1;
1837 *pEbx = (linesize - 1) |
1838 ((partitions - 1) << 12) |
1839 ((associativity - 1) << 22); /* -1 encoding */
1840 *pEcx = sets - 1;
1841 }
1842
1843 Log2(("CPUMGetGuestCpuId: iLeaf=%#010x %RX32 %RX32 %RX32 %RX32\n", iLeaf, *pEax, *pEbx, *pEcx, *pEdx));
1844}
1845
1846/**
1847 * Gets a number of standard CPUID leafs.
1848 *
1849 * @returns Number of leafs.
1850 * @param pVM Pointer to the VM.
1851 * @remark Intended for PATM.
1852 */
1853VMMDECL(uint32_t) CPUMGetGuestCpuIdStdMax(PVM pVM)
1854{
1855 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd);
1856}
1857
1858
1859/**
1860 * Gets a number of extended CPUID leafs.
1861 *
1862 * @returns Number of leafs.
1863 * @param pVM Pointer to the VM.
1864 * @remark Intended for PATM.
1865 */
1866VMMDECL(uint32_t) CPUMGetGuestCpuIdExtMax(PVM pVM)
1867{
1868 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt);
1869}
1870
1871
1872/**
1873 * Gets a number of centaur CPUID leafs.
1874 *
1875 * @returns Number of leafs.
1876 * @param pVM Pointer to the VM.
1877 * @remark Intended for PATM.
1878 */
1879VMMDECL(uint32_t) CPUMGetGuestCpuIdCentaurMax(PVM pVM)
1880{
1881 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur);
1882}
1883
1884
1885/**
1886 * Sets a CPUID feature bit.
1887 *
1888 * @param pVM Pointer to the VM.
1889 * @param enmFeature The feature to set.
1890 */
1891VMMDECL(void) CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
1892{
1893 switch (enmFeature)
1894 {
1895 /*
1896 * Set the APIC bit in both feature masks.
1897 */
1898 case CPUMCPUIDFEATURE_APIC:
1899 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1900 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_APIC;
1901 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1902 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1903 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_APIC;
1904 LogRel(("CPUMSetGuestCpuIdFeature: Enabled APIC\n"));
1905 break;
1906
1907 /*
1908 * Set the x2APIC bit in the standard feature mask.
1909 */
1910 case CPUMCPUIDFEATURE_X2APIC:
1911 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1912 pVM->cpum.s.aGuestCpuIdStd[1].ecx |= X86_CPUID_FEATURE_ECX_X2APIC;
1913 LogRel(("CPUMSetGuestCpuIdFeature: Enabled x2APIC\n"));
1914 break;
1915
1916 /*
1917 * Set the sysenter/sysexit bit in the standard feature mask.
1918 * Assumes the caller knows what it's doing! (host must support these)
1919 */
1920 case CPUMCPUIDFEATURE_SEP:
1921 {
1922 if (!(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_SEP))
1923 {
1924 AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
1925 return;
1926 }
1927
1928 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1929 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_SEP;
1930 LogRel(("CPUMSetGuestCpuIdFeature: Enabled sysenter/exit\n"));
1931 break;
1932 }
1933
1934 /*
1935 * Set the syscall/sysret bit in the extended feature mask.
1936 * Assumes the caller knows what it's doing! (host must support these)
1937 */
1938 case CPUMCPUIDFEATURE_SYSCALL:
1939 {
1940 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1941 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_SYSCALL))
1942 {
1943#if HC_ARCH_BITS == 32
1944 /* X86_CPUID_EXT_FEATURE_EDX_SYSCALL not set it seems in 32 bits mode.
1945 * Even when the cpu is capable of doing so in 64 bits mode.
1946 */
1947 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1948 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
1949 || !(ASMCpuId_EDX(1) & X86_CPUID_EXT_FEATURE_EDX_SYSCALL))
1950#endif
1951 {
1952 LogRel(("WARNING: Can't turn on SYSCALL/SYSRET when the host doesn't support it!!\n"));
1953 return;
1954 }
1955 }
1956 /* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
1957 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
1958 LogRel(("CPUMSetGuestCpuIdFeature: Enabled syscall/ret\n"));
1959 break;
1960 }
1961
1962 /*
1963 * Set the PAE bit in both feature masks.
1964 * Assumes the caller knows what it's doing! (host must support these)
1965 */
1966 case CPUMCPUIDFEATURE_PAE:
1967 {
1968 if (!(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_PAE))
1969 {
1970 LogRel(("WARNING: Can't turn on PAE when the host doesn't support it!!\n"));
1971 return;
1972 }
1973
1974 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1975 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_PAE;
1976 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1977 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1978 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_PAE;
1979 LogRel(("CPUMSetGuestCpuIdFeature: Enabled PAE\n"));
1980 break;
1981 }
1982
1983 /*
1984 * Set the LONG MODE bit in the extended feature mask.
1985 * Assumes the caller knows what it's doing! (host must support these)
1986 */
1987 case CPUMCPUIDFEATURE_LONG_MODE:
1988 {
1989 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1990 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE))
1991 {
1992 LogRel(("WARNING: Can't turn on LONG MODE when the host doesn't support it!!\n"));
1993 return;
1994 }
1995
1996 /* Valid for both Intel and AMD. */
1997 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
1998 LogRel(("CPUMSetGuestCpuIdFeature: Enabled LONG MODE\n"));
1999 break;
2000 }
2001
2002 /*
2003 * Set the NX/XD bit in the extended feature mask.
2004 * Assumes the caller knows what it's doing! (host must support these)
2005 */
2006 case CPUMCPUIDFEATURE_NX:
2007 {
2008 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
2009 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_NX))
2010 {
2011 LogRel(("WARNING: Can't turn on NX/XD when the host doesn't support it!!\n"));
2012 return;
2013 }
2014
2015 /* Valid for both Intel and AMD. */
2016 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_NX;
2017 LogRel(("CPUMSetGuestCpuIdFeature: Enabled NX\n"));
2018 break;
2019 }
2020
2021 /*
2022 * Set the LAHF/SAHF support in 64-bit mode.
2023 * Assumes the caller knows what it's doing! (host must support this)
2024 */
2025 case CPUMCPUIDFEATURE_LAHF:
2026 {
2027 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
2028 || !(ASMCpuId_ECX(0x80000001) & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF))
2029 {
2030 LogRel(("WARNING: Can't turn on LAHF/SAHF when the host doesn't support it!!\n"));
2031 return;
2032 }
2033
2034 /* Valid for both Intel and AMD. */
2035 pVM->cpum.s.aGuestCpuIdExt[1].ecx |= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
2036 LogRel(("CPUMSetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
2037 break;
2038 }
2039
2040 case CPUMCPUIDFEATURE_PAT:
2041 {
2042 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2043 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_PAT;
2044 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
2045 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
2046 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_PAT;
2047 LogRel(("CPUMSetGuestCpuIdFeature: Enabled PAT\n"));
2048 break;
2049 }
2050
2051 /*
2052 * Set the RDTSCP support bit.
2053 * Assumes the caller knows what it's doing! (host must support this)
2054 */
2055 case CPUMCPUIDFEATURE_RDTSCP:
2056 {
2057 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
2058 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
2059 || pVM->cpum.s.u8PortableCpuIdLevel > 0)
2060 {
2061 if (!pVM->cpum.s.u8PortableCpuIdLevel)
2062 LogRel(("WARNING: Can't turn on RDTSCP when the host doesn't support it!!\n"));
2063 return;
2064 }
2065
2066 /* Valid for both Intel and AMD. */
2067 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
2068 LogRel(("CPUMSetGuestCpuIdFeature: Enabled RDTSCP.\n"));
2069 break;
2070 }
2071
2072 /*
2073 * Set the Hypervisor Present bit in the standard feature mask.
2074 */
2075 case CPUMCPUIDFEATURE_HVP:
2076 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2077 pVM->cpum.s.aGuestCpuIdStd[1].ecx |= X86_CPUID_FEATURE_ECX_HVP;
2078 LogRel(("CPUMSetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
2079 break;
2080
2081 default:
2082 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
2083 break;
2084 }
2085 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2086 {
2087 PVMCPU pVCpu = &pVM->aCpus[i];
2088 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CPUID;
2089 }
2090}
2091
2092
2093/**
2094 * Queries a CPUID feature bit.
2095 *
2096 * @returns boolean for feature presence
2097 * @param pVM Pointer to the VM.
2098 * @param enmFeature The feature to query.
2099 */
2100VMMDECL(bool) CPUMGetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
2101{
2102 switch (enmFeature)
2103 {
2104 case CPUMCPUIDFEATURE_PAE:
2105 {
2106 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2107 return !!(pVM->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PAE);
2108 break;
2109 }
2110
2111 case CPUMCPUIDFEATURE_NX:
2112 {
2113 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
2114 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_EXT_FEATURE_EDX_NX);
2115 }
2116
2117 case CPUMCPUIDFEATURE_SYSCALL:
2118 {
2119 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
2120 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
2121 }
2122
2123 case CPUMCPUIDFEATURE_RDTSCP:
2124 {
2125 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
2126 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2127 break;
2128 }
2129
2130 case CPUMCPUIDFEATURE_LONG_MODE:
2131 {
2132 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
2133 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
2134 break;
2135 }
2136
2137 default:
2138 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
2139 break;
2140 }
2141 return false;
2142}
2143
2144
2145/**
2146 * Clears a CPUID feature bit.
2147 *
2148 * @param pVM Pointer to the VM.
2149 * @param enmFeature The feature to clear.
2150 */
2151VMMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
2152{
2153 switch (enmFeature)
2154 {
2155 /*
2156 * Set the APIC bit in both feature masks.
2157 */
2158 case CPUMCPUIDFEATURE_APIC:
2159 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2160 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_APIC;
2161 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
2162 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
2163 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
2164 Log(("CPUMClearGuestCpuIdFeature: Disabled APIC\n"));
2165 break;
2166
2167 /*
2168 * Clear the x2APIC bit in the standard feature mask.
2169 */
2170 case CPUMCPUIDFEATURE_X2APIC:
2171 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2172 pVM->cpum.s.aGuestCpuIdStd[1].ecx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
2173 Log(("CPUMClearGuestCpuIdFeature: Disabled x2APIC\n"));
2174 break;
2175
2176 case CPUMCPUIDFEATURE_PAE:
2177 {
2178 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2179 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_PAE;
2180 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
2181 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
2182 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
2183 Log(("CPUMClearGuestCpuIdFeature: Disabled PAE!\n"));
2184 break;
2185 }
2186
2187 case CPUMCPUIDFEATURE_PAT:
2188 {
2189 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2190 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_PAT;
2191 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
2192 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
2193 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_PAT;
2194 Log(("CPUMClearGuestCpuIdFeature: Disabled PAT!\n"));
2195 break;
2196 }
2197
2198 case CPUMCPUIDFEATURE_LONG_MODE:
2199 {
2200 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
2201 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
2202 break;
2203 }
2204
2205 case CPUMCPUIDFEATURE_LAHF:
2206 {
2207 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
2208 pVM->cpum.s.aGuestCpuIdExt[1].ecx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
2209 break;
2210 }
2211
2212 case CPUMCPUIDFEATURE_RDTSCP:
2213 {
2214 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
2215 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
2216 Log(("CPUMClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
2217 break;
2218 }
2219
2220 case CPUMCPUIDFEATURE_HVP:
2221 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2222 pVM->cpum.s.aGuestCpuIdStd[1].ecx &= ~X86_CPUID_FEATURE_ECX_HVP;
2223 break;
2224
2225 default:
2226 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
2227 break;
2228 }
2229 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2230 {
2231 PVMCPU pVCpu = &pVM->aCpus[i];
2232 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CPUID;
2233 }
2234}
2235
2236
2237/**
2238 * Gets the host CPU vendor.
2239 *
2240 * @returns CPU vendor.
2241 * @param pVM Pointer to the VM.
2242 */
2243VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM)
2244{
2245 return pVM->cpum.s.enmHostCpuVendor;
2246}
2247
2248
2249/**
2250 * Gets the CPU vendor.
2251 *
2252 * @returns CPU vendor.
2253 * @param pVM Pointer to the VM.
2254 */
2255VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM)
2256{
2257 return pVM->cpum.s.enmGuestCpuVendor;
2258}
2259
2260
2261VMMDECL(int) CPUMSetGuestDR0(PVMCPU pVCpu, uint64_t uDr0)
2262{
2263 pVCpu->cpum.s.Guest.dr[0] = uDr0;
2264 return CPUMRecalcHyperDRx(pVCpu, 0, false);
2265}
2266
2267
2268VMMDECL(int) CPUMSetGuestDR1(PVMCPU pVCpu, uint64_t uDr1)
2269{
2270 pVCpu->cpum.s.Guest.dr[1] = uDr1;
2271 return CPUMRecalcHyperDRx(pVCpu, 1, false);
2272}
2273
2274
2275VMMDECL(int) CPUMSetGuestDR2(PVMCPU pVCpu, uint64_t uDr2)
2276{
2277 pVCpu->cpum.s.Guest.dr[2] = uDr2;
2278 return CPUMRecalcHyperDRx(pVCpu, 2, false);
2279}
2280
2281
2282VMMDECL(int) CPUMSetGuestDR3(PVMCPU pVCpu, uint64_t uDr3)
2283{
2284 pVCpu->cpum.s.Guest.dr[3] = uDr3;
2285 return CPUMRecalcHyperDRx(pVCpu, 3, false);
2286}
2287
2288
2289VMMDECL(int) CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6)
2290{
2291 pVCpu->cpum.s.Guest.dr[6] = uDr6;
2292 return VINF_SUCCESS; /* No need to recalc. */
2293}
2294
2295
2296VMMDECL(int) CPUMSetGuestDR7(PVMCPU pVCpu, uint64_t uDr7)
2297{
2298 pVCpu->cpum.s.Guest.dr[7] = uDr7;
2299 return CPUMRecalcHyperDRx(pVCpu, 7, false);
2300}
2301
2302
2303VMMDECL(int) CPUMSetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t Value)
2304{
2305 AssertReturn(iReg <= DISDREG_DR7, VERR_INVALID_PARAMETER);
2306 /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
2307 if (iReg == 4 || iReg == 5)
2308 iReg += 2;
2309 pVCpu->cpum.s.Guest.dr[iReg] = Value;
2310 return CPUMRecalcHyperDRx(pVCpu, iReg, false);
2311}
2312
2313
2314/**
2315 * Recalculates the hypervisor DRx register values based on current guest
2316 * registers and DBGF breakpoints, updating changed registers depending on the
2317 * context.
2318 *
2319 * This is called whenever a guest DRx register is modified (any context) and
2320 * when DBGF sets a hardware breakpoint (ring-3 only, rendezvous).
2321 *
2322 * In raw-mode context this function will reload any (hyper) DRx registers which
2323 * comes out with a different value. It may also have to save the host debug
2324 * registers if that haven't been done already. In this context though, we'll
2325 * be intercepting and emulating all DRx accesses, so the hypervisor DRx values
2326 * are only important when breakpoints are actually enabled.
2327 *
2328 * In ring-0 (HM) context DR0-3 will be relocated by us, while DR7 will be
2329 * reloaded by the HM code if it changes. Further more, we will only use the
2330 * combined register set when the VBox debugger is actually using hardware BPs,
2331 * when it isn't we'll keep the guest DR0-3 + (maybe) DR6 loaded (DR6 doesn't
2332 * concern us here).
2333 *
2334 * In ring-3 we won't be loading anything, so well calculate hypervisor values
2335 * all the time.
2336 *
2337 * @returns VINF_SUCCESS.
2338 * @param pVCpu Pointer to the VMCPU.
2339 * @param iGstReg The guest debug register number that was modified.
2340 * UINT8_MAX if not guest register.
2341 * @param fForceHyper Used in HM to force hyper registers because of single
2342 * stepping.
2343 */
2344VMMDECL(int) CPUMRecalcHyperDRx(PVMCPU pVCpu, uint8_t iGstReg, bool fForceHyper)
2345{
2346 PVM pVM = pVCpu->CTX_SUFF(pVM);
2347
2348 /*
2349 * Compare the DR7s first.
2350 *
2351 * We only care about the enabled flags. GD is virtualized when we
2352 * dispatch the #DB, we never enable it. The DBGF DR7 value is will
2353 * always have the LE and GE bits set, so no need to check and disable
2354 * stuff if they're cleared like we have to for the guest DR7.
2355 */
2356 RTGCUINTREG uGstDr7 = CPUMGetGuestDR7(pVCpu);
2357 if (!(uGstDr7 & (X86_DR7_LE | X86_DR7_GE)))
2358 uGstDr7 = 0;
2359 else if (!(uGstDr7 & X86_DR7_LE))
2360 uGstDr7 &= ~X86_DR7_LE_ALL;
2361 else if (!(uGstDr7 & X86_DR7_GE))
2362 uGstDr7 &= ~X86_DR7_GE_ALL;
2363
2364 const RTGCUINTREG uDbgfDr7 = DBGFBpGetDR7(pVM);
2365
2366#ifdef IN_RING0
2367 if (!fForceHyper && (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HYPER))
2368 fForceHyper = true;
2369#endif
2370 if (( HMIsEnabled(pVCpu->CTX_SUFF(pVM)) && !fForceHyper ? uDbgfDr7 : (uGstDr7 | uDbgfDr7)) & X86_DR7_ENABLED_MASK)
2371 {
2372 Assert(!CPUMIsGuestDebugStateActive(pVCpu));
2373#ifdef IN_RC
2374 bool const fHmEnabled = false;
2375#elif defined(IN_RING3)
2376 bool const fHmEnabled = HMIsEnabled(pVM);
2377#endif
2378
2379 /*
2380 * Ok, something is enabled. Recalc each of the breakpoints, taking
2381 * the VM debugger ones of the guest ones. In raw-mode context we will
2382 * not allow breakpoints with values inside the hypervisor area.
2383 */
2384 RTGCUINTREG uNewDr7 = X86_DR7_GE | X86_DR7_LE | X86_DR7_RA1_MASK;
2385
2386 /* bp 0 */
2387 RTGCUINTREG uNewDr0;
2388 if (uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0))
2389 {
2390 uNewDr7 |= uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
2391 uNewDr0 = DBGFBpGetDR0(pVM);
2392 }
2393 else if (uGstDr7 & (X86_DR7_L0 | X86_DR7_G0))
2394 {
2395 uNewDr0 = CPUMGetGuestDR0(pVCpu);
2396#ifndef IN_RING0
2397 if (fHmEnabled && MMHyperIsInsideArea(pVM, uNewDr0))
2398 uNewDr0 = 0;
2399 else
2400#endif
2401 uNewDr7 |= uGstDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
2402 }
2403 else
2404 uNewDr0 = 0;
2405
2406 /* bp 1 */
2407 RTGCUINTREG uNewDr1;
2408 if (uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1))
2409 {
2410 uNewDr7 |= uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
2411 uNewDr1 = DBGFBpGetDR1(pVM);
2412 }
2413 else if (uGstDr7 & (X86_DR7_L1 | X86_DR7_G1))
2414 {
2415 uNewDr1 = CPUMGetGuestDR1(pVCpu);
2416#ifndef IN_RING0
2417 if (fHmEnabled && MMHyperIsInsideArea(pVM, uNewDr1))
2418 uNewDr1 = 0;
2419 else
2420#endif
2421 uNewDr7 |= uGstDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
2422 }
2423 else
2424 uNewDr1 = 0;
2425
2426 /* bp 2 */
2427 RTGCUINTREG uNewDr2;
2428 if (uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2))
2429 {
2430 uNewDr7 |= uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
2431 uNewDr2 = DBGFBpGetDR2(pVM);
2432 }
2433 else if (uGstDr7 & (X86_DR7_L2 | X86_DR7_G2))
2434 {
2435 uNewDr2 = CPUMGetGuestDR2(pVCpu);
2436#ifndef IN_RING0
2437 if (fHmEnabled && MMHyperIsInsideArea(pVM, uNewDr2))
2438 uNewDr2 = 0;
2439 else
2440#endif
2441 uNewDr7 |= uGstDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
2442 }
2443 else
2444 uNewDr2 = 0;
2445
2446 /* bp 3 */
2447 RTGCUINTREG uNewDr3;
2448 if (uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3))
2449 {
2450 uNewDr7 |= uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
2451 uNewDr3 = DBGFBpGetDR3(pVM);
2452 }
2453 else if (uGstDr7 & (X86_DR7_L3 | X86_DR7_G3))
2454 {
2455 uNewDr3 = CPUMGetGuestDR3(pVCpu);
2456#ifndef IN_RING0
2457 if (fHmEnabled && MMHyperIsInsideArea(pVM, uNewDr3))
2458 uNewDr3 = 0;
2459 else
2460#endif
2461 uNewDr7 |= uGstDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
2462 }
2463 else
2464 uNewDr3 = 0;
2465
2466 /*
2467 * Apply the updates.
2468 */
2469#ifdef IN_RC
2470 /* Make sure to save host registers first. */
2471 if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HOST))
2472 {
2473 if (!(pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS_HOST))
2474 {
2475 pVCpu->cpum.s.Host.dr6 = ASMGetDR6();
2476 pVCpu->cpum.s.Host.dr7 = ASMGetDR7();
2477 }
2478 pVCpu->cpum.s.Host.dr0 = ASMGetDR0();
2479 pVCpu->cpum.s.Host.dr1 = ASMGetDR1();
2480 pVCpu->cpum.s.Host.dr2 = ASMGetDR2();
2481 pVCpu->cpum.s.Host.dr3 = ASMGetDR3();
2482 pVCpu->cpum.s.fUseFlags |= CPUM_USED_DEBUG_REGS_HOST | CPUM_USE_DEBUG_REGS_HYPER | CPUM_USED_DEBUG_REGS_HYPER;
2483
2484 /* We haven't loaded any hyper DRxes yet, so we'll have to load them all now. */
2485 pVCpu->cpum.s.Hyper.dr[0] = uNewDr0;
2486 ASMSetDR0(uNewDr0);
2487 pVCpu->cpum.s.Hyper.dr[1] = uNewDr1;
2488 ASMSetDR1(uNewDr1);
2489 pVCpu->cpum.s.Hyper.dr[2] = uNewDr2;
2490 ASMSetDR2(uNewDr2);
2491 pVCpu->cpum.s.Hyper.dr[3] = uNewDr3;
2492 ASMSetDR3(uNewDr3);
2493 ASMSetDR6(X86_DR6_INIT_VAL);
2494 pVCpu->cpum.s.Hyper.dr[7] = uNewDr7;
2495 ASMSetDR7(uNewDr7);
2496 }
2497 else
2498#endif
2499 {
2500 pVCpu->cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS_HYPER;
2501 if (uNewDr3 != pVCpu->cpum.s.Hyper.dr[3])
2502 CPUMSetHyperDR3(pVCpu, uNewDr3);
2503 if (uNewDr2 != pVCpu->cpum.s.Hyper.dr[2])
2504 CPUMSetHyperDR2(pVCpu, uNewDr2);
2505 if (uNewDr1 != pVCpu->cpum.s.Hyper.dr[1])
2506 CPUMSetHyperDR1(pVCpu, uNewDr1);
2507 if (uNewDr0 != pVCpu->cpum.s.Hyper.dr[0])
2508 CPUMSetHyperDR0(pVCpu, uNewDr0);
2509 if (uNewDr7 != pVCpu->cpum.s.Hyper.dr[7])
2510 CPUMSetHyperDR7(pVCpu, uNewDr7);
2511 }
2512 }
2513#ifdef IN_RING0
2514 else if (CPUMIsGuestDebugStateActive(pVCpu))
2515 {
2516 /*
2517 * Reload the register that was modified. Normally this won't happen
2518 * as we won't intercept DRx writes when not having the hyper debug
2519 * state loaded, but in case we do for some reason we'll simply deal
2520 * with it.
2521 */
2522 switch (iGstReg)
2523 {
2524 case 0: ASMSetDR0(CPUMGetGuestDR0(pVCpu)); break;
2525 case 1: ASMSetDR1(CPUMGetGuestDR1(pVCpu)); break;
2526 case 2: ASMSetDR2(CPUMGetGuestDR2(pVCpu)); break;
2527 case 3: ASMSetDR3(CPUMGetGuestDR3(pVCpu)); break;
2528 default:
2529 AssertReturn(iGstReg != UINT8_MAX, VERR_INTERNAL_ERROR_3);
2530 }
2531 }
2532#endif
2533 else
2534 {
2535 /*
2536 * No active debug state any more. In raw-mode this means we have to
2537 * make sure DR7 has everything disabled now, if we armed it already.
2538 * In ring-0 we might end up here when just single stepping.
2539 */
2540#if defined(IN_RC) || defined(IN_RING0)
2541 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HYPER)
2542 {
2543# ifdef IN_RC
2544 ASMSetDR7(X86_DR7_INIT_VAL);
2545# endif
2546 if (pVCpu->cpum.s.Hyper.dr[0])
2547 ASMSetDR0(0);
2548 if (pVCpu->cpum.s.Hyper.dr[1])
2549 ASMSetDR1(0);
2550 if (pVCpu->cpum.s.Hyper.dr[2])
2551 ASMSetDR2(0);
2552 if (pVCpu->cpum.s.Hyper.dr[3])
2553 ASMSetDR3(0);
2554 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_DEBUG_REGS_HYPER;
2555 }
2556#endif
2557 pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS_HYPER;
2558
2559 /* Clear all the registers. */
2560 pVCpu->cpum.s.Hyper.dr[7] = X86_DR7_RA1_MASK;
2561 pVCpu->cpum.s.Hyper.dr[3] = 0;
2562 pVCpu->cpum.s.Hyper.dr[2] = 0;
2563 pVCpu->cpum.s.Hyper.dr[1] = 0;
2564 pVCpu->cpum.s.Hyper.dr[0] = 0;
2565
2566 }
2567 Log2(("CPUMRecalcHyperDRx: fUseFlags=%#x %RGr %RGr %RGr %RGr %RGr %RGr\n",
2568 pVCpu->cpum.s.fUseFlags, pVCpu->cpum.s.Hyper.dr[0], pVCpu->cpum.s.Hyper.dr[1],
2569 pVCpu->cpum.s.Hyper.dr[2], pVCpu->cpum.s.Hyper.dr[3], pVCpu->cpum.s.Hyper.dr[6],
2570 pVCpu->cpum.s.Hyper.dr[7]));
2571
2572 return VINF_SUCCESS;
2573}
2574
2575
2576/**
2577 * Tests if the guest has No-Execute Page Protection Enabled (NXE).
2578 *
2579 * @returns true if in real mode, otherwise false.
2580 * @param pVCpu Pointer to the VMCPU.
2581 */
2582VMMDECL(bool) CPUMIsGuestNXEnabled(PVMCPU pVCpu)
2583{
2584 return !!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE);
2585}
2586
2587
2588/**
2589 * Tests if the guest has the Page Size Extension enabled (PSE).
2590 *
2591 * @returns true if in real mode, otherwise false.
2592 * @param pVCpu Pointer to the VMCPU.
2593 */
2594VMMDECL(bool) CPUMIsGuestPageSizeExtEnabled(PVMCPU pVCpu)
2595{
2596 /* PAE or AMD64 implies support for big pages regardless of CR4.PSE */
2597 return !!(pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PSE | X86_CR4_PAE));
2598}
2599
2600
2601/**
2602 * Tests if the guest has the paging enabled (PG).
2603 *
2604 * @returns true if in real mode, otherwise false.
2605 * @param pVCpu Pointer to the VMCPU.
2606 */
2607VMMDECL(bool) CPUMIsGuestPagingEnabled(PVMCPU pVCpu)
2608{
2609 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG);
2610}
2611
2612
2613/**
2614 * Tests if the guest has the paging enabled (PG).
2615 *
2616 * @returns true if in real mode, otherwise false.
2617 * @param pVCpu Pointer to the VMCPU.
2618 */
2619VMMDECL(bool) CPUMIsGuestR0WriteProtEnabled(PVMCPU pVCpu)
2620{
2621 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_WP);
2622}
2623
2624
2625/**
2626 * Tests if the guest is running in real mode or not.
2627 *
2628 * @returns true if in real mode, otherwise false.
2629 * @param pVCpu Pointer to the VMCPU.
2630 */
2631VMMDECL(bool) CPUMIsGuestInRealMode(PVMCPU pVCpu)
2632{
2633 return !(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
2634}
2635
2636
2637/**
2638 * Tests if the guest is running in real or virtual 8086 mode.
2639 *
2640 * @returns @c true if it is, @c false if not.
2641 * @param pVCpu Pointer to the VMCPU.
2642 */
2643VMMDECL(bool) CPUMIsGuestInRealOrV86Mode(PVMCPU pVCpu)
2644{
2645 return !(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE)
2646 || pVCpu->cpum.s.Guest.eflags.Bits.u1VM; /** @todo verify that this cannot be set in long mode. */
2647}
2648
2649
2650/**
2651 * Tests if the guest is running in protected or not.
2652 *
2653 * @returns true if in protected mode, otherwise false.
2654 * @param pVCpu Pointer to the VMCPU.
2655 */
2656VMMDECL(bool) CPUMIsGuestInProtectedMode(PVMCPU pVCpu)
2657{
2658 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
2659}
2660
2661
2662/**
2663 * Tests if the guest is running in paged protected or not.
2664 *
2665 * @returns true if in paged protected mode, otherwise false.
2666 * @param pVCpu Pointer to the VMCPU.
2667 */
2668VMMDECL(bool) CPUMIsGuestInPagedProtectedMode(PVMCPU pVCpu)
2669{
2670 return (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
2671}
2672
2673
2674/**
2675 * Tests if the guest is running in long mode or not.
2676 *
2677 * @returns true if in long mode, otherwise false.
2678 * @param pVCpu Pointer to the VMCPU.
2679 */
2680VMMDECL(bool) CPUMIsGuestInLongMode(PVMCPU pVCpu)
2681{
2682 return (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
2683}
2684
2685
2686/**
2687 * Tests if the guest is running in PAE mode or not.
2688 *
2689 * @returns true if in PAE mode, otherwise false.
2690 * @param pVCpu Pointer to the VMCPU.
2691 */
2692VMMDECL(bool) CPUMIsGuestInPAEMode(PVMCPU pVCpu)
2693{
2694 return (pVCpu->cpum.s.Guest.cr4 & X86_CR4_PAE)
2695 && (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG)
2696 && !(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LME);
2697}
2698
2699
2700/**
2701 * Tests if the guest is running in 64 bits mode or not.
2702 *
2703 * @returns true if in 64 bits protected mode, otherwise false.
2704 * @param pVCpu The current virtual CPU.
2705 */
2706VMMDECL(bool) CPUMIsGuestIn64BitCode(PVMCPU pVCpu)
2707{
2708 if (!CPUMIsGuestInLongMode(pVCpu))
2709 return false;
2710 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
2711 return pVCpu->cpum.s.Guest.cs.Attr.n.u1Long;
2712}
2713
2714
2715/**
2716 * Helper for CPUMIsGuestIn64BitCodeEx that handles lazy resolving of hidden CS
2717 * registers.
2718 *
2719 * @returns true if in 64 bits protected mode, otherwise false.
2720 * @param pCtx Pointer to the current guest CPU context.
2721 */
2722VMM_INT_DECL(bool) CPUMIsGuestIn64BitCodeSlow(PCPUMCTX pCtx)
2723{
2724 return CPUMIsGuestIn64BitCode(CPUM_GUEST_CTX_TO_VMCPU(pCtx));
2725}
2726
2727#ifdef VBOX_WITH_RAW_MODE_NOT_R0
2728
2729/**
2730 *
2731 * @returns @c true if we've entered raw-mode and selectors with RPL=1 are
2732 * really RPL=0, @c false if we've not (RPL=1 really is RPL=1).
2733 * @param pVCpu The current virtual CPU.
2734 */
2735VMM_INT_DECL(bool) CPUMIsGuestInRawMode(PVMCPU pVCpu)
2736{
2737 return pVCpu->cpum.s.fRawEntered;
2738}
2739
2740/**
2741 * Transforms the guest CPU state to raw-ring mode.
2742 *
2743 * This function will change the any of the cs and ss register with DPL=0 to DPL=1.
2744 *
2745 * @returns VBox status. (recompiler failure)
2746 * @param pVCpu Pointer to the VMCPU.
2747 * @param pCtxCore The context core (for trap usage).
2748 * @see @ref pg_raw
2749 */
2750VMM_INT_DECL(int) CPUMRawEnter(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
2751{
2752 PVM pVM = pVCpu->CTX_SUFF(pVM);
2753
2754 Assert(!pVCpu->cpum.s.fRawEntered);
2755 Assert(!pVCpu->cpum.s.fRemEntered);
2756 if (!pCtxCore)
2757 pCtxCore = CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
2758
2759 /*
2760 * Are we in Ring-0?
2761 */
2762 if ( pCtxCore->ss.Sel
2763 && (pCtxCore->ss.Sel & X86_SEL_RPL) == 0
2764 && !pCtxCore->eflags.Bits.u1VM)
2765 {
2766 /*
2767 * Enter execution mode.
2768 */
2769 PATMRawEnter(pVM, pCtxCore);
2770
2771 /*
2772 * Set CPL to Ring-1.
2773 */
2774 pCtxCore->ss.Sel |= 1;
2775 if ( pCtxCore->cs.Sel
2776 && (pCtxCore->cs.Sel & X86_SEL_RPL) == 0)
2777 pCtxCore->cs.Sel |= 1;
2778 }
2779 else
2780 {
2781# ifdef VBOX_WITH_RAW_RING1
2782 if ( EMIsRawRing1Enabled(pVM)
2783 && !pCtxCore->eflags.Bits.u1VM
2784 && (pCtxCore->ss.Sel & X86_SEL_RPL) == 1)
2785 {
2786 /* Set CPL to Ring-2. */
2787 pCtxCore->ss.Sel = (pCtxCore->ss.Sel & ~X86_SEL_RPL) | 2;
2788 if (pCtxCore->cs.Sel && (pCtxCore->cs.Sel & X86_SEL_RPL) == 1)
2789 pCtxCore->cs.Sel = (pCtxCore->cs.Sel & ~X86_SEL_RPL) | 2;
2790 }
2791# else
2792 AssertMsg((pCtxCore->ss.Sel & X86_SEL_RPL) >= 2 || pCtxCore->eflags.Bits.u1VM,
2793 ("ring-1 code not supported\n"));
2794# endif
2795 /*
2796 * PATM takes care of IOPL and IF flags for Ring-3 and Ring-2 code as well.
2797 */
2798 PATMRawEnter(pVM, pCtxCore);
2799 }
2800
2801 /*
2802 * Assert sanity.
2803 */
2804 AssertMsg((pCtxCore->eflags.u32 & X86_EFL_IF), ("X86_EFL_IF is clear\n"));
2805 AssertReleaseMsg(pCtxCore->eflags.Bits.u2IOPL == 0,
2806 ("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss.Sel & X86_SEL_RPL));
2807 Assert((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)) == (X86_CR0_PG | X86_CR0_PE | X86_CR0_WP));
2808
2809 pCtxCore->eflags.u32 |= X86_EFL_IF; /* paranoia */
2810
2811 pVCpu->cpum.s.fRawEntered = true;
2812 return VINF_SUCCESS;
2813}
2814
2815
2816/**
2817 * Transforms the guest CPU state from raw-ring mode to correct values.
2818 *
2819 * This function will change any selector registers with DPL=1 to DPL=0.
2820 *
2821 * @returns Adjusted rc.
2822 * @param pVCpu Pointer to the VMCPU.
2823 * @param rc Raw mode return code
2824 * @param pCtxCore The context core (for trap usage).
2825 * @see @ref pg_raw
2826 */
2827VMM_INT_DECL(int) CPUMRawLeave(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, int rc)
2828{
2829 PVM pVM = pVCpu->CTX_SUFF(pVM);
2830
2831 /*
2832 * Don't leave if we've already left (in RC).
2833 */
2834 Assert(!pVCpu->cpum.s.fRemEntered);
2835 if (!pVCpu->cpum.s.fRawEntered)
2836 return rc;
2837 pVCpu->cpum.s.fRawEntered = false;
2838
2839 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2840 if (!pCtxCore)
2841 pCtxCore = CPUMCTX2CORE(pCtx);
2842 Assert(pCtxCore->eflags.Bits.u1VM || (pCtxCore->ss.Sel & X86_SEL_RPL));
2843 AssertMsg(pCtxCore->eflags.Bits.u1VM || pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss.Sel & X86_SEL_RPL),
2844 ("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss.Sel & X86_SEL_RPL));
2845
2846 /*
2847 * Are we executing in raw ring-1?
2848 */
2849 if ( (pCtxCore->ss.Sel & X86_SEL_RPL) == 1
2850 && !pCtxCore->eflags.Bits.u1VM)
2851 {
2852 /*
2853 * Leave execution mode.
2854 */
2855 PATMRawLeave(pVM, pCtxCore, rc);
2856 /* Not quite sure if this is really required, but shouldn't harm (too much anyways). */
2857 /** @todo See what happens if we remove this. */
2858 if ((pCtxCore->ds.Sel & X86_SEL_RPL) == 1)
2859 pCtxCore->ds.Sel &= ~X86_SEL_RPL;
2860 if ((pCtxCore->es.Sel & X86_SEL_RPL) == 1)
2861 pCtxCore->es.Sel &= ~X86_SEL_RPL;
2862 if ((pCtxCore->fs.Sel & X86_SEL_RPL) == 1)
2863 pCtxCore->fs.Sel &= ~X86_SEL_RPL;
2864 if ((pCtxCore->gs.Sel & X86_SEL_RPL) == 1)
2865 pCtxCore->gs.Sel &= ~X86_SEL_RPL;
2866
2867 /*
2868 * Ring-1 selector => Ring-0.
2869 */
2870 pCtxCore->ss.Sel &= ~X86_SEL_RPL;
2871 if ((pCtxCore->cs.Sel & X86_SEL_RPL) == 1)
2872 pCtxCore->cs.Sel &= ~X86_SEL_RPL;
2873 }
2874 else
2875 {
2876 /*
2877 * PATM is taking care of the IOPL and IF flags for us.
2878 */
2879 PATMRawLeave(pVM, pCtxCore, rc);
2880 if (!pCtxCore->eflags.Bits.u1VM)
2881 {
2882# ifdef VBOX_WITH_RAW_RING1
2883 if ( EMIsRawRing1Enabled(pVM)
2884 && (pCtxCore->ss.Sel & X86_SEL_RPL) == 2)
2885 {
2886 /* Not quite sure if this is really required, but shouldn't harm (too much anyways). */
2887 /** @todo See what happens if we remove this. */
2888 if ((pCtxCore->ds.Sel & X86_SEL_RPL) == 2)
2889 pCtxCore->ds.Sel = (pCtxCore->ds.Sel & ~X86_SEL_RPL) | 1;
2890 if ((pCtxCore->es.Sel & X86_SEL_RPL) == 2)
2891 pCtxCore->es.Sel = (pCtxCore->es.Sel & ~X86_SEL_RPL) | 1;
2892 if ((pCtxCore->fs.Sel & X86_SEL_RPL) == 2)
2893 pCtxCore->fs.Sel = (pCtxCore->fs.Sel & ~X86_SEL_RPL) | 1;
2894 if ((pCtxCore->gs.Sel & X86_SEL_RPL) == 2)
2895 pCtxCore->gs.Sel = (pCtxCore->gs.Sel & ~X86_SEL_RPL) | 1;
2896
2897 /*
2898 * Ring-2 selector => Ring-1.
2899 */
2900 pCtxCore->ss.Sel = (pCtxCore->ss.Sel & ~X86_SEL_RPL) | 1;
2901 if ((pCtxCore->cs.Sel & X86_SEL_RPL) == 2)
2902 pCtxCore->cs.Sel = (pCtxCore->cs.Sel & ~X86_SEL_RPL) | 1;
2903 }
2904 else
2905 {
2906# endif
2907 /** @todo See what happens if we remove this. */
2908 if ((pCtxCore->ds.Sel & X86_SEL_RPL) == 1)
2909 pCtxCore->ds.Sel &= ~X86_SEL_RPL;
2910 if ((pCtxCore->es.Sel & X86_SEL_RPL) == 1)
2911 pCtxCore->es.Sel &= ~X86_SEL_RPL;
2912 if ((pCtxCore->fs.Sel & X86_SEL_RPL) == 1)
2913 pCtxCore->fs.Sel &= ~X86_SEL_RPL;
2914 if ((pCtxCore->gs.Sel & X86_SEL_RPL) == 1)
2915 pCtxCore->gs.Sel &= ~X86_SEL_RPL;
2916# ifdef VBOX_WITH_RAW_RING1
2917 }
2918# endif
2919 }
2920 }
2921
2922 return rc;
2923}
2924
2925#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
2926
2927/**
2928 * Updates the EFLAGS while we're in raw-mode.
2929 *
2930 * @param pVCpu Pointer to the VMCPU.
2931 * @param fEfl The new EFLAGS value.
2932 */
2933VMMDECL(void) CPUMRawSetEFlags(PVMCPU pVCpu, uint32_t fEfl)
2934{
2935#ifdef VBOX_WITH_RAW_MODE_NOT_R0
2936 if (pVCpu->cpum.s.fRawEntered)
2937 PATMRawSetEFlags(pVCpu->CTX_SUFF(pVM), CPUMCTX2CORE(&pVCpu->cpum.s.Guest), fEfl);
2938 else
2939#endif
2940 pVCpu->cpum.s.Guest.eflags.u32 = fEfl;
2941}
2942
2943
2944/**
2945 * Gets the EFLAGS while we're in raw-mode.
2946 *
2947 * @returns The eflags.
2948 * @param pVCpu Pointer to the current virtual CPU.
2949 */
2950VMMDECL(uint32_t) CPUMRawGetEFlags(PVMCPU pVCpu)
2951{
2952#ifdef VBOX_WITH_RAW_MODE_NOT_R0
2953 if (pVCpu->cpum.s.fRawEntered)
2954 return PATMRawGetEFlags(pVCpu->CTX_SUFF(pVM), CPUMCTX2CORE(&pVCpu->cpum.s.Guest));
2955#endif
2956 return pVCpu->cpum.s.Guest.eflags.u32;
2957}
2958
2959
2960/**
2961 * Sets the specified changed flags (CPUM_CHANGED_*).
2962 *
2963 * @param pVCpu Pointer to the current virtual CPU.
2964 */
2965VMMDECL(void) CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedFlags)
2966{
2967 pVCpu->cpum.s.fChanged |= fChangedFlags;
2968}
2969
2970
2971/**
2972 * Checks if the CPU supports the FXSAVE and FXRSTOR instruction.
2973 * @returns true if supported.
2974 * @returns false if not supported.
2975 * @param pVM Pointer to the VM.
2976 */
2977VMMDECL(bool) CPUMSupportsFXSR(PVM pVM)
2978{
2979 return pVM->cpum.s.CPUFeatures.edx.u1FXSR != 0;
2980}
2981
2982
2983/**
2984 * Checks if the host OS uses the SYSENTER / SYSEXIT instructions.
2985 * @returns true if used.
2986 * @returns false if not used.
2987 * @param pVM Pointer to the VM.
2988 */
2989VMMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM)
2990{
2991 return RT_BOOL(pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSENTER);
2992}
2993
2994
2995/**
2996 * Checks if the host OS uses the SYSCALL / SYSRET instructions.
2997 * @returns true if used.
2998 * @returns false if not used.
2999 * @param pVM Pointer to the VM.
3000 */
3001VMMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM)
3002{
3003 return RT_BOOL(pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSCALL);
3004}
3005
3006#ifndef IN_RING3
3007
3008/**
3009 * Lazily sync in the FPU/XMM state.
3010 *
3011 * @returns VBox status code.
3012 * @param pVCpu Pointer to the VMCPU.
3013 */
3014VMMDECL(int) CPUMHandleLazyFPU(PVMCPU pVCpu)
3015{
3016 return cpumHandleLazyFPUAsm(&pVCpu->cpum.s);
3017}
3018
3019#endif /* !IN_RING3 */
3020
3021/**
3022 * Checks if we activated the FPU/XMM state of the guest OS.
3023 * @returns true if we did.
3024 * @returns false if not.
3025 * @param pVCpu Pointer to the VMCPU.
3026 */
3027VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCpu)
3028{
3029 return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU);
3030}
3031
3032
3033/**
3034 * Deactivate the FPU/XMM state of the guest OS.
3035 * @param pVCpu Pointer to the VMCPU.
3036 *
3037 * @todo r=bird: Why is this needed? Looks like a workaround for mishandled
3038 * FPU state management.
3039 */
3040VMMDECL(void) CPUMDeactivateGuestFPUState(PVMCPU pVCpu)
3041{
3042 Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU));
3043 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU;
3044}
3045
3046
3047/**
3048 * Checks if the guest debug state is active.
3049 *
3050 * @returns boolean
3051 * @param pVM Pointer to the VM.
3052 */
3053VMMDECL(bool) CPUMIsGuestDebugStateActive(PVMCPU pVCpu)
3054{
3055 return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST);
3056}
3057
3058/**
3059 * Checks if the hyper debug state is active.
3060 *
3061 * @returns boolean
3062 * @param pVM Pointer to the VM.
3063 */
3064VMMDECL(bool) CPUMIsHyperDebugStateActive(PVMCPU pVCpu)
3065{
3066 return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HYPER);
3067}
3068
3069
3070/**
3071 * Mark the guest's debug state as inactive.
3072 *
3073 * @returns boolean
3074 * @param pVM Pointer to the VM.
3075 * @todo This API doesn't make sense any more.
3076 */
3077VMMDECL(void) CPUMDeactivateGuestDebugState(PVMCPU pVCpu)
3078{
3079 Assert(!(pVCpu->cpum.s.fUseFlags & (CPUM_USED_DEBUG_REGS_GUEST | CPUM_USED_DEBUG_REGS_HYPER | CPUM_USED_DEBUG_REGS_HOST)));
3080}
3081
3082
3083/**
3084 * Get the current privilege level of the guest.
3085 *
3086 * @returns CPL
3087 * @param pVCpu Pointer to the current virtual CPU.
3088 */
3089VMMDECL(uint32_t) CPUMGetGuestCPL(PVMCPU pVCpu)
3090{
3091 /*
3092 * CPL can reliably be found in SS.DPL (hidden regs valid) or SS if not.
3093 *
3094 * Note! We used to check CS.DPL here, assuming it was always equal to
3095 * CPL even if a conforming segment was loaded. But this truned out to
3096 * only apply to older AMD-V. With VT-x we had an ACP2 regression
3097 * during install after a far call to ring 2 with VT-x. Then on newer
3098 * AMD-V CPUs we have to move the VMCB.guest.u8CPL into cs.Attr.n.u2Dpl
3099 * as well as ss.Attr.n.u2Dpl to make this (and other) code work right.
3100 *
3101 * So, forget CS.DPL, always use SS.DPL.
3102 *
3103 * Note! The SS RPL is always equal to the CPL, while the CS RPL
3104 * isn't necessarily equal if the segment is conforming.
3105 * See section 4.11.1 in the AMD manual.
3106 *
3107 * Update: Where the heck does it say CS.RPL can differ from CPL other than
3108 * right after real->prot mode switch and when in V8086 mode? That
3109 * section says the RPL specified in a direct transfere (call, jmp,
3110 * ret) is not the one loaded into CS. Besides, if CS.RPL != CPL
3111 * it would be impossible for an exception handle or the iret
3112 * instruction to figure out whether SS:ESP are part of the frame
3113 * or not. VBox or qemu bug must've lead to this misconception.
3114 *
3115 * Update2: On an AMD bulldozer system here, I've no trouble loading a null
3116 * selector into SS with an RPL other than the CPL when CPL != 3 and
3117 * we're in 64-bit mode. The intel dev box doesn't allow this, on
3118 * RPL = CPL. Weird.
3119 */
3120 uint32_t uCpl;
3121 if (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE)
3122 {
3123 if (!pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
3124 {
3125 if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.s.Guest.ss))
3126 uCpl = pVCpu->cpum.s.Guest.ss.Attr.n.u2Dpl;
3127 else
3128 {
3129 uCpl = (pVCpu->cpum.s.Guest.ss.Sel & X86_SEL_RPL);
3130#ifdef VBOX_WITH_RAW_MODE_NOT_R0
3131# ifdef VBOX_WITH_RAW_RING1
3132 if (pVCpu->cpum.s.fRawEntered)
3133 {
3134 if ( uCpl == 2
3135 && EMIsRawRing1Enabled(pVCpu->CTX_SUFF(pVM)))
3136 uCpl = 1;
3137 else if (uCpl == 1)
3138 uCpl = 0;
3139 }
3140 Assert(uCpl != 2); /* ring 2 support not allowed anymore. */
3141# else
3142 if (uCpl == 1)
3143 uCpl = 0;
3144# endif
3145#endif
3146 }
3147 }
3148 else
3149 uCpl = 3; /* V86 has CPL=3; REM doesn't set DPL=3 in V8086 mode. See @bugref{5130}. */
3150 }
3151 else
3152 uCpl = 0; /* Real mode is zero; CPL set to 3 for VT-x real-mode emulation. */
3153 return uCpl;
3154}
3155
3156
3157/**
3158 * Gets the current guest CPU mode.
3159 *
3160 * If paging mode is what you need, check out PGMGetGuestMode().
3161 *
3162 * @returns The CPU mode.
3163 * @param pVCpu Pointer to the VMCPU.
3164 */
3165VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu)
3166{
3167 CPUMMODE enmMode;
3168 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
3169 enmMode = CPUMMODE_REAL;
3170 else if (!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
3171 enmMode = CPUMMODE_PROTECTED;
3172 else
3173 enmMode = CPUMMODE_LONG;
3174
3175 return enmMode;
3176}
3177
3178
3179/**
3180 * Figure whether the CPU is currently executing 16, 32 or 64 bit code.
3181 *
3182 * @returns 16, 32 or 64.
3183 * @param pVCpu The current virtual CPU.
3184 */
3185VMMDECL(uint32_t) CPUMGetGuestCodeBits(PVMCPU pVCpu)
3186{
3187 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
3188 return 16;
3189
3190 if (pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
3191 {
3192 Assert(!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA));
3193 return 16;
3194 }
3195
3196 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
3197 if ( pVCpu->cpum.s.Guest.cs.Attr.n.u1Long
3198 && (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
3199 return 64;
3200
3201 if (pVCpu->cpum.s.Guest.cs.Attr.n.u1DefBig)
3202 return 32;
3203
3204 return 16;
3205}
3206
3207
3208VMMDECL(DISCPUMODE) CPUMGetGuestDisMode(PVMCPU pVCpu)
3209{
3210 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
3211 return DISCPUMODE_16BIT;
3212
3213 if (pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
3214 {
3215 Assert(!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA));
3216 return DISCPUMODE_16BIT;
3217 }
3218
3219 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
3220 if ( pVCpu->cpum.s.Guest.cs.Attr.n.u1Long
3221 && (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
3222 return DISCPUMODE_64BIT;
3223
3224 if (pVCpu->cpum.s.Guest.cs.Attr.n.u1DefBig)
3225 return DISCPUMODE_32BIT;
3226
3227 return DISCPUMODE_16BIT;
3228}
3229
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