VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp@ 48203

Last change on this file since 48203 was 48203, checked in by vboxsync, 11 years ago

Ignore IA32_PMC0/1, too.
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1/* $Id: CPUMAllRegs.cpp 48203 2013-08-30 15:59:33Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor(/Manager) - Getters and Setters.
4 */
5
6/*
7 * Copyright (C) 2006-2012 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_CPUM
23#include <VBox/vmm/cpum.h>
24#include <VBox/vmm/patm.h>
25#include <VBox/vmm/dbgf.h>
26#include <VBox/vmm/pdm.h>
27#include <VBox/vmm/pgm.h>
28#include <VBox/vmm/mm.h>
29#include <VBox/vmm/em.h>
30#if defined(VBOX_WITH_RAW_MODE) && !defined(IN_RING0)
31# include <VBox/vmm/selm.h>
32#endif
33#include "CPUMInternal.h"
34#include <VBox/vmm/vm.h>
35#include <VBox/err.h>
36#include <VBox/dis.h>
37#include <VBox/log.h>
38#include <VBox/vmm/hm.h>
39#include <VBox/vmm/tm.h>
40#include <iprt/assert.h>
41#include <iprt/asm.h>
42#include <iprt/asm-amd64-x86.h>
43#ifdef IN_RING3
44#include <iprt/thread.h>
45#endif
46
47/** Disable stack frame pointer generation here. */
48#if defined(_MSC_VER) && !defined(DEBUG)
49# pragma optimize("y", off)
50#endif
51
52
53/*******************************************************************************
54* Defined Constants And Macros *
55*******************************************************************************/
56/**
57 * Converts a CPUMCPU::Guest pointer into a VMCPU pointer.
58 *
59 * @returns Pointer to the Virtual CPU.
60 * @param a_pGuestCtx Pointer to the guest context.
61 */
62#define CPUM_GUEST_CTX_TO_VMCPU(a_pGuestCtx) RT_FROM_MEMBER(a_pGuestCtx, VMCPU, cpum.s.Guest)
63
64/**
65 * Lazily loads the hidden parts of a selector register when using raw-mode.
66 */
67#if defined(VBOX_WITH_RAW_MODE) && !defined(IN_RING0)
68# define CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(a_pVCpu, a_pSReg) \
69 do \
70 { \
71 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(a_pVCpu, a_pSReg)) \
72 cpumGuestLazyLoadHiddenSelectorReg(a_pVCpu, a_pSReg); \
73 } while (0)
74#else
75# define CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(a_pVCpu, a_pSReg) \
76 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(a_pVCpu, a_pSReg));
77#endif
78
79
80
81#ifdef VBOX_WITH_RAW_MODE_NOT_R0
82
83/**
84 * Does the lazy hidden selector register loading.
85 *
86 * @param pVCpu The current Virtual CPU.
87 * @param pSReg The selector register to lazily load hidden parts of.
88 */
89static void cpumGuestLazyLoadHiddenSelectorReg(PVMCPU pVCpu, PCPUMSELREG pSReg)
90{
91 Assert(!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSReg));
92 Assert(!HMIsEnabled(pVCpu->CTX_SUFF(pVM)));
93 Assert((uintptr_t)(pSReg - &pVCpu->cpum.s.Guest.es) < X86_SREG_COUNT);
94
95 if (pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
96 {
97 /* V8086 mode - Tightly controlled environment, no question about the limit or flags. */
98 pSReg->Attr.u = 0;
99 pSReg->Attr.n.u4Type = pSReg == &pVCpu->cpum.s.Guest.cs ? X86_SEL_TYPE_ER_ACC : X86_SEL_TYPE_RW_ACC;
100 pSReg->Attr.n.u1DescType = 1; /* code/data segment */
101 pSReg->Attr.n.u2Dpl = 3;
102 pSReg->Attr.n.u1Present = 1;
103 pSReg->u32Limit = 0x0000ffff;
104 pSReg->u64Base = (uint32_t)pSReg->Sel << 4;
105 pSReg->ValidSel = pSReg->Sel;
106 pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
107 /** @todo Check what the accessed bit should be (VT-x and AMD-V). */
108 }
109 else if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
110 {
111 /* Real mode - leave the limit and flags alone here, at least for now. */
112 pSReg->u64Base = (uint32_t)pSReg->Sel << 4;
113 pSReg->ValidSel = pSReg->Sel;
114 pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
115 }
116 else
117 {
118 /* Protected mode - get it from the selector descriptor tables. */
119 if (!(pSReg->Sel & X86_SEL_MASK_OFF_RPL))
120 {
121 Assert(!CPUMIsGuestInLongMode(pVCpu));
122 pSReg->Sel = 0;
123 pSReg->u64Base = 0;
124 pSReg->u32Limit = 0;
125 pSReg->Attr.u = 0;
126 pSReg->ValidSel = 0;
127 pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
128 /** @todo see todo in iemHlpLoadNullDataSelectorProt. */
129 }
130 else
131 SELMLoadHiddenSelectorReg(pVCpu, &pVCpu->cpum.s.Guest, pSReg);
132 }
133}
134
135
136/**
137 * Makes sure the hidden CS and SS selector registers are valid, loading them if
138 * necessary.
139 *
140 * @param pVCpu The current virtual CPU.
141 */
142VMM_INT_DECL(void) CPUMGuestLazyLoadHiddenCsAndSs(PVMCPU pVCpu)
143{
144 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
145 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.ss);
146}
147
148
149/**
150 * Loads a the hidden parts of a selector register.
151 *
152 * @param pVCpu The current virtual CPU.
153 */
154VMM_INT_DECL(void) CPUMGuestLazyLoadHiddenSelectorReg(PVMCPU pVCpu, PCPUMSELREG pSReg)
155{
156 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, pSReg);
157}
158
159#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
160
161
162/**
163 * Obsolete.
164 *
165 * We don't support nested hypervisor context interrupts or traps. Life is much
166 * simpler when we don't. It's also slightly faster at times.
167 *
168 * @param pVM Handle to the virtual machine.
169 */
170VMMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVMCPU pVCpu)
171{
172 return CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
173}
174
175
176/**
177 * Gets the pointer to the hypervisor CPU context structure of a virtual CPU.
178 *
179 * @param pVCpu Pointer to the VMCPU.
180 */
181VMMDECL(PCPUMCTX) CPUMGetHyperCtxPtr(PVMCPU pVCpu)
182{
183 return &pVCpu->cpum.s.Hyper;
184}
185
186
187VMMDECL(void) CPUMSetHyperGDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
188{
189 pVCpu->cpum.s.Hyper.gdtr.cbGdt = limit;
190 pVCpu->cpum.s.Hyper.gdtr.pGdt = addr;
191}
192
193
194VMMDECL(void) CPUMSetHyperIDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
195{
196 pVCpu->cpum.s.Hyper.idtr.cbIdt = limit;
197 pVCpu->cpum.s.Hyper.idtr.pIdt = addr;
198}
199
200
201VMMDECL(void) CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3)
202{
203 pVCpu->cpum.s.Hyper.cr3 = cr3;
204
205#ifdef IN_RC
206 /* Update the current CR3. */
207 ASMSetCR3(cr3);
208#endif
209}
210
211VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu)
212{
213 return pVCpu->cpum.s.Hyper.cr3;
214}
215
216
217VMMDECL(void) CPUMSetHyperCS(PVMCPU pVCpu, RTSEL SelCS)
218{
219 pVCpu->cpum.s.Hyper.cs.Sel = SelCS;
220}
221
222
223VMMDECL(void) CPUMSetHyperDS(PVMCPU pVCpu, RTSEL SelDS)
224{
225 pVCpu->cpum.s.Hyper.ds.Sel = SelDS;
226}
227
228
229VMMDECL(void) CPUMSetHyperES(PVMCPU pVCpu, RTSEL SelES)
230{
231 pVCpu->cpum.s.Hyper.es.Sel = SelES;
232}
233
234
235VMMDECL(void) CPUMSetHyperFS(PVMCPU pVCpu, RTSEL SelFS)
236{
237 pVCpu->cpum.s.Hyper.fs.Sel = SelFS;
238}
239
240
241VMMDECL(void) CPUMSetHyperGS(PVMCPU pVCpu, RTSEL SelGS)
242{
243 pVCpu->cpum.s.Hyper.gs.Sel = SelGS;
244}
245
246
247VMMDECL(void) CPUMSetHyperSS(PVMCPU pVCpu, RTSEL SelSS)
248{
249 pVCpu->cpum.s.Hyper.ss.Sel = SelSS;
250}
251
252
253VMMDECL(void) CPUMSetHyperESP(PVMCPU pVCpu, uint32_t u32ESP)
254{
255 pVCpu->cpum.s.Hyper.esp = u32ESP;
256}
257
258
259VMMDECL(void) CPUMSetHyperEDX(PVMCPU pVCpu, uint32_t u32ESP)
260{
261 pVCpu->cpum.s.Hyper.esp = u32ESP;
262}
263
264
265VMMDECL(int) CPUMSetHyperEFlags(PVMCPU pVCpu, uint32_t Efl)
266{
267 pVCpu->cpum.s.Hyper.eflags.u32 = Efl;
268 return VINF_SUCCESS;
269}
270
271
272VMMDECL(void) CPUMSetHyperEIP(PVMCPU pVCpu, uint32_t u32EIP)
273{
274 pVCpu->cpum.s.Hyper.eip = u32EIP;
275}
276
277
278/**
279 * Used by VMMR3RawRunGC to reinitialize the general raw-mode context registers,
280 * EFLAGS and EIP prior to resuming guest execution.
281 *
282 * All general register not given as a parameter will be set to 0. The EFLAGS
283 * register will be set to sane values for C/C++ code execution with interrupts
284 * disabled and IOPL 0.
285 *
286 * @param pVCpu The current virtual CPU.
287 * @param u32EIP The EIP value.
288 * @param u32ESP The ESP value.
289 * @param u32EAX The EAX value.
290 * @param u32EDX The EDX value.
291 */
292VMM_INT_DECL(void) CPUMSetHyperState(PVMCPU pVCpu, uint32_t u32EIP, uint32_t u32ESP, uint32_t u32EAX, uint32_t u32EDX)
293{
294 pVCpu->cpum.s.Hyper.eip = u32EIP;
295 pVCpu->cpum.s.Hyper.esp = u32ESP;
296 pVCpu->cpum.s.Hyper.eax = u32EAX;
297 pVCpu->cpum.s.Hyper.edx = u32EDX;
298 pVCpu->cpum.s.Hyper.ecx = 0;
299 pVCpu->cpum.s.Hyper.ebx = 0;
300 pVCpu->cpum.s.Hyper.ebp = 0;
301 pVCpu->cpum.s.Hyper.esi = 0;
302 pVCpu->cpum.s.Hyper.edi = 0;
303 pVCpu->cpum.s.Hyper.eflags.u = X86_EFL_1;
304}
305
306
307VMMDECL(void) CPUMSetHyperTR(PVMCPU pVCpu, RTSEL SelTR)
308{
309 pVCpu->cpum.s.Hyper.tr.Sel = SelTR;
310}
311
312
313VMMDECL(void) CPUMSetHyperLDTR(PVMCPU pVCpu, RTSEL SelLDTR)
314{
315 pVCpu->cpum.s.Hyper.ldtr.Sel = SelLDTR;
316}
317
318
319/** @MAYBE_LOAD_DRx
320 * Macro for updating DRx values in raw-mode and ring-0 contexts.
321 */
322#ifdef IN_RING0
323# if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
324# ifndef VBOX_WITH_HYBRID_32BIT_KERNEL
325# define MAYBE_LOAD_DRx(a_pVCpu, a_fnLoad, a_uValue) \
326 do { \
327 if (!CPUMIsGuestInLongModeEx(&(a_pVCpu)->cpum.s.Guest)) \
328 a_fnLoad(a_uValue); \
329 else \
330 (a_pVCpu)->cpum.s.fUseFlags |= CPUM_SYNC_DEBUG_REGS_HYPER; \
331 } while (0)
332# else
333# define MAYBE_LOAD_DRx(a_pVCpu, a_fnLoad, a_uValue) \
334 do { \
335 /** @todo we're not loading the correct guest value here! */ \
336 a_fnLoad(a_uValue); \
337 } while (0)
338# endif
339# else
340# define MAYBE_LOAD_DRx(a_pVCpu, a_fnLoad, a_uValue) \
341 do { \
342 a_fnLoad(a_uValue); \
343 } while (0)
344# endif
345
346#elif defined(IN_RC)
347# define MAYBE_LOAD_DRx(a_pVCpu, a_fnLoad, a_uValue) \
348 do { \
349 if ((a_pVCpu)->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HYPER) \
350 { a_fnLoad(a_uValue); } \
351 } while (0)
352
353#else
354# define MAYBE_LOAD_DRx(a_pVCpu, a_fnLoad, a_uValue) do { } while (0)
355#endif
356
357VMMDECL(void) CPUMSetHyperDR0(PVMCPU pVCpu, RTGCUINTREG uDr0)
358{
359 pVCpu->cpum.s.Hyper.dr[0] = uDr0;
360 MAYBE_LOAD_DRx(pVCpu, ASMSetDR0, uDr0);
361}
362
363
364VMMDECL(void) CPUMSetHyperDR1(PVMCPU pVCpu, RTGCUINTREG uDr1)
365{
366 pVCpu->cpum.s.Hyper.dr[1] = uDr1;
367 MAYBE_LOAD_DRx(pVCpu, ASMSetDR1, uDr1);
368}
369
370
371VMMDECL(void) CPUMSetHyperDR2(PVMCPU pVCpu, RTGCUINTREG uDr2)
372{
373 pVCpu->cpum.s.Hyper.dr[2] = uDr2;
374 MAYBE_LOAD_DRx(pVCpu, ASMSetDR2, uDr2);
375}
376
377
378VMMDECL(void) CPUMSetHyperDR3(PVMCPU pVCpu, RTGCUINTREG uDr3)
379{
380 pVCpu->cpum.s.Hyper.dr[3] = uDr3;
381 MAYBE_LOAD_DRx(pVCpu, ASMSetDR3, uDr3);
382}
383
384
385VMMDECL(void) CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6)
386{
387 pVCpu->cpum.s.Hyper.dr[6] = uDr6;
388}
389
390
391VMMDECL(void) CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7)
392{
393 pVCpu->cpum.s.Hyper.dr[7] = uDr7;
394#ifdef IN_RC
395 MAYBE_LOAD_DRx(pVCpu, ASMSetDR7, uDr7);
396#endif
397}
398
399
400VMMDECL(RTSEL) CPUMGetHyperCS(PVMCPU pVCpu)
401{
402 return pVCpu->cpum.s.Hyper.cs.Sel;
403}
404
405
406VMMDECL(RTSEL) CPUMGetHyperDS(PVMCPU pVCpu)
407{
408 return pVCpu->cpum.s.Hyper.ds.Sel;
409}
410
411
412VMMDECL(RTSEL) CPUMGetHyperES(PVMCPU pVCpu)
413{
414 return pVCpu->cpum.s.Hyper.es.Sel;
415}
416
417
418VMMDECL(RTSEL) CPUMGetHyperFS(PVMCPU pVCpu)
419{
420 return pVCpu->cpum.s.Hyper.fs.Sel;
421}
422
423
424VMMDECL(RTSEL) CPUMGetHyperGS(PVMCPU pVCpu)
425{
426 return pVCpu->cpum.s.Hyper.gs.Sel;
427}
428
429
430VMMDECL(RTSEL) CPUMGetHyperSS(PVMCPU pVCpu)
431{
432 return pVCpu->cpum.s.Hyper.ss.Sel;
433}
434
435
436VMMDECL(uint32_t) CPUMGetHyperEAX(PVMCPU pVCpu)
437{
438 return pVCpu->cpum.s.Hyper.eax;
439}
440
441
442VMMDECL(uint32_t) CPUMGetHyperEBX(PVMCPU pVCpu)
443{
444 return pVCpu->cpum.s.Hyper.ebx;
445}
446
447
448VMMDECL(uint32_t) CPUMGetHyperECX(PVMCPU pVCpu)
449{
450 return pVCpu->cpum.s.Hyper.ecx;
451}
452
453
454VMMDECL(uint32_t) CPUMGetHyperEDX(PVMCPU pVCpu)
455{
456 return pVCpu->cpum.s.Hyper.edx;
457}
458
459
460VMMDECL(uint32_t) CPUMGetHyperESI(PVMCPU pVCpu)
461{
462 return pVCpu->cpum.s.Hyper.esi;
463}
464
465
466VMMDECL(uint32_t) CPUMGetHyperEDI(PVMCPU pVCpu)
467{
468 return pVCpu->cpum.s.Hyper.edi;
469}
470
471
472VMMDECL(uint32_t) CPUMGetHyperEBP(PVMCPU pVCpu)
473{
474 return pVCpu->cpum.s.Hyper.ebp;
475}
476
477
478VMMDECL(uint32_t) CPUMGetHyperESP(PVMCPU pVCpu)
479{
480 return pVCpu->cpum.s.Hyper.esp;
481}
482
483
484VMMDECL(uint32_t) CPUMGetHyperEFlags(PVMCPU pVCpu)
485{
486 return pVCpu->cpum.s.Hyper.eflags.u32;
487}
488
489
490VMMDECL(uint32_t) CPUMGetHyperEIP(PVMCPU pVCpu)
491{
492 return pVCpu->cpum.s.Hyper.eip;
493}
494
495
496VMMDECL(uint64_t) CPUMGetHyperRIP(PVMCPU pVCpu)
497{
498 return pVCpu->cpum.s.Hyper.rip;
499}
500
501
502VMMDECL(uint32_t) CPUMGetHyperIDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
503{
504 if (pcbLimit)
505 *pcbLimit = pVCpu->cpum.s.Hyper.idtr.cbIdt;
506 return pVCpu->cpum.s.Hyper.idtr.pIdt;
507}
508
509
510VMMDECL(uint32_t) CPUMGetHyperGDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
511{
512 if (pcbLimit)
513 *pcbLimit = pVCpu->cpum.s.Hyper.gdtr.cbGdt;
514 return pVCpu->cpum.s.Hyper.gdtr.pGdt;
515}
516
517
518VMMDECL(RTSEL) CPUMGetHyperLDTR(PVMCPU pVCpu)
519{
520 return pVCpu->cpum.s.Hyper.ldtr.Sel;
521}
522
523
524VMMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVMCPU pVCpu)
525{
526 return pVCpu->cpum.s.Hyper.dr[0];
527}
528
529
530VMMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVMCPU pVCpu)
531{
532 return pVCpu->cpum.s.Hyper.dr[1];
533}
534
535
536VMMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVMCPU pVCpu)
537{
538 return pVCpu->cpum.s.Hyper.dr[2];
539}
540
541
542VMMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVMCPU pVCpu)
543{
544 return pVCpu->cpum.s.Hyper.dr[3];
545}
546
547
548VMMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVMCPU pVCpu)
549{
550 return pVCpu->cpum.s.Hyper.dr[6];
551}
552
553
554VMMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVMCPU pVCpu)
555{
556 return pVCpu->cpum.s.Hyper.dr[7];
557}
558
559
560/**
561 * Gets the pointer to the internal CPUMCTXCORE structure.
562 * This is only for reading in order to save a few calls.
563 *
564 * @param pVCpu Handle to the virtual cpu.
565 */
566VMMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVMCPU pVCpu)
567{
568 return CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
569}
570
571
572/**
573 * Queries the pointer to the internal CPUMCTX structure.
574 *
575 * @returns The CPUMCTX pointer.
576 * @param pVCpu Handle to the virtual cpu.
577 */
578VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu)
579{
580 return &pVCpu->cpum.s.Guest;
581}
582
583VMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit)
584{
585#ifdef VBOX_WITH_IEM
586# ifdef VBOX_WITH_RAW_MODE_NOT_R0
587 if (!HMIsEnabled(pVCpu->CTX_SUFF(pVM)))
588 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
589# endif
590#endif
591 pVCpu->cpum.s.Guest.gdtr.cbGdt = cbLimit;
592 pVCpu->cpum.s.Guest.gdtr.pGdt = GCPtrBase;
593 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GDTR;
594 return VINF_SUCCESS; /* formality, consider it void. */
595}
596
597VMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit)
598{
599#ifdef VBOX_WITH_IEM
600# ifdef VBOX_WITH_RAW_MODE_NOT_R0
601 if (!HMIsEnabled(pVCpu->CTX_SUFF(pVM)))
602 VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
603# endif
604#endif
605 pVCpu->cpum.s.Guest.idtr.cbIdt = cbLimit;
606 pVCpu->cpum.s.Guest.idtr.pIdt = GCPtrBase;
607 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_IDTR;
608 return VINF_SUCCESS; /* formality, consider it void. */
609}
610
611VMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr)
612{
613#ifdef VBOX_WITH_IEM
614# ifdef VBOX_WITH_RAW_MODE_NOT_R0
615 if (!HMIsEnabled(pVCpu->CTX_SUFF(pVM)))
616 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
617# endif
618#endif
619 pVCpu->cpum.s.Guest.tr.Sel = tr;
620 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_TR;
621 return VINF_SUCCESS; /* formality, consider it void. */
622}
623
624VMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr)
625{
626#ifdef VBOX_WITH_IEM
627# ifdef VBOX_WITH_RAW_MODE_NOT_R0
628 if ( ( ldtr != 0
629 || pVCpu->cpum.s.Guest.ldtr.Sel != 0)
630 && !HMIsEnabled(pVCpu->CTX_SUFF(pVM)))
631 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
632# endif
633#endif
634 pVCpu->cpum.s.Guest.ldtr.Sel = ldtr;
635 /* The caller will set more hidden bits if it has them. */
636 pVCpu->cpum.s.Guest.ldtr.ValidSel = 0;
637 pVCpu->cpum.s.Guest.ldtr.fFlags = 0;
638 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_LDTR;
639 return VINF_SUCCESS; /* formality, consider it void. */
640}
641
642
643/**
644 * Set the guest CR0.
645 *
646 * When called in GC, the hyper CR0 may be updated if that is
647 * required. The caller only has to take special action if AM,
648 * WP, PG or PE changes.
649 *
650 * @returns VINF_SUCCESS (consider it void).
651 * @param pVCpu Handle to the virtual cpu.
652 * @param cr0 The new CR0 value.
653 */
654VMMDECL(int) CPUMSetGuestCR0(PVMCPU pVCpu, uint64_t cr0)
655{
656#ifdef IN_RC
657 /*
658 * Check if we need to change hypervisor CR0 because
659 * of math stuff.
660 */
661 if ( (cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP))
662 != (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP)))
663 {
664 if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU))
665 {
666 /*
667 * We haven't saved the host FPU state yet, so TS and MT are both set
668 * and EM should be reflecting the guest EM (it always does this).
669 */
670 if ((cr0 & X86_CR0_EM) != (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM))
671 {
672 uint32_t HyperCR0 = ASMGetCR0();
673 AssertMsg((HyperCR0 & (X86_CR0_TS | X86_CR0_MP)) == (X86_CR0_TS | X86_CR0_MP), ("%#x\n", HyperCR0));
674 AssertMsg((HyperCR0 & X86_CR0_EM) == (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM), ("%#x\n", HyperCR0));
675 HyperCR0 &= ~X86_CR0_EM;
676 HyperCR0 |= cr0 & X86_CR0_EM;
677 Log(("CPUM New HyperCR0=%#x\n", HyperCR0));
678 ASMSetCR0(HyperCR0);
679 }
680# ifdef VBOX_STRICT
681 else
682 {
683 uint32_t HyperCR0 = ASMGetCR0();
684 AssertMsg((HyperCR0 & (X86_CR0_TS | X86_CR0_MP)) == (X86_CR0_TS | X86_CR0_MP), ("%#x\n", HyperCR0));
685 AssertMsg((HyperCR0 & X86_CR0_EM) == (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM), ("%#x\n", HyperCR0));
686 }
687# endif
688 }
689 else
690 {
691 /*
692 * Already saved the state, so we're just mirroring
693 * the guest flags.
694 */
695 uint32_t HyperCR0 = ASMGetCR0();
696 AssertMsg( (HyperCR0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP))
697 == (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP)),
698 ("%#x %#x\n", HyperCR0, pVCpu->cpum.s.Guest.cr0));
699 HyperCR0 &= ~(X86_CR0_TS | X86_CR0_EM | X86_CR0_MP);
700 HyperCR0 |= cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP);
701 Log(("CPUM New HyperCR0=%#x\n", HyperCR0));
702 ASMSetCR0(HyperCR0);
703 }
704 }
705#endif /* IN_RC */
706
707 /*
708 * Check for changes causing TLB flushes (for REM).
709 * The caller is responsible for calling PGM when appropriate.
710 */
711 if ( (cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE))
712 != (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)))
713 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
714 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR0;
715
716 /*
717 * Let PGM know if the WP goes from 0 to 1 (netware WP0+RO+US hack)
718 */
719 if (((cr0 ^ pVCpu->cpum.s.Guest.cr0) & X86_CR0_WP) && (cr0 & X86_CR0_WP))
720 PGMCr0WpEnabled(pVCpu);
721
722 pVCpu->cpum.s.Guest.cr0 = cr0 | X86_CR0_ET;
723 return VINF_SUCCESS;
724}
725
726
727VMMDECL(int) CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2)
728{
729 pVCpu->cpum.s.Guest.cr2 = cr2;
730 return VINF_SUCCESS;
731}
732
733
734VMMDECL(int) CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3)
735{
736 pVCpu->cpum.s.Guest.cr3 = cr3;
737 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR3;
738 return VINF_SUCCESS;
739}
740
741
742VMMDECL(int) CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4)
743{
744 if ( (cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE))
745 != (pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE)))
746 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
747 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR4;
748 if (!CPUMSupportsFXSR(pVCpu->CTX_SUFF(pVM)))
749 cr4 &= ~X86_CR4_OSFSXR;
750 pVCpu->cpum.s.Guest.cr4 = cr4;
751 return VINF_SUCCESS;
752}
753
754
755VMMDECL(int) CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags)
756{
757 pVCpu->cpum.s.Guest.eflags.u32 = eflags;
758 return VINF_SUCCESS;
759}
760
761
762VMMDECL(int) CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip)
763{
764 pVCpu->cpum.s.Guest.eip = eip;
765 return VINF_SUCCESS;
766}
767
768
769VMMDECL(int) CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax)
770{
771 pVCpu->cpum.s.Guest.eax = eax;
772 return VINF_SUCCESS;
773}
774
775
776VMMDECL(int) CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx)
777{
778 pVCpu->cpum.s.Guest.ebx = ebx;
779 return VINF_SUCCESS;
780}
781
782
783VMMDECL(int) CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx)
784{
785 pVCpu->cpum.s.Guest.ecx = ecx;
786 return VINF_SUCCESS;
787}
788
789
790VMMDECL(int) CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx)
791{
792 pVCpu->cpum.s.Guest.edx = edx;
793 return VINF_SUCCESS;
794}
795
796
797VMMDECL(int) CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp)
798{
799 pVCpu->cpum.s.Guest.esp = esp;
800 return VINF_SUCCESS;
801}
802
803
804VMMDECL(int) CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp)
805{
806 pVCpu->cpum.s.Guest.ebp = ebp;
807 return VINF_SUCCESS;
808}
809
810
811VMMDECL(int) CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi)
812{
813 pVCpu->cpum.s.Guest.esi = esi;
814 return VINF_SUCCESS;
815}
816
817
818VMMDECL(int) CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi)
819{
820 pVCpu->cpum.s.Guest.edi = edi;
821 return VINF_SUCCESS;
822}
823
824
825VMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss)
826{
827 pVCpu->cpum.s.Guest.ss.Sel = ss;
828 return VINF_SUCCESS;
829}
830
831
832VMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs)
833{
834 pVCpu->cpum.s.Guest.cs.Sel = cs;
835 return VINF_SUCCESS;
836}
837
838
839VMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds)
840{
841 pVCpu->cpum.s.Guest.ds.Sel = ds;
842 return VINF_SUCCESS;
843}
844
845
846VMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es)
847{
848 pVCpu->cpum.s.Guest.es.Sel = es;
849 return VINF_SUCCESS;
850}
851
852
853VMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs)
854{
855 pVCpu->cpum.s.Guest.fs.Sel = fs;
856 return VINF_SUCCESS;
857}
858
859
860VMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs)
861{
862 pVCpu->cpum.s.Guest.gs.Sel = gs;
863 return VINF_SUCCESS;
864}
865
866
867VMMDECL(void) CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val)
868{
869 pVCpu->cpum.s.Guest.msrEFER = val;
870}
871
872
873/**
874 * Query an MSR.
875 *
876 * The caller is responsible for checking privilege if the call is the result
877 * of a RDMSR instruction. We'll do the rest.
878 *
879 * @retval VINF_SUCCESS on success.
880 * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR), the caller is
881 * expected to take the appropriate actions. @a *puValue is set to 0.
882 * @param pVCpu Pointer to the VMCPU.
883 * @param idMsr The MSR.
884 * @param puValue Where to return the value.
885 *
886 * @remarks This will always return the right values, even when we're in the
887 * recompiler.
888 */
889VMMDECL(int) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue)
890{
891 /*
892 * If we don't indicate MSR support in the CPUID feature bits, indicate
893 * that a #GP(0) should be raised.
894 */
895 if (!(pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_MSR))
896 {
897 *puValue = 0;
898 return VERR_CPUM_RAISE_GP_0; /** @todo isn't \#UD more correct if not supported? */
899 }
900
901 int rc = VINF_SUCCESS;
902 uint8_t const u8Multiplier = 4;
903 switch (idMsr)
904 {
905 case MSR_IA32_TSC:
906 *puValue = TMCpuTickGet(pVCpu);
907 break;
908
909 case MSR_IA32_APICBASE:
910 {
911 PVM pVM = pVCpu->CTX_SUFF(pVM);
912 if ( ( pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1 /* APIC Std feature */
913 && (pVM->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_APIC))
914 || ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001 /* APIC Ext feature (AMD) */
915 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD
916 && (pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_AMD_FEATURE_EDX_APIC))
917 || ( pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1 /* x2APIC */
918 && (pVM->cpum.s.aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_X2APIC)))
919 {
920 *puValue = pVCpu->cpum.s.Guest.msrApicBase;
921 }
922 else
923 {
924 *puValue = 0;
925 rc = VERR_CPUM_RAISE_GP_0;
926 }
927 break;
928 }
929
930 case MSR_IA32_CR_PAT:
931 *puValue = pVCpu->cpum.s.Guest.msrPAT;
932 break;
933
934 case MSR_IA32_SYSENTER_CS:
935 *puValue = pVCpu->cpum.s.Guest.SysEnter.cs;
936 break;
937
938 case MSR_IA32_SYSENTER_EIP:
939 *puValue = pVCpu->cpum.s.Guest.SysEnter.eip;
940 break;
941
942 case MSR_IA32_SYSENTER_ESP:
943 *puValue = pVCpu->cpum.s.Guest.SysEnter.esp;
944 break;
945
946 case MSR_IA32_MTRR_CAP:
947 {
948 /* This is currently a bit weird. :-) */
949 uint8_t const cVariableRangeRegs = 0;
950 bool const fSystemManagementRangeRegisters = false;
951 bool const fFixedRangeRegisters = false;
952 bool const fWriteCombiningType = false;
953 *puValue = cVariableRangeRegs
954 | (fFixedRangeRegisters ? RT_BIT_64(8) : 0)
955 | (fWriteCombiningType ? RT_BIT_64(10) : 0)
956 | (fSystemManagementRangeRegisters ? RT_BIT_64(11) : 0);
957 break;
958 }
959
960 case IA32_MTRR_PHYSBASE0: case IA32_MTRR_PHYSMASK0:
961 case IA32_MTRR_PHYSBASE1: case IA32_MTRR_PHYSMASK1:
962 case IA32_MTRR_PHYSBASE2: case IA32_MTRR_PHYSMASK2:
963 case IA32_MTRR_PHYSBASE3: case IA32_MTRR_PHYSMASK3:
964 case IA32_MTRR_PHYSBASE4: case IA32_MTRR_PHYSMASK4:
965 case IA32_MTRR_PHYSBASE5: case IA32_MTRR_PHYSMASK5:
966 case IA32_MTRR_PHYSBASE6: case IA32_MTRR_PHYSMASK6:
967 case IA32_MTRR_PHYSBASE7: case IA32_MTRR_PHYSMASK7:
968 /** @todo implement variable MTRRs. */
969 *puValue = 0;
970 break;
971#if 0 /** @todo newer CPUs have more, figure since when and do selective GP(). */
972 case IA32_MTRR_PHYSBASE8: case IA32_MTRR_PHYSMASK8:
973 case IA32_MTRR_PHYSBASE9: case IA32_MTRR_PHYSMASK9:
974 *puValue = 0;
975 break;
976#endif
977
978 case MSR_IA32_MTRR_DEF_TYPE:
979 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType;
980 break;
981
982 case IA32_MTRR_FIX64K_00000:
983 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix64K_00000;
984 break;
985 case IA32_MTRR_FIX16K_80000:
986 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_80000;
987 break;
988 case IA32_MTRR_FIX16K_A0000:
989 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_A0000;
990 break;
991 case IA32_MTRR_FIX4K_C0000:
992 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C0000;
993 break;
994 case IA32_MTRR_FIX4K_C8000:
995 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C8000;
996 break;
997 case IA32_MTRR_FIX4K_D0000:
998 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D0000;
999 break;
1000 case IA32_MTRR_FIX4K_D8000:
1001 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D8000;
1002 break;
1003 case IA32_MTRR_FIX4K_E0000:
1004 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E0000;
1005 break;
1006 case IA32_MTRR_FIX4K_E8000:
1007 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E8000;
1008 break;
1009 case IA32_MTRR_FIX4K_F0000:
1010 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F0000;
1011 break;
1012 case IA32_MTRR_FIX4K_F8000:
1013 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F8000;
1014 break;
1015
1016 case MSR_K6_EFER:
1017 *puValue = pVCpu->cpum.s.Guest.msrEFER;
1018 break;
1019
1020 case MSR_K8_SF_MASK:
1021 *puValue = pVCpu->cpum.s.Guest.msrSFMASK;
1022 break;
1023
1024 case MSR_K6_STAR:
1025 *puValue = pVCpu->cpum.s.Guest.msrSTAR;
1026 break;
1027
1028 case MSR_K8_LSTAR:
1029 *puValue = pVCpu->cpum.s.Guest.msrLSTAR;
1030 break;
1031
1032 case MSR_K8_CSTAR:
1033 *puValue = pVCpu->cpum.s.Guest.msrCSTAR;
1034 break;
1035
1036 case MSR_K8_FS_BASE:
1037 *puValue = pVCpu->cpum.s.Guest.fs.u64Base;
1038 break;
1039
1040 case MSR_K8_GS_BASE:
1041 *puValue = pVCpu->cpum.s.Guest.gs.u64Base;
1042 break;
1043
1044 case MSR_K8_KERNEL_GS_BASE:
1045 *puValue = pVCpu->cpum.s.Guest.msrKERNELGSBASE;
1046 break;
1047
1048 case MSR_K8_TSC_AUX:
1049 *puValue = pVCpu->cpum.s.GuestMsrs.msr.TscAux;
1050 break;
1051
1052 case MSR_IA32_PERF_STATUS:
1053 /** @todo could really be not exactly correct, maybe use host's values */
1054 *puValue = UINT64_C(1000) /* TSC increment by tick */
1055 | ((uint64_t)u8Multiplier << 24) /* CPU multiplier (aka bus ratio) min */
1056 | ((uint64_t)u8Multiplier << 40) /* CPU multiplier (aka bus ratio) max */;
1057 break;
1058
1059 case MSR_IA32_FSB_CLOCK_STS:
1060 /*
1061 * Encoded as:
1062 * 0 - 266
1063 * 1 - 133
1064 * 2 - 200
1065 * 3 - return 166
1066 * 5 - return 100
1067 */
1068 *puValue = (2 << 4);
1069 break;
1070
1071 case MSR_IA32_PLATFORM_INFO:
1072 *puValue = (u8Multiplier << 8) /* Flex ratio max */
1073 | ((uint64_t)u8Multiplier << 40) /* Flex ratio min */;
1074 break;
1075
1076 case MSR_IA32_THERM_STATUS:
1077 /* CPU temperature relative to TCC, to actually activate, CPUID leaf 6 EAX[0] must be set */
1078 *puValue = RT_BIT(31) /* validity bit */
1079 | (UINT64_C(20) << 16) /* degrees till TCC */;
1080 break;
1081
1082 case MSR_IA32_MISC_ENABLE:
1083#if 0
1084 /* Needs to be tested more before enabling. */
1085 *puValue = pVCpu->cpum.s.GuestMsr.msr.miscEnable;
1086#else
1087 /* Currenty we don't allow guests to modify enable MSRs. */
1088 *puValue = MSR_IA32_MISC_ENABLE_FAST_STRINGS /* by default */;
1089
1090 if ((pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR) != 0)
1091
1092 *puValue |= MSR_IA32_MISC_ENABLE_MONITOR /* if mwait/monitor available */;
1093 /** @todo: add more cpuid-controlled features this way. */
1094#endif
1095 break;
1096
1097 /** @todo virtualize DEBUGCTL and relatives */
1098 case MSR_IA32_DEBUGCTL:
1099 *puValue = 0;
1100 break;
1101
1102#if 0 /*def IN_RING0 */
1103 case MSR_IA32_PLATFORM_ID:
1104 case MSR_IA32_BIOS_SIGN_ID:
1105 if (CPUMGetCPUVendor(pVM) == CPUMCPUVENDOR_INTEL)
1106 {
1107 /* Available since the P6 family. VT-x implies that this feature is present. */
1108 if (idMsr == MSR_IA32_PLATFORM_ID)
1109 *puValue = ASMRdMsr(MSR_IA32_PLATFORM_ID);
1110 else if (idMsr == MSR_IA32_BIOS_SIGN_ID)
1111 *puValue = ASMRdMsr(MSR_IA32_BIOS_SIGN_ID);
1112 break;
1113 }
1114 /* no break */
1115#endif
1116 /*
1117 * The BIOS_SIGN_ID MSR and MSR_IA32_MCP_CAP et al exist on AMD64 as
1118 * well, at least bulldozer have them. Windows 7 is querying them.
1119 * XP has been observed querying MSR_IA32_MC0_CTL.
1120 */
1121 case MSR_IA32_BIOS_SIGN_ID: /* fam/mod >= 6_01 */
1122 case MSR_IA32_MCG_CAP: /* fam/mod >= 6_01 */
1123 case MSR_IA32_MCG_STATUS: /* indicated as not present in CAP */
1124 /*case MSR_IA32_MCG_CTRL: - indicated as not present in CAP */
1125 case MSR_IA32_MC0_CTL:
1126 case MSR_IA32_MC0_STATUS:
1127 *puValue = 0;
1128 break;
1129
1130
1131 /*
1132 * Intel specifics MSRs:
1133 */
1134 case MSR_P5_MC_ADDR:
1135 case MSR_P5_MC_TYPE:
1136 case MSR_P4_LASTBRANCH_TOS: /** @todo Are these branch regs still here on more recent CPUs? The documentation doesn't mention them for several archs. */
1137 case MSR_P4_LASTBRANCH_0:
1138 case MSR_P4_LASTBRANCH_1:
1139 case MSR_P4_LASTBRANCH_2:
1140 case MSR_P4_LASTBRANCH_3:
1141 case MSR_IA32_PERFEVTSEL0: /* NetWare 6.5 wants the these four. (Bet on AMD as well.) */
1142 case MSR_IA32_PERFEVTSEL1:
1143 case MSR_IA32_PMC0:
1144 case MSR_IA32_PMC1:
1145 case MSR_IA32_PLATFORM_ID: /* fam/mod >= 6_01 */
1146 /*case MSR_IA32_BIOS_UPDT_TRIG: - write-only? */
1147 case MSR_RAPL_POWER_UNIT:
1148 case MSR_BBL_CR_CTL3: /* ca. core arch? */
1149 *puValue = 0;
1150 if (CPUMGetGuestCpuVendor(pVCpu->CTX_SUFF(pVM)) != CPUMCPUVENDOR_INTEL)
1151 {
1152 Log(("MSR %#x is Intel, the virtual CPU isn't an Intel one -> #GP\n", idMsr));
1153 rc = VERR_CPUM_RAISE_GP_0;
1154 break;
1155 }
1156
1157 /* Provide more plausive values for some of them. */
1158 switch (idMsr)
1159 {
1160 case MSR_RAPL_POWER_UNIT:
1161 *puValue = RT_MAKE_U32_FROM_U8(3 /* power units (1/8 W)*/,
1162 16 /* 15.3 micro-Joules */,
1163 10 /* 976 microseconds increments */,
1164 0);
1165 break;
1166 case MSR_BBL_CR_CTL3:
1167 *puValue = RT_MAKE_U32_FROM_U8(1, /* bit 0 - L2 Hardware Enabled. (RO) */
1168 1, /* bit 8 - L2 Enabled (R/W). */
1169 0, /* bit 23 - L2 Not Present (RO). */
1170 0);
1171 break;
1172 }
1173 break;
1174
1175#if 0 /* Only on pentium CPUs! */
1176 /* Event counters, not supported. */
1177 case MSR_IA32_CESR:
1178 case MSR_IA32_CTR0:
1179 case MSR_IA32_CTR1:
1180 *puValue = 0;
1181 break;
1182#endif
1183
1184
1185 /*
1186 * AMD specific MSRs:
1187 */
1188 case MSR_K8_SYSCFG:
1189 case MSR_K8_INT_PENDING:
1190 case MSR_K8_NB_CFG: /* (All known values are 0 on reset.) */
1191 case MSR_K8_HWCR: /* Very interesting bits here. :) */
1192 case MSR_K8_VM_CR: /* Windows 8 */
1193 *puValue = 0;
1194 if (CPUMGetGuestCpuVendor(pVCpu->CTX_SUFF(pVM)) != CPUMCPUVENDOR_AMD)
1195 {
1196 Log(("MSR %#x is AMD, the virtual CPU isn't an Intel one -> #GP\n", idMsr));
1197 return VERR_CPUM_RAISE_GP_0;
1198 }
1199 /* ignored */
1200 break;
1201
1202 default:
1203 /*
1204 * Hand the X2APIC range to PDM and the APIC.
1205 */
1206 if ( idMsr >= MSR_IA32_X2APIC_START
1207 && idMsr <= MSR_IA32_X2APIC_END)
1208 {
1209 rc = PDMApicReadMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, puValue);
1210 if (RT_SUCCESS(rc))
1211 rc = VINF_SUCCESS;
1212 else
1213 {
1214 *puValue = 0;
1215 rc = VERR_CPUM_RAISE_GP_0;
1216 }
1217 }
1218 else
1219 {
1220 *puValue = 0;
1221 rc = VERR_CPUM_RAISE_GP_0;
1222 }
1223 break;
1224 }
1225
1226 return rc;
1227}
1228
1229
1230/**
1231 * Sets the MSR.
1232 *
1233 * The caller is responsible for checking privilege if the call is the result
1234 * of a WRMSR instruction. We'll do the rest.
1235 *
1236 * @retval VINF_SUCCESS on success.
1237 * @retval VERR_CPUM_RAISE_GP_0 on failure, the caller is expected to take the
1238 * appropriate actions.
1239 *
1240 * @param pVCpu Pointer to the VMCPU.
1241 * @param idMsr The MSR id.
1242 * @param uValue The value to set.
1243 *
1244 * @remarks Everyone changing MSR values, including the recompiler, shall do it
1245 * by calling this method. This makes sure we have current values and
1246 * that we trigger all the right actions when something changes.
1247 */
1248VMMDECL(int) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue)
1249{
1250 /*
1251 * If we don't indicate MSR support in the CPUID feature bits, indicate
1252 * that a #GP(0) should be raised.
1253 */
1254 if (!(pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_MSR))
1255 return VERR_CPUM_RAISE_GP_0; /** @todo isn't \#UD more correct if not supported? */
1256
1257 int rc = VINF_SUCCESS;
1258 switch (idMsr)
1259 {
1260 case MSR_IA32_MISC_ENABLE:
1261 pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = uValue;
1262 break;
1263
1264 case MSR_IA32_TSC:
1265 TMCpuTickSet(pVCpu->CTX_SUFF(pVM), pVCpu, uValue);
1266 break;
1267
1268 case MSR_IA32_APICBASE:
1269 rc = PDMApicSetBase(pVCpu, uValue);
1270 if (rc != VINF_SUCCESS)
1271 rc = VERR_CPUM_RAISE_GP_0;
1272 break;
1273
1274 case MSR_IA32_CR_PAT:
1275 pVCpu->cpum.s.Guest.msrPAT = uValue;
1276 break;
1277
1278 case MSR_IA32_SYSENTER_CS:
1279 pVCpu->cpum.s.Guest.SysEnter.cs = uValue & 0xffff; /* 16 bits selector */
1280 break;
1281
1282 case MSR_IA32_SYSENTER_EIP:
1283 pVCpu->cpum.s.Guest.SysEnter.eip = uValue;
1284 break;
1285
1286 case MSR_IA32_SYSENTER_ESP:
1287 pVCpu->cpum.s.Guest.SysEnter.esp = uValue;
1288 break;
1289
1290 case MSR_IA32_MTRR_CAP:
1291 return VERR_CPUM_RAISE_GP_0;
1292
1293 case MSR_IA32_MTRR_DEF_TYPE:
1294 if ( (uValue & UINT64_C(0xfffffffffffff300))
1295 || ( (uValue & 0xff) != 0
1296 && (uValue & 0xff) != 1
1297 && (uValue & 0xff) != 4
1298 && (uValue & 0xff) != 5
1299 && (uValue & 0xff) != 6) )
1300 {
1301 Log(("MSR_IA32_MTRR_DEF_TYPE: #GP(0) - writing reserved value (%#llx)\n", uValue));
1302 return VERR_CPUM_RAISE_GP_0;
1303 }
1304 pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType = uValue;
1305 break;
1306
1307 case IA32_MTRR_PHYSBASE0: case IA32_MTRR_PHYSMASK0:
1308 case IA32_MTRR_PHYSBASE1: case IA32_MTRR_PHYSMASK1:
1309 case IA32_MTRR_PHYSBASE2: case IA32_MTRR_PHYSMASK2:
1310 case IA32_MTRR_PHYSBASE3: case IA32_MTRR_PHYSMASK3:
1311 case IA32_MTRR_PHYSBASE4: case IA32_MTRR_PHYSMASK4:
1312 case IA32_MTRR_PHYSBASE5: case IA32_MTRR_PHYSMASK5:
1313 case IA32_MTRR_PHYSBASE6: case IA32_MTRR_PHYSMASK6:
1314 case IA32_MTRR_PHYSBASE7: case IA32_MTRR_PHYSMASK7:
1315 /** @todo implement variable MTRRs. */
1316 break;
1317#if 0 /** @todo newer CPUs have more, figure since when and do selective GP(). */
1318 case IA32_MTRR_PHYSBASE8: case IA32_MTRR_PHYSMASK8:
1319 case IA32_MTRR_PHYSBASE9: case IA32_MTRR_PHYSMASK9:
1320 break;
1321#endif
1322
1323 case IA32_MTRR_FIX64K_00000:
1324 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix64K_00000 = uValue;
1325 break;
1326 case IA32_MTRR_FIX16K_80000:
1327 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_80000 = uValue;
1328 break;
1329 case IA32_MTRR_FIX16K_A0000:
1330 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_A0000 = uValue;
1331 break;
1332 case IA32_MTRR_FIX4K_C0000:
1333 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C0000 = uValue;
1334 break;
1335 case IA32_MTRR_FIX4K_C8000:
1336 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C8000 = uValue;
1337 break;
1338 case IA32_MTRR_FIX4K_D0000:
1339 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D0000 = uValue;
1340 break;
1341 case IA32_MTRR_FIX4K_D8000:
1342 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D8000 = uValue;
1343 break;
1344 case IA32_MTRR_FIX4K_E0000:
1345 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E0000 = uValue;
1346 break;
1347 case IA32_MTRR_FIX4K_E8000:
1348 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E8000 = uValue;
1349 break;
1350 case IA32_MTRR_FIX4K_F0000:
1351 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F0000 = uValue;
1352 break;
1353 case IA32_MTRR_FIX4K_F8000:
1354 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F8000 = uValue;
1355 break;
1356
1357 /*
1358 * AMD64 MSRs.
1359 */
1360 case MSR_K6_EFER:
1361 {
1362 PVM pVM = pVCpu->CTX_SUFF(pVM);
1363 uint64_t const uOldEFER = pVCpu->cpum.s.Guest.msrEFER;
1364 uint32_t const fExtFeatures = pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1365 ? pVM->cpum.s.aGuestCpuIdExt[1].edx
1366 : 0;
1367 uint64_t fMask = 0;
1368
1369 /* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
1370 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_NX)
1371 fMask |= MSR_K6_EFER_NXE;
1372 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
1373 fMask |= MSR_K6_EFER_LME;
1374 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
1375 fMask |= MSR_K6_EFER_SCE;
1376 if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1377 fMask |= MSR_K6_EFER_FFXSR;
1378
1379 /* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if
1380 paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1381 if ( (uOldEFER & MSR_K6_EFER_LME) != (uValue & fMask & MSR_K6_EFER_LME)
1382 && (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG))
1383 {
1384 Log(("Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
1385 return VERR_CPUM_RAISE_GP_0;
1386 }
1387
1388 /* There are a few more: e.g. MSR_K6_EFER_LMSLE */
1389 AssertMsg(!(uValue & ~(MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA /* ignored anyway */ | MSR_K6_EFER_SCE | MSR_K6_EFER_FFXSR)),
1390 ("Unexpected value %RX64\n", uValue));
1391 pVCpu->cpum.s.Guest.msrEFER = (uOldEFER & ~fMask) | (uValue & fMask);
1392
1393 /* AMD64 Architecture Programmer's Manual: 15.15 TLB Control; flush the TLB
1394 if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
1395 if ( (uOldEFER & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA))
1396 != (pVCpu->cpum.s.Guest.msrEFER & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA)))
1397 {
1398 /// @todo PGMFlushTLB(pVCpu, cr3, true /*fGlobal*/);
1399 HMFlushTLB(pVCpu);
1400
1401 /* Notify PGM about NXE changes. */
1402 if ( (uOldEFER & MSR_K6_EFER_NXE)
1403 != (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE))
1404 PGMNotifyNxeChanged(pVCpu, !(uOldEFER & MSR_K6_EFER_NXE));
1405 }
1406 break;
1407 }
1408
1409 case MSR_K8_SF_MASK:
1410 pVCpu->cpum.s.Guest.msrSFMASK = uValue;
1411 break;
1412
1413 case MSR_K6_STAR:
1414 pVCpu->cpum.s.Guest.msrSTAR = uValue;
1415 break;
1416
1417 case MSR_K8_LSTAR:
1418 pVCpu->cpum.s.Guest.msrLSTAR = uValue;
1419 break;
1420
1421 case MSR_K8_CSTAR:
1422 pVCpu->cpum.s.Guest.msrCSTAR = uValue;
1423 break;
1424
1425 case MSR_K8_FS_BASE:
1426 pVCpu->cpum.s.Guest.fs.u64Base = uValue;
1427 break;
1428
1429 case MSR_K8_GS_BASE:
1430 pVCpu->cpum.s.Guest.gs.u64Base = uValue;
1431 break;
1432
1433 case MSR_K8_KERNEL_GS_BASE:
1434 pVCpu->cpum.s.Guest.msrKERNELGSBASE = uValue;
1435 break;
1436
1437 case MSR_K8_TSC_AUX:
1438 pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
1439 break;
1440
1441 case MSR_IA32_DEBUGCTL:
1442 /** @todo virtualize DEBUGCTL and relatives */
1443 break;
1444
1445
1446 /*
1447 * Intel specifics MSRs:
1448 */
1449 /*case MSR_IA32_PLATFORM_ID: - read-only */
1450 case MSR_IA32_BIOS_SIGN_ID: /* fam/mod >= 6_01 */
1451 case MSR_IA32_BIOS_UPDT_TRIG: /* fam/mod >= 6_01 */
1452 /*case MSR_IA32_MCP_CAP: - read-only */
1453 /*case MSR_IA32_MCG_STATUS: - read-only */
1454 /*case MSR_IA32_MCG_CTRL: - indicated as not present in CAP */
1455 /*case MSR_IA32_MC0_CTL: - read-only? */
1456 /*case MSR_IA32_MC0_STATUS: - read-only? */
1457 if (CPUMGetGuestCpuVendor(pVCpu->CTX_SUFF(pVM)) != CPUMCPUVENDOR_INTEL)
1458 {
1459 Log(("MSR %#x is Intel, the virtual CPU isn't an Intel one -> #GP\n", idMsr));
1460 return VERR_CPUM_RAISE_GP_0;
1461 }
1462 /* ignored */
1463 break;
1464
1465 /*
1466 * AMD specific MSRs:
1467 */
1468 case MSR_K8_SYSCFG: /** @todo can be written, but we ignore that for now. */
1469 case MSR_K8_INT_PENDING: /** @todo can be written, but we ignore that for now. */
1470 case MSR_K8_NB_CFG: /** @todo can be written; the apicid swapping might be used and would need saving, but probably unnecessary. */
1471 if (CPUMGetGuestCpuVendor(pVCpu->CTX_SUFF(pVM)) != CPUMCPUVENDOR_AMD)
1472 {
1473 Log(("MSR %#x is AMD, the virtual CPU isn't an Intel one -> #GP\n", idMsr));
1474 return VERR_CPUM_RAISE_GP_0;
1475 }
1476 /* ignored */
1477 break;
1478
1479
1480 default:
1481 /*
1482 * Hand the X2APIC range to PDM and the APIC.
1483 */
1484 if ( idMsr >= MSR_IA32_X2APIC_START
1485 && idMsr <= MSR_IA32_X2APIC_END)
1486 {
1487 rc = PDMApicWriteMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, uValue);
1488 if (rc != VINF_SUCCESS)
1489 rc = VERR_CPUM_RAISE_GP_0;
1490 }
1491 else
1492 {
1493 /* We should actually trigger a #GP here, but don't as that might cause more trouble. */
1494 /** @todo rc = VERR_CPUM_RAISE_GP_0 */
1495 Log(("CPUMSetGuestMsr: Unknown MSR %#x attempted set to %#llx\n", idMsr, uValue));
1496 }
1497 break;
1498 }
1499 return rc;
1500}
1501
1502
1503VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
1504{
1505 if (pcbLimit)
1506 *pcbLimit = pVCpu->cpum.s.Guest.idtr.cbIdt;
1507 return pVCpu->cpum.s.Guest.idtr.pIdt;
1508}
1509
1510
1511VMMDECL(RTSEL) CPUMGetGuestTR(PVMCPU pVCpu, PCPUMSELREGHID pHidden)
1512{
1513 if (pHidden)
1514 *pHidden = pVCpu->cpum.s.Guest.tr;
1515 return pVCpu->cpum.s.Guest.tr.Sel;
1516}
1517
1518
1519VMMDECL(RTSEL) CPUMGetGuestCS(PVMCPU pVCpu)
1520{
1521 return pVCpu->cpum.s.Guest.cs.Sel;
1522}
1523
1524
1525VMMDECL(RTSEL) CPUMGetGuestDS(PVMCPU pVCpu)
1526{
1527 return pVCpu->cpum.s.Guest.ds.Sel;
1528}
1529
1530
1531VMMDECL(RTSEL) CPUMGetGuestES(PVMCPU pVCpu)
1532{
1533 return pVCpu->cpum.s.Guest.es.Sel;
1534}
1535
1536
1537VMMDECL(RTSEL) CPUMGetGuestFS(PVMCPU pVCpu)
1538{
1539 return pVCpu->cpum.s.Guest.fs.Sel;
1540}
1541
1542
1543VMMDECL(RTSEL) CPUMGetGuestGS(PVMCPU pVCpu)
1544{
1545 return pVCpu->cpum.s.Guest.gs.Sel;
1546}
1547
1548
1549VMMDECL(RTSEL) CPUMGetGuestSS(PVMCPU pVCpu)
1550{
1551 return pVCpu->cpum.s.Guest.ss.Sel;
1552}
1553
1554
1555VMMDECL(RTSEL) CPUMGetGuestLDTR(PVMCPU pVCpu)
1556{
1557 return pVCpu->cpum.s.Guest.ldtr.Sel;
1558}
1559
1560
1561VMMDECL(RTSEL) CPUMGetGuestLdtrEx(PVMCPU pVCpu, uint64_t *pGCPtrBase, uint32_t *pcbLimit)
1562{
1563 *pGCPtrBase = pVCpu->cpum.s.Guest.ldtr.u64Base;
1564 *pcbLimit = pVCpu->cpum.s.Guest.ldtr.u32Limit;
1565 return pVCpu->cpum.s.Guest.ldtr.Sel;
1566}
1567
1568
1569VMMDECL(uint64_t) CPUMGetGuestCR0(PVMCPU pVCpu)
1570{
1571 return pVCpu->cpum.s.Guest.cr0;
1572}
1573
1574
1575VMMDECL(uint64_t) CPUMGetGuestCR2(PVMCPU pVCpu)
1576{
1577 return pVCpu->cpum.s.Guest.cr2;
1578}
1579
1580
1581VMMDECL(uint64_t) CPUMGetGuestCR3(PVMCPU pVCpu)
1582{
1583 return pVCpu->cpum.s.Guest.cr3;
1584}
1585
1586
1587VMMDECL(uint64_t) CPUMGetGuestCR4(PVMCPU pVCpu)
1588{
1589 return pVCpu->cpum.s.Guest.cr4;
1590}
1591
1592
1593VMMDECL(uint64_t) CPUMGetGuestCR8(PVMCPU pVCpu)
1594{
1595 uint64_t u64;
1596 int rc = CPUMGetGuestCRx(pVCpu, DISCREG_CR8, &u64);
1597 if (RT_FAILURE(rc))
1598 u64 = 0;
1599 return u64;
1600}
1601
1602
1603VMMDECL(void) CPUMGetGuestGDTR(PVMCPU pVCpu, PVBOXGDTR pGDTR)
1604{
1605 *pGDTR = pVCpu->cpum.s.Guest.gdtr;
1606}
1607
1608
1609VMMDECL(uint32_t) CPUMGetGuestEIP(PVMCPU pVCpu)
1610{
1611 return pVCpu->cpum.s.Guest.eip;
1612}
1613
1614
1615VMMDECL(uint64_t) CPUMGetGuestRIP(PVMCPU pVCpu)
1616{
1617 return pVCpu->cpum.s.Guest.rip;
1618}
1619
1620
1621VMMDECL(uint32_t) CPUMGetGuestEAX(PVMCPU pVCpu)
1622{
1623 return pVCpu->cpum.s.Guest.eax;
1624}
1625
1626
1627VMMDECL(uint32_t) CPUMGetGuestEBX(PVMCPU pVCpu)
1628{
1629 return pVCpu->cpum.s.Guest.ebx;
1630}
1631
1632
1633VMMDECL(uint32_t) CPUMGetGuestECX(PVMCPU pVCpu)
1634{
1635 return pVCpu->cpum.s.Guest.ecx;
1636}
1637
1638
1639VMMDECL(uint32_t) CPUMGetGuestEDX(PVMCPU pVCpu)
1640{
1641 return pVCpu->cpum.s.Guest.edx;
1642}
1643
1644
1645VMMDECL(uint32_t) CPUMGetGuestESI(PVMCPU pVCpu)
1646{
1647 return pVCpu->cpum.s.Guest.esi;
1648}
1649
1650
1651VMMDECL(uint32_t) CPUMGetGuestEDI(PVMCPU pVCpu)
1652{
1653 return pVCpu->cpum.s.Guest.edi;
1654}
1655
1656
1657VMMDECL(uint32_t) CPUMGetGuestESP(PVMCPU pVCpu)
1658{
1659 return pVCpu->cpum.s.Guest.esp;
1660}
1661
1662
1663VMMDECL(uint32_t) CPUMGetGuestEBP(PVMCPU pVCpu)
1664{
1665 return pVCpu->cpum.s.Guest.ebp;
1666}
1667
1668
1669VMMDECL(uint32_t) CPUMGetGuestEFlags(PVMCPU pVCpu)
1670{
1671 return pVCpu->cpum.s.Guest.eflags.u32;
1672}
1673
1674
1675VMMDECL(int) CPUMGetGuestCRx(PVMCPU pVCpu, unsigned iReg, uint64_t *pValue)
1676{
1677 switch (iReg)
1678 {
1679 case DISCREG_CR0:
1680 *pValue = pVCpu->cpum.s.Guest.cr0;
1681 break;
1682
1683 case DISCREG_CR2:
1684 *pValue = pVCpu->cpum.s.Guest.cr2;
1685 break;
1686
1687 case DISCREG_CR3:
1688 *pValue = pVCpu->cpum.s.Guest.cr3;
1689 break;
1690
1691 case DISCREG_CR4:
1692 *pValue = pVCpu->cpum.s.Guest.cr4;
1693 break;
1694
1695 case DISCREG_CR8:
1696 {
1697 uint8_t u8Tpr;
1698 int rc = PDMApicGetTPR(pVCpu, &u8Tpr, NULL /* pfPending */, NULL /* pu8PendingIrq */);
1699 if (RT_FAILURE(rc))
1700 {
1701 AssertMsg(rc == VERR_PDM_NO_APIC_INSTANCE, ("%Rrc\n", rc));
1702 *pValue = 0;
1703 return rc;
1704 }
1705 *pValue = u8Tpr >> 4; /* bits 7-4 contain the task priority that go in cr8, bits 3-0*/
1706 break;
1707 }
1708
1709 default:
1710 return VERR_INVALID_PARAMETER;
1711 }
1712 return VINF_SUCCESS;
1713}
1714
1715
1716VMMDECL(uint64_t) CPUMGetGuestDR0(PVMCPU pVCpu)
1717{
1718 return pVCpu->cpum.s.Guest.dr[0];
1719}
1720
1721
1722VMMDECL(uint64_t) CPUMGetGuestDR1(PVMCPU pVCpu)
1723{
1724 return pVCpu->cpum.s.Guest.dr[1];
1725}
1726
1727
1728VMMDECL(uint64_t) CPUMGetGuestDR2(PVMCPU pVCpu)
1729{
1730 return pVCpu->cpum.s.Guest.dr[2];
1731}
1732
1733
1734VMMDECL(uint64_t) CPUMGetGuestDR3(PVMCPU pVCpu)
1735{
1736 return pVCpu->cpum.s.Guest.dr[3];
1737}
1738
1739
1740VMMDECL(uint64_t) CPUMGetGuestDR6(PVMCPU pVCpu)
1741{
1742 return pVCpu->cpum.s.Guest.dr[6];
1743}
1744
1745
1746VMMDECL(uint64_t) CPUMGetGuestDR7(PVMCPU pVCpu)
1747{
1748 return pVCpu->cpum.s.Guest.dr[7];
1749}
1750
1751
1752VMMDECL(int) CPUMGetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t *pValue)
1753{
1754 AssertReturn(iReg <= DISDREG_DR7, VERR_INVALID_PARAMETER);
1755 /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
1756 if (iReg == 4 || iReg == 5)
1757 iReg += 2;
1758 *pValue = pVCpu->cpum.s.Guest.dr[iReg];
1759 return VINF_SUCCESS;
1760}
1761
1762
1763VMMDECL(uint64_t) CPUMGetGuestEFER(PVMCPU pVCpu)
1764{
1765 return pVCpu->cpum.s.Guest.msrEFER;
1766}
1767
1768
1769/**
1770 * Gets a CPUID leaf.
1771 *
1772 * @param pVCpu Pointer to the VMCPU.
1773 * @param iLeaf The CPUID leaf to get.
1774 * @param pEax Where to store the EAX value.
1775 * @param pEbx Where to store the EBX value.
1776 * @param pEcx Where to store the ECX value.
1777 * @param pEdx Where to store the EDX value.
1778 */
1779VMMDECL(void) CPUMGetGuestCpuId(PVMCPU pVCpu, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx)
1780{
1781 PVM pVM = pVCpu->CTX_SUFF(pVM);
1782
1783 PCCPUMCPUID pCpuId;
1784 if (iLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
1785 pCpuId = &pVM->cpum.s.aGuestCpuIdStd[iLeaf];
1786 else if (iLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
1787 pCpuId = &pVM->cpum.s.aGuestCpuIdExt[iLeaf - UINT32_C(0x80000000)];
1788 else if ( iLeaf - UINT32_C(0x40000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdHyper)
1789 && (pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_HVP))
1790 pCpuId = &pVM->cpum.s.aGuestCpuIdHyper[iLeaf - UINT32_C(0x40000000)]; /* Only report if HVP bit set. */
1791 else if (iLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
1792 pCpuId = &pVM->cpum.s.aGuestCpuIdCentaur[iLeaf - UINT32_C(0xc0000000)];
1793 else
1794 pCpuId = &pVM->cpum.s.GuestCpuIdDef;
1795
1796 uint32_t cCurrentCacheIndex = *pEcx;
1797
1798 *pEax = pCpuId->eax;
1799 *pEbx = pCpuId->ebx;
1800 *pEcx = pCpuId->ecx;
1801 *pEdx = pCpuId->edx;
1802
1803 if ( iLeaf == 1)
1804 {
1805 /* Bits 31-24: Initial APIC ID */
1806 Assert(pVCpu->idCpu <= 255);
1807 *pEbx |= (pVCpu->idCpu << 24);
1808 }
1809
1810 if ( iLeaf == 4
1811 && cCurrentCacheIndex < 3
1812 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
1813 {
1814 uint32_t type, level, sharing, linesize,
1815 partitions, associativity, sets, cores;
1816
1817 /* For type: 1 - data cache, 2 - i-cache, 3 - unified */
1818 partitions = 1;
1819 /* Those are only to shut up compiler, as they will always
1820 get overwritten, and compiler should be able to figure that out */
1821 sets = associativity = sharing = level = 1;
1822 cores = pVM->cCpus > 32 ? 32 : pVM->cCpus;
1823 switch (cCurrentCacheIndex)
1824 {
1825 case 0:
1826 type = 1;
1827 level = 1;
1828 sharing = 1;
1829 linesize = 64;
1830 associativity = 8;
1831 sets = 64;
1832 break;
1833 case 1:
1834 level = 1;
1835 type = 2;
1836 sharing = 1;
1837 linesize = 64;
1838 associativity = 8;
1839 sets = 64;
1840 break;
1841 default: /* shut up gcc.*/
1842 AssertFailed();
1843 case 2:
1844 level = 2;
1845 type = 3;
1846 sharing = cores; /* our L2 cache is modelled as shared between all cores */
1847 linesize = 64;
1848 associativity = 24;
1849 sets = 4096;
1850 break;
1851 }
1852
1853 *pEax |= ((cores - 1) << 26) |
1854 ((sharing - 1) << 14) |
1855 (level << 5) |
1856 1;
1857 *pEbx = (linesize - 1) |
1858 ((partitions - 1) << 12) |
1859 ((associativity - 1) << 22); /* -1 encoding */
1860 *pEcx = sets - 1;
1861 }
1862
1863 Log2(("CPUMGetGuestCpuId: iLeaf=%#010x %RX32 %RX32 %RX32 %RX32\n", iLeaf, *pEax, *pEbx, *pEcx, *pEdx));
1864}
1865
1866/**
1867 * Gets a number of standard CPUID leafs.
1868 *
1869 * @returns Number of leafs.
1870 * @param pVM Pointer to the VM.
1871 * @remark Intended for PATM.
1872 */
1873VMMDECL(uint32_t) CPUMGetGuestCpuIdStdMax(PVM pVM)
1874{
1875 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd);
1876}
1877
1878
1879/**
1880 * Gets a number of extended CPUID leafs.
1881 *
1882 * @returns Number of leafs.
1883 * @param pVM Pointer to the VM.
1884 * @remark Intended for PATM.
1885 */
1886VMMDECL(uint32_t) CPUMGetGuestCpuIdExtMax(PVM pVM)
1887{
1888 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt);
1889}
1890
1891
1892/**
1893 * Gets a number of centaur CPUID leafs.
1894 *
1895 * @returns Number of leafs.
1896 * @param pVM Pointer to the VM.
1897 * @remark Intended for PATM.
1898 */
1899VMMDECL(uint32_t) CPUMGetGuestCpuIdCentaurMax(PVM pVM)
1900{
1901 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur);
1902}
1903
1904
1905/**
1906 * Sets a CPUID feature bit.
1907 *
1908 * @param pVM Pointer to the VM.
1909 * @param enmFeature The feature to set.
1910 */
1911VMMDECL(void) CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
1912{
1913 switch (enmFeature)
1914 {
1915 /*
1916 * Set the APIC bit in both feature masks.
1917 */
1918 case CPUMCPUIDFEATURE_APIC:
1919 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1920 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_APIC;
1921 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1922 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1923 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_APIC;
1924 LogRel(("CPUMSetGuestCpuIdFeature: Enabled APIC\n"));
1925 break;
1926
1927 /*
1928 * Set the x2APIC bit in the standard feature mask.
1929 */
1930 case CPUMCPUIDFEATURE_X2APIC:
1931 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1932 pVM->cpum.s.aGuestCpuIdStd[1].ecx |= X86_CPUID_FEATURE_ECX_X2APIC;
1933 LogRel(("CPUMSetGuestCpuIdFeature: Enabled x2APIC\n"));
1934 break;
1935
1936 /*
1937 * Set the sysenter/sysexit bit in the standard feature mask.
1938 * Assumes the caller knows what it's doing! (host must support these)
1939 */
1940 case CPUMCPUIDFEATURE_SEP:
1941 {
1942 if (!(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_SEP))
1943 {
1944 AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
1945 return;
1946 }
1947
1948 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1949 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_SEP;
1950 LogRel(("CPUMSetGuestCpuIdFeature: Enabled sysenter/exit\n"));
1951 break;
1952 }
1953
1954 /*
1955 * Set the syscall/sysret bit in the extended feature mask.
1956 * Assumes the caller knows what it's doing! (host must support these)
1957 */
1958 case CPUMCPUIDFEATURE_SYSCALL:
1959 {
1960 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1961 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_SYSCALL))
1962 {
1963#if HC_ARCH_BITS == 32
1964 /* X86_CPUID_EXT_FEATURE_EDX_SYSCALL not set it seems in 32 bits mode.
1965 * Even when the cpu is capable of doing so in 64 bits mode.
1966 */
1967 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1968 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
1969 || !(ASMCpuId_EDX(1) & X86_CPUID_EXT_FEATURE_EDX_SYSCALL))
1970#endif
1971 {
1972 LogRel(("WARNING: Can't turn on SYSCALL/SYSRET when the host doesn't support it!!\n"));
1973 return;
1974 }
1975 }
1976 /* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
1977 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
1978 LogRel(("CPUMSetGuestCpuIdFeature: Enabled syscall/ret\n"));
1979 break;
1980 }
1981
1982 /*
1983 * Set the PAE bit in both feature masks.
1984 * Assumes the caller knows what it's doing! (host must support these)
1985 */
1986 case CPUMCPUIDFEATURE_PAE:
1987 {
1988 if (!(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_PAE))
1989 {
1990 LogRel(("WARNING: Can't turn on PAE when the host doesn't support it!!\n"));
1991 return;
1992 }
1993
1994 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1995 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_PAE;
1996 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1997 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1998 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_PAE;
1999 LogRel(("CPUMSetGuestCpuIdFeature: Enabled PAE\n"));
2000 break;
2001 }
2002
2003 /*
2004 * Set the LONG MODE bit in the extended feature mask.
2005 * Assumes the caller knows what it's doing! (host must support these)
2006 */
2007 case CPUMCPUIDFEATURE_LONG_MODE:
2008 {
2009 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
2010 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE))
2011 {
2012 LogRel(("WARNING: Can't turn on LONG MODE when the host doesn't support it!!\n"));
2013 return;
2014 }
2015
2016 /* Valid for both Intel and AMD. */
2017 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
2018 LogRel(("CPUMSetGuestCpuIdFeature: Enabled LONG MODE\n"));
2019 break;
2020 }
2021
2022 /*
2023 * Set the NX/XD bit in the extended feature mask.
2024 * Assumes the caller knows what it's doing! (host must support these)
2025 */
2026 case CPUMCPUIDFEATURE_NX:
2027 {
2028 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
2029 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_NX))
2030 {
2031 LogRel(("WARNING: Can't turn on NX/XD when the host doesn't support it!!\n"));
2032 return;
2033 }
2034
2035 /* Valid for both Intel and AMD. */
2036 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_NX;
2037 LogRel(("CPUMSetGuestCpuIdFeature: Enabled NX\n"));
2038 break;
2039 }
2040
2041 /*
2042 * Set the LAHF/SAHF support in 64-bit mode.
2043 * Assumes the caller knows what it's doing! (host must support this)
2044 */
2045 case CPUMCPUIDFEATURE_LAHF:
2046 {
2047 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
2048 || !(ASMCpuId_ECX(0x80000001) & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF))
2049 {
2050 LogRel(("WARNING: Can't turn on LAHF/SAHF when the host doesn't support it!!\n"));
2051 return;
2052 }
2053
2054 /* Valid for both Intel and AMD. */
2055 pVM->cpum.s.aGuestCpuIdExt[1].ecx |= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
2056 LogRel(("CPUMSetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
2057 break;
2058 }
2059
2060 case CPUMCPUIDFEATURE_PAT:
2061 {
2062 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2063 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_PAT;
2064 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
2065 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
2066 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_PAT;
2067 LogRel(("CPUMSetGuestCpuIdFeature: Enabled PAT\n"));
2068 break;
2069 }
2070
2071 /*
2072 * Set the RDTSCP support bit.
2073 * Assumes the caller knows what it's doing! (host must support this)
2074 */
2075 case CPUMCPUIDFEATURE_RDTSCP:
2076 {
2077 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
2078 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
2079 || pVM->cpum.s.u8PortableCpuIdLevel > 0)
2080 {
2081 if (!pVM->cpum.s.u8PortableCpuIdLevel)
2082 LogRel(("WARNING: Can't turn on RDTSCP when the host doesn't support it!!\n"));
2083 return;
2084 }
2085
2086 /* Valid for both Intel and AMD. */
2087 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
2088 LogRel(("CPUMSetGuestCpuIdFeature: Enabled RDTSCP.\n"));
2089 break;
2090 }
2091
2092 /*
2093 * Set the Hypervisor Present bit in the standard feature mask.
2094 */
2095 case CPUMCPUIDFEATURE_HVP:
2096 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2097 pVM->cpum.s.aGuestCpuIdStd[1].ecx |= X86_CPUID_FEATURE_ECX_HVP;
2098 LogRel(("CPUMSetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
2099 break;
2100
2101 default:
2102 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
2103 break;
2104 }
2105 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2106 {
2107 PVMCPU pVCpu = &pVM->aCpus[i];
2108 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CPUID;
2109 }
2110}
2111
2112
2113/**
2114 * Queries a CPUID feature bit.
2115 *
2116 * @returns boolean for feature presence
2117 * @param pVM Pointer to the VM.
2118 * @param enmFeature The feature to query.
2119 */
2120VMMDECL(bool) CPUMGetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
2121{
2122 switch (enmFeature)
2123 {
2124 case CPUMCPUIDFEATURE_PAE:
2125 {
2126 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2127 return !!(pVM->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PAE);
2128 break;
2129 }
2130
2131 case CPUMCPUIDFEATURE_NX:
2132 {
2133 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
2134 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_EXT_FEATURE_EDX_NX);
2135 }
2136
2137 case CPUMCPUIDFEATURE_SYSCALL:
2138 {
2139 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
2140 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
2141 }
2142
2143 case CPUMCPUIDFEATURE_RDTSCP:
2144 {
2145 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
2146 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2147 break;
2148 }
2149
2150 case CPUMCPUIDFEATURE_LONG_MODE:
2151 {
2152 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
2153 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
2154 break;
2155 }
2156
2157 default:
2158 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
2159 break;
2160 }
2161 return false;
2162}
2163
2164
2165/**
2166 * Clears a CPUID feature bit.
2167 *
2168 * @param pVM Pointer to the VM.
2169 * @param enmFeature The feature to clear.
2170 */
2171VMMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
2172{
2173 switch (enmFeature)
2174 {
2175 /*
2176 * Set the APIC bit in both feature masks.
2177 */
2178 case CPUMCPUIDFEATURE_APIC:
2179 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2180 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_APIC;
2181 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
2182 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
2183 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
2184 Log(("CPUMClearGuestCpuIdFeature: Disabled APIC\n"));
2185 break;
2186
2187 /*
2188 * Clear the x2APIC bit in the standard feature mask.
2189 */
2190 case CPUMCPUIDFEATURE_X2APIC:
2191 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2192 pVM->cpum.s.aGuestCpuIdStd[1].ecx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
2193 Log(("CPUMClearGuestCpuIdFeature: Disabled x2APIC\n"));
2194 break;
2195
2196 case CPUMCPUIDFEATURE_PAE:
2197 {
2198 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2199 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_PAE;
2200 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
2201 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
2202 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
2203 Log(("CPUMClearGuestCpuIdFeature: Disabled PAE!\n"));
2204 break;
2205 }
2206
2207 case CPUMCPUIDFEATURE_PAT:
2208 {
2209 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2210 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_PAT;
2211 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
2212 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
2213 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_PAT;
2214 Log(("CPUMClearGuestCpuIdFeature: Disabled PAT!\n"));
2215 break;
2216 }
2217
2218 case CPUMCPUIDFEATURE_LONG_MODE:
2219 {
2220 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
2221 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
2222 break;
2223 }
2224
2225 case CPUMCPUIDFEATURE_LAHF:
2226 {
2227 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
2228 pVM->cpum.s.aGuestCpuIdExt[1].ecx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
2229 break;
2230 }
2231
2232 case CPUMCPUIDFEATURE_RDTSCP:
2233 {
2234 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
2235 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
2236 Log(("CPUMClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
2237 break;
2238 }
2239
2240 case CPUMCPUIDFEATURE_HVP:
2241 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2242 pVM->cpum.s.aGuestCpuIdStd[1].ecx &= ~X86_CPUID_FEATURE_ECX_HVP;
2243 break;
2244
2245 default:
2246 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
2247 break;
2248 }
2249 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2250 {
2251 PVMCPU pVCpu = &pVM->aCpus[i];
2252 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CPUID;
2253 }
2254}
2255
2256
2257/**
2258 * Gets the host CPU vendor.
2259 *
2260 * @returns CPU vendor.
2261 * @param pVM Pointer to the VM.
2262 */
2263VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM)
2264{
2265 return pVM->cpum.s.enmHostCpuVendor;
2266}
2267
2268
2269/**
2270 * Gets the CPU vendor.
2271 *
2272 * @returns CPU vendor.
2273 * @param pVM Pointer to the VM.
2274 */
2275VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM)
2276{
2277 return pVM->cpum.s.enmGuestCpuVendor;
2278}
2279
2280
2281VMMDECL(int) CPUMSetGuestDR0(PVMCPU pVCpu, uint64_t uDr0)
2282{
2283 pVCpu->cpum.s.Guest.dr[0] = uDr0;
2284 return CPUMRecalcHyperDRx(pVCpu, 0, false);
2285}
2286
2287
2288VMMDECL(int) CPUMSetGuestDR1(PVMCPU pVCpu, uint64_t uDr1)
2289{
2290 pVCpu->cpum.s.Guest.dr[1] = uDr1;
2291 return CPUMRecalcHyperDRx(pVCpu, 1, false);
2292}
2293
2294
2295VMMDECL(int) CPUMSetGuestDR2(PVMCPU pVCpu, uint64_t uDr2)
2296{
2297 pVCpu->cpum.s.Guest.dr[2] = uDr2;
2298 return CPUMRecalcHyperDRx(pVCpu, 2, false);
2299}
2300
2301
2302VMMDECL(int) CPUMSetGuestDR3(PVMCPU pVCpu, uint64_t uDr3)
2303{
2304 pVCpu->cpum.s.Guest.dr[3] = uDr3;
2305 return CPUMRecalcHyperDRx(pVCpu, 3, false);
2306}
2307
2308
2309VMMDECL(int) CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6)
2310{
2311 pVCpu->cpum.s.Guest.dr[6] = uDr6;
2312 return VINF_SUCCESS; /* No need to recalc. */
2313}
2314
2315
2316VMMDECL(int) CPUMSetGuestDR7(PVMCPU pVCpu, uint64_t uDr7)
2317{
2318 pVCpu->cpum.s.Guest.dr[7] = uDr7;
2319 return CPUMRecalcHyperDRx(pVCpu, 7, false);
2320}
2321
2322
2323VMMDECL(int) CPUMSetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t Value)
2324{
2325 AssertReturn(iReg <= DISDREG_DR7, VERR_INVALID_PARAMETER);
2326 /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
2327 if (iReg == 4 || iReg == 5)
2328 iReg += 2;
2329 pVCpu->cpum.s.Guest.dr[iReg] = Value;
2330 return CPUMRecalcHyperDRx(pVCpu, iReg, false);
2331}
2332
2333
2334/**
2335 * Recalculates the hypervisor DRx register values based on current guest
2336 * registers and DBGF breakpoints, updating changed registers depending on the
2337 * context.
2338 *
2339 * This is called whenever a guest DRx register is modified (any context) and
2340 * when DBGF sets a hardware breakpoint (ring-3 only, rendezvous).
2341 *
2342 * In raw-mode context this function will reload any (hyper) DRx registers which
2343 * comes out with a different value. It may also have to save the host debug
2344 * registers if that haven't been done already. In this context though, we'll
2345 * be intercepting and emulating all DRx accesses, so the hypervisor DRx values
2346 * are only important when breakpoints are actually enabled.
2347 *
2348 * In ring-0 (HM) context DR0-3 will be relocated by us, while DR7 will be
2349 * reloaded by the HM code if it changes. Further more, we will only use the
2350 * combined register set when the VBox debugger is actually using hardware BPs,
2351 * when it isn't we'll keep the guest DR0-3 + (maybe) DR6 loaded (DR6 doesn't
2352 * concern us here).
2353 *
2354 * In ring-3 we won't be loading anything, so well calculate hypervisor values
2355 * all the time.
2356 *
2357 * @returns VINF_SUCCESS.
2358 * @param pVCpu Pointer to the VMCPU.
2359 * @param iGstReg The guest debug register number that was modified.
2360 * UINT8_MAX if not guest register.
2361 * @param fForceHyper Used in HM to force hyper registers because of single
2362 * stepping.
2363 */
2364VMMDECL(int) CPUMRecalcHyperDRx(PVMCPU pVCpu, uint8_t iGstReg, bool fForceHyper)
2365{
2366 PVM pVM = pVCpu->CTX_SUFF(pVM);
2367
2368 /*
2369 * Compare the DR7s first.
2370 *
2371 * We only care about the enabled flags. GD is virtualized when we
2372 * dispatch the #DB, we never enable it. The DBGF DR7 value is will
2373 * always have the LE and GE bits set, so no need to check and disable
2374 * stuff if they're cleared like we have to for the guest DR7.
2375 */
2376 RTGCUINTREG uGstDr7 = CPUMGetGuestDR7(pVCpu);
2377 if (!(uGstDr7 & (X86_DR7_LE | X86_DR7_GE)))
2378 uGstDr7 = 0;
2379 else if (!(uGstDr7 & X86_DR7_LE))
2380 uGstDr7 &= ~X86_DR7_LE_ALL;
2381 else if (!(uGstDr7 & X86_DR7_GE))
2382 uGstDr7 &= ~X86_DR7_GE_ALL;
2383
2384 const RTGCUINTREG uDbgfDr7 = DBGFBpGetDR7(pVM);
2385
2386#ifdef IN_RING0
2387 if (!fForceHyper && (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HYPER))
2388 fForceHyper = true;
2389#endif
2390 if (( HMIsEnabled(pVCpu->CTX_SUFF(pVM)) && !fForceHyper ? uDbgfDr7 : (uGstDr7 | uDbgfDr7)) & X86_DR7_ENABLED_MASK)
2391 {
2392 Assert(!CPUMIsGuestDebugStateActive(pVCpu));
2393#ifdef IN_RC
2394 bool const fHmEnabled = false;
2395#elif defined(IN_RING3)
2396 bool const fHmEnabled = HMIsEnabled(pVM);
2397#endif
2398
2399 /*
2400 * Ok, something is enabled. Recalc each of the breakpoints, taking
2401 * the VM debugger ones of the guest ones. In raw-mode context we will
2402 * not allow breakpoints with values inside the hypervisor area.
2403 */
2404 RTGCUINTREG uNewDr7 = X86_DR7_GE | X86_DR7_LE | X86_DR7_RA1_MASK;
2405
2406 /* bp 0 */
2407 RTGCUINTREG uNewDr0;
2408 if (uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0))
2409 {
2410 uNewDr7 |= uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
2411 uNewDr0 = DBGFBpGetDR0(pVM);
2412 }
2413 else if (uGstDr7 & (X86_DR7_L0 | X86_DR7_G0))
2414 {
2415 uNewDr0 = CPUMGetGuestDR0(pVCpu);
2416#ifndef IN_RING0
2417 if (fHmEnabled && MMHyperIsInsideArea(pVM, uNewDr0))
2418 uNewDr0 = 0;
2419 else
2420#endif
2421 uNewDr7 |= uGstDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
2422 }
2423 else
2424 uNewDr0 = 0;
2425
2426 /* bp 1 */
2427 RTGCUINTREG uNewDr1;
2428 if (uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1))
2429 {
2430 uNewDr7 |= uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
2431 uNewDr1 = DBGFBpGetDR1(pVM);
2432 }
2433 else if (uGstDr7 & (X86_DR7_L1 | X86_DR7_G1))
2434 {
2435 uNewDr1 = CPUMGetGuestDR1(pVCpu);
2436#ifndef IN_RING0
2437 if (fHmEnabled && MMHyperIsInsideArea(pVM, uNewDr1))
2438 uNewDr1 = 0;
2439 else
2440#endif
2441 uNewDr7 |= uGstDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
2442 }
2443 else
2444 uNewDr1 = 0;
2445
2446 /* bp 2 */
2447 RTGCUINTREG uNewDr2;
2448 if (uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2))
2449 {
2450 uNewDr7 |= uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
2451 uNewDr2 = DBGFBpGetDR2(pVM);
2452 }
2453 else if (uGstDr7 & (X86_DR7_L2 | X86_DR7_G2))
2454 {
2455 uNewDr2 = CPUMGetGuestDR2(pVCpu);
2456#ifndef IN_RING0
2457 if (fHmEnabled && MMHyperIsInsideArea(pVM, uNewDr2))
2458 uNewDr2 = 0;
2459 else
2460#endif
2461 uNewDr7 |= uGstDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
2462 }
2463 else
2464 uNewDr2 = 0;
2465
2466 /* bp 3 */
2467 RTGCUINTREG uNewDr3;
2468 if (uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3))
2469 {
2470 uNewDr7 |= uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
2471 uNewDr3 = DBGFBpGetDR3(pVM);
2472 }
2473 else if (uGstDr7 & (X86_DR7_L3 | X86_DR7_G3))
2474 {
2475 uNewDr3 = CPUMGetGuestDR3(pVCpu);
2476#ifndef IN_RING0
2477 if (fHmEnabled && MMHyperIsInsideArea(pVM, uNewDr3))
2478 uNewDr3 = 0;
2479 else
2480#endif
2481 uNewDr7 |= uGstDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
2482 }
2483 else
2484 uNewDr3 = 0;
2485
2486 /*
2487 * Apply the updates.
2488 */
2489#ifdef IN_RC
2490 /* Make sure to save host registers first. */
2491 if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HOST))
2492 {
2493 if (!(pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS_HOST))
2494 {
2495 pVCpu->cpum.s.Host.dr6 = ASMGetDR6();
2496 pVCpu->cpum.s.Host.dr7 = ASMGetDR7();
2497 }
2498 pVCpu->cpum.s.Host.dr0 = ASMGetDR0();
2499 pVCpu->cpum.s.Host.dr1 = ASMGetDR1();
2500 pVCpu->cpum.s.Host.dr2 = ASMGetDR2();
2501 pVCpu->cpum.s.Host.dr3 = ASMGetDR3();
2502 pVCpu->cpum.s.fUseFlags |= CPUM_USED_DEBUG_REGS_HOST | CPUM_USE_DEBUG_REGS_HYPER | CPUM_USED_DEBUG_REGS_HYPER;
2503
2504 /* We haven't loaded any hyper DRxes yet, so we'll have to load them all now. */
2505 pVCpu->cpum.s.Hyper.dr[0] = uNewDr0;
2506 ASMSetDR0(uNewDr0);
2507 pVCpu->cpum.s.Hyper.dr[1] = uNewDr1;
2508 ASMSetDR1(uNewDr1);
2509 pVCpu->cpum.s.Hyper.dr[2] = uNewDr2;
2510 ASMSetDR2(uNewDr2);
2511 pVCpu->cpum.s.Hyper.dr[3] = uNewDr3;
2512 ASMSetDR3(uNewDr3);
2513 ASMSetDR6(X86_DR6_INIT_VAL);
2514 pVCpu->cpum.s.Hyper.dr[7] = uNewDr7;
2515 ASMSetDR7(uNewDr7);
2516 }
2517 else
2518#endif
2519 {
2520 pVCpu->cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS_HYPER;
2521 if (uNewDr3 != pVCpu->cpum.s.Hyper.dr[3])
2522 CPUMSetHyperDR3(pVCpu, uNewDr3);
2523 if (uNewDr2 != pVCpu->cpum.s.Hyper.dr[2])
2524 CPUMSetHyperDR2(pVCpu, uNewDr2);
2525 if (uNewDr1 != pVCpu->cpum.s.Hyper.dr[1])
2526 CPUMSetHyperDR1(pVCpu, uNewDr1);
2527 if (uNewDr0 != pVCpu->cpum.s.Hyper.dr[0])
2528 CPUMSetHyperDR0(pVCpu, uNewDr0);
2529 if (uNewDr7 != pVCpu->cpum.s.Hyper.dr[7])
2530 CPUMSetHyperDR7(pVCpu, uNewDr7);
2531 }
2532 }
2533#ifdef IN_RING0
2534 else if (CPUMIsGuestDebugStateActive(pVCpu))
2535 {
2536 /*
2537 * Reload the register that was modified. Normally this won't happen
2538 * as we won't intercept DRx writes when not having the hyper debug
2539 * state loaded, but in case we do for some reason we'll simply deal
2540 * with it.
2541 */
2542 switch (iGstReg)
2543 {
2544 case 0: ASMSetDR0(CPUMGetGuestDR0(pVCpu)); break;
2545 case 1: ASMSetDR1(CPUMGetGuestDR1(pVCpu)); break;
2546 case 2: ASMSetDR2(CPUMGetGuestDR2(pVCpu)); break;
2547 case 3: ASMSetDR3(CPUMGetGuestDR3(pVCpu)); break;
2548 default:
2549 AssertReturn(iGstReg != UINT8_MAX, VERR_INTERNAL_ERROR_3);
2550 }
2551 }
2552#endif
2553 else
2554 {
2555 /*
2556 * No active debug state any more. In raw-mode this means we have to
2557 * make sure DR7 has everything disabled now, if we armed it already.
2558 * In ring-0 we might end up here when just single stepping.
2559 */
2560#if defined(IN_RC) || defined(IN_RING0)
2561 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HYPER)
2562 {
2563# ifdef IN_RC
2564 ASMSetDR7(X86_DR7_INIT_VAL);
2565# endif
2566 if (pVCpu->cpum.s.Hyper.dr[0])
2567 ASMSetDR0(0);
2568 if (pVCpu->cpum.s.Hyper.dr[1])
2569 ASMSetDR1(0);
2570 if (pVCpu->cpum.s.Hyper.dr[2])
2571 ASMSetDR2(0);
2572 if (pVCpu->cpum.s.Hyper.dr[3])
2573 ASMSetDR3(0);
2574 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_DEBUG_REGS_HYPER;
2575 }
2576#endif
2577 pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS_HYPER;
2578
2579 /* Clear all the registers. */
2580 pVCpu->cpum.s.Hyper.dr[7] = X86_DR7_RA1_MASK;
2581 pVCpu->cpum.s.Hyper.dr[3] = 0;
2582 pVCpu->cpum.s.Hyper.dr[2] = 0;
2583 pVCpu->cpum.s.Hyper.dr[1] = 0;
2584 pVCpu->cpum.s.Hyper.dr[0] = 0;
2585
2586 }
2587 Log2(("CPUMRecalcHyperDRx: fUseFlags=%#x %RGr %RGr %RGr %RGr %RGr %RGr\n",
2588 pVCpu->cpum.s.fUseFlags, pVCpu->cpum.s.Hyper.dr[0], pVCpu->cpum.s.Hyper.dr[1],
2589 pVCpu->cpum.s.Hyper.dr[2], pVCpu->cpum.s.Hyper.dr[3], pVCpu->cpum.s.Hyper.dr[6],
2590 pVCpu->cpum.s.Hyper.dr[7]));
2591
2592 return VINF_SUCCESS;
2593}
2594
2595
2596/**
2597 * Tests if the guest has No-Execute Page Protection Enabled (NXE).
2598 *
2599 * @returns true if in real mode, otherwise false.
2600 * @param pVCpu Pointer to the VMCPU.
2601 */
2602VMMDECL(bool) CPUMIsGuestNXEnabled(PVMCPU pVCpu)
2603{
2604 return !!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE);
2605}
2606
2607
2608/**
2609 * Tests if the guest has the Page Size Extension enabled (PSE).
2610 *
2611 * @returns true if in real mode, otherwise false.
2612 * @param pVCpu Pointer to the VMCPU.
2613 */
2614VMMDECL(bool) CPUMIsGuestPageSizeExtEnabled(PVMCPU pVCpu)
2615{
2616 /* PAE or AMD64 implies support for big pages regardless of CR4.PSE */
2617 return !!(pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PSE | X86_CR4_PAE));
2618}
2619
2620
2621/**
2622 * Tests if the guest has the paging enabled (PG).
2623 *
2624 * @returns true if in real mode, otherwise false.
2625 * @param pVCpu Pointer to the VMCPU.
2626 */
2627VMMDECL(bool) CPUMIsGuestPagingEnabled(PVMCPU pVCpu)
2628{
2629 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG);
2630}
2631
2632
2633/**
2634 * Tests if the guest has the paging enabled (PG).
2635 *
2636 * @returns true if in real mode, otherwise false.
2637 * @param pVCpu Pointer to the VMCPU.
2638 */
2639VMMDECL(bool) CPUMIsGuestR0WriteProtEnabled(PVMCPU pVCpu)
2640{
2641 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_WP);
2642}
2643
2644
2645/**
2646 * Tests if the guest is running in real mode or not.
2647 *
2648 * @returns true if in real mode, otherwise false.
2649 * @param pVCpu Pointer to the VMCPU.
2650 */
2651VMMDECL(bool) CPUMIsGuestInRealMode(PVMCPU pVCpu)
2652{
2653 return !(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
2654}
2655
2656
2657/**
2658 * Tests if the guest is running in real or virtual 8086 mode.
2659 *
2660 * @returns @c true if it is, @c false if not.
2661 * @param pVCpu Pointer to the VMCPU.
2662 */
2663VMMDECL(bool) CPUMIsGuestInRealOrV86Mode(PVMCPU pVCpu)
2664{
2665 return !(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE)
2666 || pVCpu->cpum.s.Guest.eflags.Bits.u1VM; /** @todo verify that this cannot be set in long mode. */
2667}
2668
2669
2670/**
2671 * Tests if the guest is running in protected or not.
2672 *
2673 * @returns true if in protected mode, otherwise false.
2674 * @param pVCpu Pointer to the VMCPU.
2675 */
2676VMMDECL(bool) CPUMIsGuestInProtectedMode(PVMCPU pVCpu)
2677{
2678 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
2679}
2680
2681
2682/**
2683 * Tests if the guest is running in paged protected or not.
2684 *
2685 * @returns true if in paged protected mode, otherwise false.
2686 * @param pVCpu Pointer to the VMCPU.
2687 */
2688VMMDECL(bool) CPUMIsGuestInPagedProtectedMode(PVMCPU pVCpu)
2689{
2690 return (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
2691}
2692
2693
2694/**
2695 * Tests if the guest is running in long mode or not.
2696 *
2697 * @returns true if in long mode, otherwise false.
2698 * @param pVCpu Pointer to the VMCPU.
2699 */
2700VMMDECL(bool) CPUMIsGuestInLongMode(PVMCPU pVCpu)
2701{
2702 return (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
2703}
2704
2705
2706/**
2707 * Tests if the guest is running in PAE mode or not.
2708 *
2709 * @returns true if in PAE mode, otherwise false.
2710 * @param pVCpu Pointer to the VMCPU.
2711 */
2712VMMDECL(bool) CPUMIsGuestInPAEMode(PVMCPU pVCpu)
2713{
2714 return (pVCpu->cpum.s.Guest.cr4 & X86_CR4_PAE)
2715 && (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG)
2716 && !(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LME);
2717}
2718
2719
2720/**
2721 * Tests if the guest is running in 64 bits mode or not.
2722 *
2723 * @returns true if in 64 bits protected mode, otherwise false.
2724 * @param pVCpu The current virtual CPU.
2725 */
2726VMMDECL(bool) CPUMIsGuestIn64BitCode(PVMCPU pVCpu)
2727{
2728 if (!CPUMIsGuestInLongMode(pVCpu))
2729 return false;
2730 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
2731 return pVCpu->cpum.s.Guest.cs.Attr.n.u1Long;
2732}
2733
2734
2735/**
2736 * Helper for CPUMIsGuestIn64BitCodeEx that handles lazy resolving of hidden CS
2737 * registers.
2738 *
2739 * @returns true if in 64 bits protected mode, otherwise false.
2740 * @param pCtx Pointer to the current guest CPU context.
2741 */
2742VMM_INT_DECL(bool) CPUMIsGuestIn64BitCodeSlow(PCPUMCTX pCtx)
2743{
2744 return CPUMIsGuestIn64BitCode(CPUM_GUEST_CTX_TO_VMCPU(pCtx));
2745}
2746
2747#ifdef VBOX_WITH_RAW_MODE_NOT_R0
2748
2749/**
2750 *
2751 * @returns @c true if we've entered raw-mode and selectors with RPL=1 are
2752 * really RPL=0, @c false if we've not (RPL=1 really is RPL=1).
2753 * @param pVCpu The current virtual CPU.
2754 */
2755VMM_INT_DECL(bool) CPUMIsGuestInRawMode(PVMCPU pVCpu)
2756{
2757 return pVCpu->cpum.s.fRawEntered;
2758}
2759
2760/**
2761 * Transforms the guest CPU state to raw-ring mode.
2762 *
2763 * This function will change the any of the cs and ss register with DPL=0 to DPL=1.
2764 *
2765 * @returns VBox status. (recompiler failure)
2766 * @param pVCpu Pointer to the VMCPU.
2767 * @param pCtxCore The context core (for trap usage).
2768 * @see @ref pg_raw
2769 */
2770VMM_INT_DECL(int) CPUMRawEnter(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
2771{
2772 PVM pVM = pVCpu->CTX_SUFF(pVM);
2773
2774 Assert(!pVCpu->cpum.s.fRawEntered);
2775 Assert(!pVCpu->cpum.s.fRemEntered);
2776 if (!pCtxCore)
2777 pCtxCore = CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
2778
2779 /*
2780 * Are we in Ring-0?
2781 */
2782 if ( pCtxCore->ss.Sel
2783 && (pCtxCore->ss.Sel & X86_SEL_RPL) == 0
2784 && !pCtxCore->eflags.Bits.u1VM)
2785 {
2786 /*
2787 * Enter execution mode.
2788 */
2789 PATMRawEnter(pVM, pCtxCore);
2790
2791 /*
2792 * Set CPL to Ring-1.
2793 */
2794 pCtxCore->ss.Sel |= 1;
2795 if ( pCtxCore->cs.Sel
2796 && (pCtxCore->cs.Sel & X86_SEL_RPL) == 0)
2797 pCtxCore->cs.Sel |= 1;
2798 }
2799 else
2800 {
2801# ifdef VBOX_WITH_RAW_RING1
2802 if ( EMIsRawRing1Enabled(pVM)
2803 && !pCtxCore->eflags.Bits.u1VM
2804 && (pCtxCore->ss.Sel & X86_SEL_RPL) == 1)
2805 {
2806 /* Set CPL to Ring-2. */
2807 pCtxCore->ss.Sel = (pCtxCore->ss.Sel & ~X86_SEL_RPL) | 2;
2808 if (pCtxCore->cs.Sel && (pCtxCore->cs.Sel & X86_SEL_RPL) == 1)
2809 pCtxCore->cs.Sel = (pCtxCore->cs.Sel & ~X86_SEL_RPL) | 2;
2810 }
2811# else
2812 AssertMsg((pCtxCore->ss.Sel & X86_SEL_RPL) >= 2 || pCtxCore->eflags.Bits.u1VM,
2813 ("ring-1 code not supported\n"));
2814# endif
2815 /*
2816 * PATM takes care of IOPL and IF flags for Ring-3 and Ring-2 code as well.
2817 */
2818 PATMRawEnter(pVM, pCtxCore);
2819 }
2820
2821 /*
2822 * Assert sanity.
2823 */
2824 AssertMsg((pCtxCore->eflags.u32 & X86_EFL_IF), ("X86_EFL_IF is clear\n"));
2825 AssertReleaseMsg(pCtxCore->eflags.Bits.u2IOPL == 0,
2826 ("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss.Sel & X86_SEL_RPL));
2827 Assert((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)) == (X86_CR0_PG | X86_CR0_PE | X86_CR0_WP));
2828
2829 pCtxCore->eflags.u32 |= X86_EFL_IF; /* paranoia */
2830
2831 pVCpu->cpum.s.fRawEntered = true;
2832 return VINF_SUCCESS;
2833}
2834
2835
2836/**
2837 * Transforms the guest CPU state from raw-ring mode to correct values.
2838 *
2839 * This function will change any selector registers with DPL=1 to DPL=0.
2840 *
2841 * @returns Adjusted rc.
2842 * @param pVCpu Pointer to the VMCPU.
2843 * @param rc Raw mode return code
2844 * @param pCtxCore The context core (for trap usage).
2845 * @see @ref pg_raw
2846 */
2847VMM_INT_DECL(int) CPUMRawLeave(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, int rc)
2848{
2849 PVM pVM = pVCpu->CTX_SUFF(pVM);
2850
2851 /*
2852 * Don't leave if we've already left (in RC).
2853 */
2854 Assert(!pVCpu->cpum.s.fRemEntered);
2855 if (!pVCpu->cpum.s.fRawEntered)
2856 return rc;
2857 pVCpu->cpum.s.fRawEntered = false;
2858
2859 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2860 if (!pCtxCore)
2861 pCtxCore = CPUMCTX2CORE(pCtx);
2862 Assert(pCtxCore->eflags.Bits.u1VM || (pCtxCore->ss.Sel & X86_SEL_RPL));
2863 AssertMsg(pCtxCore->eflags.Bits.u1VM || pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss.Sel & X86_SEL_RPL),
2864 ("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss.Sel & X86_SEL_RPL));
2865
2866 /*
2867 * Are we executing in raw ring-1?
2868 */
2869 if ( (pCtxCore->ss.Sel & X86_SEL_RPL) == 1
2870 && !pCtxCore->eflags.Bits.u1VM)
2871 {
2872 /*
2873 * Leave execution mode.
2874 */
2875 PATMRawLeave(pVM, pCtxCore, rc);
2876 /* Not quite sure if this is really required, but shouldn't harm (too much anyways). */
2877 /** @todo See what happens if we remove this. */
2878 if ((pCtxCore->ds.Sel & X86_SEL_RPL) == 1)
2879 pCtxCore->ds.Sel &= ~X86_SEL_RPL;
2880 if ((pCtxCore->es.Sel & X86_SEL_RPL) == 1)
2881 pCtxCore->es.Sel &= ~X86_SEL_RPL;
2882 if ((pCtxCore->fs.Sel & X86_SEL_RPL) == 1)
2883 pCtxCore->fs.Sel &= ~X86_SEL_RPL;
2884 if ((pCtxCore->gs.Sel & X86_SEL_RPL) == 1)
2885 pCtxCore->gs.Sel &= ~X86_SEL_RPL;
2886
2887 /*
2888 * Ring-1 selector => Ring-0.
2889 */
2890 pCtxCore->ss.Sel &= ~X86_SEL_RPL;
2891 if ((pCtxCore->cs.Sel & X86_SEL_RPL) == 1)
2892 pCtxCore->cs.Sel &= ~X86_SEL_RPL;
2893 }
2894 else
2895 {
2896 /*
2897 * PATM is taking care of the IOPL and IF flags for us.
2898 */
2899 PATMRawLeave(pVM, pCtxCore, rc);
2900 if (!pCtxCore->eflags.Bits.u1VM)
2901 {
2902# ifdef VBOX_WITH_RAW_RING1
2903 if ( EMIsRawRing1Enabled(pVM)
2904 && (pCtxCore->ss.Sel & X86_SEL_RPL) == 2)
2905 {
2906 /* Not quite sure if this is really required, but shouldn't harm (too much anyways). */
2907 /** @todo See what happens if we remove this. */
2908 if ((pCtxCore->ds.Sel & X86_SEL_RPL) == 2)
2909 pCtxCore->ds.Sel = (pCtxCore->ds.Sel & ~X86_SEL_RPL) | 1;
2910 if ((pCtxCore->es.Sel & X86_SEL_RPL) == 2)
2911 pCtxCore->es.Sel = (pCtxCore->es.Sel & ~X86_SEL_RPL) | 1;
2912 if ((pCtxCore->fs.Sel & X86_SEL_RPL) == 2)
2913 pCtxCore->fs.Sel = (pCtxCore->fs.Sel & ~X86_SEL_RPL) | 1;
2914 if ((pCtxCore->gs.Sel & X86_SEL_RPL) == 2)
2915 pCtxCore->gs.Sel = (pCtxCore->gs.Sel & ~X86_SEL_RPL) | 1;
2916
2917 /*
2918 * Ring-2 selector => Ring-1.
2919 */
2920 pCtxCore->ss.Sel = (pCtxCore->ss.Sel & ~X86_SEL_RPL) | 1;
2921 if ((pCtxCore->cs.Sel & X86_SEL_RPL) == 2)
2922 pCtxCore->cs.Sel = (pCtxCore->cs.Sel & ~X86_SEL_RPL) | 1;
2923 }
2924 else
2925 {
2926# endif
2927 /** @todo See what happens if we remove this. */
2928 if ((pCtxCore->ds.Sel & X86_SEL_RPL) == 1)
2929 pCtxCore->ds.Sel &= ~X86_SEL_RPL;
2930 if ((pCtxCore->es.Sel & X86_SEL_RPL) == 1)
2931 pCtxCore->es.Sel &= ~X86_SEL_RPL;
2932 if ((pCtxCore->fs.Sel & X86_SEL_RPL) == 1)
2933 pCtxCore->fs.Sel &= ~X86_SEL_RPL;
2934 if ((pCtxCore->gs.Sel & X86_SEL_RPL) == 1)
2935 pCtxCore->gs.Sel &= ~X86_SEL_RPL;
2936# ifdef VBOX_WITH_RAW_RING1
2937 }
2938# endif
2939 }
2940 }
2941
2942 return rc;
2943}
2944
2945#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
2946
2947/**
2948 * Updates the EFLAGS while we're in raw-mode.
2949 *
2950 * @param pVCpu Pointer to the VMCPU.
2951 * @param fEfl The new EFLAGS value.
2952 */
2953VMMDECL(void) CPUMRawSetEFlags(PVMCPU pVCpu, uint32_t fEfl)
2954{
2955#ifdef VBOX_WITH_RAW_MODE_NOT_R0
2956 if (pVCpu->cpum.s.fRawEntered)
2957 PATMRawSetEFlags(pVCpu->CTX_SUFF(pVM), CPUMCTX2CORE(&pVCpu->cpum.s.Guest), fEfl);
2958 else
2959#endif
2960 pVCpu->cpum.s.Guest.eflags.u32 = fEfl;
2961}
2962
2963
2964/**
2965 * Gets the EFLAGS while we're in raw-mode.
2966 *
2967 * @returns The eflags.
2968 * @param pVCpu Pointer to the current virtual CPU.
2969 */
2970VMMDECL(uint32_t) CPUMRawGetEFlags(PVMCPU pVCpu)
2971{
2972#ifdef VBOX_WITH_RAW_MODE_NOT_R0
2973 if (pVCpu->cpum.s.fRawEntered)
2974 return PATMRawGetEFlags(pVCpu->CTX_SUFF(pVM), CPUMCTX2CORE(&pVCpu->cpum.s.Guest));
2975#endif
2976 return pVCpu->cpum.s.Guest.eflags.u32;
2977}
2978
2979
2980/**
2981 * Sets the specified changed flags (CPUM_CHANGED_*).
2982 *
2983 * @param pVCpu Pointer to the current virtual CPU.
2984 */
2985VMMDECL(void) CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedFlags)
2986{
2987 pVCpu->cpum.s.fChanged |= fChangedFlags;
2988}
2989
2990
2991/**
2992 * Checks if the CPU supports the FXSAVE and FXRSTOR instruction.
2993 * @returns true if supported.
2994 * @returns false if not supported.
2995 * @param pVM Pointer to the VM.
2996 */
2997VMMDECL(bool) CPUMSupportsFXSR(PVM pVM)
2998{
2999 return pVM->cpum.s.CPUFeatures.edx.u1FXSR != 0;
3000}
3001
3002
3003/**
3004 * Checks if the host OS uses the SYSENTER / SYSEXIT instructions.
3005 * @returns true if used.
3006 * @returns false if not used.
3007 * @param pVM Pointer to the VM.
3008 */
3009VMMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM)
3010{
3011 return RT_BOOL(pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSENTER);
3012}
3013
3014
3015/**
3016 * Checks if the host OS uses the SYSCALL / SYSRET instructions.
3017 * @returns true if used.
3018 * @returns false if not used.
3019 * @param pVM Pointer to the VM.
3020 */
3021VMMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM)
3022{
3023 return RT_BOOL(pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSCALL);
3024}
3025
3026#ifndef IN_RING3
3027
3028/**
3029 * Lazily sync in the FPU/XMM state.
3030 *
3031 * @returns VBox status code.
3032 * @param pVCpu Pointer to the VMCPU.
3033 */
3034VMMDECL(int) CPUMHandleLazyFPU(PVMCPU pVCpu)
3035{
3036 return cpumHandleLazyFPUAsm(&pVCpu->cpum.s);
3037}
3038
3039#endif /* !IN_RING3 */
3040
3041/**
3042 * Checks if we activated the FPU/XMM state of the guest OS.
3043 * @returns true if we did.
3044 * @returns false if not.
3045 * @param pVCpu Pointer to the VMCPU.
3046 */
3047VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCpu)
3048{
3049 return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU);
3050}
3051
3052
3053/**
3054 * Deactivate the FPU/XMM state of the guest OS.
3055 * @param pVCpu Pointer to the VMCPU.
3056 *
3057 * @todo r=bird: Why is this needed? Looks like a workaround for mishandled
3058 * FPU state management.
3059 */
3060VMMDECL(void) CPUMDeactivateGuestFPUState(PVMCPU pVCpu)
3061{
3062 Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU));
3063 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU;
3064}
3065
3066
3067/**
3068 * Checks if the guest debug state is active.
3069 *
3070 * @returns boolean
3071 * @param pVM Pointer to the VM.
3072 */
3073VMMDECL(bool) CPUMIsGuestDebugStateActive(PVMCPU pVCpu)
3074{
3075 return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST);
3076}
3077
3078/**
3079 * Checks if the hyper debug state is active.
3080 *
3081 * @returns boolean
3082 * @param pVM Pointer to the VM.
3083 */
3084VMMDECL(bool) CPUMIsHyperDebugStateActive(PVMCPU pVCpu)
3085{
3086 return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HYPER);
3087}
3088
3089
3090/**
3091 * Mark the guest's debug state as inactive.
3092 *
3093 * @returns boolean
3094 * @param pVM Pointer to the VM.
3095 * @todo This API doesn't make sense any more.
3096 */
3097VMMDECL(void) CPUMDeactivateGuestDebugState(PVMCPU pVCpu)
3098{
3099 Assert(!(pVCpu->cpum.s.fUseFlags & (CPUM_USED_DEBUG_REGS_GUEST | CPUM_USED_DEBUG_REGS_HYPER | CPUM_USED_DEBUG_REGS_HOST)));
3100}
3101
3102
3103/**
3104 * Get the current privilege level of the guest.
3105 *
3106 * @returns CPL
3107 * @param pVCpu Pointer to the current virtual CPU.
3108 */
3109VMMDECL(uint32_t) CPUMGetGuestCPL(PVMCPU pVCpu)
3110{
3111 /*
3112 * CPL can reliably be found in SS.DPL (hidden regs valid) or SS if not.
3113 *
3114 * Note! We used to check CS.DPL here, assuming it was always equal to
3115 * CPL even if a conforming segment was loaded. But this truned out to
3116 * only apply to older AMD-V. With VT-x we had an ACP2 regression
3117 * during install after a far call to ring 2 with VT-x. Then on newer
3118 * AMD-V CPUs we have to move the VMCB.guest.u8CPL into cs.Attr.n.u2Dpl
3119 * as well as ss.Attr.n.u2Dpl to make this (and other) code work right.
3120 *
3121 * So, forget CS.DPL, always use SS.DPL.
3122 *
3123 * Note! The SS RPL is always equal to the CPL, while the CS RPL
3124 * isn't necessarily equal if the segment is conforming.
3125 * See section 4.11.1 in the AMD manual.
3126 *
3127 * Update: Where the heck does it say CS.RPL can differ from CPL other than
3128 * right after real->prot mode switch and when in V8086 mode? That
3129 * section says the RPL specified in a direct transfere (call, jmp,
3130 * ret) is not the one loaded into CS. Besides, if CS.RPL != CPL
3131 * it would be impossible for an exception handle or the iret
3132 * instruction to figure out whether SS:ESP are part of the frame
3133 * or not. VBox or qemu bug must've lead to this misconception.
3134 *
3135 * Update2: On an AMD bulldozer system here, I've no trouble loading a null
3136 * selector into SS with an RPL other than the CPL when CPL != 3 and
3137 * we're in 64-bit mode. The intel dev box doesn't allow this, on
3138 * RPL = CPL. Weird.
3139 */
3140 uint32_t uCpl;
3141 if (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE)
3142 {
3143 if (!pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
3144 {
3145 if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.s.Guest.ss))
3146 uCpl = pVCpu->cpum.s.Guest.ss.Attr.n.u2Dpl;
3147 else
3148 {
3149 uCpl = (pVCpu->cpum.s.Guest.ss.Sel & X86_SEL_RPL);
3150#ifdef VBOX_WITH_RAW_MODE_NOT_R0
3151# ifdef VBOX_WITH_RAW_RING1
3152 if (pVCpu->cpum.s.fRawEntered)
3153 {
3154 if ( uCpl == 2
3155 && EMIsRawRing1Enabled(pVCpu->CTX_SUFF(pVM)))
3156 uCpl = 1;
3157 else if (uCpl == 1)
3158 uCpl = 0;
3159 }
3160 Assert(uCpl != 2); /* ring 2 support not allowed anymore. */
3161# else
3162 if (uCpl == 1)
3163 uCpl = 0;
3164# endif
3165#endif
3166 }
3167 }
3168 else
3169 uCpl = 3; /* V86 has CPL=3; REM doesn't set DPL=3 in V8086 mode. See @bugref{5130}. */
3170 }
3171 else
3172 uCpl = 0; /* Real mode is zero; CPL set to 3 for VT-x real-mode emulation. */
3173 return uCpl;
3174}
3175
3176
3177/**
3178 * Gets the current guest CPU mode.
3179 *
3180 * If paging mode is what you need, check out PGMGetGuestMode().
3181 *
3182 * @returns The CPU mode.
3183 * @param pVCpu Pointer to the VMCPU.
3184 */
3185VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu)
3186{
3187 CPUMMODE enmMode;
3188 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
3189 enmMode = CPUMMODE_REAL;
3190 else if (!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
3191 enmMode = CPUMMODE_PROTECTED;
3192 else
3193 enmMode = CPUMMODE_LONG;
3194
3195 return enmMode;
3196}
3197
3198
3199/**
3200 * Figure whether the CPU is currently executing 16, 32 or 64 bit code.
3201 *
3202 * @returns 16, 32 or 64.
3203 * @param pVCpu The current virtual CPU.
3204 */
3205VMMDECL(uint32_t) CPUMGetGuestCodeBits(PVMCPU pVCpu)
3206{
3207 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
3208 return 16;
3209
3210 if (pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
3211 {
3212 Assert(!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA));
3213 return 16;
3214 }
3215
3216 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
3217 if ( pVCpu->cpum.s.Guest.cs.Attr.n.u1Long
3218 && (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
3219 return 64;
3220
3221 if (pVCpu->cpum.s.Guest.cs.Attr.n.u1DefBig)
3222 return 32;
3223
3224 return 16;
3225}
3226
3227
3228VMMDECL(DISCPUMODE) CPUMGetGuestDisMode(PVMCPU pVCpu)
3229{
3230 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
3231 return DISCPUMODE_16BIT;
3232
3233 if (pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
3234 {
3235 Assert(!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA));
3236 return DISCPUMODE_16BIT;
3237 }
3238
3239 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
3240 if ( pVCpu->cpum.s.Guest.cs.Attr.n.u1Long
3241 && (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
3242 return DISCPUMODE_64BIT;
3243
3244 if (pVCpu->cpum.s.Guest.cs.Attr.n.u1DefBig)
3245 return DISCPUMODE_32BIT;
3246
3247 return DISCPUMODE_16BIT;
3248}
3249
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