VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp@ 48567

Last change on this file since 48567 was 48567, checked in by vboxsync, 11 years ago

CPUMR0: Avoid EFER writes whenever possible. Don't know which kernels actually set the EFER.FFXSR bit.
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1/* $Id: CPUMAllRegs.cpp 48567 2013-09-19 22:51:40Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor(/Manager) - Getters and Setters.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_CPUM
23#include <VBox/vmm/cpum.h>
24#include <VBox/vmm/patm.h>
25#include <VBox/vmm/dbgf.h>
26#include <VBox/vmm/pdm.h>
27#include <VBox/vmm/pgm.h>
28#include <VBox/vmm/mm.h>
29#include <VBox/vmm/em.h>
30#if defined(VBOX_WITH_RAW_MODE) && !defined(IN_RING0)
31# include <VBox/vmm/selm.h>
32#endif
33#include "CPUMInternal.h"
34#include <VBox/vmm/vm.h>
35#include <VBox/err.h>
36#include <VBox/dis.h>
37#include <VBox/log.h>
38#include <VBox/vmm/hm.h>
39#include <VBox/vmm/tm.h>
40#include <iprt/assert.h>
41#include <iprt/asm.h>
42#include <iprt/asm-amd64-x86.h>
43#ifdef IN_RING3
44#include <iprt/thread.h>
45#endif
46
47/** Disable stack frame pointer generation here. */
48#if defined(_MSC_VER) && !defined(DEBUG)
49# pragma optimize("y", off)
50#endif
51
52
53/*******************************************************************************
54* Defined Constants And Macros *
55*******************************************************************************/
56/**
57 * Converts a CPUMCPU::Guest pointer into a VMCPU pointer.
58 *
59 * @returns Pointer to the Virtual CPU.
60 * @param a_pGuestCtx Pointer to the guest context.
61 */
62#define CPUM_GUEST_CTX_TO_VMCPU(a_pGuestCtx) RT_FROM_MEMBER(a_pGuestCtx, VMCPU, cpum.s.Guest)
63
64/**
65 * Lazily loads the hidden parts of a selector register when using raw-mode.
66 */
67#if defined(VBOX_WITH_RAW_MODE) && !defined(IN_RING0)
68# define CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(a_pVCpu, a_pSReg) \
69 do \
70 { \
71 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(a_pVCpu, a_pSReg)) \
72 cpumGuestLazyLoadHiddenSelectorReg(a_pVCpu, a_pSReg); \
73 } while (0)
74#else
75# define CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(a_pVCpu, a_pSReg) \
76 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(a_pVCpu, a_pSReg));
77#endif
78
79
80
81#ifdef VBOX_WITH_RAW_MODE_NOT_R0
82
83/**
84 * Does the lazy hidden selector register loading.
85 *
86 * @param pVCpu The current Virtual CPU.
87 * @param pSReg The selector register to lazily load hidden parts of.
88 */
89static void cpumGuestLazyLoadHiddenSelectorReg(PVMCPU pVCpu, PCPUMSELREG pSReg)
90{
91 Assert(!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSReg));
92 Assert(!HMIsEnabled(pVCpu->CTX_SUFF(pVM)));
93 Assert((uintptr_t)(pSReg - &pVCpu->cpum.s.Guest.es) < X86_SREG_COUNT);
94
95 if (pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
96 {
97 /* V8086 mode - Tightly controlled environment, no question about the limit or flags. */
98 pSReg->Attr.u = 0;
99 pSReg->Attr.n.u4Type = pSReg == &pVCpu->cpum.s.Guest.cs ? X86_SEL_TYPE_ER_ACC : X86_SEL_TYPE_RW_ACC;
100 pSReg->Attr.n.u1DescType = 1; /* code/data segment */
101 pSReg->Attr.n.u2Dpl = 3;
102 pSReg->Attr.n.u1Present = 1;
103 pSReg->u32Limit = 0x0000ffff;
104 pSReg->u64Base = (uint32_t)pSReg->Sel << 4;
105 pSReg->ValidSel = pSReg->Sel;
106 pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
107 /** @todo Check what the accessed bit should be (VT-x and AMD-V). */
108 }
109 else if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
110 {
111 /* Real mode - leave the limit and flags alone here, at least for now. */
112 pSReg->u64Base = (uint32_t)pSReg->Sel << 4;
113 pSReg->ValidSel = pSReg->Sel;
114 pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
115 }
116 else
117 {
118 /* Protected mode - get it from the selector descriptor tables. */
119 if (!(pSReg->Sel & X86_SEL_MASK_OFF_RPL))
120 {
121 Assert(!CPUMIsGuestInLongMode(pVCpu));
122 pSReg->Sel = 0;
123 pSReg->u64Base = 0;
124 pSReg->u32Limit = 0;
125 pSReg->Attr.u = 0;
126 pSReg->ValidSel = 0;
127 pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
128 /** @todo see todo in iemHlpLoadNullDataSelectorProt. */
129 }
130 else
131 SELMLoadHiddenSelectorReg(pVCpu, &pVCpu->cpum.s.Guest, pSReg);
132 }
133}
134
135
136/**
137 * Makes sure the hidden CS and SS selector registers are valid, loading them if
138 * necessary.
139 *
140 * @param pVCpu The current virtual CPU.
141 */
142VMM_INT_DECL(void) CPUMGuestLazyLoadHiddenCsAndSs(PVMCPU pVCpu)
143{
144 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
145 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.ss);
146}
147
148
149/**
150 * Loads a the hidden parts of a selector register.
151 *
152 * @param pVCpu The current virtual CPU.
153 */
154VMM_INT_DECL(void) CPUMGuestLazyLoadHiddenSelectorReg(PVMCPU pVCpu, PCPUMSELREG pSReg)
155{
156 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, pSReg);
157}
158
159#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
160
161
162/**
163 * Obsolete.
164 *
165 * We don't support nested hypervisor context interrupts or traps. Life is much
166 * simpler when we don't. It's also slightly faster at times.
167 *
168 * @param pVM Handle to the virtual machine.
169 */
170VMMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVMCPU pVCpu)
171{
172 return CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
173}
174
175
176/**
177 * Gets the pointer to the hypervisor CPU context structure of a virtual CPU.
178 *
179 * @param pVCpu Pointer to the VMCPU.
180 */
181VMMDECL(PCPUMCTX) CPUMGetHyperCtxPtr(PVMCPU pVCpu)
182{
183 return &pVCpu->cpum.s.Hyper;
184}
185
186
187VMMDECL(void) CPUMSetHyperGDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
188{
189 pVCpu->cpum.s.Hyper.gdtr.cbGdt = limit;
190 pVCpu->cpum.s.Hyper.gdtr.pGdt = addr;
191}
192
193
194VMMDECL(void) CPUMSetHyperIDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
195{
196 pVCpu->cpum.s.Hyper.idtr.cbIdt = limit;
197 pVCpu->cpum.s.Hyper.idtr.pIdt = addr;
198}
199
200
201VMMDECL(void) CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3)
202{
203 pVCpu->cpum.s.Hyper.cr3 = cr3;
204
205#ifdef IN_RC
206 /* Update the current CR3. */
207 ASMSetCR3(cr3);
208#endif
209}
210
211VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu)
212{
213 return pVCpu->cpum.s.Hyper.cr3;
214}
215
216
217VMMDECL(void) CPUMSetHyperCS(PVMCPU pVCpu, RTSEL SelCS)
218{
219 pVCpu->cpum.s.Hyper.cs.Sel = SelCS;
220}
221
222
223VMMDECL(void) CPUMSetHyperDS(PVMCPU pVCpu, RTSEL SelDS)
224{
225 pVCpu->cpum.s.Hyper.ds.Sel = SelDS;
226}
227
228
229VMMDECL(void) CPUMSetHyperES(PVMCPU pVCpu, RTSEL SelES)
230{
231 pVCpu->cpum.s.Hyper.es.Sel = SelES;
232}
233
234
235VMMDECL(void) CPUMSetHyperFS(PVMCPU pVCpu, RTSEL SelFS)
236{
237 pVCpu->cpum.s.Hyper.fs.Sel = SelFS;
238}
239
240
241VMMDECL(void) CPUMSetHyperGS(PVMCPU pVCpu, RTSEL SelGS)
242{
243 pVCpu->cpum.s.Hyper.gs.Sel = SelGS;
244}
245
246
247VMMDECL(void) CPUMSetHyperSS(PVMCPU pVCpu, RTSEL SelSS)
248{
249 pVCpu->cpum.s.Hyper.ss.Sel = SelSS;
250}
251
252
253VMMDECL(void) CPUMSetHyperESP(PVMCPU pVCpu, uint32_t u32ESP)
254{
255 pVCpu->cpum.s.Hyper.esp = u32ESP;
256}
257
258
259VMMDECL(void) CPUMSetHyperEDX(PVMCPU pVCpu, uint32_t u32ESP)
260{
261 pVCpu->cpum.s.Hyper.esp = u32ESP;
262}
263
264
265VMMDECL(int) CPUMSetHyperEFlags(PVMCPU pVCpu, uint32_t Efl)
266{
267 pVCpu->cpum.s.Hyper.eflags.u32 = Efl;
268 return VINF_SUCCESS;
269}
270
271
272VMMDECL(void) CPUMSetHyperEIP(PVMCPU pVCpu, uint32_t u32EIP)
273{
274 pVCpu->cpum.s.Hyper.eip = u32EIP;
275}
276
277
278/**
279 * Used by VMMR3RawRunGC to reinitialize the general raw-mode context registers,
280 * EFLAGS and EIP prior to resuming guest execution.
281 *
282 * All general register not given as a parameter will be set to 0. The EFLAGS
283 * register will be set to sane values for C/C++ code execution with interrupts
284 * disabled and IOPL 0.
285 *
286 * @param pVCpu The current virtual CPU.
287 * @param u32EIP The EIP value.
288 * @param u32ESP The ESP value.
289 * @param u32EAX The EAX value.
290 * @param u32EDX The EDX value.
291 */
292VMM_INT_DECL(void) CPUMSetHyperState(PVMCPU pVCpu, uint32_t u32EIP, uint32_t u32ESP, uint32_t u32EAX, uint32_t u32EDX)
293{
294 pVCpu->cpum.s.Hyper.eip = u32EIP;
295 pVCpu->cpum.s.Hyper.esp = u32ESP;
296 pVCpu->cpum.s.Hyper.eax = u32EAX;
297 pVCpu->cpum.s.Hyper.edx = u32EDX;
298 pVCpu->cpum.s.Hyper.ecx = 0;
299 pVCpu->cpum.s.Hyper.ebx = 0;
300 pVCpu->cpum.s.Hyper.ebp = 0;
301 pVCpu->cpum.s.Hyper.esi = 0;
302 pVCpu->cpum.s.Hyper.edi = 0;
303 pVCpu->cpum.s.Hyper.eflags.u = X86_EFL_1;
304}
305
306
307VMMDECL(void) CPUMSetHyperTR(PVMCPU pVCpu, RTSEL SelTR)
308{
309 pVCpu->cpum.s.Hyper.tr.Sel = SelTR;
310}
311
312
313VMMDECL(void) CPUMSetHyperLDTR(PVMCPU pVCpu, RTSEL SelLDTR)
314{
315 pVCpu->cpum.s.Hyper.ldtr.Sel = SelLDTR;
316}
317
318
319/** @MAYBE_LOAD_DRx
320 * Macro for updating DRx values in raw-mode and ring-0 contexts.
321 */
322#ifdef IN_RING0
323# if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
324# ifndef VBOX_WITH_HYBRID_32BIT_KERNEL
325# define MAYBE_LOAD_DRx(a_pVCpu, a_fnLoad, a_uValue) \
326 do { \
327 if (!CPUMIsGuestInLongModeEx(&(a_pVCpu)->cpum.s.Guest)) \
328 a_fnLoad(a_uValue); \
329 else \
330 (a_pVCpu)->cpum.s.fUseFlags |= CPUM_SYNC_DEBUG_REGS_HYPER; \
331 } while (0)
332# else
333# define MAYBE_LOAD_DRx(a_pVCpu, a_fnLoad, a_uValue) \
334 do { \
335 /** @todo we're not loading the correct guest value here! */ \
336 a_fnLoad(a_uValue); \
337 } while (0)
338# endif
339# else
340# define MAYBE_LOAD_DRx(a_pVCpu, a_fnLoad, a_uValue) \
341 do { \
342 a_fnLoad(a_uValue); \
343 } while (0)
344# endif
345
346#elif defined(IN_RC)
347# define MAYBE_LOAD_DRx(a_pVCpu, a_fnLoad, a_uValue) \
348 do { \
349 if ((a_pVCpu)->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HYPER) \
350 { a_fnLoad(a_uValue); } \
351 } while (0)
352
353#else
354# define MAYBE_LOAD_DRx(a_pVCpu, a_fnLoad, a_uValue) do { } while (0)
355#endif
356
357VMMDECL(void) CPUMSetHyperDR0(PVMCPU pVCpu, RTGCUINTREG uDr0)
358{
359 pVCpu->cpum.s.Hyper.dr[0] = uDr0;
360 MAYBE_LOAD_DRx(pVCpu, ASMSetDR0, uDr0);
361}
362
363
364VMMDECL(void) CPUMSetHyperDR1(PVMCPU pVCpu, RTGCUINTREG uDr1)
365{
366 pVCpu->cpum.s.Hyper.dr[1] = uDr1;
367 MAYBE_LOAD_DRx(pVCpu, ASMSetDR1, uDr1);
368}
369
370
371VMMDECL(void) CPUMSetHyperDR2(PVMCPU pVCpu, RTGCUINTREG uDr2)
372{
373 pVCpu->cpum.s.Hyper.dr[2] = uDr2;
374 MAYBE_LOAD_DRx(pVCpu, ASMSetDR2, uDr2);
375}
376
377
378VMMDECL(void) CPUMSetHyperDR3(PVMCPU pVCpu, RTGCUINTREG uDr3)
379{
380 pVCpu->cpum.s.Hyper.dr[3] = uDr3;
381 MAYBE_LOAD_DRx(pVCpu, ASMSetDR3, uDr3);
382}
383
384
385VMMDECL(void) CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6)
386{
387 pVCpu->cpum.s.Hyper.dr[6] = uDr6;
388}
389
390
391VMMDECL(void) CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7)
392{
393 pVCpu->cpum.s.Hyper.dr[7] = uDr7;
394#ifdef IN_RC
395 MAYBE_LOAD_DRx(pVCpu, ASMSetDR7, uDr7);
396#endif
397}
398
399
400VMMDECL(RTSEL) CPUMGetHyperCS(PVMCPU pVCpu)
401{
402 return pVCpu->cpum.s.Hyper.cs.Sel;
403}
404
405
406VMMDECL(RTSEL) CPUMGetHyperDS(PVMCPU pVCpu)
407{
408 return pVCpu->cpum.s.Hyper.ds.Sel;
409}
410
411
412VMMDECL(RTSEL) CPUMGetHyperES(PVMCPU pVCpu)
413{
414 return pVCpu->cpum.s.Hyper.es.Sel;
415}
416
417
418VMMDECL(RTSEL) CPUMGetHyperFS(PVMCPU pVCpu)
419{
420 return pVCpu->cpum.s.Hyper.fs.Sel;
421}
422
423
424VMMDECL(RTSEL) CPUMGetHyperGS(PVMCPU pVCpu)
425{
426 return pVCpu->cpum.s.Hyper.gs.Sel;
427}
428
429
430VMMDECL(RTSEL) CPUMGetHyperSS(PVMCPU pVCpu)
431{
432 return pVCpu->cpum.s.Hyper.ss.Sel;
433}
434
435
436VMMDECL(uint32_t) CPUMGetHyperEAX(PVMCPU pVCpu)
437{
438 return pVCpu->cpum.s.Hyper.eax;
439}
440
441
442VMMDECL(uint32_t) CPUMGetHyperEBX(PVMCPU pVCpu)
443{
444 return pVCpu->cpum.s.Hyper.ebx;
445}
446
447
448VMMDECL(uint32_t) CPUMGetHyperECX(PVMCPU pVCpu)
449{
450 return pVCpu->cpum.s.Hyper.ecx;
451}
452
453
454VMMDECL(uint32_t) CPUMGetHyperEDX(PVMCPU pVCpu)
455{
456 return pVCpu->cpum.s.Hyper.edx;
457}
458
459
460VMMDECL(uint32_t) CPUMGetHyperESI(PVMCPU pVCpu)
461{
462 return pVCpu->cpum.s.Hyper.esi;
463}
464
465
466VMMDECL(uint32_t) CPUMGetHyperEDI(PVMCPU pVCpu)
467{
468 return pVCpu->cpum.s.Hyper.edi;
469}
470
471
472VMMDECL(uint32_t) CPUMGetHyperEBP(PVMCPU pVCpu)
473{
474 return pVCpu->cpum.s.Hyper.ebp;
475}
476
477
478VMMDECL(uint32_t) CPUMGetHyperESP(PVMCPU pVCpu)
479{
480 return pVCpu->cpum.s.Hyper.esp;
481}
482
483
484VMMDECL(uint32_t) CPUMGetHyperEFlags(PVMCPU pVCpu)
485{
486 return pVCpu->cpum.s.Hyper.eflags.u32;
487}
488
489
490VMMDECL(uint32_t) CPUMGetHyperEIP(PVMCPU pVCpu)
491{
492 return pVCpu->cpum.s.Hyper.eip;
493}
494
495
496VMMDECL(uint64_t) CPUMGetHyperRIP(PVMCPU pVCpu)
497{
498 return pVCpu->cpum.s.Hyper.rip;
499}
500
501
502VMMDECL(uint32_t) CPUMGetHyperIDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
503{
504 if (pcbLimit)
505 *pcbLimit = pVCpu->cpum.s.Hyper.idtr.cbIdt;
506 return pVCpu->cpum.s.Hyper.idtr.pIdt;
507}
508
509
510VMMDECL(uint32_t) CPUMGetHyperGDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
511{
512 if (pcbLimit)
513 *pcbLimit = pVCpu->cpum.s.Hyper.gdtr.cbGdt;
514 return pVCpu->cpum.s.Hyper.gdtr.pGdt;
515}
516
517
518VMMDECL(RTSEL) CPUMGetHyperLDTR(PVMCPU pVCpu)
519{
520 return pVCpu->cpum.s.Hyper.ldtr.Sel;
521}
522
523
524VMMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVMCPU pVCpu)
525{
526 return pVCpu->cpum.s.Hyper.dr[0];
527}
528
529
530VMMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVMCPU pVCpu)
531{
532 return pVCpu->cpum.s.Hyper.dr[1];
533}
534
535
536VMMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVMCPU pVCpu)
537{
538 return pVCpu->cpum.s.Hyper.dr[2];
539}
540
541
542VMMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVMCPU pVCpu)
543{
544 return pVCpu->cpum.s.Hyper.dr[3];
545}
546
547
548VMMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVMCPU pVCpu)
549{
550 return pVCpu->cpum.s.Hyper.dr[6];
551}
552
553
554VMMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVMCPU pVCpu)
555{
556 return pVCpu->cpum.s.Hyper.dr[7];
557}
558
559
560/**
561 * Gets the pointer to the internal CPUMCTXCORE structure.
562 * This is only for reading in order to save a few calls.
563 *
564 * @param pVCpu Handle to the virtual cpu.
565 */
566VMMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVMCPU pVCpu)
567{
568 return CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
569}
570
571
572/**
573 * Queries the pointer to the internal CPUMCTX structure.
574 *
575 * @returns The CPUMCTX pointer.
576 * @param pVCpu Handle to the virtual cpu.
577 */
578VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu)
579{
580 return &pVCpu->cpum.s.Guest;
581}
582
583VMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit)
584{
585#ifdef VBOX_WITH_IEM
586# ifdef VBOX_WITH_RAW_MODE_NOT_R0
587 if (!HMIsEnabled(pVCpu->CTX_SUFF(pVM)))
588 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
589# endif
590#endif
591 pVCpu->cpum.s.Guest.gdtr.cbGdt = cbLimit;
592 pVCpu->cpum.s.Guest.gdtr.pGdt = GCPtrBase;
593 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GDTR;
594 return VINF_SUCCESS; /* formality, consider it void. */
595}
596
597VMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit)
598{
599#ifdef VBOX_WITH_IEM
600# ifdef VBOX_WITH_RAW_MODE_NOT_R0
601 if (!HMIsEnabled(pVCpu->CTX_SUFF(pVM)))
602 VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
603# endif
604#endif
605 pVCpu->cpum.s.Guest.idtr.cbIdt = cbLimit;
606 pVCpu->cpum.s.Guest.idtr.pIdt = GCPtrBase;
607 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_IDTR;
608 return VINF_SUCCESS; /* formality, consider it void. */
609}
610
611VMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr)
612{
613#ifdef VBOX_WITH_IEM
614# ifdef VBOX_WITH_RAW_MODE_NOT_R0
615 if (!HMIsEnabled(pVCpu->CTX_SUFF(pVM)))
616 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
617# endif
618#endif
619 pVCpu->cpum.s.Guest.tr.Sel = tr;
620 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_TR;
621 return VINF_SUCCESS; /* formality, consider it void. */
622}
623
624VMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr)
625{
626#ifdef VBOX_WITH_IEM
627# ifdef VBOX_WITH_RAW_MODE_NOT_R0
628 if ( ( ldtr != 0
629 || pVCpu->cpum.s.Guest.ldtr.Sel != 0)
630 && !HMIsEnabled(pVCpu->CTX_SUFF(pVM)))
631 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
632# endif
633#endif
634 pVCpu->cpum.s.Guest.ldtr.Sel = ldtr;
635 /* The caller will set more hidden bits if it has them. */
636 pVCpu->cpum.s.Guest.ldtr.ValidSel = 0;
637 pVCpu->cpum.s.Guest.ldtr.fFlags = 0;
638 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_LDTR;
639 return VINF_SUCCESS; /* formality, consider it void. */
640}
641
642
643/**
644 * Set the guest CR0.
645 *
646 * When called in GC, the hyper CR0 may be updated if that is
647 * required. The caller only has to take special action if AM,
648 * WP, PG or PE changes.
649 *
650 * @returns VINF_SUCCESS (consider it void).
651 * @param pVCpu Handle to the virtual cpu.
652 * @param cr0 The new CR0 value.
653 */
654VMMDECL(int) CPUMSetGuestCR0(PVMCPU pVCpu, uint64_t cr0)
655{
656#ifdef IN_RC
657 /*
658 * Check if we need to change hypervisor CR0 because
659 * of math stuff.
660 */
661 if ( (cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP))
662 != (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP)))
663 {
664 if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU))
665 {
666 /*
667 * We haven't saved the host FPU state yet, so TS and MT are both set
668 * and EM should be reflecting the guest EM (it always does this).
669 */
670 if ((cr0 & X86_CR0_EM) != (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM))
671 {
672 uint32_t HyperCR0 = ASMGetCR0();
673 AssertMsg((HyperCR0 & (X86_CR0_TS | X86_CR0_MP)) == (X86_CR0_TS | X86_CR0_MP), ("%#x\n", HyperCR0));
674 AssertMsg((HyperCR0 & X86_CR0_EM) == (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM), ("%#x\n", HyperCR0));
675 HyperCR0 &= ~X86_CR0_EM;
676 HyperCR0 |= cr0 & X86_CR0_EM;
677 Log(("CPUM: New HyperCR0=%#x\n", HyperCR0));
678 ASMSetCR0(HyperCR0);
679 }
680# ifdef VBOX_STRICT
681 else
682 {
683 uint32_t HyperCR0 = ASMGetCR0();
684 AssertMsg((HyperCR0 & (X86_CR0_TS | X86_CR0_MP)) == (X86_CR0_TS | X86_CR0_MP), ("%#x\n", HyperCR0));
685 AssertMsg((HyperCR0 & X86_CR0_EM) == (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM), ("%#x\n", HyperCR0));
686 }
687# endif
688 }
689 else
690 {
691 /*
692 * Already saved the state, so we're just mirroring
693 * the guest flags.
694 */
695 uint32_t HyperCR0 = ASMGetCR0();
696 AssertMsg( (HyperCR0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP))
697 == (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP)),
698 ("%#x %#x\n", HyperCR0, pVCpu->cpum.s.Guest.cr0));
699 HyperCR0 &= ~(X86_CR0_TS | X86_CR0_EM | X86_CR0_MP);
700 HyperCR0 |= cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP);
701 Log(("CPUM: New HyperCR0=%#x\n", HyperCR0));
702 ASMSetCR0(HyperCR0);
703 }
704 }
705#endif /* IN_RC */
706
707 /*
708 * Check for changes causing TLB flushes (for REM).
709 * The caller is responsible for calling PGM when appropriate.
710 */
711 if ( (cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE))
712 != (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)))
713 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
714 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR0;
715
716 /*
717 * Let PGM know if the WP goes from 0 to 1 (netware WP0+RO+US hack)
718 */
719 if (((cr0 ^ pVCpu->cpum.s.Guest.cr0) & X86_CR0_WP) && (cr0 & X86_CR0_WP))
720 PGMCr0WpEnabled(pVCpu);
721
722 pVCpu->cpum.s.Guest.cr0 = cr0 | X86_CR0_ET;
723 return VINF_SUCCESS;
724}
725
726
727VMMDECL(int) CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2)
728{
729 pVCpu->cpum.s.Guest.cr2 = cr2;
730 return VINF_SUCCESS;
731}
732
733
734VMMDECL(int) CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3)
735{
736 pVCpu->cpum.s.Guest.cr3 = cr3;
737 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR3;
738 return VINF_SUCCESS;
739}
740
741
742VMMDECL(int) CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4)
743{
744 if ( (cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE))
745 != (pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE)))
746 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
747 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR4;
748 if (!CPUMSupportsFXSR(pVCpu->CTX_SUFF(pVM)))
749 cr4 &= ~X86_CR4_OSFSXR;
750 pVCpu->cpum.s.Guest.cr4 = cr4;
751 return VINF_SUCCESS;
752}
753
754
755VMMDECL(int) CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags)
756{
757 pVCpu->cpum.s.Guest.eflags.u32 = eflags;
758 return VINF_SUCCESS;
759}
760
761
762VMMDECL(int) CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip)
763{
764 pVCpu->cpum.s.Guest.eip = eip;
765 return VINF_SUCCESS;
766}
767
768
769VMMDECL(int) CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax)
770{
771 pVCpu->cpum.s.Guest.eax = eax;
772 return VINF_SUCCESS;
773}
774
775
776VMMDECL(int) CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx)
777{
778 pVCpu->cpum.s.Guest.ebx = ebx;
779 return VINF_SUCCESS;
780}
781
782
783VMMDECL(int) CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx)
784{
785 pVCpu->cpum.s.Guest.ecx = ecx;
786 return VINF_SUCCESS;
787}
788
789
790VMMDECL(int) CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx)
791{
792 pVCpu->cpum.s.Guest.edx = edx;
793 return VINF_SUCCESS;
794}
795
796
797VMMDECL(int) CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp)
798{
799 pVCpu->cpum.s.Guest.esp = esp;
800 return VINF_SUCCESS;
801}
802
803
804VMMDECL(int) CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp)
805{
806 pVCpu->cpum.s.Guest.ebp = ebp;
807 return VINF_SUCCESS;
808}
809
810
811VMMDECL(int) CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi)
812{
813 pVCpu->cpum.s.Guest.esi = esi;
814 return VINF_SUCCESS;
815}
816
817
818VMMDECL(int) CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi)
819{
820 pVCpu->cpum.s.Guest.edi = edi;
821 return VINF_SUCCESS;
822}
823
824
825VMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss)
826{
827 pVCpu->cpum.s.Guest.ss.Sel = ss;
828 return VINF_SUCCESS;
829}
830
831
832VMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs)
833{
834 pVCpu->cpum.s.Guest.cs.Sel = cs;
835 return VINF_SUCCESS;
836}
837
838
839VMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds)
840{
841 pVCpu->cpum.s.Guest.ds.Sel = ds;
842 return VINF_SUCCESS;
843}
844
845
846VMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es)
847{
848 pVCpu->cpum.s.Guest.es.Sel = es;
849 return VINF_SUCCESS;
850}
851
852
853VMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs)
854{
855 pVCpu->cpum.s.Guest.fs.Sel = fs;
856 return VINF_SUCCESS;
857}
858
859
860VMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs)
861{
862 pVCpu->cpum.s.Guest.gs.Sel = gs;
863 return VINF_SUCCESS;
864}
865
866
867VMMDECL(void) CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val)
868{
869 pVCpu->cpum.s.Guest.msrEFER = val;
870}
871
872
873/**
874 * Worker for CPUMQueryGuestMsr().
875 *
876 * @retval VINF_SUCCESS
877 * @retval VERR_CPUM_RAISE_GP_0
878 * @param pVCpu The cross context CPU structure.
879 * @param idMsr The MSR to read.
880 * @param puValue Where to store the return value.
881 */
882static int cpumQueryGuestMsrInt(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue)
883{
884 /*
885 * If we don't indicate MSR support in the CPUID feature bits, indicate
886 * that a #GP(0) should be raised.
887 */
888 if (!(pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_MSR))
889 {
890 *puValue = 0;
891 return VERR_CPUM_RAISE_GP_0; /** @todo isn't \#UD more correct if not supported? */
892 }
893
894 int rc = VINF_SUCCESS;
895 uint8_t const u8Multiplier = 4;
896 switch (idMsr)
897 {
898 case MSR_IA32_TSC:
899 *puValue = TMCpuTickGet(pVCpu);
900 break;
901
902 case MSR_IA32_APICBASE:
903 {
904 PVM pVM = pVCpu->CTX_SUFF(pVM);
905 if ( ( pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1 /* APIC Std feature */
906 && (pVM->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_APIC))
907 || ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001 /* APIC Ext feature (AMD) */
908 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD
909 && (pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_AMD_FEATURE_EDX_APIC))
910 || ( pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1 /* x2APIC */
911 && (pVM->cpum.s.aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_X2APIC)))
912 {
913 *puValue = pVCpu->cpum.s.Guest.msrApicBase;
914 }
915 else
916 {
917 *puValue = 0;
918 rc = VERR_CPUM_RAISE_GP_0;
919 }
920 break;
921 }
922
923 case MSR_IA32_CR_PAT:
924 *puValue = pVCpu->cpum.s.Guest.msrPAT;
925 break;
926
927 case MSR_IA32_SYSENTER_CS:
928 *puValue = pVCpu->cpum.s.Guest.SysEnter.cs;
929 break;
930
931 case MSR_IA32_SYSENTER_EIP:
932 *puValue = pVCpu->cpum.s.Guest.SysEnter.eip;
933 break;
934
935 case MSR_IA32_SYSENTER_ESP:
936 *puValue = pVCpu->cpum.s.Guest.SysEnter.esp;
937 break;
938
939 case MSR_IA32_MTRR_CAP:
940 {
941 /* This is currently a bit weird. :-) */
942 uint8_t const cVariableRangeRegs = 0;
943 bool const fSystemManagementRangeRegisters = false;
944 bool const fFixedRangeRegisters = false;
945 bool const fWriteCombiningType = false;
946 *puValue = cVariableRangeRegs
947 | (fFixedRangeRegisters ? RT_BIT_64(8) : 0)
948 | (fWriteCombiningType ? RT_BIT_64(10) : 0)
949 | (fSystemManagementRangeRegisters ? RT_BIT_64(11) : 0);
950 break;
951 }
952
953 case IA32_MTRR_PHYSBASE0: case IA32_MTRR_PHYSMASK0:
954 case IA32_MTRR_PHYSBASE1: case IA32_MTRR_PHYSMASK1:
955 case IA32_MTRR_PHYSBASE2: case IA32_MTRR_PHYSMASK2:
956 case IA32_MTRR_PHYSBASE3: case IA32_MTRR_PHYSMASK3:
957 case IA32_MTRR_PHYSBASE4: case IA32_MTRR_PHYSMASK4:
958 case IA32_MTRR_PHYSBASE5: case IA32_MTRR_PHYSMASK5:
959 case IA32_MTRR_PHYSBASE6: case IA32_MTRR_PHYSMASK6:
960 case IA32_MTRR_PHYSBASE7: case IA32_MTRR_PHYSMASK7:
961 /** @todo implement variable MTRRs. */
962 *puValue = 0;
963 break;
964#if 0 /** @todo newer CPUs have more, figure since when and do selective GP(). */
965 case IA32_MTRR_PHYSBASE8: case IA32_MTRR_PHYSMASK8:
966 case IA32_MTRR_PHYSBASE9: case IA32_MTRR_PHYSMASK9:
967 *puValue = 0;
968 break;
969#endif
970
971 case MSR_IA32_MTRR_DEF_TYPE:
972 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType;
973 break;
974
975 case IA32_MTRR_FIX64K_00000:
976 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix64K_00000;
977 break;
978 case IA32_MTRR_FIX16K_80000:
979 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_80000;
980 break;
981 case IA32_MTRR_FIX16K_A0000:
982 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_A0000;
983 break;
984 case IA32_MTRR_FIX4K_C0000:
985 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C0000;
986 break;
987 case IA32_MTRR_FIX4K_C8000:
988 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C8000;
989 break;
990 case IA32_MTRR_FIX4K_D0000:
991 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D0000;
992 break;
993 case IA32_MTRR_FIX4K_D8000:
994 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D8000;
995 break;
996 case IA32_MTRR_FIX4K_E0000:
997 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E0000;
998 break;
999 case IA32_MTRR_FIX4K_E8000:
1000 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E8000;
1001 break;
1002 case IA32_MTRR_FIX4K_F0000:
1003 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F0000;
1004 break;
1005 case IA32_MTRR_FIX4K_F8000:
1006 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F8000;
1007 break;
1008
1009 case MSR_K6_EFER:
1010 *puValue = pVCpu->cpum.s.Guest.msrEFER;
1011 break;
1012
1013 case MSR_K8_SF_MASK:
1014 *puValue = pVCpu->cpum.s.Guest.msrSFMASK;
1015 break;
1016
1017 case MSR_K6_STAR:
1018 *puValue = pVCpu->cpum.s.Guest.msrSTAR;
1019 break;
1020
1021 case MSR_K8_LSTAR:
1022 *puValue = pVCpu->cpum.s.Guest.msrLSTAR;
1023 break;
1024
1025 case MSR_K8_CSTAR:
1026 *puValue = pVCpu->cpum.s.Guest.msrCSTAR;
1027 break;
1028
1029 case MSR_K8_FS_BASE:
1030 *puValue = pVCpu->cpum.s.Guest.fs.u64Base;
1031 break;
1032
1033 case MSR_K8_GS_BASE:
1034 *puValue = pVCpu->cpum.s.Guest.gs.u64Base;
1035 break;
1036
1037 case MSR_K8_KERNEL_GS_BASE:
1038 *puValue = pVCpu->cpum.s.Guest.msrKERNELGSBASE;
1039 break;
1040
1041 case MSR_K8_TSC_AUX:
1042 *puValue = pVCpu->cpum.s.GuestMsrs.msr.TscAux;
1043 break;
1044
1045 case MSR_IA32_PERF_STATUS:
1046 /** @todo could really be not exactly correct, maybe use host's values */
1047 *puValue = UINT64_C(1000) /* TSC increment by tick */
1048 | ((uint64_t)u8Multiplier << 24) /* CPU multiplier (aka bus ratio) min */
1049 | ((uint64_t)u8Multiplier << 40) /* CPU multiplier (aka bus ratio) max */;
1050 break;
1051
1052 case MSR_IA32_FSB_CLOCK_STS:
1053 /*
1054 * Encoded as:
1055 * 0 - 266
1056 * 1 - 133
1057 * 2 - 200
1058 * 3 - return 166
1059 * 5 - return 100
1060 */
1061 *puValue = (2 << 4);
1062 break;
1063
1064 case MSR_IA32_PLATFORM_INFO:
1065 *puValue = (u8Multiplier << 8) /* Flex ratio max */
1066 | ((uint64_t)u8Multiplier << 40) /* Flex ratio min */;
1067 break;
1068
1069 case MSR_IA32_THERM_STATUS:
1070 /* CPU temperature relative to TCC, to actually activate, CPUID leaf 6 EAX[0] must be set */
1071 *puValue = RT_BIT(31) /* validity bit */
1072 | (UINT64_C(20) << 16) /* degrees till TCC */;
1073 break;
1074
1075 case MSR_IA32_MISC_ENABLE:
1076#if 0
1077 /* Needs to be tested more before enabling. */
1078 *puValue = pVCpu->cpum.s.GuestMsr.msr.miscEnable;
1079#else
1080 /* Currenty we don't allow guests to modify enable MSRs. */
1081 *puValue = MSR_IA32_MISC_ENABLE_FAST_STRINGS /* by default */;
1082
1083 if ((pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR) != 0)
1084
1085 *puValue |= MSR_IA32_MISC_ENABLE_MONITOR /* if mwait/monitor available */;
1086 /** @todo: add more cpuid-controlled features this way. */
1087#endif
1088 break;
1089
1090 /** @todo virtualize DEBUGCTL and relatives */
1091 case MSR_IA32_DEBUGCTL:
1092 *puValue = 0;
1093 break;
1094
1095#if 0 /*def IN_RING0 */
1096 case MSR_IA32_PLATFORM_ID:
1097 case MSR_IA32_BIOS_SIGN_ID:
1098 if (CPUMGetCPUVendor(pVM) == CPUMCPUVENDOR_INTEL)
1099 {
1100 /* Available since the P6 family. VT-x implies that this feature is present. */
1101 if (idMsr == MSR_IA32_PLATFORM_ID)
1102 *puValue = ASMRdMsr(MSR_IA32_PLATFORM_ID);
1103 else if (idMsr == MSR_IA32_BIOS_SIGN_ID)
1104 *puValue = ASMRdMsr(MSR_IA32_BIOS_SIGN_ID);
1105 break;
1106 }
1107 /* no break */
1108#endif
1109 /*
1110 * The BIOS_SIGN_ID MSR and MSR_IA32_MCP_CAP et al exist on AMD64 as
1111 * well, at least bulldozer have them. Windows 7 is querying them.
1112 * XP has been observed querying MSR_IA32_MC0_CTL.
1113 */
1114 case MSR_IA32_BIOS_SIGN_ID: /* fam/mod >= 6_01 */
1115 case MSR_IA32_MCG_CAP: /* fam/mod >= 6_01 */
1116 case MSR_IA32_MCG_STATUS: /* indicated as not present in CAP */
1117 /*case MSR_IA32_MCG_CTRL: - indicated as not present in CAP */
1118 case MSR_IA32_MC0_CTL:
1119 case MSR_IA32_MC0_STATUS:
1120 *puValue = 0;
1121 break;
1122
1123
1124 /*
1125 * Intel specifics MSRs:
1126 */
1127 case MSR_P5_MC_ADDR:
1128 case MSR_P5_MC_TYPE:
1129 case MSR_P4_LASTBRANCH_TOS: /** @todo Are these branch regs still here on more recent CPUs? The documentation doesn't mention them for several archs. */
1130 case MSR_P4_LASTBRANCH_0:
1131 case MSR_P4_LASTBRANCH_1:
1132 case MSR_P4_LASTBRANCH_2:
1133 case MSR_P4_LASTBRANCH_3:
1134 case MSR_IA32_PERFEVTSEL0: /* NetWare 6.5 wants the these four. (Bet on AMD as well.) */
1135 case MSR_IA32_PERFEVTSEL1:
1136 case MSR_IA32_PMC0:
1137 case MSR_IA32_PMC1:
1138 case MSR_IA32_PLATFORM_ID: /* fam/mod >= 6_01 */
1139 case MSR_IA32_MPERF: /* intel_pstate depends on this but does a validation test */
1140 case MSR_IA32_APERF: /* intel_pstate depends on this but does a validation test */
1141 /*case MSR_IA32_BIOS_UPDT_TRIG: - write-only? */
1142 case MSR_RAPL_POWER_UNIT:
1143 case MSR_BBL_CR_CTL3: /* ca. core arch? */
1144 case MSR_PKG_CST_CONFIG_CONTROL: /* Nahalem, Sandy Bridge */
1145 *puValue = 0;
1146 if (CPUMGetGuestCpuVendor(pVCpu->CTX_SUFF(pVM)) != CPUMCPUVENDOR_INTEL)
1147 {
1148 Log(("CPUM: MSR %#x is Intel, the virtual CPU isn't an Intel one -> #GP\n", idMsr));
1149 rc = VERR_CPUM_RAISE_GP_0;
1150 break;
1151 }
1152
1153 /* Provide more plausive values for some of them. */
1154 switch (idMsr)
1155 {
1156 case MSR_RAPL_POWER_UNIT:
1157 *puValue = RT_MAKE_U32_FROM_U8(3 /* power units (1/8 W)*/,
1158 16 /* 15.3 micro-Joules */,
1159 10 /* 976 microseconds increments */,
1160 0);
1161 break;
1162 case MSR_BBL_CR_CTL3:
1163 *puValue = RT_MAKE_U32_FROM_U8(1, /* bit 0 - L2 Hardware Enabled. (RO) */
1164 1, /* bit 8 - L2 Enabled (R/W). */
1165 0, /* bit 23 - L2 Not Present (RO). */
1166 0);
1167 break;
1168 case MSR_PKG_CST_CONFIG_CONTROL:
1169 *puValue = pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl;
1170 break;
1171 }
1172 break;
1173
1174#if 0 /* Only on pentium CPUs! */
1175 /* Event counters, not supported. */
1176 case MSR_IA32_CESR:
1177 case MSR_IA32_CTR0:
1178 case MSR_IA32_CTR1:
1179 *puValue = 0;
1180 break;
1181#endif
1182
1183
1184 /*
1185 * AMD specific MSRs:
1186 */
1187 case MSR_K8_SYSCFG:
1188 case MSR_K8_INT_PENDING:
1189 case MSR_K8_NB_CFG: /* (All known values are 0 on reset.) */
1190 case MSR_K8_HWCR: /* Very interesting bits here. :) */
1191 case MSR_K8_VM_CR: /* Windows 8 */
1192 *puValue = 0;
1193 if (CPUMGetGuestCpuVendor(pVCpu->CTX_SUFF(pVM)) != CPUMCPUVENDOR_AMD)
1194 {
1195 Log(("CPUM: MSR %#x is AMD, the virtual CPU isn't an Intel one -> #GP\n", idMsr));
1196 return VERR_CPUM_RAISE_GP_0;
1197 }
1198 /* ignored */
1199 break;
1200
1201 default:
1202 /*
1203 * Hand the X2APIC range to PDM and the APIC.
1204 */
1205 if ( idMsr >= MSR_IA32_X2APIC_START
1206 && idMsr <= MSR_IA32_X2APIC_END)
1207 {
1208 rc = PDMApicReadMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, puValue);
1209 if (RT_SUCCESS(rc))
1210 rc = VINF_SUCCESS;
1211 else
1212 {
1213 *puValue = 0;
1214 rc = VERR_CPUM_RAISE_GP_0;
1215 }
1216 }
1217 else
1218 {
1219 *puValue = 0;
1220 rc = VERR_CPUM_RAISE_GP_0;
1221 }
1222 break;
1223 }
1224
1225 return rc;
1226}
1227
1228
1229/**
1230 * Query an MSR.
1231 *
1232 * The caller is responsible for checking privilege if the call is the result
1233 * of a RDMSR instruction. We'll do the rest.
1234 *
1235 * @retval VINF_SUCCESS on success.
1236 * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR), the caller is
1237 * expected to take the appropriate actions. @a *puValue is set to 0.
1238 * @param pVCpu Pointer to the VMCPU.
1239 * @param idMsr The MSR.
1240 * @param puValue Where to return the value.
1241 *
1242 * @remarks This will always return the right values, even when we're in the
1243 * recompiler.
1244 */
1245VMMDECL(int) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue)
1246{
1247 int rc = cpumQueryGuestMsrInt(pVCpu, idMsr, puValue);
1248 LogFlow(("CPUMQueryGuestMsr: %#x -> %llx rc=%d\n", idMsr, *puValue, rc));
1249 return rc;
1250}
1251
1252
1253/**
1254 * Sets the MSR.
1255 *
1256 * The caller is responsible for checking privilege if the call is the result
1257 * of a WRMSR instruction. We'll do the rest.
1258 *
1259 * @retval VINF_SUCCESS on success.
1260 * @retval VERR_CPUM_RAISE_GP_0 on failure, the caller is expected to take the
1261 * appropriate actions.
1262 *
1263 * @param pVCpu Pointer to the VMCPU.
1264 * @param idMsr The MSR id.
1265 * @param uValue The value to set.
1266 *
1267 * @remarks Everyone changing MSR values, including the recompiler, shall do it
1268 * by calling this method. This makes sure we have current values and
1269 * that we trigger all the right actions when something changes.
1270 */
1271VMMDECL(int) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue)
1272{
1273 LogFlow(("CPUSetGuestMsr: %#x <- %#llx\n", idMsr, uValue));
1274
1275 /*
1276 * If we don't indicate MSR support in the CPUID feature bits, indicate
1277 * that a #GP(0) should be raised.
1278 */
1279 if (!(pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_MSR))
1280 return VERR_CPUM_RAISE_GP_0; /** @todo isn't \#UD more correct if not supported? */
1281
1282 int rc = VINF_SUCCESS;
1283 switch (idMsr)
1284 {
1285 case MSR_IA32_MISC_ENABLE:
1286 pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = uValue;
1287 break;
1288
1289 case MSR_IA32_TSC:
1290 TMCpuTickSet(pVCpu->CTX_SUFF(pVM), pVCpu, uValue);
1291 break;
1292
1293 case MSR_IA32_APICBASE:
1294 rc = PDMApicSetBase(pVCpu, uValue);
1295 if (rc != VINF_SUCCESS)
1296 rc = VERR_CPUM_RAISE_GP_0;
1297 break;
1298
1299 case MSR_IA32_CR_PAT:
1300 pVCpu->cpum.s.Guest.msrPAT = uValue;
1301 break;
1302
1303 case MSR_IA32_SYSENTER_CS:
1304 pVCpu->cpum.s.Guest.SysEnter.cs = uValue & 0xffff; /* 16 bits selector */
1305 break;
1306
1307 case MSR_IA32_SYSENTER_EIP:
1308 pVCpu->cpum.s.Guest.SysEnter.eip = uValue;
1309 break;
1310
1311 case MSR_IA32_SYSENTER_ESP:
1312 pVCpu->cpum.s.Guest.SysEnter.esp = uValue;
1313 break;
1314
1315 case MSR_IA32_MTRR_CAP:
1316 return VERR_CPUM_RAISE_GP_0;
1317
1318 case MSR_IA32_MTRR_DEF_TYPE:
1319 if ( (uValue & UINT64_C(0xfffffffffffff300))
1320 || ( (uValue & 0xff) != 0
1321 && (uValue & 0xff) != 1
1322 && (uValue & 0xff) != 4
1323 && (uValue & 0xff) != 5
1324 && (uValue & 0xff) != 6) )
1325 {
1326 Log(("CPUM: MSR_IA32_MTRR_DEF_TYPE: #GP(0) - writing reserved value (%#llx)\n", uValue));
1327 return VERR_CPUM_RAISE_GP_0;
1328 }
1329 pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType = uValue;
1330 break;
1331
1332 case IA32_MTRR_PHYSBASE0: case IA32_MTRR_PHYSMASK0:
1333 case IA32_MTRR_PHYSBASE1: case IA32_MTRR_PHYSMASK1:
1334 case IA32_MTRR_PHYSBASE2: case IA32_MTRR_PHYSMASK2:
1335 case IA32_MTRR_PHYSBASE3: case IA32_MTRR_PHYSMASK3:
1336 case IA32_MTRR_PHYSBASE4: case IA32_MTRR_PHYSMASK4:
1337 case IA32_MTRR_PHYSBASE5: case IA32_MTRR_PHYSMASK5:
1338 case IA32_MTRR_PHYSBASE6: case IA32_MTRR_PHYSMASK6:
1339 case IA32_MTRR_PHYSBASE7: case IA32_MTRR_PHYSMASK7:
1340 /** @todo implement variable MTRRs. */
1341 break;
1342#if 0 /** @todo newer CPUs have more, figure since when and do selective GP(). */
1343 case IA32_MTRR_PHYSBASE8: case IA32_MTRR_PHYSMASK8:
1344 case IA32_MTRR_PHYSBASE9: case IA32_MTRR_PHYSMASK9:
1345 break;
1346#endif
1347
1348 case IA32_MTRR_FIX64K_00000:
1349 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix64K_00000 = uValue;
1350 break;
1351 case IA32_MTRR_FIX16K_80000:
1352 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_80000 = uValue;
1353 break;
1354 case IA32_MTRR_FIX16K_A0000:
1355 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_A0000 = uValue;
1356 break;
1357 case IA32_MTRR_FIX4K_C0000:
1358 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C0000 = uValue;
1359 break;
1360 case IA32_MTRR_FIX4K_C8000:
1361 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C8000 = uValue;
1362 break;
1363 case IA32_MTRR_FIX4K_D0000:
1364 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D0000 = uValue;
1365 break;
1366 case IA32_MTRR_FIX4K_D8000:
1367 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D8000 = uValue;
1368 break;
1369 case IA32_MTRR_FIX4K_E0000:
1370 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E0000 = uValue;
1371 break;
1372 case IA32_MTRR_FIX4K_E8000:
1373 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E8000 = uValue;
1374 break;
1375 case IA32_MTRR_FIX4K_F0000:
1376 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F0000 = uValue;
1377 break;
1378 case IA32_MTRR_FIX4K_F8000:
1379 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F8000 = uValue;
1380 break;
1381
1382 /*
1383 * AMD64 MSRs.
1384 */
1385 case MSR_K6_EFER:
1386 {
1387 PVM pVM = pVCpu->CTX_SUFF(pVM);
1388 uint64_t const uOldEFER = pVCpu->cpum.s.Guest.msrEFER;
1389 uint32_t const fExtFeatures = pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1390 ? pVM->cpum.s.aGuestCpuIdExt[1].edx
1391 : 0;
1392 uint64_t fMask = 0;
1393
1394 /* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
1395 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_NX)
1396 fMask |= MSR_K6_EFER_NXE;
1397 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
1398 fMask |= MSR_K6_EFER_LME;
1399 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
1400 fMask |= MSR_K6_EFER_SCE;
1401 if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1402 fMask |= MSR_K6_EFER_FFXSR;
1403
1404 /* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if
1405 paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1406 if ( (uOldEFER & MSR_K6_EFER_LME) != (uValue & fMask & MSR_K6_EFER_LME)
1407 && (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG))
1408 {
1409 Log(("CPUM: Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
1410 return VERR_CPUM_RAISE_GP_0;
1411 }
1412
1413 /* There are a few more: e.g. MSR_K6_EFER_LMSLE */
1414 AssertMsg(!(uValue & ~(MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA /* ignored anyway */ | MSR_K6_EFER_SCE | MSR_K6_EFER_FFXSR)),
1415 ("Unexpected value %RX64\n", uValue));
1416 pVCpu->cpum.s.Guest.msrEFER = (uOldEFER & ~fMask) | (uValue & fMask);
1417
1418 /* AMD64 Architecture Programmer's Manual: 15.15 TLB Control; flush the TLB
1419 if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
1420 if ( (uOldEFER & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA))
1421 != (pVCpu->cpum.s.Guest.msrEFER & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA)))
1422 {
1423 /// @todo PGMFlushTLB(pVCpu, cr3, true /*fGlobal*/);
1424 HMFlushTLB(pVCpu);
1425
1426 /* Notify PGM about NXE changes. */
1427 if ( (uOldEFER & MSR_K6_EFER_NXE)
1428 != (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE))
1429 PGMNotifyNxeChanged(pVCpu, !(uOldEFER & MSR_K6_EFER_NXE));
1430 }
1431 break;
1432 }
1433
1434 case MSR_K8_SF_MASK:
1435 pVCpu->cpum.s.Guest.msrSFMASK = uValue;
1436 break;
1437
1438 case MSR_K6_STAR:
1439 pVCpu->cpum.s.Guest.msrSTAR = uValue;
1440 break;
1441
1442 case MSR_K8_LSTAR:
1443 pVCpu->cpum.s.Guest.msrLSTAR = uValue;
1444 break;
1445
1446 case MSR_K8_CSTAR:
1447 pVCpu->cpum.s.Guest.msrCSTAR = uValue;
1448 break;
1449
1450 case MSR_K8_FS_BASE:
1451 pVCpu->cpum.s.Guest.fs.u64Base = uValue;
1452 break;
1453
1454 case MSR_K8_GS_BASE:
1455 pVCpu->cpum.s.Guest.gs.u64Base = uValue;
1456 break;
1457
1458 case MSR_K8_KERNEL_GS_BASE:
1459 pVCpu->cpum.s.Guest.msrKERNELGSBASE = uValue;
1460 break;
1461
1462 case MSR_K8_TSC_AUX:
1463 pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
1464 break;
1465
1466 case MSR_IA32_DEBUGCTL:
1467 /** @todo virtualize DEBUGCTL and relatives */
1468 break;
1469
1470
1471 /*
1472 * Intel specifics MSRs:
1473 */
1474 /*case MSR_IA32_PLATFORM_ID: - read-only */
1475 case MSR_IA32_BIOS_SIGN_ID: /* fam/mod >= 6_01 */
1476 case MSR_IA32_BIOS_UPDT_TRIG: /* fam/mod >= 6_01 */
1477 /*case MSR_IA32_MCP_CAP: - read-only */
1478 /*case MSR_IA32_MCG_STATUS: - read-only */
1479 /*case MSR_IA32_MCG_CTRL: - indicated as not present in CAP */
1480 /*case MSR_IA32_MC0_CTL: - read-only? */
1481 /*case MSR_IA32_MC0_STATUS: - read-only? */
1482 case MSR_PKG_CST_CONFIG_CONTROL:
1483 if (CPUMGetGuestCpuVendor(pVCpu->CTX_SUFF(pVM)) != CPUMCPUVENDOR_INTEL)
1484 {
1485 Log(("CPUM: MSR %#x is Intel, the virtual CPU isn't an Intel one -> #GP\n", idMsr));
1486 return VERR_CPUM_RAISE_GP_0;
1487 }
1488
1489 switch (idMsr)
1490 {
1491 case MSR_PKG_CST_CONFIG_CONTROL:
1492 {
1493 if (pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl & RT_BIT_64(15))
1494 {
1495 Log(("MSR_PKG_CST_CONFIG_CONTROL: Write protected -> #GP\n"));
1496 return VERR_CPUM_RAISE_GP_0;
1497 }
1498 static uint64_t s_fMask = UINT64_C(0x01f08407); /** @todo Only Nehalem has 24; Only Sandy has 27 and 28. */
1499 static uint64_t s_fGpInvalid = UINT64_C(0xffffffff00ff0000); /** @todo figure out exactly what's off limits. */
1500 if ((uValue & s_fGpInvalid) || (uValue & 7) >= 5)
1501 {
1502 Log(("MSR_PKG_CST_CONFIG_CONTROL: Invalid value %#llx -> #GP\n", uValue));
1503 return VERR_CPUM_RAISE_GP_0;
1504 }
1505 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = uValue & s_fMask;
1506 break;
1507 }
1508
1509 }
1510 /* ignored */
1511 break;
1512
1513 /*
1514 * AMD specific MSRs:
1515 */
1516 case MSR_K8_SYSCFG: /** @todo can be written, but we ignore that for now. */
1517 case MSR_K8_INT_PENDING: /** @todo can be written, but we ignore that for now. */
1518 case MSR_K8_NB_CFG: /** @todo can be written; the apicid swapping might be used and would need saving, but probably unnecessary. */
1519 if (CPUMGetGuestCpuVendor(pVCpu->CTX_SUFF(pVM)) != CPUMCPUVENDOR_AMD)
1520 {
1521 Log(("CPUM: MSR %#x is AMD, the virtual CPU isn't an Intel one -> #GP\n", idMsr));
1522 return VERR_CPUM_RAISE_GP_0;
1523 }
1524 /* ignored */
1525 break;
1526
1527
1528 default:
1529 /*
1530 * Hand the X2APIC range to PDM and the APIC.
1531 */
1532 if ( idMsr >= MSR_IA32_X2APIC_START
1533 && idMsr <= MSR_IA32_X2APIC_END)
1534 {
1535 rc = PDMApicWriteMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, uValue);
1536 if (rc != VINF_SUCCESS)
1537 rc = VERR_CPUM_RAISE_GP_0;
1538 }
1539 else
1540 {
1541 /* We should actually trigger a #GP here, but don't as that might cause more trouble. */
1542 /** @todo rc = VERR_CPUM_RAISE_GP_0 */
1543 Log(("CPUMSetGuestMsr: Unknown MSR %#x attempted set to %#llx\n", idMsr, uValue));
1544 }
1545 break;
1546 }
1547 return rc;
1548}
1549
1550
1551VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
1552{
1553 if (pcbLimit)
1554 *pcbLimit = pVCpu->cpum.s.Guest.idtr.cbIdt;
1555 return pVCpu->cpum.s.Guest.idtr.pIdt;
1556}
1557
1558
1559VMMDECL(RTSEL) CPUMGetGuestTR(PVMCPU pVCpu, PCPUMSELREGHID pHidden)
1560{
1561 if (pHidden)
1562 *pHidden = pVCpu->cpum.s.Guest.tr;
1563 return pVCpu->cpum.s.Guest.tr.Sel;
1564}
1565
1566
1567VMMDECL(RTSEL) CPUMGetGuestCS(PVMCPU pVCpu)
1568{
1569 return pVCpu->cpum.s.Guest.cs.Sel;
1570}
1571
1572
1573VMMDECL(RTSEL) CPUMGetGuestDS(PVMCPU pVCpu)
1574{
1575 return pVCpu->cpum.s.Guest.ds.Sel;
1576}
1577
1578
1579VMMDECL(RTSEL) CPUMGetGuestES(PVMCPU pVCpu)
1580{
1581 return pVCpu->cpum.s.Guest.es.Sel;
1582}
1583
1584
1585VMMDECL(RTSEL) CPUMGetGuestFS(PVMCPU pVCpu)
1586{
1587 return pVCpu->cpum.s.Guest.fs.Sel;
1588}
1589
1590
1591VMMDECL(RTSEL) CPUMGetGuestGS(PVMCPU pVCpu)
1592{
1593 return pVCpu->cpum.s.Guest.gs.Sel;
1594}
1595
1596
1597VMMDECL(RTSEL) CPUMGetGuestSS(PVMCPU pVCpu)
1598{
1599 return pVCpu->cpum.s.Guest.ss.Sel;
1600}
1601
1602
1603VMMDECL(RTSEL) CPUMGetGuestLDTR(PVMCPU pVCpu)
1604{
1605 return pVCpu->cpum.s.Guest.ldtr.Sel;
1606}
1607
1608
1609VMMDECL(RTSEL) CPUMGetGuestLdtrEx(PVMCPU pVCpu, uint64_t *pGCPtrBase, uint32_t *pcbLimit)
1610{
1611 *pGCPtrBase = pVCpu->cpum.s.Guest.ldtr.u64Base;
1612 *pcbLimit = pVCpu->cpum.s.Guest.ldtr.u32Limit;
1613 return pVCpu->cpum.s.Guest.ldtr.Sel;
1614}
1615
1616
1617VMMDECL(uint64_t) CPUMGetGuestCR0(PVMCPU pVCpu)
1618{
1619 return pVCpu->cpum.s.Guest.cr0;
1620}
1621
1622
1623VMMDECL(uint64_t) CPUMGetGuestCR2(PVMCPU pVCpu)
1624{
1625 return pVCpu->cpum.s.Guest.cr2;
1626}
1627
1628
1629VMMDECL(uint64_t) CPUMGetGuestCR3(PVMCPU pVCpu)
1630{
1631 return pVCpu->cpum.s.Guest.cr3;
1632}
1633
1634
1635VMMDECL(uint64_t) CPUMGetGuestCR4(PVMCPU pVCpu)
1636{
1637 return pVCpu->cpum.s.Guest.cr4;
1638}
1639
1640
1641VMMDECL(uint64_t) CPUMGetGuestCR8(PVMCPU pVCpu)
1642{
1643 uint64_t u64;
1644 int rc = CPUMGetGuestCRx(pVCpu, DISCREG_CR8, &u64);
1645 if (RT_FAILURE(rc))
1646 u64 = 0;
1647 return u64;
1648}
1649
1650
1651VMMDECL(void) CPUMGetGuestGDTR(PVMCPU pVCpu, PVBOXGDTR pGDTR)
1652{
1653 *pGDTR = pVCpu->cpum.s.Guest.gdtr;
1654}
1655
1656
1657VMMDECL(uint32_t) CPUMGetGuestEIP(PVMCPU pVCpu)
1658{
1659 return pVCpu->cpum.s.Guest.eip;
1660}
1661
1662
1663VMMDECL(uint64_t) CPUMGetGuestRIP(PVMCPU pVCpu)
1664{
1665 return pVCpu->cpum.s.Guest.rip;
1666}
1667
1668
1669VMMDECL(uint32_t) CPUMGetGuestEAX(PVMCPU pVCpu)
1670{
1671 return pVCpu->cpum.s.Guest.eax;
1672}
1673
1674
1675VMMDECL(uint32_t) CPUMGetGuestEBX(PVMCPU pVCpu)
1676{
1677 return pVCpu->cpum.s.Guest.ebx;
1678}
1679
1680
1681VMMDECL(uint32_t) CPUMGetGuestECX(PVMCPU pVCpu)
1682{
1683 return pVCpu->cpum.s.Guest.ecx;
1684}
1685
1686
1687VMMDECL(uint32_t) CPUMGetGuestEDX(PVMCPU pVCpu)
1688{
1689 return pVCpu->cpum.s.Guest.edx;
1690}
1691
1692
1693VMMDECL(uint32_t) CPUMGetGuestESI(PVMCPU pVCpu)
1694{
1695 return pVCpu->cpum.s.Guest.esi;
1696}
1697
1698
1699VMMDECL(uint32_t) CPUMGetGuestEDI(PVMCPU pVCpu)
1700{
1701 return pVCpu->cpum.s.Guest.edi;
1702}
1703
1704
1705VMMDECL(uint32_t) CPUMGetGuestESP(PVMCPU pVCpu)
1706{
1707 return pVCpu->cpum.s.Guest.esp;
1708}
1709
1710
1711VMMDECL(uint32_t) CPUMGetGuestEBP(PVMCPU pVCpu)
1712{
1713 return pVCpu->cpum.s.Guest.ebp;
1714}
1715
1716
1717VMMDECL(uint32_t) CPUMGetGuestEFlags(PVMCPU pVCpu)
1718{
1719 return pVCpu->cpum.s.Guest.eflags.u32;
1720}
1721
1722
1723VMMDECL(int) CPUMGetGuestCRx(PVMCPU pVCpu, unsigned iReg, uint64_t *pValue)
1724{
1725 switch (iReg)
1726 {
1727 case DISCREG_CR0:
1728 *pValue = pVCpu->cpum.s.Guest.cr0;
1729 break;
1730
1731 case DISCREG_CR2:
1732 *pValue = pVCpu->cpum.s.Guest.cr2;
1733 break;
1734
1735 case DISCREG_CR3:
1736 *pValue = pVCpu->cpum.s.Guest.cr3;
1737 break;
1738
1739 case DISCREG_CR4:
1740 *pValue = pVCpu->cpum.s.Guest.cr4;
1741 break;
1742
1743 case DISCREG_CR8:
1744 {
1745 uint8_t u8Tpr;
1746 int rc = PDMApicGetTPR(pVCpu, &u8Tpr, NULL /* pfPending */, NULL /* pu8PendingIrq */);
1747 if (RT_FAILURE(rc))
1748 {
1749 AssertMsg(rc == VERR_PDM_NO_APIC_INSTANCE, ("%Rrc\n", rc));
1750 *pValue = 0;
1751 return rc;
1752 }
1753 *pValue = u8Tpr >> 4; /* bits 7-4 contain the task priority that go in cr8, bits 3-0*/
1754 break;
1755 }
1756
1757 default:
1758 return VERR_INVALID_PARAMETER;
1759 }
1760 return VINF_SUCCESS;
1761}
1762
1763
1764VMMDECL(uint64_t) CPUMGetGuestDR0(PVMCPU pVCpu)
1765{
1766 return pVCpu->cpum.s.Guest.dr[0];
1767}
1768
1769
1770VMMDECL(uint64_t) CPUMGetGuestDR1(PVMCPU pVCpu)
1771{
1772 return pVCpu->cpum.s.Guest.dr[1];
1773}
1774
1775
1776VMMDECL(uint64_t) CPUMGetGuestDR2(PVMCPU pVCpu)
1777{
1778 return pVCpu->cpum.s.Guest.dr[2];
1779}
1780
1781
1782VMMDECL(uint64_t) CPUMGetGuestDR3(PVMCPU pVCpu)
1783{
1784 return pVCpu->cpum.s.Guest.dr[3];
1785}
1786
1787
1788VMMDECL(uint64_t) CPUMGetGuestDR6(PVMCPU pVCpu)
1789{
1790 return pVCpu->cpum.s.Guest.dr[6];
1791}
1792
1793
1794VMMDECL(uint64_t) CPUMGetGuestDR7(PVMCPU pVCpu)
1795{
1796 return pVCpu->cpum.s.Guest.dr[7];
1797}
1798
1799
1800VMMDECL(int) CPUMGetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t *pValue)
1801{
1802 AssertReturn(iReg <= DISDREG_DR7, VERR_INVALID_PARAMETER);
1803 /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
1804 if (iReg == 4 || iReg == 5)
1805 iReg += 2;
1806 *pValue = pVCpu->cpum.s.Guest.dr[iReg];
1807 return VINF_SUCCESS;
1808}
1809
1810
1811VMMDECL(uint64_t) CPUMGetGuestEFER(PVMCPU pVCpu)
1812{
1813 return pVCpu->cpum.s.Guest.msrEFER;
1814}
1815
1816
1817/**
1818 * Gets a CPUID leaf.
1819 *
1820 * @param pVCpu Pointer to the VMCPU.
1821 * @param iLeaf The CPUID leaf to get.
1822 * @param pEax Where to store the EAX value.
1823 * @param pEbx Where to store the EBX value.
1824 * @param pEcx Where to store the ECX value.
1825 * @param pEdx Where to store the EDX value.
1826 */
1827VMMDECL(void) CPUMGetGuestCpuId(PVMCPU pVCpu, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx)
1828{
1829 PVM pVM = pVCpu->CTX_SUFF(pVM);
1830
1831 PCCPUMCPUID pCpuId;
1832 if (iLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
1833 pCpuId = &pVM->cpum.s.aGuestCpuIdStd[iLeaf];
1834 else if (iLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
1835 pCpuId = &pVM->cpum.s.aGuestCpuIdExt[iLeaf - UINT32_C(0x80000000)];
1836 else if ( iLeaf - UINT32_C(0x40000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdHyper)
1837 && (pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_HVP))
1838 pCpuId = &pVM->cpum.s.aGuestCpuIdHyper[iLeaf - UINT32_C(0x40000000)]; /* Only report if HVP bit set. */
1839 else if (iLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
1840 pCpuId = &pVM->cpum.s.aGuestCpuIdCentaur[iLeaf - UINT32_C(0xc0000000)];
1841 else
1842 pCpuId = &pVM->cpum.s.GuestCpuIdDef;
1843
1844 uint32_t cCurrentCacheIndex = *pEcx;
1845
1846 *pEax = pCpuId->eax;
1847 *pEbx = pCpuId->ebx;
1848 *pEcx = pCpuId->ecx;
1849 *pEdx = pCpuId->edx;
1850
1851 if ( iLeaf == 1)
1852 {
1853 /* Bits 31-24: Initial APIC ID */
1854 Assert(pVCpu->idCpu <= 255);
1855 *pEbx |= (pVCpu->idCpu << 24);
1856 }
1857
1858 if ( iLeaf == 4
1859 && cCurrentCacheIndex < 3
1860 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
1861 {
1862 uint32_t type, level, sharing, linesize,
1863 partitions, associativity, sets, cores;
1864
1865 /* For type: 1 - data cache, 2 - i-cache, 3 - unified */
1866 partitions = 1;
1867 /* Those are only to shut up compiler, as they will always
1868 get overwritten, and compiler should be able to figure that out */
1869 sets = associativity = sharing = level = 1;
1870 cores = pVM->cCpus > 32 ? 32 : pVM->cCpus;
1871 switch (cCurrentCacheIndex)
1872 {
1873 case 0:
1874 type = 1;
1875 level = 1;
1876 sharing = 1;
1877 linesize = 64;
1878 associativity = 8;
1879 sets = 64;
1880 break;
1881 case 1:
1882 level = 1;
1883 type = 2;
1884 sharing = 1;
1885 linesize = 64;
1886 associativity = 8;
1887 sets = 64;
1888 break;
1889 default: /* shut up gcc.*/
1890 AssertFailed();
1891 case 2:
1892 level = 2;
1893 type = 3;
1894 sharing = cores; /* our L2 cache is modelled as shared between all cores */
1895 linesize = 64;
1896 associativity = 24;
1897 sets = 4096;
1898 break;
1899 }
1900
1901 *pEax |= ((cores - 1) << 26) |
1902 ((sharing - 1) << 14) |
1903 (level << 5) |
1904 1;
1905 *pEbx = (linesize - 1) |
1906 ((partitions - 1) << 12) |
1907 ((associativity - 1) << 22); /* -1 encoding */
1908 *pEcx = sets - 1;
1909 }
1910
1911 Log2(("CPUMGetGuestCpuId: iLeaf=%#010x %RX32 %RX32 %RX32 %RX32\n", iLeaf, *pEax, *pEbx, *pEcx, *pEdx));
1912}
1913
1914/**
1915 * Gets a number of standard CPUID leafs.
1916 *
1917 * @returns Number of leafs.
1918 * @param pVM Pointer to the VM.
1919 * @remark Intended for PATM.
1920 */
1921VMMDECL(uint32_t) CPUMGetGuestCpuIdStdMax(PVM pVM)
1922{
1923 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd);
1924}
1925
1926
1927/**
1928 * Gets a number of extended CPUID leafs.
1929 *
1930 * @returns Number of leafs.
1931 * @param pVM Pointer to the VM.
1932 * @remark Intended for PATM.
1933 */
1934VMMDECL(uint32_t) CPUMGetGuestCpuIdExtMax(PVM pVM)
1935{
1936 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt);
1937}
1938
1939
1940/**
1941 * Gets a number of centaur CPUID leafs.
1942 *
1943 * @returns Number of leafs.
1944 * @param pVM Pointer to the VM.
1945 * @remark Intended for PATM.
1946 */
1947VMMDECL(uint32_t) CPUMGetGuestCpuIdCentaurMax(PVM pVM)
1948{
1949 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur);
1950}
1951
1952
1953/**
1954 * Sets a CPUID feature bit.
1955 *
1956 * @param pVM Pointer to the VM.
1957 * @param enmFeature The feature to set.
1958 */
1959VMMDECL(void) CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
1960{
1961 switch (enmFeature)
1962 {
1963 /*
1964 * Set the APIC bit in both feature masks.
1965 */
1966 case CPUMCPUIDFEATURE_APIC:
1967 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1968 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_APIC;
1969 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1970 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1971 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_APIC;
1972 LogRel(("CPUM: SetGuestCpuIdFeature: Enabled APIC\n"));
1973 break;
1974
1975 /*
1976 * Set the x2APIC bit in the standard feature mask.
1977 */
1978 case CPUMCPUIDFEATURE_X2APIC:
1979 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1980 pVM->cpum.s.aGuestCpuIdStd[1].ecx |= X86_CPUID_FEATURE_ECX_X2APIC;
1981 LogRel(("CPUM: SetGuestCpuIdFeature: Enabled x2APIC\n"));
1982 break;
1983
1984 /*
1985 * Set the sysenter/sysexit bit in the standard feature mask.
1986 * Assumes the caller knows what it's doing! (host must support these)
1987 */
1988 case CPUMCPUIDFEATURE_SEP:
1989 {
1990 if (!(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_SEP))
1991 {
1992 AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
1993 return;
1994 }
1995
1996 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1997 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_SEP;
1998 LogRel(("CPUM: SetGuestCpuIdFeature: Enabled sysenter/exit\n"));
1999 break;
2000 }
2001
2002 /*
2003 * Set the syscall/sysret bit in the extended feature mask.
2004 * Assumes the caller knows what it's doing! (host must support these)
2005 */
2006 case CPUMCPUIDFEATURE_SYSCALL:
2007 {
2008 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
2009 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_SYSCALL))
2010 {
2011#if HC_ARCH_BITS == 32
2012 /* X86_CPUID_EXT_FEATURE_EDX_SYSCALL not set it seems in 32 bits mode.
2013 * Even when the cpu is capable of doing so in 64 bits mode.
2014 */
2015 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
2016 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
2017 || !(ASMCpuId_EDX(1) & X86_CPUID_EXT_FEATURE_EDX_SYSCALL))
2018#endif
2019 {
2020 LogRel(("CPUM: WARNING! Can't turn on SYSCALL/SYSRET when the host doesn't support it!\n"));
2021 return;
2022 }
2023 }
2024 /* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
2025 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
2026 LogRel(("CPUM: SetGuestCpuIdFeature: Enabled syscall/ret\n"));
2027 break;
2028 }
2029
2030 /*
2031 * Set the PAE bit in both feature masks.
2032 * Assumes the caller knows what it's doing! (host must support these)
2033 */
2034 case CPUMCPUIDFEATURE_PAE:
2035 {
2036 if (!(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_PAE))
2037 {
2038 LogRel(("CPUM: WARNING! Can't turn on PAE when the host doesn't support it!\n"));
2039 return;
2040 }
2041
2042 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2043 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_PAE;
2044 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
2045 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
2046 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_PAE;
2047 LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAE\n"));
2048 break;
2049 }
2050
2051 /*
2052 * Set the LONG MODE bit in the extended feature mask.
2053 * Assumes the caller knows what it's doing! (host must support these)
2054 */
2055 case CPUMCPUIDFEATURE_LONG_MODE:
2056 {
2057 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
2058 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE))
2059 {
2060 LogRel(("CPUM: WARNING! Can't turn on LONG MODE when the host doesn't support it!\n"));
2061 return;
2062 }
2063
2064 /* Valid for both Intel and AMD. */
2065 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
2066 LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LONG MODE\n"));
2067 break;
2068 }
2069
2070 /*
2071 * Set the NX/XD bit in the extended feature mask.
2072 * Assumes the caller knows what it's doing! (host must support these)
2073 */
2074 case CPUMCPUIDFEATURE_NX:
2075 {
2076 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
2077 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_NX))
2078 {
2079 LogRel(("CPUM: WARNING! Can't turn on NX/XD when the host doesn't support it!\n"));
2080 return;
2081 }
2082
2083 /* Valid for both Intel and AMD. */
2084 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_NX;
2085 LogRel(("CPUM: SetGuestCpuIdFeature: Enabled NX\n"));
2086 break;
2087 }
2088
2089 /*
2090 * Set the LAHF/SAHF support in 64-bit mode.
2091 * Assumes the caller knows what it's doing! (host must support this)
2092 */
2093 case CPUMCPUIDFEATURE_LAHF:
2094 {
2095 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
2096 || !(ASMCpuId_ECX(0x80000001) & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF))
2097 {
2098 LogRel(("CPUM: WARNING! Can't turn on LAHF/SAHF when the host doesn't support it!\n"));
2099 return;
2100 }
2101
2102 /* Valid for both Intel and AMD. */
2103 pVM->cpum.s.aGuestCpuIdExt[1].ecx |= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
2104 LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
2105 break;
2106 }
2107
2108 case CPUMCPUIDFEATURE_PAT:
2109 {
2110 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2111 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_PAT;
2112 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
2113 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
2114 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_PAT;
2115 LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAT\n"));
2116 break;
2117 }
2118
2119 /*
2120 * Set the RDTSCP support bit.
2121 * Assumes the caller knows what it's doing! (host must support this)
2122 */
2123 case CPUMCPUIDFEATURE_RDTSCP:
2124 {
2125 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
2126 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
2127 || pVM->cpum.s.u8PortableCpuIdLevel > 0)
2128 {
2129 if (!pVM->cpum.s.u8PortableCpuIdLevel)
2130 LogRel(("CPUM: WARNING! Can't turn on RDTSCP when the host doesn't support it!\n"));
2131 return;
2132 }
2133
2134 /* Valid for both Intel and AMD. */
2135 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
2136 LogRel(("CPUM: SetGuestCpuIdFeature: Enabled RDTSCP.\n"));
2137 break;
2138 }
2139
2140 /*
2141 * Set the Hypervisor Present bit in the standard feature mask.
2142 */
2143 case CPUMCPUIDFEATURE_HVP:
2144 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2145 pVM->cpum.s.aGuestCpuIdStd[1].ecx |= X86_CPUID_FEATURE_ECX_HVP;
2146 LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
2147 break;
2148
2149 default:
2150 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
2151 break;
2152 }
2153 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2154 {
2155 PVMCPU pVCpu = &pVM->aCpus[i];
2156 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CPUID;
2157 }
2158}
2159
2160
2161/**
2162 * Queries a CPUID feature bit.
2163 *
2164 * @returns boolean for feature presence
2165 * @param pVM Pointer to the VM.
2166 * @param enmFeature The feature to query.
2167 */
2168VMMDECL(bool) CPUMGetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
2169{
2170 switch (enmFeature)
2171 {
2172 case CPUMCPUIDFEATURE_PAE:
2173 {
2174 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2175 return !!(pVM->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PAE);
2176 break;
2177 }
2178
2179 case CPUMCPUIDFEATURE_NX:
2180 {
2181 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
2182 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_EXT_FEATURE_EDX_NX);
2183 }
2184
2185 case CPUMCPUIDFEATURE_SYSCALL:
2186 {
2187 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
2188 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
2189 }
2190
2191 case CPUMCPUIDFEATURE_RDTSCP:
2192 {
2193 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
2194 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2195 break;
2196 }
2197
2198 case CPUMCPUIDFEATURE_LONG_MODE:
2199 {
2200 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
2201 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
2202 break;
2203 }
2204
2205 default:
2206 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
2207 break;
2208 }
2209 return false;
2210}
2211
2212
2213/**
2214 * Clears a CPUID feature bit.
2215 *
2216 * @param pVM Pointer to the VM.
2217 * @param enmFeature The feature to clear.
2218 */
2219VMMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
2220{
2221 switch (enmFeature)
2222 {
2223 /*
2224 * Set the APIC bit in both feature masks.
2225 */
2226 case CPUMCPUIDFEATURE_APIC:
2227 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2228 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_APIC;
2229 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
2230 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
2231 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
2232 Log(("CPUM: ClearGuestCpuIdFeature: Disabled APIC\n"));
2233 break;
2234
2235 /*
2236 * Clear the x2APIC bit in the standard feature mask.
2237 */
2238 case CPUMCPUIDFEATURE_X2APIC:
2239 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2240 pVM->cpum.s.aGuestCpuIdStd[1].ecx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
2241 Log(("CPUM: ClearGuestCpuIdFeature: Disabled x2APIC\n"));
2242 break;
2243
2244 case CPUMCPUIDFEATURE_PAE:
2245 {
2246 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2247 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_PAE;
2248 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
2249 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
2250 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
2251 Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAE!\n"));
2252 break;
2253 }
2254
2255 case CPUMCPUIDFEATURE_PAT:
2256 {
2257 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2258 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_PAT;
2259 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
2260 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
2261 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_PAT;
2262 Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAT!\n"));
2263 break;
2264 }
2265
2266 case CPUMCPUIDFEATURE_LONG_MODE:
2267 {
2268 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
2269 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
2270 break;
2271 }
2272
2273 case CPUMCPUIDFEATURE_LAHF:
2274 {
2275 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
2276 pVM->cpum.s.aGuestCpuIdExt[1].ecx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
2277 break;
2278 }
2279
2280 case CPUMCPUIDFEATURE_RDTSCP:
2281 {
2282 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
2283 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
2284 Log(("CPUM: ClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
2285 break;
2286 }
2287
2288 case CPUMCPUIDFEATURE_HVP:
2289 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2290 pVM->cpum.s.aGuestCpuIdStd[1].ecx &= ~X86_CPUID_FEATURE_ECX_HVP;
2291 break;
2292
2293 default:
2294 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
2295 break;
2296 }
2297 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2298 {
2299 PVMCPU pVCpu = &pVM->aCpus[i];
2300 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CPUID;
2301 }
2302}
2303
2304
2305/**
2306 * Gets the host CPU vendor.
2307 *
2308 * @returns CPU vendor.
2309 * @param pVM Pointer to the VM.
2310 */
2311VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM)
2312{
2313 return pVM->cpum.s.enmHostCpuVendor;
2314}
2315
2316
2317/**
2318 * Gets the CPU vendor.
2319 *
2320 * @returns CPU vendor.
2321 * @param pVM Pointer to the VM.
2322 */
2323VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM)
2324{
2325 return pVM->cpum.s.enmGuestCpuVendor;
2326}
2327
2328
2329VMMDECL(int) CPUMSetGuestDR0(PVMCPU pVCpu, uint64_t uDr0)
2330{
2331 pVCpu->cpum.s.Guest.dr[0] = uDr0;
2332 return CPUMRecalcHyperDRx(pVCpu, 0, false);
2333}
2334
2335
2336VMMDECL(int) CPUMSetGuestDR1(PVMCPU pVCpu, uint64_t uDr1)
2337{
2338 pVCpu->cpum.s.Guest.dr[1] = uDr1;
2339 return CPUMRecalcHyperDRx(pVCpu, 1, false);
2340}
2341
2342
2343VMMDECL(int) CPUMSetGuestDR2(PVMCPU pVCpu, uint64_t uDr2)
2344{
2345 pVCpu->cpum.s.Guest.dr[2] = uDr2;
2346 return CPUMRecalcHyperDRx(pVCpu, 2, false);
2347}
2348
2349
2350VMMDECL(int) CPUMSetGuestDR3(PVMCPU pVCpu, uint64_t uDr3)
2351{
2352 pVCpu->cpum.s.Guest.dr[3] = uDr3;
2353 return CPUMRecalcHyperDRx(pVCpu, 3, false);
2354}
2355
2356
2357VMMDECL(int) CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6)
2358{
2359 pVCpu->cpum.s.Guest.dr[6] = uDr6;
2360 return VINF_SUCCESS; /* No need to recalc. */
2361}
2362
2363
2364VMMDECL(int) CPUMSetGuestDR7(PVMCPU pVCpu, uint64_t uDr7)
2365{
2366 pVCpu->cpum.s.Guest.dr[7] = uDr7;
2367 return CPUMRecalcHyperDRx(pVCpu, 7, false);
2368}
2369
2370
2371VMMDECL(int) CPUMSetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t Value)
2372{
2373 AssertReturn(iReg <= DISDREG_DR7, VERR_INVALID_PARAMETER);
2374 /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
2375 if (iReg == 4 || iReg == 5)
2376 iReg += 2;
2377 pVCpu->cpum.s.Guest.dr[iReg] = Value;
2378 return CPUMRecalcHyperDRx(pVCpu, iReg, false);
2379}
2380
2381
2382/**
2383 * Recalculates the hypervisor DRx register values based on current guest
2384 * registers and DBGF breakpoints, updating changed registers depending on the
2385 * context.
2386 *
2387 * This is called whenever a guest DRx register is modified (any context) and
2388 * when DBGF sets a hardware breakpoint (ring-3 only, rendezvous).
2389 *
2390 * In raw-mode context this function will reload any (hyper) DRx registers which
2391 * comes out with a different value. It may also have to save the host debug
2392 * registers if that haven't been done already. In this context though, we'll
2393 * be intercepting and emulating all DRx accesses, so the hypervisor DRx values
2394 * are only important when breakpoints are actually enabled.
2395 *
2396 * In ring-0 (HM) context DR0-3 will be relocated by us, while DR7 will be
2397 * reloaded by the HM code if it changes. Further more, we will only use the
2398 * combined register set when the VBox debugger is actually using hardware BPs,
2399 * when it isn't we'll keep the guest DR0-3 + (maybe) DR6 loaded (DR6 doesn't
2400 * concern us here).
2401 *
2402 * In ring-3 we won't be loading anything, so well calculate hypervisor values
2403 * all the time.
2404 *
2405 * @returns VINF_SUCCESS.
2406 * @param pVCpu Pointer to the VMCPU.
2407 * @param iGstReg The guest debug register number that was modified.
2408 * UINT8_MAX if not guest register.
2409 * @param fForceHyper Used in HM to force hyper registers because of single
2410 * stepping.
2411 */
2412VMMDECL(int) CPUMRecalcHyperDRx(PVMCPU pVCpu, uint8_t iGstReg, bool fForceHyper)
2413{
2414 PVM pVM = pVCpu->CTX_SUFF(pVM);
2415
2416 /*
2417 * Compare the DR7s first.
2418 *
2419 * We only care about the enabled flags. GD is virtualized when we
2420 * dispatch the #DB, we never enable it. The DBGF DR7 value is will
2421 * always have the LE and GE bits set, so no need to check and disable
2422 * stuff if they're cleared like we have to for the guest DR7.
2423 */
2424 RTGCUINTREG uGstDr7 = CPUMGetGuestDR7(pVCpu);
2425 if (!(uGstDr7 & (X86_DR7_LE | X86_DR7_GE)))
2426 uGstDr7 = 0;
2427 else if (!(uGstDr7 & X86_DR7_LE))
2428 uGstDr7 &= ~X86_DR7_LE_ALL;
2429 else if (!(uGstDr7 & X86_DR7_GE))
2430 uGstDr7 &= ~X86_DR7_GE_ALL;
2431
2432 const RTGCUINTREG uDbgfDr7 = DBGFBpGetDR7(pVM);
2433
2434#ifdef IN_RING0
2435 if (!fForceHyper && (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HYPER))
2436 fForceHyper = true;
2437#endif
2438 if (( HMIsEnabled(pVCpu->CTX_SUFF(pVM)) && !fForceHyper ? uDbgfDr7 : (uGstDr7 | uDbgfDr7)) & X86_DR7_ENABLED_MASK)
2439 {
2440 Assert(!CPUMIsGuestDebugStateActive(pVCpu));
2441#ifdef IN_RC
2442 bool const fHmEnabled = false;
2443#elif defined(IN_RING3)
2444 bool const fHmEnabled = HMIsEnabled(pVM);
2445#endif
2446
2447 /*
2448 * Ok, something is enabled. Recalc each of the breakpoints, taking
2449 * the VM debugger ones of the guest ones. In raw-mode context we will
2450 * not allow breakpoints with values inside the hypervisor area.
2451 */
2452 RTGCUINTREG uNewDr7 = X86_DR7_GE | X86_DR7_LE | X86_DR7_RA1_MASK;
2453
2454 /* bp 0 */
2455 RTGCUINTREG uNewDr0;
2456 if (uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0))
2457 {
2458 uNewDr7 |= uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
2459 uNewDr0 = DBGFBpGetDR0(pVM);
2460 }
2461 else if (uGstDr7 & (X86_DR7_L0 | X86_DR7_G0))
2462 {
2463 uNewDr0 = CPUMGetGuestDR0(pVCpu);
2464#ifndef IN_RING0
2465 if (fHmEnabled && MMHyperIsInsideArea(pVM, uNewDr0))
2466 uNewDr0 = 0;
2467 else
2468#endif
2469 uNewDr7 |= uGstDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
2470 }
2471 else
2472 uNewDr0 = 0;
2473
2474 /* bp 1 */
2475 RTGCUINTREG uNewDr1;
2476 if (uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1))
2477 {
2478 uNewDr7 |= uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
2479 uNewDr1 = DBGFBpGetDR1(pVM);
2480 }
2481 else if (uGstDr7 & (X86_DR7_L1 | X86_DR7_G1))
2482 {
2483 uNewDr1 = CPUMGetGuestDR1(pVCpu);
2484#ifndef IN_RING0
2485 if (fHmEnabled && MMHyperIsInsideArea(pVM, uNewDr1))
2486 uNewDr1 = 0;
2487 else
2488#endif
2489 uNewDr7 |= uGstDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
2490 }
2491 else
2492 uNewDr1 = 0;
2493
2494 /* bp 2 */
2495 RTGCUINTREG uNewDr2;
2496 if (uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2))
2497 {
2498 uNewDr7 |= uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
2499 uNewDr2 = DBGFBpGetDR2(pVM);
2500 }
2501 else if (uGstDr7 & (X86_DR7_L2 | X86_DR7_G2))
2502 {
2503 uNewDr2 = CPUMGetGuestDR2(pVCpu);
2504#ifndef IN_RING0
2505 if (fHmEnabled && MMHyperIsInsideArea(pVM, uNewDr2))
2506 uNewDr2 = 0;
2507 else
2508#endif
2509 uNewDr7 |= uGstDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
2510 }
2511 else
2512 uNewDr2 = 0;
2513
2514 /* bp 3 */
2515 RTGCUINTREG uNewDr3;
2516 if (uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3))
2517 {
2518 uNewDr7 |= uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
2519 uNewDr3 = DBGFBpGetDR3(pVM);
2520 }
2521 else if (uGstDr7 & (X86_DR7_L3 | X86_DR7_G3))
2522 {
2523 uNewDr3 = CPUMGetGuestDR3(pVCpu);
2524#ifndef IN_RING0
2525 if (fHmEnabled && MMHyperIsInsideArea(pVM, uNewDr3))
2526 uNewDr3 = 0;
2527 else
2528#endif
2529 uNewDr7 |= uGstDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
2530 }
2531 else
2532 uNewDr3 = 0;
2533
2534 /*
2535 * Apply the updates.
2536 */
2537#ifdef IN_RC
2538 /* Make sure to save host registers first. */
2539 if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HOST))
2540 {
2541 if (!(pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS_HOST))
2542 {
2543 pVCpu->cpum.s.Host.dr6 = ASMGetDR6();
2544 pVCpu->cpum.s.Host.dr7 = ASMGetDR7();
2545 }
2546 pVCpu->cpum.s.Host.dr0 = ASMGetDR0();
2547 pVCpu->cpum.s.Host.dr1 = ASMGetDR1();
2548 pVCpu->cpum.s.Host.dr2 = ASMGetDR2();
2549 pVCpu->cpum.s.Host.dr3 = ASMGetDR3();
2550 pVCpu->cpum.s.fUseFlags |= CPUM_USED_DEBUG_REGS_HOST | CPUM_USE_DEBUG_REGS_HYPER | CPUM_USED_DEBUG_REGS_HYPER;
2551
2552 /* We haven't loaded any hyper DRxes yet, so we'll have to load them all now. */
2553 pVCpu->cpum.s.Hyper.dr[0] = uNewDr0;
2554 ASMSetDR0(uNewDr0);
2555 pVCpu->cpum.s.Hyper.dr[1] = uNewDr1;
2556 ASMSetDR1(uNewDr1);
2557 pVCpu->cpum.s.Hyper.dr[2] = uNewDr2;
2558 ASMSetDR2(uNewDr2);
2559 pVCpu->cpum.s.Hyper.dr[3] = uNewDr3;
2560 ASMSetDR3(uNewDr3);
2561 ASMSetDR6(X86_DR6_INIT_VAL);
2562 pVCpu->cpum.s.Hyper.dr[7] = uNewDr7;
2563 ASMSetDR7(uNewDr7);
2564 }
2565 else
2566#endif
2567 {
2568 pVCpu->cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS_HYPER;
2569 if (uNewDr3 != pVCpu->cpum.s.Hyper.dr[3])
2570 CPUMSetHyperDR3(pVCpu, uNewDr3);
2571 if (uNewDr2 != pVCpu->cpum.s.Hyper.dr[2])
2572 CPUMSetHyperDR2(pVCpu, uNewDr2);
2573 if (uNewDr1 != pVCpu->cpum.s.Hyper.dr[1])
2574 CPUMSetHyperDR1(pVCpu, uNewDr1);
2575 if (uNewDr0 != pVCpu->cpum.s.Hyper.dr[0])
2576 CPUMSetHyperDR0(pVCpu, uNewDr0);
2577 if (uNewDr7 != pVCpu->cpum.s.Hyper.dr[7])
2578 CPUMSetHyperDR7(pVCpu, uNewDr7);
2579 }
2580 }
2581#ifdef IN_RING0
2582 else if (CPUMIsGuestDebugStateActive(pVCpu))
2583 {
2584 /*
2585 * Reload the register that was modified. Normally this won't happen
2586 * as we won't intercept DRx writes when not having the hyper debug
2587 * state loaded, but in case we do for some reason we'll simply deal
2588 * with it.
2589 */
2590 switch (iGstReg)
2591 {
2592 case 0: ASMSetDR0(CPUMGetGuestDR0(pVCpu)); break;
2593 case 1: ASMSetDR1(CPUMGetGuestDR1(pVCpu)); break;
2594 case 2: ASMSetDR2(CPUMGetGuestDR2(pVCpu)); break;
2595 case 3: ASMSetDR3(CPUMGetGuestDR3(pVCpu)); break;
2596 default:
2597 AssertReturn(iGstReg != UINT8_MAX, VERR_INTERNAL_ERROR_3);
2598 }
2599 }
2600#endif
2601 else
2602 {
2603 /*
2604 * No active debug state any more. In raw-mode this means we have to
2605 * make sure DR7 has everything disabled now, if we armed it already.
2606 * In ring-0 we might end up here when just single stepping.
2607 */
2608#if defined(IN_RC) || defined(IN_RING0)
2609 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HYPER)
2610 {
2611# ifdef IN_RC
2612 ASMSetDR7(X86_DR7_INIT_VAL);
2613# endif
2614 if (pVCpu->cpum.s.Hyper.dr[0])
2615 ASMSetDR0(0);
2616 if (pVCpu->cpum.s.Hyper.dr[1])
2617 ASMSetDR1(0);
2618 if (pVCpu->cpum.s.Hyper.dr[2])
2619 ASMSetDR2(0);
2620 if (pVCpu->cpum.s.Hyper.dr[3])
2621 ASMSetDR3(0);
2622 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_DEBUG_REGS_HYPER;
2623 }
2624#endif
2625 pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS_HYPER;
2626
2627 /* Clear all the registers. */
2628 pVCpu->cpum.s.Hyper.dr[7] = X86_DR7_RA1_MASK;
2629 pVCpu->cpum.s.Hyper.dr[3] = 0;
2630 pVCpu->cpum.s.Hyper.dr[2] = 0;
2631 pVCpu->cpum.s.Hyper.dr[1] = 0;
2632 pVCpu->cpum.s.Hyper.dr[0] = 0;
2633
2634 }
2635 Log2(("CPUMRecalcHyperDRx: fUseFlags=%#x %RGr %RGr %RGr %RGr %RGr %RGr\n",
2636 pVCpu->cpum.s.fUseFlags, pVCpu->cpum.s.Hyper.dr[0], pVCpu->cpum.s.Hyper.dr[1],
2637 pVCpu->cpum.s.Hyper.dr[2], pVCpu->cpum.s.Hyper.dr[3], pVCpu->cpum.s.Hyper.dr[6],
2638 pVCpu->cpum.s.Hyper.dr[7]));
2639
2640 return VINF_SUCCESS;
2641}
2642
2643
2644/**
2645 * Tests if the guest has No-Execute Page Protection Enabled (NXE).
2646 *
2647 * @returns true if in real mode, otherwise false.
2648 * @param pVCpu Pointer to the VMCPU.
2649 */
2650VMMDECL(bool) CPUMIsGuestNXEnabled(PVMCPU pVCpu)
2651{
2652 return !!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE);
2653}
2654
2655
2656/**
2657 * Tests if the guest has the Page Size Extension enabled (PSE).
2658 *
2659 * @returns true if in real mode, otherwise false.
2660 * @param pVCpu Pointer to the VMCPU.
2661 */
2662VMMDECL(bool) CPUMIsGuestPageSizeExtEnabled(PVMCPU pVCpu)
2663{
2664 /* PAE or AMD64 implies support for big pages regardless of CR4.PSE */
2665 return !!(pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PSE | X86_CR4_PAE));
2666}
2667
2668
2669/**
2670 * Tests if the guest has the paging enabled (PG).
2671 *
2672 * @returns true if in real mode, otherwise false.
2673 * @param pVCpu Pointer to the VMCPU.
2674 */
2675VMMDECL(bool) CPUMIsGuestPagingEnabled(PVMCPU pVCpu)
2676{
2677 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG);
2678}
2679
2680
2681/**
2682 * Tests if the guest has the paging enabled (PG).
2683 *
2684 * @returns true if in real mode, otherwise false.
2685 * @param pVCpu Pointer to the VMCPU.
2686 */
2687VMMDECL(bool) CPUMIsGuestR0WriteProtEnabled(PVMCPU pVCpu)
2688{
2689 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_WP);
2690}
2691
2692
2693/**
2694 * Tests if the guest is running in real mode or not.
2695 *
2696 * @returns true if in real mode, otherwise false.
2697 * @param pVCpu Pointer to the VMCPU.
2698 */
2699VMMDECL(bool) CPUMIsGuestInRealMode(PVMCPU pVCpu)
2700{
2701 return !(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
2702}
2703
2704
2705/**
2706 * Tests if the guest is running in real or virtual 8086 mode.
2707 *
2708 * @returns @c true if it is, @c false if not.
2709 * @param pVCpu Pointer to the VMCPU.
2710 */
2711VMMDECL(bool) CPUMIsGuestInRealOrV86Mode(PVMCPU pVCpu)
2712{
2713 return !(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE)
2714 || pVCpu->cpum.s.Guest.eflags.Bits.u1VM; /** @todo verify that this cannot be set in long mode. */
2715}
2716
2717
2718/**
2719 * Tests if the guest is running in protected or not.
2720 *
2721 * @returns true if in protected mode, otherwise false.
2722 * @param pVCpu Pointer to the VMCPU.
2723 */
2724VMMDECL(bool) CPUMIsGuestInProtectedMode(PVMCPU pVCpu)
2725{
2726 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
2727}
2728
2729
2730/**
2731 * Tests if the guest is running in paged protected or not.
2732 *
2733 * @returns true if in paged protected mode, otherwise false.
2734 * @param pVCpu Pointer to the VMCPU.
2735 */
2736VMMDECL(bool) CPUMIsGuestInPagedProtectedMode(PVMCPU pVCpu)
2737{
2738 return (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
2739}
2740
2741
2742/**
2743 * Tests if the guest is running in long mode or not.
2744 *
2745 * @returns true if in long mode, otherwise false.
2746 * @param pVCpu Pointer to the VMCPU.
2747 */
2748VMMDECL(bool) CPUMIsGuestInLongMode(PVMCPU pVCpu)
2749{
2750 return (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
2751}
2752
2753
2754/**
2755 * Tests if the guest is running in PAE mode or not.
2756 *
2757 * @returns true if in PAE mode, otherwise false.
2758 * @param pVCpu Pointer to the VMCPU.
2759 */
2760VMMDECL(bool) CPUMIsGuestInPAEMode(PVMCPU pVCpu)
2761{
2762 return (pVCpu->cpum.s.Guest.cr4 & X86_CR4_PAE)
2763 && (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG)
2764 && !(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LME);
2765}
2766
2767
2768/**
2769 * Tests if the guest is running in 64 bits mode or not.
2770 *
2771 * @returns true if in 64 bits protected mode, otherwise false.
2772 * @param pVCpu The current virtual CPU.
2773 */
2774VMMDECL(bool) CPUMIsGuestIn64BitCode(PVMCPU pVCpu)
2775{
2776 if (!CPUMIsGuestInLongMode(pVCpu))
2777 return false;
2778 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
2779 return pVCpu->cpum.s.Guest.cs.Attr.n.u1Long;
2780}
2781
2782
2783/**
2784 * Helper for CPUMIsGuestIn64BitCodeEx that handles lazy resolving of hidden CS
2785 * registers.
2786 *
2787 * @returns true if in 64 bits protected mode, otherwise false.
2788 * @param pCtx Pointer to the current guest CPU context.
2789 */
2790VMM_INT_DECL(bool) CPUMIsGuestIn64BitCodeSlow(PCPUMCTX pCtx)
2791{
2792 return CPUMIsGuestIn64BitCode(CPUM_GUEST_CTX_TO_VMCPU(pCtx));
2793}
2794
2795#ifdef VBOX_WITH_RAW_MODE_NOT_R0
2796
2797/**
2798 *
2799 * @returns @c true if we've entered raw-mode and selectors with RPL=1 are
2800 * really RPL=0, @c false if we've not (RPL=1 really is RPL=1).
2801 * @param pVCpu The current virtual CPU.
2802 */
2803VMM_INT_DECL(bool) CPUMIsGuestInRawMode(PVMCPU pVCpu)
2804{
2805 return pVCpu->cpum.s.fRawEntered;
2806}
2807
2808/**
2809 * Transforms the guest CPU state to raw-ring mode.
2810 *
2811 * This function will change the any of the cs and ss register with DPL=0 to DPL=1.
2812 *
2813 * @returns VBox status. (recompiler failure)
2814 * @param pVCpu Pointer to the VMCPU.
2815 * @param pCtxCore The context core (for trap usage).
2816 * @see @ref pg_raw
2817 */
2818VMM_INT_DECL(int) CPUMRawEnter(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
2819{
2820 PVM pVM = pVCpu->CTX_SUFF(pVM);
2821
2822 Assert(!pVCpu->cpum.s.fRawEntered);
2823 Assert(!pVCpu->cpum.s.fRemEntered);
2824 if (!pCtxCore)
2825 pCtxCore = CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
2826
2827 /*
2828 * Are we in Ring-0?
2829 */
2830 if ( pCtxCore->ss.Sel
2831 && (pCtxCore->ss.Sel & X86_SEL_RPL) == 0
2832 && !pCtxCore->eflags.Bits.u1VM)
2833 {
2834 /*
2835 * Enter execution mode.
2836 */
2837 PATMRawEnter(pVM, pCtxCore);
2838
2839 /*
2840 * Set CPL to Ring-1.
2841 */
2842 pCtxCore->ss.Sel |= 1;
2843 if ( pCtxCore->cs.Sel
2844 && (pCtxCore->cs.Sel & X86_SEL_RPL) == 0)
2845 pCtxCore->cs.Sel |= 1;
2846 }
2847 else
2848 {
2849# ifdef VBOX_WITH_RAW_RING1
2850 if ( EMIsRawRing1Enabled(pVM)
2851 && !pCtxCore->eflags.Bits.u1VM
2852 && (pCtxCore->ss.Sel & X86_SEL_RPL) == 1)
2853 {
2854 /* Set CPL to Ring-2. */
2855 pCtxCore->ss.Sel = (pCtxCore->ss.Sel & ~X86_SEL_RPL) | 2;
2856 if (pCtxCore->cs.Sel && (pCtxCore->cs.Sel & X86_SEL_RPL) == 1)
2857 pCtxCore->cs.Sel = (pCtxCore->cs.Sel & ~X86_SEL_RPL) | 2;
2858 }
2859# else
2860 AssertMsg((pCtxCore->ss.Sel & X86_SEL_RPL) >= 2 || pCtxCore->eflags.Bits.u1VM,
2861 ("ring-1 code not supported\n"));
2862# endif
2863 /*
2864 * PATM takes care of IOPL and IF flags for Ring-3 and Ring-2 code as well.
2865 */
2866 PATMRawEnter(pVM, pCtxCore);
2867 }
2868
2869 /*
2870 * Assert sanity.
2871 */
2872 AssertMsg((pCtxCore->eflags.u32 & X86_EFL_IF), ("X86_EFL_IF is clear\n"));
2873 AssertReleaseMsg(pCtxCore->eflags.Bits.u2IOPL == 0,
2874 ("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss.Sel & X86_SEL_RPL));
2875 Assert((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)) == (X86_CR0_PG | X86_CR0_PE | X86_CR0_WP));
2876
2877 pCtxCore->eflags.u32 |= X86_EFL_IF; /* paranoia */
2878
2879 pVCpu->cpum.s.fRawEntered = true;
2880 return VINF_SUCCESS;
2881}
2882
2883
2884/**
2885 * Transforms the guest CPU state from raw-ring mode to correct values.
2886 *
2887 * This function will change any selector registers with DPL=1 to DPL=0.
2888 *
2889 * @returns Adjusted rc.
2890 * @param pVCpu Pointer to the VMCPU.
2891 * @param rc Raw mode return code
2892 * @param pCtxCore The context core (for trap usage).
2893 * @see @ref pg_raw
2894 */
2895VMM_INT_DECL(int) CPUMRawLeave(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, int rc)
2896{
2897 PVM pVM = pVCpu->CTX_SUFF(pVM);
2898
2899 /*
2900 * Don't leave if we've already left (in RC).
2901 */
2902 Assert(!pVCpu->cpum.s.fRemEntered);
2903 if (!pVCpu->cpum.s.fRawEntered)
2904 return rc;
2905 pVCpu->cpum.s.fRawEntered = false;
2906
2907 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2908 if (!pCtxCore)
2909 pCtxCore = CPUMCTX2CORE(pCtx);
2910 Assert(pCtxCore->eflags.Bits.u1VM || (pCtxCore->ss.Sel & X86_SEL_RPL));
2911 AssertMsg(pCtxCore->eflags.Bits.u1VM || pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss.Sel & X86_SEL_RPL),
2912 ("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss.Sel & X86_SEL_RPL));
2913
2914 /*
2915 * Are we executing in raw ring-1?
2916 */
2917 if ( (pCtxCore->ss.Sel & X86_SEL_RPL) == 1
2918 && !pCtxCore->eflags.Bits.u1VM)
2919 {
2920 /*
2921 * Leave execution mode.
2922 */
2923 PATMRawLeave(pVM, pCtxCore, rc);
2924 /* Not quite sure if this is really required, but shouldn't harm (too much anyways). */
2925 /** @todo See what happens if we remove this. */
2926 if ((pCtxCore->ds.Sel & X86_SEL_RPL) == 1)
2927 pCtxCore->ds.Sel &= ~X86_SEL_RPL;
2928 if ((pCtxCore->es.Sel & X86_SEL_RPL) == 1)
2929 pCtxCore->es.Sel &= ~X86_SEL_RPL;
2930 if ((pCtxCore->fs.Sel & X86_SEL_RPL) == 1)
2931 pCtxCore->fs.Sel &= ~X86_SEL_RPL;
2932 if ((pCtxCore->gs.Sel & X86_SEL_RPL) == 1)
2933 pCtxCore->gs.Sel &= ~X86_SEL_RPL;
2934
2935 /*
2936 * Ring-1 selector => Ring-0.
2937 */
2938 pCtxCore->ss.Sel &= ~X86_SEL_RPL;
2939 if ((pCtxCore->cs.Sel & X86_SEL_RPL) == 1)
2940 pCtxCore->cs.Sel &= ~X86_SEL_RPL;
2941 }
2942 else
2943 {
2944 /*
2945 * PATM is taking care of the IOPL and IF flags for us.
2946 */
2947 PATMRawLeave(pVM, pCtxCore, rc);
2948 if (!pCtxCore->eflags.Bits.u1VM)
2949 {
2950# ifdef VBOX_WITH_RAW_RING1
2951 if ( EMIsRawRing1Enabled(pVM)
2952 && (pCtxCore->ss.Sel & X86_SEL_RPL) == 2)
2953 {
2954 /* Not quite sure if this is really required, but shouldn't harm (too much anyways). */
2955 /** @todo See what happens if we remove this. */
2956 if ((pCtxCore->ds.Sel & X86_SEL_RPL) == 2)
2957 pCtxCore->ds.Sel = (pCtxCore->ds.Sel & ~X86_SEL_RPL) | 1;
2958 if ((pCtxCore->es.Sel & X86_SEL_RPL) == 2)
2959 pCtxCore->es.Sel = (pCtxCore->es.Sel & ~X86_SEL_RPL) | 1;
2960 if ((pCtxCore->fs.Sel & X86_SEL_RPL) == 2)
2961 pCtxCore->fs.Sel = (pCtxCore->fs.Sel & ~X86_SEL_RPL) | 1;
2962 if ((pCtxCore->gs.Sel & X86_SEL_RPL) == 2)
2963 pCtxCore->gs.Sel = (pCtxCore->gs.Sel & ~X86_SEL_RPL) | 1;
2964
2965 /*
2966 * Ring-2 selector => Ring-1.
2967 */
2968 pCtxCore->ss.Sel = (pCtxCore->ss.Sel & ~X86_SEL_RPL) | 1;
2969 if ((pCtxCore->cs.Sel & X86_SEL_RPL) == 2)
2970 pCtxCore->cs.Sel = (pCtxCore->cs.Sel & ~X86_SEL_RPL) | 1;
2971 }
2972 else
2973 {
2974# endif
2975 /** @todo See what happens if we remove this. */
2976 if ((pCtxCore->ds.Sel & X86_SEL_RPL) == 1)
2977 pCtxCore->ds.Sel &= ~X86_SEL_RPL;
2978 if ((pCtxCore->es.Sel & X86_SEL_RPL) == 1)
2979 pCtxCore->es.Sel &= ~X86_SEL_RPL;
2980 if ((pCtxCore->fs.Sel & X86_SEL_RPL) == 1)
2981 pCtxCore->fs.Sel &= ~X86_SEL_RPL;
2982 if ((pCtxCore->gs.Sel & X86_SEL_RPL) == 1)
2983 pCtxCore->gs.Sel &= ~X86_SEL_RPL;
2984# ifdef VBOX_WITH_RAW_RING1
2985 }
2986# endif
2987 }
2988 }
2989
2990 return rc;
2991}
2992
2993#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
2994
2995/**
2996 * Updates the EFLAGS while we're in raw-mode.
2997 *
2998 * @param pVCpu Pointer to the VMCPU.
2999 * @param fEfl The new EFLAGS value.
3000 */
3001VMMDECL(void) CPUMRawSetEFlags(PVMCPU pVCpu, uint32_t fEfl)
3002{
3003#ifdef VBOX_WITH_RAW_MODE_NOT_R0
3004 if (pVCpu->cpum.s.fRawEntered)
3005 PATMRawSetEFlags(pVCpu->CTX_SUFF(pVM), CPUMCTX2CORE(&pVCpu->cpum.s.Guest), fEfl);
3006 else
3007#endif
3008 pVCpu->cpum.s.Guest.eflags.u32 = fEfl;
3009}
3010
3011
3012/**
3013 * Gets the EFLAGS while we're in raw-mode.
3014 *
3015 * @returns The eflags.
3016 * @param pVCpu Pointer to the current virtual CPU.
3017 */
3018VMMDECL(uint32_t) CPUMRawGetEFlags(PVMCPU pVCpu)
3019{
3020#ifdef VBOX_WITH_RAW_MODE_NOT_R0
3021 if (pVCpu->cpum.s.fRawEntered)
3022 return PATMRawGetEFlags(pVCpu->CTX_SUFF(pVM), CPUMCTX2CORE(&pVCpu->cpum.s.Guest));
3023#endif
3024 return pVCpu->cpum.s.Guest.eflags.u32;
3025}
3026
3027
3028/**
3029 * Sets the specified changed flags (CPUM_CHANGED_*).
3030 *
3031 * @param pVCpu Pointer to the current virtual CPU.
3032 */
3033VMMDECL(void) CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedFlags)
3034{
3035 pVCpu->cpum.s.fChanged |= fChangedFlags;
3036}
3037
3038
3039/**
3040 * Checks if the CPU supports the FXSAVE and FXRSTOR instruction.
3041 * @returns true if supported.
3042 * @returns false if not supported.
3043 * @param pVM Pointer to the VM.
3044 */
3045VMMDECL(bool) CPUMSupportsFXSR(PVM pVM)
3046{
3047 return pVM->cpum.s.CPUFeatures.edx.u1FXSR != 0;
3048}
3049
3050
3051/**
3052 * Checks if the host OS uses the SYSENTER / SYSEXIT instructions.
3053 * @returns true if used.
3054 * @returns false if not used.
3055 * @param pVM Pointer to the VM.
3056 */
3057VMMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM)
3058{
3059 return RT_BOOL(pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSENTER);
3060}
3061
3062
3063/**
3064 * Checks if the host OS uses the SYSCALL / SYSRET instructions.
3065 * @returns true if used.
3066 * @returns false if not used.
3067 * @param pVM Pointer to the VM.
3068 */
3069VMMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM)
3070{
3071 return RT_BOOL(pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSCALL);
3072}
3073
3074#ifndef IN_RING3
3075
3076/**
3077 * Lazily sync in the FPU/XMM state.
3078 *
3079 * @returns VBox status code.
3080 * @param pVCpu Pointer to the VMCPU.
3081 */
3082VMMDECL(int) CPUMHandleLazyFPU(PVMCPU pVCpu)
3083{
3084 return cpumHandleLazyFPUAsm(&pVCpu->cpum.s);
3085}
3086
3087#endif /* !IN_RING3 */
3088
3089/**
3090 * Checks if we activated the FPU/XMM state of the guest OS.
3091 * @returns true if we did.
3092 * @returns false if not.
3093 * @param pVCpu Pointer to the VMCPU.
3094 */
3095VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCpu)
3096{
3097 return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU);
3098}
3099
3100
3101/**
3102 * Deactivate the FPU/XMM state of the guest OS.
3103 * @param pVCpu Pointer to the VMCPU.
3104 *
3105 * @todo r=bird: Why is this needed? Looks like a workaround for mishandled
3106 * FPU state management.
3107 */
3108VMMDECL(void) CPUMDeactivateGuestFPUState(PVMCPU pVCpu)
3109{
3110 Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU));
3111 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU;
3112}
3113
3114
3115/**
3116 * Checks if the guest debug state is active.
3117 *
3118 * @returns boolean
3119 * @param pVM Pointer to the VMCPU.
3120 */
3121VMMDECL(bool) CPUMIsGuestDebugStateActive(PVMCPU pVCpu)
3122{
3123 return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST);
3124}
3125
3126
3127/**
3128 * Checks if the guest debug state is to be made active during the world-switch
3129 * (currently only used for the 32->64 switcher case).
3130 *
3131 * @returns boolean
3132 * @param pVM Pointer to the VMCPU.
3133 */
3134VMMDECL(bool) CPUMIsGuestDebugStateActivePending(PVMCPU pVCpu)
3135{
3136 return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_DEBUG_REGS_GUEST);
3137}
3138
3139
3140/**
3141 * Checks if the hyper debug state is active.
3142 *
3143 * @returns boolean
3144 * @param pVM Pointer to the VM.
3145 */
3146VMMDECL(bool) CPUMIsHyperDebugStateActive(PVMCPU pVCpu)
3147{
3148 return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HYPER);
3149}
3150
3151
3152/**
3153 * Checks if the hyper debug state is to be made active during the world-switch
3154 * (currently only used for the 32->64 switcher case).
3155 *
3156 * @returns boolean
3157 * @param pVM Pointer to the VMCPU.
3158 */
3159VMMDECL(bool) CPUMIsHyperDebugStateActivePending(PVMCPU pVCpu)
3160{
3161 return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_DEBUG_REGS_HYPER);
3162}
3163
3164
3165/**
3166 * Mark the guest's debug state as inactive.
3167 *
3168 * @returns boolean
3169 * @param pVM Pointer to the VM.
3170 * @todo This API doesn't make sense any more.
3171 */
3172VMMDECL(void) CPUMDeactivateGuestDebugState(PVMCPU pVCpu)
3173{
3174 Assert(!(pVCpu->cpum.s.fUseFlags & (CPUM_USED_DEBUG_REGS_GUEST | CPUM_USED_DEBUG_REGS_HYPER | CPUM_USED_DEBUG_REGS_HOST)));
3175}
3176
3177
3178/**
3179 * Get the current privilege level of the guest.
3180 *
3181 * @returns CPL
3182 * @param pVCpu Pointer to the current virtual CPU.
3183 */
3184VMMDECL(uint32_t) CPUMGetGuestCPL(PVMCPU pVCpu)
3185{
3186 /*
3187 * CPL can reliably be found in SS.DPL (hidden regs valid) or SS if not.
3188 *
3189 * Note! We used to check CS.DPL here, assuming it was always equal to
3190 * CPL even if a conforming segment was loaded. But this truned out to
3191 * only apply to older AMD-V. With VT-x we had an ACP2 regression
3192 * during install after a far call to ring 2 with VT-x. Then on newer
3193 * AMD-V CPUs we have to move the VMCB.guest.u8CPL into cs.Attr.n.u2Dpl
3194 * as well as ss.Attr.n.u2Dpl to make this (and other) code work right.
3195 *
3196 * So, forget CS.DPL, always use SS.DPL.
3197 *
3198 * Note! The SS RPL is always equal to the CPL, while the CS RPL
3199 * isn't necessarily equal if the segment is conforming.
3200 * See section 4.11.1 in the AMD manual.
3201 *
3202 * Update: Where the heck does it say CS.RPL can differ from CPL other than
3203 * right after real->prot mode switch and when in V8086 mode? That
3204 * section says the RPL specified in a direct transfere (call, jmp,
3205 * ret) is not the one loaded into CS. Besides, if CS.RPL != CPL
3206 * it would be impossible for an exception handle or the iret
3207 * instruction to figure out whether SS:ESP are part of the frame
3208 * or not. VBox or qemu bug must've lead to this misconception.
3209 *
3210 * Update2: On an AMD bulldozer system here, I've no trouble loading a null
3211 * selector into SS with an RPL other than the CPL when CPL != 3 and
3212 * we're in 64-bit mode. The intel dev box doesn't allow this, on
3213 * RPL = CPL. Weird.
3214 */
3215 uint32_t uCpl;
3216 if (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE)
3217 {
3218 if (!pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
3219 {
3220 if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.s.Guest.ss))
3221 uCpl = pVCpu->cpum.s.Guest.ss.Attr.n.u2Dpl;
3222 else
3223 {
3224 uCpl = (pVCpu->cpum.s.Guest.ss.Sel & X86_SEL_RPL);
3225#ifdef VBOX_WITH_RAW_MODE_NOT_R0
3226# ifdef VBOX_WITH_RAW_RING1
3227 if (pVCpu->cpum.s.fRawEntered)
3228 {
3229 if ( uCpl == 2
3230 && EMIsRawRing1Enabled(pVCpu->CTX_SUFF(pVM)))
3231 uCpl = 1;
3232 else if (uCpl == 1)
3233 uCpl = 0;
3234 }
3235 Assert(uCpl != 2); /* ring 2 support not allowed anymore. */
3236# else
3237 if (uCpl == 1)
3238 uCpl = 0;
3239# endif
3240#endif
3241 }
3242 }
3243 else
3244 uCpl = 3; /* V86 has CPL=3; REM doesn't set DPL=3 in V8086 mode. See @bugref{5130}. */
3245 }
3246 else
3247 uCpl = 0; /* Real mode is zero; CPL set to 3 for VT-x real-mode emulation. */
3248 return uCpl;
3249}
3250
3251
3252/**
3253 * Gets the current guest CPU mode.
3254 *
3255 * If paging mode is what you need, check out PGMGetGuestMode().
3256 *
3257 * @returns The CPU mode.
3258 * @param pVCpu Pointer to the VMCPU.
3259 */
3260VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu)
3261{
3262 CPUMMODE enmMode;
3263 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
3264 enmMode = CPUMMODE_REAL;
3265 else if (!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
3266 enmMode = CPUMMODE_PROTECTED;
3267 else
3268 enmMode = CPUMMODE_LONG;
3269
3270 return enmMode;
3271}
3272
3273
3274/**
3275 * Figure whether the CPU is currently executing 16, 32 or 64 bit code.
3276 *
3277 * @returns 16, 32 or 64.
3278 * @param pVCpu The current virtual CPU.
3279 */
3280VMMDECL(uint32_t) CPUMGetGuestCodeBits(PVMCPU pVCpu)
3281{
3282 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
3283 return 16;
3284
3285 if (pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
3286 {
3287 Assert(!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA));
3288 return 16;
3289 }
3290
3291 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
3292 if ( pVCpu->cpum.s.Guest.cs.Attr.n.u1Long
3293 && (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
3294 return 64;
3295
3296 if (pVCpu->cpum.s.Guest.cs.Attr.n.u1DefBig)
3297 return 32;
3298
3299 return 16;
3300}
3301
3302
3303VMMDECL(DISCPUMODE) CPUMGetGuestDisMode(PVMCPU pVCpu)
3304{
3305 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
3306 return DISCPUMODE_16BIT;
3307
3308 if (pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
3309 {
3310 Assert(!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA));
3311 return DISCPUMODE_16BIT;
3312 }
3313
3314 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
3315 if ( pVCpu->cpum.s.Guest.cs.Attr.n.u1Long
3316 && (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
3317 return DISCPUMODE_64BIT;
3318
3319 if (pVCpu->cpum.s.Guest.cs.Attr.n.u1DefBig)
3320 return DISCPUMODE_32BIT;
3321
3322 return DISCPUMODE_16BIT;
3323}
3324
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