VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp@ 4859

Last change on this file since 4859 was 4208, checked in by vboxsync, 17 years ago

CPUMGetGuestMode
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1/* $Id: CPUMAllRegs.cpp 4208 2007-08-17 22:11:20Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor(/Manager) - Gets and Sets.
4 */
5
6/*
7 * Copyright (C) 2006-2007 innotek GmbH
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License as published by the Free Software Foundation,
13 * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14 * distribution. VirtualBox OSE is distributed in the hope that it will
15 * be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_CPUM
23#include <VBox/cpum.h>
24#include <VBox/patm.h>
25#include <VBox/dbgf.h>
26#include <VBox/mm.h>
27#include "CPUMInternal.h"
28#include <VBox/vm.h>
29#include <VBox/err.h>
30#include <VBox/dis.h>
31#include <VBox/log.h>
32#include <iprt/assert.h>
33#include <iprt/asm.h>
34
35
36
37/** Disable stack frame pointer generation here. */
38#if defined(_MSC_VER) && !defined(DEBUG)
39# pragma optimize("y", off)
40#endif
41
42
43/**
44 * Sets or resets an alternative hypervisor context core.
45 *
46 * This is called when we get a hypervisor trap set switch the context
47 * core with the trap frame on the stack. It is called again to reset
48 * back to the default context core when resuming hypervisor execution.
49 *
50 * @param pVM The VM handle.
51 * @param pCtxCore Pointer to the alternative context core or NULL
52 * to go back to the default context core.
53 */
54CPUMDECL(void) CPUMHyperSetCtxCore(PVM pVM, PCPUMCTXCORE pCtxCore)
55{
56 LogFlow(("CPUMHyperSetCtxCore: %p -> %p\n", pVM->cpum.s.CTXSUFF(pHyperCore), pCtxCore));
57 if (!pCtxCore)
58 {
59 pCtxCore = CPUMCTX2CORE(&pVM->cpum.s.Hyper);
60#ifdef IN_GC
61 pVM->cpum.s.pHyperCoreHC = VM_HOST_ADDR(pVM, pCtxCore);
62#else
63 pVM->cpum.s.pHyperCoreGC = VM_GUEST_ADDR(pVM, pCtxCore);
64#endif
65 }
66 else
67 {
68#ifdef IN_GC
69 pVM->cpum.s.pHyperCoreHC = MMHyperGC2HC(pVM, pCtxCore);
70#else
71 pVM->cpum.s.pHyperCoreGC = MMHyperHC2GC(pVM, pCtxCore);
72#endif
73 }
74 pVM->cpum.s.CTXSUFF(pHyperCore) = pCtxCore;
75}
76
77
78/**
79 * Gets the pointer to the internal CPUMCTXCORE structure for the hypervisor.
80 * This is only for reading in order to save a few calls.
81 *
82 * @param pVM Handle to the virtual machine.
83 */
84CPUMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVM pVM)
85{
86 return pVM->cpum.s.CTXSUFF(pHyperCore);
87}
88
89
90/**
91 * Queries the pointer to the internal CPUMCTX structure for the hypervisor.
92 *
93 * @returns VBox status code.
94 * @param pVM Handle to the virtual machine.
95 * @param ppCtx Receives the hyper CPUMCTX pointer when successful.
96 *
97 * @deprecated This will *not* (and has never) given the right picture of the
98 * hypervisor register state. With CPUMHyperSetCtxCore() this is
99 * getting much worse. So, use the individual functions for getting
100 * and esp. setting the hypervisor registers.
101 */
102CPUMDECL(int) CPUMQueryHyperCtxPtr(PVM pVM, PCPUMCTX *ppCtx)
103{
104 *ppCtx = &pVM->cpum.s.Hyper;
105 return VINF_SUCCESS;
106}
107
108CPUMDECL(void) CPUMSetHyperGDTR(PVM pVM, uint32_t addr, uint16_t limit)
109{
110 pVM->cpum.s.Hyper.gdtr.cbGdt = limit;
111 pVM->cpum.s.Hyper.gdtr.pGdt = addr;
112 pVM->cpum.s.Hyper.gdtrPadding = 0;
113 pVM->cpum.s.Hyper.gdtrPadding64 = 0;
114}
115
116CPUMDECL(void) CPUMSetHyperIDTR(PVM pVM, uint32_t addr, uint16_t limit)
117{
118 pVM->cpum.s.Hyper.idtr.cbIdt = limit;
119 pVM->cpum.s.Hyper.idtr.pIdt = addr;
120 pVM->cpum.s.Hyper.idtrPadding = 0;
121 pVM->cpum.s.Hyper.idtrPadding64 = 0;
122}
123
124CPUMDECL(void) CPUMSetHyperCR3(PVM pVM, uint32_t cr3)
125{
126 pVM->cpum.s.Hyper.cr3 = cr3;
127}
128
129CPUMDECL(void) CPUMSetHyperCS(PVM pVM, RTSEL SelCS)
130{
131 pVM->cpum.s.CTXSUFF(pHyperCore)->cs = SelCS;
132}
133
134CPUMDECL(void) CPUMSetHyperDS(PVM pVM, RTSEL SelDS)
135{
136 pVM->cpum.s.CTXSUFF(pHyperCore)->ds = SelDS;
137}
138
139CPUMDECL(void) CPUMSetHyperES(PVM pVM, RTSEL SelES)
140{
141 pVM->cpum.s.CTXSUFF(pHyperCore)->es = SelES;
142}
143
144CPUMDECL(void) CPUMSetHyperFS(PVM pVM, RTSEL SelFS)
145{
146 pVM->cpum.s.CTXSUFF(pHyperCore)->fs = SelFS;
147}
148
149CPUMDECL(void) CPUMSetHyperGS(PVM pVM, RTSEL SelGS)
150{
151 pVM->cpum.s.CTXSUFF(pHyperCore)->gs = SelGS;
152}
153
154CPUMDECL(void) CPUMSetHyperSS(PVM pVM, RTSEL SelSS)
155{
156 pVM->cpum.s.CTXSUFF(pHyperCore)->ss = SelSS;
157}
158
159CPUMDECL(void) CPUMSetHyperESP(PVM pVM, uint32_t u32ESP)
160{
161 pVM->cpum.s.CTXSUFF(pHyperCore)->esp = u32ESP;
162}
163
164CPUMDECL(int) CPUMSetHyperEFlags(PVM pVM, uint32_t Efl)
165{
166 pVM->cpum.s.CTXSUFF(pHyperCore)->eflags.u32 = Efl;
167 return VINF_SUCCESS;
168}
169
170CPUMDECL(void) CPUMSetHyperEIP(PVM pVM, uint32_t u32EIP)
171{
172 pVM->cpum.s.CTXSUFF(pHyperCore)->eip = u32EIP;
173}
174
175CPUMDECL(void) CPUMSetHyperTR(PVM pVM, RTSEL SelTR)
176{
177 pVM->cpum.s.Hyper.tr = SelTR;
178}
179
180CPUMDECL(void) CPUMSetHyperLDTR(PVM pVM, RTSEL SelLDTR)
181{
182 pVM->cpum.s.Hyper.ldtr = SelLDTR;
183}
184
185CPUMDECL(void) CPUMSetHyperDR0(PVM pVM, RTGCUINTREG uDr0)
186{
187 pVM->cpum.s.Hyper.dr0 = uDr0;
188 /** @todo in GC we must load it! */
189}
190
191CPUMDECL(void) CPUMSetHyperDR1(PVM pVM, RTGCUINTREG uDr1)
192{
193 pVM->cpum.s.Hyper.dr1 = uDr1;
194 /** @todo in GC we must load it! */
195}
196
197CPUMDECL(void) CPUMSetHyperDR2(PVM pVM, RTGCUINTREG uDr2)
198{
199 pVM->cpum.s.Hyper.dr2 = uDr2;
200 /** @todo in GC we must load it! */
201}
202
203CPUMDECL(void) CPUMSetHyperDR3(PVM pVM, RTGCUINTREG uDr3)
204{
205 pVM->cpum.s.Hyper.dr3 = uDr3;
206 /** @todo in GC we must load it! */
207}
208
209CPUMDECL(void) CPUMSetHyperDR6(PVM pVM, RTGCUINTREG uDr6)
210{
211 pVM->cpum.s.Hyper.dr6 = uDr6;
212 /** @todo in GC we must load it! */
213}
214
215CPUMDECL(void) CPUMSetHyperDR7(PVM pVM, RTGCUINTREG uDr7)
216{
217 pVM->cpum.s.Hyper.dr7 = uDr7;
218 /** @todo in GC we must load it! */
219}
220
221
222CPUMDECL(RTSEL) CPUMGetHyperCS(PVM pVM)
223{
224 return pVM->cpum.s.CTXSUFF(pHyperCore)->cs;
225}
226
227CPUMDECL(RTSEL) CPUMGetHyperDS(PVM pVM)
228{
229 return pVM->cpum.s.CTXSUFF(pHyperCore)->ds;
230}
231
232CPUMDECL(RTSEL) CPUMGetHyperES(PVM pVM)
233{
234 return pVM->cpum.s.CTXSUFF(pHyperCore)->es;
235}
236
237CPUMDECL(RTSEL) CPUMGetHyperFS(PVM pVM)
238{
239 return pVM->cpum.s.CTXSUFF(pHyperCore)->fs;
240}
241
242CPUMDECL(RTSEL) CPUMGetHyperGS(PVM pVM)
243{
244 return pVM->cpum.s.CTXSUFF(pHyperCore)->gs;
245}
246
247CPUMDECL(RTSEL) CPUMGetHyperSS(PVM pVM)
248{
249 return pVM->cpum.s.CTXSUFF(pHyperCore)->ss;
250}
251
252#if 0 /* these are not correct. */
253
254CPUMDECL(uint32_t) CPUMGetHyperCR0(PVM pVM)
255{
256 return pVM->cpum.s.Hyper.cr0;
257}
258
259CPUMDECL(uint32_t) CPUMGetHyperCR2(PVM pVM)
260{
261 return pVM->cpum.s.Hyper.cr2;
262}
263
264CPUMDECL(uint32_t) CPUMGetHyperCR3(PVM pVM)
265{
266 return pVM->cpum.s.Hyper.cr3;
267}
268
269CPUMDECL(uint32_t) CPUMGetHyperCR4(PVM pVM)
270{
271 return pVM->cpum.s.Hyper.cr4;
272}
273
274#endif /* not correct */
275
276CPUMDECL(uint32_t) CPUMGetHyperEAX(PVM pVM)
277{
278 return pVM->cpum.s.CTXSUFF(pHyperCore)->eax;
279}
280
281CPUMDECL(uint32_t) CPUMGetHyperEBX(PVM pVM)
282{
283 return pVM->cpum.s.CTXSUFF(pHyperCore)->ebx;
284}
285
286CPUMDECL(uint32_t) CPUMGetHyperECX(PVM pVM)
287{
288 return pVM->cpum.s.CTXSUFF(pHyperCore)->ecx;
289}
290
291CPUMDECL(uint32_t) CPUMGetHyperEDX(PVM pVM)
292{
293 return pVM->cpum.s.CTXSUFF(pHyperCore)->edx;
294}
295
296CPUMDECL(uint32_t) CPUMGetHyperESI(PVM pVM)
297{
298 return pVM->cpum.s.CTXSUFF(pHyperCore)->esi;
299}
300
301CPUMDECL(uint32_t) CPUMGetHyperEDI(PVM pVM)
302{
303 return pVM->cpum.s.CTXSUFF(pHyperCore)->edi;
304}
305
306CPUMDECL(uint32_t) CPUMGetHyperEBP(PVM pVM)
307{
308 return pVM->cpum.s.CTXSUFF(pHyperCore)->ebp;
309}
310
311CPUMDECL(uint32_t) CPUMGetHyperESP(PVM pVM)
312{
313 return pVM->cpum.s.CTXSUFF(pHyperCore)->esp;
314}
315
316CPUMDECL(uint32_t) CPUMGetHyperEFlags(PVM pVM)
317{
318 return pVM->cpum.s.CTXSUFF(pHyperCore)->eflags.u32;
319}
320
321CPUMDECL(uint32_t) CPUMGetHyperEIP(PVM pVM)
322{
323 return pVM->cpum.s.CTXSUFF(pHyperCore)->eip;
324}
325
326CPUMDECL(uint32_t) CPUMGetHyperIDTR(PVM pVM, uint16_t *pcbLimit)
327{
328 if (pcbLimit)
329 *pcbLimit = pVM->cpum.s.Hyper.idtr.cbIdt;
330 return pVM->cpum.s.Hyper.idtr.pIdt;
331}
332
333CPUMDECL(uint32_t) CPUMGetHyperGDTR(PVM pVM, uint16_t *pcbLimit)
334{
335 if (pcbLimit)
336 *pcbLimit = pVM->cpum.s.Hyper.gdtr.cbGdt;
337 return pVM->cpum.s.Hyper.gdtr.pGdt;
338}
339
340CPUMDECL(RTSEL) CPUMGetHyperLDTR(PVM pVM)
341{
342 return pVM->cpum.s.Hyper.ldtr;
343}
344
345CPUMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVM pVM)
346{
347 return pVM->cpum.s.Hyper.dr0;
348}
349
350CPUMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVM pVM)
351{
352 return pVM->cpum.s.Hyper.dr1;
353}
354
355CPUMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVM pVM)
356{
357 return pVM->cpum.s.Hyper.dr2;
358}
359
360CPUMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVM pVM)
361{
362 return pVM->cpum.s.Hyper.dr3;
363}
364
365CPUMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVM pVM)
366{
367 return pVM->cpum.s.Hyper.dr6;
368}
369
370CPUMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVM pVM)
371{
372 return pVM->cpum.s.Hyper.dr7;
373}
374
375
376/**
377 * Gets the pointer to the internal CPUMCTXCORE structure.
378 * This is only for reading in order to save a few calls.
379 *
380 * @param pVM Handle to the virtual machine.
381 */
382CPUMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVM pVM)
383{
384 return CPUMCTX2CORE(&pVM->cpum.s.Guest);
385}
386
387
388/**
389 * Sets the guest context core registers.
390 *
391 * @param pVM Handle to the virtual machine.
392 * @param pCtxCore The new context core values.
393 */
394CPUMDECL(void) CPUMSetGuestCtxCore(PVM pVM, PCCPUMCTXCORE pCtxCore)
395{
396 /** @todo #1410 requires selectors to be checked. */
397
398 PCPUMCTXCORE pCtxCoreDst CPUMCTX2CORE(&pVM->cpum.s.Guest);
399 *pCtxCoreDst = *pCtxCore;
400}
401
402
403/**
404 * Queries the pointer to the internal CPUMCTX structure
405 *
406 * @returns VBox status code.
407 * @param pVM Handle to the virtual machine.
408 * @param ppCtx Receives the CPUMCTX pointer when successful.
409 */
410CPUMDECL(int) CPUMQueryGuestCtxPtr(PVM pVM, PCPUMCTX *ppCtx)
411{
412 *ppCtx = &pVM->cpum.s.Guest;
413 return VINF_SUCCESS;
414}
415
416
417CPUMDECL(int) CPUMSetGuestGDTR(PVM pVM, uint32_t addr, uint16_t limit)
418{
419 pVM->cpum.s.Guest.gdtr.cbGdt = limit;
420 pVM->cpum.s.Guest.gdtr.pGdt = addr;
421 pVM->cpum.s.fChanged |= CPUM_CHANGED_GDTR;
422 return VINF_SUCCESS;
423}
424
425CPUMDECL(int) CPUMSetGuestIDTR(PVM pVM, uint32_t addr, uint16_t limit)
426{
427 pVM->cpum.s.Guest.idtr.cbIdt = limit;
428 pVM->cpum.s.Guest.idtr.pIdt = addr;
429 pVM->cpum.s.fChanged |= CPUM_CHANGED_IDTR;
430 return VINF_SUCCESS;
431}
432
433CPUMDECL(int) CPUMSetGuestTR(PVM pVM, uint16_t tr)
434{
435 pVM->cpum.s.Guest.tr = tr;
436 pVM->cpum.s.fChanged |= CPUM_CHANGED_TR;
437 return VINF_SUCCESS;
438}
439
440CPUMDECL(int) CPUMSetGuestLDTR(PVM pVM, uint16_t ldtr)
441{
442 pVM->cpum.s.Guest.ldtr = ldtr;
443 pVM->cpum.s.fChanged |= CPUM_CHANGED_LDTR;
444 return VINF_SUCCESS;
445}
446
447
448CPUMDECL(int) CPUMSetGuestCR0(PVM pVM, uint32_t cr0)
449{
450 if ( (cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE))
451 != (pVM->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)))
452 pVM->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
453 pVM->cpum.s.fChanged |= CPUM_CHANGED_CR0;
454 pVM->cpum.s.Guest.cr0 = cr0 | X86_CR0_ET;
455 return VINF_SUCCESS;
456}
457
458CPUMDECL(int) CPUMSetGuestCR2(PVM pVM, uint32_t cr2)
459{
460 pVM->cpum.s.Guest.cr2 = cr2;
461 return VINF_SUCCESS;
462}
463
464CPUMDECL(int) CPUMSetGuestCR3(PVM pVM, uint32_t cr3)
465{
466 pVM->cpum.s.Guest.cr3 = cr3;
467 pVM->cpum.s.fChanged |= CPUM_CHANGED_CR3;
468 return VINF_SUCCESS;
469}
470
471CPUMDECL(int) CPUMSetGuestCR4(PVM pVM, uint32_t cr4)
472{
473 if ( (cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE))
474 != (pVM->cpum.s.Guest.cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE)))
475 pVM->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
476 pVM->cpum.s.fChanged |= CPUM_CHANGED_CR4;
477 if (!CPUMSupportsFXSR(pVM))
478 cr4 &= ~X86_CR4_OSFSXR;
479 pVM->cpum.s.Guest.cr4 = cr4;
480 return VINF_SUCCESS;
481}
482
483CPUMDECL(int) CPUMSetGuestEFlags(PVM pVM, uint32_t eflags)
484{
485 pVM->cpum.s.Guest.eflags.u32 = eflags;
486 return VINF_SUCCESS;
487}
488
489CPUMDECL(int) CPUMSetGuestEIP(PVM pVM, uint32_t eip)
490{
491 pVM->cpum.s.Guest.eip = eip;
492 return VINF_SUCCESS;
493}
494
495CPUMDECL(int) CPUMSetGuestEAX(PVM pVM, uint32_t eax)
496{
497 pVM->cpum.s.Guest.eax = eax;
498 return VINF_SUCCESS;
499}
500
501CPUMDECL(int) CPUMSetGuestEBX(PVM pVM, uint32_t ebx)
502{
503 pVM->cpum.s.Guest.ebx = ebx;
504 return VINF_SUCCESS;
505}
506
507CPUMDECL(int) CPUMSetGuestECX(PVM pVM, uint32_t ecx)
508{
509 pVM->cpum.s.Guest.ecx = ecx;
510 return VINF_SUCCESS;
511}
512
513CPUMDECL(int) CPUMSetGuestEDX(PVM pVM, uint32_t edx)
514{
515 pVM->cpum.s.Guest.edx = edx;
516 return VINF_SUCCESS;
517}
518
519CPUMDECL(int) CPUMSetGuestESP(PVM pVM, uint32_t esp)
520{
521 pVM->cpum.s.Guest.esp = esp;
522 return VINF_SUCCESS;
523}
524
525CPUMDECL(int) CPUMSetGuestEBP(PVM pVM, uint32_t ebp)
526{
527 pVM->cpum.s.Guest.ebp = ebp;
528 return VINF_SUCCESS;
529}
530
531CPUMDECL(int) CPUMSetGuestESI(PVM pVM, uint32_t esi)
532{
533 pVM->cpum.s.Guest.esi = esi;
534 return VINF_SUCCESS;
535}
536
537CPUMDECL(int) CPUMSetGuestEDI(PVM pVM, uint32_t edi)
538{
539 pVM->cpum.s.Guest.edi = edi;
540 return VINF_SUCCESS;
541}
542
543CPUMDECL(int) CPUMSetGuestSS(PVM pVM, uint16_t ss)
544{
545 pVM->cpum.s.Guest.ss = ss;
546 return VINF_SUCCESS;
547}
548
549CPUMDECL(int) CPUMSetGuestCS(PVM pVM, uint16_t cs)
550{
551 pVM->cpum.s.Guest.cs = cs;
552 return VINF_SUCCESS;
553}
554
555CPUMDECL(int) CPUMSetGuestDS(PVM pVM, uint16_t ds)
556{
557 pVM->cpum.s.Guest.ds = ds;
558 return VINF_SUCCESS;
559}
560
561CPUMDECL(int) CPUMSetGuestES(PVM pVM, uint16_t es)
562{
563 pVM->cpum.s.Guest.es = es;
564 return VINF_SUCCESS;
565}
566
567CPUMDECL(int) CPUMSetGuestFS(PVM pVM, uint16_t fs)
568{
569 pVM->cpum.s.Guest.fs = fs;
570 return VINF_SUCCESS;
571}
572
573CPUMDECL(int) CPUMSetGuestGS(PVM pVM, uint16_t gs)
574{
575 pVM->cpum.s.Guest.gs = gs;
576 return VINF_SUCCESS;
577}
578
579
580CPUMDECL(uint32_t) CPUMGetGuestIDTR(PVM pVM, uint16_t *pcbLimit)
581{
582 if (pcbLimit)
583 *pcbLimit = pVM->cpum.s.Guest.idtr.cbIdt;
584 return pVM->cpum.s.Guest.idtr.pIdt;
585}
586
587CPUMDECL(RTSEL) CPUMGetGuestTR(PVM pVM)
588{
589 return pVM->cpum.s.Guest.tr;
590}
591
592CPUMDECL(RTSEL) CPUMGetGuestCS(PVM pVM)
593{
594 return pVM->cpum.s.Guest.cs;
595}
596
597CPUMDECL(RTSEL) CPUMGetGuestDS(PVM pVM)
598{
599 return pVM->cpum.s.Guest.ds;
600}
601
602CPUMDECL(RTSEL) CPUMGetGuestES(PVM pVM)
603{
604 return pVM->cpum.s.Guest.es;
605}
606
607CPUMDECL(RTSEL) CPUMGetGuestFS(PVM pVM)
608{
609 return pVM->cpum.s.Guest.fs;
610}
611
612CPUMDECL(RTSEL) CPUMGetGuestGS(PVM pVM)
613{
614 return pVM->cpum.s.Guest.gs;
615}
616
617CPUMDECL(RTSEL) CPUMGetGuestSS(PVM pVM)
618{
619 return pVM->cpum.s.Guest.ss;
620}
621
622CPUMDECL(RTSEL) CPUMGetGuestLDTR(PVM pVM)
623{
624 return pVM->cpum.s.Guest.ldtr;
625}
626
627
628CPUMDECL(uint32_t) CPUMGetGuestCR0(PVM pVM)
629{
630 return pVM->cpum.s.Guest.cr0;
631}
632
633CPUMDECL(uint32_t) CPUMGetGuestCR2(PVM pVM)
634{
635 return pVM->cpum.s.Guest.cr2;
636}
637
638CPUMDECL(uint32_t) CPUMGetGuestCR3(PVM pVM)
639{
640 return pVM->cpum.s.Guest.cr3;
641}
642
643CPUMDECL(uint32_t) CPUMGetGuestCR4(PVM pVM)
644{
645 return pVM->cpum.s.Guest.cr4;
646}
647
648CPUMDECL(void) CPUMGetGuestGDTR(PVM pVM, PVBOXGDTR pGDTR)
649{
650 *pGDTR = pVM->cpum.s.Guest.gdtr;
651}
652
653CPUMDECL(uint32_t) CPUMGetGuestEIP(PVM pVM)
654{
655 return pVM->cpum.s.Guest.eip;
656}
657
658CPUMDECL(uint32_t) CPUMGetGuestEAX(PVM pVM)
659{
660 return pVM->cpum.s.Guest.eax;
661}
662
663CPUMDECL(uint32_t) CPUMGetGuestEBX(PVM pVM)
664{
665 return pVM->cpum.s.Guest.ebx;
666}
667
668CPUMDECL(uint32_t) CPUMGetGuestECX(PVM pVM)
669{
670 return pVM->cpum.s.Guest.ecx;
671}
672
673CPUMDECL(uint32_t) CPUMGetGuestEDX(PVM pVM)
674{
675 return pVM->cpum.s.Guest.edx;
676}
677
678CPUMDECL(uint32_t) CPUMGetGuestESI(PVM pVM)
679{
680 return pVM->cpum.s.Guest.esi;
681}
682
683CPUMDECL(uint32_t) CPUMGetGuestEDI(PVM pVM)
684{
685 return pVM->cpum.s.Guest.edi;
686}
687
688CPUMDECL(uint32_t) CPUMGetGuestESP(PVM pVM)
689{
690 return pVM->cpum.s.Guest.esp;
691}
692
693CPUMDECL(uint32_t) CPUMGetGuestEBP(PVM pVM)
694{
695 return pVM->cpum.s.Guest.ebp;
696}
697
698CPUMDECL(uint32_t) CPUMGetGuestEFlags(PVM pVM)
699{
700 return pVM->cpum.s.Guest.eflags.u32;
701}
702
703CPUMDECL(CPUMSELREGHID *) CPUMGetGuestTRHid(PVM pVM)
704{
705 return &pVM->cpum.s.Guest.trHid;
706}
707
708//@todo: crx should be an array
709CPUMDECL(int) CPUMGetGuestCRx(PVM pVM, uint32_t iReg, uint32_t *pValue)
710{
711 switch (iReg)
712 {
713 case USE_REG_CR0:
714 *pValue = pVM->cpum.s.Guest.cr0;
715 break;
716 case USE_REG_CR2:
717 *pValue = pVM->cpum.s.Guest.cr2;
718 break;
719 case USE_REG_CR3:
720 *pValue = pVM->cpum.s.Guest.cr3;
721 break;
722 case USE_REG_CR4:
723 *pValue = pVM->cpum.s.Guest.cr4;
724 break;
725 default:
726 return VERR_INVALID_PARAMETER;
727 }
728 return VINF_SUCCESS;
729}
730
731CPUMDECL(RTUINTREG) CPUMGetGuestDR0(PVM pVM)
732{
733 return pVM->cpum.s.Guest.dr0;
734}
735
736CPUMDECL(RTUINTREG) CPUMGetGuestDR1(PVM pVM)
737{
738 return pVM->cpum.s.Guest.dr1;
739}
740
741CPUMDECL(RTUINTREG) CPUMGetGuestDR2(PVM pVM)
742{
743 return pVM->cpum.s.Guest.dr2;
744}
745
746CPUMDECL(RTUINTREG) CPUMGetGuestDR3(PVM pVM)
747{
748 return pVM->cpum.s.Guest.dr3;
749}
750
751CPUMDECL(RTUINTREG) CPUMGetGuestDR6(PVM pVM)
752{
753 return pVM->cpum.s.Guest.dr6;
754}
755
756CPUMDECL(RTUINTREG) CPUMGetGuestDR7(PVM pVM)
757{
758 return pVM->cpum.s.Guest.dr7;
759}
760
761/** @todo drx should be an array */
762CPUMDECL(int) CPUMGetGuestDRx(PVM pVM, uint32_t iReg, uint32_t *pValue)
763{
764 switch (iReg)
765 {
766 case USE_REG_DR0:
767 *pValue = pVM->cpum.s.Guest.dr0;
768 break;
769 case USE_REG_DR1:
770 *pValue = pVM->cpum.s.Guest.dr1;
771 break;
772 case USE_REG_DR2:
773 *pValue = pVM->cpum.s.Guest.dr2;
774 break;
775 case USE_REG_DR3:
776 *pValue = pVM->cpum.s.Guest.dr3;
777 break;
778 case USE_REG_DR4:
779 case USE_REG_DR6:
780 *pValue = pVM->cpum.s.Guest.dr6;
781 break;
782 case USE_REG_DR5:
783 case USE_REG_DR7:
784 *pValue = pVM->cpum.s.Guest.dr7;
785 break;
786
787 default:
788 return VERR_INVALID_PARAMETER;
789 }
790 return VINF_SUCCESS;
791}
792
793/**
794 * Gets a CpuId leaf.
795 *
796 * @param pVM The VM handle.
797 * @param iLeaf The CPUID leaf to get.
798 * @param pEax Where to store the EAX value.
799 * @param pEbx Where to store the EBX value.
800 * @param pEcx Where to store the ECX value.
801 * @param pEdx Where to store the EDX value.
802 */
803CPUMDECL(void) CPUMGetGuestCpuId(PVM pVM, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx)
804{
805 PCCPUMCPUID pCpuId;
806 if (iLeaf < ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
807 pCpuId = &pVM->cpum.s.aGuestCpuIdStd[iLeaf];
808 else if (iLeaf - UINT32_C(0x80000000) < ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
809 pCpuId = &pVM->cpum.s.aGuestCpuIdExt[iLeaf - UINT32_C(0x80000000)];
810 else
811 pCpuId = &pVM->cpum.s.GuestCpuIdDef;
812
813 *pEax = pCpuId->eax;
814 *pEbx = pCpuId->ebx;
815 *pEcx = pCpuId->ecx;
816 *pEdx = pCpuId->edx;
817 Log2(("CPUMGetGuestCpuId: iLeaf=%#010x %RX32 %RX32 %RX32 %RX32\n", iLeaf, *pEax, *pEbx, *pEcx, *pEdx));
818}
819
820/**
821 * Gets a pointer to the array of standard CPUID leafs.
822 *
823 * CPUMGetGuestCpuIdStdMax() give the size of the array.
824 *
825 * @returns Pointer to the standard CPUID leafs (read-only).
826 * @param pVM The VM handle.
827 * @remark Intended for PATM.
828 */
829CPUMDECL(GCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdStdGCPtr(PVM pVM)
830{
831 return GCPTRTYPE(PCCPUMCPUID)VM_GUEST_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdStd[0]);
832}
833
834/**
835 * Gets a pointer to the array of extended CPUID leafs.
836 *
837 * CPUMGetGuestCpuIdExtMax() give the size of the array.
838 *
839 * @returns Pointer to the extended CPUID leafs (read-only).
840 * @param pVM The VM handle.
841 * @remark Intended for PATM.
842 */
843CPUMDECL(GCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdExtGCPtr(PVM pVM)
844{
845 return GCPTRTYPE(PCCPUMCPUID)VM_GUEST_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
846}
847
848/**
849 * Gets a pointer to the default CPUID leaf.
850 *
851 * @returns Pointer to the default CPUID leaf (read-only).
852 * @param pVM The VM handle.
853 * @remark Intended for PATM.
854 */
855CPUMDECL(GCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdDefGCPtr(PVM pVM)
856{
857 return GCPTRTYPE(PCCPUMCPUID)VM_GUEST_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
858}
859
860/**
861 * Gets a number of standard CPUID leafs.
862 *
863 * @returns Number of leafs.
864 * @param pVM The VM handle.
865 * @remark Intended for PATM.
866 */
867CPUMDECL(uint32_t) CPUMGetGuestCpuIdStdMax(PVM pVM)
868{
869 return ELEMENTS(pVM->cpum.s.aGuestCpuIdStd);
870}
871
872/**
873 * Gets a number of extended CPUID leafs.
874 *
875 * @returns Number of leafs.
876 * @param pVM The VM handle.
877 * @remark Intended for PATM.
878 */
879CPUMDECL(uint32_t) CPUMGetGuestCpuIdExtMax(PVM pVM)
880{
881 return ELEMENTS(pVM->cpum.s.aGuestCpuIdStd);
882}
883
884/**
885 * Sets a CPUID feature bit.
886 *
887 * @param pVM The VM Handle.
888 * @param enmFeature The feature to set.
889 */
890CPUMDECL(void) CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
891{
892 switch (enmFeature)
893 {
894 /*
895 * Set the APIC bit in both feature masks.
896 */
897 case CPUMCPUIDFEATURE_APIC:
898 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
899 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_APIC;
900 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
901 && pVM->cpum.s.aGuestCpuIdExt[1].edx)
902 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_APIC;
903 Log(("CPUMSetGuestCpuIdFeature: Enabled APIC\n"));
904 break;
905
906 /*
907 * Set the sysenter/sysexit bit in both feature masks.
908 * Assumes the caller knows what it's doing! (host must support these)
909 */
910 case CPUMCPUIDFEATURE_SEP:
911 {
912 uint32_t ulEdx, ulDummy;
913
914 ASMCpuId(1, &ulDummy, &ulDummy, &ulDummy, &ulEdx);
915 if (!(ulEdx & X86_CPUID_FEATURE_EDX_SEP))
916 {
917 AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
918 return;
919 }
920
921 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
922 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_SEP;
923 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
924 && pVM->cpum.s.aGuestCpuIdExt[1].edx)
925 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_SEP;
926 Log(("CPUMSetGuestCpuIdFeature: Enabled sysenter/exit\n"));
927 break;
928 }
929
930 default:
931 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
932 break;
933 }
934}
935
936/**
937 * Clears a CPUID feature bit.
938 *
939 * @param pVM The VM Handle.
940 * @param enmFeature The feature to clear.
941 */
942CPUMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
943{
944 switch (enmFeature)
945 {
946 /*
947 * Set the APIC bit in both feature masks.
948 */
949 case CPUMCPUIDFEATURE_APIC:
950 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
951 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_APIC;
952 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
953 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
954 Log(("CPUMSetGuestCpuIdFeature: Disabled APIC\n"));
955 break;
956
957 default:
958 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
959 break;
960 }
961}
962
963
964
965CPUMDECL(int) CPUMSetGuestDR0(PVM pVM, RTGCUINTREG uDr0)
966{
967 pVM->cpum.s.Guest.dr0 = uDr0;
968 return CPUMRecalcHyperDRx(pVM);
969}
970
971CPUMDECL(int) CPUMSetGuestDR1(PVM pVM, RTGCUINTREG uDr1)
972{
973 pVM->cpum.s.Guest.dr1 = uDr1;
974 return CPUMRecalcHyperDRx(pVM);
975}
976
977CPUMDECL(int) CPUMSetGuestDR2(PVM pVM, RTGCUINTREG uDr2)
978{
979 pVM->cpum.s.Guest.dr2 = uDr2;
980 return CPUMRecalcHyperDRx(pVM);
981}
982
983CPUMDECL(int) CPUMSetGuestDR3(PVM pVM, RTGCUINTREG uDr3)
984{
985 pVM->cpum.s.Guest.dr3 = uDr3;
986 return CPUMRecalcHyperDRx(pVM);
987}
988
989CPUMDECL(int) CPUMSetGuestDR6(PVM pVM, RTGCUINTREG uDr6)
990{
991 pVM->cpum.s.Guest.dr6 = uDr6;
992 return CPUMRecalcHyperDRx(pVM);
993}
994
995CPUMDECL(int) CPUMSetGuestDR7(PVM pVM, RTGCUINTREG uDr7)
996{
997 pVM->cpum.s.Guest.dr7 = uDr7;
998 return CPUMRecalcHyperDRx(pVM);
999}
1000
1001/** @todo drx should be an array */
1002CPUMDECL(int) CPUMSetGuestDRx(PVM pVM, uint32_t iReg, uint32_t Value)
1003{
1004 switch (iReg)
1005 {
1006 case USE_REG_DR0:
1007 pVM->cpum.s.Guest.dr0 = Value;
1008 break;
1009 case USE_REG_DR1:
1010 pVM->cpum.s.Guest.dr1 = Value;
1011 break;
1012 case USE_REG_DR2:
1013 pVM->cpum.s.Guest.dr2 = Value;
1014 break;
1015 case USE_REG_DR3:
1016 pVM->cpum.s.Guest.dr3 = Value;
1017 break;
1018 case USE_REG_DR4:
1019 case USE_REG_DR6:
1020 pVM->cpum.s.Guest.dr6 = Value;
1021 break;
1022 case USE_REG_DR5:
1023 case USE_REG_DR7:
1024 pVM->cpum.s.Guest.dr7 = Value;
1025 break;
1026
1027 default:
1028 return VERR_INVALID_PARAMETER;
1029 }
1030 return CPUMRecalcHyperDRx(pVM);
1031}
1032
1033
1034/**
1035 * Recalculates the hypvervisor DRx register values based on
1036 * current guest registers and DBGF breakpoints.
1037 *
1038 * This is called whenever a guest DRx register is modified and when DBGF
1039 * sets a hardware breakpoint. In guest context this function will reload
1040 * any (hyper) DRx registers which comes out with a different value.
1041 *
1042 * @returns VINF_SUCCESS.
1043 * @param pVM The VM handle.
1044 */
1045CPUMDECL(int) CPUMRecalcHyperDRx(PVM pVM)
1046{
1047 /*
1048 * Compare the DR7s first.
1049 *
1050 * We only care about the enabled flags. The GE and LE flags are always
1051 * set and we don't care if the guest doesn't set them. GD is virtualized
1052 * when we dispatch #DB, we never enable it.
1053 */
1054 const RTGCUINTREG uDbgfDr7 = DBGFBpGetDR7(pVM);
1055#ifdef CPUM_VIRTUALIZE_DRX
1056 const RTGCUINTREG uGstDr7 = CPUMGetGuestDR7(pVM);
1057#else
1058 const RTGCUINTREG uGstDr7 = 0;
1059#endif
1060 if ((uGstDr7 | uDbgfDr7) & X86_DR7_ENABLED_MASK)
1061 {
1062 /*
1063 * Ok, something is enabled. Recalc each of the breakpoints.
1064 * Straight forward code, not optimized/minimized in any way.
1065 */
1066 RTGCUINTREG uNewDr7 = X86_DR7_GE | X86_DR7_LE | X86_DR7_MB1_MASK;
1067
1068 /* bp 0 */
1069 RTGCUINTREG uNewDr0;
1070 if (uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0))
1071 {
1072 uNewDr7 |= uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
1073 uNewDr0 = DBGFBpGetDR0(pVM);
1074 }
1075 else if (uGstDr7 & (X86_DR7_L0 | X86_DR7_G0))
1076 {
1077 uNewDr7 |= uGstDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
1078 uNewDr0 = CPUMGetGuestDR0(pVM);
1079 }
1080 else
1081 uNewDr0 = pVM->cpum.s.Hyper.dr0;
1082
1083 /* bp 1 */
1084 RTGCUINTREG uNewDr1;
1085 if (uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1))
1086 {
1087 uNewDr7 |= uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
1088 uNewDr1 = DBGFBpGetDR1(pVM);
1089 }
1090 else if (uGstDr7 & (X86_DR7_L1 | X86_DR7_G1))
1091 {
1092 uNewDr7 |= uGstDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
1093 uNewDr1 = CPUMGetGuestDR1(pVM);
1094 }
1095 else
1096 uNewDr1 = pVM->cpum.s.Hyper.dr1;
1097
1098 /* bp 2 */
1099 RTGCUINTREG uNewDr2;
1100 if (uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2))
1101 {
1102 uNewDr7 |= uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
1103 uNewDr2 = DBGFBpGetDR2(pVM);
1104 }
1105 else if (uGstDr7 & (X86_DR7_L2 | X86_DR7_G2))
1106 {
1107 uNewDr7 |= uGstDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
1108 uNewDr2 = CPUMGetGuestDR2(pVM);
1109 }
1110 else
1111 uNewDr2 = pVM->cpum.s.Hyper.dr2;
1112
1113 /* bp 3 */
1114 RTGCUINTREG uNewDr3;
1115 if (uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3))
1116 {
1117 uNewDr7 |= uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
1118 uNewDr3 = DBGFBpGetDR3(pVM);
1119 }
1120 else if (uGstDr7 & (X86_DR7_L3 | X86_DR7_G3))
1121 {
1122 uNewDr7 |= uGstDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
1123 uNewDr3 = CPUMGetGuestDR3(pVM);
1124 }
1125 else
1126 uNewDr3 = pVM->cpum.s.Hyper.dr3;
1127
1128 /*
1129 * Apply the updates.
1130 */
1131#ifdef IN_GC
1132 if (!(pVM->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS))
1133 {
1134 /** @todo save host DBx registers. */
1135 }
1136#endif
1137 pVM->cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS;
1138 if (uNewDr3 != pVM->cpum.s.Hyper.dr3)
1139 CPUMSetHyperDR3(pVM, uNewDr3);
1140 if (uNewDr2 != pVM->cpum.s.Hyper.dr2)
1141 CPUMSetHyperDR2(pVM, uNewDr2);
1142 if (uNewDr1 != pVM->cpum.s.Hyper.dr1)
1143 CPUMSetHyperDR1(pVM, uNewDr1);
1144 if (uNewDr0 != pVM->cpum.s.Hyper.dr0)
1145 CPUMSetHyperDR0(pVM, uNewDr0);
1146 if (uNewDr7 != pVM->cpum.s.Hyper.dr7)
1147 CPUMSetHyperDR7(pVM, uNewDr7);
1148 }
1149 else
1150 {
1151#ifdef IN_GC
1152 if (pVM->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS)
1153 {
1154 /** @todo restore host DBx registers. */
1155 }
1156#endif
1157 pVM->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS;
1158 }
1159 Log2(("CPUMRecalcHyperDRx: fUseFlags=%#x %RGr %RGr %RGr %RGr %RGr %RGr\n",
1160 pVM->cpum.s.fUseFlags, pVM->cpum.s.Hyper.dr0, pVM->cpum.s.Hyper.dr1,
1161 pVM->cpum.s.Hyper.dr2, pVM->cpum.s.Hyper.dr3, pVM->cpum.s.Hyper.dr6,
1162 pVM->cpum.s.Hyper.dr7));
1163
1164 return VINF_SUCCESS;
1165}
1166
1167#ifndef IN_RING0 /** @todo I don't think we need this in R0, so move it to CPUMAll.cpp? */
1168
1169/**
1170 * Transforms the guest CPU state to raw-ring mode.
1171 *
1172 * This function will change the any of the cs and ss register with DPL=0 to DPL=1.
1173 *
1174 * @returns VBox status. (recompiler failure)
1175 * @param pVM VM handle.
1176 * @param pCtxCore The context core (for trap usage).
1177 * @see @ref pg_raw
1178 */
1179CPUMDECL(int) CPUMRawEnter(PVM pVM, PCPUMCTXCORE pCtxCore)
1180{
1181 Assert(!pVM->cpum.s.fRawEntered);
1182 if (!pCtxCore)
1183 pCtxCore = CPUMCTX2CORE(&pVM->cpum.s.Guest);
1184
1185 /*
1186 * Are we in Ring-0?
1187 */
1188 if ( pCtxCore->ss && (pCtxCore->ss & X86_SEL_RPL) == 0
1189 && !pCtxCore->eflags.Bits.u1VM)
1190 {
1191 /*
1192 * Enter execution mode.
1193 */
1194 PATMRawEnter(pVM, pCtxCore);
1195
1196 /*
1197 * Set CPL to Ring-1.
1198 */
1199 pCtxCore->ss |= 1;
1200 if (pCtxCore->cs && (pCtxCore->cs & X86_SEL_RPL) == 0)
1201 pCtxCore->cs |= 1;
1202 }
1203 else
1204 {
1205 AssertMsg((pCtxCore->ss & X86_SEL_RPL) >= 2 || pCtxCore->eflags.Bits.u1VM,
1206 ("ring-1 code not supported\n"));
1207 /*
1208 * PATM takes care of IOPL and IF flags for Ring-3 and Ring-2 code as well.
1209 */
1210 PATMRawEnter(pVM, pCtxCore);
1211 }
1212
1213 /*
1214 * Assert sanity.
1215 */
1216 AssertMsg((pCtxCore->eflags.u32 & X86_EFL_IF), ("X86_EFL_IF is clear\n"));
1217 AssertReleaseMsg( pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss & X86_SEL_RPL)
1218 || pCtxCore->eflags.Bits.u1VM,
1219 ("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss & X86_SEL_RPL));
1220 Assert((pVM->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)) == (X86_CR0_PG | X86_CR0_PE | X86_CR0_WP));
1221 pCtxCore->eflags.u32 |= X86_EFL_IF; /* paranoia */
1222
1223 pVM->cpum.s.fRawEntered = true;
1224 return VINF_SUCCESS;
1225}
1226
1227
1228/**
1229 * Transforms the guest CPU state from raw-ring mode to correct values.
1230 *
1231 * This function will change any selector registers with DPL=1 to DPL=0.
1232 *
1233 * @returns Adjusted rc.
1234 * @param pVM VM handle.
1235 * @param rc Raw mode return code
1236 * @param pCtxCore The context core (for trap usage).
1237 * @see @ref pg_raw
1238 */
1239CPUMDECL(int) CPUMRawLeave(PVM pVM, PCPUMCTXCORE pCtxCore, int rc)
1240{
1241 /*
1242 * Don't leave if we've already left (in GC).
1243 */
1244 Assert(pVM->cpum.s.fRawEntered);
1245 if (!pVM->cpum.s.fRawEntered)
1246 return rc;
1247 pVM->cpum.s.fRawEntered = false;
1248
1249 PCPUMCTX pCtx = &pVM->cpum.s.Guest;
1250 if (!pCtxCore)
1251 pCtxCore = CPUMCTX2CORE(pCtx);
1252 Assert(pCtxCore->eflags.Bits.u1VM || (pCtxCore->ss & X86_SEL_RPL));
1253 AssertMsg(pCtxCore->eflags.Bits.u1VM || pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss & X86_SEL_RPL),
1254 ("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss & X86_SEL_RPL));
1255
1256 /*
1257 * Are we executing in raw ring-1?
1258 */
1259 if ( (pCtxCore->ss & X86_SEL_RPL) == 1
1260 && !pCtxCore->eflags.Bits.u1VM)
1261 {
1262 /*
1263 * Leave execution mode.
1264 */
1265 PATMRawLeave(pVM, pCtxCore, rc);
1266 /* Not quite sure if this is really required, but shouldn't harm (too much anyways). */
1267 /** @todo See what happens if we remove this. */
1268 if ((pCtxCore->ds & X86_SEL_RPL) == 1)
1269 pCtxCore->ds &= ~X86_SEL_RPL;
1270 if ((pCtxCore->es & X86_SEL_RPL) == 1)
1271 pCtxCore->es &= ~X86_SEL_RPL;
1272 if ((pCtxCore->fs & X86_SEL_RPL) == 1)
1273 pCtxCore->fs &= ~X86_SEL_RPL;
1274 if ((pCtxCore->gs & X86_SEL_RPL) == 1)
1275 pCtxCore->gs &= ~X86_SEL_RPL;
1276
1277 /*
1278 * Ring-1 selector => Ring-0.
1279 */
1280 pCtxCore->ss &= ~X86_SEL_RPL;
1281 if ((pCtxCore->cs & X86_SEL_RPL) == 1)
1282 pCtxCore->cs &= ~X86_SEL_RPL;
1283 }
1284 else
1285 {
1286 /*
1287 * PATM is taking care of the IOPL and IF flags for us.
1288 */
1289 PATMRawLeave(pVM, pCtxCore, rc);
1290 if (!pCtxCore->eflags.Bits.u1VM)
1291 {
1292 /** @todo See what happens if we remove this. */
1293 if ((pCtxCore->ds & X86_SEL_RPL) == 1)
1294 pCtxCore->ds &= ~X86_SEL_RPL;
1295 if ((pCtxCore->es & X86_SEL_RPL) == 1)
1296 pCtxCore->es &= ~X86_SEL_RPL;
1297 if ((pCtxCore->fs & X86_SEL_RPL) == 1)
1298 pCtxCore->fs &= ~X86_SEL_RPL;
1299 if ((pCtxCore->gs & X86_SEL_RPL) == 1)
1300 pCtxCore->gs &= ~X86_SEL_RPL;
1301 }
1302 }
1303
1304 return rc;
1305}
1306
1307/**
1308 * Updates the EFLAGS while we're in raw-mode.
1309 *
1310 * @param pVM The VM handle.
1311 * @param pCtxCore The context core.
1312 * @param eflags The new EFLAGS value.
1313 */
1314CPUMDECL(void) CPUMRawSetEFlags(PVM pVM, PCPUMCTXCORE pCtxCore, uint32_t eflags)
1315{
1316 if (!pVM->cpum.s.fRawEntered)
1317 {
1318 pCtxCore->eflags.u32 = eflags;
1319 return;
1320 }
1321 PATMRawSetEFlags(pVM, pCtxCore, eflags);
1322}
1323
1324#endif /* !IN_RING0 */
1325
1326/**
1327 * Gets the EFLAGS while we're in raw-mode.
1328 *
1329 * @returns The eflags.
1330 * @param pVM The VM handle.
1331 * @param pCtxCore The context core.
1332 */
1333CPUMDECL(uint32_t) CPUMRawGetEFlags(PVM pVM, PCPUMCTXCORE pCtxCore)
1334{
1335#ifdef IN_RING0
1336 return pCtxCore->eflags.u32;
1337#else
1338 if (!pVM->cpum.s.fRawEntered)
1339 return pCtxCore->eflags.u32;
1340 return PATMRawGetEFlags(pVM, pCtxCore);
1341#endif
1342}
1343
1344
1345
1346
1347/**
1348 * Gets and resets the changed flags (CPUM_CHANGED_*).
1349 * Only REM should call this function.
1350 *
1351 * @returns The changed flags.
1352 * @param pVM The VM handle.
1353 */
1354CPUMDECL(unsigned) CPUMGetAndClearChangedFlagsREM(PVM pVM)
1355{
1356 unsigned fFlags = pVM->cpum.s.fChanged;
1357 pVM->cpum.s.fChanged = 0;
1358 /** @todo change the switcher to use the fChanged flags. */
1359 if (pVM->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
1360 {
1361 fFlags |= CPUM_CHANGED_FPU_REM;
1362 pVM->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
1363 }
1364 return fFlags;
1365}
1366
1367/**
1368 * Sets the specified changed flags (CPUM_CHANGED_*).
1369 *
1370 * @param pVM The VM handle.
1371 */
1372CPUMDECL(void) CPUMSetChangedFlags(PVM pVM, uint32_t fChangedFlags)
1373{
1374 pVM->cpum.s.fChanged |= fChangedFlags;
1375}
1376
1377/**
1378 * Checks if the CPU supports the FXSAVE and FXRSTOR instruction.
1379 * @returns true if supported.
1380 * @returns false if not supported.
1381 * @param pVM The VM handle.
1382 */
1383CPUMDECL(bool) CPUMSupportsFXSR(PVM pVM)
1384{
1385 return pVM->cpum.s.CPUFeatures.edx.u1FXSR != 0;
1386}
1387
1388
1389/**
1390 * Checks if the host OS uses the SYSENTER / SYSEXIT instructions.
1391 * @returns true if used.
1392 * @returns false if not used.
1393 * @param pVM The VM handle.
1394 */
1395CPUMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM)
1396{
1397 return (pVM->cpum.s.fUseFlags & CPUM_USE_SYSENTER) != 0;
1398}
1399
1400
1401/**
1402 * Checks if the host OS uses the SYSCALL / SYSRET instructions.
1403 * @returns true if used.
1404 * @returns false if not used.
1405 * @param pVM The VM handle.
1406 */
1407CPUMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM)
1408{
1409 return (pVM->cpum.s.fUseFlags & CPUM_USE_SYSCALL) != 0;
1410}
1411
1412/**
1413 * Lazily sync in the FPU/XMM state
1414 *
1415 * @returns VBox status code.
1416 * @param pVM VM handle.
1417 */
1418CPUMDECL(int) CPUMHandleLazyFPU(PVM pVM)
1419{
1420 return CPUMHandleLazyFPUAsm(&pVM->cpum.s);
1421}
1422
1423/**
1424 * Restore host FPU/XMM state
1425 *
1426 * @returns VBox status code.
1427 * @param pVM VM handle.
1428 */
1429CPUMDECL(int) CPUMRestoreHostFPUState(PVM pVM)
1430{
1431 Assert(pVM->cpum.s.CPUFeatures.edx.u1FXSR);
1432 return CPUMRestoreHostFPUStateAsm(&pVM->cpum.s);
1433}
1434
1435/**
1436 * Checks if we activated the FPU/XMM state of the guest OS
1437 * @returns true if we did.
1438 * @returns false if not.
1439 * @param pVM The VM handle.
1440 */
1441CPUMDECL(bool) CPUMIsGuestFPUStateActive(PVM pVM)
1442{
1443 return (pVM->cpum.s.fUseFlags & CPUM_USED_FPU) != 0;
1444}
1445
1446/**
1447 * Deactivate the FPU/XMM state of the guest OS
1448 * @param pVM The VM handle.
1449 */
1450CPUMDECL(void) CPUMDeactivateGuestFPUState(PVM pVM)
1451{
1452 pVM->cpum.s.fUseFlags &= ~CPUM_USED_FPU;
1453}
1454
1455/**
1456 * Checks if the hidden selector registers are valid
1457 * @returns true if they are.
1458 * @returns false if not.
1459 * @param pVM The VM handle.
1460 */
1461CPUMDECL(bool) CPUMAreHiddenSelRegsValid(PVM pVM)
1462{
1463 return !!pVM->cpum.s.fValidHiddenSelRegs; /** @todo change fValidHiddenSelRegs to bool! */
1464}
1465
1466/**
1467 * Checks if the hidden selector registers are valid
1468 * @param pVM The VM handle.
1469 * @param fValid Valid or not
1470 */
1471CPUMDECL(void) CPUMSetHiddenSelRegsValid(PVM pVM, bool fValid)
1472{
1473 pVM->cpum.s.fValidHiddenSelRegs = fValid;
1474}
1475
1476/**
1477 * Get the current privilege level of the guest.
1478 *
1479 * @returns cpl
1480 * @param pVM VM Handle.
1481 * @param pRegFrame Trap register frame.
1482 */
1483CPUMDECL(uint32_t) CPUMGetGuestCPL(PVM pVM, PCPUMCTXCORE pCtxCore)
1484{
1485 uint32_t cpl;
1486
1487 if (CPUMAreHiddenSelRegsValid(pVM))
1488 cpl = pCtxCore->ssHid.Attr.n.u2Dpl;
1489 else if (RT_LIKELY(pVM->cpum.s.Guest.cr0 & X86_CR0_PE))
1490 {
1491 if (RT_LIKELY(!pCtxCore->eflags.Bits.u1VM))
1492 {
1493 cpl = (pCtxCore->ss & X86_SEL_RPL);
1494#ifndef IN_RING0
1495 if (cpl == 1)
1496 cpl = 0;
1497#endif
1498 }
1499 else
1500 cpl = 3;
1501 }
1502 else
1503 cpl = 0; /* real mode; cpl is zero */
1504
1505 return cpl;
1506}
1507
1508
1509/**
1510 * Gets the current guest CPU mode.
1511 *
1512 * If paging mode is what you need, check out PGMGetGuestMode().
1513 *
1514 * @returns The CPU mode.
1515 * @param pVM The VM handle.
1516 */
1517CPUMDECL(CPUMMODE) CPUMGetGuestMode(PVM pVM)
1518{
1519 CPUMMODE enmMode;
1520 if (!(pVM->cpum.s.Guest.cr0 & X86_CR0_PE))
1521 enmMode = CPUMMODE_REAL;
1522 else //GUEST64 if (!(pVM->cpum.s.Guest.efer & MSR_K6_EFER_LMA)
1523 enmMode = CPUMMODE_PROTECTED;
1524//GUEST64 else
1525//GUEST64 enmMode = CPUMMODE_LONG;
1526
1527 return enmMode;
1528}
1529
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