VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp@ 48749

Last change on this file since 48749 was 48697, checked in by vboxsync, 11 years ago

build fix
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 100.6 KB
Line 
1/* $Id: CPUMAllRegs.cpp 48697 2013-09-26 01:02:55Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor(/Manager) - Getters and Setters.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_CPUM
23#include <VBox/vmm/cpum.h>
24#include <VBox/vmm/patm.h>
25#include <VBox/vmm/dbgf.h>
26#include <VBox/vmm/pdm.h>
27#include <VBox/vmm/pgm.h>
28#include <VBox/vmm/mm.h>
29#include <VBox/vmm/em.h>
30#if defined(VBOX_WITH_RAW_MODE) && !defined(IN_RING0)
31# include <VBox/vmm/selm.h>
32#endif
33#include "CPUMInternal.h"
34#include <VBox/vmm/vm.h>
35#include <VBox/err.h>
36#include <VBox/dis.h>
37#include <VBox/log.h>
38#include <VBox/vmm/hm.h>
39#include <VBox/vmm/tm.h>
40#include <iprt/assert.h>
41#include <iprt/asm.h>
42#include <iprt/asm-amd64-x86.h>
43#ifdef IN_RING3
44#include <iprt/thread.h>
45#endif
46
47/** Disable stack frame pointer generation here. */
48#if defined(_MSC_VER) && !defined(DEBUG)
49# pragma optimize("y", off)
50#endif
51
52
53/*******************************************************************************
54* Defined Constants And Macros *
55*******************************************************************************/
56/**
57 * Converts a CPUMCPU::Guest pointer into a VMCPU pointer.
58 *
59 * @returns Pointer to the Virtual CPU.
60 * @param a_pGuestCtx Pointer to the guest context.
61 */
62#define CPUM_GUEST_CTX_TO_VMCPU(a_pGuestCtx) RT_FROM_MEMBER(a_pGuestCtx, VMCPU, cpum.s.Guest)
63
64/**
65 * Lazily loads the hidden parts of a selector register when using raw-mode.
66 */
67#if defined(VBOX_WITH_RAW_MODE) && !defined(IN_RING0)
68# define CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(a_pVCpu, a_pSReg) \
69 do \
70 { \
71 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(a_pVCpu, a_pSReg)) \
72 cpumGuestLazyLoadHiddenSelectorReg(a_pVCpu, a_pSReg); \
73 } while (0)
74#else
75# define CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(a_pVCpu, a_pSReg) \
76 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(a_pVCpu, a_pSReg));
77#endif
78
79
80
81#ifdef VBOX_WITH_RAW_MODE_NOT_R0
82
83/**
84 * Does the lazy hidden selector register loading.
85 *
86 * @param pVCpu The current Virtual CPU.
87 * @param pSReg The selector register to lazily load hidden parts of.
88 */
89static void cpumGuestLazyLoadHiddenSelectorReg(PVMCPU pVCpu, PCPUMSELREG pSReg)
90{
91 Assert(!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSReg));
92 Assert(!HMIsEnabled(pVCpu->CTX_SUFF(pVM)));
93 Assert((uintptr_t)(pSReg - &pVCpu->cpum.s.Guest.es) < X86_SREG_COUNT);
94
95 if (pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
96 {
97 /* V8086 mode - Tightly controlled environment, no question about the limit or flags. */
98 pSReg->Attr.u = 0;
99 pSReg->Attr.n.u4Type = pSReg == &pVCpu->cpum.s.Guest.cs ? X86_SEL_TYPE_ER_ACC : X86_SEL_TYPE_RW_ACC;
100 pSReg->Attr.n.u1DescType = 1; /* code/data segment */
101 pSReg->Attr.n.u2Dpl = 3;
102 pSReg->Attr.n.u1Present = 1;
103 pSReg->u32Limit = 0x0000ffff;
104 pSReg->u64Base = (uint32_t)pSReg->Sel << 4;
105 pSReg->ValidSel = pSReg->Sel;
106 pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
107 /** @todo Check what the accessed bit should be (VT-x and AMD-V). */
108 }
109 else if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
110 {
111 /* Real mode - leave the limit and flags alone here, at least for now. */
112 pSReg->u64Base = (uint32_t)pSReg->Sel << 4;
113 pSReg->ValidSel = pSReg->Sel;
114 pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
115 }
116 else
117 {
118 /* Protected mode - get it from the selector descriptor tables. */
119 if (!(pSReg->Sel & X86_SEL_MASK_OFF_RPL))
120 {
121 Assert(!CPUMIsGuestInLongMode(pVCpu));
122 pSReg->Sel = 0;
123 pSReg->u64Base = 0;
124 pSReg->u32Limit = 0;
125 pSReg->Attr.u = 0;
126 pSReg->ValidSel = 0;
127 pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
128 /** @todo see todo in iemHlpLoadNullDataSelectorProt. */
129 }
130 else
131 SELMLoadHiddenSelectorReg(pVCpu, &pVCpu->cpum.s.Guest, pSReg);
132 }
133}
134
135
136/**
137 * Makes sure the hidden CS and SS selector registers are valid, loading them if
138 * necessary.
139 *
140 * @param pVCpu The current virtual CPU.
141 */
142VMM_INT_DECL(void) CPUMGuestLazyLoadHiddenCsAndSs(PVMCPU pVCpu)
143{
144 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
145 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.ss);
146}
147
148
149/**
150 * Loads a the hidden parts of a selector register.
151 *
152 * @param pVCpu The current virtual CPU.
153 */
154VMM_INT_DECL(void) CPUMGuestLazyLoadHiddenSelectorReg(PVMCPU pVCpu, PCPUMSELREG pSReg)
155{
156 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, pSReg);
157}
158
159#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
160
161
162/**
163 * Obsolete.
164 *
165 * We don't support nested hypervisor context interrupts or traps. Life is much
166 * simpler when we don't. It's also slightly faster at times.
167 *
168 * @param pVM Handle to the virtual machine.
169 */
170VMMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVMCPU pVCpu)
171{
172 return CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
173}
174
175
176/**
177 * Gets the pointer to the hypervisor CPU context structure of a virtual CPU.
178 *
179 * @param pVCpu Pointer to the VMCPU.
180 */
181VMMDECL(PCPUMCTX) CPUMGetHyperCtxPtr(PVMCPU pVCpu)
182{
183 return &pVCpu->cpum.s.Hyper;
184}
185
186
187VMMDECL(void) CPUMSetHyperGDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
188{
189 pVCpu->cpum.s.Hyper.gdtr.cbGdt = limit;
190 pVCpu->cpum.s.Hyper.gdtr.pGdt = addr;
191}
192
193
194VMMDECL(void) CPUMSetHyperIDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
195{
196 pVCpu->cpum.s.Hyper.idtr.cbIdt = limit;
197 pVCpu->cpum.s.Hyper.idtr.pIdt = addr;
198}
199
200
201VMMDECL(void) CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3)
202{
203 pVCpu->cpum.s.Hyper.cr3 = cr3;
204
205#ifdef IN_RC
206 /* Update the current CR3. */
207 ASMSetCR3(cr3);
208#endif
209}
210
211VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu)
212{
213 return pVCpu->cpum.s.Hyper.cr3;
214}
215
216
217VMMDECL(void) CPUMSetHyperCS(PVMCPU pVCpu, RTSEL SelCS)
218{
219 pVCpu->cpum.s.Hyper.cs.Sel = SelCS;
220}
221
222
223VMMDECL(void) CPUMSetHyperDS(PVMCPU pVCpu, RTSEL SelDS)
224{
225 pVCpu->cpum.s.Hyper.ds.Sel = SelDS;
226}
227
228
229VMMDECL(void) CPUMSetHyperES(PVMCPU pVCpu, RTSEL SelES)
230{
231 pVCpu->cpum.s.Hyper.es.Sel = SelES;
232}
233
234
235VMMDECL(void) CPUMSetHyperFS(PVMCPU pVCpu, RTSEL SelFS)
236{
237 pVCpu->cpum.s.Hyper.fs.Sel = SelFS;
238}
239
240
241VMMDECL(void) CPUMSetHyperGS(PVMCPU pVCpu, RTSEL SelGS)
242{
243 pVCpu->cpum.s.Hyper.gs.Sel = SelGS;
244}
245
246
247VMMDECL(void) CPUMSetHyperSS(PVMCPU pVCpu, RTSEL SelSS)
248{
249 pVCpu->cpum.s.Hyper.ss.Sel = SelSS;
250}
251
252
253VMMDECL(void) CPUMSetHyperESP(PVMCPU pVCpu, uint32_t u32ESP)
254{
255 pVCpu->cpum.s.Hyper.esp = u32ESP;
256}
257
258
259VMMDECL(void) CPUMSetHyperEDX(PVMCPU pVCpu, uint32_t u32ESP)
260{
261 pVCpu->cpum.s.Hyper.esp = u32ESP;
262}
263
264
265VMMDECL(int) CPUMSetHyperEFlags(PVMCPU pVCpu, uint32_t Efl)
266{
267 pVCpu->cpum.s.Hyper.eflags.u32 = Efl;
268 return VINF_SUCCESS;
269}
270
271
272VMMDECL(void) CPUMSetHyperEIP(PVMCPU pVCpu, uint32_t u32EIP)
273{
274 pVCpu->cpum.s.Hyper.eip = u32EIP;
275}
276
277
278/**
279 * Used by VMMR3RawRunGC to reinitialize the general raw-mode context registers,
280 * EFLAGS and EIP prior to resuming guest execution.
281 *
282 * All general register not given as a parameter will be set to 0. The EFLAGS
283 * register will be set to sane values for C/C++ code execution with interrupts
284 * disabled and IOPL 0.
285 *
286 * @param pVCpu The current virtual CPU.
287 * @param u32EIP The EIP value.
288 * @param u32ESP The ESP value.
289 * @param u32EAX The EAX value.
290 * @param u32EDX The EDX value.
291 */
292VMM_INT_DECL(void) CPUMSetHyperState(PVMCPU pVCpu, uint32_t u32EIP, uint32_t u32ESP, uint32_t u32EAX, uint32_t u32EDX)
293{
294 pVCpu->cpum.s.Hyper.eip = u32EIP;
295 pVCpu->cpum.s.Hyper.esp = u32ESP;
296 pVCpu->cpum.s.Hyper.eax = u32EAX;
297 pVCpu->cpum.s.Hyper.edx = u32EDX;
298 pVCpu->cpum.s.Hyper.ecx = 0;
299 pVCpu->cpum.s.Hyper.ebx = 0;
300 pVCpu->cpum.s.Hyper.ebp = 0;
301 pVCpu->cpum.s.Hyper.esi = 0;
302 pVCpu->cpum.s.Hyper.edi = 0;
303 pVCpu->cpum.s.Hyper.eflags.u = X86_EFL_1;
304}
305
306
307VMMDECL(void) CPUMSetHyperTR(PVMCPU pVCpu, RTSEL SelTR)
308{
309 pVCpu->cpum.s.Hyper.tr.Sel = SelTR;
310}
311
312
313VMMDECL(void) CPUMSetHyperLDTR(PVMCPU pVCpu, RTSEL SelLDTR)
314{
315 pVCpu->cpum.s.Hyper.ldtr.Sel = SelLDTR;
316}
317
318
319/** @MAYBE_LOAD_DRx
320 * Macro for updating DRx values in raw-mode and ring-0 contexts.
321 */
322#ifdef IN_RING0
323# if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
324# ifndef VBOX_WITH_HYBRID_32BIT_KERNEL
325# define MAYBE_LOAD_DRx(a_pVCpu, a_fnLoad, a_uValue) \
326 do { \
327 if (!CPUMIsGuestInLongModeEx(&(a_pVCpu)->cpum.s.Guest)) \
328 a_fnLoad(a_uValue); \
329 else \
330 (a_pVCpu)->cpum.s.fUseFlags |= CPUM_SYNC_DEBUG_REGS_HYPER; \
331 } while (0)
332# else
333# define MAYBE_LOAD_DRx(a_pVCpu, a_fnLoad, a_uValue) \
334 do { \
335 /** @todo we're not loading the correct guest value here! */ \
336 a_fnLoad(a_uValue); \
337 } while (0)
338# endif
339# else
340# define MAYBE_LOAD_DRx(a_pVCpu, a_fnLoad, a_uValue) \
341 do { \
342 a_fnLoad(a_uValue); \
343 } while (0)
344# endif
345
346#elif defined(IN_RC)
347# define MAYBE_LOAD_DRx(a_pVCpu, a_fnLoad, a_uValue) \
348 do { \
349 if ((a_pVCpu)->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HYPER) \
350 { a_fnLoad(a_uValue); } \
351 } while (0)
352
353#else
354# define MAYBE_LOAD_DRx(a_pVCpu, a_fnLoad, a_uValue) do { } while (0)
355#endif
356
357VMMDECL(void) CPUMSetHyperDR0(PVMCPU pVCpu, RTGCUINTREG uDr0)
358{
359 pVCpu->cpum.s.Hyper.dr[0] = uDr0;
360 MAYBE_LOAD_DRx(pVCpu, ASMSetDR0, uDr0);
361}
362
363
364VMMDECL(void) CPUMSetHyperDR1(PVMCPU pVCpu, RTGCUINTREG uDr1)
365{
366 pVCpu->cpum.s.Hyper.dr[1] = uDr1;
367 MAYBE_LOAD_DRx(pVCpu, ASMSetDR1, uDr1);
368}
369
370
371VMMDECL(void) CPUMSetHyperDR2(PVMCPU pVCpu, RTGCUINTREG uDr2)
372{
373 pVCpu->cpum.s.Hyper.dr[2] = uDr2;
374 MAYBE_LOAD_DRx(pVCpu, ASMSetDR2, uDr2);
375}
376
377
378VMMDECL(void) CPUMSetHyperDR3(PVMCPU pVCpu, RTGCUINTREG uDr3)
379{
380 pVCpu->cpum.s.Hyper.dr[3] = uDr3;
381 MAYBE_LOAD_DRx(pVCpu, ASMSetDR3, uDr3);
382}
383
384
385VMMDECL(void) CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6)
386{
387 pVCpu->cpum.s.Hyper.dr[6] = uDr6;
388}
389
390
391VMMDECL(void) CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7)
392{
393 pVCpu->cpum.s.Hyper.dr[7] = uDr7;
394#ifdef IN_RC
395 MAYBE_LOAD_DRx(pVCpu, ASMSetDR7, uDr7);
396#endif
397}
398
399
400VMMDECL(RTSEL) CPUMGetHyperCS(PVMCPU pVCpu)
401{
402 return pVCpu->cpum.s.Hyper.cs.Sel;
403}
404
405
406VMMDECL(RTSEL) CPUMGetHyperDS(PVMCPU pVCpu)
407{
408 return pVCpu->cpum.s.Hyper.ds.Sel;
409}
410
411
412VMMDECL(RTSEL) CPUMGetHyperES(PVMCPU pVCpu)
413{
414 return pVCpu->cpum.s.Hyper.es.Sel;
415}
416
417
418VMMDECL(RTSEL) CPUMGetHyperFS(PVMCPU pVCpu)
419{
420 return pVCpu->cpum.s.Hyper.fs.Sel;
421}
422
423
424VMMDECL(RTSEL) CPUMGetHyperGS(PVMCPU pVCpu)
425{
426 return pVCpu->cpum.s.Hyper.gs.Sel;
427}
428
429
430VMMDECL(RTSEL) CPUMGetHyperSS(PVMCPU pVCpu)
431{
432 return pVCpu->cpum.s.Hyper.ss.Sel;
433}
434
435
436VMMDECL(uint32_t) CPUMGetHyperEAX(PVMCPU pVCpu)
437{
438 return pVCpu->cpum.s.Hyper.eax;
439}
440
441
442VMMDECL(uint32_t) CPUMGetHyperEBX(PVMCPU pVCpu)
443{
444 return pVCpu->cpum.s.Hyper.ebx;
445}
446
447
448VMMDECL(uint32_t) CPUMGetHyperECX(PVMCPU pVCpu)
449{
450 return pVCpu->cpum.s.Hyper.ecx;
451}
452
453
454VMMDECL(uint32_t) CPUMGetHyperEDX(PVMCPU pVCpu)
455{
456 return pVCpu->cpum.s.Hyper.edx;
457}
458
459
460VMMDECL(uint32_t) CPUMGetHyperESI(PVMCPU pVCpu)
461{
462 return pVCpu->cpum.s.Hyper.esi;
463}
464
465
466VMMDECL(uint32_t) CPUMGetHyperEDI(PVMCPU pVCpu)
467{
468 return pVCpu->cpum.s.Hyper.edi;
469}
470
471
472VMMDECL(uint32_t) CPUMGetHyperEBP(PVMCPU pVCpu)
473{
474 return pVCpu->cpum.s.Hyper.ebp;
475}
476
477
478VMMDECL(uint32_t) CPUMGetHyperESP(PVMCPU pVCpu)
479{
480 return pVCpu->cpum.s.Hyper.esp;
481}
482
483
484VMMDECL(uint32_t) CPUMGetHyperEFlags(PVMCPU pVCpu)
485{
486 return pVCpu->cpum.s.Hyper.eflags.u32;
487}
488
489
490VMMDECL(uint32_t) CPUMGetHyperEIP(PVMCPU pVCpu)
491{
492 return pVCpu->cpum.s.Hyper.eip;
493}
494
495
496VMMDECL(uint64_t) CPUMGetHyperRIP(PVMCPU pVCpu)
497{
498 return pVCpu->cpum.s.Hyper.rip;
499}
500
501
502VMMDECL(uint32_t) CPUMGetHyperIDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
503{
504 if (pcbLimit)
505 *pcbLimit = pVCpu->cpum.s.Hyper.idtr.cbIdt;
506 return pVCpu->cpum.s.Hyper.idtr.pIdt;
507}
508
509
510VMMDECL(uint32_t) CPUMGetHyperGDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
511{
512 if (pcbLimit)
513 *pcbLimit = pVCpu->cpum.s.Hyper.gdtr.cbGdt;
514 return pVCpu->cpum.s.Hyper.gdtr.pGdt;
515}
516
517
518VMMDECL(RTSEL) CPUMGetHyperLDTR(PVMCPU pVCpu)
519{
520 return pVCpu->cpum.s.Hyper.ldtr.Sel;
521}
522
523
524VMMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVMCPU pVCpu)
525{
526 return pVCpu->cpum.s.Hyper.dr[0];
527}
528
529
530VMMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVMCPU pVCpu)
531{
532 return pVCpu->cpum.s.Hyper.dr[1];
533}
534
535
536VMMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVMCPU pVCpu)
537{
538 return pVCpu->cpum.s.Hyper.dr[2];
539}
540
541
542VMMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVMCPU pVCpu)
543{
544 return pVCpu->cpum.s.Hyper.dr[3];
545}
546
547
548VMMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVMCPU pVCpu)
549{
550 return pVCpu->cpum.s.Hyper.dr[6];
551}
552
553
554VMMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVMCPU pVCpu)
555{
556 return pVCpu->cpum.s.Hyper.dr[7];
557}
558
559
560/**
561 * Gets the pointer to the internal CPUMCTXCORE structure.
562 * This is only for reading in order to save a few calls.
563 *
564 * @param pVCpu Handle to the virtual cpu.
565 */
566VMMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVMCPU pVCpu)
567{
568 return CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
569}
570
571
572/**
573 * Queries the pointer to the internal CPUMCTX structure.
574 *
575 * @returns The CPUMCTX pointer.
576 * @param pVCpu Handle to the virtual cpu.
577 */
578VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu)
579{
580 return &pVCpu->cpum.s.Guest;
581}
582
583VMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit)
584{
585#ifdef VBOX_WITH_IEM
586# ifdef VBOX_WITH_RAW_MODE_NOT_R0
587 if (!HMIsEnabled(pVCpu->CTX_SUFF(pVM)))
588 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
589# endif
590#endif
591 pVCpu->cpum.s.Guest.gdtr.cbGdt = cbLimit;
592 pVCpu->cpum.s.Guest.gdtr.pGdt = GCPtrBase;
593 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GDTR;
594 return VINF_SUCCESS; /* formality, consider it void. */
595}
596
597VMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit)
598{
599#ifdef VBOX_WITH_IEM
600# ifdef VBOX_WITH_RAW_MODE_NOT_R0
601 if (!HMIsEnabled(pVCpu->CTX_SUFF(pVM)))
602 VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
603# endif
604#endif
605 pVCpu->cpum.s.Guest.idtr.cbIdt = cbLimit;
606 pVCpu->cpum.s.Guest.idtr.pIdt = GCPtrBase;
607 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_IDTR;
608 return VINF_SUCCESS; /* formality, consider it void. */
609}
610
611VMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr)
612{
613#ifdef VBOX_WITH_IEM
614# ifdef VBOX_WITH_RAW_MODE_NOT_R0
615 if (!HMIsEnabled(pVCpu->CTX_SUFF(pVM)))
616 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
617# endif
618#endif
619 pVCpu->cpum.s.Guest.tr.Sel = tr;
620 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_TR;
621 return VINF_SUCCESS; /* formality, consider it void. */
622}
623
624VMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr)
625{
626#ifdef VBOX_WITH_IEM
627# ifdef VBOX_WITH_RAW_MODE_NOT_R0
628 if ( ( ldtr != 0
629 || pVCpu->cpum.s.Guest.ldtr.Sel != 0)
630 && !HMIsEnabled(pVCpu->CTX_SUFF(pVM)))
631 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
632# endif
633#endif
634 pVCpu->cpum.s.Guest.ldtr.Sel = ldtr;
635 /* The caller will set more hidden bits if it has them. */
636 pVCpu->cpum.s.Guest.ldtr.ValidSel = 0;
637 pVCpu->cpum.s.Guest.ldtr.fFlags = 0;
638 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_LDTR;
639 return VINF_SUCCESS; /* formality, consider it void. */
640}
641
642
643/**
644 * Set the guest CR0.
645 *
646 * When called in GC, the hyper CR0 may be updated if that is
647 * required. The caller only has to take special action if AM,
648 * WP, PG or PE changes.
649 *
650 * @returns VINF_SUCCESS (consider it void).
651 * @param pVCpu Handle to the virtual cpu.
652 * @param cr0 The new CR0 value.
653 */
654VMMDECL(int) CPUMSetGuestCR0(PVMCPU pVCpu, uint64_t cr0)
655{
656#ifdef IN_RC
657 /*
658 * Check if we need to change hypervisor CR0 because
659 * of math stuff.
660 */
661 if ( (cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP))
662 != (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP)))
663 {
664 if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU))
665 {
666 /*
667 * We haven't saved the host FPU state yet, so TS and MT are both set
668 * and EM should be reflecting the guest EM (it always does this).
669 */
670 if ((cr0 & X86_CR0_EM) != (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM))
671 {
672 uint32_t HyperCR0 = ASMGetCR0();
673 AssertMsg((HyperCR0 & (X86_CR0_TS | X86_CR0_MP)) == (X86_CR0_TS | X86_CR0_MP), ("%#x\n", HyperCR0));
674 AssertMsg((HyperCR0 & X86_CR0_EM) == (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM), ("%#x\n", HyperCR0));
675 HyperCR0 &= ~X86_CR0_EM;
676 HyperCR0 |= cr0 & X86_CR0_EM;
677 Log(("CPUM: New HyperCR0=%#x\n", HyperCR0));
678 ASMSetCR0(HyperCR0);
679 }
680# ifdef VBOX_STRICT
681 else
682 {
683 uint32_t HyperCR0 = ASMGetCR0();
684 AssertMsg((HyperCR0 & (X86_CR0_TS | X86_CR0_MP)) == (X86_CR0_TS | X86_CR0_MP), ("%#x\n", HyperCR0));
685 AssertMsg((HyperCR0 & X86_CR0_EM) == (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM), ("%#x\n", HyperCR0));
686 }
687# endif
688 }
689 else
690 {
691 /*
692 * Already saved the state, so we're just mirroring
693 * the guest flags.
694 */
695 uint32_t HyperCR0 = ASMGetCR0();
696 AssertMsg( (HyperCR0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP))
697 == (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP)),
698 ("%#x %#x\n", HyperCR0, pVCpu->cpum.s.Guest.cr0));
699 HyperCR0 &= ~(X86_CR0_TS | X86_CR0_EM | X86_CR0_MP);
700 HyperCR0 |= cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP);
701 Log(("CPUM: New HyperCR0=%#x\n", HyperCR0));
702 ASMSetCR0(HyperCR0);
703 }
704 }
705#endif /* IN_RC */
706
707 /*
708 * Check for changes causing TLB flushes (for REM).
709 * The caller is responsible for calling PGM when appropriate.
710 */
711 if ( (cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE))
712 != (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)))
713 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
714 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR0;
715
716 /*
717 * Let PGM know if the WP goes from 0 to 1 (netware WP0+RO+US hack)
718 */
719 if (((cr0 ^ pVCpu->cpum.s.Guest.cr0) & X86_CR0_WP) && (cr0 & X86_CR0_WP))
720 PGMCr0WpEnabled(pVCpu);
721
722 pVCpu->cpum.s.Guest.cr0 = cr0 | X86_CR0_ET;
723 return VINF_SUCCESS;
724}
725
726
727VMMDECL(int) CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2)
728{
729 pVCpu->cpum.s.Guest.cr2 = cr2;
730 return VINF_SUCCESS;
731}
732
733
734VMMDECL(int) CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3)
735{
736 pVCpu->cpum.s.Guest.cr3 = cr3;
737 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR3;
738 return VINF_SUCCESS;
739}
740
741
742VMMDECL(int) CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4)
743{
744 if ( (cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE))
745 != (pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE)))
746 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
747 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR4;
748 if (!CPUMSupportsFXSR(pVCpu->CTX_SUFF(pVM)))
749 cr4 &= ~X86_CR4_OSFSXR;
750 pVCpu->cpum.s.Guest.cr4 = cr4;
751 return VINF_SUCCESS;
752}
753
754
755VMMDECL(int) CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags)
756{
757 pVCpu->cpum.s.Guest.eflags.u32 = eflags;
758 return VINF_SUCCESS;
759}
760
761
762VMMDECL(int) CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip)
763{
764 pVCpu->cpum.s.Guest.eip = eip;
765 return VINF_SUCCESS;
766}
767
768
769VMMDECL(int) CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax)
770{
771 pVCpu->cpum.s.Guest.eax = eax;
772 return VINF_SUCCESS;
773}
774
775
776VMMDECL(int) CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx)
777{
778 pVCpu->cpum.s.Guest.ebx = ebx;
779 return VINF_SUCCESS;
780}
781
782
783VMMDECL(int) CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx)
784{
785 pVCpu->cpum.s.Guest.ecx = ecx;
786 return VINF_SUCCESS;
787}
788
789
790VMMDECL(int) CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx)
791{
792 pVCpu->cpum.s.Guest.edx = edx;
793 return VINF_SUCCESS;
794}
795
796
797VMMDECL(int) CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp)
798{
799 pVCpu->cpum.s.Guest.esp = esp;
800 return VINF_SUCCESS;
801}
802
803
804VMMDECL(int) CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp)
805{
806 pVCpu->cpum.s.Guest.ebp = ebp;
807 return VINF_SUCCESS;
808}
809
810
811VMMDECL(int) CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi)
812{
813 pVCpu->cpum.s.Guest.esi = esi;
814 return VINF_SUCCESS;
815}
816
817
818VMMDECL(int) CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi)
819{
820 pVCpu->cpum.s.Guest.edi = edi;
821 return VINF_SUCCESS;
822}
823
824
825VMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss)
826{
827 pVCpu->cpum.s.Guest.ss.Sel = ss;
828 return VINF_SUCCESS;
829}
830
831
832VMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs)
833{
834 pVCpu->cpum.s.Guest.cs.Sel = cs;
835 return VINF_SUCCESS;
836}
837
838
839VMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds)
840{
841 pVCpu->cpum.s.Guest.ds.Sel = ds;
842 return VINF_SUCCESS;
843}
844
845
846VMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es)
847{
848 pVCpu->cpum.s.Guest.es.Sel = es;
849 return VINF_SUCCESS;
850}
851
852
853VMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs)
854{
855 pVCpu->cpum.s.Guest.fs.Sel = fs;
856 return VINF_SUCCESS;
857}
858
859
860VMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs)
861{
862 pVCpu->cpum.s.Guest.gs.Sel = gs;
863 return VINF_SUCCESS;
864}
865
866
867VMMDECL(void) CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val)
868{
869 pVCpu->cpum.s.Guest.msrEFER = val;
870}
871
872
873/**
874 * Worker for CPUMQueryGuestMsr().
875 *
876 * @retval VINF_SUCCESS
877 * @retval VERR_CPUM_RAISE_GP_0
878 * @param pVCpu The cross context CPU structure.
879 * @param idMsr The MSR to read.
880 * @param puValue Where to store the return value.
881 */
882static int cpumQueryGuestMsrInt(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue)
883{
884 /*
885 * If we don't indicate MSR support in the CPUID feature bits, indicate
886 * that a #GP(0) should be raised.
887 */
888 if (!(pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_MSR))
889 {
890 *puValue = 0;
891 return VERR_CPUM_RAISE_GP_0; /** @todo isn't \#UD more correct if not supported? */
892 }
893
894 int rc = VINF_SUCCESS;
895 uint8_t const u8Multiplier = 4;
896 switch (idMsr)
897 {
898 case MSR_IA32_TSC:
899 *puValue = TMCpuTickGet(pVCpu);
900 break;
901
902 case MSR_IA32_APICBASE:
903 {
904 PVM pVM = pVCpu->CTX_SUFF(pVM);
905 if ( ( pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1 /* APIC Std feature */
906 && (pVM->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_APIC))
907 || ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001 /* APIC Ext feature (AMD) */
908 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD
909 && (pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_AMD_FEATURE_EDX_APIC))
910 || ( pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1 /* x2APIC */
911 && (pVM->cpum.s.aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_X2APIC)))
912 {
913 *puValue = pVCpu->cpum.s.Guest.msrApicBase;
914 }
915 else
916 {
917 *puValue = 0;
918 rc = VERR_CPUM_RAISE_GP_0;
919 }
920 break;
921 }
922
923 case MSR_IA32_CR_PAT:
924 *puValue = pVCpu->cpum.s.Guest.msrPAT;
925 break;
926
927 case MSR_IA32_SYSENTER_CS:
928 *puValue = pVCpu->cpum.s.Guest.SysEnter.cs;
929 break;
930
931 case MSR_IA32_SYSENTER_EIP:
932 *puValue = pVCpu->cpum.s.Guest.SysEnter.eip;
933 break;
934
935 case MSR_IA32_SYSENTER_ESP:
936 *puValue = pVCpu->cpum.s.Guest.SysEnter.esp;
937 break;
938
939 case MSR_IA32_MTRR_CAP:
940 {
941 /* This is currently a bit weird. :-) */
942 uint8_t const cVariableRangeRegs = 0;
943 bool const fSystemManagementRangeRegisters = false;
944 bool const fFixedRangeRegisters = false;
945 bool const fWriteCombiningType = false;
946 *puValue = cVariableRangeRegs
947 | (fFixedRangeRegisters ? RT_BIT_64(8) : 0)
948 | (fWriteCombiningType ? RT_BIT_64(10) : 0)
949 | (fSystemManagementRangeRegisters ? RT_BIT_64(11) : 0);
950 break;
951 }
952
953 case IA32_MTRR_PHYSBASE0: case IA32_MTRR_PHYSMASK0:
954 case IA32_MTRR_PHYSBASE1: case IA32_MTRR_PHYSMASK1:
955 case IA32_MTRR_PHYSBASE2: case IA32_MTRR_PHYSMASK2:
956 case IA32_MTRR_PHYSBASE3: case IA32_MTRR_PHYSMASK3:
957 case IA32_MTRR_PHYSBASE4: case IA32_MTRR_PHYSMASK4:
958 case IA32_MTRR_PHYSBASE5: case IA32_MTRR_PHYSMASK5:
959 case IA32_MTRR_PHYSBASE6: case IA32_MTRR_PHYSMASK6:
960 case IA32_MTRR_PHYSBASE7: case IA32_MTRR_PHYSMASK7:
961 /** @todo implement variable MTRRs. */
962 *puValue = 0;
963 break;
964#if 0 /** @todo newer CPUs have more, figure since when and do selective GP(). */
965 case IA32_MTRR_PHYSBASE8: case IA32_MTRR_PHYSMASK8:
966 case IA32_MTRR_PHYSBASE9: case IA32_MTRR_PHYSMASK9:
967 *puValue = 0;
968 break;
969#endif
970
971 case MSR_IA32_MTRR_DEF_TYPE:
972 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType;
973 break;
974
975 case IA32_MTRR_FIX64K_00000:
976 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix64K_00000;
977 break;
978 case IA32_MTRR_FIX16K_80000:
979 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_80000;
980 break;
981 case IA32_MTRR_FIX16K_A0000:
982 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_A0000;
983 break;
984 case IA32_MTRR_FIX4K_C0000:
985 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C0000;
986 break;
987 case IA32_MTRR_FIX4K_C8000:
988 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C8000;
989 break;
990 case IA32_MTRR_FIX4K_D0000:
991 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D0000;
992 break;
993 case IA32_MTRR_FIX4K_D8000:
994 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D8000;
995 break;
996 case IA32_MTRR_FIX4K_E0000:
997 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E0000;
998 break;
999 case IA32_MTRR_FIX4K_E8000:
1000 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E8000;
1001 break;
1002 case IA32_MTRR_FIX4K_F0000:
1003 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F0000;
1004 break;
1005 case IA32_MTRR_FIX4K_F8000:
1006 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F8000;
1007 break;
1008
1009 case MSR_K6_EFER:
1010 *puValue = pVCpu->cpum.s.Guest.msrEFER;
1011 break;
1012
1013 case MSR_K8_SF_MASK:
1014 *puValue = pVCpu->cpum.s.Guest.msrSFMASK;
1015 break;
1016
1017 case MSR_K6_STAR:
1018 *puValue = pVCpu->cpum.s.Guest.msrSTAR;
1019 break;
1020
1021 case MSR_K8_LSTAR:
1022 *puValue = pVCpu->cpum.s.Guest.msrLSTAR;
1023 break;
1024
1025 case MSR_K8_CSTAR:
1026 *puValue = pVCpu->cpum.s.Guest.msrCSTAR;
1027 break;
1028
1029 case MSR_K8_FS_BASE:
1030 *puValue = pVCpu->cpum.s.Guest.fs.u64Base;
1031 break;
1032
1033 case MSR_K8_GS_BASE:
1034 *puValue = pVCpu->cpum.s.Guest.gs.u64Base;
1035 break;
1036
1037 case MSR_K8_KERNEL_GS_BASE:
1038 *puValue = pVCpu->cpum.s.Guest.msrKERNELGSBASE;
1039 break;
1040
1041 case MSR_K8_TSC_AUX:
1042 *puValue = pVCpu->cpum.s.GuestMsrs.msr.TscAux;
1043 break;
1044
1045 case MSR_IA32_PERF_STATUS:
1046 /** @todo could really be not exactly correct, maybe use host's values
1047 * Apple code indicates that we should use CPU Hz / 1.333MHz here. */
1048 /** @todo Where are the specs implemented here found? */
1049 *puValue = UINT64_C(1000) /* TSC increment by tick */
1050 | ((uint64_t)u8Multiplier << 24) /* CPU multiplier (aka bus ratio) min */
1051 | ((uint64_t)u8Multiplier << 40) /* CPU multiplier (aka bus ratio) max */;
1052 break;
1053
1054 case MSR_IA32_FSB_CLOCK_STS:
1055 /*
1056 * Encoded as:
1057 * 0 - 266
1058 * 1 - 133
1059 * 2 - 200
1060 * 3 - return 166
1061 * 5 - return 100
1062 */
1063 *puValue = (2 << 4);
1064 break;
1065
1066 case MSR_IA32_PLATFORM_INFO:
1067 *puValue = ((uint32_t)u8Multiplier << 8) /* Flex ratio max */
1068 | ((uint64_t)u8Multiplier << 40) /* Flex ratio min */;
1069 break;
1070
1071 case MSR_IA32_THERM_STATUS:
1072 /* CPU temperature relative to TCC, to actually activate, CPUID leaf 6 EAX[0] must be set */
1073 *puValue = RT_BIT(31) /* validity bit */
1074 | (UINT64_C(20) << 16) /* degrees till TCC */;
1075 break;
1076
1077 case MSR_IA32_MISC_ENABLE:
1078#if 0
1079 /* Needs to be tested more before enabling. */
1080 *puValue = pVCpu->cpum.s.GuestMsr.msr.miscEnable;
1081#else
1082 /* Currenty we don't allow guests to modify enable MSRs. */
1083 *puValue = MSR_IA32_MISC_ENABLE_FAST_STRINGS /* by default */;
1084
1085 if ((pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR) != 0)
1086
1087 *puValue |= MSR_IA32_MISC_ENABLE_MONITOR /* if mwait/monitor available */;
1088 /** @todo: add more cpuid-controlled features this way. */
1089#endif
1090 break;
1091
1092 /** @todo virtualize DEBUGCTL and relatives */
1093 case MSR_IA32_DEBUGCTL:
1094 *puValue = 0;
1095 break;
1096
1097#if 0 /*def IN_RING0 */
1098 case MSR_IA32_PLATFORM_ID:
1099 case MSR_IA32_BIOS_SIGN_ID:
1100 if (CPUMGetCPUVendor(pVM) == CPUMCPUVENDOR_INTEL)
1101 {
1102 /* Available since the P6 family. VT-x implies that this feature is present. */
1103 if (idMsr == MSR_IA32_PLATFORM_ID)
1104 *puValue = ASMRdMsr(MSR_IA32_PLATFORM_ID);
1105 else if (idMsr == MSR_IA32_BIOS_SIGN_ID)
1106 *puValue = ASMRdMsr(MSR_IA32_BIOS_SIGN_ID);
1107 break;
1108 }
1109 /* no break */
1110#endif
1111 /*
1112 * The BIOS_SIGN_ID MSR and MSR_IA32_MCP_CAP et al exist on AMD64 as
1113 * well, at least bulldozer have them. Windows 7 is querying them.
1114 * XP has been observed querying MSR_IA32_MC0_CTL.
1115 */
1116 case MSR_IA32_BIOS_SIGN_ID: /* fam/mod >= 6_01 */
1117 case MSR_IA32_MCG_CAP: /* fam/mod >= 6_01 */
1118 case MSR_IA32_MCG_STATUS: /* indicated as not present in CAP */
1119 /*case MSR_IA32_MCG_CTRL: - indicated as not present in CAP */
1120 case MSR_IA32_MC0_CTL:
1121 case MSR_IA32_MC0_STATUS:
1122 *puValue = 0;
1123 break;
1124
1125
1126 /*
1127 * Intel specifics MSRs:
1128 */
1129 case MSR_P5_MC_ADDR:
1130 case MSR_P5_MC_TYPE:
1131 case MSR_P4_LASTBRANCH_TOS: /** @todo Are these branch regs still here on more recent CPUs? The documentation doesn't mention them for several archs. */
1132 case MSR_P4_LASTBRANCH_0:
1133 case MSR_P4_LASTBRANCH_1:
1134 case MSR_P4_LASTBRANCH_2:
1135 case MSR_P4_LASTBRANCH_3:
1136 case MSR_IA32_PERFEVTSEL0: /* NetWare 6.5 wants the these four. (Bet on AMD as well.) */
1137 case MSR_IA32_PERFEVTSEL1:
1138 case MSR_IA32_PMC0:
1139 case MSR_IA32_PMC1:
1140 case MSR_IA32_PLATFORM_ID: /* fam/mod >= 6_01 */
1141 case MSR_IA32_MPERF: /* intel_pstate depends on this but does a validation test */
1142 case MSR_IA32_APERF: /* intel_pstate depends on this but does a validation test */
1143 /*case MSR_IA32_BIOS_UPDT_TRIG: - write-only? */
1144 case MSR_RAPL_POWER_UNIT:
1145 case MSR_BBL_CR_CTL3: /* ca. core arch? */
1146 case MSR_PKG_CST_CONFIG_CONTROL: /* Nahalem, Sandy Bridge */
1147 case MSR_CORE_THREAD_COUNT: /* Apple queries this. */
1148 case MSR_FLEX_RATIO: /* Apple queries this. */
1149 *puValue = 0;
1150 if (CPUMGetGuestCpuVendor(pVCpu->CTX_SUFF(pVM)) != CPUMCPUVENDOR_INTEL)
1151 {
1152 Log(("CPUM: MSR %#x is Intel, the virtual CPU isn't an Intel one -> #GP\n", idMsr));
1153 rc = VERR_CPUM_RAISE_GP_0;
1154 break;
1155 }
1156
1157 /* Provide more plausive values for some of them. */
1158 switch (idMsr)
1159 {
1160 case MSR_RAPL_POWER_UNIT:
1161 *puValue = RT_MAKE_U32_FROM_U8(3 /* power units (1/8 W)*/,
1162 16 /* 15.3 micro-Joules */,
1163 10 /* 976 microseconds increments */,
1164 0);
1165 break;
1166 case MSR_BBL_CR_CTL3:
1167 *puValue = RT_MAKE_U32_FROM_U8(1, /* bit 0 - L2 Hardware Enabled. (RO) */
1168 1, /* bit 8 - L2 Enabled (R/W). */
1169 0, /* bit 23 - L2 Not Present (RO). */
1170 0);
1171 break;
1172 case MSR_PKG_CST_CONFIG_CONTROL:
1173 *puValue = pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl;
1174 break;
1175 case MSR_CORE_THREAD_COUNT:
1176 {
1177 /** @todo restrict this to nehalem. */
1178 PVM pVM = pVCpu->CTX_SUFF(pVM); /* Note! Not sweating the 4-bit core count limit on westmere. */
1179 *puValue = (pVM->cCpus & 0xffff) | ((pVM->cCpus & 0xffff) << 16);
1180 break;
1181 }
1182
1183 case MSR_FLEX_RATIO:
1184 {
1185 /** @todo Check for P4, it's different there. Try find accurate specs. */
1186 *puValue = (uint32_t)u8Multiplier << 8;
1187 break;
1188 }
1189 }
1190 break;
1191
1192#if 0 /* Only on pentium CPUs! */
1193 /* Event counters, not supported. */
1194 case MSR_IA32_CESR:
1195 case MSR_IA32_CTR0:
1196 case MSR_IA32_CTR1:
1197 *puValue = 0;
1198 break;
1199#endif
1200
1201
1202 /*
1203 * AMD specific MSRs:
1204 */
1205 case MSR_K8_SYSCFG:
1206 case MSR_K8_INT_PENDING:
1207 case MSR_K8_NB_CFG: /* (All known values are 0 on reset.) */
1208 case MSR_K8_HWCR: /* Very interesting bits here. :) */
1209 case MSR_K8_VM_CR: /* Windows 8 */
1210 *puValue = 0;
1211 if (CPUMGetGuestCpuVendor(pVCpu->CTX_SUFF(pVM)) != CPUMCPUVENDOR_AMD)
1212 {
1213 Log(("CPUM: MSR %#x is AMD, the virtual CPU isn't an Intel one -> #GP\n", idMsr));
1214 return VERR_CPUM_RAISE_GP_0;
1215 }
1216 /* ignored */
1217 break;
1218
1219 default:
1220 /*
1221 * Hand the X2APIC range to PDM and the APIC.
1222 */
1223 if ( idMsr >= MSR_IA32_X2APIC_START
1224 && idMsr <= MSR_IA32_X2APIC_END)
1225 {
1226 rc = PDMApicReadMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, puValue);
1227 if (RT_SUCCESS(rc))
1228 rc = VINF_SUCCESS;
1229 else
1230 {
1231 *puValue = 0;
1232 rc = VERR_CPUM_RAISE_GP_0;
1233 }
1234 }
1235 else
1236 {
1237 *puValue = 0;
1238 rc = VERR_CPUM_RAISE_GP_0;
1239 }
1240 break;
1241 }
1242
1243 return rc;
1244}
1245
1246
1247/**
1248 * Query an MSR.
1249 *
1250 * The caller is responsible for checking privilege if the call is the result
1251 * of a RDMSR instruction. We'll do the rest.
1252 *
1253 * @retval VINF_SUCCESS on success.
1254 * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR), the caller is
1255 * expected to take the appropriate actions. @a *puValue is set to 0.
1256 * @param pVCpu Pointer to the VMCPU.
1257 * @param idMsr The MSR.
1258 * @param puValue Where to return the value.
1259 *
1260 * @remarks This will always return the right values, even when we're in the
1261 * recompiler.
1262 */
1263VMMDECL(int) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue)
1264{
1265 int rc = cpumQueryGuestMsrInt(pVCpu, idMsr, puValue);
1266 LogFlow(("CPUMQueryGuestMsr: %#x -> %llx rc=%d\n", idMsr, *puValue, rc));
1267 return rc;
1268}
1269
1270
1271/**
1272 * Sets the MSR.
1273 *
1274 * The caller is responsible for checking privilege if the call is the result
1275 * of a WRMSR instruction. We'll do the rest.
1276 *
1277 * @retval VINF_SUCCESS on success.
1278 * @retval VERR_CPUM_RAISE_GP_0 on failure, the caller is expected to take the
1279 * appropriate actions.
1280 *
1281 * @param pVCpu Pointer to the VMCPU.
1282 * @param idMsr The MSR id.
1283 * @param uValue The value to set.
1284 *
1285 * @remarks Everyone changing MSR values, including the recompiler, shall do it
1286 * by calling this method. This makes sure we have current values and
1287 * that we trigger all the right actions when something changes.
1288 */
1289VMMDECL(int) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue)
1290{
1291 LogFlow(("CPUSetGuestMsr: %#x <- %#llx\n", idMsr, uValue));
1292
1293 /*
1294 * If we don't indicate MSR support in the CPUID feature bits, indicate
1295 * that a #GP(0) should be raised.
1296 */
1297 if (!(pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_MSR))
1298 return VERR_CPUM_RAISE_GP_0; /** @todo isn't \#UD more correct if not supported? */
1299
1300 int rc = VINF_SUCCESS;
1301 switch (idMsr)
1302 {
1303 case MSR_IA32_MISC_ENABLE:
1304 pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = uValue;
1305 break;
1306
1307 case MSR_IA32_TSC:
1308 TMCpuTickSet(pVCpu->CTX_SUFF(pVM), pVCpu, uValue);
1309 break;
1310
1311 case MSR_IA32_APICBASE:
1312 rc = PDMApicSetBase(pVCpu, uValue);
1313 if (rc != VINF_SUCCESS)
1314 rc = VERR_CPUM_RAISE_GP_0;
1315 break;
1316
1317 case MSR_IA32_CR_PAT:
1318 pVCpu->cpum.s.Guest.msrPAT = uValue;
1319 break;
1320
1321 case MSR_IA32_SYSENTER_CS:
1322 pVCpu->cpum.s.Guest.SysEnter.cs = uValue & 0xffff; /* 16 bits selector */
1323 break;
1324
1325 case MSR_IA32_SYSENTER_EIP:
1326 pVCpu->cpum.s.Guest.SysEnter.eip = uValue;
1327 break;
1328
1329 case MSR_IA32_SYSENTER_ESP:
1330 pVCpu->cpum.s.Guest.SysEnter.esp = uValue;
1331 break;
1332
1333 case MSR_IA32_MTRR_CAP:
1334 return VERR_CPUM_RAISE_GP_0;
1335
1336 case MSR_IA32_MTRR_DEF_TYPE:
1337 if ( (uValue & UINT64_C(0xfffffffffffff300))
1338 || ( (uValue & 0xff) != 0
1339 && (uValue & 0xff) != 1
1340 && (uValue & 0xff) != 4
1341 && (uValue & 0xff) != 5
1342 && (uValue & 0xff) != 6) )
1343 {
1344 Log(("CPUM: MSR_IA32_MTRR_DEF_TYPE: #GP(0) - writing reserved value (%#llx)\n", uValue));
1345 return VERR_CPUM_RAISE_GP_0;
1346 }
1347 pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType = uValue;
1348 break;
1349
1350 case IA32_MTRR_PHYSBASE0: case IA32_MTRR_PHYSMASK0:
1351 case IA32_MTRR_PHYSBASE1: case IA32_MTRR_PHYSMASK1:
1352 case IA32_MTRR_PHYSBASE2: case IA32_MTRR_PHYSMASK2:
1353 case IA32_MTRR_PHYSBASE3: case IA32_MTRR_PHYSMASK3:
1354 case IA32_MTRR_PHYSBASE4: case IA32_MTRR_PHYSMASK4:
1355 case IA32_MTRR_PHYSBASE5: case IA32_MTRR_PHYSMASK5:
1356 case IA32_MTRR_PHYSBASE6: case IA32_MTRR_PHYSMASK6:
1357 case IA32_MTRR_PHYSBASE7: case IA32_MTRR_PHYSMASK7:
1358 /** @todo implement variable MTRRs. */
1359 break;
1360#if 0 /** @todo newer CPUs have more, figure since when and do selective GP(). */
1361 case IA32_MTRR_PHYSBASE8: case IA32_MTRR_PHYSMASK8:
1362 case IA32_MTRR_PHYSBASE9: case IA32_MTRR_PHYSMASK9:
1363 break;
1364#endif
1365
1366 case IA32_MTRR_FIX64K_00000:
1367 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix64K_00000 = uValue;
1368 break;
1369 case IA32_MTRR_FIX16K_80000:
1370 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_80000 = uValue;
1371 break;
1372 case IA32_MTRR_FIX16K_A0000:
1373 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_A0000 = uValue;
1374 break;
1375 case IA32_MTRR_FIX4K_C0000:
1376 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C0000 = uValue;
1377 break;
1378 case IA32_MTRR_FIX4K_C8000:
1379 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C8000 = uValue;
1380 break;
1381 case IA32_MTRR_FIX4K_D0000:
1382 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D0000 = uValue;
1383 break;
1384 case IA32_MTRR_FIX4K_D8000:
1385 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D8000 = uValue;
1386 break;
1387 case IA32_MTRR_FIX4K_E0000:
1388 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E0000 = uValue;
1389 break;
1390 case IA32_MTRR_FIX4K_E8000:
1391 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E8000 = uValue;
1392 break;
1393 case IA32_MTRR_FIX4K_F0000:
1394 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F0000 = uValue;
1395 break;
1396 case IA32_MTRR_FIX4K_F8000:
1397 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F8000 = uValue;
1398 break;
1399
1400 /*
1401 * AMD64 MSRs.
1402 */
1403 case MSR_K6_EFER:
1404 {
1405 PVM pVM = pVCpu->CTX_SUFF(pVM);
1406 uint64_t const uOldEFER = pVCpu->cpum.s.Guest.msrEFER;
1407 uint32_t const fExtFeatures = pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1408 ? pVM->cpum.s.aGuestCpuIdExt[1].edx
1409 : 0;
1410 uint64_t fMask = 0;
1411
1412 /* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
1413 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_NX)
1414 fMask |= MSR_K6_EFER_NXE;
1415 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
1416 fMask |= MSR_K6_EFER_LME;
1417 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
1418 fMask |= MSR_K6_EFER_SCE;
1419 if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1420 fMask |= MSR_K6_EFER_FFXSR;
1421
1422 /* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if
1423 paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1424 if ( (uOldEFER & MSR_K6_EFER_LME) != (uValue & fMask & MSR_K6_EFER_LME)
1425 && (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG))
1426 {
1427 Log(("CPUM: Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
1428 return VERR_CPUM_RAISE_GP_0;
1429 }
1430
1431 /* There are a few more: e.g. MSR_K6_EFER_LMSLE */
1432 AssertMsg(!(uValue & ~(MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA /* ignored anyway */ | MSR_K6_EFER_SCE | MSR_K6_EFER_FFXSR)),
1433 ("Unexpected value %RX64\n", uValue));
1434 pVCpu->cpum.s.Guest.msrEFER = (uOldEFER & ~fMask) | (uValue & fMask);
1435
1436 /* AMD64 Architecture Programmer's Manual: 15.15 TLB Control; flush the TLB
1437 if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
1438 if ( (uOldEFER & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA))
1439 != (pVCpu->cpum.s.Guest.msrEFER & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA)))
1440 {
1441 /// @todo PGMFlushTLB(pVCpu, cr3, true /*fGlobal*/);
1442 HMFlushTLB(pVCpu);
1443
1444 /* Notify PGM about NXE changes. */
1445 if ( (uOldEFER & MSR_K6_EFER_NXE)
1446 != (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE))
1447 PGMNotifyNxeChanged(pVCpu, !(uOldEFER & MSR_K6_EFER_NXE));
1448 }
1449 break;
1450 }
1451
1452 case MSR_K8_SF_MASK:
1453 pVCpu->cpum.s.Guest.msrSFMASK = uValue;
1454 break;
1455
1456 case MSR_K6_STAR:
1457 pVCpu->cpum.s.Guest.msrSTAR = uValue;
1458 break;
1459
1460 case MSR_K8_LSTAR:
1461 pVCpu->cpum.s.Guest.msrLSTAR = uValue;
1462 break;
1463
1464 case MSR_K8_CSTAR:
1465 pVCpu->cpum.s.Guest.msrCSTAR = uValue;
1466 break;
1467
1468 case MSR_K8_FS_BASE:
1469 pVCpu->cpum.s.Guest.fs.u64Base = uValue;
1470 break;
1471
1472 case MSR_K8_GS_BASE:
1473 pVCpu->cpum.s.Guest.gs.u64Base = uValue;
1474 break;
1475
1476 case MSR_K8_KERNEL_GS_BASE:
1477 pVCpu->cpum.s.Guest.msrKERNELGSBASE = uValue;
1478 break;
1479
1480 case MSR_K8_TSC_AUX:
1481 pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
1482 break;
1483
1484 case MSR_IA32_DEBUGCTL:
1485 /** @todo virtualize DEBUGCTL and relatives */
1486 break;
1487
1488
1489 /*
1490 * Intel specifics MSRs:
1491 */
1492 /*case MSR_IA32_PLATFORM_ID: - read-only */
1493 case MSR_IA32_BIOS_SIGN_ID: /* fam/mod >= 6_01 */
1494 case MSR_IA32_BIOS_UPDT_TRIG: /* fam/mod >= 6_01 */
1495 /*case MSR_IA32_MCP_CAP: - read-only */
1496 /*case MSR_IA32_MCG_STATUS: - read-only */
1497 /*case MSR_IA32_MCG_CTRL: - indicated as not present in CAP */
1498 /*case MSR_IA32_MC0_CTL: - read-only? */
1499 /*case MSR_IA32_MC0_STATUS: - read-only? */
1500 case MSR_PKG_CST_CONFIG_CONTROL:
1501 if (CPUMGetGuestCpuVendor(pVCpu->CTX_SUFF(pVM)) != CPUMCPUVENDOR_INTEL)
1502 {
1503 Log(("CPUM: MSR %#x is Intel, the virtual CPU isn't an Intel one -> #GP\n", idMsr));
1504 return VERR_CPUM_RAISE_GP_0;
1505 }
1506
1507 switch (idMsr)
1508 {
1509 case MSR_PKG_CST_CONFIG_CONTROL:
1510 {
1511 if (pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl & RT_BIT_64(15))
1512 {
1513 Log(("MSR_PKG_CST_CONFIG_CONTROL: Write protected -> #GP\n"));
1514 return VERR_CPUM_RAISE_GP_0;
1515 }
1516 static uint64_t s_fMask = UINT64_C(0x01f08407); /** @todo Only Nehalem has 24; Only Sandy has 27 and 28. */
1517 static uint64_t s_fGpInvalid = UINT64_C(0xffffffff00ff0000); /** @todo figure out exactly what's off limits. */
1518 if ((uValue & s_fGpInvalid) || (uValue & 7) >= 5)
1519 {
1520 Log(("MSR_PKG_CST_CONFIG_CONTROL: Invalid value %#llx -> #GP\n", uValue));
1521 return VERR_CPUM_RAISE_GP_0;
1522 }
1523 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = uValue & s_fMask;
1524 break;
1525 }
1526
1527 }
1528 /* ignored */
1529 break;
1530
1531 /*
1532 * AMD specific MSRs:
1533 */
1534 case MSR_K8_SYSCFG: /** @todo can be written, but we ignore that for now. */
1535 case MSR_K8_INT_PENDING: /** @todo can be written, but we ignore that for now. */
1536 case MSR_K8_NB_CFG: /** @todo can be written; the apicid swapping might be used and would need saving, but probably unnecessary. */
1537 if (CPUMGetGuestCpuVendor(pVCpu->CTX_SUFF(pVM)) != CPUMCPUVENDOR_AMD)
1538 {
1539 Log(("CPUM: MSR %#x is AMD, the virtual CPU isn't an Intel one -> #GP\n", idMsr));
1540 return VERR_CPUM_RAISE_GP_0;
1541 }
1542 /* ignored */
1543 break;
1544
1545
1546 default:
1547 /*
1548 * Hand the X2APIC range to PDM and the APIC.
1549 */
1550 if ( idMsr >= MSR_IA32_X2APIC_START
1551 && idMsr <= MSR_IA32_X2APIC_END)
1552 {
1553 rc = PDMApicWriteMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, uValue);
1554 if (rc != VINF_SUCCESS)
1555 rc = VERR_CPUM_RAISE_GP_0;
1556 }
1557 else
1558 {
1559 /* We should actually trigger a #GP here, but don't as that might cause more trouble. */
1560 /** @todo rc = VERR_CPUM_RAISE_GP_0 */
1561 Log(("CPUMSetGuestMsr: Unknown MSR %#x attempted set to %#llx\n", idMsr, uValue));
1562 }
1563 break;
1564 }
1565 return rc;
1566}
1567
1568
1569VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
1570{
1571 if (pcbLimit)
1572 *pcbLimit = pVCpu->cpum.s.Guest.idtr.cbIdt;
1573 return pVCpu->cpum.s.Guest.idtr.pIdt;
1574}
1575
1576
1577VMMDECL(RTSEL) CPUMGetGuestTR(PVMCPU pVCpu, PCPUMSELREGHID pHidden)
1578{
1579 if (pHidden)
1580 *pHidden = pVCpu->cpum.s.Guest.tr;
1581 return pVCpu->cpum.s.Guest.tr.Sel;
1582}
1583
1584
1585VMMDECL(RTSEL) CPUMGetGuestCS(PVMCPU pVCpu)
1586{
1587 return pVCpu->cpum.s.Guest.cs.Sel;
1588}
1589
1590
1591VMMDECL(RTSEL) CPUMGetGuestDS(PVMCPU pVCpu)
1592{
1593 return pVCpu->cpum.s.Guest.ds.Sel;
1594}
1595
1596
1597VMMDECL(RTSEL) CPUMGetGuestES(PVMCPU pVCpu)
1598{
1599 return pVCpu->cpum.s.Guest.es.Sel;
1600}
1601
1602
1603VMMDECL(RTSEL) CPUMGetGuestFS(PVMCPU pVCpu)
1604{
1605 return pVCpu->cpum.s.Guest.fs.Sel;
1606}
1607
1608
1609VMMDECL(RTSEL) CPUMGetGuestGS(PVMCPU pVCpu)
1610{
1611 return pVCpu->cpum.s.Guest.gs.Sel;
1612}
1613
1614
1615VMMDECL(RTSEL) CPUMGetGuestSS(PVMCPU pVCpu)
1616{
1617 return pVCpu->cpum.s.Guest.ss.Sel;
1618}
1619
1620
1621VMMDECL(RTSEL) CPUMGetGuestLDTR(PVMCPU pVCpu)
1622{
1623 return pVCpu->cpum.s.Guest.ldtr.Sel;
1624}
1625
1626
1627VMMDECL(RTSEL) CPUMGetGuestLdtrEx(PVMCPU pVCpu, uint64_t *pGCPtrBase, uint32_t *pcbLimit)
1628{
1629 *pGCPtrBase = pVCpu->cpum.s.Guest.ldtr.u64Base;
1630 *pcbLimit = pVCpu->cpum.s.Guest.ldtr.u32Limit;
1631 return pVCpu->cpum.s.Guest.ldtr.Sel;
1632}
1633
1634
1635VMMDECL(uint64_t) CPUMGetGuestCR0(PVMCPU pVCpu)
1636{
1637 return pVCpu->cpum.s.Guest.cr0;
1638}
1639
1640
1641VMMDECL(uint64_t) CPUMGetGuestCR2(PVMCPU pVCpu)
1642{
1643 return pVCpu->cpum.s.Guest.cr2;
1644}
1645
1646
1647VMMDECL(uint64_t) CPUMGetGuestCR3(PVMCPU pVCpu)
1648{
1649 return pVCpu->cpum.s.Guest.cr3;
1650}
1651
1652
1653VMMDECL(uint64_t) CPUMGetGuestCR4(PVMCPU pVCpu)
1654{
1655 return pVCpu->cpum.s.Guest.cr4;
1656}
1657
1658
1659VMMDECL(uint64_t) CPUMGetGuestCR8(PVMCPU pVCpu)
1660{
1661 uint64_t u64;
1662 int rc = CPUMGetGuestCRx(pVCpu, DISCREG_CR8, &u64);
1663 if (RT_FAILURE(rc))
1664 u64 = 0;
1665 return u64;
1666}
1667
1668
1669VMMDECL(void) CPUMGetGuestGDTR(PVMCPU pVCpu, PVBOXGDTR pGDTR)
1670{
1671 *pGDTR = pVCpu->cpum.s.Guest.gdtr;
1672}
1673
1674
1675VMMDECL(uint32_t) CPUMGetGuestEIP(PVMCPU pVCpu)
1676{
1677 return pVCpu->cpum.s.Guest.eip;
1678}
1679
1680
1681VMMDECL(uint64_t) CPUMGetGuestRIP(PVMCPU pVCpu)
1682{
1683 return pVCpu->cpum.s.Guest.rip;
1684}
1685
1686
1687VMMDECL(uint32_t) CPUMGetGuestEAX(PVMCPU pVCpu)
1688{
1689 return pVCpu->cpum.s.Guest.eax;
1690}
1691
1692
1693VMMDECL(uint32_t) CPUMGetGuestEBX(PVMCPU pVCpu)
1694{
1695 return pVCpu->cpum.s.Guest.ebx;
1696}
1697
1698
1699VMMDECL(uint32_t) CPUMGetGuestECX(PVMCPU pVCpu)
1700{
1701 return pVCpu->cpum.s.Guest.ecx;
1702}
1703
1704
1705VMMDECL(uint32_t) CPUMGetGuestEDX(PVMCPU pVCpu)
1706{
1707 return pVCpu->cpum.s.Guest.edx;
1708}
1709
1710
1711VMMDECL(uint32_t) CPUMGetGuestESI(PVMCPU pVCpu)
1712{
1713 return pVCpu->cpum.s.Guest.esi;
1714}
1715
1716
1717VMMDECL(uint32_t) CPUMGetGuestEDI(PVMCPU pVCpu)
1718{
1719 return pVCpu->cpum.s.Guest.edi;
1720}
1721
1722
1723VMMDECL(uint32_t) CPUMGetGuestESP(PVMCPU pVCpu)
1724{
1725 return pVCpu->cpum.s.Guest.esp;
1726}
1727
1728
1729VMMDECL(uint32_t) CPUMGetGuestEBP(PVMCPU pVCpu)
1730{
1731 return pVCpu->cpum.s.Guest.ebp;
1732}
1733
1734
1735VMMDECL(uint32_t) CPUMGetGuestEFlags(PVMCPU pVCpu)
1736{
1737 return pVCpu->cpum.s.Guest.eflags.u32;
1738}
1739
1740
1741VMMDECL(int) CPUMGetGuestCRx(PVMCPU pVCpu, unsigned iReg, uint64_t *pValue)
1742{
1743 switch (iReg)
1744 {
1745 case DISCREG_CR0:
1746 *pValue = pVCpu->cpum.s.Guest.cr0;
1747 break;
1748
1749 case DISCREG_CR2:
1750 *pValue = pVCpu->cpum.s.Guest.cr2;
1751 break;
1752
1753 case DISCREG_CR3:
1754 *pValue = pVCpu->cpum.s.Guest.cr3;
1755 break;
1756
1757 case DISCREG_CR4:
1758 *pValue = pVCpu->cpum.s.Guest.cr4;
1759 break;
1760
1761 case DISCREG_CR8:
1762 {
1763 uint8_t u8Tpr;
1764 int rc = PDMApicGetTPR(pVCpu, &u8Tpr, NULL /* pfPending */, NULL /* pu8PendingIrq */);
1765 if (RT_FAILURE(rc))
1766 {
1767 AssertMsg(rc == VERR_PDM_NO_APIC_INSTANCE, ("%Rrc\n", rc));
1768 *pValue = 0;
1769 return rc;
1770 }
1771 *pValue = u8Tpr >> 4; /* bits 7-4 contain the task priority that go in cr8, bits 3-0*/
1772 break;
1773 }
1774
1775 default:
1776 return VERR_INVALID_PARAMETER;
1777 }
1778 return VINF_SUCCESS;
1779}
1780
1781
1782VMMDECL(uint64_t) CPUMGetGuestDR0(PVMCPU pVCpu)
1783{
1784 return pVCpu->cpum.s.Guest.dr[0];
1785}
1786
1787
1788VMMDECL(uint64_t) CPUMGetGuestDR1(PVMCPU pVCpu)
1789{
1790 return pVCpu->cpum.s.Guest.dr[1];
1791}
1792
1793
1794VMMDECL(uint64_t) CPUMGetGuestDR2(PVMCPU pVCpu)
1795{
1796 return pVCpu->cpum.s.Guest.dr[2];
1797}
1798
1799
1800VMMDECL(uint64_t) CPUMGetGuestDR3(PVMCPU pVCpu)
1801{
1802 return pVCpu->cpum.s.Guest.dr[3];
1803}
1804
1805
1806VMMDECL(uint64_t) CPUMGetGuestDR6(PVMCPU pVCpu)
1807{
1808 return pVCpu->cpum.s.Guest.dr[6];
1809}
1810
1811
1812VMMDECL(uint64_t) CPUMGetGuestDR7(PVMCPU pVCpu)
1813{
1814 return pVCpu->cpum.s.Guest.dr[7];
1815}
1816
1817
1818VMMDECL(int) CPUMGetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t *pValue)
1819{
1820 AssertReturn(iReg <= DISDREG_DR7, VERR_INVALID_PARAMETER);
1821 /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
1822 if (iReg == 4 || iReg == 5)
1823 iReg += 2;
1824 *pValue = pVCpu->cpum.s.Guest.dr[iReg];
1825 return VINF_SUCCESS;
1826}
1827
1828
1829VMMDECL(uint64_t) CPUMGetGuestEFER(PVMCPU pVCpu)
1830{
1831 return pVCpu->cpum.s.Guest.msrEFER;
1832}
1833
1834
1835/**
1836 * Gets a CPUID leaf.
1837 *
1838 * @param pVCpu Pointer to the VMCPU.
1839 * @param iLeaf The CPUID leaf to get.
1840 * @param pEax Where to store the EAX value.
1841 * @param pEbx Where to store the EBX value.
1842 * @param pEcx Where to store the ECX value.
1843 * @param pEdx Where to store the EDX value.
1844 */
1845VMMDECL(void) CPUMGetGuestCpuId(PVMCPU pVCpu, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx)
1846{
1847 PVM pVM = pVCpu->CTX_SUFF(pVM);
1848
1849 PCCPUMCPUID pCpuId;
1850 if (iLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
1851 pCpuId = &pVM->cpum.s.aGuestCpuIdStd[iLeaf];
1852 else if (iLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
1853 pCpuId = &pVM->cpum.s.aGuestCpuIdExt[iLeaf - UINT32_C(0x80000000)];
1854 else if ( iLeaf - UINT32_C(0x40000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdHyper)
1855 && (pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_HVP))
1856 pCpuId = &pVM->cpum.s.aGuestCpuIdHyper[iLeaf - UINT32_C(0x40000000)]; /* Only report if HVP bit set. */
1857 else if (iLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
1858 pCpuId = &pVM->cpum.s.aGuestCpuIdCentaur[iLeaf - UINT32_C(0xc0000000)];
1859 else
1860 pCpuId = &pVM->cpum.s.GuestCpuIdDef;
1861
1862 uint32_t cCurrentCacheIndex = *pEcx;
1863
1864 *pEax = pCpuId->eax;
1865 *pEbx = pCpuId->ebx;
1866 *pEcx = pCpuId->ecx;
1867 *pEdx = pCpuId->edx;
1868
1869 if ( iLeaf == 1)
1870 {
1871 /* Bits 31-24: Initial APIC ID */
1872 Assert(pVCpu->idCpu <= 255);
1873 *pEbx |= (pVCpu->idCpu << 24);
1874 }
1875
1876 if ( iLeaf == 4
1877 && cCurrentCacheIndex < 3
1878 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
1879 {
1880 uint32_t type, level, sharing, linesize,
1881 partitions, associativity, sets, cores;
1882
1883 /* For type: 1 - data cache, 2 - i-cache, 3 - unified */
1884 partitions = 1;
1885 /* Those are only to shut up compiler, as they will always
1886 get overwritten, and compiler should be able to figure that out */
1887 sets = associativity = sharing = level = 1;
1888 cores = pVM->cCpus > 32 ? 32 : pVM->cCpus;
1889 switch (cCurrentCacheIndex)
1890 {
1891 case 0:
1892 type = 1;
1893 level = 1;
1894 sharing = 1;
1895 linesize = 64;
1896 associativity = 8;
1897 sets = 64;
1898 break;
1899 case 1:
1900 level = 1;
1901 type = 2;
1902 sharing = 1;
1903 linesize = 64;
1904 associativity = 8;
1905 sets = 64;
1906 break;
1907 default: /* shut up gcc.*/
1908 AssertFailed();
1909 case 2:
1910 level = 2;
1911 type = 3;
1912 sharing = cores; /* our L2 cache is modelled as shared between all cores */
1913 linesize = 64;
1914 associativity = 24;
1915 sets = 4096;
1916 break;
1917 }
1918
1919 *pEax |= ((cores - 1) << 26) |
1920 ((sharing - 1) << 14) |
1921 (level << 5) |
1922 1;
1923 *pEbx = (linesize - 1) |
1924 ((partitions - 1) << 12) |
1925 ((associativity - 1) << 22); /* -1 encoding */
1926 *pEcx = sets - 1;
1927 }
1928
1929 Log2(("CPUMGetGuestCpuId: iLeaf=%#010x %RX32 %RX32 %RX32 %RX32\n", iLeaf, *pEax, *pEbx, *pEcx, *pEdx));
1930}
1931
1932/**
1933 * Gets a number of standard CPUID leafs.
1934 *
1935 * @returns Number of leafs.
1936 * @param pVM Pointer to the VM.
1937 * @remark Intended for PATM.
1938 */
1939VMMDECL(uint32_t) CPUMGetGuestCpuIdStdMax(PVM pVM)
1940{
1941 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd);
1942}
1943
1944
1945/**
1946 * Gets a number of extended CPUID leafs.
1947 *
1948 * @returns Number of leafs.
1949 * @param pVM Pointer to the VM.
1950 * @remark Intended for PATM.
1951 */
1952VMMDECL(uint32_t) CPUMGetGuestCpuIdExtMax(PVM pVM)
1953{
1954 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt);
1955}
1956
1957
1958/**
1959 * Gets a number of centaur CPUID leafs.
1960 *
1961 * @returns Number of leafs.
1962 * @param pVM Pointer to the VM.
1963 * @remark Intended for PATM.
1964 */
1965VMMDECL(uint32_t) CPUMGetGuestCpuIdCentaurMax(PVM pVM)
1966{
1967 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur);
1968}
1969
1970
1971/**
1972 * Sets a CPUID feature bit.
1973 *
1974 * @param pVM Pointer to the VM.
1975 * @param enmFeature The feature to set.
1976 */
1977VMMDECL(void) CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
1978{
1979 switch (enmFeature)
1980 {
1981 /*
1982 * Set the APIC bit in both feature masks.
1983 */
1984 case CPUMCPUIDFEATURE_APIC:
1985 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1986 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_APIC;
1987 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1988 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1989 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_APIC;
1990 LogRel(("CPUM: SetGuestCpuIdFeature: Enabled APIC\n"));
1991 break;
1992
1993 /*
1994 * Set the x2APIC bit in the standard feature mask.
1995 */
1996 case CPUMCPUIDFEATURE_X2APIC:
1997 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1998 pVM->cpum.s.aGuestCpuIdStd[1].ecx |= X86_CPUID_FEATURE_ECX_X2APIC;
1999 LogRel(("CPUM: SetGuestCpuIdFeature: Enabled x2APIC\n"));
2000 break;
2001
2002 /*
2003 * Set the sysenter/sysexit bit in the standard feature mask.
2004 * Assumes the caller knows what it's doing! (host must support these)
2005 */
2006 case CPUMCPUIDFEATURE_SEP:
2007 {
2008 if (!(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_SEP))
2009 {
2010 AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
2011 return;
2012 }
2013
2014 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2015 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_SEP;
2016 LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSENTER/EXIT\n"));
2017 break;
2018 }
2019
2020 /*
2021 * Set the syscall/sysret bit in the extended feature mask.
2022 * Assumes the caller knows what it's doing! (host must support these)
2023 */
2024 case CPUMCPUIDFEATURE_SYSCALL:
2025 {
2026 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
2027 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_SYSCALL))
2028 {
2029#if HC_ARCH_BITS == 32
2030 /* X86_CPUID_EXT_FEATURE_EDX_SYSCALL not set it seems in 32 bits mode.
2031 * Even when the cpu is capable of doing so in 64 bits mode.
2032 */
2033 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
2034 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
2035 || !(ASMCpuId_EDX(1) & X86_CPUID_EXT_FEATURE_EDX_SYSCALL))
2036#endif
2037 {
2038 LogRel(("CPUM: WARNING! Can't turn on SYSCALL/SYSRET when the host doesn't support it!\n"));
2039 return;
2040 }
2041 }
2042 /* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
2043 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
2044 LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSCALL/RET\n"));
2045 break;
2046 }
2047
2048 /*
2049 * Set the PAE bit in both feature masks.
2050 * Assumes the caller knows what it's doing! (host must support these)
2051 */
2052 case CPUMCPUIDFEATURE_PAE:
2053 {
2054 if (!(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_PAE))
2055 {
2056 LogRel(("CPUM: WARNING! Can't turn on PAE when the host doesn't support it!\n"));
2057 return;
2058 }
2059
2060 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2061 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_PAE;
2062 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
2063 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
2064 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_PAE;
2065 LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAE\n"));
2066 break;
2067 }
2068
2069 /*
2070 * Set the LONG MODE bit in the extended feature mask.
2071 * Assumes the caller knows what it's doing! (host must support these)
2072 */
2073 case CPUMCPUIDFEATURE_LONG_MODE:
2074 {
2075 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
2076 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE))
2077 {
2078 LogRel(("CPUM: WARNING! Can't turn on LONG MODE when the host doesn't support it!\n"));
2079 return;
2080 }
2081
2082 /* Valid for both Intel and AMD. */
2083 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
2084 LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LONG MODE\n"));
2085 break;
2086 }
2087
2088 /*
2089 * Set the NX/XD bit in the extended feature mask.
2090 * Assumes the caller knows what it's doing! (host must support these)
2091 */
2092 case CPUMCPUIDFEATURE_NX:
2093 {
2094 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
2095 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_NX))
2096 {
2097 LogRel(("CPUM: WARNING! Can't turn on NX/XD when the host doesn't support it!\n"));
2098 return;
2099 }
2100
2101 /* Valid for both Intel and AMD. */
2102 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_NX;
2103 LogRel(("CPUM: SetGuestCpuIdFeature: Enabled NX\n"));
2104 break;
2105 }
2106
2107 /*
2108 * Set the LAHF/SAHF support in 64-bit mode.
2109 * Assumes the caller knows what it's doing! (host must support this)
2110 */
2111 case CPUMCPUIDFEATURE_LAHF:
2112 {
2113 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
2114 || !(ASMCpuId_ECX(0x80000001) & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF))
2115 {
2116 LogRel(("CPUM: WARNING! Can't turn on LAHF/SAHF when the host doesn't support it!\n"));
2117 return;
2118 }
2119
2120 /* Valid for both Intel and AMD. */
2121 pVM->cpum.s.aGuestCpuIdExt[1].ecx |= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
2122 LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
2123 break;
2124 }
2125
2126 case CPUMCPUIDFEATURE_PAT:
2127 {
2128 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2129 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_PAT;
2130 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
2131 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
2132 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_PAT;
2133 LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAT\n"));
2134 break;
2135 }
2136
2137 /*
2138 * Set the RDTSCP support bit.
2139 * Assumes the caller knows what it's doing! (host must support this)
2140 */
2141 case CPUMCPUIDFEATURE_RDTSCP:
2142 {
2143 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
2144 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
2145 || pVM->cpum.s.u8PortableCpuIdLevel > 0)
2146 {
2147 if (!pVM->cpum.s.u8PortableCpuIdLevel)
2148 LogRel(("CPUM: WARNING! Can't turn on RDTSCP when the host doesn't support it!\n"));
2149 return;
2150 }
2151
2152 /* Valid for both Intel and AMD. */
2153 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
2154 LogRel(("CPUM: SetGuestCpuIdFeature: Enabled RDTSCP.\n"));
2155 break;
2156 }
2157
2158 /*
2159 * Set the Hypervisor Present bit in the standard feature mask.
2160 */
2161 case CPUMCPUIDFEATURE_HVP:
2162 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2163 pVM->cpum.s.aGuestCpuIdStd[1].ecx |= X86_CPUID_FEATURE_ECX_HVP;
2164 LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
2165 break;
2166
2167 default:
2168 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
2169 break;
2170 }
2171 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2172 {
2173 PVMCPU pVCpu = &pVM->aCpus[i];
2174 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CPUID;
2175 }
2176}
2177
2178
2179/**
2180 * Queries a CPUID feature bit.
2181 *
2182 * @returns boolean for feature presence
2183 * @param pVM Pointer to the VM.
2184 * @param enmFeature The feature to query.
2185 */
2186VMMDECL(bool) CPUMGetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
2187{
2188 switch (enmFeature)
2189 {
2190 case CPUMCPUIDFEATURE_PAE:
2191 {
2192 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2193 return !!(pVM->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PAE);
2194 break;
2195 }
2196
2197 case CPUMCPUIDFEATURE_NX:
2198 {
2199 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
2200 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_EXT_FEATURE_EDX_NX);
2201 }
2202
2203 case CPUMCPUIDFEATURE_SYSCALL:
2204 {
2205 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
2206 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
2207 }
2208
2209 case CPUMCPUIDFEATURE_RDTSCP:
2210 {
2211 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
2212 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2213 break;
2214 }
2215
2216 case CPUMCPUIDFEATURE_LONG_MODE:
2217 {
2218 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
2219 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
2220 break;
2221 }
2222
2223 default:
2224 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
2225 break;
2226 }
2227 return false;
2228}
2229
2230
2231/**
2232 * Clears a CPUID feature bit.
2233 *
2234 * @param pVM Pointer to the VM.
2235 * @param enmFeature The feature to clear.
2236 */
2237VMMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
2238{
2239 switch (enmFeature)
2240 {
2241 /*
2242 * Set the APIC bit in both feature masks.
2243 */
2244 case CPUMCPUIDFEATURE_APIC:
2245 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2246 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_APIC;
2247 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
2248 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
2249 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
2250 Log(("CPUM: ClearGuestCpuIdFeature: Disabled APIC\n"));
2251 break;
2252
2253 /*
2254 * Clear the x2APIC bit in the standard feature mask.
2255 */
2256 case CPUMCPUIDFEATURE_X2APIC:
2257 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2258 pVM->cpum.s.aGuestCpuIdStd[1].ecx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
2259 Log(("CPUM: ClearGuestCpuIdFeature: Disabled x2APIC\n"));
2260 break;
2261
2262 case CPUMCPUIDFEATURE_PAE:
2263 {
2264 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2265 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_PAE;
2266 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
2267 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
2268 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
2269 Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAE!\n"));
2270 break;
2271 }
2272
2273 case CPUMCPUIDFEATURE_PAT:
2274 {
2275 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2276 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_PAT;
2277 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
2278 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
2279 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_PAT;
2280 Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAT!\n"));
2281 break;
2282 }
2283
2284 case CPUMCPUIDFEATURE_LONG_MODE:
2285 {
2286 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
2287 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
2288 break;
2289 }
2290
2291 case CPUMCPUIDFEATURE_LAHF:
2292 {
2293 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
2294 pVM->cpum.s.aGuestCpuIdExt[1].ecx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
2295 break;
2296 }
2297
2298 case CPUMCPUIDFEATURE_RDTSCP:
2299 {
2300 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
2301 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
2302 Log(("CPUM: ClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
2303 break;
2304 }
2305
2306 case CPUMCPUIDFEATURE_HVP:
2307 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2308 pVM->cpum.s.aGuestCpuIdStd[1].ecx &= ~X86_CPUID_FEATURE_ECX_HVP;
2309 break;
2310
2311 default:
2312 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
2313 break;
2314 }
2315 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2316 {
2317 PVMCPU pVCpu = &pVM->aCpus[i];
2318 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CPUID;
2319 }
2320}
2321
2322
2323/**
2324 * Gets the host CPU vendor.
2325 *
2326 * @returns CPU vendor.
2327 * @param pVM Pointer to the VM.
2328 */
2329VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM)
2330{
2331 return pVM->cpum.s.enmHostCpuVendor;
2332}
2333
2334
2335/**
2336 * Gets the CPU vendor.
2337 *
2338 * @returns CPU vendor.
2339 * @param pVM Pointer to the VM.
2340 */
2341VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM)
2342{
2343 return pVM->cpum.s.enmGuestCpuVendor;
2344}
2345
2346
2347VMMDECL(int) CPUMSetGuestDR0(PVMCPU pVCpu, uint64_t uDr0)
2348{
2349 pVCpu->cpum.s.Guest.dr[0] = uDr0;
2350 return CPUMRecalcHyperDRx(pVCpu, 0, false);
2351}
2352
2353
2354VMMDECL(int) CPUMSetGuestDR1(PVMCPU pVCpu, uint64_t uDr1)
2355{
2356 pVCpu->cpum.s.Guest.dr[1] = uDr1;
2357 return CPUMRecalcHyperDRx(pVCpu, 1, false);
2358}
2359
2360
2361VMMDECL(int) CPUMSetGuestDR2(PVMCPU pVCpu, uint64_t uDr2)
2362{
2363 pVCpu->cpum.s.Guest.dr[2] = uDr2;
2364 return CPUMRecalcHyperDRx(pVCpu, 2, false);
2365}
2366
2367
2368VMMDECL(int) CPUMSetGuestDR3(PVMCPU pVCpu, uint64_t uDr3)
2369{
2370 pVCpu->cpum.s.Guest.dr[3] = uDr3;
2371 return CPUMRecalcHyperDRx(pVCpu, 3, false);
2372}
2373
2374
2375VMMDECL(int) CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6)
2376{
2377 pVCpu->cpum.s.Guest.dr[6] = uDr6;
2378 return VINF_SUCCESS; /* No need to recalc. */
2379}
2380
2381
2382VMMDECL(int) CPUMSetGuestDR7(PVMCPU pVCpu, uint64_t uDr7)
2383{
2384 pVCpu->cpum.s.Guest.dr[7] = uDr7;
2385 return CPUMRecalcHyperDRx(pVCpu, 7, false);
2386}
2387
2388
2389VMMDECL(int) CPUMSetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t Value)
2390{
2391 AssertReturn(iReg <= DISDREG_DR7, VERR_INVALID_PARAMETER);
2392 /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
2393 if (iReg == 4 || iReg == 5)
2394 iReg += 2;
2395 pVCpu->cpum.s.Guest.dr[iReg] = Value;
2396 return CPUMRecalcHyperDRx(pVCpu, iReg, false);
2397}
2398
2399
2400/**
2401 * Recalculates the hypervisor DRx register values based on current guest
2402 * registers and DBGF breakpoints, updating changed registers depending on the
2403 * context.
2404 *
2405 * This is called whenever a guest DRx register is modified (any context) and
2406 * when DBGF sets a hardware breakpoint (ring-3 only, rendezvous).
2407 *
2408 * In raw-mode context this function will reload any (hyper) DRx registers which
2409 * comes out with a different value. It may also have to save the host debug
2410 * registers if that haven't been done already. In this context though, we'll
2411 * be intercepting and emulating all DRx accesses, so the hypervisor DRx values
2412 * are only important when breakpoints are actually enabled.
2413 *
2414 * In ring-0 (HM) context DR0-3 will be relocated by us, while DR7 will be
2415 * reloaded by the HM code if it changes. Further more, we will only use the
2416 * combined register set when the VBox debugger is actually using hardware BPs,
2417 * when it isn't we'll keep the guest DR0-3 + (maybe) DR6 loaded (DR6 doesn't
2418 * concern us here).
2419 *
2420 * In ring-3 we won't be loading anything, so well calculate hypervisor values
2421 * all the time.
2422 *
2423 * @returns VINF_SUCCESS.
2424 * @param pVCpu Pointer to the VMCPU.
2425 * @param iGstReg The guest debug register number that was modified.
2426 * UINT8_MAX if not guest register.
2427 * @param fForceHyper Used in HM to force hyper registers because of single
2428 * stepping.
2429 */
2430VMMDECL(int) CPUMRecalcHyperDRx(PVMCPU pVCpu, uint8_t iGstReg, bool fForceHyper)
2431{
2432 PVM pVM = pVCpu->CTX_SUFF(pVM);
2433
2434 /*
2435 * Compare the DR7s first.
2436 *
2437 * We only care about the enabled flags. GD is virtualized when we
2438 * dispatch the #DB, we never enable it. The DBGF DR7 value is will
2439 * always have the LE and GE bits set, so no need to check and disable
2440 * stuff if they're cleared like we have to for the guest DR7.
2441 */
2442 RTGCUINTREG uGstDr7 = CPUMGetGuestDR7(pVCpu);
2443 if (!(uGstDr7 & (X86_DR7_LE | X86_DR7_GE)))
2444 uGstDr7 = 0;
2445 else if (!(uGstDr7 & X86_DR7_LE))
2446 uGstDr7 &= ~X86_DR7_LE_ALL;
2447 else if (!(uGstDr7 & X86_DR7_GE))
2448 uGstDr7 &= ~X86_DR7_GE_ALL;
2449
2450 const RTGCUINTREG uDbgfDr7 = DBGFBpGetDR7(pVM);
2451
2452#ifdef IN_RING0
2453 if (!fForceHyper && (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HYPER))
2454 fForceHyper = true;
2455#endif
2456 if (( HMIsEnabled(pVCpu->CTX_SUFF(pVM)) && !fForceHyper ? uDbgfDr7 : (uGstDr7 | uDbgfDr7)) & X86_DR7_ENABLED_MASK)
2457 {
2458 Assert(!CPUMIsGuestDebugStateActive(pVCpu));
2459#ifdef IN_RC
2460 bool const fHmEnabled = false;
2461#elif defined(IN_RING3)
2462 bool const fHmEnabled = HMIsEnabled(pVM);
2463#endif
2464
2465 /*
2466 * Ok, something is enabled. Recalc each of the breakpoints, taking
2467 * the VM debugger ones of the guest ones. In raw-mode context we will
2468 * not allow breakpoints with values inside the hypervisor area.
2469 */
2470 RTGCUINTREG uNewDr7 = X86_DR7_GE | X86_DR7_LE | X86_DR7_RA1_MASK;
2471
2472 /* bp 0 */
2473 RTGCUINTREG uNewDr0;
2474 if (uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0))
2475 {
2476 uNewDr7 |= uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
2477 uNewDr0 = DBGFBpGetDR0(pVM);
2478 }
2479 else if (uGstDr7 & (X86_DR7_L0 | X86_DR7_G0))
2480 {
2481 uNewDr0 = CPUMGetGuestDR0(pVCpu);
2482#ifndef IN_RING0
2483 if (fHmEnabled && MMHyperIsInsideArea(pVM, uNewDr0))
2484 uNewDr0 = 0;
2485 else
2486#endif
2487 uNewDr7 |= uGstDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
2488 }
2489 else
2490 uNewDr0 = 0;
2491
2492 /* bp 1 */
2493 RTGCUINTREG uNewDr1;
2494 if (uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1))
2495 {
2496 uNewDr7 |= uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
2497 uNewDr1 = DBGFBpGetDR1(pVM);
2498 }
2499 else if (uGstDr7 & (X86_DR7_L1 | X86_DR7_G1))
2500 {
2501 uNewDr1 = CPUMGetGuestDR1(pVCpu);
2502#ifndef IN_RING0
2503 if (fHmEnabled && MMHyperIsInsideArea(pVM, uNewDr1))
2504 uNewDr1 = 0;
2505 else
2506#endif
2507 uNewDr7 |= uGstDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
2508 }
2509 else
2510 uNewDr1 = 0;
2511
2512 /* bp 2 */
2513 RTGCUINTREG uNewDr2;
2514 if (uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2))
2515 {
2516 uNewDr7 |= uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
2517 uNewDr2 = DBGFBpGetDR2(pVM);
2518 }
2519 else if (uGstDr7 & (X86_DR7_L2 | X86_DR7_G2))
2520 {
2521 uNewDr2 = CPUMGetGuestDR2(pVCpu);
2522#ifndef IN_RING0
2523 if (fHmEnabled && MMHyperIsInsideArea(pVM, uNewDr2))
2524 uNewDr2 = 0;
2525 else
2526#endif
2527 uNewDr7 |= uGstDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
2528 }
2529 else
2530 uNewDr2 = 0;
2531
2532 /* bp 3 */
2533 RTGCUINTREG uNewDr3;
2534 if (uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3))
2535 {
2536 uNewDr7 |= uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
2537 uNewDr3 = DBGFBpGetDR3(pVM);
2538 }
2539 else if (uGstDr7 & (X86_DR7_L3 | X86_DR7_G3))
2540 {
2541 uNewDr3 = CPUMGetGuestDR3(pVCpu);
2542#ifndef IN_RING0
2543 if (fHmEnabled && MMHyperIsInsideArea(pVM, uNewDr3))
2544 uNewDr3 = 0;
2545 else
2546#endif
2547 uNewDr7 |= uGstDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
2548 }
2549 else
2550 uNewDr3 = 0;
2551
2552 /*
2553 * Apply the updates.
2554 */
2555#ifdef IN_RC
2556 /* Make sure to save host registers first. */
2557 if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HOST))
2558 {
2559 if (!(pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS_HOST))
2560 {
2561 pVCpu->cpum.s.Host.dr6 = ASMGetDR6();
2562 pVCpu->cpum.s.Host.dr7 = ASMGetDR7();
2563 }
2564 pVCpu->cpum.s.Host.dr0 = ASMGetDR0();
2565 pVCpu->cpum.s.Host.dr1 = ASMGetDR1();
2566 pVCpu->cpum.s.Host.dr2 = ASMGetDR2();
2567 pVCpu->cpum.s.Host.dr3 = ASMGetDR3();
2568 pVCpu->cpum.s.fUseFlags |= CPUM_USED_DEBUG_REGS_HOST | CPUM_USE_DEBUG_REGS_HYPER | CPUM_USED_DEBUG_REGS_HYPER;
2569
2570 /* We haven't loaded any hyper DRxes yet, so we'll have to load them all now. */
2571 pVCpu->cpum.s.Hyper.dr[0] = uNewDr0;
2572 ASMSetDR0(uNewDr0);
2573 pVCpu->cpum.s.Hyper.dr[1] = uNewDr1;
2574 ASMSetDR1(uNewDr1);
2575 pVCpu->cpum.s.Hyper.dr[2] = uNewDr2;
2576 ASMSetDR2(uNewDr2);
2577 pVCpu->cpum.s.Hyper.dr[3] = uNewDr3;
2578 ASMSetDR3(uNewDr3);
2579 ASMSetDR6(X86_DR6_INIT_VAL);
2580 pVCpu->cpum.s.Hyper.dr[7] = uNewDr7;
2581 ASMSetDR7(uNewDr7);
2582 }
2583 else
2584#endif
2585 {
2586 pVCpu->cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS_HYPER;
2587 if (uNewDr3 != pVCpu->cpum.s.Hyper.dr[3])
2588 CPUMSetHyperDR3(pVCpu, uNewDr3);
2589 if (uNewDr2 != pVCpu->cpum.s.Hyper.dr[2])
2590 CPUMSetHyperDR2(pVCpu, uNewDr2);
2591 if (uNewDr1 != pVCpu->cpum.s.Hyper.dr[1])
2592 CPUMSetHyperDR1(pVCpu, uNewDr1);
2593 if (uNewDr0 != pVCpu->cpum.s.Hyper.dr[0])
2594 CPUMSetHyperDR0(pVCpu, uNewDr0);
2595 if (uNewDr7 != pVCpu->cpum.s.Hyper.dr[7])
2596 CPUMSetHyperDR7(pVCpu, uNewDr7);
2597 }
2598 }
2599#ifdef IN_RING0
2600 else if (CPUMIsGuestDebugStateActive(pVCpu))
2601 {
2602 /*
2603 * Reload the register that was modified. Normally this won't happen
2604 * as we won't intercept DRx writes when not having the hyper debug
2605 * state loaded, but in case we do for some reason we'll simply deal
2606 * with it.
2607 */
2608 switch (iGstReg)
2609 {
2610 case 0: ASMSetDR0(CPUMGetGuestDR0(pVCpu)); break;
2611 case 1: ASMSetDR1(CPUMGetGuestDR1(pVCpu)); break;
2612 case 2: ASMSetDR2(CPUMGetGuestDR2(pVCpu)); break;
2613 case 3: ASMSetDR3(CPUMGetGuestDR3(pVCpu)); break;
2614 default:
2615 AssertReturn(iGstReg != UINT8_MAX, VERR_INTERNAL_ERROR_3);
2616 }
2617 }
2618#endif
2619 else
2620 {
2621 /*
2622 * No active debug state any more. In raw-mode this means we have to
2623 * make sure DR7 has everything disabled now, if we armed it already.
2624 * In ring-0 we might end up here when just single stepping.
2625 */
2626#if defined(IN_RC) || defined(IN_RING0)
2627 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HYPER)
2628 {
2629# ifdef IN_RC
2630 ASMSetDR7(X86_DR7_INIT_VAL);
2631# endif
2632 if (pVCpu->cpum.s.Hyper.dr[0])
2633 ASMSetDR0(0);
2634 if (pVCpu->cpum.s.Hyper.dr[1])
2635 ASMSetDR1(0);
2636 if (pVCpu->cpum.s.Hyper.dr[2])
2637 ASMSetDR2(0);
2638 if (pVCpu->cpum.s.Hyper.dr[3])
2639 ASMSetDR3(0);
2640 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_DEBUG_REGS_HYPER;
2641 }
2642#endif
2643 pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS_HYPER;
2644
2645 /* Clear all the registers. */
2646 pVCpu->cpum.s.Hyper.dr[7] = X86_DR7_RA1_MASK;
2647 pVCpu->cpum.s.Hyper.dr[3] = 0;
2648 pVCpu->cpum.s.Hyper.dr[2] = 0;
2649 pVCpu->cpum.s.Hyper.dr[1] = 0;
2650 pVCpu->cpum.s.Hyper.dr[0] = 0;
2651
2652 }
2653 Log2(("CPUMRecalcHyperDRx: fUseFlags=%#x %RGr %RGr %RGr %RGr %RGr %RGr\n",
2654 pVCpu->cpum.s.fUseFlags, pVCpu->cpum.s.Hyper.dr[0], pVCpu->cpum.s.Hyper.dr[1],
2655 pVCpu->cpum.s.Hyper.dr[2], pVCpu->cpum.s.Hyper.dr[3], pVCpu->cpum.s.Hyper.dr[6],
2656 pVCpu->cpum.s.Hyper.dr[7]));
2657
2658 return VINF_SUCCESS;
2659}
2660
2661
2662/**
2663 * Tests if the guest has No-Execute Page Protection Enabled (NXE).
2664 *
2665 * @returns true if in real mode, otherwise false.
2666 * @param pVCpu Pointer to the VMCPU.
2667 */
2668VMMDECL(bool) CPUMIsGuestNXEnabled(PVMCPU pVCpu)
2669{
2670 return !!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE);
2671}
2672
2673
2674/**
2675 * Tests if the guest has the Page Size Extension enabled (PSE).
2676 *
2677 * @returns true if in real mode, otherwise false.
2678 * @param pVCpu Pointer to the VMCPU.
2679 */
2680VMMDECL(bool) CPUMIsGuestPageSizeExtEnabled(PVMCPU pVCpu)
2681{
2682 /* PAE or AMD64 implies support for big pages regardless of CR4.PSE */
2683 return !!(pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PSE | X86_CR4_PAE));
2684}
2685
2686
2687/**
2688 * Tests if the guest has the paging enabled (PG).
2689 *
2690 * @returns true if in real mode, otherwise false.
2691 * @param pVCpu Pointer to the VMCPU.
2692 */
2693VMMDECL(bool) CPUMIsGuestPagingEnabled(PVMCPU pVCpu)
2694{
2695 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG);
2696}
2697
2698
2699/**
2700 * Tests if the guest has the paging enabled (PG).
2701 *
2702 * @returns true if in real mode, otherwise false.
2703 * @param pVCpu Pointer to the VMCPU.
2704 */
2705VMMDECL(bool) CPUMIsGuestR0WriteProtEnabled(PVMCPU pVCpu)
2706{
2707 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_WP);
2708}
2709
2710
2711/**
2712 * Tests if the guest is running in real mode or not.
2713 *
2714 * @returns true if in real mode, otherwise false.
2715 * @param pVCpu Pointer to the VMCPU.
2716 */
2717VMMDECL(bool) CPUMIsGuestInRealMode(PVMCPU pVCpu)
2718{
2719 return !(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
2720}
2721
2722
2723/**
2724 * Tests if the guest is running in real or virtual 8086 mode.
2725 *
2726 * @returns @c true if it is, @c false if not.
2727 * @param pVCpu Pointer to the VMCPU.
2728 */
2729VMMDECL(bool) CPUMIsGuestInRealOrV86Mode(PVMCPU pVCpu)
2730{
2731 return !(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE)
2732 || pVCpu->cpum.s.Guest.eflags.Bits.u1VM; /** @todo verify that this cannot be set in long mode. */
2733}
2734
2735
2736/**
2737 * Tests if the guest is running in protected or not.
2738 *
2739 * @returns true if in protected mode, otherwise false.
2740 * @param pVCpu Pointer to the VMCPU.
2741 */
2742VMMDECL(bool) CPUMIsGuestInProtectedMode(PVMCPU pVCpu)
2743{
2744 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
2745}
2746
2747
2748/**
2749 * Tests if the guest is running in paged protected or not.
2750 *
2751 * @returns true if in paged protected mode, otherwise false.
2752 * @param pVCpu Pointer to the VMCPU.
2753 */
2754VMMDECL(bool) CPUMIsGuestInPagedProtectedMode(PVMCPU pVCpu)
2755{
2756 return (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
2757}
2758
2759
2760/**
2761 * Tests if the guest is running in long mode or not.
2762 *
2763 * @returns true if in long mode, otherwise false.
2764 * @param pVCpu Pointer to the VMCPU.
2765 */
2766VMMDECL(bool) CPUMIsGuestInLongMode(PVMCPU pVCpu)
2767{
2768 return (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
2769}
2770
2771
2772/**
2773 * Tests if the guest is running in PAE mode or not.
2774 *
2775 * @returns true if in PAE mode, otherwise false.
2776 * @param pVCpu Pointer to the VMCPU.
2777 */
2778VMMDECL(bool) CPUMIsGuestInPAEMode(PVMCPU pVCpu)
2779{
2780 return (pVCpu->cpum.s.Guest.cr4 & X86_CR4_PAE)
2781 && (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG)
2782 && !(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LME);
2783}
2784
2785
2786/**
2787 * Tests if the guest is running in 64 bits mode or not.
2788 *
2789 * @returns true if in 64 bits protected mode, otherwise false.
2790 * @param pVCpu The current virtual CPU.
2791 */
2792VMMDECL(bool) CPUMIsGuestIn64BitCode(PVMCPU pVCpu)
2793{
2794 if (!CPUMIsGuestInLongMode(pVCpu))
2795 return false;
2796 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
2797 return pVCpu->cpum.s.Guest.cs.Attr.n.u1Long;
2798}
2799
2800
2801/**
2802 * Helper for CPUMIsGuestIn64BitCodeEx that handles lazy resolving of hidden CS
2803 * registers.
2804 *
2805 * @returns true if in 64 bits protected mode, otherwise false.
2806 * @param pCtx Pointer to the current guest CPU context.
2807 */
2808VMM_INT_DECL(bool) CPUMIsGuestIn64BitCodeSlow(PCPUMCTX pCtx)
2809{
2810 return CPUMIsGuestIn64BitCode(CPUM_GUEST_CTX_TO_VMCPU(pCtx));
2811}
2812
2813#ifdef VBOX_WITH_RAW_MODE_NOT_R0
2814
2815/**
2816 *
2817 * @returns @c true if we've entered raw-mode and selectors with RPL=1 are
2818 * really RPL=0, @c false if we've not (RPL=1 really is RPL=1).
2819 * @param pVCpu The current virtual CPU.
2820 */
2821VMM_INT_DECL(bool) CPUMIsGuestInRawMode(PVMCPU pVCpu)
2822{
2823 return pVCpu->cpum.s.fRawEntered;
2824}
2825
2826/**
2827 * Transforms the guest CPU state to raw-ring mode.
2828 *
2829 * This function will change the any of the cs and ss register with DPL=0 to DPL=1.
2830 *
2831 * @returns VBox status. (recompiler failure)
2832 * @param pVCpu Pointer to the VMCPU.
2833 * @param pCtxCore The context core (for trap usage).
2834 * @see @ref pg_raw
2835 */
2836VMM_INT_DECL(int) CPUMRawEnter(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
2837{
2838 PVM pVM = pVCpu->CTX_SUFF(pVM);
2839
2840 Assert(!pVCpu->cpum.s.fRawEntered);
2841 Assert(!pVCpu->cpum.s.fRemEntered);
2842 if (!pCtxCore)
2843 pCtxCore = CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
2844
2845 /*
2846 * Are we in Ring-0?
2847 */
2848 if ( pCtxCore->ss.Sel
2849 && (pCtxCore->ss.Sel & X86_SEL_RPL) == 0
2850 && !pCtxCore->eflags.Bits.u1VM)
2851 {
2852 /*
2853 * Enter execution mode.
2854 */
2855 PATMRawEnter(pVM, pCtxCore);
2856
2857 /*
2858 * Set CPL to Ring-1.
2859 */
2860 pCtxCore->ss.Sel |= 1;
2861 if ( pCtxCore->cs.Sel
2862 && (pCtxCore->cs.Sel & X86_SEL_RPL) == 0)
2863 pCtxCore->cs.Sel |= 1;
2864 }
2865 else
2866 {
2867# ifdef VBOX_WITH_RAW_RING1
2868 if ( EMIsRawRing1Enabled(pVM)
2869 && !pCtxCore->eflags.Bits.u1VM
2870 && (pCtxCore->ss.Sel & X86_SEL_RPL) == 1)
2871 {
2872 /* Set CPL to Ring-2. */
2873 pCtxCore->ss.Sel = (pCtxCore->ss.Sel & ~X86_SEL_RPL) | 2;
2874 if (pCtxCore->cs.Sel && (pCtxCore->cs.Sel & X86_SEL_RPL) == 1)
2875 pCtxCore->cs.Sel = (pCtxCore->cs.Sel & ~X86_SEL_RPL) | 2;
2876 }
2877# else
2878 AssertMsg((pCtxCore->ss.Sel & X86_SEL_RPL) >= 2 || pCtxCore->eflags.Bits.u1VM,
2879 ("ring-1 code not supported\n"));
2880# endif
2881 /*
2882 * PATM takes care of IOPL and IF flags for Ring-3 and Ring-2 code as well.
2883 */
2884 PATMRawEnter(pVM, pCtxCore);
2885 }
2886
2887 /*
2888 * Assert sanity.
2889 */
2890 AssertMsg((pCtxCore->eflags.u32 & X86_EFL_IF), ("X86_EFL_IF is clear\n"));
2891 AssertReleaseMsg(pCtxCore->eflags.Bits.u2IOPL == 0,
2892 ("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss.Sel & X86_SEL_RPL));
2893 Assert((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)) == (X86_CR0_PG | X86_CR0_PE | X86_CR0_WP));
2894
2895 pCtxCore->eflags.u32 |= X86_EFL_IF; /* paranoia */
2896
2897 pVCpu->cpum.s.fRawEntered = true;
2898 return VINF_SUCCESS;
2899}
2900
2901
2902/**
2903 * Transforms the guest CPU state from raw-ring mode to correct values.
2904 *
2905 * This function will change any selector registers with DPL=1 to DPL=0.
2906 *
2907 * @returns Adjusted rc.
2908 * @param pVCpu Pointer to the VMCPU.
2909 * @param rc Raw mode return code
2910 * @param pCtxCore The context core (for trap usage).
2911 * @see @ref pg_raw
2912 */
2913VMM_INT_DECL(int) CPUMRawLeave(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, int rc)
2914{
2915 PVM pVM = pVCpu->CTX_SUFF(pVM);
2916
2917 /*
2918 * Don't leave if we've already left (in RC).
2919 */
2920 Assert(!pVCpu->cpum.s.fRemEntered);
2921 if (!pVCpu->cpum.s.fRawEntered)
2922 return rc;
2923 pVCpu->cpum.s.fRawEntered = false;
2924
2925 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2926 if (!pCtxCore)
2927 pCtxCore = CPUMCTX2CORE(pCtx);
2928 Assert(pCtxCore->eflags.Bits.u1VM || (pCtxCore->ss.Sel & X86_SEL_RPL));
2929 AssertMsg(pCtxCore->eflags.Bits.u1VM || pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss.Sel & X86_SEL_RPL),
2930 ("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss.Sel & X86_SEL_RPL));
2931
2932 /*
2933 * Are we executing in raw ring-1?
2934 */
2935 if ( (pCtxCore->ss.Sel & X86_SEL_RPL) == 1
2936 && !pCtxCore->eflags.Bits.u1VM)
2937 {
2938 /*
2939 * Leave execution mode.
2940 */
2941 PATMRawLeave(pVM, pCtxCore, rc);
2942 /* Not quite sure if this is really required, but shouldn't harm (too much anyways). */
2943 /** @todo See what happens if we remove this. */
2944 if ((pCtxCore->ds.Sel & X86_SEL_RPL) == 1)
2945 pCtxCore->ds.Sel &= ~X86_SEL_RPL;
2946 if ((pCtxCore->es.Sel & X86_SEL_RPL) == 1)
2947 pCtxCore->es.Sel &= ~X86_SEL_RPL;
2948 if ((pCtxCore->fs.Sel & X86_SEL_RPL) == 1)
2949 pCtxCore->fs.Sel &= ~X86_SEL_RPL;
2950 if ((pCtxCore->gs.Sel & X86_SEL_RPL) == 1)
2951 pCtxCore->gs.Sel &= ~X86_SEL_RPL;
2952
2953 /*
2954 * Ring-1 selector => Ring-0.
2955 */
2956 pCtxCore->ss.Sel &= ~X86_SEL_RPL;
2957 if ((pCtxCore->cs.Sel & X86_SEL_RPL) == 1)
2958 pCtxCore->cs.Sel &= ~X86_SEL_RPL;
2959 }
2960 else
2961 {
2962 /*
2963 * PATM is taking care of the IOPL and IF flags for us.
2964 */
2965 PATMRawLeave(pVM, pCtxCore, rc);
2966 if (!pCtxCore->eflags.Bits.u1VM)
2967 {
2968# ifdef VBOX_WITH_RAW_RING1
2969 if ( EMIsRawRing1Enabled(pVM)
2970 && (pCtxCore->ss.Sel & X86_SEL_RPL) == 2)
2971 {
2972 /* Not quite sure if this is really required, but shouldn't harm (too much anyways). */
2973 /** @todo See what happens if we remove this. */
2974 if ((pCtxCore->ds.Sel & X86_SEL_RPL) == 2)
2975 pCtxCore->ds.Sel = (pCtxCore->ds.Sel & ~X86_SEL_RPL) | 1;
2976 if ((pCtxCore->es.Sel & X86_SEL_RPL) == 2)
2977 pCtxCore->es.Sel = (pCtxCore->es.Sel & ~X86_SEL_RPL) | 1;
2978 if ((pCtxCore->fs.Sel & X86_SEL_RPL) == 2)
2979 pCtxCore->fs.Sel = (pCtxCore->fs.Sel & ~X86_SEL_RPL) | 1;
2980 if ((pCtxCore->gs.Sel & X86_SEL_RPL) == 2)
2981 pCtxCore->gs.Sel = (pCtxCore->gs.Sel & ~X86_SEL_RPL) | 1;
2982
2983 /*
2984 * Ring-2 selector => Ring-1.
2985 */
2986 pCtxCore->ss.Sel = (pCtxCore->ss.Sel & ~X86_SEL_RPL) | 1;
2987 if ((pCtxCore->cs.Sel & X86_SEL_RPL) == 2)
2988 pCtxCore->cs.Sel = (pCtxCore->cs.Sel & ~X86_SEL_RPL) | 1;
2989 }
2990 else
2991 {
2992# endif
2993 /** @todo See what happens if we remove this. */
2994 if ((pCtxCore->ds.Sel & X86_SEL_RPL) == 1)
2995 pCtxCore->ds.Sel &= ~X86_SEL_RPL;
2996 if ((pCtxCore->es.Sel & X86_SEL_RPL) == 1)
2997 pCtxCore->es.Sel &= ~X86_SEL_RPL;
2998 if ((pCtxCore->fs.Sel & X86_SEL_RPL) == 1)
2999 pCtxCore->fs.Sel &= ~X86_SEL_RPL;
3000 if ((pCtxCore->gs.Sel & X86_SEL_RPL) == 1)
3001 pCtxCore->gs.Sel &= ~X86_SEL_RPL;
3002# ifdef VBOX_WITH_RAW_RING1
3003 }
3004# endif
3005 }
3006 }
3007
3008 return rc;
3009}
3010
3011#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
3012
3013/**
3014 * Updates the EFLAGS while we're in raw-mode.
3015 *
3016 * @param pVCpu Pointer to the VMCPU.
3017 * @param fEfl The new EFLAGS value.
3018 */
3019VMMDECL(void) CPUMRawSetEFlags(PVMCPU pVCpu, uint32_t fEfl)
3020{
3021#ifdef VBOX_WITH_RAW_MODE_NOT_R0
3022 if (pVCpu->cpum.s.fRawEntered)
3023 PATMRawSetEFlags(pVCpu->CTX_SUFF(pVM), CPUMCTX2CORE(&pVCpu->cpum.s.Guest), fEfl);
3024 else
3025#endif
3026 pVCpu->cpum.s.Guest.eflags.u32 = fEfl;
3027}
3028
3029
3030/**
3031 * Gets the EFLAGS while we're in raw-mode.
3032 *
3033 * @returns The eflags.
3034 * @param pVCpu Pointer to the current virtual CPU.
3035 */
3036VMMDECL(uint32_t) CPUMRawGetEFlags(PVMCPU pVCpu)
3037{
3038#ifdef VBOX_WITH_RAW_MODE_NOT_R0
3039 if (pVCpu->cpum.s.fRawEntered)
3040 return PATMRawGetEFlags(pVCpu->CTX_SUFF(pVM), CPUMCTX2CORE(&pVCpu->cpum.s.Guest));
3041#endif
3042 return pVCpu->cpum.s.Guest.eflags.u32;
3043}
3044
3045
3046/**
3047 * Sets the specified changed flags (CPUM_CHANGED_*).
3048 *
3049 * @param pVCpu Pointer to the current virtual CPU.
3050 */
3051VMMDECL(void) CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedFlags)
3052{
3053 pVCpu->cpum.s.fChanged |= fChangedFlags;
3054}
3055
3056
3057/**
3058 * Checks if the CPU supports the FXSAVE and FXRSTOR instruction.
3059 * @returns true if supported.
3060 * @returns false if not supported.
3061 * @param pVM Pointer to the VM.
3062 */
3063VMMDECL(bool) CPUMSupportsFXSR(PVM pVM)
3064{
3065 return pVM->cpum.s.CPUFeatures.edx.u1FXSR != 0;
3066}
3067
3068
3069/**
3070 * Checks if the host OS uses the SYSENTER / SYSEXIT instructions.
3071 * @returns true if used.
3072 * @returns false if not used.
3073 * @param pVM Pointer to the VM.
3074 */
3075VMMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM)
3076{
3077 return RT_BOOL(pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSENTER);
3078}
3079
3080
3081/**
3082 * Checks if the host OS uses the SYSCALL / SYSRET instructions.
3083 * @returns true if used.
3084 * @returns false if not used.
3085 * @param pVM Pointer to the VM.
3086 */
3087VMMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM)
3088{
3089 return RT_BOOL(pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSCALL);
3090}
3091
3092#ifndef IN_RING3
3093
3094/**
3095 * Lazily sync in the FPU/XMM state.
3096 *
3097 * @returns VBox status code.
3098 * @param pVCpu Pointer to the VMCPU.
3099 */
3100VMMDECL(int) CPUMHandleLazyFPU(PVMCPU pVCpu)
3101{
3102 return cpumHandleLazyFPUAsm(&pVCpu->cpum.s);
3103}
3104
3105#endif /* !IN_RING3 */
3106
3107/**
3108 * Checks if we activated the FPU/XMM state of the guest OS.
3109 * @returns true if we did.
3110 * @returns false if not.
3111 * @param pVCpu Pointer to the VMCPU.
3112 */
3113VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCpu)
3114{
3115 return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU);
3116}
3117
3118
3119/**
3120 * Deactivate the FPU/XMM state of the guest OS.
3121 * @param pVCpu Pointer to the VMCPU.
3122 *
3123 * @todo r=bird: Why is this needed? Looks like a workaround for mishandled
3124 * FPU state management.
3125 */
3126VMMDECL(void) CPUMDeactivateGuestFPUState(PVMCPU pVCpu)
3127{
3128 Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU));
3129 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU;
3130}
3131
3132
3133/**
3134 * Checks if the guest debug state is active.
3135 *
3136 * @returns boolean
3137 * @param pVM Pointer to the VMCPU.
3138 */
3139VMMDECL(bool) CPUMIsGuestDebugStateActive(PVMCPU pVCpu)
3140{
3141 return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST);
3142}
3143
3144
3145/**
3146 * Checks if the guest debug state is to be made active during the world-switch
3147 * (currently only used for the 32->64 switcher case).
3148 *
3149 * @returns boolean
3150 * @param pVM Pointer to the VMCPU.
3151 */
3152VMMDECL(bool) CPUMIsGuestDebugStateActivePending(PVMCPU pVCpu)
3153{
3154 return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_DEBUG_REGS_GUEST);
3155}
3156
3157
3158/**
3159 * Checks if the hyper debug state is active.
3160 *
3161 * @returns boolean
3162 * @param pVM Pointer to the VM.
3163 */
3164VMMDECL(bool) CPUMIsHyperDebugStateActive(PVMCPU pVCpu)
3165{
3166 return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HYPER);
3167}
3168
3169
3170/**
3171 * Checks if the hyper debug state is to be made active during the world-switch
3172 * (currently only used for the 32->64 switcher case).
3173 *
3174 * @returns boolean
3175 * @param pVM Pointer to the VMCPU.
3176 */
3177VMMDECL(bool) CPUMIsHyperDebugStateActivePending(PVMCPU pVCpu)
3178{
3179 return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_DEBUG_REGS_HYPER);
3180}
3181
3182
3183/**
3184 * Mark the guest's debug state as inactive.
3185 *
3186 * @returns boolean
3187 * @param pVM Pointer to the VM.
3188 * @todo This API doesn't make sense any more.
3189 */
3190VMMDECL(void) CPUMDeactivateGuestDebugState(PVMCPU pVCpu)
3191{
3192 Assert(!(pVCpu->cpum.s.fUseFlags & (CPUM_USED_DEBUG_REGS_GUEST | CPUM_USED_DEBUG_REGS_HYPER | CPUM_USED_DEBUG_REGS_HOST)));
3193}
3194
3195
3196/**
3197 * Get the current privilege level of the guest.
3198 *
3199 * @returns CPL
3200 * @param pVCpu Pointer to the current virtual CPU.
3201 */
3202VMMDECL(uint32_t) CPUMGetGuestCPL(PVMCPU pVCpu)
3203{
3204 /*
3205 * CPL can reliably be found in SS.DPL (hidden regs valid) or SS if not.
3206 *
3207 * Note! We used to check CS.DPL here, assuming it was always equal to
3208 * CPL even if a conforming segment was loaded. But this truned out to
3209 * only apply to older AMD-V. With VT-x we had an ACP2 regression
3210 * during install after a far call to ring 2 with VT-x. Then on newer
3211 * AMD-V CPUs we have to move the VMCB.guest.u8CPL into cs.Attr.n.u2Dpl
3212 * as well as ss.Attr.n.u2Dpl to make this (and other) code work right.
3213 *
3214 * So, forget CS.DPL, always use SS.DPL.
3215 *
3216 * Note! The SS RPL is always equal to the CPL, while the CS RPL
3217 * isn't necessarily equal if the segment is conforming.
3218 * See section 4.11.1 in the AMD manual.
3219 *
3220 * Update: Where the heck does it say CS.RPL can differ from CPL other than
3221 * right after real->prot mode switch and when in V8086 mode? That
3222 * section says the RPL specified in a direct transfere (call, jmp,
3223 * ret) is not the one loaded into CS. Besides, if CS.RPL != CPL
3224 * it would be impossible for an exception handle or the iret
3225 * instruction to figure out whether SS:ESP are part of the frame
3226 * or not. VBox or qemu bug must've lead to this misconception.
3227 *
3228 * Update2: On an AMD bulldozer system here, I've no trouble loading a null
3229 * selector into SS with an RPL other than the CPL when CPL != 3 and
3230 * we're in 64-bit mode. The intel dev box doesn't allow this, on
3231 * RPL = CPL. Weird.
3232 */
3233 uint32_t uCpl;
3234 if (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE)
3235 {
3236 if (!pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
3237 {
3238 if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.s.Guest.ss))
3239 uCpl = pVCpu->cpum.s.Guest.ss.Attr.n.u2Dpl;
3240 else
3241 {
3242 uCpl = (pVCpu->cpum.s.Guest.ss.Sel & X86_SEL_RPL);
3243#ifdef VBOX_WITH_RAW_MODE_NOT_R0
3244# ifdef VBOX_WITH_RAW_RING1
3245 if (pVCpu->cpum.s.fRawEntered)
3246 {
3247 if ( uCpl == 2
3248 && EMIsRawRing1Enabled(pVCpu->CTX_SUFF(pVM)))
3249 uCpl = 1;
3250 else if (uCpl == 1)
3251 uCpl = 0;
3252 }
3253 Assert(uCpl != 2); /* ring 2 support not allowed anymore. */
3254# else
3255 if (uCpl == 1)
3256 uCpl = 0;
3257# endif
3258#endif
3259 }
3260 }
3261 else
3262 uCpl = 3; /* V86 has CPL=3; REM doesn't set DPL=3 in V8086 mode. See @bugref{5130}. */
3263 }
3264 else
3265 uCpl = 0; /* Real mode is zero; CPL set to 3 for VT-x real-mode emulation. */
3266 return uCpl;
3267}
3268
3269
3270/**
3271 * Gets the current guest CPU mode.
3272 *
3273 * If paging mode is what you need, check out PGMGetGuestMode().
3274 *
3275 * @returns The CPU mode.
3276 * @param pVCpu Pointer to the VMCPU.
3277 */
3278VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu)
3279{
3280 CPUMMODE enmMode;
3281 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
3282 enmMode = CPUMMODE_REAL;
3283 else if (!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
3284 enmMode = CPUMMODE_PROTECTED;
3285 else
3286 enmMode = CPUMMODE_LONG;
3287
3288 return enmMode;
3289}
3290
3291
3292/**
3293 * Figure whether the CPU is currently executing 16, 32 or 64 bit code.
3294 *
3295 * @returns 16, 32 or 64.
3296 * @param pVCpu The current virtual CPU.
3297 */
3298VMMDECL(uint32_t) CPUMGetGuestCodeBits(PVMCPU pVCpu)
3299{
3300 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
3301 return 16;
3302
3303 if (pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
3304 {
3305 Assert(!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA));
3306 return 16;
3307 }
3308
3309 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
3310 if ( pVCpu->cpum.s.Guest.cs.Attr.n.u1Long
3311 && (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
3312 return 64;
3313
3314 if (pVCpu->cpum.s.Guest.cs.Attr.n.u1DefBig)
3315 return 32;
3316
3317 return 16;
3318}
3319
3320
3321VMMDECL(DISCPUMODE) CPUMGetGuestDisMode(PVMCPU pVCpu)
3322{
3323 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
3324 return DISCPUMODE_16BIT;
3325
3326 if (pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
3327 {
3328 Assert(!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA));
3329 return DISCPUMODE_16BIT;
3330 }
3331
3332 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
3333 if ( pVCpu->cpum.s.Guest.cs.Attr.n.u1Long
3334 && (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
3335 return DISCPUMODE_64BIT;
3336
3337 if (pVCpu->cpum.s.Guest.cs.Attr.n.u1DefBig)
3338 return DISCPUMODE_32BIT;
3339
3340 return DISCPUMODE_16BIT;
3341}
3342
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette