VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp@ 4991

Last change on this file since 4991 was 4958, checked in by vboxsync, 17 years ago

Added hSelf and removed pVMHC from the VM structure.
  • Property svn:eol-style set to native
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File size: 38.3 KB
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1/* $Id: CPUMAllRegs.cpp 4958 2007-09-21 14:54:04Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor(/Manager) - Gets and Sets.
4 */
5
6/*
7 * Copyright (C) 2006-2007 innotek GmbH
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License as published by the Free Software Foundation,
13 * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14 * distribution. VirtualBox OSE is distributed in the hope that it will
15 * be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_CPUM
23#include <VBox/cpum.h>
24#include <VBox/patm.h>
25#include <VBox/dbgf.h>
26#include <VBox/mm.h>
27#include "CPUMInternal.h"
28#include <VBox/vm.h>
29#include <VBox/err.h>
30#include <VBox/dis.h>
31#include <VBox/log.h>
32#include <iprt/assert.h>
33#include <iprt/asm.h>
34
35
36
37/** Disable stack frame pointer generation here. */
38#if defined(_MSC_VER) && !defined(DEBUG)
39# pragma optimize("y", off)
40#endif
41
42
43/**
44 * Sets or resets an alternative hypervisor context core.
45 *
46 * This is called when we get a hypervisor trap set switch the context
47 * core with the trap frame on the stack. It is called again to reset
48 * back to the default context core when resuming hypervisor execution.
49 *
50 * @param pVM The VM handle.
51 * @param pCtxCore Pointer to the alternative context core or NULL
52 * to go back to the default context core.
53 */
54CPUMDECL(void) CPUMHyperSetCtxCore(PVM pVM, PCPUMCTXCORE pCtxCore)
55{
56 LogFlow(("CPUMHyperSetCtxCore: %p/%p/%p -> %p\n", pVM->cpum.s.CTXALLSUFF(pHyperCore), pCtxCore));
57 if (!pCtxCore)
58 {
59 pCtxCore = CPUMCTX2CORE(&pVM->cpum.s.Hyper);
60 pVM->cpum.s.pHyperCoreR3 = (R3PTRTYPE(PCPUMCTXCORE))VM_R3_ADDR(pVM, pCtxCore);
61 pVM->cpum.s.pHyperCoreR0 = (R0PTRTYPE(PCPUMCTXCORE))VM_R0_ADDR(pVM, pCtxCore);
62 pVM->cpum.s.pHyperCoreGC = (GCPTRTYPE(PCPUMCTXCORE))VM_GUEST_ADDR(pVM, pCtxCore);
63 }
64 else
65 {
66 pVM->cpum.s.pHyperCoreR3 = (R3PTRTYPE(PCPUMCTXCORE))MMHyperCCToR3(pVM, pCtxCore);
67 pVM->cpum.s.pHyperCoreR0 = (R0PTRTYPE(PCPUMCTXCORE))MMHyperCCToR0(pVM, pCtxCore);
68 pVM->cpum.s.pHyperCoreGC = (GCPTRTYPE(PCPUMCTXCORE))MMHyperCCToGC(pVM, pCtxCore);
69 }
70}
71
72
73/**
74 * Gets the pointer to the internal CPUMCTXCORE structure for the hypervisor.
75 * This is only for reading in order to save a few calls.
76 *
77 * @param pVM Handle to the virtual machine.
78 */
79CPUMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVM pVM)
80{
81 return pVM->cpum.s.CTXALLSUFF(pHyperCore);
82}
83
84
85/**
86 * Queries the pointer to the internal CPUMCTX structure for the hypervisor.
87 *
88 * @returns VBox status code.
89 * @param pVM Handle to the virtual machine.
90 * @param ppCtx Receives the hyper CPUMCTX pointer when successful.
91 *
92 * @deprecated This will *not* (and has never) given the right picture of the
93 * hypervisor register state. With CPUMHyperSetCtxCore() this is
94 * getting much worse. So, use the individual functions for getting
95 * and esp. setting the hypervisor registers.
96 */
97CPUMDECL(int) CPUMQueryHyperCtxPtr(PVM pVM, PCPUMCTX *ppCtx)
98{
99 *ppCtx = &pVM->cpum.s.Hyper;
100 return VINF_SUCCESS;
101}
102
103CPUMDECL(void) CPUMSetHyperGDTR(PVM pVM, uint32_t addr, uint16_t limit)
104{
105 pVM->cpum.s.Hyper.gdtr.cbGdt = limit;
106 pVM->cpum.s.Hyper.gdtr.pGdt = addr;
107 pVM->cpum.s.Hyper.gdtrPadding = 0;
108 pVM->cpum.s.Hyper.gdtrPadding64 = 0;
109}
110
111CPUMDECL(void) CPUMSetHyperIDTR(PVM pVM, uint32_t addr, uint16_t limit)
112{
113 pVM->cpum.s.Hyper.idtr.cbIdt = limit;
114 pVM->cpum.s.Hyper.idtr.pIdt = addr;
115 pVM->cpum.s.Hyper.idtrPadding = 0;
116 pVM->cpum.s.Hyper.idtrPadding64 = 0;
117}
118
119CPUMDECL(void) CPUMSetHyperCR3(PVM pVM, uint32_t cr3)
120{
121 pVM->cpum.s.Hyper.cr3 = cr3;
122}
123
124CPUMDECL(void) CPUMSetHyperCS(PVM pVM, RTSEL SelCS)
125{
126 pVM->cpum.s.CTXALLSUFF(pHyperCore)->cs = SelCS;
127}
128
129CPUMDECL(void) CPUMSetHyperDS(PVM pVM, RTSEL SelDS)
130{
131 pVM->cpum.s.CTXALLSUFF(pHyperCore)->ds = SelDS;
132}
133
134CPUMDECL(void) CPUMSetHyperES(PVM pVM, RTSEL SelES)
135{
136 pVM->cpum.s.CTXALLSUFF(pHyperCore)->es = SelES;
137}
138
139CPUMDECL(void) CPUMSetHyperFS(PVM pVM, RTSEL SelFS)
140{
141 pVM->cpum.s.CTXALLSUFF(pHyperCore)->fs = SelFS;
142}
143
144CPUMDECL(void) CPUMSetHyperGS(PVM pVM, RTSEL SelGS)
145{
146 pVM->cpum.s.CTXALLSUFF(pHyperCore)->gs = SelGS;
147}
148
149CPUMDECL(void) CPUMSetHyperSS(PVM pVM, RTSEL SelSS)
150{
151 pVM->cpum.s.CTXALLSUFF(pHyperCore)->ss = SelSS;
152}
153
154CPUMDECL(void) CPUMSetHyperESP(PVM pVM, uint32_t u32ESP)
155{
156 pVM->cpum.s.CTXALLSUFF(pHyperCore)->esp = u32ESP;
157}
158
159CPUMDECL(int) CPUMSetHyperEFlags(PVM pVM, uint32_t Efl)
160{
161 pVM->cpum.s.CTXALLSUFF(pHyperCore)->eflags.u32 = Efl;
162 return VINF_SUCCESS;
163}
164
165CPUMDECL(void) CPUMSetHyperEIP(PVM pVM, uint32_t u32EIP)
166{
167 pVM->cpum.s.CTXALLSUFF(pHyperCore)->eip = u32EIP;
168}
169
170CPUMDECL(void) CPUMSetHyperTR(PVM pVM, RTSEL SelTR)
171{
172 pVM->cpum.s.Hyper.tr = SelTR;
173}
174
175CPUMDECL(void) CPUMSetHyperLDTR(PVM pVM, RTSEL SelLDTR)
176{
177 pVM->cpum.s.Hyper.ldtr = SelLDTR;
178}
179
180CPUMDECL(void) CPUMSetHyperDR0(PVM pVM, RTGCUINTREG uDr0)
181{
182 pVM->cpum.s.Hyper.dr0 = uDr0;
183 /** @todo in GC we must load it! */
184}
185
186CPUMDECL(void) CPUMSetHyperDR1(PVM pVM, RTGCUINTREG uDr1)
187{
188 pVM->cpum.s.Hyper.dr1 = uDr1;
189 /** @todo in GC we must load it! */
190}
191
192CPUMDECL(void) CPUMSetHyperDR2(PVM pVM, RTGCUINTREG uDr2)
193{
194 pVM->cpum.s.Hyper.dr2 = uDr2;
195 /** @todo in GC we must load it! */
196}
197
198CPUMDECL(void) CPUMSetHyperDR3(PVM pVM, RTGCUINTREG uDr3)
199{
200 pVM->cpum.s.Hyper.dr3 = uDr3;
201 /** @todo in GC we must load it! */
202}
203
204CPUMDECL(void) CPUMSetHyperDR6(PVM pVM, RTGCUINTREG uDr6)
205{
206 pVM->cpum.s.Hyper.dr6 = uDr6;
207 /** @todo in GC we must load it! */
208}
209
210CPUMDECL(void) CPUMSetHyperDR7(PVM pVM, RTGCUINTREG uDr7)
211{
212 pVM->cpum.s.Hyper.dr7 = uDr7;
213 /** @todo in GC we must load it! */
214}
215
216
217CPUMDECL(RTSEL) CPUMGetHyperCS(PVM pVM)
218{
219 return pVM->cpum.s.CTXALLSUFF(pHyperCore)->cs;
220}
221
222CPUMDECL(RTSEL) CPUMGetHyperDS(PVM pVM)
223{
224 return pVM->cpum.s.CTXALLSUFF(pHyperCore)->ds;
225}
226
227CPUMDECL(RTSEL) CPUMGetHyperES(PVM pVM)
228{
229 return pVM->cpum.s.CTXALLSUFF(pHyperCore)->es;
230}
231
232CPUMDECL(RTSEL) CPUMGetHyperFS(PVM pVM)
233{
234 return pVM->cpum.s.CTXALLSUFF(pHyperCore)->fs;
235}
236
237CPUMDECL(RTSEL) CPUMGetHyperGS(PVM pVM)
238{
239 return pVM->cpum.s.CTXALLSUFF(pHyperCore)->gs;
240}
241
242CPUMDECL(RTSEL) CPUMGetHyperSS(PVM pVM)
243{
244 return pVM->cpum.s.CTXALLSUFF(pHyperCore)->ss;
245}
246
247#if 0 /* these are not correct. */
248
249CPUMDECL(uint32_t) CPUMGetHyperCR0(PVM pVM)
250{
251 return pVM->cpum.s.Hyper.cr0;
252}
253
254CPUMDECL(uint32_t) CPUMGetHyperCR2(PVM pVM)
255{
256 return pVM->cpum.s.Hyper.cr2;
257}
258
259CPUMDECL(uint32_t) CPUMGetHyperCR3(PVM pVM)
260{
261 return pVM->cpum.s.Hyper.cr3;
262}
263
264CPUMDECL(uint32_t) CPUMGetHyperCR4(PVM pVM)
265{
266 return pVM->cpum.s.Hyper.cr4;
267}
268
269#endif /* not correct */
270
271CPUMDECL(uint32_t) CPUMGetHyperEAX(PVM pVM)
272{
273 return pVM->cpum.s.CTXALLSUFF(pHyperCore)->eax;
274}
275
276CPUMDECL(uint32_t) CPUMGetHyperEBX(PVM pVM)
277{
278 return pVM->cpum.s.CTXALLSUFF(pHyperCore)->ebx;
279}
280
281CPUMDECL(uint32_t) CPUMGetHyperECX(PVM pVM)
282{
283 return pVM->cpum.s.CTXALLSUFF(pHyperCore)->ecx;
284}
285
286CPUMDECL(uint32_t) CPUMGetHyperEDX(PVM pVM)
287{
288 return pVM->cpum.s.CTXALLSUFF(pHyperCore)->edx;
289}
290
291CPUMDECL(uint32_t) CPUMGetHyperESI(PVM pVM)
292{
293 return pVM->cpum.s.CTXALLSUFF(pHyperCore)->esi;
294}
295
296CPUMDECL(uint32_t) CPUMGetHyperEDI(PVM pVM)
297{
298 return pVM->cpum.s.CTXALLSUFF(pHyperCore)->edi;
299}
300
301CPUMDECL(uint32_t) CPUMGetHyperEBP(PVM pVM)
302{
303 return pVM->cpum.s.CTXALLSUFF(pHyperCore)->ebp;
304}
305
306CPUMDECL(uint32_t) CPUMGetHyperESP(PVM pVM)
307{
308 return pVM->cpum.s.CTXALLSUFF(pHyperCore)->esp;
309}
310
311CPUMDECL(uint32_t) CPUMGetHyperEFlags(PVM pVM)
312{
313 return pVM->cpum.s.CTXALLSUFF(pHyperCore)->eflags.u32;
314}
315
316CPUMDECL(uint32_t) CPUMGetHyperEIP(PVM pVM)
317{
318 return pVM->cpum.s.CTXALLSUFF(pHyperCore)->eip;
319}
320
321CPUMDECL(uint32_t) CPUMGetHyperIDTR(PVM pVM, uint16_t *pcbLimit)
322{
323 if (pcbLimit)
324 *pcbLimit = pVM->cpum.s.Hyper.idtr.cbIdt;
325 return pVM->cpum.s.Hyper.idtr.pIdt;
326}
327
328CPUMDECL(uint32_t) CPUMGetHyperGDTR(PVM pVM, uint16_t *pcbLimit)
329{
330 if (pcbLimit)
331 *pcbLimit = pVM->cpum.s.Hyper.gdtr.cbGdt;
332 return pVM->cpum.s.Hyper.gdtr.pGdt;
333}
334
335CPUMDECL(RTSEL) CPUMGetHyperLDTR(PVM pVM)
336{
337 return pVM->cpum.s.Hyper.ldtr;
338}
339
340CPUMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVM pVM)
341{
342 return pVM->cpum.s.Hyper.dr0;
343}
344
345CPUMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVM pVM)
346{
347 return pVM->cpum.s.Hyper.dr1;
348}
349
350CPUMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVM pVM)
351{
352 return pVM->cpum.s.Hyper.dr2;
353}
354
355CPUMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVM pVM)
356{
357 return pVM->cpum.s.Hyper.dr3;
358}
359
360CPUMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVM pVM)
361{
362 return pVM->cpum.s.Hyper.dr6;
363}
364
365CPUMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVM pVM)
366{
367 return pVM->cpum.s.Hyper.dr7;
368}
369
370
371/**
372 * Gets the pointer to the internal CPUMCTXCORE structure.
373 * This is only for reading in order to save a few calls.
374 *
375 * @param pVM Handle to the virtual machine.
376 */
377CPUMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVM pVM)
378{
379 return CPUMCTX2CORE(&pVM->cpum.s.Guest);
380}
381
382
383/**
384 * Sets the guest context core registers.
385 *
386 * @param pVM Handle to the virtual machine.
387 * @param pCtxCore The new context core values.
388 */
389CPUMDECL(void) CPUMSetGuestCtxCore(PVM pVM, PCCPUMCTXCORE pCtxCore)
390{
391 /** @todo #1410 requires selectors to be checked. */
392
393 PCPUMCTXCORE pCtxCoreDst CPUMCTX2CORE(&pVM->cpum.s.Guest);
394 *pCtxCoreDst = *pCtxCore;
395}
396
397
398/**
399 * Queries the pointer to the internal CPUMCTX structure
400 *
401 * @returns VBox status code.
402 * @param pVM Handle to the virtual machine.
403 * @param ppCtx Receives the CPUMCTX pointer when successful.
404 */
405CPUMDECL(int) CPUMQueryGuestCtxPtr(PVM pVM, PCPUMCTX *ppCtx)
406{
407 *ppCtx = &pVM->cpum.s.Guest;
408 return VINF_SUCCESS;
409}
410
411
412CPUMDECL(int) CPUMSetGuestGDTR(PVM pVM, uint32_t addr, uint16_t limit)
413{
414 pVM->cpum.s.Guest.gdtr.cbGdt = limit;
415 pVM->cpum.s.Guest.gdtr.pGdt = addr;
416 pVM->cpum.s.fChanged |= CPUM_CHANGED_GDTR;
417 return VINF_SUCCESS;
418}
419
420CPUMDECL(int) CPUMSetGuestIDTR(PVM pVM, uint32_t addr, uint16_t limit)
421{
422 pVM->cpum.s.Guest.idtr.cbIdt = limit;
423 pVM->cpum.s.Guest.idtr.pIdt = addr;
424 pVM->cpum.s.fChanged |= CPUM_CHANGED_IDTR;
425 return VINF_SUCCESS;
426}
427
428CPUMDECL(int) CPUMSetGuestTR(PVM pVM, uint16_t tr)
429{
430 pVM->cpum.s.Guest.tr = tr;
431 pVM->cpum.s.fChanged |= CPUM_CHANGED_TR;
432 return VINF_SUCCESS;
433}
434
435CPUMDECL(int) CPUMSetGuestLDTR(PVM pVM, uint16_t ldtr)
436{
437 pVM->cpum.s.Guest.ldtr = ldtr;
438 pVM->cpum.s.fChanged |= CPUM_CHANGED_LDTR;
439 return VINF_SUCCESS;
440}
441
442
443CPUMDECL(int) CPUMSetGuestCR0(PVM pVM, uint32_t cr0)
444{
445 if ( (cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE))
446 != (pVM->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)))
447 pVM->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
448 pVM->cpum.s.fChanged |= CPUM_CHANGED_CR0;
449 pVM->cpum.s.Guest.cr0 = cr0 | X86_CR0_ET;
450 return VINF_SUCCESS;
451}
452
453CPUMDECL(int) CPUMSetGuestCR2(PVM pVM, uint32_t cr2)
454{
455 pVM->cpum.s.Guest.cr2 = cr2;
456 return VINF_SUCCESS;
457}
458
459CPUMDECL(int) CPUMSetGuestCR3(PVM pVM, uint32_t cr3)
460{
461 pVM->cpum.s.Guest.cr3 = cr3;
462 pVM->cpum.s.fChanged |= CPUM_CHANGED_CR3;
463 return VINF_SUCCESS;
464}
465
466CPUMDECL(int) CPUMSetGuestCR4(PVM pVM, uint32_t cr4)
467{
468 if ( (cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE))
469 != (pVM->cpum.s.Guest.cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE)))
470 pVM->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
471 pVM->cpum.s.fChanged |= CPUM_CHANGED_CR4;
472 if (!CPUMSupportsFXSR(pVM))
473 cr4 &= ~X86_CR4_OSFSXR;
474 pVM->cpum.s.Guest.cr4 = cr4;
475 return VINF_SUCCESS;
476}
477
478CPUMDECL(int) CPUMSetGuestEFlags(PVM pVM, uint32_t eflags)
479{
480 pVM->cpum.s.Guest.eflags.u32 = eflags;
481 return VINF_SUCCESS;
482}
483
484CPUMDECL(int) CPUMSetGuestEIP(PVM pVM, uint32_t eip)
485{
486 pVM->cpum.s.Guest.eip = eip;
487 return VINF_SUCCESS;
488}
489
490CPUMDECL(int) CPUMSetGuestEAX(PVM pVM, uint32_t eax)
491{
492 pVM->cpum.s.Guest.eax = eax;
493 return VINF_SUCCESS;
494}
495
496CPUMDECL(int) CPUMSetGuestEBX(PVM pVM, uint32_t ebx)
497{
498 pVM->cpum.s.Guest.ebx = ebx;
499 return VINF_SUCCESS;
500}
501
502CPUMDECL(int) CPUMSetGuestECX(PVM pVM, uint32_t ecx)
503{
504 pVM->cpum.s.Guest.ecx = ecx;
505 return VINF_SUCCESS;
506}
507
508CPUMDECL(int) CPUMSetGuestEDX(PVM pVM, uint32_t edx)
509{
510 pVM->cpum.s.Guest.edx = edx;
511 return VINF_SUCCESS;
512}
513
514CPUMDECL(int) CPUMSetGuestESP(PVM pVM, uint32_t esp)
515{
516 pVM->cpum.s.Guest.esp = esp;
517 return VINF_SUCCESS;
518}
519
520CPUMDECL(int) CPUMSetGuestEBP(PVM pVM, uint32_t ebp)
521{
522 pVM->cpum.s.Guest.ebp = ebp;
523 return VINF_SUCCESS;
524}
525
526CPUMDECL(int) CPUMSetGuestESI(PVM pVM, uint32_t esi)
527{
528 pVM->cpum.s.Guest.esi = esi;
529 return VINF_SUCCESS;
530}
531
532CPUMDECL(int) CPUMSetGuestEDI(PVM pVM, uint32_t edi)
533{
534 pVM->cpum.s.Guest.edi = edi;
535 return VINF_SUCCESS;
536}
537
538CPUMDECL(int) CPUMSetGuestSS(PVM pVM, uint16_t ss)
539{
540 pVM->cpum.s.Guest.ss = ss;
541 return VINF_SUCCESS;
542}
543
544CPUMDECL(int) CPUMSetGuestCS(PVM pVM, uint16_t cs)
545{
546 pVM->cpum.s.Guest.cs = cs;
547 return VINF_SUCCESS;
548}
549
550CPUMDECL(int) CPUMSetGuestDS(PVM pVM, uint16_t ds)
551{
552 pVM->cpum.s.Guest.ds = ds;
553 return VINF_SUCCESS;
554}
555
556CPUMDECL(int) CPUMSetGuestES(PVM pVM, uint16_t es)
557{
558 pVM->cpum.s.Guest.es = es;
559 return VINF_SUCCESS;
560}
561
562CPUMDECL(int) CPUMSetGuestFS(PVM pVM, uint16_t fs)
563{
564 pVM->cpum.s.Guest.fs = fs;
565 return VINF_SUCCESS;
566}
567
568CPUMDECL(int) CPUMSetGuestGS(PVM pVM, uint16_t gs)
569{
570 pVM->cpum.s.Guest.gs = gs;
571 return VINF_SUCCESS;
572}
573
574
575CPUMDECL(uint32_t) CPUMGetGuestIDTR(PVM pVM, uint16_t *pcbLimit)
576{
577 if (pcbLimit)
578 *pcbLimit = pVM->cpum.s.Guest.idtr.cbIdt;
579 return pVM->cpum.s.Guest.idtr.pIdt;
580}
581
582CPUMDECL(RTSEL) CPUMGetGuestTR(PVM pVM)
583{
584 return pVM->cpum.s.Guest.tr;
585}
586
587CPUMDECL(RTSEL) CPUMGetGuestCS(PVM pVM)
588{
589 return pVM->cpum.s.Guest.cs;
590}
591
592CPUMDECL(RTSEL) CPUMGetGuestDS(PVM pVM)
593{
594 return pVM->cpum.s.Guest.ds;
595}
596
597CPUMDECL(RTSEL) CPUMGetGuestES(PVM pVM)
598{
599 return pVM->cpum.s.Guest.es;
600}
601
602CPUMDECL(RTSEL) CPUMGetGuestFS(PVM pVM)
603{
604 return pVM->cpum.s.Guest.fs;
605}
606
607CPUMDECL(RTSEL) CPUMGetGuestGS(PVM pVM)
608{
609 return pVM->cpum.s.Guest.gs;
610}
611
612CPUMDECL(RTSEL) CPUMGetGuestSS(PVM pVM)
613{
614 return pVM->cpum.s.Guest.ss;
615}
616
617CPUMDECL(RTSEL) CPUMGetGuestLDTR(PVM pVM)
618{
619 return pVM->cpum.s.Guest.ldtr;
620}
621
622
623CPUMDECL(uint32_t) CPUMGetGuestCR0(PVM pVM)
624{
625 return pVM->cpum.s.Guest.cr0;
626}
627
628CPUMDECL(uint32_t) CPUMGetGuestCR2(PVM pVM)
629{
630 return pVM->cpum.s.Guest.cr2;
631}
632
633CPUMDECL(uint32_t) CPUMGetGuestCR3(PVM pVM)
634{
635 return pVM->cpum.s.Guest.cr3;
636}
637
638CPUMDECL(uint32_t) CPUMGetGuestCR4(PVM pVM)
639{
640 return pVM->cpum.s.Guest.cr4;
641}
642
643CPUMDECL(void) CPUMGetGuestGDTR(PVM pVM, PVBOXGDTR pGDTR)
644{
645 *pGDTR = pVM->cpum.s.Guest.gdtr;
646}
647
648CPUMDECL(uint32_t) CPUMGetGuestEIP(PVM pVM)
649{
650 return pVM->cpum.s.Guest.eip;
651}
652
653CPUMDECL(uint32_t) CPUMGetGuestEAX(PVM pVM)
654{
655 return pVM->cpum.s.Guest.eax;
656}
657
658CPUMDECL(uint32_t) CPUMGetGuestEBX(PVM pVM)
659{
660 return pVM->cpum.s.Guest.ebx;
661}
662
663CPUMDECL(uint32_t) CPUMGetGuestECX(PVM pVM)
664{
665 return pVM->cpum.s.Guest.ecx;
666}
667
668CPUMDECL(uint32_t) CPUMGetGuestEDX(PVM pVM)
669{
670 return pVM->cpum.s.Guest.edx;
671}
672
673CPUMDECL(uint32_t) CPUMGetGuestESI(PVM pVM)
674{
675 return pVM->cpum.s.Guest.esi;
676}
677
678CPUMDECL(uint32_t) CPUMGetGuestEDI(PVM pVM)
679{
680 return pVM->cpum.s.Guest.edi;
681}
682
683CPUMDECL(uint32_t) CPUMGetGuestESP(PVM pVM)
684{
685 return pVM->cpum.s.Guest.esp;
686}
687
688CPUMDECL(uint32_t) CPUMGetGuestEBP(PVM pVM)
689{
690 return pVM->cpum.s.Guest.ebp;
691}
692
693CPUMDECL(uint32_t) CPUMGetGuestEFlags(PVM pVM)
694{
695 return pVM->cpum.s.Guest.eflags.u32;
696}
697
698CPUMDECL(CPUMSELREGHID *) CPUMGetGuestTRHid(PVM pVM)
699{
700 return &pVM->cpum.s.Guest.trHid;
701}
702
703//@todo: crx should be an array
704CPUMDECL(int) CPUMGetGuestCRx(PVM pVM, uint32_t iReg, uint32_t *pValue)
705{
706 switch (iReg)
707 {
708 case USE_REG_CR0:
709 *pValue = pVM->cpum.s.Guest.cr0;
710 break;
711 case USE_REG_CR2:
712 *pValue = pVM->cpum.s.Guest.cr2;
713 break;
714 case USE_REG_CR3:
715 *pValue = pVM->cpum.s.Guest.cr3;
716 break;
717 case USE_REG_CR4:
718 *pValue = pVM->cpum.s.Guest.cr4;
719 break;
720 default:
721 return VERR_INVALID_PARAMETER;
722 }
723 return VINF_SUCCESS;
724}
725
726CPUMDECL(RTUINTREG) CPUMGetGuestDR0(PVM pVM)
727{
728 return pVM->cpum.s.Guest.dr0;
729}
730
731CPUMDECL(RTUINTREG) CPUMGetGuestDR1(PVM pVM)
732{
733 return pVM->cpum.s.Guest.dr1;
734}
735
736CPUMDECL(RTUINTREG) CPUMGetGuestDR2(PVM pVM)
737{
738 return pVM->cpum.s.Guest.dr2;
739}
740
741CPUMDECL(RTUINTREG) CPUMGetGuestDR3(PVM pVM)
742{
743 return pVM->cpum.s.Guest.dr3;
744}
745
746CPUMDECL(RTUINTREG) CPUMGetGuestDR6(PVM pVM)
747{
748 return pVM->cpum.s.Guest.dr6;
749}
750
751CPUMDECL(RTUINTREG) CPUMGetGuestDR7(PVM pVM)
752{
753 return pVM->cpum.s.Guest.dr7;
754}
755
756/** @todo drx should be an array */
757CPUMDECL(int) CPUMGetGuestDRx(PVM pVM, uint32_t iReg, uint32_t *pValue)
758{
759 switch (iReg)
760 {
761 case USE_REG_DR0:
762 *pValue = pVM->cpum.s.Guest.dr0;
763 break;
764 case USE_REG_DR1:
765 *pValue = pVM->cpum.s.Guest.dr1;
766 break;
767 case USE_REG_DR2:
768 *pValue = pVM->cpum.s.Guest.dr2;
769 break;
770 case USE_REG_DR3:
771 *pValue = pVM->cpum.s.Guest.dr3;
772 break;
773 case USE_REG_DR4:
774 case USE_REG_DR6:
775 *pValue = pVM->cpum.s.Guest.dr6;
776 break;
777 case USE_REG_DR5:
778 case USE_REG_DR7:
779 *pValue = pVM->cpum.s.Guest.dr7;
780 break;
781
782 default:
783 return VERR_INVALID_PARAMETER;
784 }
785 return VINF_SUCCESS;
786}
787
788/**
789 * Gets a CpuId leaf.
790 *
791 * @param pVM The VM handle.
792 * @param iLeaf The CPUID leaf to get.
793 * @param pEax Where to store the EAX value.
794 * @param pEbx Where to store the EBX value.
795 * @param pEcx Where to store the ECX value.
796 * @param pEdx Where to store the EDX value.
797 */
798CPUMDECL(void) CPUMGetGuestCpuId(PVM pVM, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx)
799{
800 PCCPUMCPUID pCpuId;
801 if (iLeaf < ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
802 pCpuId = &pVM->cpum.s.aGuestCpuIdStd[iLeaf];
803 else if (iLeaf - UINT32_C(0x80000000) < ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
804 pCpuId = &pVM->cpum.s.aGuestCpuIdExt[iLeaf - UINT32_C(0x80000000)];
805 else
806 pCpuId = &pVM->cpum.s.GuestCpuIdDef;
807
808 *pEax = pCpuId->eax;
809 *pEbx = pCpuId->ebx;
810 *pEcx = pCpuId->ecx;
811 *pEdx = pCpuId->edx;
812 Log2(("CPUMGetGuestCpuId: iLeaf=%#010x %RX32 %RX32 %RX32 %RX32\n", iLeaf, *pEax, *pEbx, *pEcx, *pEdx));
813}
814
815/**
816 * Gets a pointer to the array of standard CPUID leafs.
817 *
818 * CPUMGetGuestCpuIdStdMax() give the size of the array.
819 *
820 * @returns Pointer to the standard CPUID leafs (read-only).
821 * @param pVM The VM handle.
822 * @remark Intended for PATM.
823 */
824CPUMDECL(GCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdStdGCPtr(PVM pVM)
825{
826 return GCPTRTYPE(PCCPUMCPUID)VM_GUEST_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdStd[0]);
827}
828
829/**
830 * Gets a pointer to the array of extended CPUID leafs.
831 *
832 * CPUMGetGuestCpuIdExtMax() give the size of the array.
833 *
834 * @returns Pointer to the extended CPUID leafs (read-only).
835 * @param pVM The VM handle.
836 * @remark Intended for PATM.
837 */
838CPUMDECL(GCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdExtGCPtr(PVM pVM)
839{
840 return GCPTRTYPE(PCCPUMCPUID)VM_GUEST_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
841}
842
843/**
844 * Gets a pointer to the default CPUID leaf.
845 *
846 * @returns Pointer to the default CPUID leaf (read-only).
847 * @param pVM The VM handle.
848 * @remark Intended for PATM.
849 */
850CPUMDECL(GCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdDefGCPtr(PVM pVM)
851{
852 return GCPTRTYPE(PCCPUMCPUID)VM_GUEST_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
853}
854
855/**
856 * Gets a number of standard CPUID leafs.
857 *
858 * @returns Number of leafs.
859 * @param pVM The VM handle.
860 * @remark Intended for PATM.
861 */
862CPUMDECL(uint32_t) CPUMGetGuestCpuIdStdMax(PVM pVM)
863{
864 return ELEMENTS(pVM->cpum.s.aGuestCpuIdStd);
865}
866
867/**
868 * Gets a number of extended CPUID leafs.
869 *
870 * @returns Number of leafs.
871 * @param pVM The VM handle.
872 * @remark Intended for PATM.
873 */
874CPUMDECL(uint32_t) CPUMGetGuestCpuIdExtMax(PVM pVM)
875{
876 return ELEMENTS(pVM->cpum.s.aGuestCpuIdStd);
877}
878
879/**
880 * Sets a CPUID feature bit.
881 *
882 * @param pVM The VM Handle.
883 * @param enmFeature The feature to set.
884 */
885CPUMDECL(void) CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
886{
887 switch (enmFeature)
888 {
889 /*
890 * Set the APIC bit in both feature masks.
891 */
892 case CPUMCPUIDFEATURE_APIC:
893 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
894 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_APIC;
895 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
896 && pVM->cpum.s.aGuestCpuIdExt[1].edx)
897 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_APIC;
898 Log(("CPUMSetGuestCpuIdFeature: Enabled APIC\n"));
899 break;
900
901 /*
902 * Set the sysenter/sysexit bit in both feature masks.
903 * Assumes the caller knows what it's doing! (host must support these)
904 */
905 case CPUMCPUIDFEATURE_SEP:
906 {
907 uint32_t ulEdx, ulDummy;
908
909 ASMCpuId(1, &ulDummy, &ulDummy, &ulDummy, &ulEdx);
910 if (!(ulEdx & X86_CPUID_FEATURE_EDX_SEP))
911 {
912 AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
913 return;
914 }
915
916 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
917 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_SEP;
918 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
919 && pVM->cpum.s.aGuestCpuIdExt[1].edx)
920 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_SEP;
921 Log(("CPUMSetGuestCpuIdFeature: Enabled sysenter/exit\n"));
922 break;
923 }
924
925 default:
926 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
927 break;
928 }
929}
930
931/**
932 * Clears a CPUID feature bit.
933 *
934 * @param pVM The VM Handle.
935 * @param enmFeature The feature to clear.
936 */
937CPUMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
938{
939 switch (enmFeature)
940 {
941 /*
942 * Set the APIC bit in both feature masks.
943 */
944 case CPUMCPUIDFEATURE_APIC:
945 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
946 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_APIC;
947 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
948 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
949 Log(("CPUMSetGuestCpuIdFeature: Disabled APIC\n"));
950 break;
951
952 default:
953 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
954 break;
955 }
956}
957
958
959
960CPUMDECL(int) CPUMSetGuestDR0(PVM pVM, RTGCUINTREG uDr0)
961{
962 pVM->cpum.s.Guest.dr0 = uDr0;
963 return CPUMRecalcHyperDRx(pVM);
964}
965
966CPUMDECL(int) CPUMSetGuestDR1(PVM pVM, RTGCUINTREG uDr1)
967{
968 pVM->cpum.s.Guest.dr1 = uDr1;
969 return CPUMRecalcHyperDRx(pVM);
970}
971
972CPUMDECL(int) CPUMSetGuestDR2(PVM pVM, RTGCUINTREG uDr2)
973{
974 pVM->cpum.s.Guest.dr2 = uDr2;
975 return CPUMRecalcHyperDRx(pVM);
976}
977
978CPUMDECL(int) CPUMSetGuestDR3(PVM pVM, RTGCUINTREG uDr3)
979{
980 pVM->cpum.s.Guest.dr3 = uDr3;
981 return CPUMRecalcHyperDRx(pVM);
982}
983
984CPUMDECL(int) CPUMSetGuestDR6(PVM pVM, RTGCUINTREG uDr6)
985{
986 pVM->cpum.s.Guest.dr6 = uDr6;
987 return CPUMRecalcHyperDRx(pVM);
988}
989
990CPUMDECL(int) CPUMSetGuestDR7(PVM pVM, RTGCUINTREG uDr7)
991{
992 pVM->cpum.s.Guest.dr7 = uDr7;
993 return CPUMRecalcHyperDRx(pVM);
994}
995
996/** @todo drx should be an array */
997CPUMDECL(int) CPUMSetGuestDRx(PVM pVM, uint32_t iReg, uint32_t Value)
998{
999 switch (iReg)
1000 {
1001 case USE_REG_DR0:
1002 pVM->cpum.s.Guest.dr0 = Value;
1003 break;
1004 case USE_REG_DR1:
1005 pVM->cpum.s.Guest.dr1 = Value;
1006 break;
1007 case USE_REG_DR2:
1008 pVM->cpum.s.Guest.dr2 = Value;
1009 break;
1010 case USE_REG_DR3:
1011 pVM->cpum.s.Guest.dr3 = Value;
1012 break;
1013 case USE_REG_DR4:
1014 case USE_REG_DR6:
1015 pVM->cpum.s.Guest.dr6 = Value;
1016 break;
1017 case USE_REG_DR5:
1018 case USE_REG_DR7:
1019 pVM->cpum.s.Guest.dr7 = Value;
1020 break;
1021
1022 default:
1023 return VERR_INVALID_PARAMETER;
1024 }
1025 return CPUMRecalcHyperDRx(pVM);
1026}
1027
1028
1029/**
1030 * Recalculates the hypvervisor DRx register values based on
1031 * current guest registers and DBGF breakpoints.
1032 *
1033 * This is called whenever a guest DRx register is modified and when DBGF
1034 * sets a hardware breakpoint. In guest context this function will reload
1035 * any (hyper) DRx registers which comes out with a different value.
1036 *
1037 * @returns VINF_SUCCESS.
1038 * @param pVM The VM handle.
1039 */
1040CPUMDECL(int) CPUMRecalcHyperDRx(PVM pVM)
1041{
1042 /*
1043 * Compare the DR7s first.
1044 *
1045 * We only care about the enabled flags. The GE and LE flags are always
1046 * set and we don't care if the guest doesn't set them. GD is virtualized
1047 * when we dispatch #DB, we never enable it.
1048 */
1049 const RTGCUINTREG uDbgfDr7 = DBGFBpGetDR7(pVM);
1050#ifdef CPUM_VIRTUALIZE_DRX
1051 const RTGCUINTREG uGstDr7 = CPUMGetGuestDR7(pVM);
1052#else
1053 const RTGCUINTREG uGstDr7 = 0;
1054#endif
1055 if ((uGstDr7 | uDbgfDr7) & X86_DR7_ENABLED_MASK)
1056 {
1057 /*
1058 * Ok, something is enabled. Recalc each of the breakpoints.
1059 * Straight forward code, not optimized/minimized in any way.
1060 */
1061 RTGCUINTREG uNewDr7 = X86_DR7_GE | X86_DR7_LE | X86_DR7_MB1_MASK;
1062
1063 /* bp 0 */
1064 RTGCUINTREG uNewDr0;
1065 if (uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0))
1066 {
1067 uNewDr7 |= uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
1068 uNewDr0 = DBGFBpGetDR0(pVM);
1069 }
1070 else if (uGstDr7 & (X86_DR7_L0 | X86_DR7_G0))
1071 {
1072 uNewDr7 |= uGstDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
1073 uNewDr0 = CPUMGetGuestDR0(pVM);
1074 }
1075 else
1076 uNewDr0 = pVM->cpum.s.Hyper.dr0;
1077
1078 /* bp 1 */
1079 RTGCUINTREG uNewDr1;
1080 if (uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1))
1081 {
1082 uNewDr7 |= uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
1083 uNewDr1 = DBGFBpGetDR1(pVM);
1084 }
1085 else if (uGstDr7 & (X86_DR7_L1 | X86_DR7_G1))
1086 {
1087 uNewDr7 |= uGstDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
1088 uNewDr1 = CPUMGetGuestDR1(pVM);
1089 }
1090 else
1091 uNewDr1 = pVM->cpum.s.Hyper.dr1;
1092
1093 /* bp 2 */
1094 RTGCUINTREG uNewDr2;
1095 if (uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2))
1096 {
1097 uNewDr7 |= uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
1098 uNewDr2 = DBGFBpGetDR2(pVM);
1099 }
1100 else if (uGstDr7 & (X86_DR7_L2 | X86_DR7_G2))
1101 {
1102 uNewDr7 |= uGstDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
1103 uNewDr2 = CPUMGetGuestDR2(pVM);
1104 }
1105 else
1106 uNewDr2 = pVM->cpum.s.Hyper.dr2;
1107
1108 /* bp 3 */
1109 RTGCUINTREG uNewDr3;
1110 if (uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3))
1111 {
1112 uNewDr7 |= uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
1113 uNewDr3 = DBGFBpGetDR3(pVM);
1114 }
1115 else if (uGstDr7 & (X86_DR7_L3 | X86_DR7_G3))
1116 {
1117 uNewDr7 |= uGstDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
1118 uNewDr3 = CPUMGetGuestDR3(pVM);
1119 }
1120 else
1121 uNewDr3 = pVM->cpum.s.Hyper.dr3;
1122
1123 /*
1124 * Apply the updates.
1125 */
1126#ifdef IN_GC
1127 if (!(pVM->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS))
1128 {
1129 /** @todo save host DBx registers. */
1130 }
1131#endif
1132 pVM->cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS;
1133 if (uNewDr3 != pVM->cpum.s.Hyper.dr3)
1134 CPUMSetHyperDR3(pVM, uNewDr3);
1135 if (uNewDr2 != pVM->cpum.s.Hyper.dr2)
1136 CPUMSetHyperDR2(pVM, uNewDr2);
1137 if (uNewDr1 != pVM->cpum.s.Hyper.dr1)
1138 CPUMSetHyperDR1(pVM, uNewDr1);
1139 if (uNewDr0 != pVM->cpum.s.Hyper.dr0)
1140 CPUMSetHyperDR0(pVM, uNewDr0);
1141 if (uNewDr7 != pVM->cpum.s.Hyper.dr7)
1142 CPUMSetHyperDR7(pVM, uNewDr7);
1143 }
1144 else
1145 {
1146#ifdef IN_GC
1147 if (pVM->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS)
1148 {
1149 /** @todo restore host DBx registers. */
1150 }
1151#endif
1152 pVM->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS;
1153 }
1154 Log2(("CPUMRecalcHyperDRx: fUseFlags=%#x %RGr %RGr %RGr %RGr %RGr %RGr\n",
1155 pVM->cpum.s.fUseFlags, pVM->cpum.s.Hyper.dr0, pVM->cpum.s.Hyper.dr1,
1156 pVM->cpum.s.Hyper.dr2, pVM->cpum.s.Hyper.dr3, pVM->cpum.s.Hyper.dr6,
1157 pVM->cpum.s.Hyper.dr7));
1158
1159 return VINF_SUCCESS;
1160}
1161
1162#ifndef IN_RING0 /** @todo I don't think we need this in R0, so move it to CPUMAll.cpp? */
1163
1164/**
1165 * Transforms the guest CPU state to raw-ring mode.
1166 *
1167 * This function will change the any of the cs and ss register with DPL=0 to DPL=1.
1168 *
1169 * @returns VBox status. (recompiler failure)
1170 * @param pVM VM handle.
1171 * @param pCtxCore The context core (for trap usage).
1172 * @see @ref pg_raw
1173 */
1174CPUMDECL(int) CPUMRawEnter(PVM pVM, PCPUMCTXCORE pCtxCore)
1175{
1176 Assert(!pVM->cpum.s.fRawEntered);
1177 if (!pCtxCore)
1178 pCtxCore = CPUMCTX2CORE(&pVM->cpum.s.Guest);
1179
1180 /*
1181 * Are we in Ring-0?
1182 */
1183 if ( pCtxCore->ss && (pCtxCore->ss & X86_SEL_RPL) == 0
1184 && !pCtxCore->eflags.Bits.u1VM)
1185 {
1186 /*
1187 * Enter execution mode.
1188 */
1189 PATMRawEnter(pVM, pCtxCore);
1190
1191 /*
1192 * Set CPL to Ring-1.
1193 */
1194 pCtxCore->ss |= 1;
1195 if (pCtxCore->cs && (pCtxCore->cs & X86_SEL_RPL) == 0)
1196 pCtxCore->cs |= 1;
1197 }
1198 else
1199 {
1200 AssertMsg((pCtxCore->ss & X86_SEL_RPL) >= 2 || pCtxCore->eflags.Bits.u1VM,
1201 ("ring-1 code not supported\n"));
1202 /*
1203 * PATM takes care of IOPL and IF flags for Ring-3 and Ring-2 code as well.
1204 */
1205 PATMRawEnter(pVM, pCtxCore);
1206 }
1207
1208 /*
1209 * Assert sanity.
1210 */
1211 AssertMsg((pCtxCore->eflags.u32 & X86_EFL_IF), ("X86_EFL_IF is clear\n"));
1212 AssertReleaseMsg( pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss & X86_SEL_RPL)
1213 || pCtxCore->eflags.Bits.u1VM,
1214 ("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss & X86_SEL_RPL));
1215 Assert((pVM->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)) == (X86_CR0_PG | X86_CR0_PE | X86_CR0_WP));
1216 pCtxCore->eflags.u32 |= X86_EFL_IF; /* paranoia */
1217
1218 pVM->cpum.s.fRawEntered = true;
1219 return VINF_SUCCESS;
1220}
1221
1222
1223/**
1224 * Transforms the guest CPU state from raw-ring mode to correct values.
1225 *
1226 * This function will change any selector registers with DPL=1 to DPL=0.
1227 *
1228 * @returns Adjusted rc.
1229 * @param pVM VM handle.
1230 * @param rc Raw mode return code
1231 * @param pCtxCore The context core (for trap usage).
1232 * @see @ref pg_raw
1233 */
1234CPUMDECL(int) CPUMRawLeave(PVM pVM, PCPUMCTXCORE pCtxCore, int rc)
1235{
1236 /*
1237 * Don't leave if we've already left (in GC).
1238 */
1239 Assert(pVM->cpum.s.fRawEntered);
1240 if (!pVM->cpum.s.fRawEntered)
1241 return rc;
1242 pVM->cpum.s.fRawEntered = false;
1243
1244 PCPUMCTX pCtx = &pVM->cpum.s.Guest;
1245 if (!pCtxCore)
1246 pCtxCore = CPUMCTX2CORE(pCtx);
1247 Assert(pCtxCore->eflags.Bits.u1VM || (pCtxCore->ss & X86_SEL_RPL));
1248 AssertMsg(pCtxCore->eflags.Bits.u1VM || pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss & X86_SEL_RPL),
1249 ("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss & X86_SEL_RPL));
1250
1251 /*
1252 * Are we executing in raw ring-1?
1253 */
1254 if ( (pCtxCore->ss & X86_SEL_RPL) == 1
1255 && !pCtxCore->eflags.Bits.u1VM)
1256 {
1257 /*
1258 * Leave execution mode.
1259 */
1260 PATMRawLeave(pVM, pCtxCore, rc);
1261 /* Not quite sure if this is really required, but shouldn't harm (too much anyways). */
1262 /** @todo See what happens if we remove this. */
1263 if ((pCtxCore->ds & X86_SEL_RPL) == 1)
1264 pCtxCore->ds &= ~X86_SEL_RPL;
1265 if ((pCtxCore->es & X86_SEL_RPL) == 1)
1266 pCtxCore->es &= ~X86_SEL_RPL;
1267 if ((pCtxCore->fs & X86_SEL_RPL) == 1)
1268 pCtxCore->fs &= ~X86_SEL_RPL;
1269 if ((pCtxCore->gs & X86_SEL_RPL) == 1)
1270 pCtxCore->gs &= ~X86_SEL_RPL;
1271
1272 /*
1273 * Ring-1 selector => Ring-0.
1274 */
1275 pCtxCore->ss &= ~X86_SEL_RPL;
1276 if ((pCtxCore->cs & X86_SEL_RPL) == 1)
1277 pCtxCore->cs &= ~X86_SEL_RPL;
1278 }
1279 else
1280 {
1281 /*
1282 * PATM is taking care of the IOPL and IF flags for us.
1283 */
1284 PATMRawLeave(pVM, pCtxCore, rc);
1285 if (!pCtxCore->eflags.Bits.u1VM)
1286 {
1287 /** @todo See what happens if we remove this. */
1288 if ((pCtxCore->ds & X86_SEL_RPL) == 1)
1289 pCtxCore->ds &= ~X86_SEL_RPL;
1290 if ((pCtxCore->es & X86_SEL_RPL) == 1)
1291 pCtxCore->es &= ~X86_SEL_RPL;
1292 if ((pCtxCore->fs & X86_SEL_RPL) == 1)
1293 pCtxCore->fs &= ~X86_SEL_RPL;
1294 if ((pCtxCore->gs & X86_SEL_RPL) == 1)
1295 pCtxCore->gs &= ~X86_SEL_RPL;
1296 }
1297 }
1298
1299 return rc;
1300}
1301
1302/**
1303 * Updates the EFLAGS while we're in raw-mode.
1304 *
1305 * @param pVM The VM handle.
1306 * @param pCtxCore The context core.
1307 * @param eflags The new EFLAGS value.
1308 */
1309CPUMDECL(void) CPUMRawSetEFlags(PVM pVM, PCPUMCTXCORE pCtxCore, uint32_t eflags)
1310{
1311 if (!pVM->cpum.s.fRawEntered)
1312 {
1313 pCtxCore->eflags.u32 = eflags;
1314 return;
1315 }
1316 PATMRawSetEFlags(pVM, pCtxCore, eflags);
1317}
1318
1319#endif /* !IN_RING0 */
1320
1321/**
1322 * Gets the EFLAGS while we're in raw-mode.
1323 *
1324 * @returns The eflags.
1325 * @param pVM The VM handle.
1326 * @param pCtxCore The context core.
1327 */
1328CPUMDECL(uint32_t) CPUMRawGetEFlags(PVM pVM, PCPUMCTXCORE pCtxCore)
1329{
1330#ifdef IN_RING0
1331 return pCtxCore->eflags.u32;
1332#else
1333 if (!pVM->cpum.s.fRawEntered)
1334 return pCtxCore->eflags.u32;
1335 return PATMRawGetEFlags(pVM, pCtxCore);
1336#endif
1337}
1338
1339
1340
1341
1342/**
1343 * Gets and resets the changed flags (CPUM_CHANGED_*).
1344 * Only REM should call this function.
1345 *
1346 * @returns The changed flags.
1347 * @param pVM The VM handle.
1348 */
1349CPUMDECL(unsigned) CPUMGetAndClearChangedFlagsREM(PVM pVM)
1350{
1351 unsigned fFlags = pVM->cpum.s.fChanged;
1352 pVM->cpum.s.fChanged = 0;
1353 /** @todo change the switcher to use the fChanged flags. */
1354 if (pVM->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
1355 {
1356 fFlags |= CPUM_CHANGED_FPU_REM;
1357 pVM->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
1358 }
1359 return fFlags;
1360}
1361
1362/**
1363 * Sets the specified changed flags (CPUM_CHANGED_*).
1364 *
1365 * @param pVM The VM handle.
1366 */
1367CPUMDECL(void) CPUMSetChangedFlags(PVM pVM, uint32_t fChangedFlags)
1368{
1369 pVM->cpum.s.fChanged |= fChangedFlags;
1370}
1371
1372/**
1373 * Checks if the CPU supports the FXSAVE and FXRSTOR instruction.
1374 * @returns true if supported.
1375 * @returns false if not supported.
1376 * @param pVM The VM handle.
1377 */
1378CPUMDECL(bool) CPUMSupportsFXSR(PVM pVM)
1379{
1380 return pVM->cpum.s.CPUFeatures.edx.u1FXSR != 0;
1381}
1382
1383
1384/**
1385 * Checks if the host OS uses the SYSENTER / SYSEXIT instructions.
1386 * @returns true if used.
1387 * @returns false if not used.
1388 * @param pVM The VM handle.
1389 */
1390CPUMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM)
1391{
1392 return (pVM->cpum.s.fUseFlags & CPUM_USE_SYSENTER) != 0;
1393}
1394
1395
1396/**
1397 * Checks if the host OS uses the SYSCALL / SYSRET instructions.
1398 * @returns true if used.
1399 * @returns false if not used.
1400 * @param pVM The VM handle.
1401 */
1402CPUMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM)
1403{
1404 return (pVM->cpum.s.fUseFlags & CPUM_USE_SYSCALL) != 0;
1405}
1406
1407/**
1408 * Lazily sync in the FPU/XMM state
1409 *
1410 * @returns VBox status code.
1411 * @param pVM VM handle.
1412 */
1413CPUMDECL(int) CPUMHandleLazyFPU(PVM pVM)
1414{
1415 return CPUMHandleLazyFPUAsm(&pVM->cpum.s);
1416}
1417
1418/**
1419 * Restore host FPU/XMM state
1420 *
1421 * @returns VBox status code.
1422 * @param pVM VM handle.
1423 */
1424CPUMDECL(int) CPUMRestoreHostFPUState(PVM pVM)
1425{
1426 Assert(pVM->cpum.s.CPUFeatures.edx.u1FXSR);
1427 return CPUMRestoreHostFPUStateAsm(&pVM->cpum.s);
1428}
1429
1430/**
1431 * Checks if we activated the FPU/XMM state of the guest OS
1432 * @returns true if we did.
1433 * @returns false if not.
1434 * @param pVM The VM handle.
1435 */
1436CPUMDECL(bool) CPUMIsGuestFPUStateActive(PVM pVM)
1437{
1438 return (pVM->cpum.s.fUseFlags & CPUM_USED_FPU) != 0;
1439}
1440
1441/**
1442 * Deactivate the FPU/XMM state of the guest OS
1443 * @param pVM The VM handle.
1444 */
1445CPUMDECL(void) CPUMDeactivateGuestFPUState(PVM pVM)
1446{
1447 pVM->cpum.s.fUseFlags &= ~CPUM_USED_FPU;
1448}
1449
1450/**
1451 * Checks if the hidden selector registers are valid
1452 * @returns true if they are.
1453 * @returns false if not.
1454 * @param pVM The VM handle.
1455 */
1456CPUMDECL(bool) CPUMAreHiddenSelRegsValid(PVM pVM)
1457{
1458 return !!pVM->cpum.s.fValidHiddenSelRegs; /** @todo change fValidHiddenSelRegs to bool! */
1459}
1460
1461/**
1462 * Checks if the hidden selector registers are valid
1463 * @param pVM The VM handle.
1464 * @param fValid Valid or not
1465 */
1466CPUMDECL(void) CPUMSetHiddenSelRegsValid(PVM pVM, bool fValid)
1467{
1468 pVM->cpum.s.fValidHiddenSelRegs = fValid;
1469}
1470
1471/**
1472 * Get the current privilege level of the guest.
1473 *
1474 * @returns cpl
1475 * @param pVM VM Handle.
1476 * @param pRegFrame Trap register frame.
1477 */
1478CPUMDECL(uint32_t) CPUMGetGuestCPL(PVM pVM, PCPUMCTXCORE pCtxCore)
1479{
1480 uint32_t cpl;
1481
1482 if (CPUMAreHiddenSelRegsValid(pVM))
1483 cpl = pCtxCore->ssHid.Attr.n.u2Dpl;
1484 else if (RT_LIKELY(pVM->cpum.s.Guest.cr0 & X86_CR0_PE))
1485 {
1486 if (RT_LIKELY(!pCtxCore->eflags.Bits.u1VM))
1487 {
1488 cpl = (pCtxCore->ss & X86_SEL_RPL);
1489#ifndef IN_RING0
1490 if (cpl == 1)
1491 cpl = 0;
1492#endif
1493 }
1494 else
1495 cpl = 3;
1496 }
1497 else
1498 cpl = 0; /* real mode; cpl is zero */
1499
1500 return cpl;
1501}
1502
1503
1504/**
1505 * Gets the current guest CPU mode.
1506 *
1507 * If paging mode is what you need, check out PGMGetGuestMode().
1508 *
1509 * @returns The CPU mode.
1510 * @param pVM The VM handle.
1511 */
1512CPUMDECL(CPUMMODE) CPUMGetGuestMode(PVM pVM)
1513{
1514 CPUMMODE enmMode;
1515 if (!(pVM->cpum.s.Guest.cr0 & X86_CR0_PE))
1516 enmMode = CPUMMODE_REAL;
1517 else //GUEST64 if (!(pVM->cpum.s.Guest.efer & MSR_K6_EFER_LMA)
1518 enmMode = CPUMMODE_PROTECTED;
1519//GUEST64 else
1520//GUEST64 enmMode = CPUMMODE_LONG;
1521
1522 return enmMode;
1523}
1524
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