VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp@ 72306

Last change on this file since 72306 was 72129, checked in by vboxsync, 7 years ago

CPUMAllRegs.cpp/CPUMRecalcHyperDRx: Added comment regarding misconception of the LE and GE flags. [update]
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File size: 78.9 KB
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1/* $Id: CPUMAllRegs.cpp 72129 2018-05-04 22:43:03Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor(/Manager) - Getters and Setters.
4 */
5
6/*
7 * Copyright (C) 2006-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_CPUM
23#include <VBox/vmm/cpum.h>
24#include <VBox/vmm/patm.h>
25#include <VBox/vmm/dbgf.h>
26#include <VBox/vmm/apic.h>
27#include <VBox/vmm/pgm.h>
28#include <VBox/vmm/mm.h>
29#include <VBox/vmm/em.h>
30#if defined(VBOX_WITH_RAW_MODE) && !defined(IN_RING0)
31# include <VBox/vmm/selm.h>
32#endif
33#include "CPUMInternal.h"
34#include <VBox/vmm/vm.h>
35#include <VBox/err.h>
36#include <VBox/dis.h>
37#include <VBox/log.h>
38#include <VBox/vmm/hm.h>
39#include <VBox/vmm/tm.h>
40#include <iprt/assert.h>
41#include <iprt/asm.h>
42#include <iprt/asm-amd64-x86.h>
43#ifdef IN_RING3
44#include <iprt/thread.h>
45#endif
46
47/** Disable stack frame pointer generation here. */
48#if defined(_MSC_VER) && !defined(DEBUG) && defined(RT_ARCH_X86)
49# pragma optimize("y", off)
50#endif
51
52AssertCompile2MemberOffsets(VM, cpum.s.HostFeatures, cpum.ro.HostFeatures);
53AssertCompile2MemberOffsets(VM, cpum.s.GuestFeatures, cpum.ro.GuestFeatures);
54
55
56/*********************************************************************************************************************************
57* Defined Constants And Macros *
58*********************************************************************************************************************************/
59/**
60 * Converts a CPUMCPU::Guest pointer into a VMCPU pointer.
61 *
62 * @returns Pointer to the Virtual CPU.
63 * @param a_pGuestCtx Pointer to the guest context.
64 */
65#define CPUM_GUEST_CTX_TO_VMCPU(a_pGuestCtx) RT_FROM_MEMBER(a_pGuestCtx, VMCPU, cpum.s.Guest)
66
67/**
68 * Lazily loads the hidden parts of a selector register when using raw-mode.
69 */
70#if defined(VBOX_WITH_RAW_MODE) && !defined(IN_RING0)
71# define CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(a_pVCpu, a_pSReg) \
72 do \
73 { \
74 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(a_pVCpu, a_pSReg)) \
75 cpumGuestLazyLoadHiddenSelectorReg(a_pVCpu, a_pSReg); \
76 } while (0)
77#else
78# define CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(a_pVCpu, a_pSReg) \
79 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(a_pVCpu, a_pSReg));
80#endif
81
82
83
84#ifdef VBOX_WITH_RAW_MODE_NOT_R0
85
86/**
87 * Does the lazy hidden selector register loading.
88 *
89 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
90 * @param pSReg The selector register to lazily load hidden parts of.
91 */
92static void cpumGuestLazyLoadHiddenSelectorReg(PVMCPU pVCpu, PCPUMSELREG pSReg)
93{
94 Assert(!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSReg));
95 Assert(VM_IS_RAW_MODE_ENABLED(pVCpu->CTX_SUFF(pVM)));
96 Assert((uintptr_t)(pSReg - &pVCpu->cpum.s.Guest.es) < X86_SREG_COUNT);
97
98 if (pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
99 {
100 /* V8086 mode - Tightly controlled environment, no question about the limit or flags. */
101 pSReg->Attr.u = 0;
102 pSReg->Attr.n.u4Type = pSReg == &pVCpu->cpum.s.Guest.cs ? X86_SEL_TYPE_ER_ACC : X86_SEL_TYPE_RW_ACC;
103 pSReg->Attr.n.u1DescType = 1; /* code/data segment */
104 pSReg->Attr.n.u2Dpl = 3;
105 pSReg->Attr.n.u1Present = 1;
106 pSReg->u32Limit = 0x0000ffff;
107 pSReg->u64Base = (uint32_t)pSReg->Sel << 4;
108 pSReg->ValidSel = pSReg->Sel;
109 pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
110 /** @todo Check what the accessed bit should be (VT-x and AMD-V). */
111 }
112 else if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
113 {
114 /* Real mode - leave the limit and flags alone here, at least for now. */
115 pSReg->u64Base = (uint32_t)pSReg->Sel << 4;
116 pSReg->ValidSel = pSReg->Sel;
117 pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
118 }
119 else
120 {
121 /* Protected mode - get it from the selector descriptor tables. */
122 if (!(pSReg->Sel & X86_SEL_MASK_OFF_RPL))
123 {
124 Assert(!CPUMIsGuestInLongMode(pVCpu));
125 pSReg->Sel = 0;
126 pSReg->u64Base = 0;
127 pSReg->u32Limit = 0;
128 pSReg->Attr.u = 0;
129 pSReg->ValidSel = 0;
130 pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
131 /** @todo see todo in iemHlpLoadNullDataSelectorProt. */
132 }
133 else
134 SELMLoadHiddenSelectorReg(pVCpu, &pVCpu->cpum.s.Guest, pSReg);
135 }
136}
137
138
139/**
140 * Makes sure the hidden CS and SS selector registers are valid, loading them if
141 * necessary.
142 *
143 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
144 */
145VMM_INT_DECL(void) CPUMGuestLazyLoadHiddenCsAndSs(PVMCPU pVCpu)
146{
147 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
148 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.ss);
149}
150
151
152/**
153 * Loads a the hidden parts of a selector register.
154 *
155 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
156 * @param pSReg The selector register to lazily load hidden parts of.
157 */
158VMM_INT_DECL(void) CPUMGuestLazyLoadHiddenSelectorReg(PVMCPU pVCpu, PCPUMSELREG pSReg)
159{
160 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, pSReg);
161}
162
163#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
164
165
166/**
167 * Obsolete.
168 *
169 * We don't support nested hypervisor context interrupts or traps. Life is much
170 * simpler when we don't. It's also slightly faster at times.
171 *
172 * @param pVCpu The cross context virtual CPU structure.
173 */
174VMMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVMCPU pVCpu)
175{
176 return CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
177}
178
179
180/**
181 * Gets the pointer to the hypervisor CPU context structure of a virtual CPU.
182 *
183 * @param pVCpu The cross context virtual CPU structure.
184 */
185VMMDECL(PCPUMCTX) CPUMGetHyperCtxPtr(PVMCPU pVCpu)
186{
187 return &pVCpu->cpum.s.Hyper;
188}
189
190
191VMMDECL(void) CPUMSetHyperGDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
192{
193 pVCpu->cpum.s.Hyper.gdtr.cbGdt = limit;
194 pVCpu->cpum.s.Hyper.gdtr.pGdt = addr;
195}
196
197
198VMMDECL(void) CPUMSetHyperIDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
199{
200 pVCpu->cpum.s.Hyper.idtr.cbIdt = limit;
201 pVCpu->cpum.s.Hyper.idtr.pIdt = addr;
202}
203
204
205VMMDECL(void) CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3)
206{
207 pVCpu->cpum.s.Hyper.cr3 = cr3;
208
209#ifdef IN_RC
210 /* Update the current CR3. */
211 ASMSetCR3(cr3);
212#endif
213}
214
215VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu)
216{
217 return pVCpu->cpum.s.Hyper.cr3;
218}
219
220
221VMMDECL(void) CPUMSetHyperCS(PVMCPU pVCpu, RTSEL SelCS)
222{
223 pVCpu->cpum.s.Hyper.cs.Sel = SelCS;
224}
225
226
227VMMDECL(void) CPUMSetHyperDS(PVMCPU pVCpu, RTSEL SelDS)
228{
229 pVCpu->cpum.s.Hyper.ds.Sel = SelDS;
230}
231
232
233VMMDECL(void) CPUMSetHyperES(PVMCPU pVCpu, RTSEL SelES)
234{
235 pVCpu->cpum.s.Hyper.es.Sel = SelES;
236}
237
238
239VMMDECL(void) CPUMSetHyperFS(PVMCPU pVCpu, RTSEL SelFS)
240{
241 pVCpu->cpum.s.Hyper.fs.Sel = SelFS;
242}
243
244
245VMMDECL(void) CPUMSetHyperGS(PVMCPU pVCpu, RTSEL SelGS)
246{
247 pVCpu->cpum.s.Hyper.gs.Sel = SelGS;
248}
249
250
251VMMDECL(void) CPUMSetHyperSS(PVMCPU pVCpu, RTSEL SelSS)
252{
253 pVCpu->cpum.s.Hyper.ss.Sel = SelSS;
254}
255
256
257VMMDECL(void) CPUMSetHyperESP(PVMCPU pVCpu, uint32_t u32ESP)
258{
259 pVCpu->cpum.s.Hyper.esp = u32ESP;
260}
261
262
263VMMDECL(void) CPUMSetHyperEDX(PVMCPU pVCpu, uint32_t u32ESP)
264{
265 pVCpu->cpum.s.Hyper.esp = u32ESP;
266}
267
268
269VMMDECL(int) CPUMSetHyperEFlags(PVMCPU pVCpu, uint32_t Efl)
270{
271 pVCpu->cpum.s.Hyper.eflags.u32 = Efl;
272 return VINF_SUCCESS;
273}
274
275
276VMMDECL(void) CPUMSetHyperEIP(PVMCPU pVCpu, uint32_t u32EIP)
277{
278 pVCpu->cpum.s.Hyper.eip = u32EIP;
279}
280
281
282/**
283 * Used by VMMR3RawRunGC to reinitialize the general raw-mode context registers,
284 * EFLAGS and EIP prior to resuming guest execution.
285 *
286 * All general register not given as a parameter will be set to 0. The EFLAGS
287 * register will be set to sane values for C/C++ code execution with interrupts
288 * disabled and IOPL 0.
289 *
290 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
291 * @param u32EIP The EIP value.
292 * @param u32ESP The ESP value.
293 * @param u32EAX The EAX value.
294 * @param u32EDX The EDX value.
295 */
296VMM_INT_DECL(void) CPUMSetHyperState(PVMCPU pVCpu, uint32_t u32EIP, uint32_t u32ESP, uint32_t u32EAX, uint32_t u32EDX)
297{
298 pVCpu->cpum.s.Hyper.eip = u32EIP;
299 pVCpu->cpum.s.Hyper.esp = u32ESP;
300 pVCpu->cpum.s.Hyper.eax = u32EAX;
301 pVCpu->cpum.s.Hyper.edx = u32EDX;
302 pVCpu->cpum.s.Hyper.ecx = 0;
303 pVCpu->cpum.s.Hyper.ebx = 0;
304 pVCpu->cpum.s.Hyper.ebp = 0;
305 pVCpu->cpum.s.Hyper.esi = 0;
306 pVCpu->cpum.s.Hyper.edi = 0;
307 pVCpu->cpum.s.Hyper.eflags.u = X86_EFL_1;
308}
309
310
311VMMDECL(void) CPUMSetHyperTR(PVMCPU pVCpu, RTSEL SelTR)
312{
313 pVCpu->cpum.s.Hyper.tr.Sel = SelTR;
314}
315
316
317VMMDECL(void) CPUMSetHyperLDTR(PVMCPU pVCpu, RTSEL SelLDTR)
318{
319 pVCpu->cpum.s.Hyper.ldtr.Sel = SelLDTR;
320}
321
322
323/** @def MAYBE_LOAD_DRx
324 * Macro for updating DRx values in raw-mode and ring-0 contexts.
325 */
326#ifdef IN_RING0
327# if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
328# define MAYBE_LOAD_DRx(a_pVCpu, a_fnLoad, a_uValue) \
329 do { \
330 if (!CPUMIsGuestInLongModeEx(&(a_pVCpu)->cpum.s.Guest)) \
331 a_fnLoad(a_uValue); \
332 else \
333 (a_pVCpu)->cpum.s.fUseFlags |= CPUM_SYNC_DEBUG_REGS_HYPER; \
334 } while (0)
335# else
336# define MAYBE_LOAD_DRx(a_pVCpu, a_fnLoad, a_uValue) \
337 do { \
338 a_fnLoad(a_uValue); \
339 } while (0)
340# endif
341
342#elif defined(IN_RC)
343# define MAYBE_LOAD_DRx(a_pVCpu, a_fnLoad, a_uValue) \
344 do { \
345 if ((a_pVCpu)->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HYPER) \
346 { a_fnLoad(a_uValue); } \
347 } while (0)
348
349#else
350# define MAYBE_LOAD_DRx(a_pVCpu, a_fnLoad, a_uValue) do { } while (0)
351#endif
352
353VMMDECL(void) CPUMSetHyperDR0(PVMCPU pVCpu, RTGCUINTREG uDr0)
354{
355 pVCpu->cpum.s.Hyper.dr[0] = uDr0;
356 MAYBE_LOAD_DRx(pVCpu, ASMSetDR0, uDr0);
357}
358
359
360VMMDECL(void) CPUMSetHyperDR1(PVMCPU pVCpu, RTGCUINTREG uDr1)
361{
362 pVCpu->cpum.s.Hyper.dr[1] = uDr1;
363 MAYBE_LOAD_DRx(pVCpu, ASMSetDR1, uDr1);
364}
365
366
367VMMDECL(void) CPUMSetHyperDR2(PVMCPU pVCpu, RTGCUINTREG uDr2)
368{
369 pVCpu->cpum.s.Hyper.dr[2] = uDr2;
370 MAYBE_LOAD_DRx(pVCpu, ASMSetDR2, uDr2);
371}
372
373
374VMMDECL(void) CPUMSetHyperDR3(PVMCPU pVCpu, RTGCUINTREG uDr3)
375{
376 pVCpu->cpum.s.Hyper.dr[3] = uDr3;
377 MAYBE_LOAD_DRx(pVCpu, ASMSetDR3, uDr3);
378}
379
380
381VMMDECL(void) CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6)
382{
383 pVCpu->cpum.s.Hyper.dr[6] = uDr6;
384}
385
386
387VMMDECL(void) CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7)
388{
389 pVCpu->cpum.s.Hyper.dr[7] = uDr7;
390#ifdef IN_RC
391 MAYBE_LOAD_DRx(pVCpu, ASMSetDR7, uDr7);
392#endif
393}
394
395
396VMMDECL(RTSEL) CPUMGetHyperCS(PVMCPU pVCpu)
397{
398 return pVCpu->cpum.s.Hyper.cs.Sel;
399}
400
401
402VMMDECL(RTSEL) CPUMGetHyperDS(PVMCPU pVCpu)
403{
404 return pVCpu->cpum.s.Hyper.ds.Sel;
405}
406
407
408VMMDECL(RTSEL) CPUMGetHyperES(PVMCPU pVCpu)
409{
410 return pVCpu->cpum.s.Hyper.es.Sel;
411}
412
413
414VMMDECL(RTSEL) CPUMGetHyperFS(PVMCPU pVCpu)
415{
416 return pVCpu->cpum.s.Hyper.fs.Sel;
417}
418
419
420VMMDECL(RTSEL) CPUMGetHyperGS(PVMCPU pVCpu)
421{
422 return pVCpu->cpum.s.Hyper.gs.Sel;
423}
424
425
426VMMDECL(RTSEL) CPUMGetHyperSS(PVMCPU pVCpu)
427{
428 return pVCpu->cpum.s.Hyper.ss.Sel;
429}
430
431
432VMMDECL(uint32_t) CPUMGetHyperEAX(PVMCPU pVCpu)
433{
434 return pVCpu->cpum.s.Hyper.eax;
435}
436
437
438VMMDECL(uint32_t) CPUMGetHyperEBX(PVMCPU pVCpu)
439{
440 return pVCpu->cpum.s.Hyper.ebx;
441}
442
443
444VMMDECL(uint32_t) CPUMGetHyperECX(PVMCPU pVCpu)
445{
446 return pVCpu->cpum.s.Hyper.ecx;
447}
448
449
450VMMDECL(uint32_t) CPUMGetHyperEDX(PVMCPU pVCpu)
451{
452 return pVCpu->cpum.s.Hyper.edx;
453}
454
455
456VMMDECL(uint32_t) CPUMGetHyperESI(PVMCPU pVCpu)
457{
458 return pVCpu->cpum.s.Hyper.esi;
459}
460
461
462VMMDECL(uint32_t) CPUMGetHyperEDI(PVMCPU pVCpu)
463{
464 return pVCpu->cpum.s.Hyper.edi;
465}
466
467
468VMMDECL(uint32_t) CPUMGetHyperEBP(PVMCPU pVCpu)
469{
470 return pVCpu->cpum.s.Hyper.ebp;
471}
472
473
474VMMDECL(uint32_t) CPUMGetHyperESP(PVMCPU pVCpu)
475{
476 return pVCpu->cpum.s.Hyper.esp;
477}
478
479
480VMMDECL(uint32_t) CPUMGetHyperEFlags(PVMCPU pVCpu)
481{
482 return pVCpu->cpum.s.Hyper.eflags.u32;
483}
484
485
486VMMDECL(uint32_t) CPUMGetHyperEIP(PVMCPU pVCpu)
487{
488 return pVCpu->cpum.s.Hyper.eip;
489}
490
491
492VMMDECL(uint64_t) CPUMGetHyperRIP(PVMCPU pVCpu)
493{
494 return pVCpu->cpum.s.Hyper.rip;
495}
496
497
498VMMDECL(uint32_t) CPUMGetHyperIDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
499{
500 if (pcbLimit)
501 *pcbLimit = pVCpu->cpum.s.Hyper.idtr.cbIdt;
502 return pVCpu->cpum.s.Hyper.idtr.pIdt;
503}
504
505
506VMMDECL(uint32_t) CPUMGetHyperGDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
507{
508 if (pcbLimit)
509 *pcbLimit = pVCpu->cpum.s.Hyper.gdtr.cbGdt;
510 return pVCpu->cpum.s.Hyper.gdtr.pGdt;
511}
512
513
514VMMDECL(RTSEL) CPUMGetHyperLDTR(PVMCPU pVCpu)
515{
516 return pVCpu->cpum.s.Hyper.ldtr.Sel;
517}
518
519
520VMMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVMCPU pVCpu)
521{
522 return pVCpu->cpum.s.Hyper.dr[0];
523}
524
525
526VMMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVMCPU pVCpu)
527{
528 return pVCpu->cpum.s.Hyper.dr[1];
529}
530
531
532VMMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVMCPU pVCpu)
533{
534 return pVCpu->cpum.s.Hyper.dr[2];
535}
536
537
538VMMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVMCPU pVCpu)
539{
540 return pVCpu->cpum.s.Hyper.dr[3];
541}
542
543
544VMMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVMCPU pVCpu)
545{
546 return pVCpu->cpum.s.Hyper.dr[6];
547}
548
549
550VMMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVMCPU pVCpu)
551{
552 return pVCpu->cpum.s.Hyper.dr[7];
553}
554
555
556/**
557 * Gets the pointer to the internal CPUMCTXCORE structure.
558 * This is only for reading in order to save a few calls.
559 *
560 * @param pVCpu The cross context virtual CPU structure.
561 */
562VMMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVMCPU pVCpu)
563{
564 return CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
565}
566
567
568/**
569 * Queries the pointer to the internal CPUMCTX structure.
570 *
571 * @returns The CPUMCTX pointer.
572 * @param pVCpu The cross context virtual CPU structure.
573 */
574VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu)
575{
576 return &pVCpu->cpum.s.Guest;
577}
578
579VMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit)
580{
581#ifdef VBOX_WITH_RAW_MODE_NOT_R0
582 if (VM_IS_RAW_MODE_ENABLED(pVCpu->CTX_SUFF(pVM)))
583 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
584#endif
585 pVCpu->cpum.s.Guest.gdtr.cbGdt = cbLimit;
586 pVCpu->cpum.s.Guest.gdtr.pGdt = GCPtrBase;
587 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GDTR;
588 return VINF_SUCCESS; /* formality, consider it void. */
589}
590
591VMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit)
592{
593#ifdef VBOX_WITH_RAW_MODE_NOT_R0
594 if (VM_IS_RAW_MODE_ENABLED(pVCpu->CTX_SUFF(pVM)))
595 VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
596#endif
597 pVCpu->cpum.s.Guest.idtr.cbIdt = cbLimit;
598 pVCpu->cpum.s.Guest.idtr.pIdt = GCPtrBase;
599 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_IDTR;
600 return VINF_SUCCESS; /* formality, consider it void. */
601}
602
603VMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr)
604{
605#ifdef VBOX_WITH_RAW_MODE_NOT_R0
606 if (VM_IS_RAW_MODE_ENABLED(pVCpu->CTX_SUFF(pVM)))
607 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
608#endif
609 pVCpu->cpum.s.Guest.tr.Sel = tr;
610 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_TR;
611 return VINF_SUCCESS; /* formality, consider it void. */
612}
613
614VMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr)
615{
616#ifdef VBOX_WITH_RAW_MODE_NOT_R0
617 if ( ( ldtr != 0
618 || pVCpu->cpum.s.Guest.ldtr.Sel != 0)
619 && VM_IS_RAW_MODE_ENABLED(pVCpu->CTX_SUFF(pVM)))
620 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
621#endif
622 pVCpu->cpum.s.Guest.ldtr.Sel = ldtr;
623 /* The caller will set more hidden bits if it has them. */
624 pVCpu->cpum.s.Guest.ldtr.ValidSel = 0;
625 pVCpu->cpum.s.Guest.ldtr.fFlags = 0;
626 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_LDTR;
627 return VINF_SUCCESS; /* formality, consider it void. */
628}
629
630
631/**
632 * Set the guest CR0.
633 *
634 * When called in GC, the hyper CR0 may be updated if that is
635 * required. The caller only has to take special action if AM,
636 * WP, PG or PE changes.
637 *
638 * @returns VINF_SUCCESS (consider it void).
639 * @param pVCpu The cross context virtual CPU structure.
640 * @param cr0 The new CR0 value.
641 */
642VMMDECL(int) CPUMSetGuestCR0(PVMCPU pVCpu, uint64_t cr0)
643{
644#ifdef IN_RC
645 /*
646 * Check if we need to change hypervisor CR0 because
647 * of math stuff.
648 */
649 if ( (cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP))
650 != (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP)))
651 {
652 if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST))
653 {
654 /*
655 * We haven't loaded the guest FPU state yet, so TS and MT are both set
656 * and EM should be reflecting the guest EM (it always does this).
657 */
658 if ((cr0 & X86_CR0_EM) != (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM))
659 {
660 uint32_t HyperCR0 = ASMGetCR0();
661 AssertMsg((HyperCR0 & (X86_CR0_TS | X86_CR0_MP)) == (X86_CR0_TS | X86_CR0_MP), ("%#x\n", HyperCR0));
662 AssertMsg((HyperCR0 & X86_CR0_EM) == (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM), ("%#x\n", HyperCR0));
663 HyperCR0 &= ~X86_CR0_EM;
664 HyperCR0 |= cr0 & X86_CR0_EM;
665 Log(("CPUM: New HyperCR0=%#x\n", HyperCR0));
666 ASMSetCR0(HyperCR0);
667 }
668# ifdef VBOX_STRICT
669 else
670 {
671 uint32_t HyperCR0 = ASMGetCR0();
672 AssertMsg((HyperCR0 & (X86_CR0_TS | X86_CR0_MP)) == (X86_CR0_TS | X86_CR0_MP), ("%#x\n", HyperCR0));
673 AssertMsg((HyperCR0 & X86_CR0_EM) == (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM), ("%#x\n", HyperCR0));
674 }
675# endif
676 }
677 else
678 {
679 /*
680 * Already loaded the guest FPU state, so we're just mirroring
681 * the guest flags.
682 */
683 uint32_t HyperCR0 = ASMGetCR0();
684 AssertMsg( (HyperCR0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP))
685 == (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP)),
686 ("%#x %#x\n", HyperCR0, pVCpu->cpum.s.Guest.cr0));
687 HyperCR0 &= ~(X86_CR0_TS | X86_CR0_EM | X86_CR0_MP);
688 HyperCR0 |= cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP);
689 Log(("CPUM: New HyperCR0=%#x\n", HyperCR0));
690 ASMSetCR0(HyperCR0);
691 }
692 }
693#endif /* IN_RC */
694
695 /*
696 * Check for changes causing TLB flushes (for REM).
697 * The caller is responsible for calling PGM when appropriate.
698 */
699 if ( (cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE))
700 != (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)))
701 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
702 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR0;
703
704 /*
705 * Let PGM know if the WP goes from 0 to 1 (netware WP0+RO+US hack)
706 */
707 if (((cr0 ^ pVCpu->cpum.s.Guest.cr0) & X86_CR0_WP) && (cr0 & X86_CR0_WP))
708 PGMCr0WpEnabled(pVCpu);
709
710 /* The ET flag is settable on a 386 and hardwired on 486+. */
711 if ( !(cr0 & X86_CR0_ET)
712 && pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.enmMicroarch != kCpumMicroarch_Intel_80386)
713 cr0 |= X86_CR0_ET;
714
715 pVCpu->cpum.s.Guest.cr0 = cr0;
716 return VINF_SUCCESS;
717}
718
719
720VMMDECL(int) CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2)
721{
722 pVCpu->cpum.s.Guest.cr2 = cr2;
723 return VINF_SUCCESS;
724}
725
726
727VMMDECL(int) CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3)
728{
729 pVCpu->cpum.s.Guest.cr3 = cr3;
730 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR3;
731 return VINF_SUCCESS;
732}
733
734
735VMMDECL(int) CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4)
736{
737 /* Note! We don't bother with OSXSAVE and legacy CPUID patches. */
738
739 if ( (cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE))
740 != (pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE)))
741 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
742
743 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR4;
744 pVCpu->cpum.s.Guest.cr4 = cr4;
745 return VINF_SUCCESS;
746}
747
748
749VMMDECL(int) CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags)
750{
751 pVCpu->cpum.s.Guest.eflags.u32 = eflags;
752 return VINF_SUCCESS;
753}
754
755
756VMMDECL(int) CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip)
757{
758 pVCpu->cpum.s.Guest.eip = eip;
759 return VINF_SUCCESS;
760}
761
762
763VMMDECL(int) CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax)
764{
765 pVCpu->cpum.s.Guest.eax = eax;
766 return VINF_SUCCESS;
767}
768
769
770VMMDECL(int) CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx)
771{
772 pVCpu->cpum.s.Guest.ebx = ebx;
773 return VINF_SUCCESS;
774}
775
776
777VMMDECL(int) CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx)
778{
779 pVCpu->cpum.s.Guest.ecx = ecx;
780 return VINF_SUCCESS;
781}
782
783
784VMMDECL(int) CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx)
785{
786 pVCpu->cpum.s.Guest.edx = edx;
787 return VINF_SUCCESS;
788}
789
790
791VMMDECL(int) CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp)
792{
793 pVCpu->cpum.s.Guest.esp = esp;
794 return VINF_SUCCESS;
795}
796
797
798VMMDECL(int) CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp)
799{
800 pVCpu->cpum.s.Guest.ebp = ebp;
801 return VINF_SUCCESS;
802}
803
804
805VMMDECL(int) CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi)
806{
807 pVCpu->cpum.s.Guest.esi = esi;
808 return VINF_SUCCESS;
809}
810
811
812VMMDECL(int) CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi)
813{
814 pVCpu->cpum.s.Guest.edi = edi;
815 return VINF_SUCCESS;
816}
817
818
819VMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss)
820{
821 pVCpu->cpum.s.Guest.ss.Sel = ss;
822 return VINF_SUCCESS;
823}
824
825
826VMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs)
827{
828 pVCpu->cpum.s.Guest.cs.Sel = cs;
829 return VINF_SUCCESS;
830}
831
832
833VMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds)
834{
835 pVCpu->cpum.s.Guest.ds.Sel = ds;
836 return VINF_SUCCESS;
837}
838
839
840VMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es)
841{
842 pVCpu->cpum.s.Guest.es.Sel = es;
843 return VINF_SUCCESS;
844}
845
846
847VMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs)
848{
849 pVCpu->cpum.s.Guest.fs.Sel = fs;
850 return VINF_SUCCESS;
851}
852
853
854VMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs)
855{
856 pVCpu->cpum.s.Guest.gs.Sel = gs;
857 return VINF_SUCCESS;
858}
859
860
861VMMDECL(void) CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val)
862{
863 pVCpu->cpum.s.Guest.msrEFER = val;
864}
865
866
867VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
868{
869 if (pcbLimit)
870 *pcbLimit = pVCpu->cpum.s.Guest.idtr.cbIdt;
871 return pVCpu->cpum.s.Guest.idtr.pIdt;
872}
873
874
875VMMDECL(RTSEL) CPUMGetGuestTR(PVMCPU pVCpu, PCPUMSELREGHID pHidden)
876{
877 if (pHidden)
878 *pHidden = pVCpu->cpum.s.Guest.tr;
879 return pVCpu->cpum.s.Guest.tr.Sel;
880}
881
882
883VMMDECL(RTSEL) CPUMGetGuestCS(PVMCPU pVCpu)
884{
885 return pVCpu->cpum.s.Guest.cs.Sel;
886}
887
888
889VMMDECL(RTSEL) CPUMGetGuestDS(PVMCPU pVCpu)
890{
891 return pVCpu->cpum.s.Guest.ds.Sel;
892}
893
894
895VMMDECL(RTSEL) CPUMGetGuestES(PVMCPU pVCpu)
896{
897 return pVCpu->cpum.s.Guest.es.Sel;
898}
899
900
901VMMDECL(RTSEL) CPUMGetGuestFS(PVMCPU pVCpu)
902{
903 return pVCpu->cpum.s.Guest.fs.Sel;
904}
905
906
907VMMDECL(RTSEL) CPUMGetGuestGS(PVMCPU pVCpu)
908{
909 return pVCpu->cpum.s.Guest.gs.Sel;
910}
911
912
913VMMDECL(RTSEL) CPUMGetGuestSS(PVMCPU pVCpu)
914{
915 return pVCpu->cpum.s.Guest.ss.Sel;
916}
917
918
919VMMDECL(uint64_t) CPUMGetGuestFlatPC(PVMCPU pVCpu)
920{
921 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
922 if ( !CPUMIsGuestInLongMode(pVCpu)
923 || pVCpu->cpum.s.Guest.cs.Attr.n.u1Long)
924 return pVCpu->cpum.s.Guest.eip + (uint32_t)pVCpu->cpum.s.Guest.cs.u64Base;
925 return pVCpu->cpum.s.Guest.rip + pVCpu->cpum.s.Guest.cs.u64Base;
926}
927
928
929VMMDECL(uint64_t) CPUMGetGuestFlatSP(PVMCPU pVCpu)
930{
931 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.ss);
932 if ( !CPUMIsGuestInLongMode(pVCpu)
933 || pVCpu->cpum.s.Guest.ss.Attr.n.u1Long)
934 return pVCpu->cpum.s.Guest.eip + (uint32_t)pVCpu->cpum.s.Guest.ss.u64Base;
935 return pVCpu->cpum.s.Guest.rip + pVCpu->cpum.s.Guest.ss.u64Base;
936}
937
938
939VMMDECL(RTSEL) CPUMGetGuestLDTR(PVMCPU pVCpu)
940{
941 return pVCpu->cpum.s.Guest.ldtr.Sel;
942}
943
944
945VMMDECL(RTSEL) CPUMGetGuestLdtrEx(PVMCPU pVCpu, uint64_t *pGCPtrBase, uint32_t *pcbLimit)
946{
947 *pGCPtrBase = pVCpu->cpum.s.Guest.ldtr.u64Base;
948 *pcbLimit = pVCpu->cpum.s.Guest.ldtr.u32Limit;
949 return pVCpu->cpum.s.Guest.ldtr.Sel;
950}
951
952
953VMMDECL(uint64_t) CPUMGetGuestCR0(PVMCPU pVCpu)
954{
955 return pVCpu->cpum.s.Guest.cr0;
956}
957
958
959VMMDECL(uint64_t) CPUMGetGuestCR2(PVMCPU pVCpu)
960{
961 return pVCpu->cpum.s.Guest.cr2;
962}
963
964
965VMMDECL(uint64_t) CPUMGetGuestCR3(PVMCPU pVCpu)
966{
967 return pVCpu->cpum.s.Guest.cr3;
968}
969
970
971VMMDECL(uint64_t) CPUMGetGuestCR4(PVMCPU pVCpu)
972{
973 return pVCpu->cpum.s.Guest.cr4;
974}
975
976
977VMMDECL(uint64_t) CPUMGetGuestCR8(PVMCPU pVCpu)
978{
979 uint64_t u64;
980 int rc = CPUMGetGuestCRx(pVCpu, DISCREG_CR8, &u64);
981 if (RT_FAILURE(rc))
982 u64 = 0;
983 return u64;
984}
985
986
987VMMDECL(void) CPUMGetGuestGDTR(PVMCPU pVCpu, PVBOXGDTR pGDTR)
988{
989 *pGDTR = pVCpu->cpum.s.Guest.gdtr;
990}
991
992
993VMMDECL(uint32_t) CPUMGetGuestEIP(PVMCPU pVCpu)
994{
995 return pVCpu->cpum.s.Guest.eip;
996}
997
998
999VMMDECL(uint64_t) CPUMGetGuestRIP(PVMCPU pVCpu)
1000{
1001 return pVCpu->cpum.s.Guest.rip;
1002}
1003
1004
1005VMMDECL(uint32_t) CPUMGetGuestEAX(PVMCPU pVCpu)
1006{
1007 return pVCpu->cpum.s.Guest.eax;
1008}
1009
1010
1011VMMDECL(uint32_t) CPUMGetGuestEBX(PVMCPU pVCpu)
1012{
1013 return pVCpu->cpum.s.Guest.ebx;
1014}
1015
1016
1017VMMDECL(uint32_t) CPUMGetGuestECX(PVMCPU pVCpu)
1018{
1019 return pVCpu->cpum.s.Guest.ecx;
1020}
1021
1022
1023VMMDECL(uint32_t) CPUMGetGuestEDX(PVMCPU pVCpu)
1024{
1025 return pVCpu->cpum.s.Guest.edx;
1026}
1027
1028
1029VMMDECL(uint32_t) CPUMGetGuestESI(PVMCPU pVCpu)
1030{
1031 return pVCpu->cpum.s.Guest.esi;
1032}
1033
1034
1035VMMDECL(uint32_t) CPUMGetGuestEDI(PVMCPU pVCpu)
1036{
1037 return pVCpu->cpum.s.Guest.edi;
1038}
1039
1040
1041VMMDECL(uint32_t) CPUMGetGuestESP(PVMCPU pVCpu)
1042{
1043 return pVCpu->cpum.s.Guest.esp;
1044}
1045
1046
1047VMMDECL(uint32_t) CPUMGetGuestEBP(PVMCPU pVCpu)
1048{
1049 return pVCpu->cpum.s.Guest.ebp;
1050}
1051
1052
1053VMMDECL(uint32_t) CPUMGetGuestEFlags(PVMCPU pVCpu)
1054{
1055 return pVCpu->cpum.s.Guest.eflags.u32;
1056}
1057
1058
1059VMMDECL(int) CPUMGetGuestCRx(PVMCPU pVCpu, unsigned iReg, uint64_t *pValue)
1060{
1061 switch (iReg)
1062 {
1063 case DISCREG_CR0:
1064 *pValue = pVCpu->cpum.s.Guest.cr0;
1065 break;
1066
1067 case DISCREG_CR2:
1068 *pValue = pVCpu->cpum.s.Guest.cr2;
1069 break;
1070
1071 case DISCREG_CR3:
1072 *pValue = pVCpu->cpum.s.Guest.cr3;
1073 break;
1074
1075 case DISCREG_CR4:
1076 *pValue = pVCpu->cpum.s.Guest.cr4;
1077 break;
1078
1079 case DISCREG_CR8:
1080 {
1081 uint8_t u8Tpr;
1082 int rc = APICGetTpr(pVCpu, &u8Tpr, NULL /* pfPending */, NULL /* pu8PendingIrq */);
1083 if (RT_FAILURE(rc))
1084 {
1085 AssertMsg(rc == VERR_PDM_NO_APIC_INSTANCE, ("%Rrc\n", rc));
1086 *pValue = 0;
1087 return rc;
1088 }
1089 *pValue = u8Tpr >> 4; /* bits 7-4 contain the task priority that go in cr8, bits 3-0 */
1090 break;
1091 }
1092
1093 default:
1094 return VERR_INVALID_PARAMETER;
1095 }
1096 return VINF_SUCCESS;
1097}
1098
1099
1100VMMDECL(uint64_t) CPUMGetGuestDR0(PVMCPU pVCpu)
1101{
1102 return pVCpu->cpum.s.Guest.dr[0];
1103}
1104
1105
1106VMMDECL(uint64_t) CPUMGetGuestDR1(PVMCPU pVCpu)
1107{
1108 return pVCpu->cpum.s.Guest.dr[1];
1109}
1110
1111
1112VMMDECL(uint64_t) CPUMGetGuestDR2(PVMCPU pVCpu)
1113{
1114 return pVCpu->cpum.s.Guest.dr[2];
1115}
1116
1117
1118VMMDECL(uint64_t) CPUMGetGuestDR3(PVMCPU pVCpu)
1119{
1120 return pVCpu->cpum.s.Guest.dr[3];
1121}
1122
1123
1124VMMDECL(uint64_t) CPUMGetGuestDR6(PVMCPU pVCpu)
1125{
1126 return pVCpu->cpum.s.Guest.dr[6];
1127}
1128
1129
1130VMMDECL(uint64_t) CPUMGetGuestDR7(PVMCPU pVCpu)
1131{
1132 return pVCpu->cpum.s.Guest.dr[7];
1133}
1134
1135
1136VMMDECL(int) CPUMGetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t *pValue)
1137{
1138 AssertReturn(iReg <= DISDREG_DR7, VERR_INVALID_PARAMETER);
1139 /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
1140 if (iReg == 4 || iReg == 5)
1141 iReg += 2;
1142 *pValue = pVCpu->cpum.s.Guest.dr[iReg];
1143 return VINF_SUCCESS;
1144}
1145
1146
1147VMMDECL(uint64_t) CPUMGetGuestEFER(PVMCPU pVCpu)
1148{
1149 return pVCpu->cpum.s.Guest.msrEFER;
1150}
1151
1152
1153/**
1154 * Looks up a CPUID leaf in the CPUID leaf array, no subleaf.
1155 *
1156 * @returns Pointer to the leaf if found, NULL if not.
1157 *
1158 * @param pVM The cross context VM structure.
1159 * @param uLeaf The leaf to get.
1160 */
1161PCPUMCPUIDLEAF cpumCpuIdGetLeaf(PVM pVM, uint32_t uLeaf)
1162{
1163 unsigned iEnd = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
1164 if (iEnd)
1165 {
1166 unsigned iStart = 0;
1167 PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.CTX_SUFF(paCpuIdLeaves);
1168 for (;;)
1169 {
1170 unsigned i = iStart + (iEnd - iStart) / 2U;
1171 if (uLeaf < paLeaves[i].uLeaf)
1172 {
1173 if (i <= iStart)
1174 return NULL;
1175 iEnd = i;
1176 }
1177 else if (uLeaf > paLeaves[i].uLeaf)
1178 {
1179 i += 1;
1180 if (i >= iEnd)
1181 return NULL;
1182 iStart = i;
1183 }
1184 else
1185 {
1186 if (RT_LIKELY(paLeaves[i].fSubLeafMask == 0 && paLeaves[i].uSubLeaf == 0))
1187 return &paLeaves[i];
1188
1189 /* This shouldn't normally happen. But in case the it does due
1190 to user configuration overrids or something, just return the
1191 first sub-leaf. */
1192 AssertMsgFailed(("uLeaf=%#x fSubLeafMask=%#x uSubLeaf=%#x\n",
1193 uLeaf, paLeaves[i].fSubLeafMask, paLeaves[i].uSubLeaf));
1194 while ( paLeaves[i].uSubLeaf != 0
1195 && i > 0
1196 && uLeaf == paLeaves[i - 1].uLeaf)
1197 i--;
1198 return &paLeaves[i];
1199 }
1200 }
1201 }
1202
1203 return NULL;
1204}
1205
1206
1207/**
1208 * Looks up a CPUID leaf in the CPUID leaf array.
1209 *
1210 * @returns Pointer to the leaf if found, NULL if not.
1211 *
1212 * @param pVM The cross context VM structure.
1213 * @param uLeaf The leaf to get.
1214 * @param uSubLeaf The subleaf, if applicable. Just pass 0 if it
1215 * isn't.
1216 * @param pfExactSubLeafHit Whether we've got an exact subleaf hit or not.
1217 */
1218PCPUMCPUIDLEAF cpumCpuIdGetLeafEx(PVM pVM, uint32_t uLeaf, uint32_t uSubLeaf, bool *pfExactSubLeafHit)
1219{
1220 unsigned iEnd = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
1221 if (iEnd)
1222 {
1223 unsigned iStart = 0;
1224 PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.CTX_SUFF(paCpuIdLeaves);
1225 for (;;)
1226 {
1227 unsigned i = iStart + (iEnd - iStart) / 2U;
1228 if (uLeaf < paLeaves[i].uLeaf)
1229 {
1230 if (i <= iStart)
1231 return NULL;
1232 iEnd = i;
1233 }
1234 else if (uLeaf > paLeaves[i].uLeaf)
1235 {
1236 i += 1;
1237 if (i >= iEnd)
1238 return NULL;
1239 iStart = i;
1240 }
1241 else
1242 {
1243 uSubLeaf &= paLeaves[i].fSubLeafMask;
1244 if (uSubLeaf == paLeaves[i].uSubLeaf)
1245 *pfExactSubLeafHit = true;
1246 else
1247 {
1248 /* Find the right subleaf. We return the last one before
1249 uSubLeaf if we don't find an exact match. */
1250 if (uSubLeaf < paLeaves[i].uSubLeaf)
1251 while ( i > 0
1252 && uLeaf == paLeaves[i - 1].uLeaf
1253 && uSubLeaf <= paLeaves[i - 1].uSubLeaf)
1254 i--;
1255 else
1256 while ( i + 1 < pVM->cpum.s.GuestInfo.cCpuIdLeaves
1257 && uLeaf == paLeaves[i + 1].uLeaf
1258 && uSubLeaf >= paLeaves[i + 1].uSubLeaf)
1259 i++;
1260 *pfExactSubLeafHit = uSubLeaf == paLeaves[i].uSubLeaf;
1261 }
1262 return &paLeaves[i];
1263 }
1264 }
1265 }
1266
1267 *pfExactSubLeafHit = false;
1268 return NULL;
1269}
1270
1271
1272/**
1273 * Gets a CPUID leaf.
1274 *
1275 * @param pVCpu The cross context virtual CPU structure.
1276 * @param uLeaf The CPUID leaf to get.
1277 * @param uSubLeaf The CPUID sub-leaf to get, if applicable.
1278 * @param pEax Where to store the EAX value.
1279 * @param pEbx Where to store the EBX value.
1280 * @param pEcx Where to store the ECX value.
1281 * @param pEdx Where to store the EDX value.
1282 */
1283VMMDECL(void) CPUMGetGuestCpuId(PVMCPU pVCpu, uint32_t uLeaf, uint32_t uSubLeaf,
1284 uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx)
1285{
1286 bool fExactSubLeafHit;
1287 PVM pVM = pVCpu->CTX_SUFF(pVM);
1288 PCCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafEx(pVM, uLeaf, uSubLeaf, &fExactSubLeafHit);
1289 if (pLeaf)
1290 {
1291 AssertMsg(pLeaf->uLeaf == uLeaf, ("%#x %#x\n", pLeaf->uLeaf, uLeaf));
1292 if (fExactSubLeafHit)
1293 {
1294 *pEax = pLeaf->uEax;
1295 *pEbx = pLeaf->uEbx;
1296 *pEcx = pLeaf->uEcx;
1297 *pEdx = pLeaf->uEdx;
1298
1299 /*
1300 * Deal with CPU specific information.
1301 */
1302 if (pLeaf->fFlags & ( CPUMCPUIDLEAF_F_CONTAINS_APIC_ID
1303 | CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE
1304 | CPUMCPUIDLEAF_F_CONTAINS_APIC ))
1305 {
1306 if (uLeaf == 1)
1307 {
1308 /* EBX: Bits 31-24: Initial APIC ID. */
1309 Assert(pVCpu->idCpu <= 255);
1310 AssertMsg((pLeaf->uEbx >> 24) == 0, ("%#x\n", pLeaf->uEbx)); /* raw-mode assumption */
1311 *pEbx = (pLeaf->uEbx & UINT32_C(0x00ffffff)) | (pVCpu->idCpu << 24);
1312
1313 /* EDX: Bit 9: AND with APICBASE.EN. */
1314 if (!pVCpu->cpum.s.fCpuIdApicFeatureVisible && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
1315 *pEdx &= ~X86_CPUID_FEATURE_EDX_APIC;
1316
1317 /* ECX: Bit 27: CR4.OSXSAVE mirror. */
1318 *pEcx = (pLeaf->uEcx & ~X86_CPUID_FEATURE_ECX_OSXSAVE)
1319 | (pVCpu->cpum.s.Guest.cr4 & X86_CR4_OSXSAVE ? X86_CPUID_FEATURE_ECX_OSXSAVE : 0);
1320 }
1321 else if (uLeaf == 0xb)
1322 {
1323 /* EDX: Initial extended APIC ID. */
1324 AssertMsg(pLeaf->uEdx == 0, ("%#x\n", pLeaf->uEdx)); /* raw-mode assumption */
1325 *pEdx = pVCpu->idCpu;
1326 Assert(!(pLeaf->fFlags & ~(CPUMCPUIDLEAF_F_CONTAINS_APIC_ID | CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES)));
1327 }
1328 else if (uLeaf == UINT32_C(0x8000001e))
1329 {
1330 /* EAX: Initial extended APIC ID. */
1331 AssertMsg(pLeaf->uEax == 0, ("%#x\n", pLeaf->uEax)); /* raw-mode assumption */
1332 *pEax = pVCpu->idCpu;
1333 Assert(!(pLeaf->fFlags & ~CPUMCPUIDLEAF_F_CONTAINS_APIC_ID));
1334 }
1335 else if (uLeaf == UINT32_C(0x80000001))
1336 {
1337 /* EDX: Bit 9: AND with APICBASE.EN. */
1338 if (!pVCpu->cpum.s.fCpuIdApicFeatureVisible)
1339 *pEdx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
1340 Assert(!(pLeaf->fFlags & ~CPUMCPUIDLEAF_F_CONTAINS_APIC));
1341 }
1342 else
1343 AssertMsgFailed(("uLeaf=%#x\n", uLeaf));
1344 }
1345 }
1346 /*
1347 * Out of range sub-leaves aren't quite as easy and pretty as we emulate
1348 * them here, but we do the best we can here...
1349 */
1350 else
1351 {
1352 *pEax = *pEbx = *pEcx = *pEdx = 0;
1353 if (pLeaf->fFlags & CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES)
1354 {
1355 *pEcx = uSubLeaf & 0xff;
1356 *pEdx = pVCpu->idCpu;
1357 }
1358 }
1359 }
1360 else
1361 {
1362 /*
1363 * Different CPUs have different ways of dealing with unknown CPUID leaves.
1364 */
1365 switch (pVM->cpum.s.GuestInfo.enmUnknownCpuIdMethod)
1366 {
1367 default:
1368 AssertFailed();
1369 RT_FALL_THRU();
1370 case CPUMUNKNOWNCPUID_DEFAULTS:
1371 case CPUMUNKNOWNCPUID_LAST_STD_LEAF: /* ASSUME this is executed */
1372 case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: /** @todo Implement CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX */
1373 *pEax = pVM->cpum.s.GuestInfo.DefCpuId.uEax;
1374 *pEbx = pVM->cpum.s.GuestInfo.DefCpuId.uEbx;
1375 *pEcx = pVM->cpum.s.GuestInfo.DefCpuId.uEcx;
1376 *pEdx = pVM->cpum.s.GuestInfo.DefCpuId.uEdx;
1377 break;
1378 case CPUMUNKNOWNCPUID_PASSTHRU:
1379 *pEax = uLeaf;
1380 *pEbx = 0;
1381 *pEcx = uSubLeaf;
1382 *pEdx = 0;
1383 break;
1384 }
1385 }
1386 Log2(("CPUMGetGuestCpuId: uLeaf=%#010x/%#010x %RX32 %RX32 %RX32 %RX32\n", uLeaf, uSubLeaf, *pEax, *pEbx, *pEcx, *pEdx));
1387}
1388
1389
1390/**
1391 * Sets the visibility of the X86_CPUID_FEATURE_EDX_APIC and
1392 * X86_CPUID_AMD_FEATURE_EDX_APIC CPUID bits.
1393 *
1394 * @returns Previous value.
1395 * @param pVCpu The cross context virtual CPU structure to make the
1396 * change on. Usually the calling EMT.
1397 * @param fVisible Whether to make it visible (true) or hide it (false).
1398 *
1399 * @remarks This is "VMMDECL" so that it still links with
1400 * the old APIC code which is in VBoxDD2 and not in
1401 * the VMM module.
1402 */
1403VMMDECL(bool) CPUMSetGuestCpuIdPerCpuApicFeature(PVMCPU pVCpu, bool fVisible)
1404{
1405 bool fOld = pVCpu->cpum.s.fCpuIdApicFeatureVisible;
1406 pVCpu->cpum.s.fCpuIdApicFeatureVisible = fVisible;
1407
1408#ifdef VBOX_WITH_RAW_MODE_NOT_R0
1409 /*
1410 * Patch manager saved state legacy pain.
1411 */
1412 PVM pVM = pVCpu->CTX_SUFF(pVM);
1413 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
1414 if (pLeaf)
1415 {
1416 if (fVisible || (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
1417 pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx;
1418 else
1419 pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx & ~X86_CPUID_FEATURE_EDX_APIC;
1420 }
1421
1422 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
1423 if (pLeaf)
1424 {
1425 if (fVisible || (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
1426 pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx;
1427 else
1428 pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx & ~X86_CPUID_AMD_FEATURE_EDX_APIC;
1429 }
1430#endif
1431
1432 return fOld;
1433}
1434
1435
1436/**
1437 * Gets the host CPU vendor.
1438 *
1439 * @returns CPU vendor.
1440 * @param pVM The cross context VM structure.
1441 */
1442VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM)
1443{
1444 return (CPUMCPUVENDOR)pVM->cpum.s.HostFeatures.enmCpuVendor;
1445}
1446
1447
1448/**
1449 * Gets the CPU vendor.
1450 *
1451 * @returns CPU vendor.
1452 * @param pVM The cross context VM structure.
1453 */
1454VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM)
1455{
1456 return (CPUMCPUVENDOR)pVM->cpum.s.GuestFeatures.enmCpuVendor;
1457}
1458
1459
1460VMMDECL(int) CPUMSetGuestDR0(PVMCPU pVCpu, uint64_t uDr0)
1461{
1462 pVCpu->cpum.s.Guest.dr[0] = uDr0;
1463 return CPUMRecalcHyperDRx(pVCpu, 0, false);
1464}
1465
1466
1467VMMDECL(int) CPUMSetGuestDR1(PVMCPU pVCpu, uint64_t uDr1)
1468{
1469 pVCpu->cpum.s.Guest.dr[1] = uDr1;
1470 return CPUMRecalcHyperDRx(pVCpu, 1, false);
1471}
1472
1473
1474VMMDECL(int) CPUMSetGuestDR2(PVMCPU pVCpu, uint64_t uDr2)
1475{
1476 pVCpu->cpum.s.Guest.dr[2] = uDr2;
1477 return CPUMRecalcHyperDRx(pVCpu, 2, false);
1478}
1479
1480
1481VMMDECL(int) CPUMSetGuestDR3(PVMCPU pVCpu, uint64_t uDr3)
1482{
1483 pVCpu->cpum.s.Guest.dr[3] = uDr3;
1484 return CPUMRecalcHyperDRx(pVCpu, 3, false);
1485}
1486
1487
1488VMMDECL(int) CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6)
1489{
1490 pVCpu->cpum.s.Guest.dr[6] = uDr6;
1491 return VINF_SUCCESS; /* No need to recalc. */
1492}
1493
1494
1495VMMDECL(int) CPUMSetGuestDR7(PVMCPU pVCpu, uint64_t uDr7)
1496{
1497 pVCpu->cpum.s.Guest.dr[7] = uDr7;
1498 return CPUMRecalcHyperDRx(pVCpu, 7, false);
1499}
1500
1501
1502VMMDECL(int) CPUMSetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t Value)
1503{
1504 AssertReturn(iReg <= DISDREG_DR7, VERR_INVALID_PARAMETER);
1505 /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
1506 if (iReg == 4 || iReg == 5)
1507 iReg += 2;
1508 pVCpu->cpum.s.Guest.dr[iReg] = Value;
1509 return CPUMRecalcHyperDRx(pVCpu, iReg, false);
1510}
1511
1512
1513/**
1514 * Recalculates the hypervisor DRx register values based on current guest
1515 * registers and DBGF breakpoints, updating changed registers depending on the
1516 * context.
1517 *
1518 * This is called whenever a guest DRx register is modified (any context) and
1519 * when DBGF sets a hardware breakpoint (ring-3 only, rendezvous).
1520 *
1521 * In raw-mode context this function will reload any (hyper) DRx registers which
1522 * comes out with a different value. It may also have to save the host debug
1523 * registers if that haven't been done already. In this context though, we'll
1524 * be intercepting and emulating all DRx accesses, so the hypervisor DRx values
1525 * are only important when breakpoints are actually enabled.
1526 *
1527 * In ring-0 (HM) context DR0-3 will be relocated by us, while DR7 will be
1528 * reloaded by the HM code if it changes. Further more, we will only use the
1529 * combined register set when the VBox debugger is actually using hardware BPs,
1530 * when it isn't we'll keep the guest DR0-3 + (maybe) DR6 loaded (DR6 doesn't
1531 * concern us here).
1532 *
1533 * In ring-3 we won't be loading anything, so well calculate hypervisor values
1534 * all the time.
1535 *
1536 * @returns VINF_SUCCESS.
1537 * @param pVCpu The cross context virtual CPU structure.
1538 * @param iGstReg The guest debug register number that was modified.
1539 * UINT8_MAX if not guest register.
1540 * @param fForceHyper Used in HM to force hyper registers because of single
1541 * stepping.
1542 */
1543VMMDECL(int) CPUMRecalcHyperDRx(PVMCPU pVCpu, uint8_t iGstReg, bool fForceHyper)
1544{
1545 PVM pVM = pVCpu->CTX_SUFF(pVM);
1546#ifndef IN_RING0
1547 RT_NOREF_PV(iGstReg);
1548#endif
1549
1550 /*
1551 * Compare the DR7s first.
1552 *
1553 * We only care about the enabled flags. GD is virtualized when we
1554 * dispatch the #DB, we never enable it. The DBGF DR7 value is will
1555 * always have the LE and GE bits set, so no need to check and disable
1556 * stuff if they're cleared like we have to for the guest DR7.
1557 */
1558 RTGCUINTREG uGstDr7 = CPUMGetGuestDR7(pVCpu);
1559 /** @todo This isn't correct. BPs work without setting LE and GE under AMD-V. They are also documented as unsupported by P6+. */
1560 if (!(uGstDr7 & (X86_DR7_LE | X86_DR7_GE)))
1561 uGstDr7 = 0;
1562 else if (!(uGstDr7 & X86_DR7_LE))
1563 uGstDr7 &= ~X86_DR7_LE_ALL;
1564 else if (!(uGstDr7 & X86_DR7_GE))
1565 uGstDr7 &= ~X86_DR7_GE_ALL;
1566
1567 const RTGCUINTREG uDbgfDr7 = DBGFBpGetDR7(pVM);
1568
1569#ifdef IN_RING0
1570 if (!fForceHyper && (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HYPER))
1571 fForceHyper = true;
1572#endif
1573 if ( (!VM_IS_RAW_MODE_ENABLED(pVCpu->CTX_SUFF(pVM)) && !fForceHyper ? uDbgfDr7 : (uGstDr7 | uDbgfDr7))
1574 & X86_DR7_ENABLED_MASK)
1575 {
1576 Assert(!CPUMIsGuestDebugStateActive(pVCpu));
1577#ifdef IN_RC
1578 bool const fRawModeEnabled = true;
1579#elif defined(IN_RING3)
1580 bool const fRawModeEnabled = VM_IS_RAW_MODE_ENABLED(pVM);
1581#endif
1582
1583 /*
1584 * Ok, something is enabled. Recalc each of the breakpoints, taking
1585 * the VM debugger ones of the guest ones. In raw-mode context we will
1586 * not allow breakpoints with values inside the hypervisor area.
1587 */
1588 RTGCUINTREG uNewDr7 = X86_DR7_GE | X86_DR7_LE | X86_DR7_RA1_MASK;
1589
1590 /* bp 0 */
1591 RTGCUINTREG uNewDr0;
1592 if (uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0))
1593 {
1594 uNewDr7 |= uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
1595 uNewDr0 = DBGFBpGetDR0(pVM);
1596 }
1597 else if (uGstDr7 & (X86_DR7_L0 | X86_DR7_G0))
1598 {
1599 uNewDr0 = CPUMGetGuestDR0(pVCpu);
1600#ifndef IN_RING0
1601 if (fRawModeEnabled && MMHyperIsInsideArea(pVM, uNewDr0))
1602 uNewDr0 = 0;
1603 else
1604#endif
1605 uNewDr7 |= uGstDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
1606 }
1607 else
1608 uNewDr0 = 0;
1609
1610 /* bp 1 */
1611 RTGCUINTREG uNewDr1;
1612 if (uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1))
1613 {
1614 uNewDr7 |= uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
1615 uNewDr1 = DBGFBpGetDR1(pVM);
1616 }
1617 else if (uGstDr7 & (X86_DR7_L1 | X86_DR7_G1))
1618 {
1619 uNewDr1 = CPUMGetGuestDR1(pVCpu);
1620#ifndef IN_RING0
1621 if (fRawModeEnabled && MMHyperIsInsideArea(pVM, uNewDr1))
1622 uNewDr1 = 0;
1623 else
1624#endif
1625 uNewDr7 |= uGstDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
1626 }
1627 else
1628 uNewDr1 = 0;
1629
1630 /* bp 2 */
1631 RTGCUINTREG uNewDr2;
1632 if (uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2))
1633 {
1634 uNewDr7 |= uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
1635 uNewDr2 = DBGFBpGetDR2(pVM);
1636 }
1637 else if (uGstDr7 & (X86_DR7_L2 | X86_DR7_G2))
1638 {
1639 uNewDr2 = CPUMGetGuestDR2(pVCpu);
1640#ifndef IN_RING0
1641 if (fRawModeEnabled && MMHyperIsInsideArea(pVM, uNewDr2))
1642 uNewDr2 = 0;
1643 else
1644#endif
1645 uNewDr7 |= uGstDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
1646 }
1647 else
1648 uNewDr2 = 0;
1649
1650 /* bp 3 */
1651 RTGCUINTREG uNewDr3;
1652 if (uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3))
1653 {
1654 uNewDr7 |= uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
1655 uNewDr3 = DBGFBpGetDR3(pVM);
1656 }
1657 else if (uGstDr7 & (X86_DR7_L3 | X86_DR7_G3))
1658 {
1659 uNewDr3 = CPUMGetGuestDR3(pVCpu);
1660#ifndef IN_RING0
1661 if (fRawModeEnabled && MMHyperIsInsideArea(pVM, uNewDr3))
1662 uNewDr3 = 0;
1663 else
1664#endif
1665 uNewDr7 |= uGstDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
1666 }
1667 else
1668 uNewDr3 = 0;
1669
1670 /*
1671 * Apply the updates.
1672 */
1673#ifdef IN_RC
1674 /* Make sure to save host registers first. */
1675 if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HOST))
1676 {
1677 if (!(pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS_HOST))
1678 {
1679 pVCpu->cpum.s.Host.dr6 = ASMGetDR6();
1680 pVCpu->cpum.s.Host.dr7 = ASMGetDR7();
1681 }
1682 pVCpu->cpum.s.Host.dr0 = ASMGetDR0();
1683 pVCpu->cpum.s.Host.dr1 = ASMGetDR1();
1684 pVCpu->cpum.s.Host.dr2 = ASMGetDR2();
1685 pVCpu->cpum.s.Host.dr3 = ASMGetDR3();
1686 pVCpu->cpum.s.fUseFlags |= CPUM_USED_DEBUG_REGS_HOST | CPUM_USE_DEBUG_REGS_HYPER | CPUM_USED_DEBUG_REGS_HYPER;
1687
1688 /* We haven't loaded any hyper DRxes yet, so we'll have to load them all now. */
1689 pVCpu->cpum.s.Hyper.dr[0] = uNewDr0;
1690 ASMSetDR0(uNewDr0);
1691 pVCpu->cpum.s.Hyper.dr[1] = uNewDr1;
1692 ASMSetDR1(uNewDr1);
1693 pVCpu->cpum.s.Hyper.dr[2] = uNewDr2;
1694 ASMSetDR2(uNewDr2);
1695 pVCpu->cpum.s.Hyper.dr[3] = uNewDr3;
1696 ASMSetDR3(uNewDr3);
1697 ASMSetDR6(X86_DR6_INIT_VAL);
1698 pVCpu->cpum.s.Hyper.dr[7] = uNewDr7;
1699 ASMSetDR7(uNewDr7);
1700 }
1701 else
1702#endif
1703 {
1704 pVCpu->cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS_HYPER;
1705 if (uNewDr3 != pVCpu->cpum.s.Hyper.dr[3])
1706 CPUMSetHyperDR3(pVCpu, uNewDr3);
1707 if (uNewDr2 != pVCpu->cpum.s.Hyper.dr[2])
1708 CPUMSetHyperDR2(pVCpu, uNewDr2);
1709 if (uNewDr1 != pVCpu->cpum.s.Hyper.dr[1])
1710 CPUMSetHyperDR1(pVCpu, uNewDr1);
1711 if (uNewDr0 != pVCpu->cpum.s.Hyper.dr[0])
1712 CPUMSetHyperDR0(pVCpu, uNewDr0);
1713 if (uNewDr7 != pVCpu->cpum.s.Hyper.dr[7])
1714 CPUMSetHyperDR7(pVCpu, uNewDr7);
1715 }
1716 }
1717#ifdef IN_RING0
1718 else if (CPUMIsGuestDebugStateActive(pVCpu))
1719 {
1720 /*
1721 * Reload the register that was modified. Normally this won't happen
1722 * as we won't intercept DRx writes when not having the hyper debug
1723 * state loaded, but in case we do for some reason we'll simply deal
1724 * with it.
1725 */
1726 switch (iGstReg)
1727 {
1728 case 0: ASMSetDR0(CPUMGetGuestDR0(pVCpu)); break;
1729 case 1: ASMSetDR1(CPUMGetGuestDR1(pVCpu)); break;
1730 case 2: ASMSetDR2(CPUMGetGuestDR2(pVCpu)); break;
1731 case 3: ASMSetDR3(CPUMGetGuestDR3(pVCpu)); break;
1732 default:
1733 AssertReturn(iGstReg != UINT8_MAX, VERR_INTERNAL_ERROR_3);
1734 }
1735 }
1736#endif
1737 else
1738 {
1739 /*
1740 * No active debug state any more. In raw-mode this means we have to
1741 * make sure DR7 has everything disabled now, if we armed it already.
1742 * In ring-0 we might end up here when just single stepping.
1743 */
1744#if defined(IN_RC) || defined(IN_RING0)
1745 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HYPER)
1746 {
1747# ifdef IN_RC
1748 ASMSetDR7(X86_DR7_INIT_VAL);
1749# endif
1750 if (pVCpu->cpum.s.Hyper.dr[0])
1751 ASMSetDR0(0);
1752 if (pVCpu->cpum.s.Hyper.dr[1])
1753 ASMSetDR1(0);
1754 if (pVCpu->cpum.s.Hyper.dr[2])
1755 ASMSetDR2(0);
1756 if (pVCpu->cpum.s.Hyper.dr[3])
1757 ASMSetDR3(0);
1758 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_DEBUG_REGS_HYPER;
1759 }
1760#endif
1761 pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS_HYPER;
1762
1763 /* Clear all the registers. */
1764 pVCpu->cpum.s.Hyper.dr[7] = X86_DR7_RA1_MASK;
1765 pVCpu->cpum.s.Hyper.dr[3] = 0;
1766 pVCpu->cpum.s.Hyper.dr[2] = 0;
1767 pVCpu->cpum.s.Hyper.dr[1] = 0;
1768 pVCpu->cpum.s.Hyper.dr[0] = 0;
1769
1770 }
1771 Log2(("CPUMRecalcHyperDRx: fUseFlags=%#x %RGr %RGr %RGr %RGr %RGr %RGr\n",
1772 pVCpu->cpum.s.fUseFlags, pVCpu->cpum.s.Hyper.dr[0], pVCpu->cpum.s.Hyper.dr[1],
1773 pVCpu->cpum.s.Hyper.dr[2], pVCpu->cpum.s.Hyper.dr[3], pVCpu->cpum.s.Hyper.dr[6],
1774 pVCpu->cpum.s.Hyper.dr[7]));
1775
1776 return VINF_SUCCESS;
1777}
1778
1779
1780/**
1781 * Set the guest XCR0 register.
1782 *
1783 * Will load additional state if the FPU state is already loaded (in ring-0 &
1784 * raw-mode context).
1785 *
1786 * @returns VINF_SUCCESS on success, VERR_CPUM_RAISE_GP_0 on invalid input
1787 * value.
1788 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1789 * @param uNewValue The new value.
1790 * @thread EMT(pVCpu)
1791 */
1792VMM_INT_DECL(int) CPUMSetGuestXcr0(PVMCPU pVCpu, uint64_t uNewValue)
1793{
1794 if ( (uNewValue & ~pVCpu->CTX_SUFF(pVM)->cpum.s.fXStateGuestMask) == 0
1795 /* The X87 bit cannot be cleared. */
1796 && (uNewValue & XSAVE_C_X87)
1797 /* AVX requires SSE. */
1798 && (uNewValue & (XSAVE_C_SSE | XSAVE_C_YMM)) != XSAVE_C_YMM
1799 /* AVX-512 requires YMM, SSE and all of its three components to be enabled. */
1800 && ( (uNewValue & (XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI)) == 0
1801 || (uNewValue & (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI))
1802 == (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI) )
1803 )
1804 {
1805 pVCpu->cpum.s.Guest.aXcr[0] = uNewValue;
1806
1807 /* If more state components are enabled, we need to take care to load
1808 them if the FPU/SSE state is already loaded. May otherwise leak
1809 host state to the guest. */
1810 uint64_t fNewComponents = ~pVCpu->cpum.s.Guest.fXStateMask & uNewValue;
1811 if (fNewComponents)
1812 {
1813#if defined(IN_RING0) || defined(IN_RC)
1814 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST)
1815 {
1816 if (pVCpu->cpum.s.Guest.fXStateMask != 0)
1817 /* Adding more components. */
1818 ASMXRstor(pVCpu->cpum.s.Guest.CTX_SUFF(pXState), fNewComponents);
1819 else
1820 {
1821 /* We're switching from FXSAVE/FXRSTOR to XSAVE/XRSTOR. */
1822 pVCpu->cpum.s.Guest.fXStateMask |= XSAVE_C_X87 | XSAVE_C_SSE;
1823 if (uNewValue & ~(XSAVE_C_X87 | XSAVE_C_SSE))
1824 ASMXRstor(pVCpu->cpum.s.Guest.CTX_SUFF(pXState), uNewValue & ~(XSAVE_C_X87 | XSAVE_C_SSE));
1825 }
1826 }
1827#endif
1828 pVCpu->cpum.s.Guest.fXStateMask |= uNewValue;
1829 }
1830 return VINF_SUCCESS;
1831 }
1832 return VERR_CPUM_RAISE_GP_0;
1833}
1834
1835
1836/**
1837 * Tests if the guest has No-Execute Page Protection Enabled (NXE).
1838 *
1839 * @returns true if in real mode, otherwise false.
1840 * @param pVCpu The cross context virtual CPU structure.
1841 */
1842VMMDECL(bool) CPUMIsGuestNXEnabled(PVMCPU pVCpu)
1843{
1844 return !!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE);
1845}
1846
1847
1848/**
1849 * Tests if the guest has the Page Size Extension enabled (PSE).
1850 *
1851 * @returns true if in real mode, otherwise false.
1852 * @param pVCpu The cross context virtual CPU structure.
1853 */
1854VMMDECL(bool) CPUMIsGuestPageSizeExtEnabled(PVMCPU pVCpu)
1855{
1856 /* PAE or AMD64 implies support for big pages regardless of CR4.PSE */
1857 return !!(pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PSE | X86_CR4_PAE));
1858}
1859
1860
1861/**
1862 * Tests if the guest has the paging enabled (PG).
1863 *
1864 * @returns true if in real mode, otherwise false.
1865 * @param pVCpu The cross context virtual CPU structure.
1866 */
1867VMMDECL(bool) CPUMIsGuestPagingEnabled(PVMCPU pVCpu)
1868{
1869 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG);
1870}
1871
1872
1873/**
1874 * Tests if the guest has the paging enabled (PG).
1875 *
1876 * @returns true if in real mode, otherwise false.
1877 * @param pVCpu The cross context virtual CPU structure.
1878 */
1879VMMDECL(bool) CPUMIsGuestR0WriteProtEnabled(PVMCPU pVCpu)
1880{
1881 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_WP);
1882}
1883
1884
1885/**
1886 * Tests if the guest is running in real mode or not.
1887 *
1888 * @returns true if in real mode, otherwise false.
1889 * @param pVCpu The cross context virtual CPU structure.
1890 */
1891VMMDECL(bool) CPUMIsGuestInRealMode(PVMCPU pVCpu)
1892{
1893 return !(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
1894}
1895
1896
1897/**
1898 * Tests if the guest is running in real or virtual 8086 mode.
1899 *
1900 * @returns @c true if it is, @c false if not.
1901 * @param pVCpu The cross context virtual CPU structure.
1902 */
1903VMMDECL(bool) CPUMIsGuestInRealOrV86Mode(PVMCPU pVCpu)
1904{
1905 return !(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE)
1906 || pVCpu->cpum.s.Guest.eflags.Bits.u1VM; /** @todo verify that this cannot be set in long mode. */
1907}
1908
1909
1910/**
1911 * Tests if the guest is running in protected or not.
1912 *
1913 * @returns true if in protected mode, otherwise false.
1914 * @param pVCpu The cross context virtual CPU structure.
1915 */
1916VMMDECL(bool) CPUMIsGuestInProtectedMode(PVMCPU pVCpu)
1917{
1918 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
1919}
1920
1921
1922/**
1923 * Tests if the guest is running in paged protected or not.
1924 *
1925 * @returns true if in paged protected mode, otherwise false.
1926 * @param pVCpu The cross context virtual CPU structure.
1927 */
1928VMMDECL(bool) CPUMIsGuestInPagedProtectedMode(PVMCPU pVCpu)
1929{
1930 return (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
1931}
1932
1933
1934/**
1935 * Tests if the guest is running in long mode or not.
1936 *
1937 * @returns true if in long mode, otherwise false.
1938 * @param pVCpu The cross context virtual CPU structure.
1939 */
1940VMMDECL(bool) CPUMIsGuestInLongMode(PVMCPU pVCpu)
1941{
1942 return (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
1943}
1944
1945
1946/**
1947 * Tests if the guest is running in PAE mode or not.
1948 *
1949 * @returns true if in PAE mode, otherwise false.
1950 * @param pVCpu The cross context virtual CPU structure.
1951 */
1952VMMDECL(bool) CPUMIsGuestInPAEMode(PVMCPU pVCpu)
1953{
1954 /* Intel mentions EFER.LMA and EFER.LME in different parts of their spec. We shall use EFER.LMA rather
1955 than EFER.LME as it reflects if the CPU has entered paging with EFER.LME set. */
1956 return (pVCpu->cpum.s.Guest.cr4 & X86_CR4_PAE)
1957 && (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG)
1958 && !(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA);
1959}
1960
1961
1962/**
1963 * Tests if the guest is running in 64 bits mode or not.
1964 *
1965 * @returns true if in 64 bits protected mode, otherwise false.
1966 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1967 */
1968VMMDECL(bool) CPUMIsGuestIn64BitCode(PVMCPU pVCpu)
1969{
1970 if (!CPUMIsGuestInLongMode(pVCpu))
1971 return false;
1972 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
1973 return pVCpu->cpum.s.Guest.cs.Attr.n.u1Long;
1974}
1975
1976
1977/**
1978 * Helper for CPUMIsGuestIn64BitCodeEx that handles lazy resolving of hidden CS
1979 * registers.
1980 *
1981 * @returns true if in 64 bits protected mode, otherwise false.
1982 * @param pCtx Pointer to the current guest CPU context.
1983 */
1984VMM_INT_DECL(bool) CPUMIsGuestIn64BitCodeSlow(PCPUMCTX pCtx)
1985{
1986 return CPUMIsGuestIn64BitCode(CPUM_GUEST_CTX_TO_VMCPU(pCtx));
1987}
1988
1989#ifdef VBOX_WITH_RAW_MODE_NOT_R0
1990
1991/**
1992 *
1993 * @returns @c true if we've entered raw-mode and selectors with RPL=1 are
1994 * really RPL=0, @c false if we've not (RPL=1 really is RPL=1).
1995 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1996 */
1997VMM_INT_DECL(bool) CPUMIsGuestInRawMode(PVMCPU pVCpu)
1998{
1999 return pVCpu->cpum.s.fRawEntered;
2000}
2001
2002/**
2003 * Transforms the guest CPU state to raw-ring mode.
2004 *
2005 * This function will change the any of the cs and ss register with DPL=0 to DPL=1.
2006 *
2007 * @returns VBox status code. (recompiler failure)
2008 * @param pVCpu The cross context virtual CPU structure.
2009 * @see @ref pg_raw
2010 */
2011VMM_INT_DECL(int) CPUMRawEnter(PVMCPU pVCpu)
2012{
2013 PVM pVM = pVCpu->CTX_SUFF(pVM);
2014
2015 Assert(!pVCpu->cpum.s.fRawEntered);
2016 Assert(!pVCpu->cpum.s.fRemEntered);
2017 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2018
2019 /*
2020 * Are we in Ring-0?
2021 */
2022 if ( pCtx->ss.Sel
2023 && (pCtx->ss.Sel & X86_SEL_RPL) == 0
2024 && !pCtx->eflags.Bits.u1VM)
2025 {
2026 /*
2027 * Enter execution mode.
2028 */
2029 PATMRawEnter(pVM, pCtx);
2030
2031 /*
2032 * Set CPL to Ring-1.
2033 */
2034 pCtx->ss.Sel |= 1;
2035 if ( pCtx->cs.Sel
2036 && (pCtx->cs.Sel & X86_SEL_RPL) == 0)
2037 pCtx->cs.Sel |= 1;
2038 }
2039 else
2040 {
2041# ifdef VBOX_WITH_RAW_RING1
2042 if ( EMIsRawRing1Enabled(pVM)
2043 && !pCtx->eflags.Bits.u1VM
2044 && (pCtx->ss.Sel & X86_SEL_RPL) == 1)
2045 {
2046 /* Set CPL to Ring-2. */
2047 pCtx->ss.Sel = (pCtx->ss.Sel & ~X86_SEL_RPL) | 2;
2048 if (pCtx->cs.Sel && (pCtx->cs.Sel & X86_SEL_RPL) == 1)
2049 pCtx->cs.Sel = (pCtx->cs.Sel & ~X86_SEL_RPL) | 2;
2050 }
2051# else
2052 AssertMsg((pCtx->ss.Sel & X86_SEL_RPL) >= 2 || pCtx->eflags.Bits.u1VM,
2053 ("ring-1 code not supported\n"));
2054# endif
2055 /*
2056 * PATM takes care of IOPL and IF flags for Ring-3 and Ring-2 code as well.
2057 */
2058 PATMRawEnter(pVM, pCtx);
2059 }
2060
2061 /*
2062 * Assert sanity.
2063 */
2064 AssertMsg((pCtx->eflags.u32 & X86_EFL_IF), ("X86_EFL_IF is clear\n"));
2065 AssertReleaseMsg(pCtx->eflags.Bits.u2IOPL == 0,
2066 ("X86_EFL_IOPL=%d CPL=%d\n", pCtx->eflags.Bits.u2IOPL, pCtx->ss.Sel & X86_SEL_RPL));
2067 Assert((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_PE)) == (X86_CR0_PG | X86_CR0_PE));
2068
2069 pCtx->eflags.u32 |= X86_EFL_IF; /* paranoia */
2070
2071 pVCpu->cpum.s.fRawEntered = true;
2072 return VINF_SUCCESS;
2073}
2074
2075
2076/**
2077 * Transforms the guest CPU state from raw-ring mode to correct values.
2078 *
2079 * This function will change any selector registers with DPL=1 to DPL=0.
2080 *
2081 * @returns Adjusted rc.
2082 * @param pVCpu The cross context virtual CPU structure.
2083 * @param rc Raw mode return code
2084 * @see @ref pg_raw
2085 */
2086VMM_INT_DECL(int) CPUMRawLeave(PVMCPU pVCpu, int rc)
2087{
2088 PVM pVM = pVCpu->CTX_SUFF(pVM);
2089
2090 /*
2091 * Don't leave if we've already left (in RC).
2092 */
2093 Assert(!pVCpu->cpum.s.fRemEntered);
2094 if (!pVCpu->cpum.s.fRawEntered)
2095 return rc;
2096 pVCpu->cpum.s.fRawEntered = false;
2097
2098 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2099 Assert(pCtx->eflags.Bits.u1VM || (pCtx->ss.Sel & X86_SEL_RPL));
2100 AssertMsg(pCtx->eflags.Bits.u1VM || pCtx->eflags.Bits.u2IOPL < (unsigned)(pCtx->ss.Sel & X86_SEL_RPL),
2101 ("X86_EFL_IOPL=%d CPL=%d\n", pCtx->eflags.Bits.u2IOPL, pCtx->ss.Sel & X86_SEL_RPL));
2102
2103 /*
2104 * Are we executing in raw ring-1?
2105 */
2106 if ( (pCtx->ss.Sel & X86_SEL_RPL) == 1
2107 && !pCtx->eflags.Bits.u1VM)
2108 {
2109 /*
2110 * Leave execution mode.
2111 */
2112 PATMRawLeave(pVM, pCtx, rc);
2113 /* Not quite sure if this is really required, but shouldn't harm (too much anyways). */
2114 /** @todo See what happens if we remove this. */
2115 if ((pCtx->ds.Sel & X86_SEL_RPL) == 1)
2116 pCtx->ds.Sel &= ~X86_SEL_RPL;
2117 if ((pCtx->es.Sel & X86_SEL_RPL) == 1)
2118 pCtx->es.Sel &= ~X86_SEL_RPL;
2119 if ((pCtx->fs.Sel & X86_SEL_RPL) == 1)
2120 pCtx->fs.Sel &= ~X86_SEL_RPL;
2121 if ((pCtx->gs.Sel & X86_SEL_RPL) == 1)
2122 pCtx->gs.Sel &= ~X86_SEL_RPL;
2123
2124 /*
2125 * Ring-1 selector => Ring-0.
2126 */
2127 pCtx->ss.Sel &= ~X86_SEL_RPL;
2128 if ((pCtx->cs.Sel & X86_SEL_RPL) == 1)
2129 pCtx->cs.Sel &= ~X86_SEL_RPL;
2130 }
2131 else
2132 {
2133 /*
2134 * PATM is taking care of the IOPL and IF flags for us.
2135 */
2136 PATMRawLeave(pVM, pCtx, rc);
2137 if (!pCtx->eflags.Bits.u1VM)
2138 {
2139# ifdef VBOX_WITH_RAW_RING1
2140 if ( EMIsRawRing1Enabled(pVM)
2141 && (pCtx->ss.Sel & X86_SEL_RPL) == 2)
2142 {
2143 /* Not quite sure if this is really required, but shouldn't harm (too much anyways). */
2144 /** @todo See what happens if we remove this. */
2145 if ((pCtx->ds.Sel & X86_SEL_RPL) == 2)
2146 pCtx->ds.Sel = (pCtx->ds.Sel & ~X86_SEL_RPL) | 1;
2147 if ((pCtx->es.Sel & X86_SEL_RPL) == 2)
2148 pCtx->es.Sel = (pCtx->es.Sel & ~X86_SEL_RPL) | 1;
2149 if ((pCtx->fs.Sel & X86_SEL_RPL) == 2)
2150 pCtx->fs.Sel = (pCtx->fs.Sel & ~X86_SEL_RPL) | 1;
2151 if ((pCtx->gs.Sel & X86_SEL_RPL) == 2)
2152 pCtx->gs.Sel = (pCtx->gs.Sel & ~X86_SEL_RPL) | 1;
2153
2154 /*
2155 * Ring-2 selector => Ring-1.
2156 */
2157 pCtx->ss.Sel = (pCtx->ss.Sel & ~X86_SEL_RPL) | 1;
2158 if ((pCtx->cs.Sel & X86_SEL_RPL) == 2)
2159 pCtx->cs.Sel = (pCtx->cs.Sel & ~X86_SEL_RPL) | 1;
2160 }
2161 else
2162 {
2163# endif
2164 /** @todo See what happens if we remove this. */
2165 if ((pCtx->ds.Sel & X86_SEL_RPL) == 1)
2166 pCtx->ds.Sel &= ~X86_SEL_RPL;
2167 if ((pCtx->es.Sel & X86_SEL_RPL) == 1)
2168 pCtx->es.Sel &= ~X86_SEL_RPL;
2169 if ((pCtx->fs.Sel & X86_SEL_RPL) == 1)
2170 pCtx->fs.Sel &= ~X86_SEL_RPL;
2171 if ((pCtx->gs.Sel & X86_SEL_RPL) == 1)
2172 pCtx->gs.Sel &= ~X86_SEL_RPL;
2173# ifdef VBOX_WITH_RAW_RING1
2174 }
2175# endif
2176 }
2177 }
2178
2179 return rc;
2180}
2181
2182#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
2183
2184/**
2185 * Updates the EFLAGS while we're in raw-mode.
2186 *
2187 * @param pVCpu The cross context virtual CPU structure.
2188 * @param fEfl The new EFLAGS value.
2189 */
2190VMMDECL(void) CPUMRawSetEFlags(PVMCPU pVCpu, uint32_t fEfl)
2191{
2192#ifdef VBOX_WITH_RAW_MODE_NOT_R0
2193 if (pVCpu->cpum.s.fRawEntered)
2194 PATMRawSetEFlags(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.s.Guest, fEfl);
2195 else
2196#endif
2197 pVCpu->cpum.s.Guest.eflags.u32 = fEfl;
2198}
2199
2200
2201/**
2202 * Gets the EFLAGS while we're in raw-mode.
2203 *
2204 * @returns The eflags.
2205 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2206 */
2207VMMDECL(uint32_t) CPUMRawGetEFlags(PVMCPU pVCpu)
2208{
2209#ifdef VBOX_WITH_RAW_MODE_NOT_R0
2210 if (pVCpu->cpum.s.fRawEntered)
2211 return PATMRawGetEFlags(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.s.Guest);
2212#endif
2213 return pVCpu->cpum.s.Guest.eflags.u32;
2214}
2215
2216
2217/**
2218 * Sets the specified changed flags (CPUM_CHANGED_*).
2219 *
2220 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2221 * @param fChangedAdd The changed flags to add.
2222 */
2223VMMDECL(void) CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedAdd)
2224{
2225 pVCpu->cpum.s.fChanged |= fChangedAdd;
2226}
2227
2228
2229/**
2230 * Checks if the CPU supports the XSAVE and XRSTOR instruction.
2231 *
2232 * @returns true if supported.
2233 * @returns false if not supported.
2234 * @param pVM The cross context VM structure.
2235 */
2236VMMDECL(bool) CPUMSupportsXSave(PVM pVM)
2237{
2238 return pVM->cpum.s.HostFeatures.fXSaveRstor != 0;
2239}
2240
2241
2242/**
2243 * Checks if the host OS uses the SYSENTER / SYSEXIT instructions.
2244 * @returns true if used.
2245 * @returns false if not used.
2246 * @param pVM The cross context VM structure.
2247 */
2248VMMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM)
2249{
2250 return RT_BOOL(pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSENTER);
2251}
2252
2253
2254/**
2255 * Checks if the host OS uses the SYSCALL / SYSRET instructions.
2256 * @returns true if used.
2257 * @returns false if not used.
2258 * @param pVM The cross context VM structure.
2259 */
2260VMMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM)
2261{
2262 return RT_BOOL(pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSCALL);
2263}
2264
2265#ifdef IN_RC
2266
2267/**
2268 * Lazily sync in the FPU/XMM state.
2269 *
2270 * @returns VBox status code.
2271 * @param pVCpu The cross context virtual CPU structure.
2272 */
2273VMMDECL(int) CPUMHandleLazyFPU(PVMCPU pVCpu)
2274{
2275 return cpumHandleLazyFPUAsm(&pVCpu->cpum.s);
2276}
2277
2278#endif /* !IN_RC */
2279
2280/**
2281 * Checks if we activated the FPU/XMM state of the guest OS.
2282 *
2283 * This differs from CPUMIsGuestFPUStateLoaded() in that it refers to the next
2284 * time we'll be executing guest code, so it may return true for 64-on-32 when
2285 * we still haven't actually loaded the FPU status, just scheduled it to be
2286 * loaded the next time we go thru the world switcher (CPUM_SYNC_FPU_STATE).
2287 *
2288 * @returns true / false.
2289 * @param pVCpu The cross context virtual CPU structure.
2290 */
2291VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCpu)
2292{
2293 return RT_BOOL(pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU_GUEST | CPUM_SYNC_FPU_STATE));
2294}
2295
2296
2297/**
2298 * Checks if we've really loaded the FPU/XMM state of the guest OS.
2299 *
2300 * @returns true / false.
2301 * @param pVCpu The cross context virtual CPU structure.
2302 */
2303VMMDECL(bool) CPUMIsGuestFPUStateLoaded(PVMCPU pVCpu)
2304{
2305 return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST);
2306}
2307
2308
2309/**
2310 * Checks if we saved the FPU/XMM state of the host OS.
2311 *
2312 * @returns true / false.
2313 * @param pVCpu The cross context virtual CPU structure.
2314 */
2315VMMDECL(bool) CPUMIsHostFPUStateSaved(PVMCPU pVCpu)
2316{
2317 return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_HOST);
2318}
2319
2320
2321/**
2322 * Checks if the guest debug state is active.
2323 *
2324 * @returns boolean
2325 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2326 */
2327VMMDECL(bool) CPUMIsGuestDebugStateActive(PVMCPU pVCpu)
2328{
2329 return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST);
2330}
2331
2332
2333/**
2334 * Checks if the guest debug state is to be made active during the world-switch
2335 * (currently only used for the 32->64 switcher case).
2336 *
2337 * @returns boolean
2338 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2339 */
2340VMMDECL(bool) CPUMIsGuestDebugStateActivePending(PVMCPU pVCpu)
2341{
2342 return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_DEBUG_REGS_GUEST);
2343}
2344
2345
2346/**
2347 * Checks if the hyper debug state is active.
2348 *
2349 * @returns boolean
2350 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2351 */
2352VMMDECL(bool) CPUMIsHyperDebugStateActive(PVMCPU pVCpu)
2353{
2354 return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HYPER);
2355}
2356
2357
2358/**
2359 * Checks if the hyper debug state is to be made active during the world-switch
2360 * (currently only used for the 32->64 switcher case).
2361 *
2362 * @returns boolean
2363 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2364 */
2365VMMDECL(bool) CPUMIsHyperDebugStateActivePending(PVMCPU pVCpu)
2366{
2367 return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_DEBUG_REGS_HYPER);
2368}
2369
2370
2371/**
2372 * Mark the guest's debug state as inactive.
2373 *
2374 * @returns boolean
2375 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2376 * @todo This API doesn't make sense any more.
2377 */
2378VMMDECL(void) CPUMDeactivateGuestDebugState(PVMCPU pVCpu)
2379{
2380 Assert(!(pVCpu->cpum.s.fUseFlags & (CPUM_USED_DEBUG_REGS_GUEST | CPUM_USED_DEBUG_REGS_HYPER | CPUM_USED_DEBUG_REGS_HOST)));
2381 NOREF(pVCpu);
2382}
2383
2384
2385/**
2386 * Get the current privilege level of the guest.
2387 *
2388 * @returns CPL
2389 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2390 */
2391VMMDECL(uint32_t) CPUMGetGuestCPL(PVMCPU pVCpu)
2392{
2393 /*
2394 * CPL can reliably be found in SS.DPL (hidden regs valid) or SS if not.
2395 *
2396 * Note! We used to check CS.DPL here, assuming it was always equal to
2397 * CPL even if a conforming segment was loaded. But this turned out to
2398 * only apply to older AMD-V. With VT-x we had an ACP2 regression
2399 * during install after a far call to ring 2 with VT-x. Then on newer
2400 * AMD-V CPUs we have to move the VMCB.guest.u8CPL into cs.Attr.n.u2Dpl
2401 * as well as ss.Attr.n.u2Dpl to make this (and other) code work right.
2402 *
2403 * So, forget CS.DPL, always use SS.DPL.
2404 *
2405 * Note! The SS RPL is always equal to the CPL, while the CS RPL
2406 * isn't necessarily equal if the segment is conforming.
2407 * See section 4.11.1 in the AMD manual.
2408 *
2409 * Update: Where the heck does it say CS.RPL can differ from CPL other than
2410 * right after real->prot mode switch and when in V8086 mode? That
2411 * section says the RPL specified in a direct transfere (call, jmp,
2412 * ret) is not the one loaded into CS. Besides, if CS.RPL != CPL
2413 * it would be impossible for an exception handle or the iret
2414 * instruction to figure out whether SS:ESP are part of the frame
2415 * or not. VBox or qemu bug must've lead to this misconception.
2416 *
2417 * Update2: On an AMD bulldozer system here, I've no trouble loading a null
2418 * selector into SS with an RPL other than the CPL when CPL != 3 and
2419 * we're in 64-bit mode. The intel dev box doesn't allow this, on
2420 * RPL = CPL. Weird.
2421 */
2422 uint32_t uCpl;
2423 if (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE)
2424 {
2425 if (!pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
2426 {
2427 if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.s.Guest.ss))
2428 uCpl = pVCpu->cpum.s.Guest.ss.Attr.n.u2Dpl;
2429 else
2430 {
2431 uCpl = (pVCpu->cpum.s.Guest.ss.Sel & X86_SEL_RPL);
2432#ifdef VBOX_WITH_RAW_MODE_NOT_R0
2433# ifdef VBOX_WITH_RAW_RING1
2434 if (pVCpu->cpum.s.fRawEntered)
2435 {
2436 if ( uCpl == 2
2437 && EMIsRawRing1Enabled(pVCpu->CTX_SUFF(pVM)))
2438 uCpl = 1;
2439 else if (uCpl == 1)
2440 uCpl = 0;
2441 }
2442 Assert(uCpl != 2); /* ring 2 support not allowed anymore. */
2443# else
2444 if (uCpl == 1)
2445 uCpl = 0;
2446# endif
2447#endif
2448 }
2449 }
2450 else
2451 uCpl = 3; /* V86 has CPL=3; REM doesn't set DPL=3 in V8086 mode. See @bugref{5130}. */
2452 }
2453 else
2454 uCpl = 0; /* Real mode is zero; CPL set to 3 for VT-x real-mode emulation. */
2455 return uCpl;
2456}
2457
2458
2459/**
2460 * Gets the current guest CPU mode.
2461 *
2462 * If paging mode is what you need, check out PGMGetGuestMode().
2463 *
2464 * @returns The CPU mode.
2465 * @param pVCpu The cross context virtual CPU structure.
2466 */
2467VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu)
2468{
2469 CPUMMODE enmMode;
2470 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
2471 enmMode = CPUMMODE_REAL;
2472 else if (!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
2473 enmMode = CPUMMODE_PROTECTED;
2474 else
2475 enmMode = CPUMMODE_LONG;
2476
2477 return enmMode;
2478}
2479
2480
2481/**
2482 * Figure whether the CPU is currently executing 16, 32 or 64 bit code.
2483 *
2484 * @returns 16, 32 or 64.
2485 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2486 */
2487VMMDECL(uint32_t) CPUMGetGuestCodeBits(PVMCPU pVCpu)
2488{
2489 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
2490 return 16;
2491
2492 if (pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
2493 {
2494 Assert(!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA));
2495 return 16;
2496 }
2497
2498 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
2499 if ( pVCpu->cpum.s.Guest.cs.Attr.n.u1Long
2500 && (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
2501 return 64;
2502
2503 if (pVCpu->cpum.s.Guest.cs.Attr.n.u1DefBig)
2504 return 32;
2505
2506 return 16;
2507}
2508
2509
2510VMMDECL(DISCPUMODE) CPUMGetGuestDisMode(PVMCPU pVCpu)
2511{
2512 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
2513 return DISCPUMODE_16BIT;
2514
2515 if (pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
2516 {
2517 Assert(!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA));
2518 return DISCPUMODE_16BIT;
2519 }
2520
2521 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
2522 if ( pVCpu->cpum.s.Guest.cs.Attr.n.u1Long
2523 && (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
2524 return DISCPUMODE_64BIT;
2525
2526 if (pVCpu->cpum.s.Guest.cs.Attr.n.u1DefBig)
2527 return DISCPUMODE_32BIT;
2528
2529 return DISCPUMODE_16BIT;
2530}
2531
2532
2533/**
2534 * Gets the guest MXCSR_MASK value.
2535 *
2536 * This does not access the x87 state, but the value we determined at VM
2537 * initialization.
2538 *
2539 * @returns MXCSR mask.
2540 * @param pVM The cross context VM structure.
2541 */
2542VMMDECL(uint32_t) CPUMGetGuestMxCsrMask(PVM pVM)
2543{
2544 return pVM->cpum.s.GuestInfo.fMxCsrMask;
2545}
2546
2547
2548/**
2549 * Checks whether the SVM nested-guest is in a state to receive physical (APIC)
2550 * interrupts.
2551 *
2552 * @returns VBox status code.
2553 * @retval true if it's ready, false otherwise.
2554 *
2555 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2556 * @param pCtx The guest-CPU context.
2557 *
2558 * @sa hmR0SvmCanNstGstTakePhysIntr.
2559 */
2560VMM_INT_DECL(bool) CPUMCanSvmNstGstTakePhysIntr(PVMCPU pVCpu, PCCPUMCTX pCtx)
2561{
2562 /** @todo Optimization: Avoid this function call and use a pointer to the
2563 * relevant eflags instead (setup during VMRUN instruction emulation). */
2564#ifdef IN_RC
2565 RT_NOREF2(pVCpu, pCtx);
2566 AssertReleaseFailedReturn(false);
2567#else
2568 Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
2569 Assert(pCtx->hwvirt.fGif);
2570
2571 X86EFLAGS fEFlags;
2572 if (CPUMIsGuestSvmVirtIntrMasking(pVCpu, pCtx))
2573 fEFlags.u = pCtx->hwvirt.svm.HostState.rflags.u;
2574 else
2575 fEFlags.u = pCtx->eflags.u;
2576
2577 return fEFlags.Bits.u1IF;
2578#endif
2579}
2580
2581
2582/**
2583 * Checks whether the SVM nested-guest is in a state to receive virtual (setup
2584 * for injection by VMRUN instruction) interrupts.
2585 *
2586 * @returns VBox status code.
2587 * @retval true if it's ready, false otherwise.
2588 *
2589 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2590 * @param pCtx The guest-CPU context.
2591 */
2592VMM_INT_DECL(bool) CPUMCanSvmNstGstTakeVirtIntr(PVMCPU pVCpu, PCCPUMCTX pCtx)
2593{
2594#ifdef IN_RC
2595 RT_NOREF2(pVCpu, pCtx);
2596 AssertReleaseFailedReturn(false);
2597#else
2598 Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
2599 Assert(pCtx->hwvirt.fGif);
2600
2601 PCSVMVMCBCTRL pVmcbCtrl = &pCtx->hwvirt.svm.CTX_SUFF(pVmcb)->ctrl;
2602 PCSVMINTCTRL pVmcbIntCtrl = &pVmcbCtrl->IntCtrl;
2603 if ( !pVmcbIntCtrl->n.u1IgnoreTPR
2604 && pVmcbIntCtrl->n.u4VIntrPrio <= pVmcbIntCtrl->n.u8VTPR)
2605 return false;
2606
2607 X86EFLAGS fEFlags;
2608 if (CPUMIsGuestSvmVirtIntrMasking(pVCpu, pCtx))
2609 fEFlags.u = pCtx->eflags.u;
2610 else
2611 fEFlags.u = pCtx->hwvirt.svm.HostState.rflags.u;
2612
2613 return fEFlags.Bits.u1IF;
2614#endif
2615}
2616
2617
2618/**
2619 * Gets the pending SVM nested-guest interrupt.
2620 *
2621 * @returns The nested-guest interrupt to inject.
2622 * @param pCtx The guest-CPU context.
2623 */
2624VMM_INT_DECL(uint8_t) CPUMGetSvmNstGstInterrupt(PCCPUMCTX pCtx)
2625{
2626#ifdef IN_RC
2627 RT_NOREF(pCtx);
2628 AssertReleaseFailedReturn(0);
2629#else
2630 PCSVMVMCBCTRL pVmcbCtrl = &pCtx->hwvirt.svm.CTX_SUFF(pVmcb)->ctrl;
2631 return pVmcbCtrl->IntCtrl.n.u8VIntrVector;
2632#endif
2633}
2634
2635
2636/**
2637 * Gets the SVM nested-guest virtual GIF.
2638 *
2639 * @returns The nested-guest virtual GIF.
2640 * @param pCtx The guest-CPU context.
2641 */
2642VMM_INT_DECL(bool) CPUMGetSvmNstGstVGif(PCCPUMCTX pCtx)
2643{
2644#ifdef IN_RC
2645 RT_NOREF(pCtx);
2646 AssertReleaseFailedReturn(false);
2647#else
2648 PCSVMVMCBCTRL pVmcbCtrl = &pCtx->hwvirt.svm.CTX_SUFF(pVmcb)->ctrl;
2649 PCSVMINTCTRL pVmcbIntCtrl = &pVmcbCtrl->IntCtrl;
2650 if (pVmcbIntCtrl->n.u1VGifEnable)
2651 return pVmcbIntCtrl->n.u1VGif;
2652 return true;
2653#endif
2654}
2655
2656
2657/**
2658 * Restores the host-state from the host-state save area as part of a \#VMEXIT.
2659 *
2660 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2661 * @param pCtx The guest-CPU context.
2662 */
2663VMM_INT_DECL(void) CPUMSvmVmExitRestoreHostState(PVMCPU pVCpu, PCPUMCTX pCtx)
2664{
2665 /*
2666 * Reload the guest's "host state".
2667 */
2668 PSVMHOSTSTATE pHostState = &pCtx->hwvirt.svm.HostState;
2669 pCtx->es = pHostState->es;
2670 pCtx->cs = pHostState->cs;
2671 pCtx->ss = pHostState->ss;
2672 pCtx->ds = pHostState->ds;
2673 pCtx->gdtr = pHostState->gdtr;
2674 pCtx->idtr = pHostState->idtr;
2675 CPUMSetGuestMsrEferNoCheck(pVCpu, pCtx->msrEFER, pHostState->uEferMsr);
2676 CPUMSetGuestCR0(pVCpu, pHostState->uCr0 | X86_CR0_PE);
2677 pCtx->cr3 = pHostState->uCr3;
2678 CPUMSetGuestCR4(pVCpu, pHostState->uCr4);
2679 pCtx->rflags = pHostState->rflags;
2680 pCtx->rflags.Bits.u1VM = 0;
2681 pCtx->rip = pHostState->uRip;
2682 pCtx->rsp = pHostState->uRsp;
2683 pCtx->rax = pHostState->uRax;
2684 pCtx->dr[7] &= ~(X86_DR7_ENABLED_MASK | X86_DR7_RAZ_MASK | X86_DR7_MBZ_MASK);
2685 pCtx->dr[7] |= X86_DR7_RA1_MASK;
2686 Assert(pCtx->ss.Attr.n.u2Dpl == 0);
2687
2688 /** @todo if RIP is not canonical or outside the CS segment limit, we need to
2689 * raise \#GP(0) in the guest. */
2690
2691 /** @todo check the loaded host-state for consistency. Figure out what
2692 * exactly this involves? */
2693}
2694
2695
2696/**
2697 * Saves the host-state to the host-state save area as part of a VMRUN.
2698 *
2699 * @param pCtx The guest-CPU context.
2700 * @param cbInstr The length of the VMRUN instruction in bytes.
2701 */
2702VMM_INT_DECL(void) CPUMSvmVmRunSaveHostState(PCPUMCTX pCtx, uint8_t cbInstr)
2703{
2704 PSVMHOSTSTATE pHostState = &pCtx->hwvirt.svm.HostState;
2705 pHostState->es = pCtx->es;
2706 pHostState->cs = pCtx->cs;
2707 pHostState->ss = pCtx->ss;
2708 pHostState->ds = pCtx->ds;
2709 pHostState->gdtr = pCtx->gdtr;
2710 pHostState->idtr = pCtx->idtr;
2711 pHostState->uEferMsr = pCtx->msrEFER;
2712 pHostState->uCr0 = pCtx->cr0;
2713 pHostState->uCr3 = pCtx->cr3;
2714 pHostState->uCr4 = pCtx->cr4;
2715 pHostState->rflags = pCtx->rflags;
2716 pHostState->uRip = pCtx->rip + cbInstr;
2717 pHostState->uRsp = pCtx->rsp;
2718 pHostState->uRax = pCtx->rax;
2719}
2720
2721
2722/**
2723 * Applies the TSC offset of a nested-guest if any and returns the new TSC
2724 * value for the guest (or nested-guest).
2725 *
2726 * @returns The TSC offset after applying any nested-guest TSC offset.
2727 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2728 * @param uTicks The guest TSC.
2729 *
2730 * @sa HMSvmNstGstApplyTscOffset.
2731 */
2732VMM_INT_DECL(uint64_t) CPUMApplyNestedGuestTscOffset(PVMCPU pVCpu, uint64_t uTicks)
2733{
2734#ifndef IN_RC
2735 PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2736 if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
2737 {
2738 if (!pCtx->hwvirt.svm.fHMCachedVmcb)
2739 {
2740 PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
2741 return uTicks + pVmcb->ctrl.u64TSCOffset;
2742 }
2743 return HMSvmNstGstApplyTscOffset(pVCpu, uTicks);
2744 }
2745
2746 /** @todo Intel. */
2747#else
2748 RT_NOREF(pVCpu);
2749#endif
2750 return uTicks;
2751}
2752
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