VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp@ 80253

Last change on this file since 80253 was 80253, checked in by vboxsync, 5 years ago

VMM: Started refactoring VMMAll/* for bugref:9217
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 95.5 KB
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1/* $Id: CPUMAllRegs.cpp 80253 2019-08-13 15:49:33Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor(/Manager) - Getters and Setters.
4 */
5
6/*
7 * Copyright (C) 2006-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define VBOX_BUGREF_9217_PART_I
23#define LOG_GROUP LOG_GROUP_CPUM
24#include <VBox/vmm/cpum.h>
25#include <VBox/vmm/dbgf.h>
26#include <VBox/vmm/apic.h>
27#include <VBox/vmm/pgm.h>
28#include <VBox/vmm/mm.h>
29#include <VBox/vmm/em.h>
30#include <VBox/vmm/nem.h>
31#include <VBox/vmm/hm.h>
32#include "CPUMInternal.h"
33#include <VBox/vmm/vmcc.h>
34#include <VBox/err.h>
35#include <VBox/dis.h>
36#include <VBox/log.h>
37#include <VBox/vmm/hm.h>
38#include <VBox/vmm/tm.h>
39#include <iprt/assert.h>
40#include <iprt/asm.h>
41#include <iprt/asm-amd64-x86.h>
42#ifdef IN_RING3
43# include <iprt/thread.h>
44#endif
45
46/** Disable stack frame pointer generation here. */
47#if defined(_MSC_VER) && !defined(DEBUG) && defined(RT_ARCH_X86)
48# pragma optimize("y", off)
49#endif
50
51AssertCompile2MemberOffsets(VM, cpum.s.HostFeatures, cpum.ro.HostFeatures);
52AssertCompile2MemberOffsets(VM, cpum.s.GuestFeatures, cpum.ro.GuestFeatures);
53
54
55/*********************************************************************************************************************************
56* Defined Constants And Macros *
57*********************************************************************************************************************************/
58/**
59 * Converts a CPUMCPU::Guest pointer into a VMCPU pointer.
60 *
61 * @returns Pointer to the Virtual CPU.
62 * @param a_pGuestCtx Pointer to the guest context.
63 */
64#define CPUM_GUEST_CTX_TO_VMCPU(a_pGuestCtx) RT_FROM_MEMBER(a_pGuestCtx, VMCPU, cpum.s.Guest)
65
66/**
67 * Lazily loads the hidden parts of a selector register when using raw-mode.
68 */
69#define CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(a_pVCpu, a_pSReg) \
70 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(a_pVCpu, a_pSReg))
71
72/** @def CPUM_INT_ASSERT_NOT_EXTRN
73 * Macro for asserting that @a a_fNotExtrn are present.
74 *
75 * @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
76 * @param a_fNotExtrn Mask of CPUMCTX_EXTRN_XXX bits to check.
77 */
78#define CPUM_INT_ASSERT_NOT_EXTRN(a_pVCpu, a_fNotExtrn) \
79 AssertMsg(!((a_pVCpu)->cpum.s.Guest.fExtrn & (a_fNotExtrn)), \
80 ("%#RX64; a_fNotExtrn=%#RX64\n", (a_pVCpu)->cpum.s.Guest.fExtrn, (a_fNotExtrn)))
81
82
83VMMDECL(void) CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3)
84{
85 pVCpu->cpum.s.Hyper.cr3 = cr3;
86}
87
88VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu)
89{
90 return pVCpu->cpum.s.Hyper.cr3;
91}
92
93
94/** @def MAYBE_LOAD_DRx
95 * Macro for updating DRx values in raw-mode and ring-0 contexts.
96 */
97#ifdef IN_RING0
98# define MAYBE_LOAD_DRx(a_pVCpu, a_fnLoad, a_uValue) do { a_fnLoad(a_uValue); } while (0)
99#else
100# define MAYBE_LOAD_DRx(a_pVCpu, a_fnLoad, a_uValue) do { } while (0)
101#endif
102
103VMMDECL(void) CPUMSetHyperDR0(PVMCPU pVCpu, RTGCUINTREG uDr0)
104{
105 pVCpu->cpum.s.Hyper.dr[0] = uDr0;
106 MAYBE_LOAD_DRx(pVCpu, ASMSetDR0, uDr0);
107}
108
109
110VMMDECL(void) CPUMSetHyperDR1(PVMCPU pVCpu, RTGCUINTREG uDr1)
111{
112 pVCpu->cpum.s.Hyper.dr[1] = uDr1;
113 MAYBE_LOAD_DRx(pVCpu, ASMSetDR1, uDr1);
114}
115
116
117VMMDECL(void) CPUMSetHyperDR2(PVMCPU pVCpu, RTGCUINTREG uDr2)
118{
119 pVCpu->cpum.s.Hyper.dr[2] = uDr2;
120 MAYBE_LOAD_DRx(pVCpu, ASMSetDR2, uDr2);
121}
122
123
124VMMDECL(void) CPUMSetHyperDR3(PVMCPU pVCpu, RTGCUINTREG uDr3)
125{
126 pVCpu->cpum.s.Hyper.dr[3] = uDr3;
127 MAYBE_LOAD_DRx(pVCpu, ASMSetDR3, uDr3);
128}
129
130
131VMMDECL(void) CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6)
132{
133 pVCpu->cpum.s.Hyper.dr[6] = uDr6;
134}
135
136
137VMMDECL(void) CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7)
138{
139 pVCpu->cpum.s.Hyper.dr[7] = uDr7;
140}
141
142
143VMMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVMCPU pVCpu)
144{
145 return pVCpu->cpum.s.Hyper.dr[0];
146}
147
148
149VMMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVMCPU pVCpu)
150{
151 return pVCpu->cpum.s.Hyper.dr[1];
152}
153
154
155VMMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVMCPU pVCpu)
156{
157 return pVCpu->cpum.s.Hyper.dr[2];
158}
159
160
161VMMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVMCPU pVCpu)
162{
163 return pVCpu->cpum.s.Hyper.dr[3];
164}
165
166
167VMMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVMCPU pVCpu)
168{
169 return pVCpu->cpum.s.Hyper.dr[6];
170}
171
172
173VMMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVMCPU pVCpu)
174{
175 return pVCpu->cpum.s.Hyper.dr[7];
176}
177
178
179/**
180 * Gets the pointer to the internal CPUMCTXCORE structure.
181 * This is only for reading in order to save a few calls.
182 *
183 * @param pVCpu The cross context virtual CPU structure.
184 */
185VMMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVMCPU pVCpu)
186{
187 return CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
188}
189
190
191/**
192 * Queries the pointer to the internal CPUMCTX structure.
193 *
194 * @returns The CPUMCTX pointer.
195 * @param pVCpu The cross context virtual CPU structure.
196 */
197VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu)
198{
199 return &pVCpu->cpum.s.Guest;
200}
201
202
203/**
204 * Queries the pointer to the internal CPUMCTXMSRS structure.
205 *
206 * This is for NEM only.
207 *
208 * @returns The CPUMCTX pointer.
209 * @param pVCpu The cross context virtual CPU structure.
210 */
211VMM_INT_DECL(PCPUMCTXMSRS) CPUMQueryGuestCtxMsrsPtr(PVMCPU pVCpu)
212{
213 return &pVCpu->cpum.s.GuestMsrs;
214}
215
216
217VMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit)
218{
219 pVCpu->cpum.s.Guest.gdtr.cbGdt = cbLimit;
220 pVCpu->cpum.s.Guest.gdtr.pGdt = GCPtrBase;
221 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_GDTR;
222 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GDTR;
223 return VINF_SUCCESS; /* formality, consider it void. */
224}
225
226
227VMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit)
228{
229 pVCpu->cpum.s.Guest.idtr.cbIdt = cbLimit;
230 pVCpu->cpum.s.Guest.idtr.pIdt = GCPtrBase;
231 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_IDTR;
232 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_IDTR;
233 return VINF_SUCCESS; /* formality, consider it void. */
234}
235
236
237VMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr)
238{
239 pVCpu->cpum.s.Guest.tr.Sel = tr;
240 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_TR;
241 return VINF_SUCCESS; /* formality, consider it void. */
242}
243
244
245VMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr)
246{
247 pVCpu->cpum.s.Guest.ldtr.Sel = ldtr;
248 /* The caller will set more hidden bits if it has them. */
249 pVCpu->cpum.s.Guest.ldtr.ValidSel = 0;
250 pVCpu->cpum.s.Guest.ldtr.fFlags = 0;
251 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_LDTR;
252 return VINF_SUCCESS; /* formality, consider it void. */
253}
254
255
256/**
257 * Set the guest CR0.
258 *
259 * When called in GC, the hyper CR0 may be updated if that is
260 * required. The caller only has to take special action if AM,
261 * WP, PG or PE changes.
262 *
263 * @returns VINF_SUCCESS (consider it void).
264 * @param pVCpu The cross context virtual CPU structure.
265 * @param cr0 The new CR0 value.
266 */
267VMMDECL(int) CPUMSetGuestCR0(PVMCPUCC pVCpu, uint64_t cr0)
268{
269 /*
270 * Check for changes causing TLB flushes (for REM).
271 * The caller is responsible for calling PGM when appropriate.
272 */
273 if ( (cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE))
274 != (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)))
275 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
276 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR0;
277
278 /*
279 * Let PGM know if the WP goes from 0 to 1 (netware WP0+RO+US hack)
280 */
281 if (((cr0 ^ pVCpu->cpum.s.Guest.cr0) & X86_CR0_WP) && (cr0 & X86_CR0_WP))
282 PGMCr0WpEnabled(pVCpu);
283
284 /* The ET flag is settable on a 386 and hardwired on 486+. */
285 if ( !(cr0 & X86_CR0_ET)
286 && pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.enmMicroarch != kCpumMicroarch_Intel_80386)
287 cr0 |= X86_CR0_ET;
288
289 pVCpu->cpum.s.Guest.cr0 = cr0;
290 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_CR0;
291 return VINF_SUCCESS;
292}
293
294
295VMMDECL(int) CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2)
296{
297 pVCpu->cpum.s.Guest.cr2 = cr2;
298 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_CR2;
299 return VINF_SUCCESS;
300}
301
302
303VMMDECL(int) CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3)
304{
305 pVCpu->cpum.s.Guest.cr3 = cr3;
306 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR3;
307 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_CR3;
308 return VINF_SUCCESS;
309}
310
311
312VMMDECL(int) CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4)
313{
314 /* Note! We don't bother with OSXSAVE and legacy CPUID patches. */
315
316 if ( (cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE))
317 != (pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE)))
318 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
319
320 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR4;
321 pVCpu->cpum.s.Guest.cr4 = cr4;
322 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_CR4;
323 return VINF_SUCCESS;
324}
325
326
327VMMDECL(int) CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags)
328{
329 pVCpu->cpum.s.Guest.eflags.u32 = eflags;
330 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_RFLAGS;
331 return VINF_SUCCESS;
332}
333
334
335VMMDECL(int) CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip)
336{
337 pVCpu->cpum.s.Guest.eip = eip;
338 return VINF_SUCCESS;
339}
340
341
342VMMDECL(int) CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax)
343{
344 pVCpu->cpum.s.Guest.eax = eax;
345 return VINF_SUCCESS;
346}
347
348
349VMMDECL(int) CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx)
350{
351 pVCpu->cpum.s.Guest.ebx = ebx;
352 return VINF_SUCCESS;
353}
354
355
356VMMDECL(int) CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx)
357{
358 pVCpu->cpum.s.Guest.ecx = ecx;
359 return VINF_SUCCESS;
360}
361
362
363VMMDECL(int) CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx)
364{
365 pVCpu->cpum.s.Guest.edx = edx;
366 return VINF_SUCCESS;
367}
368
369
370VMMDECL(int) CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp)
371{
372 pVCpu->cpum.s.Guest.esp = esp;
373 return VINF_SUCCESS;
374}
375
376
377VMMDECL(int) CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp)
378{
379 pVCpu->cpum.s.Guest.ebp = ebp;
380 return VINF_SUCCESS;
381}
382
383
384VMMDECL(int) CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi)
385{
386 pVCpu->cpum.s.Guest.esi = esi;
387 return VINF_SUCCESS;
388}
389
390
391VMMDECL(int) CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi)
392{
393 pVCpu->cpum.s.Guest.edi = edi;
394 return VINF_SUCCESS;
395}
396
397
398VMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss)
399{
400 pVCpu->cpum.s.Guest.ss.Sel = ss;
401 return VINF_SUCCESS;
402}
403
404
405VMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs)
406{
407 pVCpu->cpum.s.Guest.cs.Sel = cs;
408 return VINF_SUCCESS;
409}
410
411
412VMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds)
413{
414 pVCpu->cpum.s.Guest.ds.Sel = ds;
415 return VINF_SUCCESS;
416}
417
418
419VMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es)
420{
421 pVCpu->cpum.s.Guest.es.Sel = es;
422 return VINF_SUCCESS;
423}
424
425
426VMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs)
427{
428 pVCpu->cpum.s.Guest.fs.Sel = fs;
429 return VINF_SUCCESS;
430}
431
432
433VMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs)
434{
435 pVCpu->cpum.s.Guest.gs.Sel = gs;
436 return VINF_SUCCESS;
437}
438
439
440VMMDECL(void) CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val)
441{
442 pVCpu->cpum.s.Guest.msrEFER = val;
443 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_EFER;
444}
445
446
447VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PCVMCPU pVCpu, uint16_t *pcbLimit)
448{
449 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_IDTR);
450 if (pcbLimit)
451 *pcbLimit = pVCpu->cpum.s.Guest.idtr.cbIdt;
452 return pVCpu->cpum.s.Guest.idtr.pIdt;
453}
454
455
456VMMDECL(RTSEL) CPUMGetGuestTR(PCVMCPU pVCpu, PCPUMSELREGHID pHidden)
457{
458 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_TR);
459 if (pHidden)
460 *pHidden = pVCpu->cpum.s.Guest.tr;
461 return pVCpu->cpum.s.Guest.tr.Sel;
462}
463
464
465VMMDECL(RTSEL) CPUMGetGuestCS(PCVMCPU pVCpu)
466{
467 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CS);
468 return pVCpu->cpum.s.Guest.cs.Sel;
469}
470
471
472VMMDECL(RTSEL) CPUMGetGuestDS(PCVMCPU pVCpu)
473{
474 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DS);
475 return pVCpu->cpum.s.Guest.ds.Sel;
476}
477
478
479VMMDECL(RTSEL) CPUMGetGuestES(PCVMCPU pVCpu)
480{
481 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_ES);
482 return pVCpu->cpum.s.Guest.es.Sel;
483}
484
485
486VMMDECL(RTSEL) CPUMGetGuestFS(PCVMCPU pVCpu)
487{
488 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_FS);
489 return pVCpu->cpum.s.Guest.fs.Sel;
490}
491
492
493VMMDECL(RTSEL) CPUMGetGuestGS(PCVMCPU pVCpu)
494{
495 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_GS);
496 return pVCpu->cpum.s.Guest.gs.Sel;
497}
498
499
500VMMDECL(RTSEL) CPUMGetGuestSS(PCVMCPU pVCpu)
501{
502 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_SS);
503 return pVCpu->cpum.s.Guest.ss.Sel;
504}
505
506
507VMMDECL(uint64_t) CPUMGetGuestFlatPC(PVMCPU pVCpu)
508{
509 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_EFER);
510 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
511 if ( !CPUMIsGuestInLongMode(pVCpu)
512 || !pVCpu->cpum.s.Guest.cs.Attr.n.u1Long)
513 return pVCpu->cpum.s.Guest.eip + (uint32_t)pVCpu->cpum.s.Guest.cs.u64Base;
514 return pVCpu->cpum.s.Guest.rip + pVCpu->cpum.s.Guest.cs.u64Base;
515}
516
517
518VMMDECL(uint64_t) CPUMGetGuestFlatSP(PVMCPU pVCpu)
519{
520 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_SS | CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_EFER);
521 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.ss);
522 if ( !CPUMIsGuestInLongMode(pVCpu)
523 || !pVCpu->cpum.s.Guest.cs.Attr.n.u1Long)
524 return pVCpu->cpum.s.Guest.eip + (uint32_t)pVCpu->cpum.s.Guest.ss.u64Base;
525 return pVCpu->cpum.s.Guest.rip + pVCpu->cpum.s.Guest.ss.u64Base;
526}
527
528
529VMMDECL(RTSEL) CPUMGetGuestLDTR(PCVMCPU pVCpu)
530{
531 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_LDTR);
532 return pVCpu->cpum.s.Guest.ldtr.Sel;
533}
534
535
536VMMDECL(RTSEL) CPUMGetGuestLdtrEx(PCVMCPU pVCpu, uint64_t *pGCPtrBase, uint32_t *pcbLimit)
537{
538 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_LDTR);
539 *pGCPtrBase = pVCpu->cpum.s.Guest.ldtr.u64Base;
540 *pcbLimit = pVCpu->cpum.s.Guest.ldtr.u32Limit;
541 return pVCpu->cpum.s.Guest.ldtr.Sel;
542}
543
544
545VMMDECL(uint64_t) CPUMGetGuestCR0(PCVMCPU pVCpu)
546{
547 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0);
548 return pVCpu->cpum.s.Guest.cr0;
549}
550
551
552VMMDECL(uint64_t) CPUMGetGuestCR2(PCVMCPU pVCpu)
553{
554 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR2);
555 return pVCpu->cpum.s.Guest.cr2;
556}
557
558
559VMMDECL(uint64_t) CPUMGetGuestCR3(PCVMCPU pVCpu)
560{
561 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR3);
562 return pVCpu->cpum.s.Guest.cr3;
563}
564
565
566VMMDECL(uint64_t) CPUMGetGuestCR4(PCVMCPU pVCpu)
567{
568 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR4);
569 return pVCpu->cpum.s.Guest.cr4;
570}
571
572
573VMMDECL(uint64_t) CPUMGetGuestCR8(PCVMCPUCC pVCpu)
574{
575 uint64_t u64;
576 int rc = CPUMGetGuestCRx(pVCpu, DISCREG_CR8, &u64);
577 if (RT_FAILURE(rc))
578 u64 = 0;
579 return u64;
580}
581
582
583VMMDECL(void) CPUMGetGuestGDTR(PCVMCPU pVCpu, PVBOXGDTR pGDTR)
584{
585 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_GDTR);
586 *pGDTR = pVCpu->cpum.s.Guest.gdtr;
587}
588
589
590VMMDECL(uint32_t) CPUMGetGuestEIP(PCVMCPU pVCpu)
591{
592 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RIP);
593 return pVCpu->cpum.s.Guest.eip;
594}
595
596
597VMMDECL(uint64_t) CPUMGetGuestRIP(PCVMCPU pVCpu)
598{
599 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RIP);
600 return pVCpu->cpum.s.Guest.rip;
601}
602
603
604VMMDECL(uint32_t) CPUMGetGuestEAX(PCVMCPU pVCpu)
605{
606 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RAX);
607 return pVCpu->cpum.s.Guest.eax;
608}
609
610
611VMMDECL(uint32_t) CPUMGetGuestEBX(PCVMCPU pVCpu)
612{
613 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RBX);
614 return pVCpu->cpum.s.Guest.ebx;
615}
616
617
618VMMDECL(uint32_t) CPUMGetGuestECX(PCVMCPU pVCpu)
619{
620 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RCX);
621 return pVCpu->cpum.s.Guest.ecx;
622}
623
624
625VMMDECL(uint32_t) CPUMGetGuestEDX(PCVMCPU pVCpu)
626{
627 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RDX);
628 return pVCpu->cpum.s.Guest.edx;
629}
630
631
632VMMDECL(uint32_t) CPUMGetGuestESI(PCVMCPU pVCpu)
633{
634 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RSI);
635 return pVCpu->cpum.s.Guest.esi;
636}
637
638
639VMMDECL(uint32_t) CPUMGetGuestEDI(PCVMCPU pVCpu)
640{
641 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RDI);
642 return pVCpu->cpum.s.Guest.edi;
643}
644
645
646VMMDECL(uint32_t) CPUMGetGuestESP(PCVMCPU pVCpu)
647{
648 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RSP);
649 return pVCpu->cpum.s.Guest.esp;
650}
651
652
653VMMDECL(uint32_t) CPUMGetGuestEBP(PCVMCPU pVCpu)
654{
655 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RBP);
656 return pVCpu->cpum.s.Guest.ebp;
657}
658
659
660VMMDECL(uint32_t) CPUMGetGuestEFlags(PCVMCPU pVCpu)
661{
662 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RFLAGS);
663 return pVCpu->cpum.s.Guest.eflags.u32;
664}
665
666
667VMMDECL(int) CPUMGetGuestCRx(PCVMCPUCC pVCpu, unsigned iReg, uint64_t *pValue)
668{
669 switch (iReg)
670 {
671 case DISCREG_CR0:
672 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0);
673 *pValue = pVCpu->cpum.s.Guest.cr0;
674 break;
675
676 case DISCREG_CR2:
677 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR2);
678 *pValue = pVCpu->cpum.s.Guest.cr2;
679 break;
680
681 case DISCREG_CR3:
682 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR3);
683 *pValue = pVCpu->cpum.s.Guest.cr3;
684 break;
685
686 case DISCREG_CR4:
687 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR4);
688 *pValue = pVCpu->cpum.s.Guest.cr4;
689 break;
690
691 case DISCREG_CR8:
692 {
693 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_APIC_TPR);
694 uint8_t u8Tpr;
695 int rc = APICGetTpr(pVCpu, &u8Tpr, NULL /* pfPending */, NULL /* pu8PendingIrq */);
696 if (RT_FAILURE(rc))
697 {
698 AssertMsg(rc == VERR_PDM_NO_APIC_INSTANCE, ("%Rrc\n", rc));
699 *pValue = 0;
700 return rc;
701 }
702 *pValue = u8Tpr >> 4; /* bits 7-4 contain the task priority that go in cr8, bits 3-0 */
703 break;
704 }
705
706 default:
707 return VERR_INVALID_PARAMETER;
708 }
709 return VINF_SUCCESS;
710}
711
712
713VMMDECL(uint64_t) CPUMGetGuestDR0(PCVMCPU pVCpu)
714{
715 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
716 return pVCpu->cpum.s.Guest.dr[0];
717}
718
719
720VMMDECL(uint64_t) CPUMGetGuestDR1(PCVMCPU pVCpu)
721{
722 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
723 return pVCpu->cpum.s.Guest.dr[1];
724}
725
726
727VMMDECL(uint64_t) CPUMGetGuestDR2(PCVMCPU pVCpu)
728{
729 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
730 return pVCpu->cpum.s.Guest.dr[2];
731}
732
733
734VMMDECL(uint64_t) CPUMGetGuestDR3(PCVMCPU pVCpu)
735{
736 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
737 return pVCpu->cpum.s.Guest.dr[3];
738}
739
740
741VMMDECL(uint64_t) CPUMGetGuestDR6(PCVMCPU pVCpu)
742{
743 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DR6);
744 return pVCpu->cpum.s.Guest.dr[6];
745}
746
747
748VMMDECL(uint64_t) CPUMGetGuestDR7(PCVMCPU pVCpu)
749{
750 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DR7);
751 return pVCpu->cpum.s.Guest.dr[7];
752}
753
754
755VMMDECL(int) CPUMGetGuestDRx(PCVMCPU pVCpu, uint32_t iReg, uint64_t *pValue)
756{
757 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DR_MASK);
758 AssertReturn(iReg <= DISDREG_DR7, VERR_INVALID_PARAMETER);
759 /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
760 if (iReg == 4 || iReg == 5)
761 iReg += 2;
762 *pValue = pVCpu->cpum.s.Guest.dr[iReg];
763 return VINF_SUCCESS;
764}
765
766
767VMMDECL(uint64_t) CPUMGetGuestEFER(PCVMCPU pVCpu)
768{
769 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_EFER);
770 return pVCpu->cpum.s.Guest.msrEFER;
771}
772
773
774/**
775 * Looks up a CPUID leaf in the CPUID leaf array, no subleaf.
776 *
777 * @returns Pointer to the leaf if found, NULL if not.
778 *
779 * @param pVM The cross context VM structure.
780 * @param uLeaf The leaf to get.
781 */
782PCPUMCPUIDLEAF cpumCpuIdGetLeaf(PVM pVM, uint32_t uLeaf)
783{
784 unsigned iEnd = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
785 if (iEnd)
786 {
787 unsigned iStart = 0;
788 PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.CTX_SUFF(paCpuIdLeaves);
789 for (;;)
790 {
791 unsigned i = iStart + (iEnd - iStart) / 2U;
792 if (uLeaf < paLeaves[i].uLeaf)
793 {
794 if (i <= iStart)
795 return NULL;
796 iEnd = i;
797 }
798 else if (uLeaf > paLeaves[i].uLeaf)
799 {
800 i += 1;
801 if (i >= iEnd)
802 return NULL;
803 iStart = i;
804 }
805 else
806 {
807 if (RT_LIKELY(paLeaves[i].fSubLeafMask == 0 && paLeaves[i].uSubLeaf == 0))
808 return &paLeaves[i];
809
810 /* This shouldn't normally happen. But in case the it does due
811 to user configuration overrids or something, just return the
812 first sub-leaf. */
813 AssertMsgFailed(("uLeaf=%#x fSubLeafMask=%#x uSubLeaf=%#x\n",
814 uLeaf, paLeaves[i].fSubLeafMask, paLeaves[i].uSubLeaf));
815 while ( paLeaves[i].uSubLeaf != 0
816 && i > 0
817 && uLeaf == paLeaves[i - 1].uLeaf)
818 i--;
819 return &paLeaves[i];
820 }
821 }
822 }
823
824 return NULL;
825}
826
827
828/**
829 * Looks up a CPUID leaf in the CPUID leaf array.
830 *
831 * @returns Pointer to the leaf if found, NULL if not.
832 *
833 * @param pVM The cross context VM structure.
834 * @param uLeaf The leaf to get.
835 * @param uSubLeaf The subleaf, if applicable. Just pass 0 if it
836 * isn't.
837 * @param pfExactSubLeafHit Whether we've got an exact subleaf hit or not.
838 */
839PCPUMCPUIDLEAF cpumCpuIdGetLeafEx(PVM pVM, uint32_t uLeaf, uint32_t uSubLeaf, bool *pfExactSubLeafHit)
840{
841 unsigned iEnd = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
842 if (iEnd)
843 {
844 unsigned iStart = 0;
845 PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.CTX_SUFF(paCpuIdLeaves);
846 for (;;)
847 {
848 unsigned i = iStart + (iEnd - iStart) / 2U;
849 if (uLeaf < paLeaves[i].uLeaf)
850 {
851 if (i <= iStart)
852 return NULL;
853 iEnd = i;
854 }
855 else if (uLeaf > paLeaves[i].uLeaf)
856 {
857 i += 1;
858 if (i >= iEnd)
859 return NULL;
860 iStart = i;
861 }
862 else
863 {
864 uSubLeaf &= paLeaves[i].fSubLeafMask;
865 if (uSubLeaf == paLeaves[i].uSubLeaf)
866 *pfExactSubLeafHit = true;
867 else
868 {
869 /* Find the right subleaf. We return the last one before
870 uSubLeaf if we don't find an exact match. */
871 if (uSubLeaf < paLeaves[i].uSubLeaf)
872 while ( i > 0
873 && uLeaf == paLeaves[i - 1].uLeaf
874 && uSubLeaf <= paLeaves[i - 1].uSubLeaf)
875 i--;
876 else
877 while ( i + 1 < pVM->cpum.s.GuestInfo.cCpuIdLeaves
878 && uLeaf == paLeaves[i + 1].uLeaf
879 && uSubLeaf >= paLeaves[i + 1].uSubLeaf)
880 i++;
881 *pfExactSubLeafHit = uSubLeaf == paLeaves[i].uSubLeaf;
882 }
883 return &paLeaves[i];
884 }
885 }
886 }
887
888 *pfExactSubLeafHit = false;
889 return NULL;
890}
891
892
893/**
894 * Gets a CPUID leaf.
895 *
896 * @param pVCpu The cross context virtual CPU structure.
897 * @param uLeaf The CPUID leaf to get.
898 * @param uSubLeaf The CPUID sub-leaf to get, if applicable.
899 * @param pEax Where to store the EAX value.
900 * @param pEbx Where to store the EBX value.
901 * @param pEcx Where to store the ECX value.
902 * @param pEdx Where to store the EDX value.
903 */
904VMMDECL(void) CPUMGetGuestCpuId(PVMCPUCC pVCpu, uint32_t uLeaf, uint32_t uSubLeaf,
905 uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx)
906{
907 bool fExactSubLeafHit;
908 PVM pVM = pVCpu->CTX_SUFF(pVM);
909 PCCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafEx(pVM, uLeaf, uSubLeaf, &fExactSubLeafHit);
910 if (pLeaf)
911 {
912 AssertMsg(pLeaf->uLeaf == uLeaf, ("%#x %#x\n", pLeaf->uLeaf, uLeaf));
913 if (fExactSubLeafHit)
914 {
915 *pEax = pLeaf->uEax;
916 *pEbx = pLeaf->uEbx;
917 *pEcx = pLeaf->uEcx;
918 *pEdx = pLeaf->uEdx;
919
920 /*
921 * Deal with CPU specific information.
922 */
923 if (pLeaf->fFlags & ( CPUMCPUIDLEAF_F_CONTAINS_APIC_ID
924 | CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE
925 | CPUMCPUIDLEAF_F_CONTAINS_APIC ))
926 {
927 if (uLeaf == 1)
928 {
929 /* EBX: Bits 31-24: Initial APIC ID. */
930 Assert(pVCpu->idCpu <= 255);
931 AssertMsg((pLeaf->uEbx >> 24) == 0, ("%#x\n", pLeaf->uEbx)); /* raw-mode assumption */
932 *pEbx = (pLeaf->uEbx & UINT32_C(0x00ffffff)) | (pVCpu->idCpu << 24);
933
934 /* EDX: Bit 9: AND with APICBASE.EN. */
935 if (!pVCpu->cpum.s.fCpuIdApicFeatureVisible && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
936 *pEdx &= ~X86_CPUID_FEATURE_EDX_APIC;
937
938 /* ECX: Bit 27: CR4.OSXSAVE mirror. */
939 *pEcx = (pLeaf->uEcx & ~X86_CPUID_FEATURE_ECX_OSXSAVE)
940 | (pVCpu->cpum.s.Guest.cr4 & X86_CR4_OSXSAVE ? X86_CPUID_FEATURE_ECX_OSXSAVE : 0);
941 }
942 else if (uLeaf == 0xb)
943 {
944 /* EDX: Initial extended APIC ID. */
945 AssertMsg(pLeaf->uEdx == 0, ("%#x\n", pLeaf->uEdx)); /* raw-mode assumption */
946 *pEdx = pVCpu->idCpu;
947 Assert(!(pLeaf->fFlags & ~(CPUMCPUIDLEAF_F_CONTAINS_APIC_ID | CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES)));
948 }
949 else if (uLeaf == UINT32_C(0x8000001e))
950 {
951 /* EAX: Initial extended APIC ID. */
952 AssertMsg(pLeaf->uEax == 0, ("%#x\n", pLeaf->uEax)); /* raw-mode assumption */
953 *pEax = pVCpu->idCpu;
954 Assert(!(pLeaf->fFlags & ~CPUMCPUIDLEAF_F_CONTAINS_APIC_ID));
955 }
956 else if (uLeaf == UINT32_C(0x80000001))
957 {
958 /* EDX: Bit 9: AND with APICBASE.EN. */
959 if (!pVCpu->cpum.s.fCpuIdApicFeatureVisible)
960 *pEdx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
961 Assert(!(pLeaf->fFlags & ~CPUMCPUIDLEAF_F_CONTAINS_APIC));
962 }
963 else
964 AssertMsgFailed(("uLeaf=%#x\n", uLeaf));
965 }
966 }
967 /*
968 * Out of range sub-leaves aren't quite as easy and pretty as we emulate
969 * them here, but we do the best we can here...
970 */
971 else
972 {
973 *pEax = *pEbx = *pEcx = *pEdx = 0;
974 if (pLeaf->fFlags & CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES)
975 {
976 *pEcx = uSubLeaf & 0xff;
977 *pEdx = pVCpu->idCpu;
978 }
979 }
980 }
981 else
982 {
983 /*
984 * Different CPUs have different ways of dealing with unknown CPUID leaves.
985 */
986 switch (pVM->cpum.s.GuestInfo.enmUnknownCpuIdMethod)
987 {
988 default:
989 AssertFailed();
990 RT_FALL_THRU();
991 case CPUMUNKNOWNCPUID_DEFAULTS:
992 case CPUMUNKNOWNCPUID_LAST_STD_LEAF: /* ASSUME this is executed */
993 case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: /** @todo Implement CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX */
994 *pEax = pVM->cpum.s.GuestInfo.DefCpuId.uEax;
995 *pEbx = pVM->cpum.s.GuestInfo.DefCpuId.uEbx;
996 *pEcx = pVM->cpum.s.GuestInfo.DefCpuId.uEcx;
997 *pEdx = pVM->cpum.s.GuestInfo.DefCpuId.uEdx;
998 break;
999 case CPUMUNKNOWNCPUID_PASSTHRU:
1000 *pEax = uLeaf;
1001 *pEbx = 0;
1002 *pEcx = uSubLeaf;
1003 *pEdx = 0;
1004 break;
1005 }
1006 }
1007 Log2(("CPUMGetGuestCpuId: uLeaf=%#010x/%#010x %RX32 %RX32 %RX32 %RX32\n", uLeaf, uSubLeaf, *pEax, *pEbx, *pEcx, *pEdx));
1008}
1009
1010
1011/**
1012 * Sets the visibility of the X86_CPUID_FEATURE_EDX_APIC and
1013 * X86_CPUID_AMD_FEATURE_EDX_APIC CPUID bits.
1014 *
1015 * @returns Previous value.
1016 * @param pVCpu The cross context virtual CPU structure to make the
1017 * change on. Usually the calling EMT.
1018 * @param fVisible Whether to make it visible (true) or hide it (false).
1019 *
1020 * @remarks This is "VMMDECL" so that it still links with
1021 * the old APIC code which is in VBoxDD2 and not in
1022 * the VMM module.
1023 */
1024VMMDECL(bool) CPUMSetGuestCpuIdPerCpuApicFeature(PVMCPU pVCpu, bool fVisible)
1025{
1026 bool fOld = pVCpu->cpum.s.fCpuIdApicFeatureVisible;
1027 pVCpu->cpum.s.fCpuIdApicFeatureVisible = fVisible;
1028 return fOld;
1029}
1030
1031
1032/**
1033 * Gets the host CPU vendor.
1034 *
1035 * @returns CPU vendor.
1036 * @param pVM The cross context VM structure.
1037 */
1038VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM)
1039{
1040 return (CPUMCPUVENDOR)pVM->cpum.s.HostFeatures.enmCpuVendor;
1041}
1042
1043
1044/**
1045 * Gets the CPU vendor.
1046 *
1047 * @returns CPU vendor.
1048 * @param pVM The cross context VM structure.
1049 */
1050VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM)
1051{
1052 return (CPUMCPUVENDOR)pVM->cpum.s.GuestFeatures.enmCpuVendor;
1053}
1054
1055
1056VMMDECL(int) CPUMSetGuestDR0(PVMCPUCC pVCpu, uint64_t uDr0)
1057{
1058 pVCpu->cpum.s.Guest.dr[0] = uDr0;
1059 return CPUMRecalcHyperDRx(pVCpu, 0, false);
1060}
1061
1062
1063VMMDECL(int) CPUMSetGuestDR1(PVMCPUCC pVCpu, uint64_t uDr1)
1064{
1065 pVCpu->cpum.s.Guest.dr[1] = uDr1;
1066 return CPUMRecalcHyperDRx(pVCpu, 1, false);
1067}
1068
1069
1070VMMDECL(int) CPUMSetGuestDR2(PVMCPUCC pVCpu, uint64_t uDr2)
1071{
1072 pVCpu->cpum.s.Guest.dr[2] = uDr2;
1073 return CPUMRecalcHyperDRx(pVCpu, 2, false);
1074}
1075
1076
1077VMMDECL(int) CPUMSetGuestDR3(PVMCPUCC pVCpu, uint64_t uDr3)
1078{
1079 pVCpu->cpum.s.Guest.dr[3] = uDr3;
1080 return CPUMRecalcHyperDRx(pVCpu, 3, false);
1081}
1082
1083
1084VMMDECL(int) CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6)
1085{
1086 pVCpu->cpum.s.Guest.dr[6] = uDr6;
1087 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_DR6;
1088 return VINF_SUCCESS; /* No need to recalc. */
1089}
1090
1091
1092VMMDECL(int) CPUMSetGuestDR7(PVMCPUCC pVCpu, uint64_t uDr7)
1093{
1094 pVCpu->cpum.s.Guest.dr[7] = uDr7;
1095 pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_DR7;
1096 return CPUMRecalcHyperDRx(pVCpu, 7, false);
1097}
1098
1099
1100VMMDECL(int) CPUMSetGuestDRx(PVMCPUCC pVCpu, uint32_t iReg, uint64_t Value)
1101{
1102 AssertReturn(iReg <= DISDREG_DR7, VERR_INVALID_PARAMETER);
1103 /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
1104 if (iReg == 4 || iReg == 5)
1105 iReg += 2;
1106 pVCpu->cpum.s.Guest.dr[iReg] = Value;
1107 return CPUMRecalcHyperDRx(pVCpu, iReg, false);
1108}
1109
1110
1111/**
1112 * Recalculates the hypervisor DRx register values based on current guest
1113 * registers and DBGF breakpoints, updating changed registers depending on the
1114 * context.
1115 *
1116 * This is called whenever a guest DRx register is modified (any context) and
1117 * when DBGF sets a hardware breakpoint (ring-3 only, rendezvous).
1118 *
1119 * In raw-mode context this function will reload any (hyper) DRx registers which
1120 * comes out with a different value. It may also have to save the host debug
1121 * registers if that haven't been done already. In this context though, we'll
1122 * be intercepting and emulating all DRx accesses, so the hypervisor DRx values
1123 * are only important when breakpoints are actually enabled.
1124 *
1125 * In ring-0 (HM) context DR0-3 will be relocated by us, while DR7 will be
1126 * reloaded by the HM code if it changes. Further more, we will only use the
1127 * combined register set when the VBox debugger is actually using hardware BPs,
1128 * when it isn't we'll keep the guest DR0-3 + (maybe) DR6 loaded (DR6 doesn't
1129 * concern us here).
1130 *
1131 * In ring-3 we won't be loading anything, so well calculate hypervisor values
1132 * all the time.
1133 *
1134 * @returns VINF_SUCCESS.
1135 * @param pVCpu The cross context virtual CPU structure.
1136 * @param iGstReg The guest debug register number that was modified.
1137 * UINT8_MAX if not guest register.
1138 * @param fForceHyper Used in HM to force hyper registers because of single
1139 * stepping.
1140 */
1141VMMDECL(int) CPUMRecalcHyperDRx(PVMCPUCC pVCpu, uint8_t iGstReg, bool fForceHyper)
1142{
1143 PVM pVM = pVCpu->CTX_SUFF(pVM);
1144#ifndef IN_RING0
1145 RT_NOREF_PV(iGstReg);
1146#endif
1147
1148 /*
1149 * Compare the DR7s first.
1150 *
1151 * We only care about the enabled flags. GD is virtualized when we
1152 * dispatch the #DB, we never enable it. The DBGF DR7 value is will
1153 * always have the LE and GE bits set, so no need to check and disable
1154 * stuff if they're cleared like we have to for the guest DR7.
1155 */
1156 RTGCUINTREG uGstDr7 = CPUMGetGuestDR7(pVCpu);
1157 /** @todo This isn't correct. BPs work without setting LE and GE under AMD-V. They are also documented as unsupported by P6+. */
1158 if (!(uGstDr7 & (X86_DR7_LE | X86_DR7_GE)))
1159 uGstDr7 = 0;
1160 else if (!(uGstDr7 & X86_DR7_LE))
1161 uGstDr7 &= ~X86_DR7_LE_ALL;
1162 else if (!(uGstDr7 & X86_DR7_GE))
1163 uGstDr7 &= ~X86_DR7_GE_ALL;
1164
1165 const RTGCUINTREG uDbgfDr7 = DBGFBpGetDR7(pVM);
1166
1167 /** @todo r=bird: I'm totally confused by fForceHyper! */
1168#ifdef IN_RING0
1169 if (!fForceHyper && (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HYPER))
1170 fForceHyper = true;
1171#endif
1172 if ((!fForceHyper ? uDbgfDr7 : (uGstDr7 | uDbgfDr7)) & X86_DR7_ENABLED_MASK)
1173 {
1174 Assert(!CPUMIsGuestDebugStateActive(pVCpu));
1175
1176 /*
1177 * Ok, something is enabled. Recalc each of the breakpoints, taking
1178 * the VM debugger ones of the guest ones. In raw-mode context we will
1179 * not allow breakpoints with values inside the hypervisor area.
1180 */
1181 RTGCUINTREG uNewDr7 = X86_DR7_GE | X86_DR7_LE | X86_DR7_RA1_MASK;
1182
1183 /* bp 0 */
1184 RTGCUINTREG uNewDr0;
1185 if (uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0))
1186 {
1187 uNewDr7 |= uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
1188 uNewDr0 = DBGFBpGetDR0(pVM);
1189 }
1190 else if (uGstDr7 & (X86_DR7_L0 | X86_DR7_G0))
1191 {
1192 uNewDr0 = CPUMGetGuestDR0(pVCpu);
1193 uNewDr7 |= uGstDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
1194 }
1195 else
1196 uNewDr0 = 0;
1197
1198 /* bp 1 */
1199 RTGCUINTREG uNewDr1;
1200 if (uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1))
1201 {
1202 uNewDr7 |= uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
1203 uNewDr1 = DBGFBpGetDR1(pVM);
1204 }
1205 else if (uGstDr7 & (X86_DR7_L1 | X86_DR7_G1))
1206 {
1207 uNewDr1 = CPUMGetGuestDR1(pVCpu);
1208 uNewDr7 |= uGstDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
1209 }
1210 else
1211 uNewDr1 = 0;
1212
1213 /* bp 2 */
1214 RTGCUINTREG uNewDr2;
1215 if (uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2))
1216 {
1217 uNewDr7 |= uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
1218 uNewDr2 = DBGFBpGetDR2(pVM);
1219 }
1220 else if (uGstDr7 & (X86_DR7_L2 | X86_DR7_G2))
1221 {
1222 uNewDr2 = CPUMGetGuestDR2(pVCpu);
1223 uNewDr7 |= uGstDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
1224 }
1225 else
1226 uNewDr2 = 0;
1227
1228 /* bp 3 */
1229 RTGCUINTREG uNewDr3;
1230 if (uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3))
1231 {
1232 uNewDr7 |= uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
1233 uNewDr3 = DBGFBpGetDR3(pVM);
1234 }
1235 else if (uGstDr7 & (X86_DR7_L3 | X86_DR7_G3))
1236 {
1237 uNewDr3 = CPUMGetGuestDR3(pVCpu);
1238 uNewDr7 |= uGstDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
1239 }
1240 else
1241 uNewDr3 = 0;
1242
1243 /*
1244 * Apply the updates.
1245 */
1246 pVCpu->cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS_HYPER;
1247 if (uNewDr3 != pVCpu->cpum.s.Hyper.dr[3])
1248 CPUMSetHyperDR3(pVCpu, uNewDr3);
1249 if (uNewDr2 != pVCpu->cpum.s.Hyper.dr[2])
1250 CPUMSetHyperDR2(pVCpu, uNewDr2);
1251 if (uNewDr1 != pVCpu->cpum.s.Hyper.dr[1])
1252 CPUMSetHyperDR1(pVCpu, uNewDr1);
1253 if (uNewDr0 != pVCpu->cpum.s.Hyper.dr[0])
1254 CPUMSetHyperDR0(pVCpu, uNewDr0);
1255 if (uNewDr7 != pVCpu->cpum.s.Hyper.dr[7])
1256 CPUMSetHyperDR7(pVCpu, uNewDr7);
1257 }
1258#ifdef IN_RING0
1259 else if (CPUMIsGuestDebugStateActive(pVCpu))
1260 {
1261 /*
1262 * Reload the register that was modified. Normally this won't happen
1263 * as we won't intercept DRx writes when not having the hyper debug
1264 * state loaded, but in case we do for some reason we'll simply deal
1265 * with it.
1266 */
1267 switch (iGstReg)
1268 {
1269 case 0: ASMSetDR0(CPUMGetGuestDR0(pVCpu)); break;
1270 case 1: ASMSetDR1(CPUMGetGuestDR1(pVCpu)); break;
1271 case 2: ASMSetDR2(CPUMGetGuestDR2(pVCpu)); break;
1272 case 3: ASMSetDR3(CPUMGetGuestDR3(pVCpu)); break;
1273 default:
1274 AssertReturn(iGstReg != UINT8_MAX, VERR_INTERNAL_ERROR_3);
1275 }
1276 }
1277#endif
1278 else
1279 {
1280 /*
1281 * No active debug state any more. In raw-mode this means we have to
1282 * make sure DR7 has everything disabled now, if we armed it already.
1283 * In ring-0 we might end up here when just single stepping.
1284 */
1285#ifdef IN_RING0
1286 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HYPER)
1287 {
1288 if (pVCpu->cpum.s.Hyper.dr[0])
1289 ASMSetDR0(0);
1290 if (pVCpu->cpum.s.Hyper.dr[1])
1291 ASMSetDR1(0);
1292 if (pVCpu->cpum.s.Hyper.dr[2])
1293 ASMSetDR2(0);
1294 if (pVCpu->cpum.s.Hyper.dr[3])
1295 ASMSetDR3(0);
1296 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_DEBUG_REGS_HYPER;
1297 }
1298#endif
1299 pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS_HYPER;
1300
1301 /* Clear all the registers. */
1302 pVCpu->cpum.s.Hyper.dr[7] = X86_DR7_RA1_MASK;
1303 pVCpu->cpum.s.Hyper.dr[3] = 0;
1304 pVCpu->cpum.s.Hyper.dr[2] = 0;
1305 pVCpu->cpum.s.Hyper.dr[1] = 0;
1306 pVCpu->cpum.s.Hyper.dr[0] = 0;
1307
1308 }
1309 Log2(("CPUMRecalcHyperDRx: fUseFlags=%#x %RGr %RGr %RGr %RGr %RGr %RGr\n",
1310 pVCpu->cpum.s.fUseFlags, pVCpu->cpum.s.Hyper.dr[0], pVCpu->cpum.s.Hyper.dr[1],
1311 pVCpu->cpum.s.Hyper.dr[2], pVCpu->cpum.s.Hyper.dr[3], pVCpu->cpum.s.Hyper.dr[6],
1312 pVCpu->cpum.s.Hyper.dr[7]));
1313
1314 return VINF_SUCCESS;
1315}
1316
1317
1318/**
1319 * Set the guest XCR0 register.
1320 *
1321 * Will load additional state if the FPU state is already loaded (in ring-0 &
1322 * raw-mode context).
1323 *
1324 * @returns VINF_SUCCESS on success, VERR_CPUM_RAISE_GP_0 on invalid input
1325 * value.
1326 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1327 * @param uNewValue The new value.
1328 * @thread EMT(pVCpu)
1329 */
1330VMM_INT_DECL(int) CPUMSetGuestXcr0(PVMCPUCC pVCpu, uint64_t uNewValue)
1331{
1332 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_XCRx);
1333 if ( (uNewValue & ~pVCpu->CTX_SUFF(pVM)->cpum.s.fXStateGuestMask) == 0
1334 /* The X87 bit cannot be cleared. */
1335 && (uNewValue & XSAVE_C_X87)
1336 /* AVX requires SSE. */
1337 && (uNewValue & (XSAVE_C_SSE | XSAVE_C_YMM)) != XSAVE_C_YMM
1338 /* AVX-512 requires YMM, SSE and all of its three components to be enabled. */
1339 && ( (uNewValue & (XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI)) == 0
1340 || (uNewValue & (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI))
1341 == (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI) )
1342 )
1343 {
1344 pVCpu->cpum.s.Guest.aXcr[0] = uNewValue;
1345
1346 /* If more state components are enabled, we need to take care to load
1347 them if the FPU/SSE state is already loaded. May otherwise leak
1348 host state to the guest. */
1349 uint64_t fNewComponents = ~pVCpu->cpum.s.Guest.fXStateMask & uNewValue;
1350 if (fNewComponents)
1351 {
1352#ifdef IN_RING0
1353 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST)
1354 {
1355 if (pVCpu->cpum.s.Guest.fXStateMask != 0)
1356 /* Adding more components. */
1357 ASMXRstor(pVCpu->cpum.s.Guest.CTX_SUFF(pXState), fNewComponents);
1358 else
1359 {
1360 /* We're switching from FXSAVE/FXRSTOR to XSAVE/XRSTOR. */
1361 pVCpu->cpum.s.Guest.fXStateMask |= XSAVE_C_X87 | XSAVE_C_SSE;
1362 if (uNewValue & ~(XSAVE_C_X87 | XSAVE_C_SSE))
1363 ASMXRstor(pVCpu->cpum.s.Guest.CTX_SUFF(pXState), uNewValue & ~(XSAVE_C_X87 | XSAVE_C_SSE));
1364 }
1365 }
1366#endif
1367 pVCpu->cpum.s.Guest.fXStateMask |= uNewValue;
1368 }
1369 return VINF_SUCCESS;
1370 }
1371 return VERR_CPUM_RAISE_GP_0;
1372}
1373
1374
1375/**
1376 * Tests if the guest has No-Execute Page Protection Enabled (NXE).
1377 *
1378 * @returns true if in real mode, otherwise false.
1379 * @param pVCpu The cross context virtual CPU structure.
1380 */
1381VMMDECL(bool) CPUMIsGuestNXEnabled(PCVMCPU pVCpu)
1382{
1383 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_EFER);
1384 return !!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE);
1385}
1386
1387
1388/**
1389 * Tests if the guest has the Page Size Extension enabled (PSE).
1390 *
1391 * @returns true if in real mode, otherwise false.
1392 * @param pVCpu The cross context virtual CPU structure.
1393 */
1394VMMDECL(bool) CPUMIsGuestPageSizeExtEnabled(PCVMCPU pVCpu)
1395{
1396 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR4);
1397 /* PAE or AMD64 implies support for big pages regardless of CR4.PSE */
1398 return !!(pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PSE | X86_CR4_PAE));
1399}
1400
1401
1402/**
1403 * Tests if the guest has the paging enabled (PG).
1404 *
1405 * @returns true if in real mode, otherwise false.
1406 * @param pVCpu The cross context virtual CPU structure.
1407 */
1408VMMDECL(bool) CPUMIsGuestPagingEnabled(PCVMCPU pVCpu)
1409{
1410 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0);
1411 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG);
1412}
1413
1414
1415/**
1416 * Tests if the guest has the paging enabled (PG).
1417 *
1418 * @returns true if in real mode, otherwise false.
1419 * @param pVCpu The cross context virtual CPU structure.
1420 */
1421VMMDECL(bool) CPUMIsGuestR0WriteProtEnabled(PCVMCPU pVCpu)
1422{
1423 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0);
1424 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_WP);
1425}
1426
1427
1428/**
1429 * Tests if the guest is running in real mode or not.
1430 *
1431 * @returns true if in real mode, otherwise false.
1432 * @param pVCpu The cross context virtual CPU structure.
1433 */
1434VMMDECL(bool) CPUMIsGuestInRealMode(PCVMCPU pVCpu)
1435{
1436 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0);
1437 return !(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
1438}
1439
1440
1441/**
1442 * Tests if the guest is running in real or virtual 8086 mode.
1443 *
1444 * @returns @c true if it is, @c false if not.
1445 * @param pVCpu The cross context virtual CPU structure.
1446 */
1447VMMDECL(bool) CPUMIsGuestInRealOrV86Mode(PCVMCPU pVCpu)
1448{
1449 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_RFLAGS);
1450 return !(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE)
1451 || pVCpu->cpum.s.Guest.eflags.Bits.u1VM; /** @todo verify that this cannot be set in long mode. */
1452}
1453
1454
1455/**
1456 * Tests if the guest is running in protected or not.
1457 *
1458 * @returns true if in protected mode, otherwise false.
1459 * @param pVCpu The cross context virtual CPU structure.
1460 */
1461VMMDECL(bool) CPUMIsGuestInProtectedMode(PCVMCPU pVCpu)
1462{
1463 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0);
1464 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
1465}
1466
1467
1468/**
1469 * Tests if the guest is running in paged protected or not.
1470 *
1471 * @returns true if in paged protected mode, otherwise false.
1472 * @param pVCpu The cross context virtual CPU structure.
1473 */
1474VMMDECL(bool) CPUMIsGuestInPagedProtectedMode(PCVMCPU pVCpu)
1475{
1476 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0);
1477 return (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
1478}
1479
1480
1481/**
1482 * Tests if the guest is running in long mode or not.
1483 *
1484 * @returns true if in long mode, otherwise false.
1485 * @param pVCpu The cross context virtual CPU structure.
1486 */
1487VMMDECL(bool) CPUMIsGuestInLongMode(PCVMCPU pVCpu)
1488{
1489 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_EFER);
1490 return (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
1491}
1492
1493
1494/**
1495 * Tests if the guest is running in PAE mode or not.
1496 *
1497 * @returns true if in PAE mode, otherwise false.
1498 * @param pVCpu The cross context virtual CPU structure.
1499 */
1500VMMDECL(bool) CPUMIsGuestInPAEMode(PCVMCPU pVCpu)
1501{
1502 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR4 | CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_EFER);
1503 /* Intel mentions EFER.LMA and EFER.LME in different parts of their spec. We shall use EFER.LMA rather
1504 than EFER.LME as it reflects if the CPU has entered paging with EFER.LME set. */
1505 return (pVCpu->cpum.s.Guest.cr4 & X86_CR4_PAE)
1506 && (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG)
1507 && !(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA);
1508}
1509
1510
1511/**
1512 * Tests if the guest is running in 64 bits mode or not.
1513 *
1514 * @returns true if in 64 bits protected mode, otherwise false.
1515 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1516 */
1517VMMDECL(bool) CPUMIsGuestIn64BitCode(PVMCPU pVCpu)
1518{
1519 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_EFER);
1520 if (!CPUMIsGuestInLongMode(pVCpu))
1521 return false;
1522 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
1523 return pVCpu->cpum.s.Guest.cs.Attr.n.u1Long;
1524}
1525
1526
1527/**
1528 * Helper for CPUMIsGuestIn64BitCodeEx that handles lazy resolving of hidden CS
1529 * registers.
1530 *
1531 * @returns true if in 64 bits protected mode, otherwise false.
1532 * @param pCtx Pointer to the current guest CPU context.
1533 */
1534VMM_INT_DECL(bool) CPUMIsGuestIn64BitCodeSlow(PCPUMCTX pCtx)
1535{
1536 return CPUMIsGuestIn64BitCode(CPUM_GUEST_CTX_TO_VMCPU(pCtx));
1537}
1538
1539
1540/**
1541 * Sets the specified changed flags (CPUM_CHANGED_*).
1542 *
1543 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1544 * @param fChangedAdd The changed flags to add.
1545 */
1546VMMDECL(void) CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedAdd)
1547{
1548 pVCpu->cpum.s.fChanged |= fChangedAdd;
1549}
1550
1551
1552/**
1553 * Checks if the CPU supports the XSAVE and XRSTOR instruction.
1554 *
1555 * @returns true if supported.
1556 * @returns false if not supported.
1557 * @param pVM The cross context VM structure.
1558 */
1559VMMDECL(bool) CPUMSupportsXSave(PVM pVM)
1560{
1561 return pVM->cpum.s.HostFeatures.fXSaveRstor != 0;
1562}
1563
1564
1565/**
1566 * Checks if the host OS uses the SYSENTER / SYSEXIT instructions.
1567 * @returns true if used.
1568 * @returns false if not used.
1569 * @param pVM The cross context VM structure.
1570 */
1571VMMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM)
1572{
1573 return RT_BOOL(pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSENTER);
1574}
1575
1576
1577/**
1578 * Checks if the host OS uses the SYSCALL / SYSRET instructions.
1579 * @returns true if used.
1580 * @returns false if not used.
1581 * @param pVM The cross context VM structure.
1582 */
1583VMMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM)
1584{
1585 return RT_BOOL(pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSCALL);
1586}
1587
1588
1589/**
1590 * Checks if we activated the FPU/XMM state of the guest OS.
1591 *
1592 * This differs from CPUMIsGuestFPUStateLoaded() in that it refers to the next
1593 * time we'll be executing guest code, so it may return true for 64-on-32 when
1594 * we still haven't actually loaded the FPU status, just scheduled it to be
1595 * loaded the next time we go thru the world switcher (CPUM_SYNC_FPU_STATE).
1596 *
1597 * @returns true / false.
1598 * @param pVCpu The cross context virtual CPU structure.
1599 */
1600VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCpu)
1601{
1602 return RT_BOOL(pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU_GUEST | CPUM_SYNC_FPU_STATE));
1603}
1604
1605
1606/**
1607 * Checks if we've really loaded the FPU/XMM state of the guest OS.
1608 *
1609 * @returns true / false.
1610 * @param pVCpu The cross context virtual CPU structure.
1611 */
1612VMMDECL(bool) CPUMIsGuestFPUStateLoaded(PVMCPU pVCpu)
1613{
1614 return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST);
1615}
1616
1617
1618/**
1619 * Checks if we saved the FPU/XMM state of the host OS.
1620 *
1621 * @returns true / false.
1622 * @param pVCpu The cross context virtual CPU structure.
1623 */
1624VMMDECL(bool) CPUMIsHostFPUStateSaved(PVMCPU pVCpu)
1625{
1626 return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_HOST);
1627}
1628
1629
1630/**
1631 * Checks if the guest debug state is active.
1632 *
1633 * @returns boolean
1634 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1635 */
1636VMMDECL(bool) CPUMIsGuestDebugStateActive(PVMCPU pVCpu)
1637{
1638 return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST);
1639}
1640
1641
1642/**
1643 * Checks if the guest debug state is to be made active during the world-switch
1644 * (currently only used for the 32->64 switcher case).
1645 *
1646 * @returns boolean
1647 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1648 */
1649VMMDECL(bool) CPUMIsGuestDebugStateActivePending(PVMCPU pVCpu)
1650{
1651 return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_DEBUG_REGS_GUEST);
1652}
1653
1654
1655/**
1656 * Checks if the hyper debug state is active.
1657 *
1658 * @returns boolean
1659 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1660 */
1661VMMDECL(bool) CPUMIsHyperDebugStateActive(PVMCPU pVCpu)
1662{
1663 return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HYPER);
1664}
1665
1666
1667/**
1668 * Checks if the hyper debug state is to be made active during the world-switch
1669 * (currently only used for the 32->64 switcher case).
1670 *
1671 * @returns boolean
1672 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1673 */
1674VMMDECL(bool) CPUMIsHyperDebugStateActivePending(PVMCPU pVCpu)
1675{
1676 return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_DEBUG_REGS_HYPER);
1677}
1678
1679
1680/**
1681 * Mark the guest's debug state as inactive.
1682 *
1683 * @returns boolean
1684 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1685 * @todo This API doesn't make sense any more.
1686 */
1687VMMDECL(void) CPUMDeactivateGuestDebugState(PVMCPU pVCpu)
1688{
1689 Assert(!(pVCpu->cpum.s.fUseFlags & (CPUM_USED_DEBUG_REGS_GUEST | CPUM_USED_DEBUG_REGS_HYPER | CPUM_USED_DEBUG_REGS_HOST)));
1690 NOREF(pVCpu);
1691}
1692
1693
1694/**
1695 * Get the current privilege level of the guest.
1696 *
1697 * @returns CPL
1698 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1699 */
1700VMMDECL(uint32_t) CPUMGetGuestCPL(PVMCPU pVCpu)
1701{
1702 /*
1703 * CPL can reliably be found in SS.DPL (hidden regs valid) or SS if not.
1704 *
1705 * Note! We used to check CS.DPL here, assuming it was always equal to
1706 * CPL even if a conforming segment was loaded. But this turned out to
1707 * only apply to older AMD-V. With VT-x we had an ACP2 regression
1708 * during install after a far call to ring 2 with VT-x. Then on newer
1709 * AMD-V CPUs we have to move the VMCB.guest.u8CPL into cs.Attr.n.u2Dpl
1710 * as well as ss.Attr.n.u2Dpl to make this (and other) code work right.
1711 *
1712 * So, forget CS.DPL, always use SS.DPL.
1713 *
1714 * Note! The SS RPL is always equal to the CPL, while the CS RPL
1715 * isn't necessarily equal if the segment is conforming.
1716 * See section 4.11.1 in the AMD manual.
1717 *
1718 * Update: Where the heck does it say CS.RPL can differ from CPL other than
1719 * right after real->prot mode switch and when in V8086 mode? That
1720 * section says the RPL specified in a direct transfere (call, jmp,
1721 * ret) is not the one loaded into CS. Besides, if CS.RPL != CPL
1722 * it would be impossible for an exception handle or the iret
1723 * instruction to figure out whether SS:ESP are part of the frame
1724 * or not. VBox or qemu bug must've lead to this misconception.
1725 *
1726 * Update2: On an AMD bulldozer system here, I've no trouble loading a null
1727 * selector into SS with an RPL other than the CPL when CPL != 3 and
1728 * we're in 64-bit mode. The intel dev box doesn't allow this, on
1729 * RPL = CPL. Weird.
1730 */
1731 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_SS);
1732 uint32_t uCpl;
1733 if (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE)
1734 {
1735 if (!pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
1736 {
1737 if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.s.Guest.ss))
1738 uCpl = pVCpu->cpum.s.Guest.ss.Attr.n.u2Dpl;
1739 else
1740 uCpl = (pVCpu->cpum.s.Guest.ss.Sel & X86_SEL_RPL);
1741 }
1742 else
1743 uCpl = 3; /* V86 has CPL=3; REM doesn't set DPL=3 in V8086 mode. See @bugref{5130}. */
1744 }
1745 else
1746 uCpl = 0; /* Real mode is zero; CPL set to 3 for VT-x real-mode emulation. */
1747 return uCpl;
1748}
1749
1750
1751/**
1752 * Gets the current guest CPU mode.
1753 *
1754 * If paging mode is what you need, check out PGMGetGuestMode().
1755 *
1756 * @returns The CPU mode.
1757 * @param pVCpu The cross context virtual CPU structure.
1758 */
1759VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu)
1760{
1761 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_EFER);
1762 CPUMMODE enmMode;
1763 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
1764 enmMode = CPUMMODE_REAL;
1765 else if (!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
1766 enmMode = CPUMMODE_PROTECTED;
1767 else
1768 enmMode = CPUMMODE_LONG;
1769
1770 return enmMode;
1771}
1772
1773
1774/**
1775 * Figure whether the CPU is currently executing 16, 32 or 64 bit code.
1776 *
1777 * @returns 16, 32 or 64.
1778 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1779 */
1780VMMDECL(uint32_t) CPUMGetGuestCodeBits(PVMCPU pVCpu)
1781{
1782 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_EFER | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_CS);
1783
1784 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
1785 return 16;
1786
1787 if (pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
1788 {
1789 Assert(!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA));
1790 return 16;
1791 }
1792
1793 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
1794 if ( pVCpu->cpum.s.Guest.cs.Attr.n.u1Long
1795 && (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
1796 return 64;
1797
1798 if (pVCpu->cpum.s.Guest.cs.Attr.n.u1DefBig)
1799 return 32;
1800
1801 return 16;
1802}
1803
1804
1805VMMDECL(DISCPUMODE) CPUMGetGuestDisMode(PVMCPU pVCpu)
1806{
1807 CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_EFER | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_CS);
1808
1809 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
1810 return DISCPUMODE_16BIT;
1811
1812 if (pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
1813 {
1814 Assert(!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA));
1815 return DISCPUMODE_16BIT;
1816 }
1817
1818 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
1819 if ( pVCpu->cpum.s.Guest.cs.Attr.n.u1Long
1820 && (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
1821 return DISCPUMODE_64BIT;
1822
1823 if (pVCpu->cpum.s.Guest.cs.Attr.n.u1DefBig)
1824 return DISCPUMODE_32BIT;
1825
1826 return DISCPUMODE_16BIT;
1827}
1828
1829
1830/**
1831 * Gets the guest MXCSR_MASK value.
1832 *
1833 * This does not access the x87 state, but the value we determined at VM
1834 * initialization.
1835 *
1836 * @returns MXCSR mask.
1837 * @param pVM The cross context VM structure.
1838 */
1839VMMDECL(uint32_t) CPUMGetGuestMxCsrMask(PVM pVM)
1840{
1841 return pVM->cpum.s.GuestInfo.fMxCsrMask;
1842}
1843
1844
1845/**
1846 * Returns whether the guest has physical interrupts enabled.
1847 *
1848 * @returns @c true if interrupts are enabled, @c false otherwise.
1849 * @param pVCpu The cross context virtual CPU structure.
1850 *
1851 * @remarks Warning! This function does -not- take into account the global-interrupt
1852 * flag (GIF).
1853 */
1854VMM_INT_DECL(bool) CPUMIsGuestPhysIntrEnabled(PVMCPU pVCpu)
1855{
1856 if (!CPUMIsGuestInNestedHwvirtMode(&pVCpu->cpum.s.Guest))
1857 {
1858 uint32_t const fEFlags = pVCpu->cpum.s.Guest.eflags.u;
1859 return RT_BOOL(fEFlags & X86_EFL_IF);
1860 }
1861
1862 if (CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.s.Guest))
1863 return CPUMIsGuestVmxPhysIntrEnabled(pVCpu, &pVCpu->cpum.s.Guest);
1864
1865 Assert(CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.s.Guest));
1866 return CPUMIsGuestSvmPhysIntrEnabled(pVCpu, &pVCpu->cpum.s.Guest);
1867}
1868
1869
1870/**
1871 * Returns whether the nested-guest has virtual interrupts enabled.
1872 *
1873 * @returns @c true if interrupts are enabled, @c false otherwise.
1874 * @param pVCpu The cross context virtual CPU structure.
1875 *
1876 * @remarks Warning! This function does -not- take into account the global-interrupt
1877 * flag (GIF).
1878 */
1879VMM_INT_DECL(bool) CPUMIsGuestVirtIntrEnabled(PVMCPU pVCpu)
1880{
1881 Assert(CPUMIsGuestInNestedHwvirtMode(&pVCpu->cpum.s.Guest));
1882
1883 if (CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.s.Guest))
1884 return CPUMIsGuestVmxVirtIntrEnabled(pVCpu, &pVCpu->cpum.s.Guest);
1885
1886 Assert(CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.s.Guest));
1887 return CPUMIsGuestSvmVirtIntrEnabled(pVCpu, &pVCpu->cpum.s.Guest);
1888}
1889
1890
1891/**
1892 * Calculates the interruptiblity of the guest.
1893 *
1894 * @returns Interruptibility level.
1895 * @param pVCpu The cross context virtual CPU structure.
1896 */
1897VMM_INT_DECL(CPUMINTERRUPTIBILITY) CPUMGetGuestInterruptibility(PVMCPU pVCpu)
1898{
1899#if 1
1900 /* Global-interrupt flag blocks pretty much everything we care about here. */
1901 if (CPUMGetGuestGif(&pVCpu->cpum.s.Guest))
1902 {
1903 /*
1904 * Physical interrupts are primarily blocked using EFLAGS. However, we cannot access
1905 * it directly here. If and how EFLAGS are used depends on the context (nested-guest
1906 * or raw-mode). Hence we use the function below which handles the details.
1907 */
1908 if ( CPUMIsGuestPhysIntrEnabled(pVCpu)
1909 && !VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_BLOCK_NMIS | VMCPU_FF_INHIBIT_INTERRUPTS))
1910 {
1911 if ( !CPUMIsGuestInNestedHwvirtMode(&pVCpu->cpum.s.Guest)
1912 || CPUMIsGuestVirtIntrEnabled(pVCpu))
1913 return CPUMINTERRUPTIBILITY_UNRESTRAINED;
1914
1915 /* Physical interrupts are enabled, but nested-guest virtual interrupts are disabled. */
1916 return CPUMINTERRUPTIBILITY_VIRT_INT_DISABLED;
1917 }
1918
1919 /*
1920 * Blocking the delivery of NMIs during an interrupt shadow is CPU implementation
1921 * specific. Therefore, in practice, we can't deliver an NMI in an interrupt shadow.
1922 * However, there is some uncertainity regarding the converse, i.e. whether
1923 * NMI-blocking until IRET blocks delivery of physical interrupts.
1924 *
1925 * See Intel spec. 25.4.1 "Event Blocking".
1926 */
1927 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1928 return CPUMINTERRUPTIBILITY_NMI_INHIBIT;
1929
1930 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
1931 return CPUMINTERRUPTIBILITY_INT_INHIBITED;
1932
1933 return CPUMINTERRUPTIBILITY_INT_DISABLED;
1934 }
1935 return CPUMINTERRUPTIBILITY_GLOBAL_INHIBIT;
1936#else
1937 if (pVCpu->cpum.s.Guest.rflags.Bits.u1IF)
1938 {
1939 if (pVCpu->cpum.s.Guest.hwvirt.fGif)
1940 {
1941 if (!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_BLOCK_NMIS | VMCPU_FF_INHIBIT_INTERRUPTS))
1942 return CPUMINTERRUPTIBILITY_UNRESTRAINED;
1943
1944 /** @todo does blocking NMIs mean interrupts are also inhibited? */
1945 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
1946 {
1947 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1948 return CPUMINTERRUPTIBILITY_INT_INHIBITED;
1949 return CPUMINTERRUPTIBILITY_NMI_INHIBIT;
1950 }
1951 AssertFailed();
1952 return CPUMINTERRUPTIBILITY_NMI_INHIBIT;
1953 }
1954 return CPUMINTERRUPTIBILITY_GLOBAL_INHIBIT;
1955 }
1956 else
1957 {
1958 if (pVCpu->cpum.s.Guest.hwvirt.fGif)
1959 {
1960 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1961 return CPUMINTERRUPTIBILITY_NMI_INHIBIT;
1962 return CPUMINTERRUPTIBILITY_INT_DISABLED;
1963 }
1964 return CPUMINTERRUPTIBILITY_GLOBAL_INHIBIT;
1965 }
1966#endif
1967}
1968
1969
1970/**
1971 * Gets whether the guest (or nested-guest) is currently blocking delivery of NMIs.
1972 *
1973 * @returns @c true if NMIs are blocked, @c false otherwise.
1974 * @param pVCpu The cross context virtual CPU structure.
1975 */
1976VMM_INT_DECL(bool) CPUMIsGuestNmiBlocking(PCVMCPU pVCpu)
1977{
1978 /*
1979 * Return the state of guest-NMI blocking in any of the following cases:
1980 * - We're not executing a nested-guest.
1981 * - We're executing an SVM nested-guest[1].
1982 * - We're executing a VMX nested-guest without virtual-NMIs enabled.
1983 *
1984 * [1] -- SVM does not support virtual-NMIs or virtual-NMI blocking.
1985 * SVM hypervisors must track NMI blocking themselves by intercepting
1986 * the IRET instruction after injection of an NMI.
1987 */
1988 PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1989 if ( !CPUMIsGuestInNestedHwvirtMode(pCtx)
1990 || CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
1991 || !CPUMIsGuestVmxPinCtlsSet(pVCpu, pCtx, VMX_PIN_CTLS_VIRT_NMI))
1992 return VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
1993
1994 /*
1995 * Return the state of virtual-NMI blocking, if we are executing a
1996 * VMX nested-guest with virtual-NMIs enabled.
1997 */
1998 return CPUMIsGuestVmxVirtNmiBlocking(pVCpu, pCtx);
1999}
2000
2001
2002/**
2003 * Sets blocking delivery of NMIs to the guest.
2004 *
2005 * @param pVCpu The cross context virtual CPU structure.
2006 * @param fBlock Whether NMIs are blocked or not.
2007 */
2008VMM_INT_DECL(void) CPUMSetGuestNmiBlocking(PVMCPU pVCpu, bool fBlock)
2009{
2010 /*
2011 * Set the state of guest-NMI blocking in any of the following cases:
2012 * - We're not executing a nested-guest.
2013 * - We're executing an SVM nested-guest[1].
2014 * - We're executing a VMX nested-guest without virtual-NMIs enabled.
2015 *
2016 * [1] -- SVM does not support virtual-NMIs or virtual-NMI blocking.
2017 * SVM hypervisors must track NMI blocking themselves by intercepting
2018 * the IRET instruction after injection of an NMI.
2019 */
2020 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2021 if ( !CPUMIsGuestInNestedHwvirtMode(pCtx)
2022 || CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
2023 || !CPUMIsGuestVmxPinCtlsSet(pVCpu, pCtx, VMX_PIN_CTLS_VIRT_NMI))
2024 {
2025 if (fBlock)
2026 {
2027 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
2028 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
2029 }
2030 else
2031 {
2032 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
2033 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
2034 }
2035 return;
2036 }
2037
2038 /*
2039 * Set the state of virtual-NMI blocking, if we are executing a
2040 * VMX nested-guest with virtual-NMIs enabled.
2041 */
2042 return CPUMSetGuestVmxVirtNmiBlocking(pVCpu, pCtx, fBlock);
2043}
2044
2045
2046/**
2047 * Checks whether the SVM nested-guest has physical interrupts enabled.
2048 *
2049 * @returns true if interrupts are enabled, false otherwise.
2050 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2051 * @param pCtx The guest-CPU context.
2052 *
2053 * @remarks This does -not- take into account the global-interrupt flag.
2054 */
2055VMM_INT_DECL(bool) CPUMIsGuestSvmPhysIntrEnabled(PCVMCPU pVCpu, PCCPUMCTX pCtx)
2056{
2057 /** @todo Optimization: Avoid this function call and use a pointer to the
2058 * relevant eflags instead (setup during VMRUN instruction emulation). */
2059 Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
2060
2061 X86EFLAGS fEFlags;
2062 if (CPUMIsGuestSvmVirtIntrMasking(pVCpu, pCtx))
2063 fEFlags.u = pCtx->hwvirt.svm.HostState.rflags.u;
2064 else
2065 fEFlags.u = pCtx->eflags.u;
2066
2067 return fEFlags.Bits.u1IF;
2068}
2069
2070
2071/**
2072 * Checks whether the SVM nested-guest is in a state to receive virtual (setup
2073 * for injection by VMRUN instruction) interrupts.
2074 *
2075 * @returns VBox status code.
2076 * @retval true if it's ready, false otherwise.
2077 *
2078 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2079 * @param pCtx The guest-CPU context.
2080 */
2081VMM_INT_DECL(bool) CPUMIsGuestSvmVirtIntrEnabled(PCVMCPU pVCpu, PCCPUMCTX pCtx)
2082{
2083 RT_NOREF(pVCpu);
2084 Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
2085
2086 PCSVMVMCBCTRL pVmcbCtrl = &pCtx->hwvirt.svm.CTX_SUFF(pVmcb)->ctrl;
2087 PCSVMINTCTRL pVmcbIntCtrl = &pVmcbCtrl->IntCtrl;
2088 Assert(!pVmcbIntCtrl->n.u1VGifEnable); /* We don't support passing virtual-GIF feature to the guest yet. */
2089 if ( !pVmcbIntCtrl->n.u1IgnoreTPR
2090 && pVmcbIntCtrl->n.u4VIntrPrio <= pVmcbIntCtrl->n.u8VTPR)
2091 return false;
2092
2093 return RT_BOOL(pCtx->eflags.u & X86_EFL_IF);
2094}
2095
2096
2097/**
2098 * Gets the pending SVM nested-guest interruptvector.
2099 *
2100 * @returns The nested-guest interrupt to inject.
2101 * @param pCtx The guest-CPU context.
2102 */
2103VMM_INT_DECL(uint8_t) CPUMGetGuestSvmVirtIntrVector(PCCPUMCTX pCtx)
2104{
2105 PCSVMVMCBCTRL pVmcbCtrl = &pCtx->hwvirt.svm.CTX_SUFF(pVmcb)->ctrl;
2106 return pVmcbCtrl->IntCtrl.n.u8VIntrVector;
2107}
2108
2109
2110/**
2111 * Restores the host-state from the host-state save area as part of a \#VMEXIT.
2112 *
2113 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2114 * @param pCtx The guest-CPU context.
2115 */
2116VMM_INT_DECL(void) CPUMSvmVmExitRestoreHostState(PVMCPUCC pVCpu, PCPUMCTX pCtx)
2117{
2118 /*
2119 * Reload the guest's "host state".
2120 */
2121 PSVMHOSTSTATE pHostState = &pCtx->hwvirt.svm.HostState;
2122 pCtx->es = pHostState->es;
2123 pCtx->cs = pHostState->cs;
2124 pCtx->ss = pHostState->ss;
2125 pCtx->ds = pHostState->ds;
2126 pCtx->gdtr = pHostState->gdtr;
2127 pCtx->idtr = pHostState->idtr;
2128 CPUMSetGuestEferMsrNoChecks(pVCpu, pCtx->msrEFER, pHostState->uEferMsr);
2129 CPUMSetGuestCR0(pVCpu, pHostState->uCr0 | X86_CR0_PE);
2130 pCtx->cr3 = pHostState->uCr3;
2131 CPUMSetGuestCR4(pVCpu, pHostState->uCr4);
2132 pCtx->rflags = pHostState->rflags;
2133 pCtx->rflags.Bits.u1VM = 0;
2134 pCtx->rip = pHostState->uRip;
2135 pCtx->rsp = pHostState->uRsp;
2136 pCtx->rax = pHostState->uRax;
2137 pCtx->dr[7] &= ~(X86_DR7_ENABLED_MASK | X86_DR7_RAZ_MASK | X86_DR7_MBZ_MASK);
2138 pCtx->dr[7] |= X86_DR7_RA1_MASK;
2139 Assert(pCtx->ss.Attr.n.u2Dpl == 0);
2140
2141 /** @todo if RIP is not canonical or outside the CS segment limit, we need to
2142 * raise \#GP(0) in the guest. */
2143
2144 /** @todo check the loaded host-state for consistency. Figure out what
2145 * exactly this involves? */
2146}
2147
2148
2149/**
2150 * Saves the host-state to the host-state save area as part of a VMRUN.
2151 *
2152 * @param pCtx The guest-CPU context.
2153 * @param cbInstr The length of the VMRUN instruction in bytes.
2154 */
2155VMM_INT_DECL(void) CPUMSvmVmRunSaveHostState(PCPUMCTX pCtx, uint8_t cbInstr)
2156{
2157 PSVMHOSTSTATE pHostState = &pCtx->hwvirt.svm.HostState;
2158 pHostState->es = pCtx->es;
2159 pHostState->cs = pCtx->cs;
2160 pHostState->ss = pCtx->ss;
2161 pHostState->ds = pCtx->ds;
2162 pHostState->gdtr = pCtx->gdtr;
2163 pHostState->idtr = pCtx->idtr;
2164 pHostState->uEferMsr = pCtx->msrEFER;
2165 pHostState->uCr0 = pCtx->cr0;
2166 pHostState->uCr3 = pCtx->cr3;
2167 pHostState->uCr4 = pCtx->cr4;
2168 pHostState->rflags = pCtx->rflags;
2169 pHostState->uRip = pCtx->rip + cbInstr;
2170 pHostState->uRsp = pCtx->rsp;
2171 pHostState->uRax = pCtx->rax;
2172}
2173
2174
2175/**
2176 * Applies the TSC offset of a nested-guest if any and returns the TSC value for the
2177 * nested-guest.
2178 *
2179 * @returns The TSC offset after applying any nested-guest TSC offset.
2180 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2181 * @param uTscValue The guest TSC.
2182 *
2183 * @sa CPUMRemoveNestedGuestTscOffset.
2184 */
2185VMM_INT_DECL(uint64_t) CPUMApplyNestedGuestTscOffset(PCVMCPU pVCpu, uint64_t uTscValue)
2186{
2187 PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2188 if (CPUMIsGuestInVmxNonRootMode(pCtx))
2189 {
2190 PCVMXVVMCS pVmcs = pCtx->hwvirt.vmx.CTX_SUFF(pVmcs);
2191 Assert(pVmcs);
2192 if (CPUMIsGuestVmxProcCtlsSet(pVCpu, pCtx, VMX_PROC_CTLS_USE_TSC_OFFSETTING))
2193 return uTscValue + pVmcs->u64TscOffset.u;
2194 return uTscValue;
2195 }
2196
2197 if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
2198 {
2199 uint64_t offTsc;
2200 if (!HMGetGuestSvmTscOffset(pVCpu, &offTsc))
2201 {
2202 PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
2203 Assert(pVmcb);
2204 offTsc = pVmcb->ctrl.u64TSCOffset;
2205 }
2206 return uTscValue + offTsc;
2207 }
2208 return uTscValue;
2209}
2210
2211
2212/**
2213 * Removes the TSC offset of a nested-guest if any and returns the TSC value for the
2214 * guest.
2215 *
2216 * @returns The TSC offset after removing any nested-guest TSC offset.
2217 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2218 * @param uTscValue The nested-guest TSC.
2219 *
2220 * @sa CPUMApplyNestedGuestTscOffset.
2221 */
2222VMM_INT_DECL(uint64_t) CPUMRemoveNestedGuestTscOffset(PCVMCPU pVCpu, uint64_t uTscValue)
2223{
2224 PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2225 if (CPUMIsGuestInVmxNonRootMode(pCtx))
2226 {
2227 if (CPUMIsGuestVmxProcCtlsSet(pVCpu, pCtx, VMX_PROC_CTLS_USE_TSC_OFFSETTING))
2228 {
2229 PCVMXVVMCS pVmcs = pCtx->hwvirt.vmx.CTX_SUFF(pVmcs);
2230 Assert(pVmcs);
2231 return uTscValue - pVmcs->u64TscOffset.u;
2232 }
2233 return uTscValue;
2234 }
2235
2236 if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
2237 {
2238 uint64_t offTsc;
2239 if (!HMGetGuestSvmTscOffset(pVCpu, &offTsc))
2240 {
2241 PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
2242 Assert(pVmcb);
2243 offTsc = pVmcb->ctrl.u64TSCOffset;
2244 }
2245 return uTscValue - offTsc;
2246 }
2247 return uTscValue;
2248}
2249
2250
2251/**
2252 * Used to dynamically imports state residing in NEM or HM.
2253 *
2254 * This is a worker for the CPUM_IMPORT_EXTRN_RET() macro and various IEM ones.
2255 *
2256 * @returns VBox status code.
2257 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2258 * @param fExtrnImport The fields to import.
2259 * @thread EMT(pVCpu)
2260 */
2261VMM_INT_DECL(int) CPUMImportGuestStateOnDemand(PVMCPUCC pVCpu, uint64_t fExtrnImport)
2262{
2263 VMCPU_ASSERT_EMT(pVCpu);
2264 if (pVCpu->cpum.s.Guest.fExtrn & fExtrnImport)
2265 {
2266 switch (pVCpu->cpum.s.Guest.fExtrn & CPUMCTX_EXTRN_KEEPER_MASK)
2267 {
2268 case CPUMCTX_EXTRN_KEEPER_NEM:
2269 {
2270 int rc = NEMImportStateOnDemand(pVCpu, fExtrnImport);
2271 Assert(rc == VINF_SUCCESS || RT_FAILURE_NP(rc));
2272 return rc;
2273 }
2274
2275 case CPUMCTX_EXTRN_KEEPER_HM:
2276 {
2277#ifdef IN_RING0
2278 int rc = HMR0ImportStateOnDemand(pVCpu, fExtrnImport);
2279 Assert(rc == VINF_SUCCESS || RT_FAILURE_NP(rc));
2280 return rc;
2281#else
2282 AssertLogRelMsgFailed(("TODO Fetch HM state: %#RX64 vs %#RX64\n", pVCpu->cpum.s.Guest.fExtrn, fExtrnImport));
2283 return VINF_SUCCESS;
2284#endif
2285 }
2286 default:
2287 AssertLogRelMsgFailedReturn(("%#RX64 vs %#RX64\n", pVCpu->cpum.s.Guest.fExtrn, fExtrnImport), VERR_CPUM_IPE_2);
2288 }
2289 }
2290 return VINF_SUCCESS;
2291}
2292
2293
2294/**
2295 * Gets valid CR4 bits for the guest.
2296 *
2297 * @returns Valid CR4 bits.
2298 * @param pVM The cross context VM structure.
2299 */
2300VMM_INT_DECL(uint64_t) CPUMGetGuestCR4ValidMask(PVM pVM)
2301{
2302 PCCPUMFEATURES pGuestFeatures = &pVM->cpum.s.GuestFeatures;
2303 uint64_t fMask = X86_CR4_VME | X86_CR4_PVI
2304 | X86_CR4_TSD | X86_CR4_DE
2305 | X86_CR4_PSE | X86_CR4_PAE
2306 | X86_CR4_MCE | X86_CR4_PGE
2307 | X86_CR4_PCE
2308 | X86_CR4_OSXMMEEXCPT; /** @todo r=ramshankar: Introduced in Pentium III along with SSE. Check fSse here? */
2309 if (pGuestFeatures->fFxSaveRstor)
2310 fMask |= X86_CR4_OSFXSR;
2311 if (pGuestFeatures->fVmx)
2312 fMask |= X86_CR4_VMXE;
2313 if (pGuestFeatures->fXSaveRstor)
2314 fMask |= X86_CR4_OSXSAVE;
2315 if (pGuestFeatures->fPcid)
2316 fMask |= X86_CR4_PCIDE;
2317 if (pGuestFeatures->fFsGsBase)
2318 fMask |= X86_CR4_FSGSBASE;
2319 return fMask;
2320}
2321
2322
2323/**
2324 * Gets the read and write permission bits for an MSR in an MSR bitmap.
2325 *
2326 * @returns VMXMSRPM_XXX - the MSR permission.
2327 * @param pvMsrBitmap Pointer to the MSR bitmap.
2328 * @param idMsr The MSR to get permissions for.
2329 *
2330 * @sa hmR0VmxSetMsrPermission.
2331 */
2332VMM_INT_DECL(uint32_t) CPUMGetVmxMsrPermission(void const *pvMsrBitmap, uint32_t idMsr)
2333{
2334 AssertPtrReturn(pvMsrBitmap, VMXMSRPM_EXIT_RD | VMXMSRPM_EXIT_WR);
2335
2336 uint8_t const * const pbMsrBitmap = (uint8_t const * const)pvMsrBitmap;
2337
2338 /*
2339 * MSR Layout:
2340 * Byte index MSR range Interpreted as
2341 * 0x000 - 0x3ff 0x00000000 - 0x00001fff Low MSR read bits.
2342 * 0x400 - 0x7ff 0xc0000000 - 0xc0001fff High MSR read bits.
2343 * 0x800 - 0xbff 0x00000000 - 0x00001fff Low MSR write bits.
2344 * 0xc00 - 0xfff 0xc0000000 - 0xc0001fff High MSR write bits.
2345 *
2346 * A bit corresponding to an MSR within the above range causes a VM-exit
2347 * if the bit is 1 on executions of RDMSR/WRMSR. If an MSR falls out of
2348 * the MSR range, it always cause a VM-exit.
2349 *
2350 * See Intel spec. 24.6.9 "MSR-Bitmap Address".
2351 */
2352 uint32_t const offBitmapRead = 0;
2353 uint32_t const offBitmapWrite = 0x800;
2354 uint32_t offMsr;
2355 uint32_t iBit;
2356 if (idMsr <= UINT32_C(0x00001fff))
2357 {
2358 offMsr = 0;
2359 iBit = idMsr;
2360 }
2361 else if (idMsr - UINT32_C(0xc0000000) <= UINT32_C(0x00001fff))
2362 {
2363 offMsr = 0x400;
2364 iBit = idMsr - UINT32_C(0xc0000000);
2365 }
2366 else
2367 {
2368 LogFunc(("Warning! Out of range MSR %#RX32\n", idMsr));
2369 return VMXMSRPM_EXIT_RD | VMXMSRPM_EXIT_WR;
2370 }
2371
2372 /*
2373 * Get the MSR read permissions.
2374 */
2375 uint32_t fRet;
2376 uint32_t const offMsrRead = offBitmapRead + offMsr;
2377 Assert(offMsrRead + (iBit >> 3) < offBitmapWrite);
2378 if (ASMBitTest(pbMsrBitmap + offMsrRead, iBit))
2379 fRet = VMXMSRPM_EXIT_RD;
2380 else
2381 fRet = VMXMSRPM_ALLOW_RD;
2382
2383 /*
2384 * Get the MSR write permissions.
2385 */
2386 uint32_t const offMsrWrite = offBitmapWrite + offMsr;
2387 Assert(offMsrWrite + (iBit >> 3) < X86_PAGE_4K_SIZE);
2388 if (ASMBitTest(pbMsrBitmap + offMsrWrite, iBit))
2389 fRet |= VMXMSRPM_EXIT_WR;
2390 else
2391 fRet |= VMXMSRPM_ALLOW_WR;
2392
2393 Assert(VMXMSRPM_IS_FLAG_VALID(fRet));
2394 return fRet;
2395}
2396
2397
2398/**
2399 * Gets the permission bits for the specified I/O port from the given I/O bitmaps.
2400 *
2401 * @returns @c true if the I/O port access must cause a VM-exit, @c false otherwise.
2402 * @param pvIoBitmapA Pointer to I/O bitmap A.
2403 * @param pvIoBitmapB Pointer to I/O bitmap B.
2404 * @param uPort The I/O port being accessed.
2405 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
2406 */
2407VMM_INT_DECL(bool) CPUMGetVmxIoBitmapPermission(void const *pvIoBitmapA, void const *pvIoBitmapB, uint16_t uPort,
2408 uint8_t cbAccess)
2409{
2410 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
2411
2412 /*
2413 * If the I/O port access wraps around the 16-bit port I/O space,
2414 * we must cause a VM-exit.
2415 *
2416 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2417 */
2418 /** @todo r=ramshankar: Reading 1, 2, 4 bytes at ports 0xffff, 0xfffe and 0xfffc
2419 * respectively are valid and do not constitute a wrap around from what I
2420 * understand. Verify this later. */
2421 uint32_t const uPortLast = uPort + cbAccess;
2422 if (uPortLast > 0x10000)
2423 return true;
2424
2425 /* Read the appropriate bit from the corresponding IO bitmap. */
2426 void const *pvIoBitmap = uPort < 0x8000 ? pvIoBitmapA : pvIoBitmapB;
2427 return ASMBitTest(pvIoBitmap, uPort);
2428}
2429
2430
2431/**
2432 * Returns whether the given VMCS field is valid and supported for the guest.
2433 *
2434 * @param pVM The cross context VM structure.
2435 * @param u64VmcsField The VMCS field.
2436 *
2437 * @remarks This takes into account the CPU features exposed to the guest.
2438 */
2439VMM_INT_DECL(bool) CPUMIsGuestVmxVmcsFieldValid(PVMCC pVM, uint64_t u64VmcsField)
2440{
2441 uint32_t const uFieldEncHi = RT_HI_U32(u64VmcsField);
2442 uint32_t const uFieldEncLo = RT_LO_U32(u64VmcsField);
2443 if (!uFieldEncHi)
2444 { /* likely */ }
2445 else
2446 return false;
2447
2448 PCCPUMFEATURES pFeat = &pVM->cpum.s.GuestFeatures;
2449 switch (uFieldEncLo)
2450 {
2451 /*
2452 * 16-bit fields.
2453 */
2454 /* Control fields. */
2455 case VMX_VMCS16_VPID: return pFeat->fVmxVpid;
2456 case VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR: return pFeat->fVmxPostedInt;
2457 case VMX_VMCS16_EPTP_INDEX: return pFeat->fVmxEptXcptVe;
2458
2459 /* Guest-state fields. */
2460 case VMX_VMCS16_GUEST_ES_SEL:
2461 case VMX_VMCS16_GUEST_CS_SEL:
2462 case VMX_VMCS16_GUEST_SS_SEL:
2463 case VMX_VMCS16_GUEST_DS_SEL:
2464 case VMX_VMCS16_GUEST_FS_SEL:
2465 case VMX_VMCS16_GUEST_GS_SEL:
2466 case VMX_VMCS16_GUEST_LDTR_SEL:
2467 case VMX_VMCS16_GUEST_TR_SEL: return true;
2468 case VMX_VMCS16_GUEST_INTR_STATUS: return pFeat->fVmxVirtIntDelivery;
2469 case VMX_VMCS16_GUEST_PML_INDEX: return pFeat->fVmxPml;
2470
2471 /* Host-state fields. */
2472 case VMX_VMCS16_HOST_ES_SEL:
2473 case VMX_VMCS16_HOST_CS_SEL:
2474 case VMX_VMCS16_HOST_SS_SEL:
2475 case VMX_VMCS16_HOST_DS_SEL:
2476 case VMX_VMCS16_HOST_FS_SEL:
2477 case VMX_VMCS16_HOST_GS_SEL:
2478 case VMX_VMCS16_HOST_TR_SEL: return true;
2479
2480 /*
2481 * 64-bit fields.
2482 */
2483 /* Control fields. */
2484 case VMX_VMCS64_CTRL_IO_BITMAP_A_FULL:
2485 case VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH:
2486 case VMX_VMCS64_CTRL_IO_BITMAP_B_FULL:
2487 case VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH: return pFeat->fVmxUseIoBitmaps;
2488 case VMX_VMCS64_CTRL_MSR_BITMAP_FULL:
2489 case VMX_VMCS64_CTRL_MSR_BITMAP_HIGH: return pFeat->fVmxUseMsrBitmaps;
2490 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL:
2491 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH:
2492 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL:
2493 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH:
2494 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL:
2495 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH:
2496 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL:
2497 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH: return true;
2498 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_FULL:
2499 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_HIGH: return pFeat->fVmxPml;
2500 case VMX_VMCS64_CTRL_TSC_OFFSET_FULL:
2501 case VMX_VMCS64_CTRL_TSC_OFFSET_HIGH: return true;
2502 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL:
2503 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_HIGH: return pFeat->fVmxUseTprShadow;
2504 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL:
2505 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH: return pFeat->fVmxVirtApicAccess;
2506 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL:
2507 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH: return pFeat->fVmxPostedInt;
2508 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL:
2509 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH: return pFeat->fVmxVmFunc;
2510 case VMX_VMCS64_CTRL_EPTP_FULL:
2511 case VMX_VMCS64_CTRL_EPTP_HIGH: return pFeat->fVmxEpt;
2512 case VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL:
2513 case VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH:
2514 case VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL:
2515 case VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH:
2516 case VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL:
2517 case VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH:
2518 case VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL:
2519 case VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH: return pFeat->fVmxVirtIntDelivery;
2520 case VMX_VMCS64_CTRL_EPTP_LIST_FULL:
2521 case VMX_VMCS64_CTRL_EPTP_LIST_HIGH:
2522 {
2523 PCVMCPU pVCpu = pVM->CTX_SUFF(apCpus)[0];
2524 uint64_t const uVmFuncMsr = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64VmFunc;
2525 return RT_BOOL(RT_BF_GET(uVmFuncMsr, VMX_BF_VMFUNC_EPTP_SWITCHING));
2526 }
2527 case VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL:
2528 case VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH:
2529 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL:
2530 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH: return pFeat->fVmxVmcsShadowing;
2531 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_FULL:
2532 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_HIGH: return pFeat->fVmxEptXcptVe;
2533 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL:
2534 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH: return pFeat->fVmxXsavesXrstors;
2535 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_FULL:
2536 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_HIGH: return false;
2537 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL:
2538 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH: return pFeat->fVmxUseTscScaling;
2539
2540 /* Read-only data fields. */
2541 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL:
2542 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_HIGH: return pFeat->fVmxEpt;
2543
2544 /* Guest-state fields. */
2545 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL:
2546 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH:
2547 case VMX_VMCS64_GUEST_DEBUGCTL_FULL:
2548 case VMX_VMCS64_GUEST_DEBUGCTL_HIGH: return true;
2549 case VMX_VMCS64_GUEST_PAT_FULL:
2550 case VMX_VMCS64_GUEST_PAT_HIGH: return pFeat->fVmxEntryLoadPatMsr || pFeat->fVmxExitSavePatMsr;
2551 case VMX_VMCS64_GUEST_EFER_FULL:
2552 case VMX_VMCS64_GUEST_EFER_HIGH: return pFeat->fVmxEntryLoadEferMsr || pFeat->fVmxExitSaveEferMsr;
2553 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL:
2554 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH: return false;
2555 case VMX_VMCS64_GUEST_PDPTE0_FULL:
2556 case VMX_VMCS64_GUEST_PDPTE0_HIGH:
2557 case VMX_VMCS64_GUEST_PDPTE1_FULL:
2558 case VMX_VMCS64_GUEST_PDPTE1_HIGH:
2559 case VMX_VMCS64_GUEST_PDPTE2_FULL:
2560 case VMX_VMCS64_GUEST_PDPTE2_HIGH:
2561 case VMX_VMCS64_GUEST_PDPTE3_FULL:
2562 case VMX_VMCS64_GUEST_PDPTE3_HIGH: return pFeat->fVmxEpt;
2563 case VMX_VMCS64_GUEST_BNDCFGS_FULL:
2564 case VMX_VMCS64_GUEST_BNDCFGS_HIGH: return false;
2565
2566 /* Host-state fields. */
2567 case VMX_VMCS64_HOST_PAT_FULL:
2568 case VMX_VMCS64_HOST_PAT_HIGH: return pFeat->fVmxExitLoadPatMsr;
2569 case VMX_VMCS64_HOST_EFER_FULL:
2570 case VMX_VMCS64_HOST_EFER_HIGH: return pFeat->fVmxExitLoadEferMsr;
2571 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL:
2572 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH: return false;
2573
2574 /*
2575 * 32-bit fields.
2576 */
2577 /* Control fields. */
2578 case VMX_VMCS32_CTRL_PIN_EXEC:
2579 case VMX_VMCS32_CTRL_PROC_EXEC:
2580 case VMX_VMCS32_CTRL_EXCEPTION_BITMAP:
2581 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK:
2582 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH:
2583 case VMX_VMCS32_CTRL_CR3_TARGET_COUNT:
2584 case VMX_VMCS32_CTRL_EXIT:
2585 case VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT:
2586 case VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT:
2587 case VMX_VMCS32_CTRL_ENTRY:
2588 case VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT:
2589 case VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO:
2590 case VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE:
2591 case VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH: return true;
2592 case VMX_VMCS32_CTRL_TPR_THRESHOLD: return pFeat->fVmxUseTprShadow;
2593 case VMX_VMCS32_CTRL_PROC_EXEC2: return pFeat->fVmxSecondaryExecCtls;
2594 case VMX_VMCS32_CTRL_PLE_GAP:
2595 case VMX_VMCS32_CTRL_PLE_WINDOW: return pFeat->fVmxPauseLoopExit;
2596
2597 /* Read-only data fields. */
2598 case VMX_VMCS32_RO_VM_INSTR_ERROR:
2599 case VMX_VMCS32_RO_EXIT_REASON:
2600 case VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO:
2601 case VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE:
2602 case VMX_VMCS32_RO_IDT_VECTORING_INFO:
2603 case VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE:
2604 case VMX_VMCS32_RO_EXIT_INSTR_LENGTH:
2605 case VMX_VMCS32_RO_EXIT_INSTR_INFO: return true;
2606
2607 /* Guest-state fields. */
2608 case VMX_VMCS32_GUEST_ES_LIMIT:
2609 case VMX_VMCS32_GUEST_CS_LIMIT:
2610 case VMX_VMCS32_GUEST_SS_LIMIT:
2611 case VMX_VMCS32_GUEST_DS_LIMIT:
2612 case VMX_VMCS32_GUEST_FS_LIMIT:
2613 case VMX_VMCS32_GUEST_GS_LIMIT:
2614 case VMX_VMCS32_GUEST_LDTR_LIMIT:
2615 case VMX_VMCS32_GUEST_TR_LIMIT:
2616 case VMX_VMCS32_GUEST_GDTR_LIMIT:
2617 case VMX_VMCS32_GUEST_IDTR_LIMIT:
2618 case VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS:
2619 case VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS:
2620 case VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS:
2621 case VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS:
2622 case VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS:
2623 case VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS:
2624 case VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS:
2625 case VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS:
2626 case VMX_VMCS32_GUEST_INT_STATE:
2627 case VMX_VMCS32_GUEST_ACTIVITY_STATE:
2628 case VMX_VMCS32_GUEST_SMBASE:
2629 case VMX_VMCS32_GUEST_SYSENTER_CS: return true;
2630 case VMX_VMCS32_PREEMPT_TIMER_VALUE: return pFeat->fVmxPreemptTimer;
2631
2632 /* Host-state fields. */
2633 case VMX_VMCS32_HOST_SYSENTER_CS: return true;
2634
2635 /*
2636 * Natural-width fields.
2637 */
2638 /* Control fields. */
2639 case VMX_VMCS_CTRL_CR0_MASK:
2640 case VMX_VMCS_CTRL_CR4_MASK:
2641 case VMX_VMCS_CTRL_CR0_READ_SHADOW:
2642 case VMX_VMCS_CTRL_CR4_READ_SHADOW:
2643 case VMX_VMCS_CTRL_CR3_TARGET_VAL0:
2644 case VMX_VMCS_CTRL_CR3_TARGET_VAL1:
2645 case VMX_VMCS_CTRL_CR3_TARGET_VAL2:
2646 case VMX_VMCS_CTRL_CR3_TARGET_VAL3: return true;
2647
2648 /* Read-only data fields. */
2649 case VMX_VMCS_RO_EXIT_QUALIFICATION:
2650 case VMX_VMCS_RO_IO_RCX:
2651 case VMX_VMCS_RO_IO_RSI:
2652 case VMX_VMCS_RO_IO_RDI:
2653 case VMX_VMCS_RO_IO_RIP:
2654 case VMX_VMCS_RO_GUEST_LINEAR_ADDR: return true;
2655
2656 /* Guest-state fields. */
2657 case VMX_VMCS_GUEST_CR0:
2658 case VMX_VMCS_GUEST_CR3:
2659 case VMX_VMCS_GUEST_CR4:
2660 case VMX_VMCS_GUEST_ES_BASE:
2661 case VMX_VMCS_GUEST_CS_BASE:
2662 case VMX_VMCS_GUEST_SS_BASE:
2663 case VMX_VMCS_GUEST_DS_BASE:
2664 case VMX_VMCS_GUEST_FS_BASE:
2665 case VMX_VMCS_GUEST_GS_BASE:
2666 case VMX_VMCS_GUEST_LDTR_BASE:
2667 case VMX_VMCS_GUEST_TR_BASE:
2668 case VMX_VMCS_GUEST_GDTR_BASE:
2669 case VMX_VMCS_GUEST_IDTR_BASE:
2670 case VMX_VMCS_GUEST_DR7:
2671 case VMX_VMCS_GUEST_RSP:
2672 case VMX_VMCS_GUEST_RIP:
2673 case VMX_VMCS_GUEST_RFLAGS:
2674 case VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS:
2675 case VMX_VMCS_GUEST_SYSENTER_ESP:
2676 case VMX_VMCS_GUEST_SYSENTER_EIP: return true;
2677
2678 /* Host-state fields. */
2679 case VMX_VMCS_HOST_CR0:
2680 case VMX_VMCS_HOST_CR3:
2681 case VMX_VMCS_HOST_CR4:
2682 case VMX_VMCS_HOST_FS_BASE:
2683 case VMX_VMCS_HOST_GS_BASE:
2684 case VMX_VMCS_HOST_TR_BASE:
2685 case VMX_VMCS_HOST_GDTR_BASE:
2686 case VMX_VMCS_HOST_IDTR_BASE:
2687 case VMX_VMCS_HOST_SYSENTER_ESP:
2688 case VMX_VMCS_HOST_SYSENTER_EIP:
2689 case VMX_VMCS_HOST_RSP:
2690 case VMX_VMCS_HOST_RIP: return true;
2691 }
2692
2693 return false;
2694}
2695
2696
2697/**
2698 * Checks whether the given I/O access should cause a nested-guest VM-exit.
2699 *
2700 * @returns @c true if it causes a VM-exit, @c false otherwise.
2701 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2702 * @param u16Port The I/O port being accessed.
2703 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
2704 */
2705VMM_INT_DECL(bool) CPUMIsGuestVmxIoInterceptSet(PCVMCPU pVCpu, uint16_t u16Port, uint8_t cbAccess)
2706{
2707 PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2708 if (CPUMIsGuestVmxProcCtlsSet(pVCpu, pCtx, VMX_PROC_CTLS_UNCOND_IO_EXIT))
2709 return true;
2710
2711 if (CPUMIsGuestVmxProcCtlsSet(pVCpu, pCtx, VMX_PROC_CTLS_USE_IO_BITMAPS))
2712 {
2713 uint8_t const *pbIoBitmapA = (uint8_t const *)pCtx->hwvirt.vmx.CTX_SUFF(pvIoBitmap);
2714 uint8_t const *pbIoBitmapB = (uint8_t const *)pCtx->hwvirt.vmx.CTX_SUFF(pvIoBitmap) + VMX_V_IO_BITMAP_A_SIZE;
2715 Assert(pbIoBitmapA);
2716 Assert(pbIoBitmapB);
2717 return CPUMGetVmxIoBitmapPermission(pbIoBitmapA, pbIoBitmapB, u16Port, cbAccess);
2718 }
2719
2720 return false;
2721}
2722
2723
2724/**
2725 * Checks whether the Mov-to-CR3 instruction causes a nested-guest VM-exit.
2726 *
2727 * @returns @c true if it causes a VM-exit, @c false otherwise.
2728 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2729 * @param uNewCr3 The CR3 value being written.
2730 */
2731VMM_INT_DECL(bool) CPUMIsGuestVmxMovToCr3InterceptSet(PVMCPU pVCpu, uint64_t uNewCr3)
2732{
2733 /*
2734 * If the CR3-load exiting control is set and the new CR3 value does not
2735 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
2736 *
2737 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2738 */
2739 PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2740 PCVMXVVMCS pVmcs = pCtx->hwvirt.vmx.CTX_SUFF(pVmcs);
2741 if (CPUMIsGuestVmxProcCtlsSet(pVCpu, pCtx, VMX_PROC_CTLS_CR3_LOAD_EXIT))
2742 {
2743 uint32_t const uCr3TargetCount = pVmcs->u32Cr3TargetCount;
2744 Assert(uCr3TargetCount <= VMX_V_CR3_TARGET_COUNT);
2745
2746 /* If the CR3-target count is 0, cause a VM-exit. */
2747 if (uCr3TargetCount == 0)
2748 return true;
2749
2750 /* If the CR3 being written doesn't match any of the target values, cause a VM-exit. */
2751 AssertCompile(VMX_V_CR3_TARGET_COUNT == 4);
2752 if ( uNewCr3 != pVmcs->u64Cr3Target0.u
2753 && uNewCr3 != pVmcs->u64Cr3Target1.u
2754 && uNewCr3 != pVmcs->u64Cr3Target2.u
2755 && uNewCr3 != pVmcs->u64Cr3Target3.u)
2756 return true;
2757 }
2758 return false;
2759}
2760
2761
2762/**
2763 * Checks whether a VMREAD or VMWRITE instruction for the given VMCS field causes a
2764 * VM-exit or not.
2765 *
2766 * @returns @c true if the VMREAD/VMWRITE is intercepted, @c false otherwise.
2767 * @param pVCpu The cross context virtual CPU structure.
2768 * @param uExitReason The VM-exit reason (VMX_EXIT_VMREAD or
2769 * VMX_EXIT_VMREAD).
2770 * @param u64VmcsField The VMCS field.
2771 */
2772VMM_INT_DECL(bool) CPUMIsGuestVmxVmreadVmwriteInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint64_t u64VmcsField)
2773{
2774 Assert(CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.s.Guest));
2775 Assert( uExitReason == VMX_EXIT_VMREAD
2776 || uExitReason == VMX_EXIT_VMWRITE);
2777
2778 /*
2779 * Without VMCS shadowing, all VMREAD and VMWRITE instructions are intercepted.
2780 */
2781 if (!CPUMIsGuestVmxProcCtls2Set(pVCpu, &pVCpu->cpum.s.Guest, VMX_PROC_CTLS2_VMCS_SHADOWING))
2782 return true;
2783
2784 /*
2785 * If any reserved bit in the 64-bit VMCS field encoding is set, the VMREAD/VMWRITE
2786 * is intercepted. This excludes any reserved bits in the valid parts of the field
2787 * encoding (i.e. bit 12).
2788 */
2789 if (u64VmcsField & VMX_VMCSFIELD_RSVD_MASK)
2790 return true;
2791
2792 /*
2793 * Finally, consult the VMREAD/VMWRITE bitmap whether to intercept the instruction or not.
2794 */
2795 uint32_t const u32VmcsField = RT_LO_U32(u64VmcsField);
2796 uint8_t const *pbBitmap = uExitReason == VMX_EXIT_VMREAD
2797 ? (uint8_t const *)pVCpu->cpum.s.Guest.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap)
2798 : (uint8_t const *)pVCpu->cpum.s.Guest.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap);
2799 Assert(pbBitmap);
2800 Assert(u32VmcsField >> 3 < VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
2801 return ASMBitTest(pbBitmap + (u32VmcsField >> 3), u32VmcsField & 7);
2802}
2803
2804
2805
2806/**
2807 * Determines whether the given I/O access should cause a nested-guest \#VMEXIT.
2808 *
2809 * @param pvIoBitmap Pointer to the nested-guest IO bitmap.
2810 * @param u16Port The IO port being accessed.
2811 * @param enmIoType The type of IO access.
2812 * @param cbReg The IO operand size in bytes.
2813 * @param cAddrSizeBits The address size bits (for 16, 32 or 64).
2814 * @param iEffSeg The effective segment number.
2815 * @param fRep Whether this is a repeating IO instruction (REP prefix).
2816 * @param fStrIo Whether this is a string IO instruction.
2817 * @param pIoExitInfo Pointer to the SVMIOIOEXITINFO struct to be filled.
2818 * Optional, can be NULL.
2819 */
2820VMM_INT_DECL(bool) CPUMIsSvmIoInterceptSet(void *pvIoBitmap, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
2821 uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo,
2822 PSVMIOIOEXITINFO pIoExitInfo)
2823{
2824 Assert(cAddrSizeBits == 16 || cAddrSizeBits == 32 || cAddrSizeBits == 64);
2825 Assert(cbReg == 1 || cbReg == 2 || cbReg == 4 || cbReg == 8);
2826
2827 /*
2828 * The IOPM layout:
2829 * Each bit represents one 8-bit port. That makes a total of 0..65535 bits or
2830 * two 4K pages.
2831 *
2832 * For IO instructions that access more than a single byte, the permission bits
2833 * for all bytes are checked; if any bit is set to 1, the IO access is intercepted.
2834 *
2835 * Since it's possible to do a 32-bit IO access at port 65534 (accessing 4 bytes),
2836 * we need 3 extra bits beyond the second 4K page.
2837 */
2838 static const uint16_t s_auSizeMasks[] = { 0, 1, 3, 0, 0xf, 0, 0, 0 };
2839
2840 uint16_t const offIopm = u16Port >> 3;
2841 uint16_t const fSizeMask = s_auSizeMasks[(cAddrSizeBits >> SVM_IOIO_OP_SIZE_SHIFT) & 7];
2842 uint8_t const cShift = u16Port - (offIopm << 3);
2843 uint16_t const fIopmMask = (1 << cShift) | (fSizeMask << cShift);
2844
2845 uint8_t const *pbIopm = (uint8_t *)pvIoBitmap;
2846 Assert(pbIopm);
2847 pbIopm += offIopm;
2848 uint16_t const u16Iopm = *(uint16_t *)pbIopm;
2849 if (u16Iopm & fIopmMask)
2850 {
2851 if (pIoExitInfo)
2852 {
2853 static const uint32_t s_auIoOpSize[] =
2854 { SVM_IOIO_32_BIT_OP, SVM_IOIO_8_BIT_OP, SVM_IOIO_16_BIT_OP, 0, SVM_IOIO_32_BIT_OP, 0, 0, 0 };
2855
2856 static const uint32_t s_auIoAddrSize[] =
2857 { 0, SVM_IOIO_16_BIT_ADDR, SVM_IOIO_32_BIT_ADDR, 0, SVM_IOIO_64_BIT_ADDR, 0, 0, 0 };
2858
2859 pIoExitInfo->u = s_auIoOpSize[cbReg & 7];
2860 pIoExitInfo->u |= s_auIoAddrSize[(cAddrSizeBits >> 4) & 7];
2861 pIoExitInfo->n.u1Str = fStrIo;
2862 pIoExitInfo->n.u1Rep = fRep;
2863 pIoExitInfo->n.u3Seg = iEffSeg & 7;
2864 pIoExitInfo->n.u1Type = enmIoType;
2865 pIoExitInfo->n.u16Port = u16Port;
2866 }
2867 return true;
2868 }
2869
2870 /** @todo remove later (for debugging as VirtualBox always traps all IO
2871 * intercepts). */
2872 AssertMsgFailed(("CPUMSvmIsIOInterceptActive: We expect an IO intercept here!\n"));
2873 return false;
2874}
2875
2876
2877/**
2878 * Gets the MSR permission bitmap byte and bit offset for the specified MSR.
2879 *
2880 * @returns VBox status code.
2881 * @param idMsr The MSR being requested.
2882 * @param pbOffMsrpm Where to store the byte offset in the MSR permission
2883 * bitmap for @a idMsr.
2884 * @param puMsrpmBit Where to store the bit offset starting at the byte
2885 * returned in @a pbOffMsrpm.
2886 */
2887VMM_INT_DECL(int) CPUMGetSvmMsrpmOffsetAndBit(uint32_t idMsr, uint16_t *pbOffMsrpm, uint8_t *puMsrpmBit)
2888{
2889 Assert(pbOffMsrpm);
2890 Assert(puMsrpmBit);
2891
2892 /*
2893 * MSRPM Layout:
2894 * Byte offset MSR range
2895 * 0x000 - 0x7ff 0x00000000 - 0x00001fff
2896 * 0x800 - 0xfff 0xc0000000 - 0xc0001fff
2897 * 0x1000 - 0x17ff 0xc0010000 - 0xc0011fff
2898 * 0x1800 - 0x1fff Reserved
2899 *
2900 * Each MSR is represented by 2 permission bits (read and write).
2901 */
2902 if (idMsr <= 0x00001fff)
2903 {
2904 /* Pentium-compatible MSRs. */
2905 uint32_t const bitoffMsr = idMsr << 1;
2906 *pbOffMsrpm = bitoffMsr >> 3;
2907 *puMsrpmBit = bitoffMsr & 7;
2908 return VINF_SUCCESS;
2909 }
2910
2911 if ( idMsr >= 0xc0000000
2912 && idMsr <= 0xc0001fff)
2913 {
2914 /* AMD Sixth Generation x86 Processor MSRs. */
2915 uint32_t const bitoffMsr = (idMsr - 0xc0000000) << 1;
2916 *pbOffMsrpm = 0x800 + (bitoffMsr >> 3);
2917 *puMsrpmBit = bitoffMsr & 7;
2918 return VINF_SUCCESS;
2919 }
2920
2921 if ( idMsr >= 0xc0010000
2922 && idMsr <= 0xc0011fff)
2923 {
2924 /* AMD Seventh and Eighth Generation Processor MSRs. */
2925 uint32_t const bitoffMsr = (idMsr - 0xc0010000) << 1;
2926 *pbOffMsrpm = 0x1000 + (bitoffMsr >> 3);
2927 *puMsrpmBit = bitoffMsr & 7;
2928 return VINF_SUCCESS;
2929 }
2930
2931 *pbOffMsrpm = 0;
2932 *puMsrpmBit = 0;
2933 return VERR_OUT_OF_RANGE;
2934}
2935
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