DBGFAll.cpp

Last change on this file was 108702, checked in by vboxsync, 4 weeks ago
VMM/IEM: More ARM target work. jiraref:VBP-1598
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1	/* $Id: DBGFAll.cpp 108702 2025-03-21 23:27:14Z vboxsync $ */
2	/** @file
3	* DBGF - Debugger Facility, All Context Code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_DBGF
33	#define VMCPU_INCL_CPUM_GST_CTX
34	#include <VBox/vmm/dbgf.h>
35	#include "DBGFInternal.h"
36	#include <VBox/vmm/cpum.h>
37	#include <VBox/vmm/vmcc.h>
38	#include <VBox/err.h>
39	#include <iprt/assert.h>
40	#include <iprt/asm.h>
41	#include <iprt/stdarg.h>
42
43
44	/*
45	* Check the read-only VM members.
46	*/
47	AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.bmSoftIntBreakpoints, VM, dbgf.ro.bmSoftIntBreakpoints);
48	AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.bmHardIntBreakpoints, VM, dbgf.ro.bmHardIntBreakpoints);
49	AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.bmSelectedEvents, VM, dbgf.ro.bmSelectedEvents);
50	AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.cHardIntBreakpoints, VM, dbgf.ro.cHardIntBreakpoints);
51	AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.cSoftIntBreakpoints, VM, dbgf.ro.cSoftIntBreakpoints);
52	AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.cSelectedEvents, VM, dbgf.ro.cSelectedEvents);
53
54	#if !defined(VBOX_VMM_TARGET_ARMV8)
55
56
57	/**
58	* Gets the hardware breakpoint configuration as DR7.
59	*
60	* @returns DR7 from the DBGF point of view.
61	* @param pVM The cross context VM structure.
62	*/
63	VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR7(PVM pVM)
64	{
65	RTGCUINTREG uDr7 = X86_DR7_GD \| X86_DR7_GE \| X86_DR7_LE \| X86_DR7_RA1_MASK;
66	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->dbgf.s.aHwBreakpoints); i++)
67	{
68	if ( pVM->dbgf.s.aHwBreakpoints[i].fEnabled
69	&& pVM->dbgf.s.aHwBreakpoints[i].hBp != NIL_DBGFBP)
70	{
71	static const uint8_t s_au8Sizes[8] =
72	{
73	X86_DR7_LEN_BYTE, X86_DR7_LEN_BYTE, X86_DR7_LEN_WORD, X86_DR7_LEN_BYTE,
74	X86_DR7_LEN_DWORD,X86_DR7_LEN_BYTE, X86_DR7_LEN_BYTE, X86_DR7_LEN_QWORD
75	};
76	uDr7 \|= X86_DR7_G(i)
77	\| X86_DR7_RW(i, pVM->dbgf.s.aHwBreakpoints[i].fType)
78	\| X86_DR7_LEN(i, s_au8Sizes[pVM->dbgf.s.aHwBreakpoints[i].cb]);
79	}
80	}
81	return uDr7;
82	}
83
84
85	/**
86	* Gets the address of the hardware breakpoint number 0.
87	*
88	* @returns DR0 from the DBGF point of view.
89	* @param pVM The cross context VM structure.
90	*/
91	VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR0(PVM pVM)
92	{
93	return pVM->dbgf.s.aHwBreakpoints[0].GCPtr;
94	}
95
96
97	/**
98	* Gets the address of the hardware breakpoint number 1.
99	*
100	* @returns DR1 from the DBGF point of view.
101	* @param pVM The cross context VM structure.
102	*/
103	VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR1(PVM pVM)
104	{
105	return pVM->dbgf.s.aHwBreakpoints[1].GCPtr;
106	}
107
108
109	/**
110	* Gets the address of the hardware breakpoint number 2.
111	*
112	* @returns DR2 from the DBGF point of view.
113	* @param pVM The cross context VM structure.
114	*/
115	VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR2(PVM pVM)
116	{
117	return pVM->dbgf.s.aHwBreakpoints[2].GCPtr;
118	}
119
120
121	/**
122	* Gets the address of the hardware breakpoint number 3.
123	*
124	* @returns DR3 from the DBGF point of view.
125	* @param pVM The cross context VM structure.
126	*/
127	VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR3(PVM pVM)
128	{
129	return pVM->dbgf.s.aHwBreakpoints[3].GCPtr;
130	}
131
132
133	/**
134	* Checks if any of the hardware breakpoints are armed.
135	*
136	* @returns true if armed, false if not.
137	* @param pVM The cross context VM structure.
138	* @remarks Don't call this from CPUMRecalcHyperDRx!
139	*/
140	VMM_INT_DECL(bool) DBGFBpIsHwArmed(PVM pVM)
141	{
142	return pVM->dbgf.s.cEnabledHwBreakpoints > 0;
143	}
144
145
146	/**
147	* Checks if any of the hardware I/O breakpoints are armed.
148	*
149	* @returns true if armed, false if not.
150	* @param pVM The cross context VM structure.
151	* @remarks Don't call this from CPUMRecalcHyperDRx!
152	*/
153	VMM_INT_DECL(bool) DBGFBpIsHwIoArmed(PVM pVM)
154	{
155	return pVM->dbgf.s.cEnabledHwIoBreakpoints > 0;
156	}
157
158
159	/**
160	* Checks if any INT3 breakpoints are armed.
161	*
162	* @returns true if armed, false if not.
163	* @param pVM The cross context VM structure.
164	* @remarks Don't call this from CPUMRecalcHyperDRx!
165	*/
166	VMM_INT_DECL(bool) DBGFBpIsInt3Armed(PVM pVM)
167	{
168	/** @todo There was a todo here and returning false when I (bird) removed
169	* VBOX_WITH_LOTS_OF_DBGF_BPS, so this might not be correct. */
170	return pVM->dbgf.s.cEnabledSwBreakpoints > 0;
171	}
172
173	#endif /* !VBOX_VMM_TARGET_ARMV8 */
174
175	/**
176	* Checks instruction boundrary for guest or hypervisor hardware breakpoints.
177	*
178	* @returns Strict VBox status code. May return DRx register import errors in
179	* addition to the ones detailed.
180	* @retval VINF_SUCCESS no breakpoint.
181	* @retval VINF_EM_DBG_BREAKPOINT hypervisor breakpoint triggered.
182	* @retval VINF_EM_RAW_GUEST_TRAP caller must trigger \#DB trap, DR6 and DR7
183	* have been updated appropriately.
184	*
185	* @param pVM The cross context VM structure.
186	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
187	* @param GCPtrPC The unsegmented PC address.
188	* @param fCheckGuest Whether to include guest breakpoints or not.
189	*/
190	VMM_INT_DECL(VBOXSTRICTRC) DBGFBpCheckInstruction(PVMCC pVM, PVMCPUCC pVCpu, RTGCPTR GCPtrPC, bool fCheckGuest)
191	{
192	#ifdef VBOX_VMM_TARGET_X86
193	CPUM_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DR7);
194	#endif
195
196	/*
197	* Check hyper breakpoints first as the VMM debugger has priority over
198	* the guest.
199	*/
200	/** @todo we need some kind of resume flag for these. */
201	if (pVM->dbgf.s.cEnabledHwBreakpoints > 0)
202	for (unsigned iBp = 0; iBp < RT_ELEMENTS(pVM->dbgf.s.aHwBreakpoints); iBp++)
203	{
204	if ( pVM->dbgf.s.aHwBreakpoints[iBp].GCPtr != GCPtrPC
205	\|\| pVM->dbgf.s.aHwBreakpoints[iBp].fType != X86_DR7_RW_EO
206	\|\| pVM->dbgf.s.aHwBreakpoints[iBp].cb != 1
207	\|\| !pVM->dbgf.s.aHwBreakpoints[iBp].fEnabled
208	\|\| pVM->dbgf.s.aHwBreakpoints[iBp].hBp == NIL_DBGFBP)
209	{ /likely/ }
210	else
211	{
212	/* (See also DBGFRZTrap01Handler.) */
213	pVCpu->dbgf.s.hBpActive = pVM->dbgf.s.aHwBreakpoints[iBp].hBp;
214	pVCpu->dbgf.s.fSingleSteppingRaw = false;
215
216	#ifdef VBOX_VMM_TARGET_X86
217	LogFlow(("DBGFBpCheckInstruction: hit hw breakpoint %u at %04x:%RGv (%RGv)\n",
218	iBp, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, GCPtrPC));
219	#else
220	LogFlow(("DBGFBpCheckInstruction: hit hw breakpoint %u at %RGv\n", iBp, GCPtrPC));
221	#endif
222	return VINF_EM_DBG_BREAKPOINT;
223	}
224	}
225
226	/*
227	* Check the guest.
228	*/
229	if (fCheckGuest)
230	{
231	#ifdef VBOX_VMM_TARGET_X86
232	uint32_t const fDr7 = (uint32_t)pVCpu->cpum.GstCtx.dr[7];
233	if (X86_DR7_ANY_EO_ENABLED(fDr7) && !pVCpu->cpum.GstCtx.eflags.Bits.u1RF)
234	{
235	/*
236	* The CPU (10980XE & 6700K at least) will set the DR6.BPx bits for any
237	* DRx that matches the current PC and is configured as an execution
238	* breakpoint (RWx=EO, LENx=1byte). They don't have to be enabled,
239	* however one that is enabled must match for the #DB to be raised and
240	* DR6 to be modified, of course.
241	*/
242	CPUM_IMPORT_EXTRN_RET(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
243	uint32_t fMatched = 0;
244	uint32_t fEnabled = 0;
245	for (unsigned iBp = 0, uBpMask = 1; iBp < 4; iBp++, uBpMask <<= 1)
246	if (X86_DR7_IS_EO_CFG(fDr7, iBp))
247	{
248	if (fDr7 & X86_DR7_L_G(iBp))
249	fEnabled \|= uBpMask;
250	if (pVCpu->cpum.GstCtx.dr[iBp] == GCPtrPC)
251	fMatched \|= uBpMask;
252	}
253	if (!(fEnabled & fMatched))
254	{ /likely/ }
255	else
256	{
257	/*
258	* Update DR6 and DR7.
259	*
260	* See "AMD64 Architecture Programmer's Manual Volume 2", chapter
261	* 13.1.1.3 for details on DR6 bits. The basics is that the B0..B3
262	* bits are always cleared while the others must be cleared by software.
263	*
264	* The following sub chapters says the GD bit is always cleared when
265	* generating a #DB so the handler can safely access the debug registers.
266	*/
267	CPUM_IMPORT_EXTRN_RET(pVCpu, CPUMCTX_EXTRN_DR6);
268	pVCpu->cpum.GstCtx.dr[6] &= ~X86_DR6_B_MASK;
269	if (pVM->cpum.ro.GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INTEL)
270	pVCpu->cpum.GstCtx.dr[6] \|= fMatched & fEnabled;
271	else
272	pVCpu->cpum.GstCtx.dr[6] \|= fMatched; /* Intel: All matched, regardless of whether they're enabled or not */
273	pVCpu->cpum.GstCtx.dr[7] &= ~X86_DR7_GD;
274	LogFlow(("DBGFBpCheckInstruction: hit hw breakpoints %#x at %04x:%RGv (%RGv)\n",
275	fMatched, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, GCPtrPC));
276	return VINF_EM_RAW_GUEST_TRAP;
277	}
278	}
279	#else
280	/** @todo ARMv8: port me! */
281	#endif
282	}
283	return VINF_SUCCESS;
284	}
285
286
287	/**
288	* Common worker for DBGFBpCheckDataRead and DBGFBpCheckDataWrite.
289	*/
290	template<bool const a_fRead>
291	DECL_FORCE_INLINE(uint32_t) dbgfBpCheckData(PVMCC pVM, PVMCPUCC pVCpu, RTGCPTR GCPtrAccess, uint32_t cbAccess, bool fSysAccess)
292	{
293	#ifdef VBOX_VMM_TARGET_X86
294	AssertCompile((X86_DR7_RW_RW & 1) && (X86_DR7_RW_WO & 1));
295	CPUM_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DR7);
296	#endif
297
298	uint32_t fRet = 0;
299	RTGCPTR const GCPtrAccessPfn = GCPtrAccess >> GUEST_PAGE_SHIFT;
300	Assert(((GCPtrAccess + cbAccess - 1) >> GUEST_PAGE_SHIFT) == GCPtrAccessPfn); /* No page crossing expected here! */
301
302	/*
303	* Check hyper breakpoints first as the VMM debugger has priority over
304	* the guest.
305	*/
306	if (pVM->dbgf.s.cEnabledHwBreakpoints > 0)
307	for (unsigned iBp = 0; iBp < RT_ELEMENTS(pVM->dbgf.s.aHwBreakpoints); iBp++)
308	{
309	if ( (pVM->dbgf.s.aHwBreakpoints[iBp].GCPtr >> GUEST_PAGE_SHIFT) != GCPtrAccessPfn
310	\|\| ( a_fRead
311	? pVM->dbgf.s.aHwBreakpoints[iBp].fType != X86_DR7_RW_RW
312	: !(pVM->dbgf.s.aHwBreakpoints[iBp].fType & 1))
313	\|\| pVM->dbgf.s.aHwBreakpoints[iBp].cb != 0
314	\|\| !pVM->dbgf.s.aHwBreakpoints[iBp].fEnabled
315	\|\| pVM->dbgf.s.aHwBreakpoints[iBp].hBp == NIL_DBGFBP)
316	{ /likely/ }
317	else
318	{
319	/* The page is of interest. */
320	#ifdef VBOX_VMM_TARGET_X86 /** @todo ARMv8: port me */
321	AssertCompile(!((CPUMCTX_DBG_HIT_DRX_MASK \| CPUMCTX_DBG_DBGF_MASK) & UINT32_C(1)));
322	#endif
323	fRet \|= UINT32_C(1);
324
325	/* If the access overlapping the breakpoint area, we have a hit. */
326	if ( GCPtrAccess < pVM->dbgf.s.aHwBreakpoints[iBp].GCPtr + pVM->dbgf.s.aHwBreakpoints[iBp].cb
327	&& GCPtrAccess + cbAccess > pVM->dbgf.s.aHwBreakpoints[iBp].GCPtr)
328	{
329	pVCpu->dbgf.s.hBpActive = pVM->dbgf.s.aHwBreakpoints[iBp].hBp; /* ? */
330	pVCpu->dbgf.s.fSingleSteppingRaw = false;
331	LogFlow(("DBGFBpCheckData%s: hit hw breakpoint %u when accessing %RGv LB %#x\n",
332	a_fRead ? "Read" : "Write", iBp, GCPtrAccess, cbAccess));
333	#ifdef VBOX_VMM_TARGET_X86 /** @todo ARMv8: port me */
334	fRet \|= CPUMCTX_DBG_DBGF_BP;
335	#endif
336	}
337	}
338	}
339
340	/*
341	* Check the guest.
342	*/
343	#ifdef VBOX_VMM_TARGET_X86
344	uint32_t const fDr7 = (uint32_t)pVCpu->cpum.GstCtx.dr[7];
345	if ( (a_fRead ? X86_DR7_ANY_RW_ENABLED(fDr7) : X86_DR7_ANY_W_ENABLED(fDr7))
346	&& !pVCpu->cpum.GstCtx.eflags.Bits.u1RF)
347	{
348	/* This is a bit suboptimal... Need a NORET variant. */
349	int rcIgn = VINF_SUCCESS;
350	CPUM_IMPORT_EXTRN_RCSTRICT(pVCpu, CPUMCTX_EXTRN_DR0_DR3, rcIgn);
351	RT_NOREF(rcIgn);
352
353	/** @todo Not sure what exactly intel and amd CPUs does here wrt disabled
354	* breakpoint configurations. We need a testcase for this. Following
355	* the guidelines of the execution breakpoints for now and making
356	* intel CPUs set status flags regardless of enabled or not. */
357	uint32_t fMatched = 0;
358	uint32_t fEnabled = 0;
359	for (uint32_t iBp = 0, fBpMask = CPUMCTX_DBG_HIT_DR0, fDr7Cfg = fDr7 >> 16, fDr7En = fDr7;
360	iBp < 4;
361	iBp++, fBpMask <<= 1, fDr7Cfg >>= 4, fDr7En >>= 2)
362	if ( (a_fRead ? (fDr7Cfg & 3) == X86_DR7_RW_RW : (fDr7Cfg & 1) != 0)
363	&& (pVCpu->cpum.GstCtx.dr[iBp] >> GUEST_PAGE_SHIFT) == GCPtrAccessPfn)
364	{
365	if (fDr7En & 3)
366	{
367	fEnabled \|= fBpMask;
368	fRet \|= UINT32_C(1);
369	}
370	static uint8_t const s_acbBp[] = { 1, 2, 8, 4 };
371	uint8_t const cbBp = s_acbBp[(fDr7Cfg >> 2) & 3];
372	if ( GCPtrAccess < pVCpu->cpum.GstCtx.dr[iBp] + cbBp
373	&& GCPtrAccess + cbAccess > pVCpu->cpum.GstCtx.dr[iBp])
374	fMatched \|= fBpMask;
375	}
376	if (!(fEnabled & fMatched))
377	{ /likely/ }
378	else
379	{
380	if (pVM->cpum.ro.GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INTEL)
381	fRet \|= fMatched & fEnabled;
382	else if (!fSysAccess)
383	fRet \|= fMatched;
384	else
385	fRet \|= CPUMCTX_DBG_HIT_DRX_SILENT; /* see bs3-cpu-weird-1 for special intel behviour */
386	LogFlow(("DBGFBpCheckData%s: hit hw breakpoints %#x (fRet=%#x) when accessing %RGv LB %#x\n",
387	a_fRead ? "Read" : "Write", fMatched, fRet, GCPtrAccess, cbAccess));
388	}
389	}
390	#else
391	/** @todo ARMv8: port me! */
392	#endif
393
394	RT_NOREF(fSysAccess);
395	return fRet;
396	}
397
398
399	/**
400	* Checks read data access for guest or hypervisor hardware breakpoints.
401	*
402	* @returns Anything in CPUMCTX_DBG_HIT_DRX_MASK and CPUMCTX_DBG_DBGF_MASK if
403	* there is a hit, zero or one if no hit. Bit 0 is set if the page
404	* being accessed has a data breakpoint associated with it and needs
405	* special handling.
406	*
407	* @param pVM The cross context VM structure.
408	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
409	* @param GCPtrAccess The address being accessed.
410	* @param cbAccess The size of the access. Must not cross a page
411	* boundrary.
412	* @param fSysAccess Set if a system access, like GDT, LDT or IDT.
413	*/
414	VMM_INT_DECL(uint32_t) DBGFBpCheckDataRead(PVMCC pVM, PVMCPUCC pVCpu, RTGCPTR GCPtrAccess, uint32_t cbAccess, bool fSysAccess)
415	{
416	return dbgfBpCheckData<true /a_fRead/>(pVM, pVCpu, GCPtrAccess, cbAccess, fSysAccess);
417	}
418
419
420	/**
421	* Checks read data access for guest or hypervisor hardware breakpoints.
422	*
423	* @returns Anything in CPUMCTX_DBG_DBGF_MASK if there is a hit, zero or one if
424	* no hit. Bit 0 is set if the page being accessed has a data
425	* breakpoint associated with it and needs special handling.
426	*
427	* @param pVM The cross context VM structure.
428	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
429	* @param GCPtrAccess The address being accessed.
430	* @param cbAccess The size of the access. Must not cross a page
431	* boundrary.
432	* @param fSysAccess Set if a system access, like GDT, LDT or IDT.
433	*/
434	VMM_INT_DECL(uint32_t) DBGFBpCheckDataWrite(PVMCC pVM, PVMCPUCC pVCpu, RTGCPTR GCPtrAccess, uint32_t cbAccess, bool fSysAccess)
435	{
436	return dbgfBpCheckData<false /a_fRead/>(pVM, pVCpu, GCPtrAccess, cbAccess, fSysAccess);
437	}
438
439	#if !defined(VBOX_VMM_TARGET_ARMV8)
440
441	/**
442	* Checks I/O access for guest or hypervisor hardware breakpoints.
443	*
444	* @returns Strict VBox status code
445	* @retval VINF_SUCCESS no breakpoint.
446	* @retval VINF_EM_DBG_BREAKPOINT hypervisor breakpoint triggered.
447	* @retval VINF_EM_RAW_GUEST_TRAP guest breakpoint triggered, DR6 and DR7 have
448	* been updated appropriately.
449	*
450	* @param pVM The cross context VM structure.
451	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
452	* @param pCtx The CPU context for the calling EMT.
453	* @param uIoPort The I/O port being accessed.
454	* @param cbValue The size/width of the access, in bytes.
455	*/
456	VMM_INT_DECL(VBOXSTRICTRC) DBGFBpCheckIo(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTIOPORT uIoPort, uint8_t cbValue)
457	{
458	uint32_t const uIoPortFirst = uIoPort;
459	uint32_t const uIoPortLast = uIoPortFirst + cbValue - 1;
460
461	/*
462	* Check hyper breakpoints first as the VMM debugger has priority over
463	* the guest.
464	*/
465	if (pVM->dbgf.s.cEnabledHwIoBreakpoints > 0)
466	{
467	for (unsigned iBp = 0; iBp < RT_ELEMENTS(pVM->dbgf.s.aHwBreakpoints); iBp++)
468	{
469	if ( pVM->dbgf.s.aHwBreakpoints[iBp].fType == X86_DR7_RW_IO
470	&& pVM->dbgf.s.aHwBreakpoints[iBp].fEnabled
471	&& pVM->dbgf.s.aHwBreakpoints[iBp].hBp != NIL_DBGFBP)
472	{
473	uint8_t cbReg = pVM->dbgf.s.aHwBreakpoints[iBp].cb; Assert(RT_IS_POWER_OF_TWO(cbReg));
474	uint64_t uDrXFirst = pVM->dbgf.s.aHwBreakpoints[iBp].GCPtr & ~(uint64_t)(cbReg - 1);
475	uint64_t uDrXLast = uDrXFirst + cbReg - 1;
476	if (uDrXFirst <= uIoPortLast && uDrXLast >= uIoPortFirst)
477	{
478	/* (See also DBGFRZTrap01Handler.) */
479	pVCpu->dbgf.s.hBpActive = pVM->dbgf.s.aHwBreakpoints[iBp].hBp;
480	pVCpu->dbgf.s.fSingleSteppingRaw = false;
481
482	LogFlow(("DBGFBpCheckIo: hit hw breakpoint %d at %04x:%RGv (iop %#x)\n",
483	iBp, pCtx->cs.Sel, pCtx->rip, uIoPort));
484	return VINF_EM_DBG_BREAKPOINT;
485	}
486	}
487	}
488	}
489
490	/*
491	* Check the guest.
492	*/
493	uint32_t const uDr7 = pCtx->dr[7];
494	if ( (uDr7 & X86_DR7_ENABLED_MASK)
495	&& X86_DR7_ANY_RW_IO(uDr7)
496	&& (pCtx->cr4 & X86_CR4_DE) )
497	{
498	for (unsigned iBp = 0; iBp < 4; iBp++)
499	{
500	if ( (uDr7 & X86_DR7_L_G(iBp))
501	&& X86_DR7_GET_RW(uDr7, iBp) == X86_DR7_RW_IO)
502	{
503	/* ASSUME the breakpoint and the I/O width qualifier uses the same encoding (1 2 x 4). */
504	static uint8_t const s_abInvAlign[4] = { 0, 1, 7, 3 };
505	uint8_t cbInvAlign = s_abInvAlign[X86_DR7_GET_LEN(uDr7, iBp)];
506	uint64_t uDrXFirst = pCtx->dr[iBp] & ~(uint64_t)cbInvAlign;
507	uint64_t uDrXLast = uDrXFirst + cbInvAlign;
508
509	if (uDrXFirst <= uIoPortLast && uDrXLast >= uIoPortFirst)
510	{
511	/*
512	* Update DR6 and DR7.
513	*
514	* See "AMD64 Architecture Programmer's Manual Volume 2",
515	* chapter 13.1.1.3 for details on DR6 bits. The basics is
516	* that the B0..B3 bits are always cleared while the others
517	* must be cleared by software.
518	*
519	* The following sub chapters says the GD bit is always
520	* cleared when generating a #DB so the handler can safely
521	* access the debug registers.
522	*/
523	pCtx->dr[6] &= ~X86_DR6_B_MASK;
524	pCtx->dr[6] \|= X86_DR6_B(iBp);
525	pCtx->dr[7] &= ~X86_DR7_GD;
526	LogFlow(("DBGFBpCheckIo: hit hw breakpoint %d at %04x:%RGv (iop %#x)\n",
527	iBp, pCtx->cs.Sel, pCtx->rip, uIoPort));
528	return VINF_EM_RAW_GUEST_TRAP;
529	}
530	}
531	}
532	}
533	return VINF_SUCCESS;
534	}
535
536
537	/**
538	* Checks I/O access for guest or hypervisor hardware breakpoints.
539	*
540	* Caller must make sure DR0-3 and DR7 are present in the CPU context before
541	* calling this function.
542	*
543	* @returns CPUMCTX_DBG_DBGF_BP, CPUMCTX_DBG_HIT_DRX_MASK, or 0 (no match).
544	*
545	* @param pVM The cross context VM structure.
546	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
547	* @param uIoPort The I/O port being accessed.
548	* @param cbValue The size/width of the access, in bytes.
549	*/
550	VMM_INT_DECL(uint32_t) DBGFBpCheckIo2(PVMCC pVM, PVMCPUCC pVCpu, RTIOPORT uIoPort, uint8_t cbValue)
551	{
552	uint32_t const uIoPortFirst = uIoPort;
553	uint32_t const uIoPortLast = uIoPortFirst + cbValue - 1;
554
555	/*
556	* Check hyper breakpoints first as the VMM debugger has priority over
557	* the guest.
558	*/
559	if (pVM->dbgf.s.cEnabledHwIoBreakpoints > 0)
560	for (unsigned iBp = 0; iBp < RT_ELEMENTS(pVM->dbgf.s.aHwBreakpoints); iBp++)
561	{
562	if ( pVM->dbgf.s.aHwBreakpoints[iBp].fType == X86_DR7_RW_IO
563	&& pVM->dbgf.s.aHwBreakpoints[iBp].fEnabled
564	&& pVM->dbgf.s.aHwBreakpoints[iBp].hBp != NIL_DBGFBP)
565	{
566	uint8_t cbReg = pVM->dbgf.s.aHwBreakpoints[iBp].cb; Assert(RT_IS_POWER_OF_TWO(cbReg));
567	uint64_t uDrXFirst = pVM->dbgf.s.aHwBreakpoints[iBp].GCPtr & ~(uint64_t)(cbReg - 1);
568	uint64_t uDrXLast = uDrXFirst + cbReg - 1;
569	if (uDrXFirst <= uIoPortLast && uDrXLast >= uIoPortFirst)
570	{
571	/* (See also DBGFRZTrap01Handler.) */
572	pVCpu->dbgf.s.hBpActive = pVM->dbgf.s.aHwBreakpoints[iBp].hBp;
573	pVCpu->dbgf.s.fSingleSteppingRaw = false;
574
575	LogFlow(("DBGFBpCheckIo2: hit hw breakpoint %d at %04x:%RGv (iop %#x L %u)\n",
576	iBp, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, uIoPort, cbValue));
577	return CPUMCTX_DBG_DBGF_BP;
578	}
579	}
580	}
581
582	/*
583	* Check the guest.
584	*/
585	uint32_t const fDr7 = pVCpu->cpum.GstCtx.dr[7];
586	if ( (fDr7 & X86_DR7_ENABLED_MASK)
587	&& X86_DR7_ANY_RW_IO(fDr7)
588	&& (pVCpu->cpum.GstCtx.cr4 & X86_CR4_DE) )
589	{
590	uint32_t fEnabled = 0;
591	uint32_t fMatched = 0;
592	for (unsigned iBp = 0, uBpMask = 1; iBp < 4; iBp++, uBpMask <<= 1)
593	{
594	if (fDr7 & X86_DR7_L_G(iBp))
595	fEnabled \|= uBpMask;
596	if (X86_DR7_GET_RW(fDr7, iBp) == X86_DR7_RW_IO)
597	{
598	/* ASSUME the breakpoint and the I/O width qualifier uses the same encoding (1 2 x 4). */
599	static uint8_t const s_abInvAlign[4] = { 0, 1, 7, 3 };
600	uint8_t const cbInvAlign = s_abInvAlign[X86_DR7_GET_LEN(fDr7, iBp)];
601	uint64_t const uDrXFirst = pVCpu->cpum.GstCtx.dr[iBp] & ~(uint64_t)cbInvAlign;
602	uint64_t const uDrXLast = uDrXFirst + cbInvAlign;
603	if (uDrXFirst <= uIoPortLast && uDrXLast >= uIoPortFirst)
604	fMatched \|= uBpMask;
605	}
606	}
607	if (fEnabled & fMatched)
608	{
609	LogFlow(("DBGFBpCheckIo2: hit hw breakpoint %#x at %04x:%RGv (iop %#x L %u)\n",
610	fMatched, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, uIoPort, cbValue));
611	return fMatched << CPUMCTX_DBG_HIT_DRX_SHIFT;
612	}
613	}
614
615	return 0;
616	}
617
618	#endif /* !VBOX_VMM_TARGET_ARMV8 */
619
620	/**
621	* Returns the single stepping state for a virtual CPU.
622	*
623	* @returns stepping (true) or not (false).
624	*
625	* @param pVCpu The cross context virtual CPU structure.
626	*/
627	VMM_INT_DECL(bool) DBGFIsStepping(PVMCPU pVCpu)
628	{
629	return pVCpu->dbgf.s.fSingleSteppingRaw;
630	}
631
632
633	/**
634	* Checks if the specified generic event is enabled or not.
635	*
636	* @returns true / false.
637	* @param pVM The cross context VM structure.
638	* @param enmEvent The generic event being raised.
639	* @param uEventArg The argument of that event.
640	*/
641	DECLINLINE(bool) dbgfEventIsGenericWithArgEnabled(PVM pVM, DBGFEVENTTYPE enmEvent, uint64_t uEventArg)
642	{
643	if (DBGF_IS_EVENT_ENABLED(pVM, enmEvent))
644	{
645	switch (enmEvent)
646	{
647	case DBGFEVENT_INTERRUPT_HARDWARE:
648	AssertReturn(uEventArg < 256, false);
649	return ASMBitTest(pVM->dbgf.s.bmHardIntBreakpoints, (uint32_t)uEventArg);
650
651	case DBGFEVENT_INTERRUPT_SOFTWARE:
652	AssertReturn(uEventArg < 256, false);
653	return ASMBitTest(pVM->dbgf.s.bmSoftIntBreakpoints, (uint32_t)uEventArg);
654
655	default:
656	return true;
657
658	}
659	}
660	return false;
661	}
662
663
664	/**
665	* Raises a generic debug event if enabled and not being ignored.
666	*
667	* @returns Strict VBox status code.
668	* @retval VINF_EM_DBG_EVENT if the event was raised and the caller should
669	* return ASAP to the debugger (via EM). We set VMCPU_FF_DBGF so, it
670	* is okay not to pass this along in some situations.
671	* @retval VINF_SUCCESS if the event was disabled or ignored.
672	*
673	* @param pVM The cross context VM structure.
674	* @param pVCpu The cross context virtual CPU structure.
675	* @param enmEvent The generic event being raised.
676	* @param enmCtx The context in which this event is being raised.
677	* @param cArgs Number of arguments (0 - 6).
678	* @param ... Event arguments.
679	*
680	* @thread EMT(pVCpu)
681	*/
682	VMM_INT_DECL(VBOXSTRICTRC) DBGFEventGenericWithArgs(PVM pVM, PVMCPU pVCpu, DBGFEVENTTYPE enmEvent, DBGFEVENTCTX enmCtx,
683	unsigned cArgs, ...)
684	{
685	Assert(cArgs < RT_ELEMENTS(pVCpu->dbgf.s.aEvents[0].Event.u.Generic.auArgs));
686
687	/*
688	* Is it enabled.
689	*/
690	va_list va;
691	va_start(va, cArgs);
692	uint64_t uEventArg0 = cArgs ? va_arg(va, uint64_t) : 0;
693	if (dbgfEventIsGenericWithArgEnabled(pVM, enmEvent, uEventArg0))
694	{
695	/*
696	* Any events on the stack. Should the incoming event be ignored?
697	*/
698	#if defined(VBOX_VMM_TARGET_ARMV8)
699	uint64_t const rip = CPUMGetGuestFlatPC(pVCpu); /* rip is a misnomer but saves us #ifdef's later on. */
700	#else
701	uint64_t const rip = CPUMGetGuestRIP(pVCpu);
702	#endif
703	uint32_t i = pVCpu->dbgf.s.cEvents;
704	if (i > 0)
705	{
706	while (i-- > 0)
707	{
708	if ( pVCpu->dbgf.s.aEvents[i].Event.enmType == enmEvent
709	&& pVCpu->dbgf.s.aEvents[i].enmState == DBGFEVENTSTATE_IGNORE
710	&& pVCpu->dbgf.s.aEvents[i].rip == rip)
711	{
712	pVCpu->dbgf.s.aEvents[i].enmState = DBGFEVENTSTATE_RESTORABLE;
713	va_end(va);
714	return VINF_SUCCESS;
715	}
716	Assert(pVCpu->dbgf.s.aEvents[i].enmState != DBGFEVENTSTATE_CURRENT);
717	}
718
719	/*
720	* Trim the event stack.
721	*/
722	i = pVCpu->dbgf.s.cEvents;
723	while (i-- > 0)
724	{
725	if ( pVCpu->dbgf.s.aEvents[i].rip == rip
726	&& ( pVCpu->dbgf.s.aEvents[i].enmState == DBGFEVENTSTATE_RESTORABLE
727	\|\| pVCpu->dbgf.s.aEvents[i].enmState == DBGFEVENTSTATE_IGNORE) )
728	pVCpu->dbgf.s.aEvents[i].enmState = DBGFEVENTSTATE_IGNORE;
729	else
730	{
731	if (i + 1 != pVCpu->dbgf.s.cEvents)
732	memmove(&pVCpu->dbgf.s.aEvents[i], &pVCpu->dbgf.s.aEvents[i + 1],
733	(pVCpu->dbgf.s.cEvents - i) * sizeof(pVCpu->dbgf.s.aEvents));
734	pVCpu->dbgf.s.cEvents--;
735	}
736	}
737
738	i = pVCpu->dbgf.s.cEvents;
739	AssertStmt(i < RT_ELEMENTS(pVCpu->dbgf.s.aEvents), i = RT_ELEMENTS(pVCpu->dbgf.s.aEvents) - 1);
740	}
741
742	/*
743	* Push the event.
744	*/
745	pVCpu->dbgf.s.aEvents[i].enmState = DBGFEVENTSTATE_CURRENT;
746	pVCpu->dbgf.s.aEvents[i].rip = rip;
747	pVCpu->dbgf.s.aEvents[i].Event.enmType = enmEvent;
748	pVCpu->dbgf.s.aEvents[i].Event.enmCtx = enmCtx;
749	pVCpu->dbgf.s.aEvents[i].Event.u.Generic.cArgs = cArgs;
750	pVCpu->dbgf.s.aEvents[i].Event.u.Generic.auArgs[0] = uEventArg0;
751	if (cArgs > 1)
752	{
753	AssertStmt(cArgs < RT_ELEMENTS(pVCpu->dbgf.s.aEvents[i].Event.u.Generic.auArgs),
754	cArgs = RT_ELEMENTS(pVCpu->dbgf.s.aEvents[i].Event.u.Generic.auArgs));
755	for (unsigned iArg = 1; iArg < cArgs; iArg++)
756	pVCpu->dbgf.s.aEvents[i].Event.u.Generic.auArgs[iArg] = va_arg(va, uint64_t);
757	}
758	pVCpu->dbgf.s.cEvents = i + 1;
759
760	VMCPU_FF_SET(pVCpu, VMCPU_FF_DBGF);
761	va_end(va);
762	return VINF_EM_DBG_EVENT;
763	}
764
765	va_end(va);
766	return VINF_SUCCESS;
767	}
768

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source: vbox/trunk/src/VBox/VMM/VMMAll/DBGFAll.cpp

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