VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/DBGFAll.cpp@ 66974

Last change on this file since 66974 was 64770, checked in by vboxsync, 8 years ago

VMM/DBGF, HM: Fix int3 based breakpoints set in the VM debugger when using VT-x.
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1/* $Id: DBGFAll.cpp 64770 2016-12-01 12:28:44Z vboxsync $ */
2/** @file
3 * DBGF - Debugger Facility, All Context Code.
4 */
5
6/*
7 * Copyright (C) 2006-2016 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DBGF
23#include <VBox/vmm/dbgf.h>
24#include "DBGFInternal.h"
25#include <VBox/vmm/vm.h>
26#include <VBox/err.h>
27#include <iprt/assert.h>
28#include <iprt/asm.h>
29
30
31/*
32 * Check the read-only VM members.
33 */
34AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.bmSoftIntBreakpoints, VM, dbgf.ro.bmSoftIntBreakpoints);
35AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.bmHardIntBreakpoints, VM, dbgf.ro.bmHardIntBreakpoints);
36AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.bmSelectedEvents, VM, dbgf.ro.bmSelectedEvents);
37AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.cHardIntBreakpoints, VM, dbgf.ro.cHardIntBreakpoints);
38AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.cSoftIntBreakpoints, VM, dbgf.ro.cSoftIntBreakpoints);
39AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.cSelectedEvents, VM, dbgf.ro.cSelectedEvents);
40
41
42/**
43 * Gets the hardware breakpoint configuration as DR7.
44 *
45 * @returns DR7 from the DBGF point of view.
46 * @param pVM The cross context VM structure.
47 */
48VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR7(PVM pVM)
49{
50 RTGCUINTREG uDr7 = X86_DR7_GD | X86_DR7_GE | X86_DR7_LE | X86_DR7_RA1_MASK;
51 PDBGFBP pBp = &pVM->dbgf.s.aHwBreakpoints[0];
52 unsigned cLeft = RT_ELEMENTS(pVM->dbgf.s.aHwBreakpoints);
53 while (cLeft-- > 0)
54 {
55 if ( pBp->enmType == DBGFBPTYPE_REG
56 && pBp->fEnabled)
57 {
58 static const uint8_t s_au8Sizes[8] =
59 {
60 X86_DR7_LEN_BYTE, X86_DR7_LEN_BYTE, X86_DR7_LEN_WORD, X86_DR7_LEN_BYTE,
61 X86_DR7_LEN_DWORD,X86_DR7_LEN_BYTE, X86_DR7_LEN_BYTE, X86_DR7_LEN_QWORD
62 };
63 uDr7 |= X86_DR7_G(pBp->u.Reg.iReg)
64 | X86_DR7_RW(pBp->u.Reg.iReg, pBp->u.Reg.fType)
65 | X86_DR7_LEN(pBp->u.Reg.iReg, s_au8Sizes[pBp->u.Reg.cb]);
66 }
67 pBp++;
68 }
69 return uDr7;
70}
71
72
73/**
74 * Gets the address of the hardware breakpoint number 0.
75 *
76 * @returns DR0 from the DBGF point of view.
77 * @param pVM The cross context VM structure.
78 */
79VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR0(PVM pVM)
80{
81 PCDBGFBP pBp = &pVM->dbgf.s.aHwBreakpoints[0];
82 Assert(pBp->u.Reg.iReg == 0);
83 return pBp->u.Reg.GCPtr;
84}
85
86
87/**
88 * Gets the address of the hardware breakpoint number 1.
89 *
90 * @returns DR1 from the DBGF point of view.
91 * @param pVM The cross context VM structure.
92 */
93VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR1(PVM pVM)
94{
95 PCDBGFBP pBp = &pVM->dbgf.s.aHwBreakpoints[1];
96 Assert(pBp->u.Reg.iReg == 1);
97 return pBp->u.Reg.GCPtr;
98}
99
100
101/**
102 * Gets the address of the hardware breakpoint number 2.
103 *
104 * @returns DR2 from the DBGF point of view.
105 * @param pVM The cross context VM structure.
106 */
107VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR2(PVM pVM)
108{
109 PCDBGFBP pBp = &pVM->dbgf.s.aHwBreakpoints[2];
110 Assert(pBp->u.Reg.iReg == 2);
111 return pBp->u.Reg.GCPtr;
112}
113
114
115/**
116 * Gets the address of the hardware breakpoint number 3.
117 *
118 * @returns DR3 from the DBGF point of view.
119 * @param pVM The cross context VM structure.
120 */
121VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR3(PVM pVM)
122{
123 PCDBGFBP pBp = &pVM->dbgf.s.aHwBreakpoints[3];
124 Assert(pBp->u.Reg.iReg == 3);
125 return pBp->u.Reg.GCPtr;
126}
127
128
129/**
130 * Checks if any of the hardware breakpoints are armed.
131 *
132 * @returns true if armed, false if not.
133 * @param pVM The cross context VM structure.
134 * @remarks Don't call this from CPUMRecalcHyperDRx!
135 */
136VMM_INT_DECL(bool) DBGFBpIsHwArmed(PVM pVM)
137{
138 return pVM->dbgf.s.cEnabledHwBreakpoints > 0;
139}
140
141
142/**
143 * Checks if any of the hardware I/O breakpoints are armed.
144 *
145 * @returns true if armed, false if not.
146 * @param pVM The cross context VM structure.
147 * @remarks Don't call this from CPUMRecalcHyperDRx!
148 */
149VMM_INT_DECL(bool) DBGFBpIsHwIoArmed(PVM pVM)
150{
151 return pVM->dbgf.s.cEnabledHwIoBreakpoints > 0;
152}
153
154
155/**
156 * Checks if any INT3 breakpoints are armed.
157 *
158 * @returns true if armed, false if not.
159 * @param pVM The cross context VM structure.
160 * @remarks Don't call this from CPUMRecalcHyperDRx!
161 */
162VMM_INT_DECL(bool) DBGFBpIsInt3Armed(PVM pVM)
163{
164 return pVM->dbgf.s.cEnabledInt3Breakpoints > 0;
165}
166
167
168/**
169 * Checks I/O access for guest or hypervisor breakpoints.
170 *
171 * @returns Strict VBox status code
172 * @retval VINF_SUCCESS no breakpoint.
173 * @retval VINF_EM_DBG_BREAKPOINT hypervisor breakpoint triggered.
174 * @retval VINF_EM_RAW_GUEST_TRAP guest breakpoint triggered, DR6 and DR7 have
175 * been updated appropriately.
176 *
177 * @param pVM The cross context VM structure.
178 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
179 * @param pCtx The CPU context for the calling EMT.
180 * @param uIoPort The I/O port being accessed.
181 * @param cbValue The size/width of the access, in bytes.
182 */
183VMM_INT_DECL(VBOXSTRICTRC) DBGFBpCheckIo(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTIOPORT uIoPort, uint8_t cbValue)
184{
185 uint32_t const uIoPortFirst = uIoPort;
186 uint32_t const uIoPortLast = uIoPortFirst + cbValue - 1;
187
188
189 /*
190 * Check hyper breakpoints first as the VMM debugger has priority over
191 * the guest.
192 */
193 if (pVM->dbgf.s.cEnabledHwIoBreakpoints > 0)
194 {
195 for (unsigned iBp = 0; iBp < RT_ELEMENTS(pVM->dbgf.s.aHwBreakpoints); iBp++)
196 {
197 if ( pVM->dbgf.s.aHwBreakpoints[iBp].u.Reg.fType == X86_DR7_RW_IO
198 && pVM->dbgf.s.aHwBreakpoints[iBp].fEnabled
199 && pVM->dbgf.s.aHwBreakpoints[iBp].enmType == DBGFBPTYPE_REG )
200 {
201 uint8_t cbReg = pVM->dbgf.s.aHwBreakpoints[iBp].u.Reg.cb; Assert(RT_IS_POWER_OF_TWO(cbReg));
202 uint64_t uDrXFirst = pVM->dbgf.s.aHwBreakpoints[iBp].u.Reg.GCPtr & ~(uint64_t)(cbReg - 1);
203 uint64_t uDrXLast = uDrXFirst + cbReg - 1;
204 if (uDrXFirst <= uIoPortLast && uDrXLast >= uIoPortFirst)
205 {
206 /* (See also DBGFRZTrap01Handler.) */
207 pVCpu->dbgf.s.iActiveBp = pVM->dbgf.s.aHwBreakpoints[iBp].iBp;
208 pVCpu->dbgf.s.fSingleSteppingRaw = false;
209
210 LogFlow(("DBGFBpCheckIo: hit hw breakpoint %d at %04x:%RGv (iop %#x)\n",
211 pVM->dbgf.s.aHwBreakpoints[iBp].iBp, pCtx->cs.Sel, pCtx->rip, uIoPort));
212 return VINF_EM_DBG_BREAKPOINT;
213 }
214 }
215 }
216 }
217
218 /*
219 * Check the guest.
220 */
221 uint32_t const uDr7 = pCtx->dr[7];
222 if ( (uDr7 & X86_DR7_ENABLED_MASK)
223 && X86_DR7_ANY_RW_IO(uDr7)
224 && (pCtx->cr4 & X86_CR4_DE) )
225 {
226 for (unsigned iBp = 0; iBp < 4; iBp++)
227 {
228 if ( (uDr7 & X86_DR7_L_G(iBp))
229 && X86_DR7_GET_RW(uDr7, iBp) == X86_DR7_RW_IO)
230 {
231 /* ASSUME the breakpoint and the I/O width qualifier uses the same encoding (1 2 x 4). */
232 static uint8_t const s_abInvAlign[4] = { 0, 1, 7, 3 };
233 uint8_t cbInvAlign = s_abInvAlign[X86_DR7_GET_LEN(uDr7, iBp)];
234 uint64_t uDrXFirst = pCtx->dr[iBp] & ~(uint64_t)cbInvAlign;
235 uint64_t uDrXLast = uDrXFirst + cbInvAlign;
236
237 if (uDrXFirst <= uIoPortLast && uDrXLast >= uIoPortFirst)
238 {
239 /*
240 * Update DR6 and DR7.
241 *
242 * See "AMD64 Architecture Programmer's Manual Volume 2",
243 * chapter 13.1.1.3 for details on DR6 bits. The basics is
244 * that the B0..B3 bits are always cleared while the others
245 * must be cleared by software.
246 *
247 * The following sub chapters says the GD bit is always
248 * cleared when generating a #DB so the handler can safely
249 * access the debug registers.
250 */
251 pCtx->dr[6] &= ~X86_DR6_B_MASK;
252 pCtx->dr[6] |= X86_DR6_B(iBp);
253 pCtx->dr[7] &= ~X86_DR7_GD;
254 LogFlow(("DBGFBpCheckIo: hit hw breakpoint %d at %04x:%RGv (iop %#x)\n",
255 pVM->dbgf.s.aHwBreakpoints[iBp].iBp, pCtx->cs.Sel, pCtx->rip, uIoPort));
256 return VINF_EM_RAW_GUEST_TRAP;
257 }
258 }
259 }
260 }
261 return VINF_SUCCESS;
262}
263
264
265/**
266 * Returns the single stepping state for a virtual CPU.
267 *
268 * @returns stepping (true) or not (false).
269 *
270 * @param pVCpu The cross context virtual CPU structure.
271 */
272VMM_INT_DECL(bool) DBGFIsStepping(PVMCPU pVCpu)
273{
274 return pVCpu->dbgf.s.fSingleSteppingRaw;
275}
276
277
278/**
279 * Checks if the specified generic event is enabled or not.
280 *
281 * @returns true / false.
282 * @param pVM The cross context VM structure.
283 * @param enmEvent The generic event being raised.
284 * @param uEventArg The argument of that event.
285 */
286DECLINLINE(bool) dbgfEventIsGenericWithArgEnabled(PVM pVM, DBGFEVENTTYPE enmEvent, uint64_t uEventArg)
287{
288 if (DBGF_IS_EVENT_ENABLED(pVM, enmEvent))
289 {
290 switch (enmEvent)
291 {
292 case DBGFEVENT_INTERRUPT_HARDWARE:
293 AssertReturn(uEventArg < 256, false);
294 return ASMBitTest(pVM->dbgf.s.bmHardIntBreakpoints, (uint32_t)uEventArg);
295
296 case DBGFEVENT_INTERRUPT_SOFTWARE:
297 AssertReturn(uEventArg < 256, false);
298 return ASMBitTest(pVM->dbgf.s.bmSoftIntBreakpoints, (uint32_t)uEventArg);
299
300 default:
301 return true;
302
303 }
304 }
305 return false;
306}
307
308
309/**
310 * Raises a generic debug event if enabled and not being ignored.
311 *
312 * @returns Strict VBox status code.
313 * @retval VINF_EM_DBG_EVENT if the event was raised and the caller should
314 * return ASAP to the debugger (via EM). We set VMCPU_FF_DBGF so, it
315 * is okay not to pass this along in some situations .
316 * @retval VINF_SUCCESS if the event was disabled or ignored.
317 *
318 * @param pVM The cross context VM structure.
319 * @param pVCpu The cross context virtual CPU structure.
320 * @param enmEvent The generic event being raised.
321 * @param uEventArg The argument of that event.
322 * @param enmCtx The context in which this event is being raised.
323 *
324 * @thread EMT(pVCpu)
325 */
326VMM_INT_DECL(VBOXSTRICTRC) DBGFEventGenericWithArg(PVM pVM, PVMCPU pVCpu, DBGFEVENTTYPE enmEvent, uint64_t uEventArg,
327 DBGFEVENTCTX enmCtx)
328{
329 /*
330 * Is it enabled.
331 */
332 if (dbgfEventIsGenericWithArgEnabled(pVM, enmEvent, uEventArg))
333 {
334 /*
335 * Any events on the stack. Should the incoming event be ignored?
336 */
337 uint64_t const rip = CPUMGetGuestRIP(pVCpu);
338 uint32_t i = pVCpu->dbgf.s.cEvents;
339 if (i > 0)
340 {
341 while (i-- > 0)
342 {
343 if ( pVCpu->dbgf.s.aEvents[i].Event.enmType == enmEvent
344 && pVCpu->dbgf.s.aEvents[i].enmState == DBGFEVENTSTATE_IGNORE
345 && pVCpu->dbgf.s.aEvents[i].rip == rip)
346 {
347 pVCpu->dbgf.s.aEvents[i].enmState = DBGFEVENTSTATE_RESTORABLE;
348 return VINF_SUCCESS;
349 }
350 Assert(pVCpu->dbgf.s.aEvents[i].enmState != DBGFEVENTSTATE_CURRENT);
351 }
352
353 /*
354 * Trim the event stack.
355 */
356 i = pVCpu->dbgf.s.cEvents;
357 while (i-- > 0)
358 {
359 if ( pVCpu->dbgf.s.aEvents[i].rip == rip
360 && ( pVCpu->dbgf.s.aEvents[i].enmState == DBGFEVENTSTATE_RESTORABLE
361 || pVCpu->dbgf.s.aEvents[i].enmState == DBGFEVENTSTATE_IGNORE) )
362 pVCpu->dbgf.s.aEvents[i].enmState = DBGFEVENTSTATE_IGNORE;
363 else
364 {
365 if (i + 1 != pVCpu->dbgf.s.cEvents)
366 memmove(&pVCpu->dbgf.s.aEvents[i], &pVCpu->dbgf.s.aEvents[i + 1],
367 (pVCpu->dbgf.s.cEvents - i) * sizeof(pVCpu->dbgf.s.aEvents));
368 pVCpu->dbgf.s.cEvents--;
369 }
370 }
371
372 i = pVCpu->dbgf.s.cEvents;
373 AssertStmt(i < RT_ELEMENTS(pVCpu->dbgf.s.aEvents), i = RT_ELEMENTS(pVCpu->dbgf.s.aEvents) - 1);
374 }
375
376 /*
377 * Push the event.
378 */
379 pVCpu->dbgf.s.aEvents[i].enmState = DBGFEVENTSTATE_CURRENT;
380 pVCpu->dbgf.s.aEvents[i].rip = rip;
381 pVCpu->dbgf.s.aEvents[i].Event.enmType = enmEvent;
382 pVCpu->dbgf.s.aEvents[i].Event.enmCtx = enmCtx;
383 pVCpu->dbgf.s.aEvents[i].Event.u.Generic.uArg = uEventArg;
384 pVCpu->dbgf.s.cEvents = i + 1;
385
386 VMCPU_FF_SET(pVCpu, VMCPU_FF_DBGF);
387 return VINF_EM_DBG_EVENT;
388 }
389
390 return VINF_SUCCESS;
391}
392
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