VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/DBGFAll.cpp@ 78359

Last change on this file since 78359 was 76553, checked in by vboxsync, 6 years ago

scm --update-copyright-year
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 14.4 KB
Line 
1/* $Id: DBGFAll.cpp 76553 2019-01-01 01:45:53Z vboxsync $ */
2/** @file
3 * DBGF - Debugger Facility, All Context Code.
4 */
5
6/*
7 * Copyright (C) 2006-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DBGF
23#include <VBox/vmm/dbgf.h>
24#include "DBGFInternal.h"
25#include <VBox/vmm/vm.h>
26#include <VBox/err.h>
27#include <iprt/assert.h>
28#include <iprt/asm.h>
29#include <iprt/stdarg.h>
30
31
32/*
33 * Check the read-only VM members.
34 */
35AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.bmSoftIntBreakpoints, VM, dbgf.ro.bmSoftIntBreakpoints);
36AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.bmHardIntBreakpoints, VM, dbgf.ro.bmHardIntBreakpoints);
37AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.bmSelectedEvents, VM, dbgf.ro.bmSelectedEvents);
38AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.cHardIntBreakpoints, VM, dbgf.ro.cHardIntBreakpoints);
39AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.cSoftIntBreakpoints, VM, dbgf.ro.cSoftIntBreakpoints);
40AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.cSelectedEvents, VM, dbgf.ro.cSelectedEvents);
41
42
43/**
44 * Gets the hardware breakpoint configuration as DR7.
45 *
46 * @returns DR7 from the DBGF point of view.
47 * @param pVM The cross context VM structure.
48 */
49VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR7(PVM pVM)
50{
51 RTGCUINTREG uDr7 = X86_DR7_GD | X86_DR7_GE | X86_DR7_LE | X86_DR7_RA1_MASK;
52 PDBGFBP pBp = &pVM->dbgf.s.aHwBreakpoints[0];
53 unsigned cLeft = RT_ELEMENTS(pVM->dbgf.s.aHwBreakpoints);
54 while (cLeft-- > 0)
55 {
56 if ( pBp->enmType == DBGFBPTYPE_REG
57 && pBp->fEnabled)
58 {
59 static const uint8_t s_au8Sizes[8] =
60 {
61 X86_DR7_LEN_BYTE, X86_DR7_LEN_BYTE, X86_DR7_LEN_WORD, X86_DR7_LEN_BYTE,
62 X86_DR7_LEN_DWORD,X86_DR7_LEN_BYTE, X86_DR7_LEN_BYTE, X86_DR7_LEN_QWORD
63 };
64 uDr7 |= X86_DR7_G(pBp->u.Reg.iReg)
65 | X86_DR7_RW(pBp->u.Reg.iReg, pBp->u.Reg.fType)
66 | X86_DR7_LEN(pBp->u.Reg.iReg, s_au8Sizes[pBp->u.Reg.cb]);
67 }
68 pBp++;
69 }
70 return uDr7;
71}
72
73
74/**
75 * Gets the address of the hardware breakpoint number 0.
76 *
77 * @returns DR0 from the DBGF point of view.
78 * @param pVM The cross context VM structure.
79 */
80VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR0(PVM pVM)
81{
82 PCDBGFBP pBp = &pVM->dbgf.s.aHwBreakpoints[0];
83 Assert(pBp->u.Reg.iReg == 0);
84 return pBp->u.Reg.GCPtr;
85}
86
87
88/**
89 * Gets the address of the hardware breakpoint number 1.
90 *
91 * @returns DR1 from the DBGF point of view.
92 * @param pVM The cross context VM structure.
93 */
94VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR1(PVM pVM)
95{
96 PCDBGFBP pBp = &pVM->dbgf.s.aHwBreakpoints[1];
97 Assert(pBp->u.Reg.iReg == 1);
98 return pBp->u.Reg.GCPtr;
99}
100
101
102/**
103 * Gets the address of the hardware breakpoint number 2.
104 *
105 * @returns DR2 from the DBGF point of view.
106 * @param pVM The cross context VM structure.
107 */
108VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR2(PVM pVM)
109{
110 PCDBGFBP pBp = &pVM->dbgf.s.aHwBreakpoints[2];
111 Assert(pBp->u.Reg.iReg == 2);
112 return pBp->u.Reg.GCPtr;
113}
114
115
116/**
117 * Gets the address of the hardware breakpoint number 3.
118 *
119 * @returns DR3 from the DBGF point of view.
120 * @param pVM The cross context VM structure.
121 */
122VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR3(PVM pVM)
123{
124 PCDBGFBP pBp = &pVM->dbgf.s.aHwBreakpoints[3];
125 Assert(pBp->u.Reg.iReg == 3);
126 return pBp->u.Reg.GCPtr;
127}
128
129
130/**
131 * Checks if any of the hardware breakpoints are armed.
132 *
133 * @returns true if armed, false if not.
134 * @param pVM The cross context VM structure.
135 * @remarks Don't call this from CPUMRecalcHyperDRx!
136 */
137VMM_INT_DECL(bool) DBGFBpIsHwArmed(PVM pVM)
138{
139 return pVM->dbgf.s.cEnabledHwBreakpoints > 0;
140}
141
142
143/**
144 * Checks if any of the hardware I/O breakpoints are armed.
145 *
146 * @returns true if armed, false if not.
147 * @param pVM The cross context VM structure.
148 * @remarks Don't call this from CPUMRecalcHyperDRx!
149 */
150VMM_INT_DECL(bool) DBGFBpIsHwIoArmed(PVM pVM)
151{
152 return pVM->dbgf.s.cEnabledHwIoBreakpoints > 0;
153}
154
155
156/**
157 * Checks if any INT3 breakpoints are armed.
158 *
159 * @returns true if armed, false if not.
160 * @param pVM The cross context VM structure.
161 * @remarks Don't call this from CPUMRecalcHyperDRx!
162 */
163VMM_INT_DECL(bool) DBGFBpIsInt3Armed(PVM pVM)
164{
165 return pVM->dbgf.s.cEnabledInt3Breakpoints > 0;
166}
167
168
169/**
170 * Checks I/O access for guest or hypervisor breakpoints.
171 *
172 * @returns Strict VBox status code
173 * @retval VINF_SUCCESS no breakpoint.
174 * @retval VINF_EM_DBG_BREAKPOINT hypervisor breakpoint triggered.
175 * @retval VINF_EM_RAW_GUEST_TRAP guest breakpoint triggered, DR6 and DR7 have
176 * been updated appropriately.
177 *
178 * @param pVM The cross context VM structure.
179 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
180 * @param pCtx The CPU context for the calling EMT.
181 * @param uIoPort The I/O port being accessed.
182 * @param cbValue The size/width of the access, in bytes.
183 */
184VMM_INT_DECL(VBOXSTRICTRC) DBGFBpCheckIo(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTIOPORT uIoPort, uint8_t cbValue)
185{
186 uint32_t const uIoPortFirst = uIoPort;
187 uint32_t const uIoPortLast = uIoPortFirst + cbValue - 1;
188
189
190 /*
191 * Check hyper breakpoints first as the VMM debugger has priority over
192 * the guest.
193 */
194 if (pVM->dbgf.s.cEnabledHwIoBreakpoints > 0)
195 {
196 for (unsigned iBp = 0; iBp < RT_ELEMENTS(pVM->dbgf.s.aHwBreakpoints); iBp++)
197 {
198 if ( pVM->dbgf.s.aHwBreakpoints[iBp].u.Reg.fType == X86_DR7_RW_IO
199 && pVM->dbgf.s.aHwBreakpoints[iBp].fEnabled
200 && pVM->dbgf.s.aHwBreakpoints[iBp].enmType == DBGFBPTYPE_REG )
201 {
202 uint8_t cbReg = pVM->dbgf.s.aHwBreakpoints[iBp].u.Reg.cb; Assert(RT_IS_POWER_OF_TWO(cbReg));
203 uint64_t uDrXFirst = pVM->dbgf.s.aHwBreakpoints[iBp].u.Reg.GCPtr & ~(uint64_t)(cbReg - 1);
204 uint64_t uDrXLast = uDrXFirst + cbReg - 1;
205 if (uDrXFirst <= uIoPortLast && uDrXLast >= uIoPortFirst)
206 {
207 /* (See also DBGFRZTrap01Handler.) */
208 pVCpu->dbgf.s.iActiveBp = pVM->dbgf.s.aHwBreakpoints[iBp].iBp;
209 pVCpu->dbgf.s.fSingleSteppingRaw = false;
210
211 LogFlow(("DBGFBpCheckIo: hit hw breakpoint %d at %04x:%RGv (iop %#x)\n",
212 pVM->dbgf.s.aHwBreakpoints[iBp].iBp, pCtx->cs.Sel, pCtx->rip, uIoPort));
213 return VINF_EM_DBG_BREAKPOINT;
214 }
215 }
216 }
217 }
218
219 /*
220 * Check the guest.
221 */
222 uint32_t const uDr7 = pCtx->dr[7];
223 if ( (uDr7 & X86_DR7_ENABLED_MASK)
224 && X86_DR7_ANY_RW_IO(uDr7)
225 && (pCtx->cr4 & X86_CR4_DE) )
226 {
227 for (unsigned iBp = 0; iBp < 4; iBp++)
228 {
229 if ( (uDr7 & X86_DR7_L_G(iBp))
230 && X86_DR7_GET_RW(uDr7, iBp) == X86_DR7_RW_IO)
231 {
232 /* ASSUME the breakpoint and the I/O width qualifier uses the same encoding (1 2 x 4). */
233 static uint8_t const s_abInvAlign[4] = { 0, 1, 7, 3 };
234 uint8_t cbInvAlign = s_abInvAlign[X86_DR7_GET_LEN(uDr7, iBp)];
235 uint64_t uDrXFirst = pCtx->dr[iBp] & ~(uint64_t)cbInvAlign;
236 uint64_t uDrXLast = uDrXFirst + cbInvAlign;
237
238 if (uDrXFirst <= uIoPortLast && uDrXLast >= uIoPortFirst)
239 {
240 /*
241 * Update DR6 and DR7.
242 *
243 * See "AMD64 Architecture Programmer's Manual Volume 2",
244 * chapter 13.1.1.3 for details on DR6 bits. The basics is
245 * that the B0..B3 bits are always cleared while the others
246 * must be cleared by software.
247 *
248 * The following sub chapters says the GD bit is always
249 * cleared when generating a #DB so the handler can safely
250 * access the debug registers.
251 */
252 pCtx->dr[6] &= ~X86_DR6_B_MASK;
253 pCtx->dr[6] |= X86_DR6_B(iBp);
254 pCtx->dr[7] &= ~X86_DR7_GD;
255 LogFlow(("DBGFBpCheckIo: hit hw breakpoint %d at %04x:%RGv (iop %#x)\n",
256 pVM->dbgf.s.aHwBreakpoints[iBp].iBp, pCtx->cs.Sel, pCtx->rip, uIoPort));
257 return VINF_EM_RAW_GUEST_TRAP;
258 }
259 }
260 }
261 }
262 return VINF_SUCCESS;
263}
264
265
266/**
267 * Returns the single stepping state for a virtual CPU.
268 *
269 * @returns stepping (true) or not (false).
270 *
271 * @param pVCpu The cross context virtual CPU structure.
272 */
273VMM_INT_DECL(bool) DBGFIsStepping(PVMCPU pVCpu)
274{
275 return pVCpu->dbgf.s.fSingleSteppingRaw;
276}
277
278
279/**
280 * Checks if the specified generic event is enabled or not.
281 *
282 * @returns true / false.
283 * @param pVM The cross context VM structure.
284 * @param enmEvent The generic event being raised.
285 * @param uEventArg The argument of that event.
286 */
287DECLINLINE(bool) dbgfEventIsGenericWithArgEnabled(PVM pVM, DBGFEVENTTYPE enmEvent, uint64_t uEventArg)
288{
289 if (DBGF_IS_EVENT_ENABLED(pVM, enmEvent))
290 {
291 switch (enmEvent)
292 {
293 case DBGFEVENT_INTERRUPT_HARDWARE:
294 AssertReturn(uEventArg < 256, false);
295 return ASMBitTest(pVM->dbgf.s.bmHardIntBreakpoints, (uint32_t)uEventArg);
296
297 case DBGFEVENT_INTERRUPT_SOFTWARE:
298 AssertReturn(uEventArg < 256, false);
299 return ASMBitTest(pVM->dbgf.s.bmSoftIntBreakpoints, (uint32_t)uEventArg);
300
301 default:
302 return true;
303
304 }
305 }
306 return false;
307}
308
309
310/**
311 * Raises a generic debug event if enabled and not being ignored.
312 *
313 * @returns Strict VBox status code.
314 * @retval VINF_EM_DBG_EVENT if the event was raised and the caller should
315 * return ASAP to the debugger (via EM). We set VMCPU_FF_DBGF so, it
316 * is okay not to pass this along in some situations.
317 * @retval VINF_SUCCESS if the event was disabled or ignored.
318 *
319 * @param pVM The cross context VM structure.
320 * @param pVCpu The cross context virtual CPU structure.
321 * @param enmEvent The generic event being raised.
322 * @param enmCtx The context in which this event is being raised.
323 * @param cArgs Number of arguments (0 - 6).
324 * @param ... Event arguments.
325 *
326 * @thread EMT(pVCpu)
327 */
328VMM_INT_DECL(VBOXSTRICTRC) DBGFEventGenericWithArgs(PVM pVM, PVMCPU pVCpu, DBGFEVENTTYPE enmEvent, DBGFEVENTCTX enmCtx,
329 unsigned cArgs, ...)
330{
331 Assert(cArgs < RT_ELEMENTS(pVCpu->dbgf.s.aEvents[0].Event.u.Generic.auArgs));
332
333 /*
334 * Is it enabled.
335 */
336 va_list va;
337 va_start(va, cArgs);
338 uint64_t uEventArg0 = cArgs ? va_arg(va, uint64_t) : 0;
339 if (dbgfEventIsGenericWithArgEnabled(pVM, enmEvent, uEventArg0))
340 {
341 /*
342 * Any events on the stack. Should the incoming event be ignored?
343 */
344 uint64_t const rip = CPUMGetGuestRIP(pVCpu);
345 uint32_t i = pVCpu->dbgf.s.cEvents;
346 if (i > 0)
347 {
348 while (i-- > 0)
349 {
350 if ( pVCpu->dbgf.s.aEvents[i].Event.enmType == enmEvent
351 && pVCpu->dbgf.s.aEvents[i].enmState == DBGFEVENTSTATE_IGNORE
352 && pVCpu->dbgf.s.aEvents[i].rip == rip)
353 {
354 pVCpu->dbgf.s.aEvents[i].enmState = DBGFEVENTSTATE_RESTORABLE;
355 va_end(va);
356 return VINF_SUCCESS;
357 }
358 Assert(pVCpu->dbgf.s.aEvents[i].enmState != DBGFEVENTSTATE_CURRENT);
359 }
360
361 /*
362 * Trim the event stack.
363 */
364 i = pVCpu->dbgf.s.cEvents;
365 while (i-- > 0)
366 {
367 if ( pVCpu->dbgf.s.aEvents[i].rip == rip
368 && ( pVCpu->dbgf.s.aEvents[i].enmState == DBGFEVENTSTATE_RESTORABLE
369 || pVCpu->dbgf.s.aEvents[i].enmState == DBGFEVENTSTATE_IGNORE) )
370 pVCpu->dbgf.s.aEvents[i].enmState = DBGFEVENTSTATE_IGNORE;
371 else
372 {
373 if (i + 1 != pVCpu->dbgf.s.cEvents)
374 memmove(&pVCpu->dbgf.s.aEvents[i], &pVCpu->dbgf.s.aEvents[i + 1],
375 (pVCpu->dbgf.s.cEvents - i) * sizeof(pVCpu->dbgf.s.aEvents));
376 pVCpu->dbgf.s.cEvents--;
377 }
378 }
379
380 i = pVCpu->dbgf.s.cEvents;
381 AssertStmt(i < RT_ELEMENTS(pVCpu->dbgf.s.aEvents), i = RT_ELEMENTS(pVCpu->dbgf.s.aEvents) - 1);
382 }
383
384 /*
385 * Push the event.
386 */
387 pVCpu->dbgf.s.aEvents[i].enmState = DBGFEVENTSTATE_CURRENT;
388 pVCpu->dbgf.s.aEvents[i].rip = rip;
389 pVCpu->dbgf.s.aEvents[i].Event.enmType = enmEvent;
390 pVCpu->dbgf.s.aEvents[i].Event.enmCtx = enmCtx;
391 pVCpu->dbgf.s.aEvents[i].Event.u.Generic.cArgs = cArgs;
392 pVCpu->dbgf.s.aEvents[i].Event.u.Generic.auArgs[0] = uEventArg0;
393 if (cArgs > 1)
394 {
395 AssertStmt(cArgs < RT_ELEMENTS(pVCpu->dbgf.s.aEvents[i].Event.u.Generic.auArgs),
396 cArgs = RT_ELEMENTS(pVCpu->dbgf.s.aEvents[i].Event.u.Generic.auArgs));
397 for (unsigned iArg = 1; iArg < cArgs; iArg++)
398 pVCpu->dbgf.s.aEvents[i].Event.u.Generic.auArgs[iArg] = va_arg(va, uint64_t);
399 }
400 pVCpu->dbgf.s.cEvents = i + 1;
401
402 VMCPU_FF_SET(pVCpu, VMCPU_FF_DBGF);
403 va_end(va);
404 return VINF_EM_DBG_EVENT;
405 }
406
407 va_end(va);
408 return VINF_SUCCESS;
409}
410
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette