EMAll.cpp@ 54834

Last change on this file since 54834 was 54737, checked in by vboxsync, 10 years ago
VMM,REM: CPUID revamp - almost there now.
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1	/* $Id: EMAll.cpp 54737 2015-03-12 21:02:21Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor(/Manager) - All contexts
4	*/
5
6	/*
7	* Copyright (C) 2006-2014 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_EM
22	#include <VBox/vmm/em.h>
23	#include <VBox/vmm/mm.h>
24	#include <VBox/vmm/selm.h>
25	#include <VBox/vmm/patm.h>
26	#include <VBox/vmm/csam.h>
27	#include <VBox/vmm/pgm.h>
28	#ifdef VBOX_WITH_IEM
29	# include <VBox/vmm/iem.h>
30	#endif
31	#include <VBox/vmm/iom.h>
32	#include <VBox/vmm/stam.h>
33	#include "EMInternal.h"
34	#include <VBox/vmm/vm.h>
35	#include <VBox/vmm/vmm.h>
36	#include <VBox/vmm/hm.h>
37	#include <VBox/vmm/tm.h>
38	#include <VBox/vmm/pdmapi.h>
39	#include <VBox/param.h>
40	#include <VBox/err.h>
41	#include <VBox/dis.h>
42	#include <VBox/disopcode.h>
43	#include <VBox/log.h>
44	#include "internal/pgm.h"
45	#include <iprt/assert.h>
46	#include <iprt/asm.h>
47	#include <iprt/string.h>
48
49	#ifndef IN_RC
50	#undef VBOX_WITH_IEM
51	#endif
52	#ifdef VBOX_WITH_IEM
53	//# define VBOX_COMPARE_IEM_AND_EM /* debugging... */
54	//# define VBOX_SAME_AS_EM
55	//# define VBOX_COMPARE_IEM_LAST
56	#endif
57
58	#ifdef VBOX_WITH_RAW_RING1
59	# define EM_EMULATE_SMSW
60	#endif
61
62
63	/*******************************************************************************
64	* Defined Constants And Macros *
65	*******************************************************************************/
66	/** @def EM_ASSERT_FAULT_RETURN
67	* Safety check.
68	*
69	* Could in theory misfire on a cross page boundary access...
70	*
71	* Currently disabled because the CSAM (+ PATM) patch monitoring occasionally
72	* turns up an alias page instead of the original faulting one and annoying the
73	* heck out of anyone running a debug build. See @bugref{2609} and @bugref{1931}.
74	*/
75	#if 0
76	# define EM_ASSERT_FAULT_RETURN(expr, rc) AssertReturn(expr, rc)
77	#else
78	# define EM_ASSERT_FAULT_RETURN(expr, rc) do { } while (0)
79	#endif
80
81
82	/*******************************************************************************
83	* Internal Functions *
84	*******************************************************************************/
85	#if !defined(VBOX_WITH_IEM) \|\| defined(VBOX_COMPARE_IEM_AND_EM)
86	DECLINLINE(VBOXSTRICTRC) emInterpretInstructionCPUOuter(PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
87	RTGCPTR pvFault, EMCODETYPE enmCodeType, uint32_t *pcbSize);
88	#endif
89
90
91	/*******************************************************************************
92	* Global Variables *
93	*******************************************************************************/
94	#ifdef VBOX_COMPARE_IEM_AND_EM
95	static const uint32_t g_fInterestingFFs = VMCPU_FF_TO_R3
96	\| VMCPU_FF_CSAM_PENDING_ACTION \| VMCPU_FF_CSAM_SCAN_PAGE \| VMCPU_FF_INHIBIT_INTERRUPTS
97	\| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT
98	\| VMCPU_FF_TLB_FLUSH \| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL;
99	static uint32_t g_fIncomingFFs;
100	static CPUMCTX g_IncomingCtx;
101	static bool g_fIgnoreRaxRdx = false;
102
103	static uint32_t g_fEmFFs;
104	static CPUMCTX g_EmCtx;
105	static uint8_t g_abEmWrote[256];
106	static size_t g_cbEmWrote;
107
108	static uint32_t g_fIemFFs;
109	static CPUMCTX g_IemCtx;
110	extern uint8_t g_abIemWrote[256];
111	#if defined(VBOX_COMPARE_IEM_FIRST) \|\| defined(VBOX_COMPARE_IEM_LAST)
112	extern size_t g_cbIemWrote;
113	#else
114	static size_t g_cbIemWrote;
115	#endif
116	#endif
117
118
119	/**
120	* Get the current execution manager status.
121	*
122	* @returns Current status.
123	* @param pVCpu Pointer to the VMCPU.
124	*/
125	VMM_INT_DECL(EMSTATE) EMGetState(PVMCPU pVCpu)
126	{
127	return pVCpu->em.s.enmState;
128	}
129
130	/**
131	* Sets the current execution manager status. (use only when you know what you're doing!)
132	*
133	* @param pVCpu Pointer to the VMCPU.
134	*/
135	VMM_INT_DECL(void) EMSetState(PVMCPU pVCpu, EMSTATE enmNewState)
136	{
137	/* Only allowed combination: */
138	Assert(pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI && enmNewState == EMSTATE_HALTED);
139	pVCpu->em.s.enmState = enmNewState;
140	}
141
142
143	/**
144	* Sets the PC for which interrupts should be inhibited.
145	*
146	* @param pVCpu Pointer to the VMCPU.
147	* @param PC The PC.
148	*/
149	VMMDECL(void) EMSetInhibitInterruptsPC(PVMCPU pVCpu, RTGCUINTPTR PC)
150	{
151	pVCpu->em.s.GCPtrInhibitInterrupts = PC;
152	VMCPU_FF_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
153	}
154
155
156	/**
157	* Gets the PC for which interrupts should be inhibited.
158	*
159	* There are a few instructions which inhibits or delays interrupts
160	* for the instruction following them. These instructions are:
161	* - STI
162	* - MOV SS, r/m16
163	* - POP SS
164	*
165	* @returns The PC for which interrupts should be inhibited.
166	* @param pVCpu Pointer to the VMCPU.
167	*
168	*/
169	VMMDECL(RTGCUINTPTR) EMGetInhibitInterruptsPC(PVMCPU pVCpu)
170	{
171	return pVCpu->em.s.GCPtrInhibitInterrupts;
172	}
173
174
175	/**
176	* Prepare an MWAIT - essentials of the MONITOR instruction.
177	*
178	* @returns VINF_SUCCESS
179	* @param pVCpu The current CPU.
180	* @param rax The content of RAX.
181	* @param rcx The content of RCX.
182	* @param rdx The content of RDX.
183	* @param GCPhys The physical address corresponding to rax.
184	*/
185	VMM_INT_DECL(int) EMMonitorWaitPrepare(PVMCPU pVCpu, uint64_t rax, uint64_t rcx, uint64_t rdx, RTGCPHYS GCPhys)
186	{
187	pVCpu->em.s.MWait.uMonitorRAX = rax;
188	pVCpu->em.s.MWait.uMonitorRCX = rcx;
189	pVCpu->em.s.MWait.uMonitorRDX = rdx;
190	pVCpu->em.s.MWait.fWait \|= EMMWAIT_FLAG_MONITOR_ACTIVE;
191	/** @todo Make use of GCPhys. */
192	NOREF(GCPhys);
193	/** @todo Complete MONITOR implementation. */
194	return VINF_SUCCESS;
195	}
196
197
198	/**
199	* Performs an MWAIT.
200	*
201	* @returns VINF_SUCCESS
202	* @param pVCpu The current CPU.
203	* @param rax The content of RAX.
204	* @param rcx The content of RCX.
205	*/
206	VMM_INT_DECL(int) EMMonitorWaitPerform(PVMCPU pVCpu, uint64_t rax, uint64_t rcx)
207	{
208	pVCpu->em.s.MWait.uMWaitRAX = rax;
209	pVCpu->em.s.MWait.uMWaitRCX = rcx;
210	pVCpu->em.s.MWait.fWait \|= EMMWAIT_FLAG_ACTIVE;
211	if (rcx)
212	pVCpu->em.s.MWait.fWait \|= EMMWAIT_FLAG_BREAKIRQIF0;
213	else
214	pVCpu->em.s.MWait.fWait &= ~EMMWAIT_FLAG_BREAKIRQIF0;
215	/** @todo not completely correct?? */
216	return VINF_EM_HALT;
217	}
218
219
220
221	/**
222	* Determine if we should continue after encountering a mwait instruction.
223	*
224	* Clears MWAIT flags if returning @c true.
225	*
226	* @returns true if we should continue, false if we should halt.
227	* @param pVCpu Pointer to the VMCPU.
228	* @param pCtx Current CPU context.
229	*/
230	VMM_INT_DECL(bool) EMMonitorWaitShouldContinue(PVMCPU pVCpu, PCPUMCTX pCtx)
231	{
232	if ( pCtx->eflags.Bits.u1IF
233	\|\| ( (pVCpu->em.s.MWait.fWait & (EMMWAIT_FLAG_ACTIVE \| EMMWAIT_FLAG_BREAKIRQIF0))
234	== (EMMWAIT_FLAG_ACTIVE \| EMMWAIT_FLAG_BREAKIRQIF0)) )
235	{
236	if (VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)))
237	{
238	pVCpu->em.s.MWait.fWait &= ~(EMMWAIT_FLAG_ACTIVE \| EMMWAIT_FLAG_BREAKIRQIF0);
239	return true;
240	}
241	}
242
243	return false;
244	}
245
246
247	/**
248	* Determine if we should continue after encountering a hlt instruction.
249	*
250	* @returns true if we should continue, false if we should halt.
251	* @param pVCpu Pointer to the VMCPU.
252	* @param pCtx Current CPU context.
253	*/
254	VMM_INT_DECL(bool) EMShouldContinueAfterHalt(PVMCPU pVCpu, PCPUMCTX pCtx)
255	{
256	if (pCtx->eflags.Bits.u1IF)
257	return !!VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC));
258	return false;
259	}
260
261
262	/**
263	* Locks REM execution to a single VCPU.
264	*
265	* @param pVM Pointer to the VM.
266	*/
267	VMMDECL(void) EMRemLock(PVM pVM)
268	{
269	#ifdef VBOX_WITH_REM
270	if (!PDMCritSectIsInitialized(&pVM->em.s.CritSectREM))
271	return; /* early init */
272
273	Assert(!PGMIsLockOwner(pVM));
274	Assert(!IOMIsLockWriteOwner(pVM));
275	int rc = PDMCritSectEnter(&pVM->em.s.CritSectREM, VERR_SEM_BUSY);
276	AssertRCSuccess(rc);
277	#endif
278	}
279
280
281	/**
282	* Unlocks REM execution
283	*
284	* @param pVM Pointer to the VM.
285	*/
286	VMMDECL(void) EMRemUnlock(PVM pVM)
287	{
288	#ifdef VBOX_WITH_REM
289	if (!PDMCritSectIsInitialized(&pVM->em.s.CritSectREM))
290	return; /* early init */
291
292	PDMCritSectLeave(&pVM->em.s.CritSectREM);
293	#endif
294	}
295
296
297	/**
298	* Check if this VCPU currently owns the REM lock.
299	*
300	* @returns bool owner/not owner
301	* @param pVM Pointer to the VM.
302	*/
303	VMMDECL(bool) EMRemIsLockOwner(PVM pVM)
304	{
305	#ifdef VBOX_WITH_REM
306	if (!PDMCritSectIsInitialized(&pVM->em.s.CritSectREM))
307	return true; /* early init */
308
309	return PDMCritSectIsOwner(&pVM->em.s.CritSectREM);
310	#else
311	return true;
312	#endif
313	}
314
315
316	/**
317	* Try to acquire the REM lock.
318	*
319	* @returns VBox status code
320	* @param pVM Pointer to the VM.
321	*/
322	VMM_INT_DECL(int) EMRemTryLock(PVM pVM)
323	{
324	#ifdef VBOX_WITH_REM
325	if (!PDMCritSectIsInitialized(&pVM->em.s.CritSectREM))
326	return VINF_SUCCESS; /* early init */
327
328	return PDMCritSectTryEnter(&pVM->em.s.CritSectREM);
329	#else
330	return VINF_SUCCESS;
331	#endif
332	}
333
334
335	/**
336	* @callback_method_impl{FNDISREADBYTES}
337	*/
338	static DECLCALLBACK(int) emReadBytes(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
339	{
340	PVMCPU pVCpu = (PVMCPU)pDis->pvUser;
341	#if defined(IN_RC) \|\| defined(IN_RING3)
342	PVM pVM = pVCpu->CTX_SUFF(pVM);
343	#endif
344	RTUINTPTR uSrcAddr = pDis->uInstrAddr + offInstr;
345	int rc;
346
347	/*
348	* Figure how much we can or must read.
349	*/
350	size_t cbToRead = PAGE_SIZE - (uSrcAddr & PAGE_OFFSET_MASK);
351	if (cbToRead > cbMaxRead)
352	cbToRead = cbMaxRead;
353	else if (cbToRead < cbMinRead)
354	cbToRead = cbMinRead;
355
356	#if defined(VBOX_WITH_RAW_MODE) && (defined(IN_RC) \|\| defined(IN_RING3))
357	/*
358	* We might be called upon to interpret an instruction in a patch.
359	*/
360	if (PATMIsPatchGCAddr(pVCpu->CTX_SUFF(pVM), uSrcAddr))
361	{
362	# ifdef IN_RC
363	memcpy(&pDis->abInstr[offInstr], (void *)(uintptr_t)uSrcAddr, cbToRead);
364	# else
365	memcpy(&pDis->abInstr[offInstr], PATMR3GCPtrToHCPtr(pVCpu->CTX_SUFF(pVM), uSrcAddr), cbToRead);
366	# endif
367	rc = VINF_SUCCESS;
368	}
369	else
370	#endif
371	{
372	# ifdef IN_RC
373	/*
374	* Try access it thru the shadow page tables first. Fall back on the
375	* slower PGM method if it fails because the TLB or page table was
376	* modified recently.
377	*/
378	rc = MMGCRamRead(pVCpu->pVMRC, &pDis->abInstr[offInstr], (void *)(uintptr_t)uSrcAddr, cbToRead);
379	if (rc == VERR_ACCESS_DENIED && cbToRead > cbMinRead)
380	{
381	cbToRead = cbMinRead;
382	rc = MMGCRamRead(pVCpu->pVMRC, &pDis->abInstr[offInstr], (void *)(uintptr_t)uSrcAddr, cbToRead);
383	}
384	if (rc == VERR_ACCESS_DENIED)
385	#endif
386	{
387	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pDis->abInstr[offInstr], uSrcAddr, cbToRead);
388	if (RT_FAILURE(rc))
389	{
390	if (cbToRead > cbMinRead)
391	{
392	cbToRead = cbMinRead;
393	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pDis->abInstr[offInstr], uSrcAddr, cbToRead);
394	}
395	if (RT_FAILURE(rc))
396	{
397	#ifndef IN_RC
398	/*
399	* If we fail to find the page via the guest's page tables
400	* we invalidate the page in the host TLB (pertaining to
401	* the guest in the NestedPaging case). See @bugref{6043}.
402	*/
403	if (rc == VERR_PAGE_TABLE_NOT_PRESENT \|\| rc == VERR_PAGE_NOT_PRESENT)
404	{
405	HMInvalidatePage(pVCpu, uSrcAddr);
406	if (((uSrcAddr + cbToRead - 1) >> PAGE_SHIFT) != (uSrcAddr >> PAGE_SHIFT))
407	HMInvalidatePage(pVCpu, uSrcAddr + cbToRead - 1);
408	}
409	#endif
410	}
411	}
412	}
413	}
414
415	pDis->cbCachedInstr = offInstr + (uint8_t)cbToRead;
416	return rc;
417	}
418
419
420	DECLINLINE(int) emDisCoreOne(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, RTGCUINTPTR InstrGC, uint32_t *pOpsize)
421	{
422	NOREF(pVM);
423	return DISInstrWithReader(InstrGC, (DISCPUMODE)pDis->uCpuMode, emReadBytes, pVCpu, pDis, pOpsize);
424	}
425
426
427	/**
428	* Disassembles the current instruction.
429	*
430	* @returns VBox status code, see SELMToFlatEx and EMInterpretDisasOneEx for
431	* details.
432	*
433	* @param pVM Pointer to the VM.
434	* @param pVCpu Pointer to the VMCPU.
435	* @param pDis Where to return the parsed instruction info.
436	* @param pcbInstr Where to return the instruction size. (optional)
437	*/
438	VMM_INT_DECL(int) EMInterpretDisasCurrent(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, unsigned *pcbInstr)
439	{
440	PCPUMCTXCORE pCtxCore = CPUMCTX2CORE(CPUMQueryGuestCtxPtr(pVCpu));
441	RTGCPTR GCPtrInstr;
442	#if 0
443	int rc = SELMToFlatEx(pVCpu, DISSELREG_CS, pCtxCore, pCtxCore->rip, 0, &GCPtrInstr);
444	#else
445	/** @todo Get the CPU mode as well while we're at it! */
446	int rc = SELMValidateAndConvertCSAddr(pVCpu, pCtxCore->eflags, pCtxCore->ss.Sel, pCtxCore->cs.Sel, &pCtxCore->cs,
447	pCtxCore->rip, &GCPtrInstr);
448	#endif
449	if (RT_FAILURE(rc))
450	{
451	Log(("EMInterpretDisasOne: Failed to convert %RTsel:%RGv (cpl=%d) - rc=%Rrc !!\n",
452	pCtxCore->cs.Sel, (RTGCPTR)pCtxCore->rip, pCtxCore->ss.Sel & X86_SEL_RPL, rc));
453	return rc;
454	}
455	return EMInterpretDisasOneEx(pVM, pVCpu, (RTGCUINTPTR)GCPtrInstr, pCtxCore, pDis, pcbInstr);
456	}
457
458
459	/**
460	* Disassembles one instruction.
461	*
462	* This is used by internally by the interpreter and by trap/access handlers.
463	*
464	* @returns VBox status code.
465	*
466	* @param pVM Pointer to the VM.
467	* @param pVCpu Pointer to the VMCPU.
468	* @param GCPtrInstr The flat address of the instruction.
469	* @param pCtxCore The context core (used to determine the cpu mode).
470	* @param pDis Where to return the parsed instruction info.
471	* @param pcbInstr Where to return the instruction size. (optional)
472	*/
473	VMM_INT_DECL(int) EMInterpretDisasOneEx(PVM pVM, PVMCPU pVCpu, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore,
474	PDISCPUSTATE pDis, unsigned *pcbInstr)
475	{
476	NOREF(pVM);
477	Assert(pCtxCore == CPUMGetGuestCtxCore(pVCpu));
478	DISCPUMODE enmCpuMode = CPUMGetGuestDisMode(pVCpu);
479	/** @todo Deal with too long instruction (=> \#GP), opcode read errors (=>
480	* \#PF, \#GP, \#??), undefined opcodes (=> \#UD), and such. */
481	int rc = DISInstrWithReader(GCPtrInstr, enmCpuMode, emReadBytes, pVCpu, pDis, pcbInstr);
482	if (RT_SUCCESS(rc))
483	return VINF_SUCCESS;
484	AssertMsg(rc == VERR_PAGE_NOT_PRESENT \|\| rc == VERR_PAGE_TABLE_NOT_PRESENT, ("DISCoreOne failed to GCPtrInstr=%RGv rc=%Rrc\n", GCPtrInstr, rc));
485	return rc;
486	}
487
488
489	#if defined(VBOX_COMPARE_IEM_FIRST) \|\| defined(VBOX_COMPARE_IEM_LAST)
490	static void emCompareWithIem(PVMCPU pVCpu, PCCPUMCTX pEmCtx, PCCPUMCTX pIemCtx,
491	VBOXSTRICTRC rcEm, VBOXSTRICTRC rcIem,
492	uint32_t cbEm, uint32_t cbIem)
493	{
494	/* Quick compare. */
495	if ( rcEm == rcIem
496	&& cbEm == cbIem
497	&& g_cbEmWrote == g_cbIemWrote
498	&& memcmp(g_abIemWrote, g_abEmWrote, g_cbIemWrote) == 0
499	&& memcmp(pIemCtx, pEmCtx, sizeof(*pIemCtx)) == 0
500	&& (g_fEmFFs & g_fInterestingFFs) == (g_fIemFFs & g_fInterestingFFs)
501	)
502	return;
503
504	/* Report exact differences. */
505	RTLogPrintf("! EM and IEM differs at %04x:%08RGv !\n", g_IncomingCtx.cs.Sel, g_IncomingCtx.rip);
506	if (rcEm != rcIem)
507	RTLogPrintf(" * rcIem=%Rrc rcEm=%Rrc\n", VBOXSTRICTRC_VAL(rcIem), VBOXSTRICTRC_VAL(rcEm));
508	else if (cbEm != cbIem)
509	RTLogPrintf(" * cbIem=%#x cbEm=%#x\n", cbIem, cbEm);
510
511	if (RT_SUCCESS(rcEm) && RT_SUCCESS(rcIem))
512	{
513	if (g_cbIemWrote != g_cbEmWrote)
514	RTLogPrintf("!! g_cbIemWrote=%#x g_cbEmWrote=%#x\n", g_cbIemWrote, g_cbEmWrote);
515	else if (memcmp(g_abIemWrote, g_abEmWrote, g_cbIemWrote))
516	{
517	RTLogPrintf("!! IemWrote %.*Rhxs\n", RT_MIN(RT_MAX(1, g_cbIemWrote), 64), g_abIemWrote);
518	RTLogPrintf("!! EemWrote %.*Rhxs\n", RT_MIN(RT_MAX(1, g_cbIemWrote), 64), g_abIemWrote);
519	}
520
521	if ((g_fEmFFs & g_fInterestingFFs) != (g_fIemFFs & g_fInterestingFFs))
522	RTLogPrintf("!! g_fIemFFs=%#x g_fEmFFs=%#x (diff=%#x)\n", g_fIemFFs & g_fInterestingFFs,
523	g_fEmFFs & g_fInterestingFFs, (g_fIemFFs ^ g_fEmFFs) & g_fInterestingFFs);
524
525	# define CHECK_FIELD(a_Field) \
526	do \
527	{ \
528	if (pEmCtx->a_Field != pIemCtx->a_Field) \
529	{ \
530	switch (sizeof(pEmCtx->a_Field)) \
531	{ \
532	case 1: RTLogPrintf("!! %8s differs - iem=%02x - em=%02x\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); break; \
533	case 2: RTLogPrintf("!! %8s differs - iem=%04x - em=%04x\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); break; \
534	case 4: RTLogPrintf("!! %8s differs - iem=%08x - em=%08x\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); break; \
535	case 8: RTLogPrintf("!! %8s differs - iem=%016llx - em=%016llx\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); break; \
536	default: RTLogPrintf("!! %8s differs\n", #a_Field); break; \
537	} \
538	cDiffs++; \
539	} \
540	} while (0)
541
542	# define CHECK_BIT_FIELD(a_Field) \
543	do \
544	{ \
545	if (pEmCtx->a_Field != pIemCtx->a_Field) \
546	{ \
547	RTLogPrintf("!! %8s differs - iem=%02x - em=%02x\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); \
548	cDiffs++; \
549	} \
550	} while (0)
551
552	# define CHECK_SEL(a_Sel) \
553	do \
554	{ \
555	CHECK_FIELD(a_Sel.Sel); \
556	CHECK_FIELD(a_Sel.Attr.u); \
557	CHECK_FIELD(a_Sel.u64Base); \
558	CHECK_FIELD(a_Sel.u32Limit); \
559	CHECK_FIELD(a_Sel.fFlags); \
560	} while (0)
561
562	unsigned cDiffs = 0;
563	if (memcmp(&pEmCtx->fpu, &pIemCtx->fpu, sizeof(pIemCtx->fpu)))
564	{
565	RTLogPrintf(" the FPU state differs\n");
566	cDiffs++;
567	CHECK_FIELD(fpu.FCW);
568	CHECK_FIELD(fpu.FSW);
569	CHECK_FIELD(fpu.FTW);
570	CHECK_FIELD(fpu.FOP);
571	CHECK_FIELD(fpu.FPUIP);
572	CHECK_FIELD(fpu.CS);
573	CHECK_FIELD(fpu.Rsrvd1);
574	CHECK_FIELD(fpu.FPUDP);
575	CHECK_FIELD(fpu.DS);
576	CHECK_FIELD(fpu.Rsrvd2);
577	CHECK_FIELD(fpu.MXCSR);
578	CHECK_FIELD(fpu.MXCSR_MASK);
579	CHECK_FIELD(fpu.aRegs[0].au64[0]); CHECK_FIELD(fpu.aRegs[0].au64[1]);
580	CHECK_FIELD(fpu.aRegs[1].au64[0]); CHECK_FIELD(fpu.aRegs[1].au64[1]);
581	CHECK_FIELD(fpu.aRegs[2].au64[0]); CHECK_FIELD(fpu.aRegs[2].au64[1]);
582	CHECK_FIELD(fpu.aRegs[3].au64[0]); CHECK_FIELD(fpu.aRegs[3].au64[1]);
583	CHECK_FIELD(fpu.aRegs[4].au64[0]); CHECK_FIELD(fpu.aRegs[4].au64[1]);
584	CHECK_FIELD(fpu.aRegs[5].au64[0]); CHECK_FIELD(fpu.aRegs[5].au64[1]);
585	CHECK_FIELD(fpu.aRegs[6].au64[0]); CHECK_FIELD(fpu.aRegs[6].au64[1]);
586	CHECK_FIELD(fpu.aRegs[7].au64[0]); CHECK_FIELD(fpu.aRegs[7].au64[1]);
587	CHECK_FIELD(fpu.aXMM[ 0].au64[0]); CHECK_FIELD(fpu.aXMM[ 0].au64[1]);
588	CHECK_FIELD(fpu.aXMM[ 1].au64[0]); CHECK_FIELD(fpu.aXMM[ 1].au64[1]);
589	CHECK_FIELD(fpu.aXMM[ 2].au64[0]); CHECK_FIELD(fpu.aXMM[ 2].au64[1]);
590	CHECK_FIELD(fpu.aXMM[ 3].au64[0]); CHECK_FIELD(fpu.aXMM[ 3].au64[1]);
591	CHECK_FIELD(fpu.aXMM[ 4].au64[0]); CHECK_FIELD(fpu.aXMM[ 4].au64[1]);
592	CHECK_FIELD(fpu.aXMM[ 5].au64[0]); CHECK_FIELD(fpu.aXMM[ 5].au64[1]);
593	CHECK_FIELD(fpu.aXMM[ 6].au64[0]); CHECK_FIELD(fpu.aXMM[ 6].au64[1]);
594	CHECK_FIELD(fpu.aXMM[ 7].au64[0]); CHECK_FIELD(fpu.aXMM[ 7].au64[1]);
595	CHECK_FIELD(fpu.aXMM[ 8].au64[0]); CHECK_FIELD(fpu.aXMM[ 8].au64[1]);
596	CHECK_FIELD(fpu.aXMM[ 9].au64[0]); CHECK_FIELD(fpu.aXMM[ 9].au64[1]);
597	CHECK_FIELD(fpu.aXMM[10].au64[0]); CHECK_FIELD(fpu.aXMM[10].au64[1]);
598	CHECK_FIELD(fpu.aXMM[11].au64[0]); CHECK_FIELD(fpu.aXMM[11].au64[1]);
599	CHECK_FIELD(fpu.aXMM[12].au64[0]); CHECK_FIELD(fpu.aXMM[12].au64[1]);
600	CHECK_FIELD(fpu.aXMM[13].au64[0]); CHECK_FIELD(fpu.aXMM[13].au64[1]);
601	CHECK_FIELD(fpu.aXMM[14].au64[0]); CHECK_FIELD(fpu.aXMM[14].au64[1]);
602	CHECK_FIELD(fpu.aXMM[15].au64[0]); CHECK_FIELD(fpu.aXMM[15].au64[1]);
603	for (unsigned i = 0; i < RT_ELEMENTS(pEmCtx->fpu.au32RsrvdRest); i++)
604	CHECK_FIELD(fpu.au32RsrvdRest[i]);
605	}
606	CHECK_FIELD(rip);
607	if (pEmCtx->rflags.u != pIemCtx->rflags.u)
608	{
609	RTLogPrintf("!! rflags differs - iem=%08llx em=%08llx\n", pIemCtx->rflags.u, pEmCtx->rflags.u);
610	CHECK_BIT_FIELD(rflags.Bits.u1CF);
611	CHECK_BIT_FIELD(rflags.Bits.u1Reserved0);
612	CHECK_BIT_FIELD(rflags.Bits.u1PF);
613	CHECK_BIT_FIELD(rflags.Bits.u1Reserved1);
614	CHECK_BIT_FIELD(rflags.Bits.u1AF);
615	CHECK_BIT_FIELD(rflags.Bits.u1Reserved2);
616	CHECK_BIT_FIELD(rflags.Bits.u1ZF);
617	CHECK_BIT_FIELD(rflags.Bits.u1SF);
618	CHECK_BIT_FIELD(rflags.Bits.u1TF);
619	CHECK_BIT_FIELD(rflags.Bits.u1IF);
620	CHECK_BIT_FIELD(rflags.Bits.u1DF);
621	CHECK_BIT_FIELD(rflags.Bits.u1OF);
622	CHECK_BIT_FIELD(rflags.Bits.u2IOPL);
623	CHECK_BIT_FIELD(rflags.Bits.u1NT);
624	CHECK_BIT_FIELD(rflags.Bits.u1Reserved3);
625	CHECK_BIT_FIELD(rflags.Bits.u1RF);
626	CHECK_BIT_FIELD(rflags.Bits.u1VM);
627	CHECK_BIT_FIELD(rflags.Bits.u1AC);
628	CHECK_BIT_FIELD(rflags.Bits.u1VIF);
629	CHECK_BIT_FIELD(rflags.Bits.u1VIP);
630	CHECK_BIT_FIELD(rflags.Bits.u1ID);
631	}
632
633	if (!g_fIgnoreRaxRdx)
634	CHECK_FIELD(rax);
635	CHECK_FIELD(rcx);
636	if (!g_fIgnoreRaxRdx)
637	CHECK_FIELD(rdx);
638	CHECK_FIELD(rbx);
639	CHECK_FIELD(rsp);
640	CHECK_FIELD(rbp);
641	CHECK_FIELD(rsi);
642	CHECK_FIELD(rdi);
643	CHECK_FIELD(r8);
644	CHECK_FIELD(r9);
645	CHECK_FIELD(r10);
646	CHECK_FIELD(r11);
647	CHECK_FIELD(r12);
648	CHECK_FIELD(r13);
649	CHECK_SEL(cs);
650	CHECK_SEL(ss);
651	CHECK_SEL(ds);
652	CHECK_SEL(es);
653	CHECK_SEL(fs);
654	CHECK_SEL(gs);
655	CHECK_FIELD(cr0);
656	CHECK_FIELD(cr2);
657	CHECK_FIELD(cr3);
658	CHECK_FIELD(cr4);
659	CHECK_FIELD(dr[0]);
660	CHECK_FIELD(dr[1]);
661	CHECK_FIELD(dr[2]);
662	CHECK_FIELD(dr[3]);
663	CHECK_FIELD(dr[6]);
664	CHECK_FIELD(dr[7]);
665	CHECK_FIELD(gdtr.cbGdt);
666	CHECK_FIELD(gdtr.pGdt);
667	CHECK_FIELD(idtr.cbIdt);
668	CHECK_FIELD(idtr.pIdt);
669	CHECK_SEL(ldtr);
670	CHECK_SEL(tr);
671	CHECK_FIELD(SysEnter.cs);
672	CHECK_FIELD(SysEnter.eip);
673	CHECK_FIELD(SysEnter.esp);
674	CHECK_FIELD(msrEFER);
675	CHECK_FIELD(msrSTAR);
676	CHECK_FIELD(msrPAT);
677	CHECK_FIELD(msrLSTAR);
678	CHECK_FIELD(msrCSTAR);
679	CHECK_FIELD(msrSFMASK);
680	CHECK_FIELD(msrKERNELGSBASE);
681
682	# undef CHECK_FIELD
683	# undef CHECK_BIT_FIELD
684	}
685	}
686	#endif /* VBOX_COMPARE_IEM_AND_EM */
687
688
689	/**
690	* Interprets the current instruction.
691	*
692	* @returns VBox status code.
693	* @retval VINF_* Scheduling instructions.
694	* @retval VERR_EM_INTERPRETER Something we can't cope with.
695	* @retval VERR_* Fatal errors.
696	*
697	* @param pVCpu Pointer to the VMCPU.
698	* @param pRegFrame The register frame.
699	* Updates the EIP if an instruction was executed successfully.
700	* @param pvFault The fault address (CR2).
701	* @param pcbSize Size of the write (if applicable).
702	*
703	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
704	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
705	* to worry about e.g. invalid modrm combinations (!)
706	*/
707	VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstruction(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
708	{
709	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
710	LogFlow(("EMInterpretInstruction %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
711	#ifdef VBOX_WITH_IEM
712	NOREF(pvFault);
713
714	# ifdef VBOX_COMPARE_IEM_AND_EM
715	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
716	g_IncomingCtx = *pCtx;
717	g_fIncomingFFs = pVCpu->fLocalForcedActions;
718	g_cbEmWrote = g_cbIemWrote = 0;
719
720	# ifdef VBOX_COMPARE_IEM_FIRST
721	/* IEM */
722	VBOXSTRICTRC rcIem = IEMExecOneBypassEx(pVCpu, pRegFrame, NULL);
723	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
724	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
725	rcIem = VERR_EM_INTERPRETER;
726	g_IemCtx = *pCtx;
727	g_fIemFFs = pVCpu->fLocalForcedActions;
728	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
729	*pCtx = g_IncomingCtx;
730	# endif
731
732	/* EM */
733	RTGCPTR pbCode;
734	VBOXSTRICTRC rcEm = SELMToFlatEx(pVCpu, DISSELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
735	if (RT_SUCCESS(rcEm))
736	{
737	uint32_t cbOp;
738	PDISCPUSTATE pDis = &pVCpu->em.s.DisState;
739	pDis->uCpuMode = CPUMGetGuestDisMode(pVCpu);
740	rcEm = emDisCoreOne(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, (RTGCUINTPTR)pbCode, &cbOp);
741	if (RT_SUCCESS(rcEm))
742	{
743	Assert(cbOp == pDis->cbInstr);
744	uint32_t cbIgnored;
745	rcEm = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, &cbIgnored);
746	if (RT_SUCCESS(rcEm))
747	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
748
749	}
750	rcEm = VERR_EM_INTERPRETER;
751	}
752	else
753	rcEm = VERR_EM_INTERPRETER;
754	# ifdef VBOX_SAME_AS_EM
755	if (rcEm == VERR_EM_INTERPRETER)
756	{
757	Log(("EMInterpretInstruction: returns %Rrc\n", VBOXSTRICTRC_VAL(rcEm)));
758	return rcEm;
759	}
760	# endif
761	g_EmCtx = *pCtx;
762	g_fEmFFs = pVCpu->fLocalForcedActions;
763	VBOXSTRICTRC rc = rcEm;
764
765	# ifdef VBOX_COMPARE_IEM_LAST
766	/* IEM */
767	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
768	*pCtx = g_IncomingCtx;
769	VBOXSTRICTRC rcIem = IEMExecOneBypassEx(pVCpu, pRegFrame, NULL);
770	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
771	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
772	rcIem = VERR_EM_INTERPRETER;
773	g_IemCtx = *pCtx;
774	g_fIemFFs = pVCpu->fLocalForcedActions;
775	rc = rcIem;
776	# endif
777
778	# if defined(VBOX_COMPARE_IEM_LAST) \|\| defined(VBOX_COMPARE_IEM_FIRST)
779	emCompareWithIem(pVCpu, &g_EmCtx, &g_IemCtx, rcEm, rcIem, 0, 0);
780	# endif
781
782	# else
783	VBOXSTRICTRC rc = IEMExecOneBypassEx(pVCpu, pRegFrame, NULL);
784	if (RT_UNLIKELY( rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED
785	\|\| rc == VERR_IEM_INSTR_NOT_IMPLEMENTED))
786	rc = VERR_EM_INTERPRETER;
787	# endif
788	if (rc != VINF_SUCCESS)
789	Log(("EMInterpretInstruction: returns %Rrc\n", VBOXSTRICTRC_VAL(rc)));
790
791	return rc;
792	#else
793	RTGCPTR pbCode;
794	VBOXSTRICTRC rc = SELMToFlatEx(pVCpu, DISSELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
795	if (RT_SUCCESS(rc))
796	{
797	uint32_t cbOp;
798	PDISCPUSTATE pDis = &pVCpu->em.s.DisState;
799	pDis->uCpuMode = CPUMGetGuestDisMode(pVCpu);
800	rc = emDisCoreOne(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, (RTGCUINTPTR)pbCode, &cbOp);
801	if (RT_SUCCESS(rc))
802	{
803	Assert(cbOp == pDis->cbInstr);
804	uint32_t cbIgnored;
805	rc = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, &cbIgnored);
806	if (RT_SUCCESS(rc))
807	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
808
809	return rc;
810	}
811	}
812	return VERR_EM_INTERPRETER;
813	#endif
814	}
815
816
817	/**
818	* Interprets the current instruction.
819	*
820	* @returns VBox status code.
821	* @retval VINF_* Scheduling instructions.
822	* @retval VERR_EM_INTERPRETER Something we can't cope with.
823	* @retval VERR_* Fatal errors.
824	*
825	* @param pVM Pointer to the VM.
826	* @param pVCpu Pointer to the VMCPU.
827	* @param pRegFrame The register frame.
828	* Updates the EIP if an instruction was executed successfully.
829	* @param pvFault The fault address (CR2).
830	* @param pcbWritten Size of the write (if applicable).
831	*
832	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
833	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
834	* to worry about e.g. invalid modrm combinations (!)
835	*/
836	VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstructionEx(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbWritten)
837	{
838	LogFlow(("EMInterpretInstructionEx %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
839	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
840	#ifdef VBOX_WITH_IEM
841	NOREF(pvFault);
842
843	# ifdef VBOX_COMPARE_IEM_AND_EM
844	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
845	g_IncomingCtx = *pCtx;
846	g_fIncomingFFs = pVCpu->fLocalForcedActions;
847	g_cbEmWrote = g_cbIemWrote = 0;
848
849	# ifdef VBOX_COMPARE_IEM_FIRST
850	/* IEM */
851	uint32_t cbIemWritten = 0;
852	VBOXSTRICTRC rcIem = IEMExecOneBypassEx(pVCpu, pRegFrame, &cbIemWritten);
853	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
854	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
855	rcIem = VERR_EM_INTERPRETER;
856	g_IemCtx = *pCtx;
857	g_fIemFFs = pVCpu->fLocalForcedActions;
858	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
859	*pCtx = g_IncomingCtx;
860	# endif
861
862	/* EM */
863	uint32_t cbEmWritten = 0;
864	RTGCPTR pbCode;
865	VBOXSTRICTRC rcEm = SELMToFlatEx(pVCpu, DISSELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
866	if (RT_SUCCESS(rcEm))
867	{
868	uint32_t cbOp;
869	PDISCPUSTATE pDis = &pVCpu->em.s.DisState;
870	pDis->uCpuMode = CPUMGetGuestDisMode(pVCpu);
871	rcEm = emDisCoreOne(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, (RTGCUINTPTR)pbCode, &cbOp);
872	if (RT_SUCCESS(rcEm))
873	{
874	Assert(cbOp == pDis->cbInstr);
875	rcEm = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, &cbEmWritten);
876	if (RT_SUCCESS(rcEm))
877	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
878
879	}
880	else
881	rcEm = VERR_EM_INTERPRETER;
882	}
883	else
884	rcEm = VERR_EM_INTERPRETER;
885	# ifdef VBOX_SAME_AS_EM
886	if (rcEm == VERR_EM_INTERPRETER)
887	{
888	Log(("EMInterpretInstruction: returns %Rrc\n", VBOXSTRICTRC_VAL(rcEm)));
889	return rcEm;
890	}
891	# endif
892	g_EmCtx = *pCtx;
893	g_fEmFFs = pVCpu->fLocalForcedActions;
894	*pcbWritten = cbEmWritten;
895	VBOXSTRICTRC rc = rcEm;
896
897	# ifdef VBOX_COMPARE_IEM_LAST
898	/* IEM */
899	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
900	*pCtx = g_IncomingCtx;
901	uint32_t cbIemWritten = 0;
902	VBOXSTRICTRC rcIem = IEMExecOneBypassEx(pVCpu, pRegFrame, &cbIemWritten);
903	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
904	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
905	rcIem = VERR_EM_INTERPRETER;
906	g_IemCtx = *pCtx;
907	g_fIemFFs = pVCpu->fLocalForcedActions;
908	*pcbWritten = cbIemWritten;
909	rc = rcIem;
910	# endif
911
912	# if defined(VBOX_COMPARE_IEM_LAST) \|\| defined(VBOX_COMPARE_IEM_FIRST)
913	emCompareWithIem(pVCpu, &g_EmCtx, &g_IemCtx, rcEm, rcIem, cbEmWritten, cbIemWritten);
914	# endif
915
916	# else
917	VBOXSTRICTRC rc = IEMExecOneBypassEx(pVCpu, pRegFrame, pcbWritten);
918	if (RT_UNLIKELY( rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED
919	\|\| rc == VERR_IEM_INSTR_NOT_IMPLEMENTED))
920	rc = VERR_EM_INTERPRETER;
921	# endif
922	if (rc != VINF_SUCCESS)
923	Log(("EMInterpretInstructionEx: returns %Rrc\n", VBOXSTRICTRC_VAL(rc)));
924
925	return rc;
926	#else
927	RTGCPTR pbCode;
928	VBOXSTRICTRC rc = SELMToFlatEx(pVCpu, DISSELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
929	if (RT_SUCCESS(rc))
930	{
931	uint32_t cbOp;
932	PDISCPUSTATE pDis = &pVCpu->em.s.DisState;
933	pDis->uCpuMode = CPUMGetGuestDisMode(pVCpu);
934	rc = emDisCoreOne(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, (RTGCUINTPTR)pbCode, &cbOp);
935	if (RT_SUCCESS(rc))
936	{
937	Assert(cbOp == pDis->cbInstr);
938	rc = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, pcbWritten);
939	if (RT_SUCCESS(rc))
940	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
941
942	return rc;
943	}
944	}
945	return VERR_EM_INTERPRETER;
946	#endif
947	}
948
949
950	/**
951	* Interprets the current instruction using the supplied DISCPUSTATE structure.
952	*
953	* IP/EIP/RIP IS updated!
954	*
955	* @returns VBox strict status code.
956	* @retval VINF_* Scheduling instructions. When these are returned, it
957	* starts to get a bit tricky to know whether code was
958	* executed or not... We'll address this when it becomes a problem.
959	* @retval VERR_EM_INTERPRETER Something we can't cope with.
960	* @retval VERR_* Fatal errors.
961	*
962	* @param pVM Pointer to the VM.
963	* @param pVCpu Pointer to the VMCPU.
964	* @param pDis The disassembler cpu state for the instruction to be
965	* interpreted.
966	* @param pRegFrame The register frame. IP/EIP/RIP IS changed!
967	* @param pvFault The fault address (CR2).
968	* @param pcbSize Size of the write (if applicable).
969	* @param enmCodeType Code type (user/supervisor)
970	*
971	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
972	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
973	* to worry about e.g. invalid modrm combinations (!)
974	*
975	* @todo At this time we do NOT check if the instruction overwrites vital information.
976	* Make sure this can't happen!! (will add some assertions/checks later)
977	*/
978	VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstructionDisasState(PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
979	RTGCPTR pvFault, EMCODETYPE enmCodeType)
980	{
981	LogFlow(("EMInterpretInstructionDisasState %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
982	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
983	#ifdef VBOX_WITH_IEM
984	NOREF(pDis); NOREF(pvFault); NOREF(enmCodeType);
985
986	# ifdef VBOX_COMPARE_IEM_AND_EM
987	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
988	g_IncomingCtx = *pCtx;
989	g_fIncomingFFs = pVCpu->fLocalForcedActions;
990	g_cbEmWrote = g_cbIemWrote = 0;
991
992	# ifdef VBOX_COMPARE_IEM_FIRST
993	VBOXSTRICTRC rcIem = IEMExecOneBypassWithPrefetchedByPC(pVCpu, pRegFrame, pRegFrame->rip, pDis->abInstr, pDis->cbCachedInstr);
994	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
995	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
996	rcIem = VERR_EM_INTERPRETER;
997	g_IemCtx = *pCtx;
998	g_fIemFFs = pVCpu->fLocalForcedActions;
999	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
1000	*pCtx = g_IncomingCtx;
1001	# endif
1002
1003	/* EM */
1004	uint32_t cbIgnored;
1005	VBOXSTRICTRC rcEm = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, enmCodeType, &cbIgnored);
1006	if (RT_SUCCESS(rcEm))
1007	pRegFrame->rip += pDis->cbInstr; /* Move on to the next instruction. */
1008	# ifdef VBOX_SAME_AS_EM
1009	if (rcEm == VERR_EM_INTERPRETER)
1010	{
1011	Log(("EMInterpretInstruction: returns %Rrc\n", VBOXSTRICTRC_VAL(rcEm)));
1012	return rcEm;
1013	}
1014	# endif
1015	g_EmCtx = *pCtx;
1016	g_fEmFFs = pVCpu->fLocalForcedActions;
1017	VBOXSTRICTRC rc = rcEm;
1018
1019	# ifdef VBOX_COMPARE_IEM_LAST
1020	/* IEM */
1021	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
1022	*pCtx = g_IncomingCtx;
1023	VBOXSTRICTRC rcIem = IEMExecOneBypassWithPrefetchedByPC(pVCpu, pRegFrame, pRegFrame->rip, pDis->abInstr, pDis->cbCachedInstr);
1024	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
1025	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
1026	rcIem = VERR_EM_INTERPRETER;
1027	g_IemCtx = *pCtx;
1028	g_fIemFFs = pVCpu->fLocalForcedActions;
1029	rc = rcIem;
1030	# endif
1031
1032	# if defined(VBOX_COMPARE_IEM_LAST) \|\| defined(VBOX_COMPARE_IEM_FIRST)
1033	emCompareWithIem(pVCpu, &g_EmCtx, &g_IemCtx, rcEm, rcIem, 0, 0);
1034	# endif
1035
1036	# else
1037	VBOXSTRICTRC rc = IEMExecOneBypassWithPrefetchedByPC(pVCpu, pRegFrame, pRegFrame->rip, pDis->abInstr, pDis->cbCachedInstr);
1038	if (RT_UNLIKELY( rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED
1039	\|\| rc == VERR_IEM_INSTR_NOT_IMPLEMENTED))
1040	rc = VERR_EM_INTERPRETER;
1041	# endif
1042
1043	if (rc != VINF_SUCCESS)
1044	Log(("EMInterpretInstructionDisasState: returns %Rrc\n", VBOXSTRICTRC_VAL(rc)));
1045
1046	return rc;
1047	#else
1048	uint32_t cbIgnored;
1049	VBOXSTRICTRC rc = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, enmCodeType, &cbIgnored);
1050	if (RT_SUCCESS(rc))
1051	pRegFrame->rip += pDis->cbInstr; /* Move on to the next instruction. */
1052	return rc;
1053	#endif
1054	}
1055
1056	#ifdef IN_RC
1057
1058	DECLINLINE(int) emRCStackRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCPTR GCPtrSrc, uint32_t cb)
1059	{
1060	int rc = MMGCRamRead(pVM, pvDst, (void *)(uintptr_t)GCPtrSrc, cb);
1061	if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
1062	return rc;
1063	return PGMPhysInterpretedReadNoHandlers(pVCpu, pCtxCore, pvDst, GCPtrSrc, cb, /fMayTrap/ false);
1064	}
1065
1066
1067	/**
1068	* Interpret IRET (currently only to V86 code) - PATM only.
1069	*
1070	* @returns VBox status code.
1071	* @param pVM Pointer to the VM.
1072	* @param pVCpu Pointer to the VMCPU.
1073	* @param pRegFrame The register frame.
1074	*
1075	*/
1076	VMM_INT_DECL(int) EMInterpretIretV86ForPatm(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1077	{
1078	RTGCUINTPTR pIretStack = (RTGCUINTPTR)pRegFrame->esp;
1079	RTGCUINTPTR eip, cs, esp, ss, eflags, ds, es, fs, gs, uMask;
1080	int rc;
1081
1082	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1083	Assert(!CPUMIsGuestIn64BitCode(pVCpu));
1084	/** @todo Rainy day: Test what happens when VERR_EM_INTERPRETER is returned by
1085	* this function. Fear that it may guru on us, thus not converted to
1086	* IEM. */
1087
1088	rc = emRCStackRead(pVM, pVCpu, pRegFrame, &eip, (RTGCPTR)pIretStack , 4);
1089	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &cs, (RTGCPTR)(pIretStack + 4), 4);
1090	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &eflags, (RTGCPTR)(pIretStack + 8), 4);
1091	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1092	AssertReturn(eflags & X86_EFL_VM, VERR_EM_INTERPRETER);
1093
1094	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &esp, (RTGCPTR)(pIretStack + 12), 4);
1095	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &ss, (RTGCPTR)(pIretStack + 16), 4);
1096	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &es, (RTGCPTR)(pIretStack + 20), 4);
1097	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &ds, (RTGCPTR)(pIretStack + 24), 4);
1098	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &fs, (RTGCPTR)(pIretStack + 28), 4);
1099	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &gs, (RTGCPTR)(pIretStack + 32), 4);
1100	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1101
1102	pRegFrame->eip = eip & 0xffff;
1103	pRegFrame->cs.Sel = cs;
1104
1105	/* Mask away all reserved bits */
1106	uMask = X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_RF \| X86_EFL_VM \| X86_EFL_AC \| X86_EFL_VIF \| X86_EFL_VIP \| X86_EFL_ID;
1107	eflags &= uMask;
1108
1109	CPUMRawSetEFlags(pVCpu, eflags);
1110	Assert((pRegFrame->eflags.u32 & (X86_EFL_IF\|X86_EFL_IOPL)) == X86_EFL_IF);
1111
1112	pRegFrame->esp = esp;
1113	pRegFrame->ss.Sel = ss;
1114	pRegFrame->ds.Sel = ds;
1115	pRegFrame->es.Sel = es;
1116	pRegFrame->fs.Sel = fs;
1117	pRegFrame->gs.Sel = gs;
1118
1119	return VINF_SUCCESS;
1120	}
1121
1122	/**
1123	* IRET Emulation.
1124	*/
1125	static int emInterpretIret(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1126	{
1127	#ifdef VBOX_WITH_RAW_RING1
1128	NOREF(pvFault); NOREF(pcbSize);
1129	if (EMIsRawRing1Enabled(pVM))
1130	{
1131	RTGCUINTPTR pIretStack = (RTGCUINTPTR)pRegFrame->esp;
1132	RTGCUINTPTR eip, cs, esp, ss, eflags, uMask;
1133	int rc;
1134	uint32_t cpl, rpl;
1135
1136	/* We only execute 32-bits protected mode code in raw mode, so no need to bother to check for 16-bits code here. */
1137	/* @todo: we don't verify all the edge cases that generate #GP faults */
1138
1139	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1140	Assert(!CPUMIsGuestIn64BitCode(pVCpu));
1141	/** @todo Rainy day: Test what happens when VERR_EM_INTERPRETER is returned by
1142	* this function. Fear that it may guru on us, thus not converted to
1143	* IEM. */
1144
1145	rc = emRCStackRead(pVM, pVCpu, pRegFrame, &eip, (RTGCPTR)pIretStack , 4);
1146	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &cs, (RTGCPTR)(pIretStack + 4), 4);
1147	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &eflags, (RTGCPTR)(pIretStack + 8), 4);
1148	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1149	AssertReturn(eflags & X86_EFL_VM, VERR_EM_INTERPRETER);
1150
1151	/* Deal with V86 above. */
1152	if (eflags & X86_EFL_VM)
1153	return EMInterpretIretV86ForPatm(pVM, pVCpu, pRegFrame);
1154
1155	cpl = CPUMRCGetGuestCPL(pVCpu, pRegFrame);
1156	rpl = cs & X86_SEL_RPL;
1157
1158	Log(("emInterpretIret: iret to CS:EIP=%04X:%08X eflags=%x\n", cs, eip, eflags));
1159	if (rpl != cpl)
1160	{
1161	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &esp, (RTGCPTR)(pIretStack + 12), 4);
1162	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &ss, (RTGCPTR)(pIretStack + 16), 4);
1163	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1164	Log(("emInterpretIret: return to different privilege level (rpl=%d cpl=%d)\n", rpl, cpl));
1165	Log(("emInterpretIret: SS:ESP=%04X:08X\n", ss, esp));
1166	pRegFrame->ss.Sel = ss;
1167	pRegFrame->esp = esp;
1168	}
1169	pRegFrame->cs.Sel = cs;
1170	pRegFrame->eip = eip;
1171
1172	/* Adjust CS & SS as required. */
1173	CPUMRCRecheckRawState(pVCpu, pRegFrame);
1174
1175	/* Mask away all reserved bits */
1176	uMask = X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_RF \| X86_EFL_VM \| X86_EFL_AC \| X86_EFL_VIF \| X86_EFL_VIP \| X86_EFL_ID;
1177	eflags &= uMask;
1178
1179	CPUMRawSetEFlags(pVCpu, eflags);
1180	Assert((pRegFrame->eflags.u32 & (X86_EFL_IF\|X86_EFL_IOPL)) == X86_EFL_IF);
1181	return VINF_SUCCESS;
1182	}
1183	#else
1184	NOREF(pVM); NOREF(pVCpu); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
1185	#endif
1186	return VERR_EM_INTERPRETER;
1187	}
1188
1189	#endif /* IN_RC */
1190
1191
1192
1193	/*
1194	*
1195	* Old interpreter primitives used by HM, move/eliminate later.
1196	* Old interpreter primitives used by HM, move/eliminate later.
1197	* Old interpreter primitives used by HM, move/eliminate later.
1198	* Old interpreter primitives used by HM, move/eliminate later.
1199	* Old interpreter primitives used by HM, move/eliminate later.
1200	*
1201	*/
1202
1203
1204	/**
1205	* Interpret CPUID given the parameters in the CPU context.
1206	*
1207	* @returns VBox status code.
1208	* @param pVM Pointer to the VM.
1209	* @param pVCpu Pointer to the VMCPU.
1210	* @param pRegFrame The register frame.
1211	*
1212	*/
1213	VMM_INT_DECL(int) EMInterpretCpuId(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1214	{
1215	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1216	uint32_t iLeaf = pRegFrame->eax;
1217	uint32_t iSubLeaf = pRegFrame->ecx;
1218	NOREF(pVM);
1219
1220	/* cpuid clears the high dwords of the affected 64 bits registers. */
1221	pRegFrame->rax = 0;
1222	pRegFrame->rbx = 0;
1223	pRegFrame->rcx = 0;
1224	pRegFrame->rdx = 0;
1225
1226	/* Note: operates the same in 64 and non-64 bits mode. */
1227	CPUMGetGuestCpuId(pVCpu, iLeaf, iSubLeaf, &pRegFrame->eax, &pRegFrame->ebx, &pRegFrame->ecx, &pRegFrame->edx);
1228	Log(("Emulate: CPUID %x -> %08x %08x %08x %08x\n", iLeaf, pRegFrame->eax, pRegFrame->ebx, pRegFrame->ecx, pRegFrame->edx));
1229	return VINF_SUCCESS;
1230	}
1231
1232
1233	/**
1234	* Interpret RDTSC.
1235	*
1236	* @returns VBox status code.
1237	* @param pVM Pointer to the VM.
1238	* @param pVCpu Pointer to the VMCPU.
1239	* @param pRegFrame The register frame.
1240	*
1241	*/
1242	VMM_INT_DECL(int) EMInterpretRdtsc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1243	{
1244	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1245	unsigned uCR4 = CPUMGetGuestCR4(pVCpu);
1246
1247	if (uCR4 & X86_CR4_TSD)
1248	return VERR_EM_INTERPRETER; /* genuine #GP */
1249
1250	uint64_t uTicks = TMCpuTickGet(pVCpu);
1251
1252	/* Same behaviour in 32 & 64 bits mode */
1253	pRegFrame->rax = (uint32_t)uTicks;
1254	pRegFrame->rdx = (uTicks >> 32ULL);
1255	#ifdef VBOX_COMPARE_IEM_AND_EM
1256	g_fIgnoreRaxRdx = true;
1257	#endif
1258
1259	NOREF(pVM);
1260	return VINF_SUCCESS;
1261	}
1262
1263	/**
1264	* Interpret RDTSCP.
1265	*
1266	* @returns VBox status code.
1267	* @param pVM Pointer to the VM.
1268	* @param pVCpu Pointer to the VMCPU.
1269	* @param pCtx The CPU context.
1270	*
1271	*/
1272	VMM_INT_DECL(int) EMInterpretRdtscp(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1273	{
1274	Assert(pCtx == CPUMQueryGuestCtxPtr(pVCpu));
1275	uint32_t uCR4 = CPUMGetGuestCR4(pVCpu);
1276
1277	if (!CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1278	{
1279	AssertFailed();
1280	return VERR_EM_INTERPRETER; /* genuine #UD */
1281	}
1282
1283	if (uCR4 & X86_CR4_TSD)
1284	return VERR_EM_INTERPRETER; /* genuine #GP */
1285
1286	uint64_t uTicks = TMCpuTickGet(pVCpu);
1287
1288	/* Same behaviour in 32 & 64 bits mode */
1289	pCtx->rax = (uint32_t)uTicks;
1290	pCtx->rdx = (uTicks >> 32ULL);
1291	#ifdef VBOX_COMPARE_IEM_AND_EM
1292	g_fIgnoreRaxRdx = true;
1293	#endif
1294	/* Low dword of the TSC_AUX msr only. */
1295	VBOXSTRICTRC rc2 = CPUMQueryGuestMsr(pVCpu, MSR_K8_TSC_AUX, &pCtx->rcx); Assert(rc2 == VINF_SUCCESS);
1296	pCtx->rcx &= UINT32_C(0xffffffff);
1297
1298	return VINF_SUCCESS;
1299	}
1300
1301	/**
1302	* Interpret RDPMC.
1303	*
1304	* @returns VBox status code.
1305	* @param pVM Pointer to the VM.
1306	* @param pVCpu Pointer to the VMCPU.
1307	* @param pRegFrame The register frame.
1308	*
1309	*/
1310	VMM_INT_DECL(int) EMInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1311	{
1312	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1313	uint32_t uCR4 = CPUMGetGuestCR4(pVCpu);
1314
1315	/* If X86_CR4_PCE is not set, then CPL must be zero. */
1316	if ( !(uCR4 & X86_CR4_PCE)
1317	&& CPUMGetGuestCPL(pVCpu) != 0)
1318	{
1319	Assert(CPUMGetGuestCR0(pVCpu) & X86_CR0_PE);
1320	return VERR_EM_INTERPRETER; /* genuine #GP */
1321	}
1322
1323	/* Just return zero here; rather tricky to properly emulate this, especially as the specs are a mess. */
1324	pRegFrame->rax = 0;
1325	pRegFrame->rdx = 0;
1326	/** @todo We should trigger a #GP here if the CPU doesn't support the index in ecx
1327	* but see @bugref{3472}! */
1328
1329	NOREF(pVM);
1330	return VINF_SUCCESS;
1331	}
1332
1333
1334	/**
1335	* MWAIT Emulation.
1336	*/
1337	VMM_INT_DECL(VBOXSTRICTRC) EMInterpretMWait(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1338	{
1339	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1340	uint32_t u32Dummy, u32ExtFeatures, cpl, u32MWaitFeatures;
1341	NOREF(pVM);
1342
1343	/* Get the current privilege level. */
1344	cpl = CPUMGetGuestCPL(pVCpu);
1345	if (cpl != 0)
1346	return VERR_EM_INTERPRETER; /* supervisor only */
1347
1348	CPUMGetGuestCpuId(pVCpu, 1, 0, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
1349	if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
1350	return VERR_EM_INTERPRETER; /* not supported */
1351
1352	/*
1353	* CPUID.05H.ECX[0] defines support for power management extensions (eax)
1354	* CPUID.05H.ECX[1] defines support for interrupts as break events for mwait even when IF=0
1355	*/
1356	CPUMGetGuestCpuId(pVCpu, 5, 0, &u32Dummy, &u32Dummy, &u32MWaitFeatures, &u32Dummy);
1357	if (pRegFrame->ecx > 1)
1358	{
1359	Log(("EMInterpretMWait: unexpected ecx value %x -> recompiler\n", pRegFrame->ecx));
1360	return VERR_EM_INTERPRETER; /* illegal value. */
1361	}
1362
1363	if (pRegFrame->ecx && !(u32MWaitFeatures & X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1364	{
1365	Log(("EMInterpretMWait: unsupported X86_CPUID_MWAIT_ECX_BREAKIRQIF0 -> recompiler\n"));
1366	return VERR_EM_INTERPRETER; /* illegal value. */
1367	}
1368
1369	return EMMonitorWaitPerform(pVCpu, pRegFrame->rax, pRegFrame->rcx);
1370	}
1371
1372
1373	/**
1374	* MONITOR Emulation.
1375	*/
1376	VMM_INT_DECL(int) EMInterpretMonitor(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1377	{
1378	uint32_t u32Dummy, u32ExtFeatures, cpl;
1379	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1380	NOREF(pVM);
1381
1382	if (pRegFrame->ecx != 0)
1383	{
1384	Log(("emInterpretMonitor: unexpected ecx=%x -> recompiler!!\n", pRegFrame->ecx));
1385	return VERR_EM_INTERPRETER; /* illegal value. */
1386	}
1387
1388	/* Get the current privilege level. */
1389	cpl = CPUMGetGuestCPL(pVCpu);
1390	if (cpl != 0)
1391	return VERR_EM_INTERPRETER; /* supervisor only */
1392
1393	CPUMGetGuestCpuId(pVCpu, 1, 0, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
1394	if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
1395	return VERR_EM_INTERPRETER; /* not supported */
1396
1397	EMMonitorWaitPrepare(pVCpu, pRegFrame->rax, pRegFrame->rcx, pRegFrame->rdx, NIL_RTGCPHYS);
1398	return VINF_SUCCESS;
1399	}
1400
1401
1402	/* VT-x only: */
1403
1404	/**
1405	* Interpret INVLPG.
1406	*
1407	* @returns VBox status code.
1408	* @param pVM Pointer to the VM.
1409	* @param pVCpu Pointer to the VMCPU.
1410	* @param pRegFrame The register frame.
1411	* @param pAddrGC Operand address.
1412	*
1413	*/
1414	VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC)
1415	{
1416	/** @todo is addr always a flat linear address or ds based
1417	* (in absence of segment override prefixes)????
1418	*/
1419	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1420	NOREF(pVM); NOREF(pRegFrame);
1421	#ifdef IN_RC
1422	LogFlow(("RC: EMULATE: invlpg %RGv\n", pAddrGC));
1423	#endif
1424	VBOXSTRICTRC rc = PGMInvalidatePage(pVCpu, pAddrGC);
1425	if ( rc == VINF_SUCCESS
1426	\|\| rc == VINF_PGM_SYNC_CR3 /* we can rely on the FF */)
1427	return VINF_SUCCESS;
1428	AssertMsgReturn(rc == VINF_EM_RAW_EMULATE_INSTR,
1429	("%Rrc addr=%RGv\n", VBOXSTRICTRC_VAL(rc), pAddrGC),
1430	VERR_EM_INTERPRETER);
1431	return rc;
1432	}
1433
1434
1435	/**
1436	* Update CRx.
1437	*
1438	* @returns VBox status code.
1439	* @param pVM Pointer to the VM.
1440	* @param pVCpu Pointer to the VMCPU.
1441	* @param pRegFrame The register frame.
1442	* @param DestRegCRx CRx register index (DISUSE_REG_CR*)
1443	* @param val New CRx value
1444	*
1445	*/
1446	static int emUpdateCRx(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint64_t val)
1447	{
1448	uint64_t oldval;
1449	uint64_t msrEFER;
1450	uint32_t fValid;
1451	int rc, rc2;
1452	NOREF(pVM);
1453
1454	/** @todo Clean up this mess. */
1455	LogFlow(("EMInterpretCRxWrite at %RGv CR%d <- %RX64\n", (RTGCPTR)pRegFrame->rip, DestRegCrx, val));
1456	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1457	switch (DestRegCrx)
1458	{
1459	case DISCREG_CR0:
1460	oldval = CPUMGetGuestCR0(pVCpu);
1461	#ifdef IN_RC
1462	/* CR0.WP and CR0.AM changes require a reschedule run in ring 3. */
1463	if ( (val & (X86_CR0_WP \| X86_CR0_AM))
1464	!= (oldval & (X86_CR0_WP \| X86_CR0_AM)))
1465	return VERR_EM_INTERPRETER;
1466	#endif
1467	rc = VINF_SUCCESS;
1468	#if !defined(VBOX_COMPARE_IEM_AND_EM) \|\| !defined(VBOX_COMPARE_IEM_LAST)
1469	CPUMSetGuestCR0(pVCpu, val);
1470	#else
1471	CPUMQueryGuestCtxPtr(pVCpu)->cr0 = val \| X86_CR0_ET;
1472	#endif
1473	val = CPUMGetGuestCR0(pVCpu);
1474	if ( (oldval & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE))
1475	!= (val & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE)))
1476	{
1477	/* global flush */
1478	rc = PGMFlushTLB(pVCpu, CPUMGetGuestCR3(pVCpu), true /* global */);
1479	AssertRCReturn(rc, rc);
1480	}
1481
1482	/* Deal with long mode enabling/disabling. */
1483	msrEFER = CPUMGetGuestEFER(pVCpu);
1484	if (msrEFER & MSR_K6_EFER_LME)
1485	{
1486	if ( !(oldval & X86_CR0_PG)
1487	&& (val & X86_CR0_PG))
1488	{
1489	/* Illegal to have an active 64 bits CS selector (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1490	if (pRegFrame->cs.Attr.n.u1Long)
1491	{
1492	AssertMsgFailed(("Illegal enabling of paging with CS.u1Long = 1!!\n"));
1493	return VERR_EM_INTERPRETER; /** @todo generate #GP(0) */
1494	}
1495
1496	/* Illegal to switch to long mode before activating PAE first (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1497	if (!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PAE))
1498	{
1499	AssertMsgFailed(("Illegal enabling of paging with PAE disabled!!\n"));
1500	return VERR_EM_INTERPRETER; /** @todo generate #GP(0) */
1501	}
1502	msrEFER \|= MSR_K6_EFER_LMA;
1503	}
1504	else
1505	if ( (oldval & X86_CR0_PG)
1506	&& !(val & X86_CR0_PG))
1507	{
1508	msrEFER &= ~MSR_K6_EFER_LMA;
1509	/** @todo Do we need to cut off rip here? High dword of rip is undefined, so it shouldn't really matter. */
1510	}
1511	CPUMSetGuestEFER(pVCpu, msrEFER);
1512	}
1513	rc2 = PGMChangeMode(pVCpu, CPUMGetGuestCR0(pVCpu), CPUMGetGuestCR4(pVCpu), CPUMGetGuestEFER(pVCpu));
1514	return rc2 == VINF_SUCCESS ? rc : rc2;
1515
1516	case DISCREG_CR2:
1517	rc = CPUMSetGuestCR2(pVCpu, val); AssertRC(rc);
1518	return VINF_SUCCESS;
1519
1520	case DISCREG_CR3:
1521	/* Reloading the current CR3 means the guest just wants to flush the TLBs */
1522	rc = CPUMSetGuestCR3(pVCpu, val); AssertRC(rc);
1523	if (CPUMGetGuestCR0(pVCpu) & X86_CR0_PG)
1524	{
1525	/* flush */
1526	rc = PGMFlushTLB(pVCpu, val, !(CPUMGetGuestCR4(pVCpu) & X86_CR4_PGE));
1527	AssertRC(rc);
1528	}
1529	return rc;
1530
1531	case DISCREG_CR4:
1532	oldval = CPUMGetGuestCR4(pVCpu);
1533	rc = CPUMSetGuestCR4(pVCpu, val); AssertRC(rc);
1534	val = CPUMGetGuestCR4(pVCpu);
1535
1536	/* Illegal to disable PAE when long mode is active. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1537	msrEFER = CPUMGetGuestEFER(pVCpu);
1538	if ( (msrEFER & MSR_K6_EFER_LMA)
1539	&& (oldval & X86_CR4_PAE)
1540	&& !(val & X86_CR4_PAE))
1541	{
1542	return VERR_EM_INTERPRETER; /** @todo generate #GP(0) */
1543	}
1544
1545	/* From IEM iemCImpl_load_CrX. */
1546	/** @todo Check guest CPUID bits for determining corresponding valid bits. */
1547	fValid = X86_CR4_VME \| X86_CR4_PVI
1548	\| X86_CR4_TSD \| X86_CR4_DE
1549	\| X86_CR4_PSE \| X86_CR4_PAE
1550	\| X86_CR4_MCE \| X86_CR4_PGE
1551	\| X86_CR4_PCE \| X86_CR4_OSFSXR
1552	\| X86_CR4_OSXMMEEXCPT;
1553	//if (xxx)
1554	// fValid \|= X86_CR4_VMXE;
1555	//if (xxx)
1556	// fValid \|= X86_CR4_OSXSAVE;
1557	if (val & ~(uint64_t)fValid)
1558	{
1559	Log(("Trying to set reserved CR4 bits: NewCR4=%#llx InvalidBits=%#llx\n", val, val & ~(uint64_t)fValid));
1560	return VERR_EM_INTERPRETER; /** @todo generate #GP(0) */
1561	}
1562
1563	rc = VINF_SUCCESS;
1564	if ( (oldval & (X86_CR4_PGE\|X86_CR4_PAE\|X86_CR4_PSE))
1565	!= (val & (X86_CR4_PGE\|X86_CR4_PAE\|X86_CR4_PSE)))
1566	{
1567	/* global flush */
1568	rc = PGMFlushTLB(pVCpu, CPUMGetGuestCR3(pVCpu), true /* global */);
1569	AssertRCReturn(rc, rc);
1570	}
1571
1572	/* Feeling extremely lazy. */
1573	# ifdef IN_RC
1574	if ( (oldval & (X86_CR4_OSFSXR\|X86_CR4_OSXMMEEXCPT\|X86_CR4_PCE\|X86_CR4_MCE\|X86_CR4_PAE\|X86_CR4_DE\|X86_CR4_TSD\|X86_CR4_PVI\|X86_CR4_VME))
1575	!= (val & (X86_CR4_OSFSXR\|X86_CR4_OSXMMEEXCPT\|X86_CR4_PCE\|X86_CR4_MCE\|X86_CR4_PAE\|X86_CR4_DE\|X86_CR4_TSD\|X86_CR4_PVI\|X86_CR4_VME)))
1576	{
1577	Log(("emInterpretMovCRx: CR4: %#RX64->%#RX64 => R3\n", oldval, val));
1578	VMCPU_FF_SET(pVCpu, VMCPU_FF_TO_R3);
1579	}
1580	# endif
1581	# ifdef VBOX_WITH_RAW_MODE
1582	if (((val ^ oldval) & X86_CR4_VME) && !HMIsEnabled(pVM))
1583	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1584	# endif
1585
1586	rc2 = PGMChangeMode(pVCpu, CPUMGetGuestCR0(pVCpu), CPUMGetGuestCR4(pVCpu), CPUMGetGuestEFER(pVCpu));
1587	return rc2 == VINF_SUCCESS ? rc : rc2;
1588
1589	case DISCREG_CR8:
1590	return PDMApicSetTPR(pVCpu, val << 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
1591
1592	default:
1593	AssertFailed();
1594	case DISCREG_CR1: /* illegal op */
1595	break;
1596	}
1597	return VERR_EM_INTERPRETER;
1598	}
1599
1600
1601	/**
1602	* Interpret CRx write.
1603	*
1604	* @returns VBox status code.
1605	* @param pVM Pointer to the VM.
1606	* @param pVCpu Pointer to the VMCPU.
1607	* @param pRegFrame The register frame.
1608	* @param DestRegCRx CRx register index (DISUSE_REG_CR*)
1609	* @param SrcRegGen General purpose register index (USE_REG_E**))
1610	*
1611	*/
1612	VMM_INT_DECL(int) EMInterpretCRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint32_t SrcRegGen)
1613	{
1614	uint64_t val;
1615	int rc;
1616	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1617
1618	if (CPUMIsGuestIn64BitCode(pVCpu))
1619	rc = DISFetchReg64(pRegFrame, SrcRegGen, &val);
1620	else
1621	{
1622	uint32_t val32;
1623	rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
1624	val = val32;
1625	}
1626
1627	if (RT_SUCCESS(rc))
1628	return emUpdateCRx(pVM, pVCpu, pRegFrame, DestRegCrx, val);
1629
1630	return VERR_EM_INTERPRETER;
1631	}
1632
1633	/**
1634	* Interpret LMSW.
1635	*
1636	* @returns VBox status code.
1637	* @param pVM Pointer to the VM.
1638	* @param pVCpu Pointer to the VMCPU.
1639	* @param pRegFrame The register frame.
1640	* @param u16Data LMSW source data.
1641	*
1642	*/
1643	VMM_INT_DECL(int) EMInterpretLMSW(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint16_t u16Data)
1644	{
1645	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1646	uint64_t OldCr0 = CPUMGetGuestCR0(pVCpu);
1647
1648	/* Only PE, MP, EM and TS can be changed; note that PE can't be cleared by this instruction. */
1649	uint64_t NewCr0 = ( OldCr0 & ~( X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
1650	\| (u16Data & (X86_CR0_PE \| X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS));
1651
1652	return emUpdateCRx(pVM, pVCpu, pRegFrame, DISCREG_CR0, NewCr0);
1653	}
1654
1655
1656	/**
1657	* Interpret CLTS.
1658	*
1659	* @returns VBox status code.
1660	* @param pVM Pointer to the VM.
1661	* @param pVCpu Pointer to the VMCPU.
1662	*
1663	*/
1664	VMM_INT_DECL(int) EMInterpretCLTS(PVM pVM, PVMCPU pVCpu)
1665	{
1666	NOREF(pVM);
1667
1668	uint64_t cr0 = CPUMGetGuestCR0(pVCpu);
1669	if (!(cr0 & X86_CR0_TS))
1670	return VINF_SUCCESS;
1671	return CPUMSetGuestCR0(pVCpu, cr0 & ~X86_CR0_TS);
1672	}
1673
1674
1675	#ifdef LOG_ENABLED
1676	static const char *emMSRtoString(uint32_t uMsr)
1677	{
1678	switch (uMsr)
1679	{
1680	case MSR_IA32_APICBASE: return "MSR_IA32_APICBASE";
1681	case MSR_IA32_CR_PAT: return "MSR_IA32_CR_PAT";
1682	case MSR_IA32_SYSENTER_CS: return "MSR_IA32_SYSENTER_CS";
1683	case MSR_IA32_SYSENTER_EIP: return "MSR_IA32_SYSENTER_EIP";
1684	case MSR_IA32_SYSENTER_ESP: return "MSR_IA32_SYSENTER_ESP";
1685	case MSR_K6_EFER: return "MSR_K6_EFER";
1686	case MSR_K8_SF_MASK: return "MSR_K8_SF_MASK";
1687	case MSR_K6_STAR: return "MSR_K6_STAR";
1688	case MSR_K8_LSTAR: return "MSR_K8_LSTAR";
1689	case MSR_K8_CSTAR: return "MSR_K8_CSTAR";
1690	case MSR_K8_FS_BASE: return "MSR_K8_FS_BASE";
1691	case MSR_K8_GS_BASE: return "MSR_K8_GS_BASE";
1692	case MSR_K8_KERNEL_GS_BASE: return "MSR_K8_KERNEL_GS_BASE";
1693	case MSR_K8_TSC_AUX: return "MSR_K8_TSC_AUX";
1694	case MSR_IA32_BIOS_SIGN_ID: return "Unsupported MSR_IA32_BIOS_SIGN_ID";
1695	case MSR_IA32_PLATFORM_ID: return "Unsupported MSR_IA32_PLATFORM_ID";
1696	case MSR_IA32_BIOS_UPDT_TRIG: return "Unsupported MSR_IA32_BIOS_UPDT_TRIG";
1697	case MSR_IA32_TSC: return "MSR_IA32_TSC";
1698	case MSR_IA32_MISC_ENABLE: return "MSR_IA32_MISC_ENABLE";
1699	case MSR_IA32_MTRR_CAP: return "MSR_IA32_MTRR_CAP";
1700	case MSR_IA32_MCG_CAP: return "Unsupported MSR_IA32_MCG_CAP";
1701	case MSR_IA32_MCG_STATUS: return "Unsupported MSR_IA32_MCG_STATUS";
1702	case MSR_IA32_MCG_CTRL: return "Unsupported MSR_IA32_MCG_CTRL";
1703	case MSR_IA32_MTRR_DEF_TYPE: return "MSR_IA32_MTRR_DEF_TYPE";
1704	case MSR_K7_EVNTSEL0: return "Unsupported MSR_K7_EVNTSEL0";
1705	case MSR_K7_EVNTSEL1: return "Unsupported MSR_K7_EVNTSEL1";
1706	case MSR_K7_EVNTSEL2: return "Unsupported MSR_K7_EVNTSEL2";
1707	case MSR_K7_EVNTSEL3: return "Unsupported MSR_K7_EVNTSEL3";
1708	case MSR_IA32_MC0_CTL: return "Unsupported MSR_IA32_MC0_CTL";
1709	case MSR_IA32_MC0_STATUS: return "Unsupported MSR_IA32_MC0_STATUS";
1710	case MSR_IA32_PERFEVTSEL0: return "Unsupported MSR_IA32_PERFEVTSEL0";
1711	case MSR_IA32_PERFEVTSEL1: return "Unsupported MSR_IA32_PERFEVTSEL1";
1712	case MSR_IA32_PERF_STATUS: return "MSR_IA32_PERF_STATUS";
1713	case MSR_IA32_PLATFORM_INFO: return "MSR_IA32_PLATFORM_INFO";
1714	case MSR_IA32_PERF_CTL: return "Unsupported MSR_IA32_PERF_CTL";
1715	case MSR_K7_PERFCTR0: return "Unsupported MSR_K7_PERFCTR0";
1716	case MSR_K7_PERFCTR1: return "Unsupported MSR_K7_PERFCTR1";
1717	case MSR_K7_PERFCTR2: return "Unsupported MSR_K7_PERFCTR2";
1718	case MSR_K7_PERFCTR3: return "Unsupported MSR_K7_PERFCTR3";
1719	case MSR_IA32_PMC0: return "Unsupported MSR_IA32_PMC0";
1720	case MSR_IA32_PMC1: return "Unsupported MSR_IA32_PMC1";
1721	case MSR_IA32_PMC2: return "Unsupported MSR_IA32_PMC2";
1722	case MSR_IA32_PMC3: return "Unsupported MSR_IA32_PMC3";
1723	}
1724	return "Unknown MSR";
1725	}
1726	#endif /* LOG_ENABLED */
1727
1728
1729	/**
1730	* Interpret RDMSR
1731	*
1732	* @returns VBox status code.
1733	* @param pVM Pointer to the VM.
1734	* @param pVCpu Pointer to the VMCPU.
1735	* @param pRegFrame The register frame.
1736	*/
1737	VMM_INT_DECL(int) EMInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1738	{
1739	NOREF(pVM);
1740
1741	/* Get the current privilege level. */
1742	if (CPUMGetGuestCPL(pVCpu) != 0)
1743	{
1744	Log4(("EM: Refuse RDMSR: CPL != 0\n"));
1745	return VERR_EM_INTERPRETER; /* supervisor only */
1746	}
1747
1748	uint64_t uValue;
1749	VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pRegFrame->ecx, &uValue);
1750	if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
1751	{
1752	Log4(("EM: Refuse RDMSR: rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1753	Assert(rcStrict == VERR_CPUM_RAISE_GP_0 \|\| rcStrict == VERR_EM_INTERPRETER \|\| rcStrict == VINF_CPUM_R3_MSR_READ);
1754	return VERR_EM_INTERPRETER;
1755	}
1756	pRegFrame->rax = (uint32_t) uValue;
1757	pRegFrame->rdx = (uint32_t)(uValue >> 32);
1758	LogFlow(("EMInterpretRdmsr %s (%x) -> %RX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx, uValue));
1759	return VINF_SUCCESS;
1760	}
1761
1762
1763	/**
1764	* Interpret WRMSR
1765	*
1766	* @returns VBox status code.
1767	* @param pVM Pointer to the VM.
1768	* @param pVCpu Pointer to the VMCPU.
1769	* @param pRegFrame The register frame.
1770	*/
1771	VMM_INT_DECL(int) EMInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1772	{
1773	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1774
1775	/* Check the current privilege level, this instruction is supervisor only. */
1776	if (CPUMGetGuestCPL(pVCpu) != 0)
1777	{
1778	Log4(("EM: Refuse WRMSR: CPL != 0\n"));
1779	return VERR_EM_INTERPRETER; /** @todo raise \#GP(0) */
1780	}
1781
1782	VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pRegFrame->ecx, RT_MAKE_U64(pRegFrame->eax, pRegFrame->edx));
1783	if (rcStrict != VINF_SUCCESS)
1784	{
1785	Log4(("EM: Refuse WRMSR: CPUMSetGuestMsr returned %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1786	Assert(rcStrict == VERR_CPUM_RAISE_GP_0 \|\| rcStrict == VERR_EM_INTERPRETER \|\| rcStrict == VINF_CPUM_R3_MSR_WRITE);
1787	return VERR_EM_INTERPRETER;
1788	}
1789	LogFlow(("EMInterpretWrmsr %s (%x) val=%RX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx,
1790	RT_MAKE_U64(pRegFrame->eax, pRegFrame->edx)));
1791	NOREF(pVM);
1792	return VINF_SUCCESS;
1793	}
1794
1795
1796	/**
1797	* Interpret CRx read.
1798	*
1799	* @returns VBox status code.
1800	* @param pVM Pointer to the VM.
1801	* @param pVCpu Pointer to the VMCPU.
1802	* @param pRegFrame The register frame.
1803	* @param DestRegGen General purpose register index (USE_REG_E**))
1804	* @param SrcRegCRx CRx register index (DISUSE_REG_CR*)
1805	*
1806	*/
1807	VMM_INT_DECL(int) EMInterpretCRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx)
1808	{
1809	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1810	uint64_t val64;
1811	int rc = CPUMGetGuestCRx(pVCpu, SrcRegCrx, &val64);
1812	AssertMsgRCReturn(rc, ("CPUMGetGuestCRx %d failed\n", SrcRegCrx), VERR_EM_INTERPRETER);
1813	NOREF(pVM);
1814
1815	if (CPUMIsGuestIn64BitCode(pVCpu))
1816	rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
1817	else
1818	rc = DISWriteReg32(pRegFrame, DestRegGen, val64);
1819
1820	if (RT_SUCCESS(rc))
1821	{
1822	LogFlow(("MOV_CR: gen32=%d CR=%d val=%RX64\n", DestRegGen, SrcRegCrx, val64));
1823	return VINF_SUCCESS;
1824	}
1825	return VERR_EM_INTERPRETER;
1826	}
1827
1828
1829	/**
1830	* Interpret DRx write.
1831	*
1832	* @returns VBox status code.
1833	* @param pVM Pointer to the VM.
1834	* @param pVCpu Pointer to the VMCPU.
1835	* @param pRegFrame The register frame.
1836	* @param DestRegDRx DRx register index (USE_REG_DR*)
1837	* @param SrcRegGen General purpose register index (USE_REG_E**))
1838	*
1839	*/
1840	VMM_INT_DECL(int) EMInterpretDRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen)
1841	{
1842	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1843	uint64_t uNewDrX;
1844	int rc;
1845	NOREF(pVM);
1846
1847	if (CPUMIsGuestIn64BitCode(pVCpu))
1848	rc = DISFetchReg64(pRegFrame, SrcRegGen, &uNewDrX);
1849	else
1850	{
1851	uint32_t val32;
1852	rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
1853	uNewDrX = val32;
1854	}
1855
1856	if (RT_SUCCESS(rc))
1857	{
1858	if (DestRegDrx == 6)
1859	{
1860	uNewDrX \|= X86_DR6_RA1_MASK;
1861	uNewDrX &= ~X86_DR6_RAZ_MASK;
1862	}
1863	else if (DestRegDrx == 7)
1864	{
1865	uNewDrX \|= X86_DR7_RA1_MASK;
1866	uNewDrX &= ~X86_DR7_RAZ_MASK;
1867	}
1868
1869	/** @todo we don't fail if illegal bits are set/cleared for e.g. dr7 */
1870	rc = CPUMSetGuestDRx(pVCpu, DestRegDrx, uNewDrX);
1871	if (RT_SUCCESS(rc))
1872	return rc;
1873	AssertMsgFailed(("CPUMSetGuestDRx %d failed\n", DestRegDrx));
1874	}
1875	return VERR_EM_INTERPRETER;
1876	}
1877
1878
1879	/**
1880	* Interpret DRx read.
1881	*
1882	* @returns VBox status code.
1883	* @param pVM Pointer to the VM.
1884	* @param pVCpu Pointer to the VMCPU.
1885	* @param pRegFrame The register frame.
1886	* @param DestRegGen General purpose register index (USE_REG_E**))
1887	* @param SrcRegDRx DRx register index (USE_REG_DR*)
1888	*
1889	*/
1890	VMM_INT_DECL(int) EMInterpretDRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx)
1891	{
1892	uint64_t val64;
1893	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1894	NOREF(pVM);
1895
1896	int rc = CPUMGetGuestDRx(pVCpu, SrcRegDrx, &val64);
1897	AssertMsgRCReturn(rc, ("CPUMGetGuestDRx %d failed\n", SrcRegDrx), VERR_EM_INTERPRETER);
1898	if (CPUMIsGuestIn64BitCode(pVCpu))
1899	rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
1900	else
1901	rc = DISWriteReg32(pRegFrame, DestRegGen, (uint32_t)val64);
1902
1903	if (RT_SUCCESS(rc))
1904	return VINF_SUCCESS;
1905
1906	return VERR_EM_INTERPRETER;
1907	}
1908
1909
1910	#if !defined(VBOX_WITH_IEM) \|\| defined(VBOX_COMPARE_IEM_AND_EM)
1911
1912
1913
1914
1915
1916
1917	/*
1918	*
1919	* The old interpreter.
1920	* The old interpreter.
1921	* The old interpreter.
1922	* The old interpreter.
1923	* The old interpreter.
1924	*
1925	*/
1926
1927	DECLINLINE(int) emRamRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCPTR GCPtrSrc, uint32_t cb)
1928	{
1929	#ifdef IN_RC
1930	int rc = MMGCRamRead(pVM, pvDst, (void *)(uintptr_t)GCPtrSrc, cb);
1931	if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
1932	return rc;
1933	/*
1934	* The page pool cache may end up here in some cases because it
1935	* flushed one of the shadow mappings used by the trapping
1936	* instruction and it either flushed the TLB or the CPU reused it.
1937	*/
1938	#else
1939	NOREF(pVM);
1940	#endif
1941	return PGMPhysInterpretedReadNoHandlers(pVCpu, pCtxCore, pvDst, GCPtrSrc, cb, /fMayTrap/ false);
1942	}
1943
1944
1945	DECLINLINE(int) emRamWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, RTGCPTR GCPtrDst, const void *pvSrc, uint32_t cb)
1946	{
1947	/* Don't use MMGCRamWrite here as it does not respect zero pages, shared
1948	pages or write monitored pages. */
1949	NOREF(pVM);
1950	#if !defined(VBOX_COMPARE_IEM_AND_EM) \|\| !defined(VBOX_COMPARE_IEM_LAST)
1951	int rc = PGMPhysInterpretedWriteNoHandlers(pVCpu, pCtxCore, GCPtrDst, pvSrc, cb, /fMayTrap/ false);
1952	#else
1953	int rc = VINF_SUCCESS;
1954	#endif
1955	#ifdef VBOX_COMPARE_IEM_AND_EM
1956	Log(("EM Wrote: %RGv %.*Rhxs rc=%Rrc\n", GCPtrDst, RT_MAX(RT_MIN(cb, 64), 1), pvSrc, rc));
1957	g_cbEmWrote = cb;
1958	memcpy(g_abEmWrote, pvSrc, RT_MIN(cb, sizeof(g_abEmWrote)));
1959	#endif
1960	return rc;
1961	}
1962
1963
1964	/** Convert sel:addr to a flat GC address. */
1965	DECLINLINE(RTGCPTR) emConvertToFlatAddr(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pDis, PDISOPPARAM pParam, RTGCPTR pvAddr)
1966	{
1967	DISSELREG enmPrefixSeg = DISDetectSegReg(pDis, pParam);
1968	return SELMToFlat(pVM, enmPrefixSeg, pRegFrame, pvAddr);
1969	}
1970
1971
1972	#if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
1973	/**
1974	* Get the mnemonic for the disassembled instruction.
1975	*
1976	* GC/R0 doesn't include the strings in the DIS tables because
1977	* of limited space.
1978	*/
1979	static const char *emGetMnemonic(PDISCPUSTATE pDis)
1980	{
1981	switch (pDis->pCurInstr->uOpcode)
1982	{
1983	case OP_XCHG: return "Xchg";
1984	case OP_DEC: return "Dec";
1985	case OP_INC: return "Inc";
1986	case OP_POP: return "Pop";
1987	case OP_OR: return "Or";
1988	case OP_AND: return "And";
1989	case OP_MOV: return "Mov";
1990	case OP_INVLPG: return "InvlPg";
1991	case OP_CPUID: return "CpuId";
1992	case OP_MOV_CR: return "MovCRx";
1993	case OP_MOV_DR: return "MovDRx";
1994	case OP_LLDT: return "LLdt";
1995	case OP_LGDT: return "LGdt";
1996	case OP_LIDT: return "LIdt";
1997	case OP_CLTS: return "Clts";
1998	case OP_MONITOR: return "Monitor";
1999	case OP_MWAIT: return "MWait";
2000	case OP_RDMSR: return "Rdmsr";
2001	case OP_WRMSR: return "Wrmsr";
2002	case OP_ADD: return "Add";
2003	case OP_ADC: return "Adc";
2004	case OP_SUB: return "Sub";
2005	case OP_SBB: return "Sbb";
2006	case OP_RDTSC: return "Rdtsc";
2007	case OP_STI: return "Sti";
2008	case OP_CLI: return "Cli";
2009	case OP_XADD: return "XAdd";
2010	case OP_HLT: return "Hlt";
2011	case OP_IRET: return "Iret";
2012	case OP_MOVNTPS: return "MovNTPS";
2013	case OP_STOSWD: return "StosWD";
2014	case OP_WBINVD: return "WbInvd";
2015	case OP_XOR: return "Xor";
2016	case OP_BTR: return "Btr";
2017	case OP_BTS: return "Bts";
2018	case OP_BTC: return "Btc";
2019	case OP_LMSW: return "Lmsw";
2020	case OP_SMSW: return "Smsw";
2021	case OP_CMPXCHG: return pDis->fPrefix & DISPREFIX_LOCK ? "Lock CmpXchg" : "CmpXchg";
2022	case OP_CMPXCHG8B: return pDis->fPrefix & DISPREFIX_LOCK ? "Lock CmpXchg8b" : "CmpXchg8b";
2023
2024	default:
2025	Log(("Unknown opcode %d\n", pDis->pCurInstr->uOpcode));
2026	return "???";
2027	}
2028	}
2029	#endif /* VBOX_STRICT \|\| LOG_ENABLED */
2030
2031
2032	/**
2033	* XCHG instruction emulation.
2034	*/
2035	static int emInterpretXchg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2036	{
2037	DISQPVPARAMVAL param1, param2;
2038	NOREF(pvFault);
2039
2040	/* Source to make DISQueryParamVal read the register value - ugly hack */
2041	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
2042	if(RT_FAILURE(rc))
2043	return VERR_EM_INTERPRETER;
2044
2045	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2046	if(RT_FAILURE(rc))
2047	return VERR_EM_INTERPRETER;
2048
2049	#ifdef IN_RC
2050	if (TRPMHasTrap(pVCpu))
2051	{
2052	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2053	{
2054	#endif
2055	RTGCPTR pParam1 = 0, pParam2 = 0;
2056	uint64_t valpar1, valpar2;
2057
2058	AssertReturn(pDis->Param1.cb == pDis->Param2.cb, VERR_EM_INTERPRETER);
2059	switch(param1.type)
2060	{
2061	case DISQPV_TYPE_IMMEDIATE: /* register type is translated to this one too */
2062	valpar1 = param1.val.val64;
2063	break;
2064
2065	case DISQPV_TYPE_ADDRESS:
2066	pParam1 = (RTGCPTR)param1.val.val64;
2067	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2068	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
2069	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
2070	if (RT_FAILURE(rc))
2071	{
2072	AssertMsgFailed(("MMGCRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2073	return VERR_EM_INTERPRETER;
2074	}
2075	break;
2076
2077	default:
2078	AssertFailed();
2079	return VERR_EM_INTERPRETER;
2080	}
2081
2082	switch(param2.type)
2083	{
2084	case DISQPV_TYPE_ADDRESS:
2085	pParam2 = (RTGCPTR)param2.val.val64;
2086	pParam2 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param2, pParam2);
2087	EM_ASSERT_FAULT_RETURN(pParam2 == pvFault, VERR_EM_INTERPRETER);
2088	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar2, pParam2, param2.size);
2089	if (RT_FAILURE(rc))
2090	{
2091	AssertMsgFailed(("MMGCRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2092	}
2093	break;
2094
2095	case DISQPV_TYPE_IMMEDIATE:
2096	valpar2 = param2.val.val64;
2097	break;
2098
2099	default:
2100	AssertFailed();
2101	return VERR_EM_INTERPRETER;
2102	}
2103
2104	/* Write value of parameter 2 to parameter 1 (reg or memory address) */
2105	if (pParam1 == 0)
2106	{
2107	Assert(param1.type == DISQPV_TYPE_IMMEDIATE); /* register actually */
2108	switch(param1.size)
2109	{
2110	case 1: //special case for AH etc
2111	rc = DISWriteReg8(pRegFrame, pDis->Param1.Base.idxGenReg, (uint8_t )valpar2); break;
2112	case 2: rc = DISWriteReg16(pRegFrame, pDis->Param1.Base.idxGenReg, (uint16_t)valpar2); break;
2113	case 4: rc = DISWriteReg32(pRegFrame, pDis->Param1.Base.idxGenReg, (uint32_t)valpar2); break;
2114	case 8: rc = DISWriteReg64(pRegFrame, pDis->Param1.Base.idxGenReg, valpar2); break;
2115	default: AssertFailedReturn(VERR_EM_INTERPRETER);
2116	}
2117	if (RT_FAILURE(rc))
2118	return VERR_EM_INTERPRETER;
2119	}
2120	else
2121	{
2122	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar2, param1.size);
2123	if (RT_FAILURE(rc))
2124	{
2125	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2126	return VERR_EM_INTERPRETER;
2127	}
2128	}
2129
2130	/* Write value of parameter 1 to parameter 2 (reg or memory address) */
2131	if (pParam2 == 0)
2132	{
2133	Assert(param2.type == DISQPV_TYPE_IMMEDIATE); /* register actually */
2134	switch(param2.size)
2135	{
2136	case 1: //special case for AH etc
2137	rc = DISWriteReg8(pRegFrame, pDis->Param2.Base.idxGenReg, (uint8_t )valpar1); break;
2138	case 2: rc = DISWriteReg16(pRegFrame, pDis->Param2.Base.idxGenReg, (uint16_t)valpar1); break;
2139	case 4: rc = DISWriteReg32(pRegFrame, pDis->Param2.Base.idxGenReg, (uint32_t)valpar1); break;
2140	case 8: rc = DISWriteReg64(pRegFrame, pDis->Param2.Base.idxGenReg, valpar1); break;
2141	default: AssertFailedReturn(VERR_EM_INTERPRETER);
2142	}
2143	if (RT_FAILURE(rc))
2144	return VERR_EM_INTERPRETER;
2145	}
2146	else
2147	{
2148	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam2, &valpar1, param2.size);
2149	if (RT_FAILURE(rc))
2150	{
2151	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2152	return VERR_EM_INTERPRETER;
2153	}
2154	}
2155
2156	*pcbSize = param2.size;
2157	return VINF_SUCCESS;
2158	#ifdef IN_RC
2159	}
2160	}
2161	return VERR_EM_INTERPRETER;
2162	#endif
2163	}
2164
2165
2166	/**
2167	* INC and DEC emulation.
2168	*/
2169	static int emInterpretIncDec(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
2170	PFNEMULATEPARAM2 pfnEmulate)
2171	{
2172	DISQPVPARAMVAL param1;
2173	NOREF(pvFault);
2174
2175	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2176	if(RT_FAILURE(rc))
2177	return VERR_EM_INTERPRETER;
2178
2179	#ifdef IN_RC
2180	if (TRPMHasTrap(pVCpu))
2181	{
2182	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2183	{
2184	#endif
2185	RTGCPTR pParam1 = 0;
2186	uint64_t valpar1;
2187
2188	if (param1.type == DISQPV_TYPE_ADDRESS)
2189	{
2190	pParam1 = (RTGCPTR)param1.val.val64;
2191	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2192	#ifdef IN_RC
2193	/* Safety check (in theory it could cross a page boundary and fault there though) */
2194	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
2195	#endif
2196	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
2197	if (RT_FAILURE(rc))
2198	{
2199	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2200	return VERR_EM_INTERPRETER;
2201	}
2202	}
2203	else
2204	{
2205	AssertFailed();
2206	return VERR_EM_INTERPRETER;
2207	}
2208
2209	uint32_t eflags;
2210
2211	eflags = pfnEmulate(&valpar1, param1.size);
2212
2213	/* Write result back */
2214	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, param1.size);
2215	if (RT_FAILURE(rc))
2216	{
2217	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2218	return VERR_EM_INTERPRETER;
2219	}
2220
2221	/* Update guest's eflags and finish. */
2222	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2223	\| (eflags & (X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2224
2225	/* All done! */
2226	*pcbSize = param1.size;
2227	return VINF_SUCCESS;
2228	#ifdef IN_RC
2229	}
2230	}
2231	return VERR_EM_INTERPRETER;
2232	#endif
2233	}
2234
2235
2236	/**
2237	* POP Emulation.
2238	*/
2239	static int emInterpretPop(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2240	{
2241	Assert(pDis->uCpuMode != DISCPUMODE_64BIT); /** @todo check */
2242	DISQPVPARAMVAL param1;
2243	NOREF(pvFault);
2244
2245	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2246	if(RT_FAILURE(rc))
2247	return VERR_EM_INTERPRETER;
2248
2249	#ifdef IN_RC
2250	if (TRPMHasTrap(pVCpu))
2251	{
2252	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2253	{
2254	#endif
2255	RTGCPTR pParam1 = 0;
2256	uint32_t valpar1;
2257	RTGCPTR pStackVal;
2258
2259	/* Read stack value first */
2260	if (CPUMGetGuestCodeBits(pVCpu) == 16)
2261	return VERR_EM_INTERPRETER; /* No legacy 16 bits stuff here, please. */
2262
2263	/* Convert address; don't bother checking limits etc, as we only read here */
2264	pStackVal = SELMToFlat(pVM, DISSELREG_SS, pRegFrame, (RTGCPTR)pRegFrame->esp);
2265	if (pStackVal == 0)
2266	return VERR_EM_INTERPRETER;
2267
2268	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pStackVal, param1.size);
2269	if (RT_FAILURE(rc))
2270	{
2271	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2272	return VERR_EM_INTERPRETER;
2273	}
2274
2275	if (param1.type == DISQPV_TYPE_ADDRESS)
2276	{
2277	pParam1 = (RTGCPTR)param1.val.val64;
2278
2279	/* pop [esp+xx] uses esp after the actual pop! */
2280	AssertCompile(DISGREG_ESP == DISGREG_SP);
2281	if ( (pDis->Param1.fUse & DISUSE_BASE)
2282	&& (pDis->Param1.fUse & (DISUSE_REG_GEN16\|DISUSE_REG_GEN32))
2283	&& pDis->Param1.Base.idxGenReg == DISGREG_ESP
2284	)
2285	pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + param1.size);
2286
2287	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2288	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault \|\| (RTGCPTR)pRegFrame->esp == pvFault, VERR_EM_INTERPRETER);
2289	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, param1.size);
2290	if (RT_FAILURE(rc))
2291	{
2292	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2293	return VERR_EM_INTERPRETER;
2294	}
2295
2296	/* Update ESP as the last step */
2297	pRegFrame->esp += param1.size;
2298	}
2299	else
2300	{
2301	#ifndef DEBUG_bird // annoying assertion.
2302	AssertFailed();
2303	#endif
2304	return VERR_EM_INTERPRETER;
2305	}
2306
2307	/* All done! */
2308	*pcbSize = param1.size;
2309	return VINF_SUCCESS;
2310	#ifdef IN_RC
2311	}
2312	}
2313	return VERR_EM_INTERPRETER;
2314	#endif
2315	}
2316
2317
2318	/**
2319	* XOR/OR/AND Emulation.
2320	*/
2321	static int emInterpretOrXorAnd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
2322	PFNEMULATEPARAM3 pfnEmulate)
2323	{
2324	DISQPVPARAMVAL param1, param2;
2325	NOREF(pvFault);
2326
2327	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2328	if(RT_FAILURE(rc))
2329	return VERR_EM_INTERPRETER;
2330
2331	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2332	if(RT_FAILURE(rc))
2333	return VERR_EM_INTERPRETER;
2334
2335	#ifdef IN_RC
2336	if (TRPMHasTrap(pVCpu))
2337	{
2338	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2339	{
2340	#endif
2341	RTGCPTR pParam1;
2342	uint64_t valpar1, valpar2;
2343
2344	if (pDis->Param1.cb != pDis->Param2.cb)
2345	{
2346	if (pDis->Param1.cb < pDis->Param2.cb)
2347	{
2348	AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip, pDis->Param1.cb, pDis->Param2.cb)); /* should never happen! */
2349	return VERR_EM_INTERPRETER;
2350	}
2351	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
2352	pDis->Param2.cb = pDis->Param1.cb;
2353	param2.size = param1.size;
2354	}
2355
2356	/* The destination is always a virtual address */
2357	if (param1.type == DISQPV_TYPE_ADDRESS)
2358	{
2359	pParam1 = (RTGCPTR)param1.val.val64;
2360	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2361	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
2362	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
2363	if (RT_FAILURE(rc))
2364	{
2365	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2366	return VERR_EM_INTERPRETER;
2367	}
2368	}
2369	else
2370	{
2371	AssertFailed();
2372	return VERR_EM_INTERPRETER;
2373	}
2374
2375	/* Register or immediate data */
2376	switch(param2.type)
2377	{
2378	case DISQPV_TYPE_IMMEDIATE: /* both immediate data and register (ugly) */
2379	valpar2 = param2.val.val64;
2380	break;
2381
2382	default:
2383	AssertFailed();
2384	return VERR_EM_INTERPRETER;
2385	}
2386
2387	LogFlow(("emInterpretOrXorAnd %s %RGv %RX64 - %RX64 size %d (%d)\n", emGetMnemonic(pDis), pParam1, valpar1, valpar2, param2.size, param1.size));
2388
2389	/* Data read, emulate instruction. */
2390	uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
2391
2392	LogFlow(("emInterpretOrXorAnd %s result %RX64\n", emGetMnemonic(pDis), valpar1));
2393
2394	/* Update guest's eflags and finish. */
2395	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2396	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2397
2398	/* And write it back */
2399	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, param1.size);
2400	if (RT_SUCCESS(rc))
2401	{
2402	/* All done! */
2403	*pcbSize = param2.size;
2404	return VINF_SUCCESS;
2405	}
2406	#ifdef IN_RC
2407	}
2408	}
2409	#endif
2410	return VERR_EM_INTERPRETER;
2411	}
2412
2413
2414	#ifndef VBOX_COMPARE_IEM_AND_EM
2415	/**
2416	* LOCK XOR/OR/AND Emulation.
2417	*/
2418	static int emInterpretLockOrXorAnd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
2419	uint32_t *pcbSize, PFNEMULATELOCKPARAM3 pfnEmulate)
2420	{
2421	void *pvParam1;
2422	DISQPVPARAMVAL param1, param2;
2423	NOREF(pvFault);
2424
2425	#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL_IN_R0)
2426	Assert(pDis->Param1.cb <= 4);
2427	#endif
2428
2429	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2430	if(RT_FAILURE(rc))
2431	return VERR_EM_INTERPRETER;
2432
2433	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2434	if(RT_FAILURE(rc))
2435	return VERR_EM_INTERPRETER;
2436
2437	if (pDis->Param1.cb != pDis->Param2.cb)
2438	{
2439	AssertMsgReturn(pDis->Param1.cb >= pDis->Param2.cb, /* should never happen! */
2440	("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip, pDis->Param1.cb, pDis->Param2.cb),
2441	VERR_EM_INTERPRETER);
2442
2443	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
2444	pDis->Param2.cb = pDis->Param1.cb;
2445	param2.size = param1.size;
2446	}
2447
2448	#ifdef IN_RC
2449	/* Safety check (in theory it could cross a page boundary and fault there though) */
2450	Assert( TRPMHasTrap(pVCpu)
2451	&& (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW));
2452	EM_ASSERT_FAULT_RETURN(GCPtrPar1 == pvFault, VERR_EM_INTERPRETER);
2453	#endif
2454
2455	/* Register and immediate data == DISQPV_TYPE_IMMEDIATE */
2456	AssertReturn(param2.type == DISQPV_TYPE_IMMEDIATE, VERR_EM_INTERPRETER);
2457	RTGCUINTREG ValPar2 = param2.val.val64;
2458
2459	/* The destination is always a virtual address */
2460	AssertReturn(param1.type == DISQPV_TYPE_ADDRESS, VERR_EM_INTERPRETER);
2461
2462	RTGCPTR GCPtrPar1 = param1.val.val64;
2463	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, GCPtrPar1);
2464	PGMPAGEMAPLOCK Lock;
2465	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
2466	AssertRCReturn(rc, VERR_EM_INTERPRETER);
2467
2468	/* Try emulate it with a one-shot #PF handler in place. (RC) */
2469	Log2(("%s %RGv imm%d=%RX64\n", emGetMnemonic(pDis), GCPtrPar1, pDis->Param2.cb*8, ValPar2));
2470
2471	RTGCUINTREG32 eflags = 0;
2472	rc = pfnEmulate(pvParam1, ValPar2, pDis->Param2.cb, &eflags);
2473	PGMPhysReleasePageMappingLock(pVM, &Lock);
2474	if (RT_FAILURE(rc))
2475	{
2476	Log(("%s %RGv imm%d=%RX64-> emulation failed due to page fault!\n", emGetMnemonic(pDis), GCPtrPar1, pDis->Param2.cb*8, ValPar2));
2477	return VERR_EM_INTERPRETER;
2478	}
2479
2480	/* Update guest's eflags and finish. */
2481	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2482	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2483
2484	*pcbSize = param2.size;
2485	return VINF_SUCCESS;
2486	}
2487	#endif /* !VBOX_COMPARE_IEM_AND_EM */
2488
2489
2490	/**
2491	* ADD, ADC & SUB Emulation.
2492	*/
2493	static int emInterpretAddSub(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
2494	PFNEMULATEPARAM3 pfnEmulate)
2495	{
2496	NOREF(pvFault);
2497	DISQPVPARAMVAL param1, param2;
2498	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2499	if(RT_FAILURE(rc))
2500	return VERR_EM_INTERPRETER;
2501
2502	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2503	if(RT_FAILURE(rc))
2504	return VERR_EM_INTERPRETER;
2505
2506	#ifdef IN_RC
2507	if (TRPMHasTrap(pVCpu))
2508	{
2509	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2510	{
2511	#endif
2512	RTGCPTR pParam1;
2513	uint64_t valpar1, valpar2;
2514
2515	if (pDis->Param1.cb != pDis->Param2.cb)
2516	{
2517	if (pDis->Param1.cb < pDis->Param2.cb)
2518	{
2519	AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip, pDis->Param1.cb, pDis->Param2.cb)); /* should never happen! */
2520	return VERR_EM_INTERPRETER;
2521	}
2522	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
2523	pDis->Param2.cb = pDis->Param1.cb;
2524	param2.size = param1.size;
2525	}
2526
2527	/* The destination is always a virtual address */
2528	if (param1.type == DISQPV_TYPE_ADDRESS)
2529	{
2530	pParam1 = (RTGCPTR)param1.val.val64;
2531	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2532	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
2533	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
2534	if (RT_FAILURE(rc))
2535	{
2536	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2537	return VERR_EM_INTERPRETER;
2538	}
2539	}
2540	else
2541	{
2542	#ifndef DEBUG_bird
2543	AssertFailed();
2544	#endif
2545	return VERR_EM_INTERPRETER;
2546	}
2547
2548	/* Register or immediate data */
2549	switch(param2.type)
2550	{
2551	case DISQPV_TYPE_IMMEDIATE: /* both immediate data and register (ugly) */
2552	valpar2 = param2.val.val64;
2553	break;
2554
2555	default:
2556	AssertFailed();
2557	return VERR_EM_INTERPRETER;
2558	}
2559
2560	/* Data read, emulate instruction. */
2561	uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
2562
2563	/* Update guest's eflags and finish. */
2564	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2565	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2566
2567	/* And write it back */
2568	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, param1.size);
2569	if (RT_SUCCESS(rc))
2570	{
2571	/* All done! */
2572	*pcbSize = param2.size;
2573	return VINF_SUCCESS;
2574	}
2575	#ifdef IN_RC
2576	}
2577	}
2578	#endif
2579	return VERR_EM_INTERPRETER;
2580	}
2581
2582
2583	/**
2584	* ADC Emulation.
2585	*/
2586	static int emInterpretAdc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2587	{
2588	if (pRegFrame->eflags.Bits.u1CF)
2589	return emInterpretAddSub(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, EMEmulateAdcWithCarrySet);
2590	else
2591	return emInterpretAddSub(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, EMEmulateAdd);
2592	}
2593
2594
2595	/**
2596	* BTR/C/S Emulation.
2597	*/
2598	static int emInterpretBitTest(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
2599	PFNEMULATEPARAM2UINT32 pfnEmulate)
2600	{
2601	DISQPVPARAMVAL param1, param2;
2602	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2603	if(RT_FAILURE(rc))
2604	return VERR_EM_INTERPRETER;
2605
2606	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2607	if(RT_FAILURE(rc))
2608	return VERR_EM_INTERPRETER;
2609
2610	#ifdef IN_RC
2611	if (TRPMHasTrap(pVCpu))
2612	{
2613	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2614	{
2615	#endif
2616	RTGCPTR pParam1;
2617	uint64_t valpar1 = 0, valpar2;
2618	uint32_t eflags;
2619
2620	/* The destination is always a virtual address */
2621	if (param1.type != DISQPV_TYPE_ADDRESS)
2622	return VERR_EM_INTERPRETER;
2623
2624	pParam1 = (RTGCPTR)param1.val.val64;
2625	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2626
2627	/* Register or immediate data */
2628	switch(param2.type)
2629	{
2630	case DISQPV_TYPE_IMMEDIATE: /* both immediate data and register (ugly) */
2631	valpar2 = param2.val.val64;
2632	break;
2633
2634	default:
2635	AssertFailed();
2636	return VERR_EM_INTERPRETER;
2637	}
2638
2639	Log2(("emInterpret%s: pvFault=%RGv pParam1=%RGv val2=%x\n", emGetMnemonic(pDis), pvFault, pParam1, valpar2));
2640	pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + valpar2/8);
2641	EM_ASSERT_FAULT_RETURN((RTGCPTR)((RTGCUINTPTR)pParam1 & ~3) == pvFault, VERR_EM_INTERPRETER);
2642	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, 1);
2643	if (RT_FAILURE(rc))
2644	{
2645	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2646	return VERR_EM_INTERPRETER;
2647	}
2648
2649	Log2(("emInterpretBtx: val=%x\n", valpar1));
2650	/* Data read, emulate bit test instruction. */
2651	eflags = pfnEmulate(&valpar1, valpar2 & 0x7);
2652
2653	Log2(("emInterpretBtx: val=%x CF=%d\n", valpar1, !!(eflags & X86_EFL_CF)));
2654
2655	/* Update guest's eflags and finish. */
2656	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2657	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2658
2659	/* And write it back */
2660	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, 1);
2661	if (RT_SUCCESS(rc))
2662	{
2663	/* All done! */
2664	*pcbSize = 1;
2665	return VINF_SUCCESS;
2666	}
2667	#ifdef IN_RC
2668	}
2669	}
2670	#endif
2671	return VERR_EM_INTERPRETER;
2672	}
2673
2674
2675	#ifndef VBOX_COMPARE_IEM_AND_EM
2676	/**
2677	* LOCK BTR/C/S Emulation.
2678	*/
2679	static int emInterpretLockBitTest(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
2680	uint32_t *pcbSize, PFNEMULATELOCKPARAM2 pfnEmulate)
2681	{
2682	void *pvParam1;
2683
2684	DISQPVPARAMVAL param1, param2;
2685	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2686	if(RT_FAILURE(rc))
2687	return VERR_EM_INTERPRETER;
2688
2689	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2690	if(RT_FAILURE(rc))
2691	return VERR_EM_INTERPRETER;
2692
2693	/* The destination is always a virtual address */
2694	if (param1.type != DISQPV_TYPE_ADDRESS)
2695	return VERR_EM_INTERPRETER;
2696
2697	/* Register and immediate data == DISQPV_TYPE_IMMEDIATE */
2698	AssertReturn(param2.type == DISQPV_TYPE_IMMEDIATE, VERR_EM_INTERPRETER);
2699	uint64_t ValPar2 = param2.val.val64;
2700
2701	/* Adjust the parameters so what we're dealing with is a bit within the byte pointed to. */
2702	RTGCPTR GCPtrPar1 = param1.val.val64;
2703	GCPtrPar1 = (GCPtrPar1 + ValPar2 / 8);
2704	ValPar2 &= 7;
2705
2706	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, GCPtrPar1);
2707	#ifdef IN_RC
2708	Assert(TRPMHasTrap(pVCpu));
2709	EM_ASSERT_FAULT_RETURN((RTGCPTR)((RTGCUINTPTR)GCPtrPar1 & ~(RTGCUINTPTR)3) == pvFault, VERR_EM_INTERPRETER);
2710	#endif
2711
2712	PGMPAGEMAPLOCK Lock;
2713	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
2714	AssertRCReturn(rc, VERR_EM_INTERPRETER);
2715
2716	Log2(("emInterpretLockBitTest %s: pvFault=%RGv GCPtrPar1=%RGv imm=%RX64\n", emGetMnemonic(pDis), pvFault, GCPtrPar1, ValPar2));
2717
2718	/* Try emulate it with a one-shot #PF handler in place. (RC) */
2719	RTGCUINTREG32 eflags = 0;
2720	rc = pfnEmulate(pvParam1, ValPar2, &eflags);
2721	PGMPhysReleasePageMappingLock(pVM, &Lock);
2722	if (RT_FAILURE(rc))
2723	{
2724	Log(("emInterpretLockBitTest %s: %RGv imm%d=%RX64 -> emulation failed due to page fault!\n",
2725	emGetMnemonic(pDis), GCPtrPar1, pDis->Param2.cb*8, ValPar2));
2726	return VERR_EM_INTERPRETER;
2727	}
2728
2729	Log2(("emInterpretLockBitTest %s: GCPtrPar1=%RGv imm=%RX64 CF=%d\n", emGetMnemonic(pDis), GCPtrPar1, ValPar2, !!(eflags & X86_EFL_CF)));
2730
2731	/* Update guest's eflags and finish. */
2732	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2733	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2734
2735	*pcbSize = 1;
2736	return VINF_SUCCESS;
2737	}
2738	#endif /* !VBOX_COMPARE_IEM_AND_EM */
2739
2740
2741	/**
2742	* MOV emulation.
2743	*/
2744	static int emInterpretMov(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2745	{
2746	NOREF(pvFault);
2747	DISQPVPARAMVAL param1, param2;
2748	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2749	if(RT_FAILURE(rc))
2750	return VERR_EM_INTERPRETER;
2751
2752	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2753	if(RT_FAILURE(rc))
2754	return VERR_EM_INTERPRETER;
2755
2756	/* If destination is a segment register, punt. We can't handle it here.
2757	* NB: Source can be a register and still trigger a #PF!
2758	*/
2759	if (RT_UNLIKELY(pDis->Param1.fUse == DISUSE_REG_SEG))
2760	return VERR_EM_INTERPRETER;
2761
2762	if (param1.type == DISQPV_TYPE_ADDRESS)
2763	{
2764	RTGCPTR pDest;
2765	uint64_t val64;
2766
2767	switch(param1.type)
2768	{
2769	case DISQPV_TYPE_IMMEDIATE:
2770	if(!(param1.flags & (DISQPV_FLAG_32\|DISQPV_FLAG_64)))
2771	return VERR_EM_INTERPRETER;
2772	/* fallthru */
2773
2774	case DISQPV_TYPE_ADDRESS:
2775	pDest = (RTGCPTR)param1.val.val64;
2776	pDest = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pDest);
2777	break;
2778
2779	default:
2780	AssertFailed();
2781	return VERR_EM_INTERPRETER;
2782	}
2783
2784	switch(param2.type)
2785	{
2786	case DISQPV_TYPE_IMMEDIATE: /* register type is translated to this one too */
2787	val64 = param2.val.val64;
2788	break;
2789
2790	default:
2791	Log(("emInterpretMov: unexpected type=%d rip=%RGv\n", param2.type, (RTGCPTR)pRegFrame->rip));
2792	return VERR_EM_INTERPRETER;
2793	}
2794	#ifdef LOG_ENABLED
2795	if (pDis->uCpuMode == DISCPUMODE_64BIT)
2796	LogFlow(("EMInterpretInstruction at %RGv: OP_MOV %RGv <- %RX64 (%d) &val64=%RHv\n", (RTGCPTR)pRegFrame->rip, pDest, val64, param2.size, &val64));
2797	else
2798	LogFlow(("EMInterpretInstruction at %08RX64: OP_MOV %RGv <- %08X (%d) &val64=%RHv\n", pRegFrame->rip, pDest, (uint32_t)val64, param2.size, &val64));
2799	#endif
2800
2801	Assert(param2.size <= 8 && param2.size > 0);
2802	EM_ASSERT_FAULT_RETURN(pDest == pvFault, VERR_EM_INTERPRETER);
2803	rc = emRamWrite(pVM, pVCpu, pRegFrame, pDest, &val64, param2.size);
2804	if (RT_FAILURE(rc))
2805	return VERR_EM_INTERPRETER;
2806
2807	*pcbSize = param2.size;
2808	}
2809	#if defined(IN_RC) && defined(VBOX_WITH_RAW_RING1)
2810	/* mov xx, cs instruction is dangerous in raw mode and replaced by an 'int3' by csam/patm. */
2811	else if ( param1.type == DISQPV_TYPE_REGISTER
2812	&& param2.type == DISQPV_TYPE_REGISTER)
2813	{
2814	AssertReturn((pDis->Param1.fUse & (DISUSE_REG_GEN8\|DISUSE_REG_GEN16\|DISUSE_REG_GEN32)), VERR_EM_INTERPRETER);
2815	AssertReturn(pDis->Param2.fUse == DISUSE_REG_SEG, VERR_EM_INTERPRETER);
2816	AssertReturn(pDis->Param2.Base.idxSegReg == DISSELREG_CS, VERR_EM_INTERPRETER);
2817
2818	uint32_t u32Cpl = CPUMRCGetGuestCPL(pVCpu, pRegFrame);
2819	uint32_t uValCS = (pRegFrame->cs.Sel & ~X86_SEL_RPL) \| u32Cpl;
2820
2821	Log(("EMInterpretInstruction: OP_MOV cs=%x->%x\n", pRegFrame->cs.Sel, uValCS));
2822	switch (param1.size)
2823	{
2824	case 1: rc = DISWriteReg8(pRegFrame, pDis->Param1.Base.idxGenReg, (uint8_t) uValCS); break;
2825	case 2: rc = DISWriteReg16(pRegFrame, pDis->Param1.Base.idxGenReg, (uint16_t)uValCS); break;
2826	case 4: rc = DISWriteReg32(pRegFrame, pDis->Param1.Base.idxGenReg, (uint32_t)uValCS); break;
2827	default:
2828	AssertFailed();
2829	return VERR_EM_INTERPRETER;
2830	}
2831	AssertRCReturn(rc, rc);
2832	}
2833	#endif
2834	else
2835	{ /* read fault */
2836	RTGCPTR pSrc;
2837	uint64_t val64;
2838
2839	/* Source */
2840	switch(param2.type)
2841	{
2842	case DISQPV_TYPE_IMMEDIATE:
2843	if(!(param2.flags & (DISQPV_FLAG_32\|DISQPV_FLAG_64)))
2844	return VERR_EM_INTERPRETER;
2845	/* fallthru */
2846
2847	case DISQPV_TYPE_ADDRESS:
2848	pSrc = (RTGCPTR)param2.val.val64;
2849	pSrc = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param2, pSrc);
2850	break;
2851
2852	default:
2853	return VERR_EM_INTERPRETER;
2854	}
2855
2856	Assert(param1.size <= 8 && param1.size > 0);
2857	EM_ASSERT_FAULT_RETURN(pSrc == pvFault, VERR_EM_INTERPRETER);
2858	rc = emRamRead(pVM, pVCpu, pRegFrame, &val64, pSrc, param1.size);
2859	if (RT_FAILURE(rc))
2860	return VERR_EM_INTERPRETER;
2861
2862	/* Destination */
2863	switch(param1.type)
2864	{
2865	case DISQPV_TYPE_REGISTER:
2866	switch(param1.size)
2867	{
2868	case 1: rc = DISWriteReg8(pRegFrame, pDis->Param1.Base.idxGenReg, (uint8_t) val64); break;
2869	case 2: rc = DISWriteReg16(pRegFrame, pDis->Param1.Base.idxGenReg, (uint16_t)val64); break;
2870	case 4: rc = DISWriteReg32(pRegFrame, pDis->Param1.Base.idxGenReg, (uint32_t)val64); break;
2871	case 8: rc = DISWriteReg64(pRegFrame, pDis->Param1.Base.idxGenReg, val64); break;
2872	default:
2873	return VERR_EM_INTERPRETER;
2874	}
2875	if (RT_FAILURE(rc))
2876	return rc;
2877	break;
2878
2879	default:
2880	return VERR_EM_INTERPRETER;
2881	}
2882	#ifdef LOG_ENABLED
2883	if (pDis->uCpuMode == DISCPUMODE_64BIT)
2884	LogFlow(("EMInterpretInstruction: OP_MOV %RGv -> %RX64 (%d)\n", pSrc, val64, param1.size));
2885	else
2886	LogFlow(("EMInterpretInstruction: OP_MOV %RGv -> %08X (%d)\n", pSrc, (uint32_t)val64, param1.size));
2887	#endif
2888	}
2889	return VINF_SUCCESS;
2890	}
2891
2892
2893	#ifndef IN_RC
2894	/**
2895	* [REP] STOSWD emulation
2896	*/
2897	static int emInterpretStosWD(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2898	{
2899	int rc;
2900	RTGCPTR GCDest, GCOffset;
2901	uint32_t cbSize;
2902	uint64_t cTransfers;
2903	int offIncrement;
2904	NOREF(pvFault);
2905
2906	/* Don't support any but these three prefix bytes. */
2907	if ((pDis->fPrefix & ~(DISPREFIX_ADDRSIZE\|DISPREFIX_OPSIZE\|DISPREFIX_REP\|DISPREFIX_REX)))
2908	return VERR_EM_INTERPRETER;
2909
2910	switch (pDis->uAddrMode)
2911	{
2912	case DISCPUMODE_16BIT:
2913	GCOffset = pRegFrame->di;
2914	cTransfers = pRegFrame->cx;
2915	break;
2916	case DISCPUMODE_32BIT:
2917	GCOffset = pRegFrame->edi;
2918	cTransfers = pRegFrame->ecx;
2919	break;
2920	case DISCPUMODE_64BIT:
2921	GCOffset = pRegFrame->rdi;
2922	cTransfers = pRegFrame->rcx;
2923	break;
2924	default:
2925	AssertFailed();
2926	return VERR_EM_INTERPRETER;
2927	}
2928
2929	GCDest = SELMToFlat(pVM, DISSELREG_ES, pRegFrame, GCOffset);
2930	switch (pDis->uOpMode)
2931	{
2932	case DISCPUMODE_16BIT:
2933	cbSize = 2;
2934	break;
2935	case DISCPUMODE_32BIT:
2936	cbSize = 4;
2937	break;
2938	case DISCPUMODE_64BIT:
2939	cbSize = 8;
2940	break;
2941	default:
2942	AssertFailed();
2943	return VERR_EM_INTERPRETER;
2944	}
2945
2946	offIncrement = pRegFrame->eflags.Bits.u1DF ? -(signed)cbSize : (signed)cbSize;
2947
2948	if (!(pDis->fPrefix & DISPREFIX_REP))
2949	{
2950	LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d\n", pRegFrame->es.Sel, GCOffset, GCDest, cbSize));
2951
2952	rc = emRamWrite(pVM, pVCpu, pRegFrame, GCDest, &pRegFrame->rax, cbSize);
2953	if (RT_FAILURE(rc))
2954	return VERR_EM_INTERPRETER;
2955	Assert(rc == VINF_SUCCESS);
2956
2957	/* Update (e/r)di. */
2958	switch (pDis->uAddrMode)
2959	{
2960	case DISCPUMODE_16BIT:
2961	pRegFrame->di += offIncrement;
2962	break;
2963	case DISCPUMODE_32BIT:
2964	pRegFrame->edi += offIncrement;
2965	break;
2966	case DISCPUMODE_64BIT:
2967	pRegFrame->rdi += offIncrement;
2968	break;
2969	default:
2970	AssertFailed();
2971	return VERR_EM_INTERPRETER;
2972	}
2973
2974	}
2975	else
2976	{
2977	if (!cTransfers)
2978	return VINF_SUCCESS;
2979
2980	/*
2981	* Do not try emulate cross page stuff here because we don't know what might
2982	* be waiting for us on the subsequent pages. The caller has only asked us to
2983	* ignore access handlers fro the current page.
2984	* This also fends off big stores which would quickly kill PGMR0DynMap.
2985	*/
2986	if ( cbSize > PAGE_SIZE
2987	\|\| cTransfers > PAGE_SIZE
2988	\|\| (GCDest >> PAGE_SHIFT) != ((GCDest + offIncrement * cTransfers) >> PAGE_SHIFT))
2989	{
2990	Log(("STOSWD is crosses pages, chicken out to the recompiler; GCDest=%RGv cbSize=%#x offIncrement=%d cTransfers=%#x\n",
2991	GCDest, cbSize, offIncrement, cTransfers));
2992	return VERR_EM_INTERPRETER;
2993	}
2994
2995	LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d cTransfers=%x DF=%d\n", pRegFrame->es.Sel, GCOffset, GCDest, cbSize, cTransfers, pRegFrame->eflags.Bits.u1DF));
2996	/* Access verification first; we currently can't recover properly from traps inside this instruction */
2997	rc = PGMVerifyAccess(pVCpu, GCDest - ((offIncrement > 0) ? 0 : ((cTransfers-1) * cbSize)),
2998	cTransfers * cbSize,
2999	X86_PTE_RW \| (CPUMGetGuestCPL(pVCpu) == 3 ? X86_PTE_US : 0));
3000	if (rc != VINF_SUCCESS)
3001	{
3002	Log(("STOSWD will generate a trap -> recompiler, rc=%d\n", rc));
3003	return VERR_EM_INTERPRETER;
3004	}
3005
3006	/* REP case */
3007	while (cTransfers)
3008	{
3009	rc = emRamWrite(pVM, pVCpu, pRegFrame, GCDest, &pRegFrame->rax, cbSize);
3010	if (RT_FAILURE(rc))
3011	{
3012	rc = VERR_EM_INTERPRETER;
3013	break;
3014	}
3015
3016	Assert(rc == VINF_SUCCESS);
3017	GCOffset += offIncrement;
3018	GCDest += offIncrement;
3019	cTransfers--;
3020	}
3021
3022	/* Update the registers. */
3023	switch (pDis->uAddrMode)
3024	{
3025	case DISCPUMODE_16BIT:
3026	pRegFrame->di = GCOffset;
3027	pRegFrame->cx = cTransfers;
3028	break;
3029	case DISCPUMODE_32BIT:
3030	pRegFrame->edi = GCOffset;
3031	pRegFrame->ecx = cTransfers;
3032	break;
3033	case DISCPUMODE_64BIT:
3034	pRegFrame->rdi = GCOffset;
3035	pRegFrame->rcx = cTransfers;
3036	break;
3037	default:
3038	AssertFailed();
3039	return VERR_EM_INTERPRETER;
3040	}
3041	}
3042
3043	*pcbSize = cbSize;
3044	return rc;
3045	}
3046	#endif /* !IN_RC */
3047
3048
3049	/**
3050	* [LOCK] CMPXCHG emulation.
3051	*/
3052	static int emInterpretCmpXchg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3053	{
3054	DISQPVPARAMVAL param1, param2;
3055	NOREF(pvFault);
3056
3057	#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL_IN_R0)
3058	Assert(pDis->Param1.cb <= 4);
3059	#endif
3060
3061	/* Source to make DISQueryParamVal read the register value - ugly hack */
3062	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3063	if(RT_FAILURE(rc))
3064	return VERR_EM_INTERPRETER;
3065
3066	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
3067	if(RT_FAILURE(rc))
3068	return VERR_EM_INTERPRETER;
3069
3070	uint64_t valpar;
3071	switch(param2.type)
3072	{
3073	case DISQPV_TYPE_IMMEDIATE: /* register actually */
3074	valpar = param2.val.val64;
3075	break;
3076
3077	default:
3078	return VERR_EM_INTERPRETER;
3079	}
3080
3081	PGMPAGEMAPLOCK Lock;
3082	RTGCPTR GCPtrPar1;
3083	void *pvParam1;
3084	uint64_t eflags;
3085
3086	AssertReturn(pDis->Param1.cb == pDis->Param2.cb, VERR_EM_INTERPRETER);
3087	switch(param1.type)
3088	{
3089	case DISQPV_TYPE_ADDRESS:
3090	GCPtrPar1 = param1.val.val64;
3091	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, GCPtrPar1);
3092
3093	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
3094	AssertRCReturn(rc, VERR_EM_INTERPRETER);
3095	break;
3096
3097	default:
3098	return VERR_EM_INTERPRETER;
3099	}
3100
3101	LogFlow(("%s %RGv rax=%RX64 %RX64\n", emGetMnemonic(pDis), GCPtrPar1, pRegFrame->rax, valpar));
3102
3103	#ifndef VBOX_COMPARE_IEM_AND_EM
3104	if (pDis->fPrefix & DISPREFIX_LOCK)
3105	eflags = EMEmulateLockCmpXchg(pvParam1, &pRegFrame->rax, valpar, pDis->Param2.cb);
3106	else
3107	eflags = EMEmulateCmpXchg(pvParam1, &pRegFrame->rax, valpar, pDis->Param2.cb);
3108	#else /* VBOX_COMPARE_IEM_AND_EM */
3109	uint64_t u64;
3110	switch (pDis->Param2.cb)
3111	{
3112	case 1: u64 = (uint8_t )pvParam1; break;
3113	case 2: u64 = (uint16_t )pvParam1; break;
3114	case 4: u64 = (uint32_t )pvParam1; break;
3115	default:
3116	case 8: u64 = (uint64_t )pvParam1; break;
3117	}
3118	eflags = EMEmulateCmpXchg(&u64, &pRegFrame->rax, valpar, pDis->Param2.cb);
3119	int rc2 = emRamWrite(pVM, pVCpu, pRegFrame, GCPtrPar1, &u64, pDis->Param2.cb); AssertRCSuccess(rc2);
3120	#endif /* VBOX_COMPARE_IEM_AND_EM */
3121
3122	LogFlow(("%s %RGv rax=%RX64 %RX64 ZF=%d\n", emGetMnemonic(pDis), GCPtrPar1, pRegFrame->rax, valpar, !!(eflags & X86_EFL_ZF)));
3123
3124	/* Update guest's eflags and finish. */
3125	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
3126	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
3127
3128	*pcbSize = param2.size;
3129	PGMPhysReleasePageMappingLock(pVM, &Lock);
3130	return VINF_SUCCESS;
3131	}
3132
3133
3134	/**
3135	* [LOCK] CMPXCHG8B emulation.
3136	*/
3137	static int emInterpretCmpXchg8b(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3138	{
3139	DISQPVPARAMVAL param1;
3140	NOREF(pvFault);
3141
3142	/* Source to make DISQueryParamVal read the register value - ugly hack */
3143	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3144	if(RT_FAILURE(rc))
3145	return VERR_EM_INTERPRETER;
3146
3147	RTGCPTR GCPtrPar1;
3148	void *pvParam1;
3149	uint64_t eflags;
3150	PGMPAGEMAPLOCK Lock;
3151
3152	AssertReturn(pDis->Param1.cb == 8, VERR_EM_INTERPRETER);
3153	switch(param1.type)
3154	{
3155	case DISQPV_TYPE_ADDRESS:
3156	GCPtrPar1 = param1.val.val64;
3157	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, GCPtrPar1);
3158
3159	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
3160	AssertRCReturn(rc, VERR_EM_INTERPRETER);
3161	break;
3162
3163	default:
3164	return VERR_EM_INTERPRETER;
3165	}
3166
3167	LogFlow(("%s %RGv=%08x eax=%08x\n", emGetMnemonic(pDis), pvParam1, pRegFrame->eax));
3168
3169	#ifndef VBOX_COMPARE_IEM_AND_EM
3170	if (pDis->fPrefix & DISPREFIX_LOCK)
3171	eflags = EMEmulateLockCmpXchg8b(pvParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
3172	else
3173	eflags = EMEmulateCmpXchg8b(pvParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
3174	#else /* VBOX_COMPARE_IEM_AND_EM */
3175	uint64_t u64 = (uint64_t )pvParam1;
3176	eflags = EMEmulateCmpXchg8b(&u64, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
3177	int rc2 = emRamWrite(pVM, pVCpu, pRegFrame, GCPtrPar1, &u64, sizeof(u64)); AssertRCSuccess(rc2);
3178	#endif /* VBOX_COMPARE_IEM_AND_EM */
3179
3180	LogFlow(("%s %RGv=%08x eax=%08x ZF=%d\n", emGetMnemonic(pDis), pvParam1, pRegFrame->eax, !!(eflags & X86_EFL_ZF)));
3181
3182	/* Update guest's eflags and finish; note that only ZF is affected. */
3183	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_ZF))
3184	\| (eflags & (X86_EFL_ZF));
3185
3186	*pcbSize = 8;
3187	PGMPhysReleasePageMappingLock(pVM, &Lock);
3188	return VINF_SUCCESS;
3189	}
3190
3191
3192	#ifdef IN_RC /** @todo test+enable for HM as well. */
3193	/**
3194	* [LOCK] XADD emulation.
3195	*/
3196	static int emInterpretXAdd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3197	{
3198	Assert(pDis->uCpuMode != DISCPUMODE_64BIT); /** @todo check */
3199	DISQPVPARAMVAL param1;
3200	void *pvParamReg2;
3201	size_t cbParamReg2;
3202	NOREF(pvFault);
3203
3204	/* Source to make DISQueryParamVal read the register value - ugly hack */
3205	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3206	if(RT_FAILURE(rc))
3207	return VERR_EM_INTERPRETER;
3208
3209	rc = DISQueryParamRegPtr(pRegFrame, pDis, &pDis->Param2, &pvParamReg2, &cbParamReg2);
3210	Assert(cbParamReg2 <= 4);
3211	if(RT_FAILURE(rc))
3212	return VERR_EM_INTERPRETER;
3213
3214	#ifdef IN_RC
3215	if (TRPMHasTrap(pVCpu))
3216	{
3217	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
3218	{
3219	#endif
3220	RTGCPTR GCPtrPar1;
3221	void *pvParam1;
3222	uint32_t eflags;
3223	PGMPAGEMAPLOCK Lock;
3224
3225	AssertReturn(pDis->Param1.cb == pDis->Param2.cb, VERR_EM_INTERPRETER);
3226	switch(param1.type)
3227	{
3228	case DISQPV_TYPE_ADDRESS:
3229	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, (RTRCUINTPTR)param1.val.val64);
3230	#ifdef IN_RC
3231	EM_ASSERT_FAULT_RETURN(GCPtrPar1 == pvFault, VERR_EM_INTERPRETER);
3232	#endif
3233
3234	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
3235	AssertRCReturn(rc, VERR_EM_INTERPRETER);
3236	break;
3237
3238	default:
3239	return VERR_EM_INTERPRETER;
3240	}
3241
3242	LogFlow(("XAdd %RGv=%p reg=%08llx\n", GCPtrPar1, pvParam1, (uint64_t )pvParamReg2));
3243
3244	#ifndef VBOX_COMPARE_IEM_AND_EM
3245	if (pDis->fPrefix & DISPREFIX_LOCK)
3246	eflags = EMEmulateLockXAdd(pvParam1, pvParamReg2, cbParamReg2);
3247	else
3248	eflags = EMEmulateXAdd(pvParam1, pvParamReg2, cbParamReg2);
3249	#else /* VBOX_COMPARE_IEM_AND_EM */
3250	uint64_t u64;
3251	switch (cbParamReg2)
3252	{
3253	case 1: u64 = (uint8_t )pvParam1; break;
3254	case 2: u64 = (uint16_t )pvParam1; break;
3255	case 4: u64 = (uint32_t )pvParam1; break;
3256	default:
3257	case 8: u64 = (uint64_t )pvParam1; break;
3258	}
3259	eflags = EMEmulateXAdd(&u64, pvParamReg2, cbParamReg2);
3260	int rc2 = emRamWrite(pVM, pVCpu, pRegFrame, GCPtrPar1, &u64, pDis->Param2.cb); AssertRCSuccess(rc2);
3261	#endif /* VBOX_COMPARE_IEM_AND_EM */
3262
3263	LogFlow(("XAdd %RGv=%p reg=%08llx ZF=%d\n", GCPtrPar1, pvParam1, (uint64_t )pvParamReg2, !!(eflags & X86_EFL_ZF) ));
3264
3265	/* Update guest's eflags and finish. */
3266	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
3267	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
3268
3269	*pcbSize = cbParamReg2;
3270	PGMPhysReleasePageMappingLock(pVM, &Lock);
3271	return VINF_SUCCESS;
3272	#ifdef IN_RC
3273	}
3274	}
3275
3276	return VERR_EM_INTERPRETER;
3277	#endif
3278	}
3279	#endif /* IN_RC */
3280
3281
3282	/**
3283	* WBINVD Emulation.
3284	*/
3285	static int emInterpretWbInvd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3286	{
3287	/* Nothing to do. */
3288	NOREF(pVM); NOREF(pVCpu); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
3289	return VINF_SUCCESS;
3290	}
3291
3292
3293	/**
3294	* INVLPG Emulation.
3295	*/
3296	static VBOXSTRICTRC emInterpretInvlPg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3297	{
3298	DISQPVPARAMVAL param1;
3299	RTGCPTR addr;
3300	NOREF(pvFault); NOREF(pVM); NOREF(pcbSize);
3301
3302	VBOXSTRICTRC rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3303	if(RT_FAILURE(rc))
3304	return VERR_EM_INTERPRETER;
3305
3306	switch(param1.type)
3307	{
3308	case DISQPV_TYPE_IMMEDIATE:
3309	case DISQPV_TYPE_ADDRESS:
3310	if(!(param1.flags & (DISQPV_FLAG_32\|DISQPV_FLAG_64)))
3311	return VERR_EM_INTERPRETER;
3312	addr = (RTGCPTR)param1.val.val64;
3313	break;
3314
3315	default:
3316	return VERR_EM_INTERPRETER;
3317	}
3318
3319	/** @todo is addr always a flat linear address or ds based
3320	* (in absence of segment override prefixes)????
3321	*/
3322	#ifdef IN_RC
3323	LogFlow(("RC: EMULATE: invlpg %RGv\n", addr));
3324	#endif
3325	rc = PGMInvalidatePage(pVCpu, addr);
3326	if ( rc == VINF_SUCCESS
3327	\|\| rc == VINF_PGM_SYNC_CR3 /* we can rely on the FF */)
3328	return VINF_SUCCESS;
3329	AssertMsgReturn(rc == VINF_EM_RAW_EMULATE_INSTR,
3330	("%Rrc addr=%RGv\n", VBOXSTRICTRC_VAL(rc), addr),
3331	VERR_EM_INTERPRETER);
3332	return rc;
3333	}
3334
3335	/** @todo change all these EMInterpretXXX methods to VBOXSTRICTRC. */
3336
3337	/**
3338	* CPUID Emulation.
3339	*/
3340	static int emInterpretCpuId(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3341	{
3342	NOREF(pVM); NOREF(pVCpu); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
3343	int rc = EMInterpretCpuId(pVM, pVCpu, pRegFrame);
3344	return rc;
3345	}
3346
3347
3348	/**
3349	* CLTS Emulation.
3350	*/
3351	static int emInterpretClts(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3352	{
3353	NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
3354	return EMInterpretCLTS(pVM, pVCpu);
3355	}
3356
3357
3358	/**
3359	* LMSW Emulation.
3360	*/
3361	static int emInterpretLmsw(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3362	{
3363	DISQPVPARAMVAL param1;
3364	uint32_t val;
3365	NOREF(pvFault); NOREF(pcbSize);
3366
3367	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3368	if(RT_FAILURE(rc))
3369	return VERR_EM_INTERPRETER;
3370
3371	switch(param1.type)
3372	{
3373	case DISQPV_TYPE_IMMEDIATE:
3374	case DISQPV_TYPE_ADDRESS:
3375	if(!(param1.flags & DISQPV_FLAG_16))
3376	return VERR_EM_INTERPRETER;
3377	val = param1.val.val32;
3378	break;
3379
3380	default:
3381	return VERR_EM_INTERPRETER;
3382	}
3383
3384	LogFlow(("emInterpretLmsw %x\n", val));
3385	return EMInterpretLMSW(pVM, pVCpu, pRegFrame, val);
3386	}
3387
3388	#ifdef EM_EMULATE_SMSW
3389	/**
3390	* SMSW Emulation.
3391	*/
3392	static int emInterpretSmsw(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3393	{
3394	NOREF(pvFault); NOREF(pcbSize);
3395	DISQPVPARAMVAL param1;
3396	uint64_t cr0 = CPUMGetGuestCR0(pVCpu);
3397
3398	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3399	if(RT_FAILURE(rc))
3400	return VERR_EM_INTERPRETER;
3401
3402	switch(param1.type)
3403	{
3404	case DISQPV_TYPE_IMMEDIATE:
3405	if(param1.size != sizeof(uint16_t))
3406	return VERR_EM_INTERPRETER;
3407	LogFlow(("emInterpretSmsw %d <- cr0 (%x)\n", pDis->Param1.Base.idxGenReg, cr0));
3408	rc = DISWriteReg16(pRegFrame, pDis->Param1.Base.idxGenReg, cr0);
3409	break;
3410
3411	case DISQPV_TYPE_ADDRESS:
3412	{
3413	RTGCPTR pParam1;
3414
3415	/* Actually forced to 16 bits regardless of the operand size. */
3416	if(param1.size != sizeof(uint16_t))
3417	return VERR_EM_INTERPRETER;
3418
3419	pParam1 = (RTGCPTR)param1.val.val64;
3420	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
3421	LogFlow(("emInterpretSmsw %RGv <- cr0 (%x)\n", pParam1, cr0));
3422
3423	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &cr0, sizeof(uint16_t));
3424	if (RT_FAILURE(rc))
3425	{
3426	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
3427	return VERR_EM_INTERPRETER;
3428	}
3429	break;
3430	}
3431
3432	default:
3433	return VERR_EM_INTERPRETER;
3434	}
3435
3436	LogFlow(("emInterpretSmsw %x\n", cr0));
3437	return rc;
3438	}
3439	#endif
3440
3441	/**
3442	* MOV CRx
3443	*/
3444	static int emInterpretMovCRx(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3445	{
3446	NOREF(pvFault); NOREF(pcbSize);
3447	if ((pDis->Param1.fUse == DISUSE_REG_GEN32 \|\| pDis->Param1.fUse == DISUSE_REG_GEN64) && pDis->Param2.fUse == DISUSE_REG_CR)
3448	return EMInterpretCRxRead(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxGenReg, pDis->Param2.Base.idxCtrlReg);
3449
3450	if (pDis->Param1.fUse == DISUSE_REG_CR && (pDis->Param2.fUse == DISUSE_REG_GEN32 \|\| pDis->Param2.fUse == DISUSE_REG_GEN64))
3451	return EMInterpretCRxWrite(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxCtrlReg, pDis->Param2.Base.idxGenReg);
3452
3453	AssertMsgFailedReturn(("Unexpected control register move\n"), VERR_EM_INTERPRETER);
3454	}
3455
3456
3457	/**
3458	* MOV DRx
3459	*/
3460	static int emInterpretMovDRx(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3461	{
3462	int rc = VERR_EM_INTERPRETER;
3463	NOREF(pvFault); NOREF(pcbSize);
3464
3465	if((pDis->Param1.fUse == DISUSE_REG_GEN32 \|\| pDis->Param1.fUse == DISUSE_REG_GEN64) && pDis->Param2.fUse == DISUSE_REG_DBG)
3466	{
3467	rc = EMInterpretDRxRead(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxGenReg, pDis->Param2.Base.idxDbgReg);
3468	}
3469	else
3470	if(pDis->Param1.fUse == DISUSE_REG_DBG && (pDis->Param2.fUse == DISUSE_REG_GEN32 \|\| pDis->Param2.fUse == DISUSE_REG_GEN64))
3471	{
3472	rc = EMInterpretDRxWrite(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxDbgReg, pDis->Param2.Base.idxGenReg);
3473	}
3474	else
3475	AssertMsgFailed(("Unexpected debug register move\n"));
3476
3477	return rc;
3478	}
3479
3480
3481	/**
3482	* LLDT Emulation.
3483	*/
3484	static int emInterpretLLdt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3485	{
3486	DISQPVPARAMVAL param1;
3487	RTSEL sel;
3488	NOREF(pVM); NOREF(pvFault); NOREF(pcbSize);
3489
3490	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3491	if(RT_FAILURE(rc))
3492	return VERR_EM_INTERPRETER;
3493
3494	switch(param1.type)
3495	{
3496	case DISQPV_TYPE_ADDRESS:
3497	return VERR_EM_INTERPRETER; //feeling lazy right now
3498
3499	case DISQPV_TYPE_IMMEDIATE:
3500	if(!(param1.flags & DISQPV_FLAG_16))
3501	return VERR_EM_INTERPRETER;
3502	sel = (RTSEL)param1.val.val16;
3503	break;
3504
3505	default:
3506	return VERR_EM_INTERPRETER;
3507	}
3508
3509	#ifdef IN_RING0
3510	/* Only for the VT-x real-mode emulation case. */
3511	AssertReturn(CPUMIsGuestInRealMode(pVCpu), VERR_EM_INTERPRETER);
3512	CPUMSetGuestLDTR(pVCpu, sel);
3513	return VINF_SUCCESS;
3514	#else
3515	if (sel == 0)
3516	{
3517	if (CPUMGetHyperLDTR(pVCpu) == 0)
3518	{
3519	// this simple case is most frequent in Windows 2000 (31k - boot & shutdown)
3520	return VINF_SUCCESS;
3521	}
3522	}
3523	//still feeling lazy
3524	return VERR_EM_INTERPRETER;
3525	#endif
3526	}
3527
3528	#ifdef IN_RING0
3529	/**
3530	* LIDT/LGDT Emulation.
3531	*/
3532	static int emInterpretLIGdt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3533	{
3534	DISQPVPARAMVAL param1;
3535	RTGCPTR pParam1;
3536	X86XDTR32 dtr32;
3537	NOREF(pvFault); NOREF(pcbSize);
3538
3539	Log(("Emulate %s at %RGv\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip));
3540
3541	/* Only for the VT-x real-mode emulation case. */
3542	AssertReturn(CPUMIsGuestInRealMode(pVCpu), VERR_EM_INTERPRETER);
3543
3544	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3545	if(RT_FAILURE(rc))
3546	return VERR_EM_INTERPRETER;
3547
3548	switch(param1.type)
3549	{
3550	case DISQPV_TYPE_ADDRESS:
3551	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, param1.val.val16);
3552	break;
3553
3554	default:
3555	return VERR_EM_INTERPRETER;
3556	}
3557
3558	rc = emRamRead(pVM, pVCpu, pRegFrame, &dtr32, pParam1, sizeof(dtr32));
3559	AssertRCReturn(rc, VERR_EM_INTERPRETER);
3560
3561	if (!(pDis->fPrefix & DISPREFIX_OPSIZE))
3562	dtr32.uAddr &= 0xffffff; /* 16 bits operand size */
3563
3564	if (pDis->pCurInstr->uOpcode == OP_LIDT)
3565	CPUMSetGuestIDTR(pVCpu, dtr32.uAddr, dtr32.cb);
3566	else
3567	CPUMSetGuestGDTR(pVCpu, dtr32.uAddr, dtr32.cb);
3568
3569	return VINF_SUCCESS;
3570	}
3571	#endif
3572
3573
3574	#ifdef IN_RC
3575	/**
3576	* STI Emulation.
3577	*
3578	* @remark the instruction following sti is guaranteed to be executed before any interrupts are dispatched
3579	*/
3580	static int emInterpretSti(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3581	{
3582	NOREF(pcbSize);
3583	PPATMGCSTATE pGCState = PATMGetGCState(pVM);
3584
3585	if(!pGCState)
3586	{
3587	Assert(pGCState);
3588	return VERR_EM_INTERPRETER;
3589	}
3590	pGCState->uVMFlags \|= X86_EFL_IF;
3591
3592	Assert(pRegFrame->eflags.u32 & X86_EFL_IF);
3593	Assert(pvFault == SELMToFlat(pVM, DISSELREG_CS, pRegFrame, (RTGCPTR)pRegFrame->rip));
3594
3595	pVCpu->em.s.GCPtrInhibitInterrupts = pRegFrame->eip + pDis->cbInstr;
3596	VMCPU_FF_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
3597
3598	return VINF_SUCCESS;
3599	}
3600	#endif /* IN_RC */
3601
3602
3603	/**
3604	* HLT Emulation.
3605	*/
3606	static VBOXSTRICTRC
3607	emInterpretHlt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3608	{
3609	NOREF(pVM); NOREF(pVCpu); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
3610	return VINF_EM_HALT;
3611	}
3612
3613
3614	/**
3615	* RDTSC Emulation.
3616	*/
3617	static int emInterpretRdtsc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3618	{
3619	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3620	return EMInterpretRdtsc(pVM, pVCpu, pRegFrame);
3621	}
3622
3623	/**
3624	* RDPMC Emulation
3625	*/
3626	static int emInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3627	{
3628	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3629	return EMInterpretRdpmc(pVM, pVCpu, pRegFrame);
3630	}
3631
3632
3633	static int emInterpretMonitor(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3634	{
3635	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3636	return EMInterpretMonitor(pVM, pVCpu, pRegFrame);
3637	}
3638
3639
3640	static VBOXSTRICTRC emInterpretMWait(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3641	{
3642	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3643	return EMInterpretMWait(pVM, pVCpu, pRegFrame);
3644	}
3645
3646
3647	/**
3648	* RDMSR Emulation.
3649	*/
3650	static int emInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3651	{
3652	/* Note: The Intel manual claims there's a REX version of RDMSR that's slightly
3653	different, so we play safe by completely disassembling the instruction. */
3654	Assert(!(pDis->fPrefix & DISPREFIX_REX));
3655	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3656	return EMInterpretRdmsr(pVM, pVCpu, pRegFrame);
3657	}
3658
3659
3660	/**
3661	* WRMSR Emulation.
3662	*/
3663	static int emInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3664	{
3665	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3666	return EMInterpretWrmsr(pVM, pVCpu, pRegFrame);
3667	}
3668
3669
3670	/**
3671	* Internal worker.
3672	* @copydoc emInterpretInstructionCPUOuter
3673	*/
3674	DECLINLINE(VBOXSTRICTRC) emInterpretInstructionCPU(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
3675	RTGCPTR pvFault, EMCODETYPE enmCodeType, uint32_t *pcbSize)
3676	{
3677	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
3678	Assert(enmCodeType == EMCODETYPE_SUPERVISOR \|\| enmCodeType == EMCODETYPE_ALL);
3679	Assert(pcbSize);
3680	*pcbSize = 0;
3681
3682	if (enmCodeType == EMCODETYPE_SUPERVISOR)
3683	{
3684	/*
3685	* Only supervisor guest code!!
3686	* And no complicated prefixes.
3687	*/
3688	/* Get the current privilege level. */
3689	uint32_t cpl = CPUMGetGuestCPL(pVCpu);
3690	#ifdef VBOX_WITH_RAW_RING1
3691	if ( !EMIsRawRing1Enabled(pVM)
3692	\|\| cpl > 1
3693	\|\| pRegFrame->eflags.Bits.u2IOPL > cpl
3694	)
3695	#endif
3696	{
3697	if ( cpl != 0
3698	&& pDis->pCurInstr->uOpcode != OP_RDTSC) /* rdtsc requires emulation in ring 3 as well */
3699	{
3700	Log(("WARNING: refusing instruction emulation for user-mode code!!\n"));
3701	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedUserMode));
3702	return VERR_EM_INTERPRETER;
3703	}
3704	}
3705	}
3706	else
3707	Log2(("emInterpretInstructionCPU allowed to interpret user-level code!!\n"));
3708
3709	#ifdef IN_RC
3710	if ( (pDis->fPrefix & (DISPREFIX_REPNE \| DISPREFIX_REP))
3711	\|\| ( (pDis->fPrefix & DISPREFIX_LOCK)
3712	&& pDis->pCurInstr->uOpcode != OP_CMPXCHG
3713	&& pDis->pCurInstr->uOpcode != OP_CMPXCHG8B
3714	&& pDis->pCurInstr->uOpcode != OP_XADD
3715	&& pDis->pCurInstr->uOpcode != OP_OR
3716	&& pDis->pCurInstr->uOpcode != OP_AND
3717	&& pDis->pCurInstr->uOpcode != OP_XOR
3718	&& pDis->pCurInstr->uOpcode != OP_BTR
3719	)
3720	)
3721	#else
3722	if ( (pDis->fPrefix & DISPREFIX_REPNE)
3723	\|\| ( (pDis->fPrefix & DISPREFIX_REP)
3724	&& pDis->pCurInstr->uOpcode != OP_STOSWD
3725	)
3726	\|\| ( (pDis->fPrefix & DISPREFIX_LOCK)
3727	&& pDis->pCurInstr->uOpcode != OP_OR
3728	&& pDis->pCurInstr->uOpcode != OP_AND
3729	&& pDis->pCurInstr->uOpcode != OP_XOR
3730	&& pDis->pCurInstr->uOpcode != OP_BTR
3731	&& pDis->pCurInstr->uOpcode != OP_CMPXCHG
3732	&& pDis->pCurInstr->uOpcode != OP_CMPXCHG8B
3733	)
3734	)
3735	#endif
3736	{
3737	//Log(("EMInterpretInstruction: wrong prefix!!\n"));
3738	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedPrefix));
3739	Log4(("EM: Refuse %u on REP/REPNE/LOCK prefix grounds\n", pDis->pCurInstr->uOpcode));
3740	return VERR_EM_INTERPRETER;
3741	}
3742
3743	#if HC_ARCH_BITS == 32
3744	/*
3745	* Unable to emulate most >4 bytes accesses in 32 bits mode.
3746	* Whitelisted instructions are safe.
3747	*/
3748	if ( pDis->Param1.cb > 4
3749	&& CPUMIsGuestIn64BitCode(pVCpu))
3750	{
3751	uint32_t uOpCode = pDis->pCurInstr->uOpcode;
3752	if ( uOpCode != OP_STOSWD
3753	&& uOpCode != OP_MOV
3754	&& uOpCode != OP_CMPXCHG8B
3755	&& uOpCode != OP_XCHG
3756	&& uOpCode != OP_BTS
3757	&& uOpCode != OP_BTR
3758	&& uOpCode != OP_BTC
3759	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL_IN_R0
3760	&& uOpCode != OP_CMPXCHG /* solaris */
3761	&& uOpCode != OP_AND /* windows */
3762	&& uOpCode != OP_OR /* windows */
3763	&& uOpCode != OP_XOR /* because we can */
3764	&& uOpCode != OP_ADD /* windows (dripple) */
3765	&& uOpCode != OP_ADC /* because we can */
3766	&& uOpCode != OP_SUB /* because we can */
3767	/** @todo OP_BTS or is that a different kind of failure? */
3768	# endif
3769	)
3770	{
3771	# ifdef VBOX_WITH_STATISTICS
3772	switch (pDis->pCurInstr->uOpcode)
3773	{
3774	# define INTERPRET_FAILED_CASE(opcode, Instr) \
3775	case opcode: STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); break;
3776	INTERPRET_FAILED_CASE(OP_XCHG,Xchg);
3777	INTERPRET_FAILED_CASE(OP_DEC,Dec);
3778	INTERPRET_FAILED_CASE(OP_INC,Inc);
3779	INTERPRET_FAILED_CASE(OP_POP,Pop);
3780	INTERPRET_FAILED_CASE(OP_OR, Or);
3781	INTERPRET_FAILED_CASE(OP_XOR,Xor);
3782	INTERPRET_FAILED_CASE(OP_AND,And);
3783	INTERPRET_FAILED_CASE(OP_MOV,Mov);
3784	INTERPRET_FAILED_CASE(OP_STOSWD,StosWD);
3785	INTERPRET_FAILED_CASE(OP_INVLPG,InvlPg);
3786	INTERPRET_FAILED_CASE(OP_CPUID,CpuId);
3787	INTERPRET_FAILED_CASE(OP_MOV_CR,MovCRx);
3788	INTERPRET_FAILED_CASE(OP_MOV_DR,MovDRx);
3789	INTERPRET_FAILED_CASE(OP_LLDT,LLdt);
3790	INTERPRET_FAILED_CASE(OP_LIDT,LIdt);
3791	INTERPRET_FAILED_CASE(OP_LGDT,LGdt);
3792	INTERPRET_FAILED_CASE(OP_LMSW,Lmsw);
3793	INTERPRET_FAILED_CASE(OP_CLTS,Clts);
3794	INTERPRET_FAILED_CASE(OP_MONITOR,Monitor);
3795	INTERPRET_FAILED_CASE(OP_MWAIT,MWait);
3796	INTERPRET_FAILED_CASE(OP_RDMSR,Rdmsr);
3797	INTERPRET_FAILED_CASE(OP_WRMSR,Wrmsr);
3798	INTERPRET_FAILED_CASE(OP_ADD,Add);
3799	INTERPRET_FAILED_CASE(OP_SUB,Sub);
3800	INTERPRET_FAILED_CASE(OP_ADC,Adc);
3801	INTERPRET_FAILED_CASE(OP_BTR,Btr);
3802	INTERPRET_FAILED_CASE(OP_BTS,Bts);
3803	INTERPRET_FAILED_CASE(OP_BTC,Btc);
3804	INTERPRET_FAILED_CASE(OP_RDTSC,Rdtsc);
3805	INTERPRET_FAILED_CASE(OP_CMPXCHG, CmpXchg);
3806	INTERPRET_FAILED_CASE(OP_STI, Sti);
3807	INTERPRET_FAILED_CASE(OP_XADD,XAdd);
3808	INTERPRET_FAILED_CASE(OP_CMPXCHG8B,CmpXchg8b);
3809	INTERPRET_FAILED_CASE(OP_HLT, Hlt);
3810	INTERPRET_FAILED_CASE(OP_IRET,Iret);
3811	INTERPRET_FAILED_CASE(OP_WBINVD,WbInvd);
3812	INTERPRET_FAILED_CASE(OP_MOVNTPS,MovNTPS);
3813	# undef INTERPRET_FAILED_CASE
3814	default:
3815	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedMisc));
3816	break;
3817	}
3818	# endif /* VBOX_WITH_STATISTICS */
3819	Log4(("EM: Refuse %u on grounds of accessing %u bytes\n", pDis->pCurInstr->uOpcode, pDis->Param1.cb));
3820	return VERR_EM_INTERPRETER;
3821	}
3822	}
3823	#endif
3824
3825	VBOXSTRICTRC rc;
3826	#if (defined(VBOX_STRICT) \|\| defined(LOG_ENABLED))
3827	LogFlow(("emInterpretInstructionCPU %s\n", emGetMnemonic(pDis)));
3828	#endif
3829	switch (pDis->pCurInstr->uOpcode)
3830	{
3831	/*
3832	* Macros for generating the right case statements.
3833	*/
3834	# ifndef VBOX_COMPARE_IEM_AND_EM
3835	# define INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
3836	case opcode:\
3837	if (pDis->fPrefix & DISPREFIX_LOCK) \
3838	rc = emInterpretLock##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulateLock); \
3839	else \
3840	rc = emInterpret##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulate); \
3841	if (RT_SUCCESS(rc)) \
3842	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3843	else \
3844	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3845	return rc
3846	# else /* VBOX_COMPARE_IEM_AND_EM */
3847	# define INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
3848	case opcode:\
3849	rc = emInterpret##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulate); \
3850	if (RT_SUCCESS(rc)) \
3851	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3852	else \
3853	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3854	return rc
3855	# endif /* VBOX_COMPARE_IEM_AND_EM */
3856
3857	#define INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate) \
3858	case opcode:\
3859	rc = emInterpret##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulate); \
3860	if (RT_SUCCESS(rc)) \
3861	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3862	else \
3863	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3864	return rc
3865
3866	#define INTERPRET_CASE_EX_PARAM2(opcode, Instr, InstrFn, pfnEmulate) \
3867	INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate)
3868	#define INTERPRET_CASE_EX_LOCK_PARAM2(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
3869	INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock)
3870
3871	#define INTERPRET_CASE(opcode, Instr) \
3872	case opcode:\
3873	rc = emInterpret##Instr(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize); \
3874	if (RT_SUCCESS(rc)) \
3875	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3876	else \
3877	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3878	return rc
3879
3880	#define INTERPRET_CASE_EX_DUAL_PARAM2(opcode, Instr, InstrFn) \
3881	case opcode:\
3882	rc = emInterpret##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize); \
3883	if (RT_SUCCESS(rc)) \
3884	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3885	else \
3886	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3887	return rc
3888
3889	#define INTERPRET_STAT_CASE(opcode, Instr) \
3890	case opcode: STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); return VERR_EM_INTERPRETER;
3891
3892	/*
3893	* The actual case statements.
3894	*/
3895	INTERPRET_CASE(OP_XCHG,Xchg);
3896	INTERPRET_CASE_EX_PARAM2(OP_DEC,Dec, IncDec, EMEmulateDec);
3897	INTERPRET_CASE_EX_PARAM2(OP_INC,Inc, IncDec, EMEmulateInc);
3898	INTERPRET_CASE(OP_POP,Pop);
3899	INTERPRET_CASE_EX_LOCK_PARAM3(OP_OR, Or, OrXorAnd, EMEmulateOr, EMEmulateLockOr);
3900	INTERPRET_CASE_EX_LOCK_PARAM3(OP_XOR,Xor, OrXorAnd, EMEmulateXor, EMEmulateLockXor);
3901	INTERPRET_CASE_EX_LOCK_PARAM3(OP_AND,And, OrXorAnd, EMEmulateAnd, EMEmulateLockAnd);
3902	INTERPRET_CASE(OP_MOV,Mov);
3903	#ifndef IN_RC
3904	INTERPRET_CASE(OP_STOSWD,StosWD);
3905	#endif
3906	INTERPRET_CASE(OP_INVLPG,InvlPg);
3907	INTERPRET_CASE(OP_CPUID,CpuId);
3908	INTERPRET_CASE(OP_MOV_CR,MovCRx);
3909	INTERPRET_CASE(OP_MOV_DR,MovDRx);
3910	#ifdef IN_RING0
3911	INTERPRET_CASE_EX_DUAL_PARAM2(OP_LIDT, LIdt, LIGdt);
3912	INTERPRET_CASE_EX_DUAL_PARAM2(OP_LGDT, LGdt, LIGdt);
3913	#endif
3914	INTERPRET_CASE(OP_LLDT,LLdt);
3915	INTERPRET_CASE(OP_LMSW,Lmsw);
3916	#ifdef EM_EMULATE_SMSW
3917	INTERPRET_CASE(OP_SMSW,Smsw);
3918	#endif
3919	INTERPRET_CASE(OP_CLTS,Clts);
3920	INTERPRET_CASE(OP_MONITOR, Monitor);
3921	INTERPRET_CASE(OP_MWAIT, MWait);
3922	INTERPRET_CASE(OP_RDMSR, Rdmsr);
3923	INTERPRET_CASE(OP_WRMSR, Wrmsr);
3924	INTERPRET_CASE_EX_PARAM3(OP_ADD,Add, AddSub, EMEmulateAdd);
3925	INTERPRET_CASE_EX_PARAM3(OP_SUB,Sub, AddSub, EMEmulateSub);
3926	INTERPRET_CASE(OP_ADC,Adc);
3927	INTERPRET_CASE_EX_LOCK_PARAM2(OP_BTR,Btr, BitTest, EMEmulateBtr, EMEmulateLockBtr);
3928	INTERPRET_CASE_EX_PARAM2(OP_BTS,Bts, BitTest, EMEmulateBts);
3929	INTERPRET_CASE_EX_PARAM2(OP_BTC,Btc, BitTest, EMEmulateBtc);
3930	INTERPRET_CASE(OP_RDPMC,Rdpmc);
3931	INTERPRET_CASE(OP_RDTSC,Rdtsc);
3932	INTERPRET_CASE(OP_CMPXCHG, CmpXchg);
3933	#ifdef IN_RC
3934	INTERPRET_CASE(OP_STI,Sti);
3935	INTERPRET_CASE(OP_XADD, XAdd);
3936	INTERPRET_CASE(OP_IRET,Iret);
3937	#endif
3938	INTERPRET_CASE(OP_CMPXCHG8B, CmpXchg8b);
3939	INTERPRET_CASE(OP_HLT,Hlt);
3940	INTERPRET_CASE(OP_WBINVD,WbInvd);
3941	#ifdef VBOX_WITH_STATISTICS
3942	# ifndef IN_RC
3943	INTERPRET_STAT_CASE(OP_XADD, XAdd);
3944	# endif
3945	INTERPRET_STAT_CASE(OP_MOVNTPS,MovNTPS);
3946	#endif
3947
3948	default:
3949	Log3(("emInterpretInstructionCPU: opcode=%d\n", pDis->pCurInstr->uOpcode));
3950	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedMisc));
3951	return VERR_EM_INTERPRETER;
3952
3953	#undef INTERPRET_CASE_EX_PARAM2
3954	#undef INTERPRET_STAT_CASE
3955	#undef INTERPRET_CASE_EX
3956	#undef INTERPRET_CASE
3957	} /* switch (opcode) */
3958	/* not reached */
3959	}
3960
3961	/**
3962	* Interprets the current instruction using the supplied DISCPUSTATE structure.
3963	*
3964	* EIP is NOT updated!
3965	*
3966	* @returns VBox strict status code.
3967	* @retval VINF_* Scheduling instructions. When these are returned, it
3968	* starts to get a bit tricky to know whether code was
3969	* executed or not... We'll address this when it becomes a problem.
3970	* @retval VERR_EM_INTERPRETER Something we can't cope with.
3971	* @retval VERR_* Fatal errors.
3972	*
3973	* @param pVCpu Pointer to the VMCPU.
3974	* @param pDis The disassembler cpu state for the instruction to be
3975	* interpreted.
3976	* @param pRegFrame The register frame. EIP is NOT changed!
3977	* @param pvFault The fault address (CR2).
3978	* @param pcbSize Size of the write (if applicable).
3979	* @param enmCodeType Code type (user/supervisor)
3980	*
3981	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
3982	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
3983	* to worry about e.g. invalid modrm combinations (!)
3984	*
3985	* @todo At this time we do NOT check if the instruction overwrites vital information.
3986	* Make sure this can't happen!! (will add some assertions/checks later)
3987	*/
3988	DECLINLINE(VBOXSTRICTRC) emInterpretInstructionCPUOuter(PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
3989	RTGCPTR pvFault, EMCODETYPE enmCodeType, uint32_t *pcbSize)
3990	{
3991	STAM_PROFILE_START(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Emulate), a);
3992	VBOXSTRICTRC rc = emInterpretInstructionCPU(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, pRegFrame, pvFault, enmCodeType, pcbSize);
3993	STAM_PROFILE_STOP(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Emulate), a);
3994	if (RT_SUCCESS(rc))
3995	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InterpretSucceeded));
3996	else
3997	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InterpretFailed));
3998	return rc;
3999	}
4000
4001
4002	#endif /* !VBOX_WITH_IEM */

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source: vbox/trunk/src/VBox/VMM/VMMAll/EMAll.cpp@ 54834

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