EMAll.cpp@ 57952

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1	/* $Id: EMAll.cpp 57860 2015-09-22 14:57:16Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor(/Manager) - All contexts
4	*/
5
6	/*
7	* Copyright (C) 2006-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_EM
23	#include <VBox/vmm/em.h>
24	#include <VBox/vmm/mm.h>
25	#include <VBox/vmm/selm.h>
26	#include <VBox/vmm/patm.h>
27	#include <VBox/vmm/csam.h>
28	#include <VBox/vmm/pgm.h>
29	#ifdef VBOX_WITH_IEM
30	# include <VBox/vmm/iem.h>
31	#endif
32	#include <VBox/vmm/iom.h>
33	#include <VBox/vmm/stam.h>
34	#include "EMInternal.h"
35	#include <VBox/vmm/vm.h>
36	#include <VBox/vmm/vmm.h>
37	#include <VBox/vmm/hm.h>
38	#include <VBox/vmm/tm.h>
39	#include <VBox/vmm/pdmapi.h>
40	#include <VBox/param.h>
41	#include <VBox/err.h>
42	#include <VBox/dis.h>
43	#include <VBox/disopcode.h>
44	#include <VBox/log.h>
45	#include "internal/pgm.h"
46	#include <iprt/assert.h>
47	#include <iprt/asm.h>
48	#include <iprt/string.h>
49
50	#ifndef IN_RC
51	#undef VBOX_WITH_IEM
52	#endif
53	#ifdef VBOX_WITH_IEM
54	//# define VBOX_COMPARE_IEM_AND_EM /* debugging... */
55	//# define VBOX_SAME_AS_EM
56	//# define VBOX_COMPARE_IEM_LAST
57	#endif
58
59	#ifdef VBOX_WITH_RAW_RING1
60	# define EM_EMULATE_SMSW
61	#endif
62
63
64	/*********************************************************************************************************************************
65	* Defined Constants And Macros *
66	*********************************************************************************************************************************/
67	/** @def EM_ASSERT_FAULT_RETURN
68	* Safety check.
69	*
70	* Could in theory misfire on a cross page boundary access...
71	*
72	* Currently disabled because the CSAM (+ PATM) patch monitoring occasionally
73	* turns up an alias page instead of the original faulting one and annoying the
74	* heck out of anyone running a debug build. See @bugref{2609} and @bugref{1931}.
75	*/
76	#if 0
77	# define EM_ASSERT_FAULT_RETURN(expr, rc) AssertReturn(expr, rc)
78	#else
79	# define EM_ASSERT_FAULT_RETURN(expr, rc) do { } while (0)
80	#endif
81
82
83	/*********************************************************************************************************************************
84	* Internal Functions *
85	*********************************************************************************************************************************/
86	#if !defined(VBOX_WITH_IEM) \|\| defined(VBOX_COMPARE_IEM_AND_EM)
87	DECLINLINE(VBOXSTRICTRC) emInterpretInstructionCPUOuter(PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
88	RTGCPTR pvFault, EMCODETYPE enmCodeType, uint32_t *pcbSize);
89	#endif
90
91
92	/*********************************************************************************************************************************
93	* Global Variables *
94	*********************************************************************************************************************************/
95	#ifdef VBOX_COMPARE_IEM_AND_EM
96	static const uint32_t g_fInterestingFFs = VMCPU_FF_TO_R3
97	\| VMCPU_FF_CSAM_PENDING_ACTION \| VMCPU_FF_CSAM_SCAN_PAGE \| VMCPU_FF_INHIBIT_INTERRUPTS
98	\| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT
99	\| VMCPU_FF_TLB_FLUSH \| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL;
100	static uint32_t g_fIncomingFFs;
101	static CPUMCTX g_IncomingCtx;
102	static bool g_fIgnoreRaxRdx = false;
103
104	static uint32_t g_fEmFFs;
105	static CPUMCTX g_EmCtx;
106	static uint8_t g_abEmWrote[256];
107	static size_t g_cbEmWrote;
108
109	static uint32_t g_fIemFFs;
110	static CPUMCTX g_IemCtx;
111	extern uint8_t g_abIemWrote[256];
112	#if defined(VBOX_COMPARE_IEM_FIRST) \|\| defined(VBOX_COMPARE_IEM_LAST)
113	extern size_t g_cbIemWrote;
114	#else
115	static size_t g_cbIemWrote;
116	#endif
117	#endif
118
119
120	/**
121	* Get the current execution manager status.
122	*
123	* @returns Current status.
124	* @param pVCpu Pointer to the VMCPU.
125	*/
126	VMM_INT_DECL(EMSTATE) EMGetState(PVMCPU pVCpu)
127	{
128	return pVCpu->em.s.enmState;
129	}
130
131	/**
132	* Sets the current execution manager status. (use only when you know what you're doing!)
133	*
134	* @param pVCpu Pointer to the VMCPU.
135	*/
136	VMM_INT_DECL(void) EMSetState(PVMCPU pVCpu, EMSTATE enmNewState)
137	{
138	/* Only allowed combination: */
139	Assert(pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI && enmNewState == EMSTATE_HALTED);
140	pVCpu->em.s.enmState = enmNewState;
141	}
142
143
144	/**
145	* Sets the PC for which interrupts should be inhibited.
146	*
147	* @param pVCpu Pointer to the VMCPU.
148	* @param PC The PC.
149	*/
150	VMMDECL(void) EMSetInhibitInterruptsPC(PVMCPU pVCpu, RTGCUINTPTR PC)
151	{
152	pVCpu->em.s.GCPtrInhibitInterrupts = PC;
153	VMCPU_FF_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
154	}
155
156
157	/**
158	* Gets the PC for which interrupts should be inhibited.
159	*
160	* There are a few instructions which inhibits or delays interrupts
161	* for the instruction following them. These instructions are:
162	* - STI
163	* - MOV SS, r/m16
164	* - POP SS
165	*
166	* @returns The PC for which interrupts should be inhibited.
167	* @param pVCpu Pointer to the VMCPU.
168	*
169	*/
170	VMMDECL(RTGCUINTPTR) EMGetInhibitInterruptsPC(PVMCPU pVCpu)
171	{
172	return pVCpu->em.s.GCPtrInhibitInterrupts;
173	}
174
175
176	/**
177	* Prepare an MWAIT - essentials of the MONITOR instruction.
178	*
179	* @returns VINF_SUCCESS
180	* @param pVCpu The current CPU.
181	* @param rax The content of RAX.
182	* @param rcx The content of RCX.
183	* @param rdx The content of RDX.
184	* @param GCPhys The physical address corresponding to rax.
185	*/
186	VMM_INT_DECL(int) EMMonitorWaitPrepare(PVMCPU pVCpu, uint64_t rax, uint64_t rcx, uint64_t rdx, RTGCPHYS GCPhys)
187	{
188	pVCpu->em.s.MWait.uMonitorRAX = rax;
189	pVCpu->em.s.MWait.uMonitorRCX = rcx;
190	pVCpu->em.s.MWait.uMonitorRDX = rdx;
191	pVCpu->em.s.MWait.fWait \|= EMMWAIT_FLAG_MONITOR_ACTIVE;
192	/** @todo Make use of GCPhys. */
193	NOREF(GCPhys);
194	/** @todo Complete MONITOR implementation. */
195	return VINF_SUCCESS;
196	}
197
198
199	/**
200	* Performs an MWAIT.
201	*
202	* @returns VINF_SUCCESS
203	* @param pVCpu The current CPU.
204	* @param rax The content of RAX.
205	* @param rcx The content of RCX.
206	*/
207	VMM_INT_DECL(int) EMMonitorWaitPerform(PVMCPU pVCpu, uint64_t rax, uint64_t rcx)
208	{
209	pVCpu->em.s.MWait.uMWaitRAX = rax;
210	pVCpu->em.s.MWait.uMWaitRCX = rcx;
211	pVCpu->em.s.MWait.fWait \|= EMMWAIT_FLAG_ACTIVE;
212	if (rcx)
213	pVCpu->em.s.MWait.fWait \|= EMMWAIT_FLAG_BREAKIRQIF0;
214	else
215	pVCpu->em.s.MWait.fWait &= ~EMMWAIT_FLAG_BREAKIRQIF0;
216	/** @todo not completely correct?? */
217	return VINF_EM_HALT;
218	}
219
220
221
222	/**
223	* Determine if we should continue after encountering a mwait instruction.
224	*
225	* Clears MWAIT flags if returning @c true.
226	*
227	* @returns true if we should continue, false if we should halt.
228	* @param pVCpu Pointer to the VMCPU.
229	* @param pCtx Current CPU context.
230	*/
231	VMM_INT_DECL(bool) EMMonitorWaitShouldContinue(PVMCPU pVCpu, PCPUMCTX pCtx)
232	{
233	if ( pCtx->eflags.Bits.u1IF
234	\|\| ( (pVCpu->em.s.MWait.fWait & (EMMWAIT_FLAG_ACTIVE \| EMMWAIT_FLAG_BREAKIRQIF0))
235	== (EMMWAIT_FLAG_ACTIVE \| EMMWAIT_FLAG_BREAKIRQIF0)) )
236	{
237	if (VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)))
238	{
239	pVCpu->em.s.MWait.fWait &= ~(EMMWAIT_FLAG_ACTIVE \| EMMWAIT_FLAG_BREAKIRQIF0);
240	return true;
241	}
242	}
243
244	return false;
245	}
246
247
248	/**
249	* Determine if we should continue after encountering a hlt instruction.
250	*
251	* @returns true if we should continue, false if we should halt.
252	* @param pVCpu Pointer to the VMCPU.
253	* @param pCtx Current CPU context.
254	*/
255	VMM_INT_DECL(bool) EMShouldContinueAfterHalt(PVMCPU pVCpu, PCPUMCTX pCtx)
256	{
257	if (pCtx->eflags.Bits.u1IF)
258	return !!VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC));
259	return false;
260	}
261
262
263	/**
264	* Locks REM execution to a single VCPU.
265	*
266	* @param pVM Pointer to the VM.
267	*/
268	VMMDECL(void) EMRemLock(PVM pVM)
269	{
270	#ifdef VBOX_WITH_REM
271	if (!PDMCritSectIsInitialized(&pVM->em.s.CritSectREM))
272	return; /* early init */
273
274	Assert(!PGMIsLockOwner(pVM));
275	Assert(!IOMIsLockWriteOwner(pVM));
276	int rc = PDMCritSectEnter(&pVM->em.s.CritSectREM, VERR_SEM_BUSY);
277	AssertRCSuccess(rc);
278	#endif
279	}
280
281
282	/**
283	* Unlocks REM execution
284	*
285	* @param pVM Pointer to the VM.
286	*/
287	VMMDECL(void) EMRemUnlock(PVM pVM)
288	{
289	#ifdef VBOX_WITH_REM
290	if (!PDMCritSectIsInitialized(&pVM->em.s.CritSectREM))
291	return; /* early init */
292
293	PDMCritSectLeave(&pVM->em.s.CritSectREM);
294	#endif
295	}
296
297
298	/**
299	* Check if this VCPU currently owns the REM lock.
300	*
301	* @returns bool owner/not owner
302	* @param pVM Pointer to the VM.
303	*/
304	VMMDECL(bool) EMRemIsLockOwner(PVM pVM)
305	{
306	#ifdef VBOX_WITH_REM
307	if (!PDMCritSectIsInitialized(&pVM->em.s.CritSectREM))
308	return true; /* early init */
309
310	return PDMCritSectIsOwner(&pVM->em.s.CritSectREM);
311	#else
312	return true;
313	#endif
314	}
315
316
317	/**
318	* Try to acquire the REM lock.
319	*
320	* @returns VBox status code
321	* @param pVM Pointer to the VM.
322	*/
323	VMM_INT_DECL(int) EMRemTryLock(PVM pVM)
324	{
325	#ifdef VBOX_WITH_REM
326	if (!PDMCritSectIsInitialized(&pVM->em.s.CritSectREM))
327	return VINF_SUCCESS; /* early init */
328
329	return PDMCritSectTryEnter(&pVM->em.s.CritSectREM);
330	#else
331	return VINF_SUCCESS;
332	#endif
333	}
334
335
336	/**
337	* @callback_method_impl{FNDISREADBYTES}
338	*/
339	static DECLCALLBACK(int) emReadBytes(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
340	{
341	PVMCPU pVCpu = (PVMCPU)pDis->pvUser;
342	#if defined(IN_RC) \|\| defined(IN_RING3)
343	PVM pVM = pVCpu->CTX_SUFF(pVM);
344	#endif
345	RTUINTPTR uSrcAddr = pDis->uInstrAddr + offInstr;
346	int rc;
347
348	/*
349	* Figure how much we can or must read.
350	*/
351	size_t cbToRead = PAGE_SIZE - (uSrcAddr & PAGE_OFFSET_MASK);
352	if (cbToRead > cbMaxRead)
353	cbToRead = cbMaxRead;
354	else if (cbToRead < cbMinRead)
355	cbToRead = cbMinRead;
356
357	#if defined(VBOX_WITH_RAW_MODE) && (defined(IN_RC) \|\| defined(IN_RING3))
358	/*
359	* We might be called upon to interpret an instruction in a patch.
360	*/
361	if (PATMIsPatchGCAddr(pVCpu->CTX_SUFF(pVM), uSrcAddr))
362	{
363	# ifdef IN_RC
364	memcpy(&pDis->abInstr[offInstr], (void *)(uintptr_t)uSrcAddr, cbToRead);
365	# else
366	memcpy(&pDis->abInstr[offInstr], PATMR3GCPtrToHCPtr(pVCpu->CTX_SUFF(pVM), uSrcAddr), cbToRead);
367	# endif
368	rc = VINF_SUCCESS;
369	}
370	else
371	#endif
372	{
373	# ifdef IN_RC
374	/*
375	* Try access it thru the shadow page tables first. Fall back on the
376	* slower PGM method if it fails because the TLB or page table was
377	* modified recently.
378	*/
379	rc = MMGCRamRead(pVCpu->pVMRC, &pDis->abInstr[offInstr], (void *)(uintptr_t)uSrcAddr, cbToRead);
380	if (rc == VERR_ACCESS_DENIED && cbToRead > cbMinRead)
381	{
382	cbToRead = cbMinRead;
383	rc = MMGCRamRead(pVCpu->pVMRC, &pDis->abInstr[offInstr], (void *)(uintptr_t)uSrcAddr, cbToRead);
384	}
385	if (rc == VERR_ACCESS_DENIED)
386	#endif
387	{
388	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pDis->abInstr[offInstr], uSrcAddr, cbToRead);
389	if (RT_FAILURE(rc))
390	{
391	if (cbToRead > cbMinRead)
392	{
393	cbToRead = cbMinRead;
394	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pDis->abInstr[offInstr], uSrcAddr, cbToRead);
395	}
396	if (RT_FAILURE(rc))
397	{
398	#ifndef IN_RC
399	/*
400	* If we fail to find the page via the guest's page tables
401	* we invalidate the page in the host TLB (pertaining to
402	* the guest in the NestedPaging case). See @bugref{6043}.
403	*/
404	if (rc == VERR_PAGE_TABLE_NOT_PRESENT \|\| rc == VERR_PAGE_NOT_PRESENT)
405	{
406	HMInvalidatePage(pVCpu, uSrcAddr);
407	if (((uSrcAddr + cbToRead - 1) >> PAGE_SHIFT) != (uSrcAddr >> PAGE_SHIFT))
408	HMInvalidatePage(pVCpu, uSrcAddr + cbToRead - 1);
409	}
410	#endif
411	}
412	}
413	}
414	}
415
416	pDis->cbCachedInstr = offInstr + (uint8_t)cbToRead;
417	return rc;
418	}
419
420
421	DECLINLINE(int) emDisCoreOne(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, RTGCUINTPTR InstrGC, uint32_t *pOpsize)
422	{
423	NOREF(pVM);
424	return DISInstrWithReader(InstrGC, (DISCPUMODE)pDis->uCpuMode, emReadBytes, pVCpu, pDis, pOpsize);
425	}
426
427
428	/**
429	* Disassembles the current instruction.
430	*
431	* @returns VBox status code, see SELMToFlatEx and EMInterpretDisasOneEx for
432	* details.
433	*
434	* @param pVM Pointer to the VM.
435	* @param pVCpu Pointer to the VMCPU.
436	* @param pDis Where to return the parsed instruction info.
437	* @param pcbInstr Where to return the instruction size. (optional)
438	*/
439	VMM_INT_DECL(int) EMInterpretDisasCurrent(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, unsigned *pcbInstr)
440	{
441	PCPUMCTXCORE pCtxCore = CPUMCTX2CORE(CPUMQueryGuestCtxPtr(pVCpu));
442	RTGCPTR GCPtrInstr;
443	#if 0
444	int rc = SELMToFlatEx(pVCpu, DISSELREG_CS, pCtxCore, pCtxCore->rip, 0, &GCPtrInstr);
445	#else
446	/** @todo Get the CPU mode as well while we're at it! */
447	int rc = SELMValidateAndConvertCSAddr(pVCpu, pCtxCore->eflags, pCtxCore->ss.Sel, pCtxCore->cs.Sel, &pCtxCore->cs,
448	pCtxCore->rip, &GCPtrInstr);
449	#endif
450	if (RT_FAILURE(rc))
451	{
452	Log(("EMInterpretDisasOne: Failed to convert %RTsel:%RGv (cpl=%d) - rc=%Rrc !!\n",
453	pCtxCore->cs.Sel, (RTGCPTR)pCtxCore->rip, pCtxCore->ss.Sel & X86_SEL_RPL, rc));
454	return rc;
455	}
456	return EMInterpretDisasOneEx(pVM, pVCpu, (RTGCUINTPTR)GCPtrInstr, pCtxCore, pDis, pcbInstr);
457	}
458
459
460	/**
461	* Disassembles one instruction.
462	*
463	* This is used by internally by the interpreter and by trap/access handlers.
464	*
465	* @returns VBox status code.
466	*
467	* @param pVM Pointer to the VM.
468	* @param pVCpu Pointer to the VMCPU.
469	* @param GCPtrInstr The flat address of the instruction.
470	* @param pCtxCore The context core (used to determine the cpu mode).
471	* @param pDis Where to return the parsed instruction info.
472	* @param pcbInstr Where to return the instruction size. (optional)
473	*/
474	VMM_INT_DECL(int) EMInterpretDisasOneEx(PVM pVM, PVMCPU pVCpu, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore,
475	PDISCPUSTATE pDis, unsigned *pcbInstr)
476	{
477	NOREF(pVM);
478	Assert(pCtxCore == CPUMGetGuestCtxCore(pVCpu)); NOREF(pCtxCore);
479	DISCPUMODE enmCpuMode = CPUMGetGuestDisMode(pVCpu);
480	/** @todo Deal with too long instruction (=> \#GP), opcode read errors (=>
481	* \#PF, \#GP, \#??), undefined opcodes (=> \#UD), and such. */
482	int rc = DISInstrWithReader(GCPtrInstr, enmCpuMode, emReadBytes, pVCpu, pDis, pcbInstr);
483	if (RT_SUCCESS(rc))
484	return VINF_SUCCESS;
485	AssertMsg(rc == VERR_PAGE_NOT_PRESENT \|\| rc == VERR_PAGE_TABLE_NOT_PRESENT, ("DISCoreOne failed to GCPtrInstr=%RGv rc=%Rrc\n", GCPtrInstr, rc));
486	return rc;
487	}
488
489
490	#if defined(VBOX_COMPARE_IEM_FIRST) \|\| defined(VBOX_COMPARE_IEM_LAST)
491	static void emCompareWithIem(PVMCPU pVCpu, PCCPUMCTX pEmCtx, PCCPUMCTX pIemCtx,
492	VBOXSTRICTRC rcEm, VBOXSTRICTRC rcIem,
493	uint32_t cbEm, uint32_t cbIem)
494	{
495	/* Quick compare. */
496	if ( rcEm == rcIem
497	&& cbEm == cbIem
498	&& g_cbEmWrote == g_cbIemWrote
499	&& memcmp(g_abIemWrote, g_abEmWrote, g_cbIemWrote) == 0
500	&& memcmp(pIemCtx, pEmCtx, sizeof(*pIemCtx)) == 0
501	&& (g_fEmFFs & g_fInterestingFFs) == (g_fIemFFs & g_fInterestingFFs)
502	)
503	return;
504
505	/* Report exact differences. */
506	RTLogPrintf("! EM and IEM differs at %04x:%08RGv !\n", g_IncomingCtx.cs.Sel, g_IncomingCtx.rip);
507	if (rcEm != rcIem)
508	RTLogPrintf(" * rcIem=%Rrc rcEm=%Rrc\n", VBOXSTRICTRC_VAL(rcIem), VBOXSTRICTRC_VAL(rcEm));
509	else if (cbEm != cbIem)
510	RTLogPrintf(" * cbIem=%#x cbEm=%#x\n", cbIem, cbEm);
511
512	if (RT_SUCCESS(rcEm) && RT_SUCCESS(rcIem))
513	{
514	if (g_cbIemWrote != g_cbEmWrote)
515	RTLogPrintf("!! g_cbIemWrote=%#x g_cbEmWrote=%#x\n", g_cbIemWrote, g_cbEmWrote);
516	else if (memcmp(g_abIemWrote, g_abEmWrote, g_cbIemWrote))
517	{
518	RTLogPrintf("!! IemWrote %.*Rhxs\n", RT_MIN(RT_MAX(1, g_cbIemWrote), 64), g_abIemWrote);
519	RTLogPrintf("!! EemWrote %.*Rhxs\n", RT_MIN(RT_MAX(1, g_cbIemWrote), 64), g_abIemWrote);
520	}
521
522	if ((g_fEmFFs & g_fInterestingFFs) != (g_fIemFFs & g_fInterestingFFs))
523	RTLogPrintf("!! g_fIemFFs=%#x g_fEmFFs=%#x (diff=%#x)\n", g_fIemFFs & g_fInterestingFFs,
524	g_fEmFFs & g_fInterestingFFs, (g_fIemFFs ^ g_fEmFFs) & g_fInterestingFFs);
525
526	# define CHECK_FIELD(a_Field) \
527	do \
528	{ \
529	if (pEmCtx->a_Field != pIemCtx->a_Field) \
530	{ \
531	switch (sizeof(pEmCtx->a_Field)) \
532	{ \
533	case 1: RTLogPrintf("!! %8s differs - iem=%02x - em=%02x\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); break; \
534	case 2: RTLogPrintf("!! %8s differs - iem=%04x - em=%04x\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); break; \
535	case 4: RTLogPrintf("!! %8s differs - iem=%08x - em=%08x\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); break; \
536	case 8: RTLogPrintf("!! %8s differs - iem=%016llx - em=%016llx\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); break; \
537	default: RTLogPrintf("!! %8s differs\n", #a_Field); break; \
538	} \
539	cDiffs++; \
540	} \
541	} while (0)
542
543	# define CHECK_BIT_FIELD(a_Field) \
544	do \
545	{ \
546	if (pEmCtx->a_Field != pIemCtx->a_Field) \
547	{ \
548	RTLogPrintf("!! %8s differs - iem=%02x - em=%02x\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); \
549	cDiffs++; \
550	} \
551	} while (0)
552
553	# define CHECK_SEL(a_Sel) \
554	do \
555	{ \
556	CHECK_FIELD(a_Sel.Sel); \
557	CHECK_FIELD(a_Sel.Attr.u); \
558	CHECK_FIELD(a_Sel.u64Base); \
559	CHECK_FIELD(a_Sel.u32Limit); \
560	CHECK_FIELD(a_Sel.fFlags); \
561	} while (0)
562
563	unsigned cDiffs = 0;
564	if (memcmp(&pEmCtx->fpu, &pIemCtx->fpu, sizeof(pIemCtx->fpu)))
565	{
566	RTLogPrintf(" the FPU state differs\n");
567	cDiffs++;
568	CHECK_FIELD(fpu.FCW);
569	CHECK_FIELD(fpu.FSW);
570	CHECK_FIELD(fpu.FTW);
571	CHECK_FIELD(fpu.FOP);
572	CHECK_FIELD(fpu.FPUIP);
573	CHECK_FIELD(fpu.CS);
574	CHECK_FIELD(fpu.Rsrvd1);
575	CHECK_FIELD(fpu.FPUDP);
576	CHECK_FIELD(fpu.DS);
577	CHECK_FIELD(fpu.Rsrvd2);
578	CHECK_FIELD(fpu.MXCSR);
579	CHECK_FIELD(fpu.MXCSR_MASK);
580	CHECK_FIELD(fpu.aRegs[0].au64[0]); CHECK_FIELD(fpu.aRegs[0].au64[1]);
581	CHECK_FIELD(fpu.aRegs[1].au64[0]); CHECK_FIELD(fpu.aRegs[1].au64[1]);
582	CHECK_FIELD(fpu.aRegs[2].au64[0]); CHECK_FIELD(fpu.aRegs[2].au64[1]);
583	CHECK_FIELD(fpu.aRegs[3].au64[0]); CHECK_FIELD(fpu.aRegs[3].au64[1]);
584	CHECK_FIELD(fpu.aRegs[4].au64[0]); CHECK_FIELD(fpu.aRegs[4].au64[1]);
585	CHECK_FIELD(fpu.aRegs[5].au64[0]); CHECK_FIELD(fpu.aRegs[5].au64[1]);
586	CHECK_FIELD(fpu.aRegs[6].au64[0]); CHECK_FIELD(fpu.aRegs[6].au64[1]);
587	CHECK_FIELD(fpu.aRegs[7].au64[0]); CHECK_FIELD(fpu.aRegs[7].au64[1]);
588	CHECK_FIELD(fpu.aXMM[ 0].au64[0]); CHECK_FIELD(fpu.aXMM[ 0].au64[1]);
589	CHECK_FIELD(fpu.aXMM[ 1].au64[0]); CHECK_FIELD(fpu.aXMM[ 1].au64[1]);
590	CHECK_FIELD(fpu.aXMM[ 2].au64[0]); CHECK_FIELD(fpu.aXMM[ 2].au64[1]);
591	CHECK_FIELD(fpu.aXMM[ 3].au64[0]); CHECK_FIELD(fpu.aXMM[ 3].au64[1]);
592	CHECK_FIELD(fpu.aXMM[ 4].au64[0]); CHECK_FIELD(fpu.aXMM[ 4].au64[1]);
593	CHECK_FIELD(fpu.aXMM[ 5].au64[0]); CHECK_FIELD(fpu.aXMM[ 5].au64[1]);
594	CHECK_FIELD(fpu.aXMM[ 6].au64[0]); CHECK_FIELD(fpu.aXMM[ 6].au64[1]);
595	CHECK_FIELD(fpu.aXMM[ 7].au64[0]); CHECK_FIELD(fpu.aXMM[ 7].au64[1]);
596	CHECK_FIELD(fpu.aXMM[ 8].au64[0]); CHECK_FIELD(fpu.aXMM[ 8].au64[1]);
597	CHECK_FIELD(fpu.aXMM[ 9].au64[0]); CHECK_FIELD(fpu.aXMM[ 9].au64[1]);
598	CHECK_FIELD(fpu.aXMM[10].au64[0]); CHECK_FIELD(fpu.aXMM[10].au64[1]);
599	CHECK_FIELD(fpu.aXMM[11].au64[0]); CHECK_FIELD(fpu.aXMM[11].au64[1]);
600	CHECK_FIELD(fpu.aXMM[12].au64[0]); CHECK_FIELD(fpu.aXMM[12].au64[1]);
601	CHECK_FIELD(fpu.aXMM[13].au64[0]); CHECK_FIELD(fpu.aXMM[13].au64[1]);
602	CHECK_FIELD(fpu.aXMM[14].au64[0]); CHECK_FIELD(fpu.aXMM[14].au64[1]);
603	CHECK_FIELD(fpu.aXMM[15].au64[0]); CHECK_FIELD(fpu.aXMM[15].au64[1]);
604	for (unsigned i = 0; i < RT_ELEMENTS(pEmCtx->fpu.au32RsrvdRest); i++)
605	CHECK_FIELD(fpu.au32RsrvdRest[i]);
606	}
607	CHECK_FIELD(rip);
608	if (pEmCtx->rflags.u != pIemCtx->rflags.u)
609	{
610	RTLogPrintf("!! rflags differs - iem=%08llx em=%08llx\n", pIemCtx->rflags.u, pEmCtx->rflags.u);
611	CHECK_BIT_FIELD(rflags.Bits.u1CF);
612	CHECK_BIT_FIELD(rflags.Bits.u1Reserved0);
613	CHECK_BIT_FIELD(rflags.Bits.u1PF);
614	CHECK_BIT_FIELD(rflags.Bits.u1Reserved1);
615	CHECK_BIT_FIELD(rflags.Bits.u1AF);
616	CHECK_BIT_FIELD(rflags.Bits.u1Reserved2);
617	CHECK_BIT_FIELD(rflags.Bits.u1ZF);
618	CHECK_BIT_FIELD(rflags.Bits.u1SF);
619	CHECK_BIT_FIELD(rflags.Bits.u1TF);
620	CHECK_BIT_FIELD(rflags.Bits.u1IF);
621	CHECK_BIT_FIELD(rflags.Bits.u1DF);
622	CHECK_BIT_FIELD(rflags.Bits.u1OF);
623	CHECK_BIT_FIELD(rflags.Bits.u2IOPL);
624	CHECK_BIT_FIELD(rflags.Bits.u1NT);
625	CHECK_BIT_FIELD(rflags.Bits.u1Reserved3);
626	CHECK_BIT_FIELD(rflags.Bits.u1RF);
627	CHECK_BIT_FIELD(rflags.Bits.u1VM);
628	CHECK_BIT_FIELD(rflags.Bits.u1AC);
629	CHECK_BIT_FIELD(rflags.Bits.u1VIF);
630	CHECK_BIT_FIELD(rflags.Bits.u1VIP);
631	CHECK_BIT_FIELD(rflags.Bits.u1ID);
632	}
633
634	if (!g_fIgnoreRaxRdx)
635	CHECK_FIELD(rax);
636	CHECK_FIELD(rcx);
637	if (!g_fIgnoreRaxRdx)
638	CHECK_FIELD(rdx);
639	CHECK_FIELD(rbx);
640	CHECK_FIELD(rsp);
641	CHECK_FIELD(rbp);
642	CHECK_FIELD(rsi);
643	CHECK_FIELD(rdi);
644	CHECK_FIELD(r8);
645	CHECK_FIELD(r9);
646	CHECK_FIELD(r10);
647	CHECK_FIELD(r11);
648	CHECK_FIELD(r12);
649	CHECK_FIELD(r13);
650	CHECK_SEL(cs);
651	CHECK_SEL(ss);
652	CHECK_SEL(ds);
653	CHECK_SEL(es);
654	CHECK_SEL(fs);
655	CHECK_SEL(gs);
656	CHECK_FIELD(cr0);
657	CHECK_FIELD(cr2);
658	CHECK_FIELD(cr3);
659	CHECK_FIELD(cr4);
660	CHECK_FIELD(dr[0]);
661	CHECK_FIELD(dr[1]);
662	CHECK_FIELD(dr[2]);
663	CHECK_FIELD(dr[3]);
664	CHECK_FIELD(dr[6]);
665	CHECK_FIELD(dr[7]);
666	CHECK_FIELD(gdtr.cbGdt);
667	CHECK_FIELD(gdtr.pGdt);
668	CHECK_FIELD(idtr.cbIdt);
669	CHECK_FIELD(idtr.pIdt);
670	CHECK_SEL(ldtr);
671	CHECK_SEL(tr);
672	CHECK_FIELD(SysEnter.cs);
673	CHECK_FIELD(SysEnter.eip);
674	CHECK_FIELD(SysEnter.esp);
675	CHECK_FIELD(msrEFER);
676	CHECK_FIELD(msrSTAR);
677	CHECK_FIELD(msrPAT);
678	CHECK_FIELD(msrLSTAR);
679	CHECK_FIELD(msrCSTAR);
680	CHECK_FIELD(msrSFMASK);
681	CHECK_FIELD(msrKERNELGSBASE);
682
683	# undef CHECK_FIELD
684	# undef CHECK_BIT_FIELD
685	}
686	}
687	#endif /* VBOX_COMPARE_IEM_AND_EM */
688
689
690	/**
691	* Interprets the current instruction.
692	*
693	* @returns VBox status code.
694	* @retval VINF_* Scheduling instructions.
695	* @retval VERR_EM_INTERPRETER Something we can't cope with.
696	* @retval VERR_* Fatal errors.
697	*
698	* @param pVCpu Pointer to the VMCPU.
699	* @param pRegFrame The register frame.
700	* Updates the EIP if an instruction was executed successfully.
701	* @param pvFault The fault address (CR2).
702	* @param pcbSize Size of the write (if applicable).
703	*
704	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
705	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
706	* to worry about e.g. invalid modrm combinations (!)
707	*/
708	VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstruction(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
709	{
710	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
711	LogFlow(("EMInterpretInstruction %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
712	#ifdef VBOX_WITH_IEM
713	NOREF(pvFault);
714
715	# ifdef VBOX_COMPARE_IEM_AND_EM
716	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
717	g_IncomingCtx = *pCtx;
718	g_fIncomingFFs = pVCpu->fLocalForcedActions;
719	g_cbEmWrote = g_cbIemWrote = 0;
720
721	# ifdef VBOX_COMPARE_IEM_FIRST
722	/* IEM */
723	VBOXSTRICTRC rcIem = IEMExecOneBypassEx(pVCpu, pRegFrame, NULL);
724	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
725	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
726	rcIem = VERR_EM_INTERPRETER;
727	g_IemCtx = *pCtx;
728	g_fIemFFs = pVCpu->fLocalForcedActions;
729	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
730	*pCtx = g_IncomingCtx;
731	# endif
732
733	/* EM */
734	RTGCPTR pbCode;
735	VBOXSTRICTRC rcEm = SELMToFlatEx(pVCpu, DISSELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
736	if (RT_SUCCESS(rcEm))
737	{
738	uint32_t cbOp;
739	PDISCPUSTATE pDis = &pVCpu->em.s.DisState;
740	pDis->uCpuMode = CPUMGetGuestDisMode(pVCpu);
741	rcEm = emDisCoreOne(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, (RTGCUINTPTR)pbCode, &cbOp);
742	if (RT_SUCCESS(rcEm))
743	{
744	Assert(cbOp == pDis->cbInstr);
745	uint32_t cbIgnored;
746	rcEm = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, &cbIgnored);
747	if (RT_SUCCESS(rcEm))
748	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
749
750	}
751	rcEm = VERR_EM_INTERPRETER;
752	}
753	else
754	rcEm = VERR_EM_INTERPRETER;
755	# ifdef VBOX_SAME_AS_EM
756	if (rcEm == VERR_EM_INTERPRETER)
757	{
758	Log(("EMInterpretInstruction: returns %Rrc\n", VBOXSTRICTRC_VAL(rcEm)));
759	return rcEm;
760	}
761	# endif
762	g_EmCtx = *pCtx;
763	g_fEmFFs = pVCpu->fLocalForcedActions;
764	VBOXSTRICTRC rc = rcEm;
765
766	# ifdef VBOX_COMPARE_IEM_LAST
767	/* IEM */
768	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
769	*pCtx = g_IncomingCtx;
770	VBOXSTRICTRC rcIem = IEMExecOneBypassEx(pVCpu, pRegFrame, NULL);
771	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
772	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
773	rcIem = VERR_EM_INTERPRETER;
774	g_IemCtx = *pCtx;
775	g_fIemFFs = pVCpu->fLocalForcedActions;
776	rc = rcIem;
777	# endif
778
779	# if defined(VBOX_COMPARE_IEM_LAST) \|\| defined(VBOX_COMPARE_IEM_FIRST)
780	emCompareWithIem(pVCpu, &g_EmCtx, &g_IemCtx, rcEm, rcIem, 0, 0);
781	# endif
782
783	# else
784	VBOXSTRICTRC rc = IEMExecOneBypassEx(pVCpu, pRegFrame, NULL);
785	if (RT_UNLIKELY( rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED
786	\|\| rc == VERR_IEM_INSTR_NOT_IMPLEMENTED))
787	rc = VERR_EM_INTERPRETER;
788	# endif
789	if (rc != VINF_SUCCESS)
790	Log(("EMInterpretInstruction: returns %Rrc\n", VBOXSTRICTRC_VAL(rc)));
791
792	return rc;
793	#else
794	RTGCPTR pbCode;
795	VBOXSTRICTRC rc = SELMToFlatEx(pVCpu, DISSELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
796	if (RT_SUCCESS(rc))
797	{
798	uint32_t cbOp;
799	PDISCPUSTATE pDis = &pVCpu->em.s.DisState;
800	pDis->uCpuMode = CPUMGetGuestDisMode(pVCpu);
801	rc = emDisCoreOne(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, (RTGCUINTPTR)pbCode, &cbOp);
802	if (RT_SUCCESS(rc))
803	{
804	Assert(cbOp == pDis->cbInstr);
805	uint32_t cbIgnored;
806	rc = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, &cbIgnored);
807	if (RT_SUCCESS(rc))
808	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
809
810	return rc;
811	}
812	}
813	return VERR_EM_INTERPRETER;
814	#endif
815	}
816
817
818	/**
819	* Interprets the current instruction.
820	*
821	* @returns VBox status code.
822	* @retval VINF_* Scheduling instructions.
823	* @retval VERR_EM_INTERPRETER Something we can't cope with.
824	* @retval VERR_* Fatal errors.
825	*
826	* @param pVM Pointer to the VM.
827	* @param pVCpu Pointer to the VMCPU.
828	* @param pRegFrame The register frame.
829	* Updates the EIP if an instruction was executed successfully.
830	* @param pvFault The fault address (CR2).
831	* @param pcbWritten Size of the write (if applicable).
832	*
833	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
834	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
835	* to worry about e.g. invalid modrm combinations (!)
836	*/
837	VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstructionEx(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbWritten)
838	{
839	LogFlow(("EMInterpretInstructionEx %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
840	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
841	#ifdef VBOX_WITH_IEM
842	NOREF(pvFault);
843
844	# ifdef VBOX_COMPARE_IEM_AND_EM
845	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
846	g_IncomingCtx = *pCtx;
847	g_fIncomingFFs = pVCpu->fLocalForcedActions;
848	g_cbEmWrote = g_cbIemWrote = 0;
849
850	# ifdef VBOX_COMPARE_IEM_FIRST
851	/* IEM */
852	uint32_t cbIemWritten = 0;
853	VBOXSTRICTRC rcIem = IEMExecOneBypassEx(pVCpu, pRegFrame, &cbIemWritten);
854	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
855	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
856	rcIem = VERR_EM_INTERPRETER;
857	g_IemCtx = *pCtx;
858	g_fIemFFs = pVCpu->fLocalForcedActions;
859	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
860	*pCtx = g_IncomingCtx;
861	# endif
862
863	/* EM */
864	uint32_t cbEmWritten = 0;
865	RTGCPTR pbCode;
866	VBOXSTRICTRC rcEm = SELMToFlatEx(pVCpu, DISSELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
867	if (RT_SUCCESS(rcEm))
868	{
869	uint32_t cbOp;
870	PDISCPUSTATE pDis = &pVCpu->em.s.DisState;
871	pDis->uCpuMode = CPUMGetGuestDisMode(pVCpu);
872	rcEm = emDisCoreOne(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, (RTGCUINTPTR)pbCode, &cbOp);
873	if (RT_SUCCESS(rcEm))
874	{
875	Assert(cbOp == pDis->cbInstr);
876	rcEm = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, &cbEmWritten);
877	if (RT_SUCCESS(rcEm))
878	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
879
880	}
881	else
882	rcEm = VERR_EM_INTERPRETER;
883	}
884	else
885	rcEm = VERR_EM_INTERPRETER;
886	# ifdef VBOX_SAME_AS_EM
887	if (rcEm == VERR_EM_INTERPRETER)
888	{
889	Log(("EMInterpretInstruction: returns %Rrc\n", VBOXSTRICTRC_VAL(rcEm)));
890	return rcEm;
891	}
892	# endif
893	g_EmCtx = *pCtx;
894	g_fEmFFs = pVCpu->fLocalForcedActions;
895	*pcbWritten = cbEmWritten;
896	VBOXSTRICTRC rc = rcEm;
897
898	# ifdef VBOX_COMPARE_IEM_LAST
899	/* IEM */
900	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
901	*pCtx = g_IncomingCtx;
902	uint32_t cbIemWritten = 0;
903	VBOXSTRICTRC rcIem = IEMExecOneBypassEx(pVCpu, pRegFrame, &cbIemWritten);
904	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
905	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
906	rcIem = VERR_EM_INTERPRETER;
907	g_IemCtx = *pCtx;
908	g_fIemFFs = pVCpu->fLocalForcedActions;
909	*pcbWritten = cbIemWritten;
910	rc = rcIem;
911	# endif
912
913	# if defined(VBOX_COMPARE_IEM_LAST) \|\| defined(VBOX_COMPARE_IEM_FIRST)
914	emCompareWithIem(pVCpu, &g_EmCtx, &g_IemCtx, rcEm, rcIem, cbEmWritten, cbIemWritten);
915	# endif
916
917	# else
918	VBOXSTRICTRC rc = IEMExecOneBypassEx(pVCpu, pRegFrame, pcbWritten);
919	if (RT_UNLIKELY( rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED
920	\|\| rc == VERR_IEM_INSTR_NOT_IMPLEMENTED))
921	rc = VERR_EM_INTERPRETER;
922	# endif
923	if (rc != VINF_SUCCESS)
924	Log(("EMInterpretInstructionEx: returns %Rrc\n", VBOXSTRICTRC_VAL(rc)));
925
926	return rc;
927	#else
928	RTGCPTR pbCode;
929	VBOXSTRICTRC rc = SELMToFlatEx(pVCpu, DISSELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
930	if (RT_SUCCESS(rc))
931	{
932	uint32_t cbOp;
933	PDISCPUSTATE pDis = &pVCpu->em.s.DisState;
934	pDis->uCpuMode = CPUMGetGuestDisMode(pVCpu);
935	rc = emDisCoreOne(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, (RTGCUINTPTR)pbCode, &cbOp);
936	if (RT_SUCCESS(rc))
937	{
938	Assert(cbOp == pDis->cbInstr);
939	rc = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, pcbWritten);
940	if (RT_SUCCESS(rc))
941	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
942
943	return rc;
944	}
945	}
946	return VERR_EM_INTERPRETER;
947	#endif
948	}
949
950
951	/**
952	* Interprets the current instruction using the supplied DISCPUSTATE structure.
953	*
954	* IP/EIP/RIP IS updated!
955	*
956	* @returns VBox strict status code.
957	* @retval VINF_* Scheduling instructions. When these are returned, it
958	* starts to get a bit tricky to know whether code was
959	* executed or not... We'll address this when it becomes a problem.
960	* @retval VERR_EM_INTERPRETER Something we can't cope with.
961	* @retval VERR_* Fatal errors.
962	*
963	* @param pVM Pointer to the VM.
964	* @param pVCpu Pointer to the VMCPU.
965	* @param pDis The disassembler cpu state for the instruction to be
966	* interpreted.
967	* @param pRegFrame The register frame. IP/EIP/RIP IS changed!
968	* @param pvFault The fault address (CR2).
969	* @param pcbSize Size of the write (if applicable).
970	* @param enmCodeType Code type (user/supervisor)
971	*
972	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
973	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
974	* to worry about e.g. invalid modrm combinations (!)
975	*
976	* @todo At this time we do NOT check if the instruction overwrites vital information.
977	* Make sure this can't happen!! (will add some assertions/checks later)
978	*/
979	VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstructionDisasState(PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
980	RTGCPTR pvFault, EMCODETYPE enmCodeType)
981	{
982	LogFlow(("EMInterpretInstructionDisasState %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
983	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
984	#ifdef VBOX_WITH_IEM
985	NOREF(pDis); NOREF(pvFault); NOREF(enmCodeType);
986
987	# ifdef VBOX_COMPARE_IEM_AND_EM
988	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
989	g_IncomingCtx = *pCtx;
990	g_fIncomingFFs = pVCpu->fLocalForcedActions;
991	g_cbEmWrote = g_cbIemWrote = 0;
992
993	# ifdef VBOX_COMPARE_IEM_FIRST
994	VBOXSTRICTRC rcIem = IEMExecOneBypassWithPrefetchedByPC(pVCpu, pRegFrame, pRegFrame->rip, pDis->abInstr, pDis->cbCachedInstr);
995	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
996	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
997	rcIem = VERR_EM_INTERPRETER;
998	g_IemCtx = *pCtx;
999	g_fIemFFs = pVCpu->fLocalForcedActions;
1000	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
1001	*pCtx = g_IncomingCtx;
1002	# endif
1003
1004	/* EM */
1005	uint32_t cbIgnored;
1006	VBOXSTRICTRC rcEm = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, enmCodeType, &cbIgnored);
1007	if (RT_SUCCESS(rcEm))
1008	pRegFrame->rip += pDis->cbInstr; /* Move on to the next instruction. */
1009	# ifdef VBOX_SAME_AS_EM
1010	if (rcEm == VERR_EM_INTERPRETER)
1011	{
1012	Log(("EMInterpretInstruction: returns %Rrc\n", VBOXSTRICTRC_VAL(rcEm)));
1013	return rcEm;
1014	}
1015	# endif
1016	g_EmCtx = *pCtx;
1017	g_fEmFFs = pVCpu->fLocalForcedActions;
1018	VBOXSTRICTRC rc = rcEm;
1019
1020	# ifdef VBOX_COMPARE_IEM_LAST
1021	/* IEM */
1022	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
1023	*pCtx = g_IncomingCtx;
1024	VBOXSTRICTRC rcIem = IEMExecOneBypassWithPrefetchedByPC(pVCpu, pRegFrame, pRegFrame->rip, pDis->abInstr, pDis->cbCachedInstr);
1025	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
1026	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
1027	rcIem = VERR_EM_INTERPRETER;
1028	g_IemCtx = *pCtx;
1029	g_fIemFFs = pVCpu->fLocalForcedActions;
1030	rc = rcIem;
1031	# endif
1032
1033	# if defined(VBOX_COMPARE_IEM_LAST) \|\| defined(VBOX_COMPARE_IEM_FIRST)
1034	emCompareWithIem(pVCpu, &g_EmCtx, &g_IemCtx, rcEm, rcIem, 0, 0);
1035	# endif
1036
1037	# else
1038	VBOXSTRICTRC rc = IEMExecOneBypassWithPrefetchedByPC(pVCpu, pRegFrame, pRegFrame->rip, pDis->abInstr, pDis->cbCachedInstr);
1039	if (RT_UNLIKELY( rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED
1040	\|\| rc == VERR_IEM_INSTR_NOT_IMPLEMENTED))
1041	rc = VERR_EM_INTERPRETER;
1042	# endif
1043
1044	if (rc != VINF_SUCCESS)
1045	Log(("EMInterpretInstructionDisasState: returns %Rrc\n", VBOXSTRICTRC_VAL(rc)));
1046
1047	return rc;
1048	#else
1049	uint32_t cbIgnored;
1050	VBOXSTRICTRC rc = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, enmCodeType, &cbIgnored);
1051	if (RT_SUCCESS(rc))
1052	pRegFrame->rip += pDis->cbInstr; /* Move on to the next instruction. */
1053	return rc;
1054	#endif
1055	}
1056
1057	#ifdef IN_RC
1058
1059	DECLINLINE(int) emRCStackRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCPTR GCPtrSrc, uint32_t cb)
1060	{
1061	int rc = MMGCRamRead(pVM, pvDst, (void *)(uintptr_t)GCPtrSrc, cb);
1062	if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
1063	return rc;
1064	return PGMPhysInterpretedReadNoHandlers(pVCpu, pCtxCore, pvDst, GCPtrSrc, cb, /fMayTrap/ false);
1065	}
1066
1067
1068	/**
1069	* Interpret IRET (currently only to V86 code) - PATM only.
1070	*
1071	* @returns VBox status code.
1072	* @param pVM Pointer to the VM.
1073	* @param pVCpu Pointer to the VMCPU.
1074	* @param pRegFrame The register frame.
1075	*
1076	*/
1077	VMM_INT_DECL(int) EMInterpretIretV86ForPatm(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1078	{
1079	RTGCUINTPTR pIretStack = (RTGCUINTPTR)pRegFrame->esp;
1080	RTGCUINTPTR eip, cs, esp, ss, eflags, ds, es, fs, gs, uMask;
1081	int rc;
1082
1083	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1084	Assert(!CPUMIsGuestIn64BitCode(pVCpu));
1085	/** @todo Rainy day: Test what happens when VERR_EM_INTERPRETER is returned by
1086	* this function. Fear that it may guru on us, thus not converted to
1087	* IEM. */
1088
1089	rc = emRCStackRead(pVM, pVCpu, pRegFrame, &eip, (RTGCPTR)pIretStack , 4);
1090	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &cs, (RTGCPTR)(pIretStack + 4), 4);
1091	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &eflags, (RTGCPTR)(pIretStack + 8), 4);
1092	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1093	AssertReturn(eflags & X86_EFL_VM, VERR_EM_INTERPRETER);
1094
1095	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &esp, (RTGCPTR)(pIretStack + 12), 4);
1096	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &ss, (RTGCPTR)(pIretStack + 16), 4);
1097	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &es, (RTGCPTR)(pIretStack + 20), 4);
1098	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &ds, (RTGCPTR)(pIretStack + 24), 4);
1099	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &fs, (RTGCPTR)(pIretStack + 28), 4);
1100	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &gs, (RTGCPTR)(pIretStack + 32), 4);
1101	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1102
1103	pRegFrame->eip = eip & 0xffff;
1104	pRegFrame->cs.Sel = cs;
1105
1106	/* Mask away all reserved bits */
1107	uMask = X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_RF \| X86_EFL_VM \| X86_EFL_AC \| X86_EFL_VIF \| X86_EFL_VIP \| X86_EFL_ID;
1108	eflags &= uMask;
1109
1110	CPUMRawSetEFlags(pVCpu, eflags);
1111	Assert((pRegFrame->eflags.u32 & (X86_EFL_IF\|X86_EFL_IOPL)) == X86_EFL_IF);
1112
1113	pRegFrame->esp = esp;
1114	pRegFrame->ss.Sel = ss;
1115	pRegFrame->ds.Sel = ds;
1116	pRegFrame->es.Sel = es;
1117	pRegFrame->fs.Sel = fs;
1118	pRegFrame->gs.Sel = gs;
1119
1120	return VINF_SUCCESS;
1121	}
1122
1123	/**
1124	* IRET Emulation.
1125	*/
1126	static int emInterpretIret(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1127	{
1128	#ifdef VBOX_WITH_RAW_RING1
1129	NOREF(pvFault); NOREF(pcbSize);
1130	if (EMIsRawRing1Enabled(pVM))
1131	{
1132	RTGCUINTPTR pIretStack = (RTGCUINTPTR)pRegFrame->esp;
1133	RTGCUINTPTR eip, cs, esp, ss, eflags, uMask;
1134	int rc;
1135	uint32_t cpl, rpl;
1136
1137	/* We only execute 32-bits protected mode code in raw mode, so no need to bother to check for 16-bits code here. */
1138	/* @todo: we don't verify all the edge cases that generate #GP faults */
1139
1140	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1141	Assert(!CPUMIsGuestIn64BitCode(pVCpu));
1142	/** @todo Rainy day: Test what happens when VERR_EM_INTERPRETER is returned by
1143	* this function. Fear that it may guru on us, thus not converted to
1144	* IEM. */
1145
1146	rc = emRCStackRead(pVM, pVCpu, pRegFrame, &eip, (RTGCPTR)pIretStack , 4);
1147	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &cs, (RTGCPTR)(pIretStack + 4), 4);
1148	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &eflags, (RTGCPTR)(pIretStack + 8), 4);
1149	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1150	AssertReturn(eflags & X86_EFL_VM, VERR_EM_INTERPRETER);
1151
1152	/* Deal with V86 above. */
1153	if (eflags & X86_EFL_VM)
1154	return EMInterpretIretV86ForPatm(pVM, pVCpu, pRegFrame);
1155
1156	cpl = CPUMRCGetGuestCPL(pVCpu, pRegFrame);
1157	rpl = cs & X86_SEL_RPL;
1158
1159	Log(("emInterpretIret: iret to CS:EIP=%04X:%08X eflags=%x\n", cs, eip, eflags));
1160	if (rpl != cpl)
1161	{
1162	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &esp, (RTGCPTR)(pIretStack + 12), 4);
1163	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &ss, (RTGCPTR)(pIretStack + 16), 4);
1164	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1165	Log(("emInterpretIret: return to different privilege level (rpl=%d cpl=%d)\n", rpl, cpl));
1166	Log(("emInterpretIret: SS:ESP=%04x:%08x\n", ss, esp));
1167	pRegFrame->ss.Sel = ss;
1168	pRegFrame->esp = esp;
1169	}
1170	pRegFrame->cs.Sel = cs;
1171	pRegFrame->eip = eip;
1172
1173	/* Adjust CS & SS as required. */
1174	CPUMRCRecheckRawState(pVCpu, pRegFrame);
1175
1176	/* Mask away all reserved bits */
1177	uMask = X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_RF \| X86_EFL_VM \| X86_EFL_AC \| X86_EFL_VIF \| X86_EFL_VIP \| X86_EFL_ID;
1178	eflags &= uMask;
1179
1180	CPUMRawSetEFlags(pVCpu, eflags);
1181	Assert((pRegFrame->eflags.u32 & (X86_EFL_IF\|X86_EFL_IOPL)) == X86_EFL_IF);
1182	return VINF_SUCCESS;
1183	}
1184	#else
1185	NOREF(pVM); NOREF(pVCpu); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
1186	#endif
1187	return VERR_EM_INTERPRETER;
1188	}
1189
1190	#endif /* IN_RC */
1191
1192
1193
1194	/*
1195	*
1196	* Old interpreter primitives used by HM, move/eliminate later.
1197	* Old interpreter primitives used by HM, move/eliminate later.
1198	* Old interpreter primitives used by HM, move/eliminate later.
1199	* Old interpreter primitives used by HM, move/eliminate later.
1200	* Old interpreter primitives used by HM, move/eliminate later.
1201	*
1202	*/
1203
1204
1205	/**
1206	* Interpret CPUID given the parameters in the CPU context.
1207	*
1208	* @returns VBox status code.
1209	* @param pVM Pointer to the VM.
1210	* @param pVCpu Pointer to the VMCPU.
1211	* @param pRegFrame The register frame.
1212	*
1213	*/
1214	VMM_INT_DECL(int) EMInterpretCpuId(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1215	{
1216	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1217	uint32_t iLeaf = pRegFrame->eax;
1218	uint32_t iSubLeaf = pRegFrame->ecx;
1219	NOREF(pVM);
1220
1221	/* cpuid clears the high dwords of the affected 64 bits registers. */
1222	pRegFrame->rax = 0;
1223	pRegFrame->rbx = 0;
1224	pRegFrame->rcx = 0;
1225	pRegFrame->rdx = 0;
1226
1227	/* Note: operates the same in 64 and non-64 bits mode. */
1228	CPUMGetGuestCpuId(pVCpu, iLeaf, iSubLeaf, &pRegFrame->eax, &pRegFrame->ebx, &pRegFrame->ecx, &pRegFrame->edx);
1229	Log(("Emulate: CPUID %x -> %08x %08x %08x %08x\n", iLeaf, pRegFrame->eax, pRegFrame->ebx, pRegFrame->ecx, pRegFrame->edx));
1230	return VINF_SUCCESS;
1231	}
1232
1233
1234	/**
1235	* Interpret RDTSC.
1236	*
1237	* @returns VBox status code.
1238	* @param pVM Pointer to the VM.
1239	* @param pVCpu Pointer to the VMCPU.
1240	* @param pRegFrame The register frame.
1241	*
1242	*/
1243	VMM_INT_DECL(int) EMInterpretRdtsc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1244	{
1245	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1246	unsigned uCR4 = CPUMGetGuestCR4(pVCpu);
1247
1248	if (uCR4 & X86_CR4_TSD)
1249	return VERR_EM_INTERPRETER; /* genuine #GP */
1250
1251	uint64_t uTicks = TMCpuTickGet(pVCpu);
1252
1253	/* Same behaviour in 32 & 64 bits mode */
1254	pRegFrame->rax = (uint32_t)uTicks;
1255	pRegFrame->rdx = (uTicks >> 32ULL);
1256	#ifdef VBOX_COMPARE_IEM_AND_EM
1257	g_fIgnoreRaxRdx = true;
1258	#endif
1259
1260	NOREF(pVM);
1261	return VINF_SUCCESS;
1262	}
1263
1264	/**
1265	* Interpret RDTSCP.
1266	*
1267	* @returns VBox status code.
1268	* @param pVM Pointer to the VM.
1269	* @param pVCpu Pointer to the VMCPU.
1270	* @param pCtx The CPU context.
1271	*
1272	*/
1273	VMM_INT_DECL(int) EMInterpretRdtscp(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1274	{
1275	Assert(pCtx == CPUMQueryGuestCtxPtr(pVCpu));
1276	uint32_t uCR4 = CPUMGetGuestCR4(pVCpu);
1277
1278	if (!CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1279	{
1280	AssertFailed();
1281	return VERR_EM_INTERPRETER; /* genuine #UD */
1282	}
1283
1284	if (uCR4 & X86_CR4_TSD)
1285	return VERR_EM_INTERPRETER; /* genuine #GP */
1286
1287	uint64_t uTicks = TMCpuTickGet(pVCpu);
1288
1289	/* Same behaviour in 32 & 64 bits mode */
1290	pCtx->rax = (uint32_t)uTicks;
1291	pCtx->rdx = (uTicks >> 32ULL);
1292	#ifdef VBOX_COMPARE_IEM_AND_EM
1293	g_fIgnoreRaxRdx = true;
1294	#endif
1295	/* Low dword of the TSC_AUX msr only. */
1296	VBOXSTRICTRC rc2 = CPUMQueryGuestMsr(pVCpu, MSR_K8_TSC_AUX, &pCtx->rcx); Assert(rc2 == VINF_SUCCESS); NOREF(rc2);
1297	pCtx->rcx &= UINT32_C(0xffffffff);
1298
1299	return VINF_SUCCESS;
1300	}
1301
1302	/**
1303	* Interpret RDPMC.
1304	*
1305	* @returns VBox status code.
1306	* @param pVM Pointer to the VM.
1307	* @param pVCpu Pointer to the VMCPU.
1308	* @param pRegFrame The register frame.
1309	*
1310	*/
1311	VMM_INT_DECL(int) EMInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1312	{
1313	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1314	uint32_t uCR4 = CPUMGetGuestCR4(pVCpu);
1315
1316	/* If X86_CR4_PCE is not set, then CPL must be zero. */
1317	if ( !(uCR4 & X86_CR4_PCE)
1318	&& CPUMGetGuestCPL(pVCpu) != 0)
1319	{
1320	Assert(CPUMGetGuestCR0(pVCpu) & X86_CR0_PE);
1321	return VERR_EM_INTERPRETER; /* genuine #GP */
1322	}
1323
1324	/* Just return zero here; rather tricky to properly emulate this, especially as the specs are a mess. */
1325	pRegFrame->rax = 0;
1326	pRegFrame->rdx = 0;
1327	/** @todo We should trigger a #GP here if the CPU doesn't support the index in ecx
1328	* but see @bugref{3472}! */
1329
1330	NOREF(pVM);
1331	return VINF_SUCCESS;
1332	}
1333
1334
1335	/**
1336	* MWAIT Emulation.
1337	*/
1338	VMM_INT_DECL(VBOXSTRICTRC) EMInterpretMWait(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1339	{
1340	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1341	uint32_t u32Dummy, u32ExtFeatures, cpl, u32MWaitFeatures;
1342	NOREF(pVM);
1343
1344	/* Get the current privilege level. */
1345	cpl = CPUMGetGuestCPL(pVCpu);
1346	if (cpl != 0)
1347	return VERR_EM_INTERPRETER; /* supervisor only */
1348
1349	CPUMGetGuestCpuId(pVCpu, 1, 0, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
1350	if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
1351	return VERR_EM_INTERPRETER; /* not supported */
1352
1353	/*
1354	* CPUID.05H.ECX[0] defines support for power management extensions (eax)
1355	* CPUID.05H.ECX[1] defines support for interrupts as break events for mwait even when IF=0
1356	*/
1357	CPUMGetGuestCpuId(pVCpu, 5, 0, &u32Dummy, &u32Dummy, &u32MWaitFeatures, &u32Dummy);
1358	if (pRegFrame->ecx > 1)
1359	{
1360	Log(("EMInterpretMWait: unexpected ecx value %x -> recompiler\n", pRegFrame->ecx));
1361	return VERR_EM_INTERPRETER; /* illegal value. */
1362	}
1363
1364	if (pRegFrame->ecx && !(u32MWaitFeatures & X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1365	{
1366	Log(("EMInterpretMWait: unsupported X86_CPUID_MWAIT_ECX_BREAKIRQIF0 -> recompiler\n"));
1367	return VERR_EM_INTERPRETER; /* illegal value. */
1368	}
1369
1370	return EMMonitorWaitPerform(pVCpu, pRegFrame->rax, pRegFrame->rcx);
1371	}
1372
1373
1374	/**
1375	* MONITOR Emulation.
1376	*/
1377	VMM_INT_DECL(int) EMInterpretMonitor(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1378	{
1379	uint32_t u32Dummy, u32ExtFeatures, cpl;
1380	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1381	NOREF(pVM);
1382
1383	if (pRegFrame->ecx != 0)
1384	{
1385	Log(("emInterpretMonitor: unexpected ecx=%x -> recompiler!!\n", pRegFrame->ecx));
1386	return VERR_EM_INTERPRETER; /* illegal value. */
1387	}
1388
1389	/* Get the current privilege level. */
1390	cpl = CPUMGetGuestCPL(pVCpu);
1391	if (cpl != 0)
1392	return VERR_EM_INTERPRETER; /* supervisor only */
1393
1394	CPUMGetGuestCpuId(pVCpu, 1, 0, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
1395	if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
1396	return VERR_EM_INTERPRETER; /* not supported */
1397
1398	EMMonitorWaitPrepare(pVCpu, pRegFrame->rax, pRegFrame->rcx, pRegFrame->rdx, NIL_RTGCPHYS);
1399	return VINF_SUCCESS;
1400	}
1401
1402
1403	/* VT-x only: */
1404
1405	/**
1406	* Interpret INVLPG.
1407	*
1408	* @returns VBox status code.
1409	* @param pVM Pointer to the VM.
1410	* @param pVCpu Pointer to the VMCPU.
1411	* @param pRegFrame The register frame.
1412	* @param pAddrGC Operand address.
1413	*
1414	*/
1415	VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC)
1416	{
1417	/** @todo is addr always a flat linear address or ds based
1418	* (in absence of segment override prefixes)????
1419	*/
1420	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1421	NOREF(pVM); NOREF(pRegFrame);
1422	#ifdef IN_RC
1423	LogFlow(("RC: EMULATE: invlpg %RGv\n", pAddrGC));
1424	#endif
1425	VBOXSTRICTRC rc = PGMInvalidatePage(pVCpu, pAddrGC);
1426	if ( rc == VINF_SUCCESS
1427	\|\| rc == VINF_PGM_SYNC_CR3 /* we can rely on the FF */)
1428	return VINF_SUCCESS;
1429	AssertMsgReturn(rc == VINF_EM_RAW_EMULATE_INSTR,
1430	("%Rrc addr=%RGv\n", VBOXSTRICTRC_VAL(rc), pAddrGC),
1431	VERR_EM_INTERPRETER);
1432	return rc;
1433	}
1434
1435
1436	/**
1437	* Update CRx.
1438	*
1439	* @returns VBox status code.
1440	* @param pVM Pointer to the VM.
1441	* @param pVCpu Pointer to the VMCPU.
1442	* @param pRegFrame The register frame.
1443	* @param DestRegCRx CRx register index (DISUSE_REG_CR*)
1444	* @param val New CRx value
1445	*
1446	*/
1447	static int emUpdateCRx(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint64_t val)
1448	{
1449	uint64_t oldval;
1450	uint64_t msrEFER;
1451	uint32_t fValid;
1452	int rc, rc2;
1453	NOREF(pVM);
1454
1455	/** @todo Clean up this mess. */
1456	LogFlow(("emInterpretCRxWrite at %RGv CR%d <- %RX64\n", (RTGCPTR)pRegFrame->rip, DestRegCrx, val));
1457	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1458	switch (DestRegCrx)
1459	{
1460	case DISCREG_CR0:
1461	oldval = CPUMGetGuestCR0(pVCpu);
1462	#ifdef IN_RC
1463	/* CR0.WP and CR0.AM changes require a reschedule run in ring 3. */
1464	if ( (val & (X86_CR0_WP \| X86_CR0_AM))
1465	!= (oldval & (X86_CR0_WP \| X86_CR0_AM)))
1466	return VERR_EM_INTERPRETER;
1467	#endif
1468	rc = VINF_SUCCESS;
1469	#if !defined(VBOX_COMPARE_IEM_AND_EM) \|\| !defined(VBOX_COMPARE_IEM_LAST)
1470	CPUMSetGuestCR0(pVCpu, val);
1471	#else
1472	CPUMQueryGuestCtxPtr(pVCpu)->cr0 = val \| X86_CR0_ET;
1473	#endif
1474	val = CPUMGetGuestCR0(pVCpu);
1475	if ( (oldval & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE))
1476	!= (val & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE)))
1477	{
1478	/* global flush */
1479	rc = PGMFlushTLB(pVCpu, CPUMGetGuestCR3(pVCpu), true /* global */);
1480	AssertRCReturn(rc, rc);
1481	}
1482
1483	/* Deal with long mode enabling/disabling. */
1484	msrEFER = CPUMGetGuestEFER(pVCpu);
1485	if (msrEFER & MSR_K6_EFER_LME)
1486	{
1487	if ( !(oldval & X86_CR0_PG)
1488	&& (val & X86_CR0_PG))
1489	{
1490	/* Illegal to have an active 64 bits CS selector (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1491	if (pRegFrame->cs.Attr.n.u1Long)
1492	{
1493	AssertMsgFailed(("Illegal enabling of paging with CS.u1Long = 1!!\n"));
1494	return VERR_EM_INTERPRETER; /** @todo generate #GP(0) */
1495	}
1496
1497	/* Illegal to switch to long mode before activating PAE first (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1498	if (!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PAE))
1499	{
1500	AssertMsgFailed(("Illegal enabling of paging with PAE disabled!!\n"));
1501	return VERR_EM_INTERPRETER; /** @todo generate #GP(0) */
1502	}
1503	msrEFER \|= MSR_K6_EFER_LMA;
1504	}
1505	else
1506	if ( (oldval & X86_CR0_PG)
1507	&& !(val & X86_CR0_PG))
1508	{
1509	msrEFER &= ~MSR_K6_EFER_LMA;
1510	/** @todo Do we need to cut off rip here? High dword of rip is undefined, so it shouldn't really matter. */
1511	}
1512	CPUMSetGuestEFER(pVCpu, msrEFER);
1513	}
1514	rc2 = PGMChangeMode(pVCpu, CPUMGetGuestCR0(pVCpu), CPUMGetGuestCR4(pVCpu), CPUMGetGuestEFER(pVCpu));
1515	return rc2 == VINF_SUCCESS ? rc : rc2;
1516
1517	case DISCREG_CR2:
1518	rc = CPUMSetGuestCR2(pVCpu, val); AssertRC(rc);
1519	return VINF_SUCCESS;
1520
1521	case DISCREG_CR3:
1522	/* Reloading the current CR3 means the guest just wants to flush the TLBs */
1523	rc = CPUMSetGuestCR3(pVCpu, val); AssertRC(rc);
1524	if (CPUMGetGuestCR0(pVCpu) & X86_CR0_PG)
1525	{
1526	/* flush */
1527	rc = PGMFlushTLB(pVCpu, val, !(CPUMGetGuestCR4(pVCpu) & X86_CR4_PGE));
1528	AssertRC(rc);
1529	}
1530	return rc;
1531
1532	case DISCREG_CR4:
1533	oldval = CPUMGetGuestCR4(pVCpu);
1534	rc = CPUMSetGuestCR4(pVCpu, val); AssertRC(rc);
1535	val = CPUMGetGuestCR4(pVCpu);
1536
1537	/* Illegal to disable PAE when long mode is active. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1538	msrEFER = CPUMGetGuestEFER(pVCpu);
1539	if ( (msrEFER & MSR_K6_EFER_LMA)
1540	&& (oldval & X86_CR4_PAE)
1541	&& !(val & X86_CR4_PAE))
1542	{
1543	return VERR_EM_INTERPRETER; /** @todo generate #GP(0) */
1544	}
1545
1546	/* From IEM iemCImpl_load_CrX. */
1547	/** @todo Check guest CPUID bits for determining corresponding valid bits. */
1548	fValid = X86_CR4_VME \| X86_CR4_PVI
1549	\| X86_CR4_TSD \| X86_CR4_DE
1550	\| X86_CR4_PSE \| X86_CR4_PAE
1551	\| X86_CR4_MCE \| X86_CR4_PGE
1552	\| X86_CR4_PCE \| X86_CR4_OSFXSR
1553	\| X86_CR4_OSXMMEEXCPT;
1554	//if (xxx)
1555	// fValid \|= X86_CR4_VMXE;
1556	//if (xxx)
1557	// fValid \|= X86_CR4_OSXSAVE;
1558	if (val & ~(uint64_t)fValid)
1559	{
1560	Log(("Trying to set reserved CR4 bits: NewCR4=%#llx InvalidBits=%#llx\n", val, val & ~(uint64_t)fValid));
1561	return VERR_EM_INTERPRETER; /** @todo generate #GP(0) */
1562	}
1563
1564	rc = VINF_SUCCESS;
1565	if ( (oldval & (X86_CR4_PGE\|X86_CR4_PAE\|X86_CR4_PSE))
1566	!= (val & (X86_CR4_PGE\|X86_CR4_PAE\|X86_CR4_PSE)))
1567	{
1568	/* global flush */
1569	rc = PGMFlushTLB(pVCpu, CPUMGetGuestCR3(pVCpu), true /* global */);
1570	AssertRCReturn(rc, rc);
1571	}
1572
1573	/* Feeling extremely lazy. */
1574	# ifdef IN_RC
1575	if ( (oldval & (X86_CR4_OSFXSR\|X86_CR4_OSXMMEEXCPT\|X86_CR4_PCE\|X86_CR4_MCE\|X86_CR4_PAE\|X86_CR4_DE\|X86_CR4_TSD\|X86_CR4_PVI\|X86_CR4_VME))
1576	!= (val & (X86_CR4_OSFXSR\|X86_CR4_OSXMMEEXCPT\|X86_CR4_PCE\|X86_CR4_MCE\|X86_CR4_PAE\|X86_CR4_DE\|X86_CR4_TSD\|X86_CR4_PVI\|X86_CR4_VME)))
1577	{
1578	Log(("emInterpretMovCRx: CR4: %#RX64->%#RX64 => R3\n", oldval, val));
1579	VMCPU_FF_SET(pVCpu, VMCPU_FF_TO_R3);
1580	}
1581	# endif
1582	# ifdef VBOX_WITH_RAW_MODE
1583	if (((val ^ oldval) & X86_CR4_VME) && !HMIsEnabled(pVM))
1584	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1585	# endif
1586
1587	rc2 = PGMChangeMode(pVCpu, CPUMGetGuestCR0(pVCpu), CPUMGetGuestCR4(pVCpu), CPUMGetGuestEFER(pVCpu));
1588	return rc2 == VINF_SUCCESS ? rc : rc2;
1589
1590	case DISCREG_CR8:
1591	return PDMApicSetTPR(pVCpu, val << 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
1592
1593	default:
1594	AssertFailed();
1595	case DISCREG_CR1: /* illegal op */
1596	break;
1597	}
1598	return VERR_EM_INTERPRETER;
1599	}
1600
1601
1602	/**
1603	* Interpret CRx write.
1604	*
1605	* @returns VBox status code.
1606	* @param pVM Pointer to the VM.
1607	* @param pVCpu Pointer to the VMCPU.
1608	* @param pRegFrame The register frame.
1609	* @param DestRegCRx CRx register index (DISUSE_REG_CR*)
1610	* @param SrcRegGen General purpose register index (USE_REG_E**))
1611	*
1612	*/
1613	static int emInterpretCRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint32_t SrcRegGen)
1614	{
1615	uint64_t val;
1616	int rc;
1617	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1618
1619	if (CPUMIsGuestIn64BitCode(pVCpu))
1620	rc = DISFetchReg64(pRegFrame, SrcRegGen, &val);
1621	else
1622	{
1623	uint32_t val32;
1624	rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
1625	val = val32;
1626	}
1627
1628	if (RT_SUCCESS(rc))
1629	return emUpdateCRx(pVM, pVCpu, pRegFrame, DestRegCrx, val);
1630
1631	return VERR_EM_INTERPRETER;
1632	}
1633
1634
1635	#ifdef LOG_ENABLED
1636	static const char *emMSRtoString(uint32_t uMsr)
1637	{
1638	switch (uMsr)
1639	{
1640	case MSR_IA32_APICBASE: return "MSR_IA32_APICBASE";
1641	case MSR_IA32_CR_PAT: return "MSR_IA32_CR_PAT";
1642	case MSR_IA32_SYSENTER_CS: return "MSR_IA32_SYSENTER_CS";
1643	case MSR_IA32_SYSENTER_EIP: return "MSR_IA32_SYSENTER_EIP";
1644	case MSR_IA32_SYSENTER_ESP: return "MSR_IA32_SYSENTER_ESP";
1645	case MSR_K6_EFER: return "MSR_K6_EFER";
1646	case MSR_K8_SF_MASK: return "MSR_K8_SF_MASK";
1647	case MSR_K6_STAR: return "MSR_K6_STAR";
1648	case MSR_K8_LSTAR: return "MSR_K8_LSTAR";
1649	case MSR_K8_CSTAR: return "MSR_K8_CSTAR";
1650	case MSR_K8_FS_BASE: return "MSR_K8_FS_BASE";
1651	case MSR_K8_GS_BASE: return "MSR_K8_GS_BASE";
1652	case MSR_K8_KERNEL_GS_BASE: return "MSR_K8_KERNEL_GS_BASE";
1653	case MSR_K8_TSC_AUX: return "MSR_K8_TSC_AUX";
1654	case MSR_IA32_BIOS_SIGN_ID: return "Unsupported MSR_IA32_BIOS_SIGN_ID";
1655	case MSR_IA32_PLATFORM_ID: return "Unsupported MSR_IA32_PLATFORM_ID";
1656	case MSR_IA32_BIOS_UPDT_TRIG: return "Unsupported MSR_IA32_BIOS_UPDT_TRIG";
1657	case MSR_IA32_TSC: return "MSR_IA32_TSC";
1658	case MSR_IA32_MISC_ENABLE: return "MSR_IA32_MISC_ENABLE";
1659	case MSR_IA32_MTRR_CAP: return "MSR_IA32_MTRR_CAP";
1660	case MSR_IA32_MCG_CAP: return "Unsupported MSR_IA32_MCG_CAP";
1661	case MSR_IA32_MCG_STATUS: return "Unsupported MSR_IA32_MCG_STATUS";
1662	case MSR_IA32_MCG_CTRL: return "Unsupported MSR_IA32_MCG_CTRL";
1663	case MSR_IA32_MTRR_DEF_TYPE: return "MSR_IA32_MTRR_DEF_TYPE";
1664	case MSR_K7_EVNTSEL0: return "Unsupported MSR_K7_EVNTSEL0";
1665	case MSR_K7_EVNTSEL1: return "Unsupported MSR_K7_EVNTSEL1";
1666	case MSR_K7_EVNTSEL2: return "Unsupported MSR_K7_EVNTSEL2";
1667	case MSR_K7_EVNTSEL3: return "Unsupported MSR_K7_EVNTSEL3";
1668	case MSR_IA32_MC0_CTL: return "Unsupported MSR_IA32_MC0_CTL";
1669	case MSR_IA32_MC0_STATUS: return "Unsupported MSR_IA32_MC0_STATUS";
1670	case MSR_IA32_PERFEVTSEL0: return "Unsupported MSR_IA32_PERFEVTSEL0";
1671	case MSR_IA32_PERFEVTSEL1: return "Unsupported MSR_IA32_PERFEVTSEL1";
1672	case MSR_IA32_PERF_STATUS: return "MSR_IA32_PERF_STATUS";
1673	case MSR_IA32_PLATFORM_INFO: return "MSR_IA32_PLATFORM_INFO";
1674	case MSR_IA32_PERF_CTL: return "Unsupported MSR_IA32_PERF_CTL";
1675	case MSR_K7_PERFCTR0: return "Unsupported MSR_K7_PERFCTR0";
1676	case MSR_K7_PERFCTR1: return "Unsupported MSR_K7_PERFCTR1";
1677	case MSR_K7_PERFCTR2: return "Unsupported MSR_K7_PERFCTR2";
1678	case MSR_K7_PERFCTR3: return "Unsupported MSR_K7_PERFCTR3";
1679	case MSR_IA32_PMC0: return "Unsupported MSR_IA32_PMC0";
1680	case MSR_IA32_PMC1: return "Unsupported MSR_IA32_PMC1";
1681	case MSR_IA32_PMC2: return "Unsupported MSR_IA32_PMC2";
1682	case MSR_IA32_PMC3: return "Unsupported MSR_IA32_PMC3";
1683	}
1684	return "Unknown MSR";
1685	}
1686	#endif /* LOG_ENABLED */
1687
1688
1689	/**
1690	* Interpret RDMSR
1691	*
1692	* @returns VBox status code.
1693	* @param pVM Pointer to the VM.
1694	* @param pVCpu Pointer to the VMCPU.
1695	* @param pRegFrame The register frame.
1696	*/
1697	VMM_INT_DECL(int) EMInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1698	{
1699	NOREF(pVM);
1700
1701	/* Get the current privilege level. */
1702	if (CPUMGetGuestCPL(pVCpu) != 0)
1703	{
1704	Log4(("EM: Refuse RDMSR: CPL != 0\n"));
1705	return VERR_EM_INTERPRETER; /* supervisor only */
1706	}
1707
1708	uint64_t uValue;
1709	VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pRegFrame->ecx, &uValue);
1710	if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
1711	{
1712	Log4(("EM: Refuse RDMSR: rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1713	Assert(rcStrict == VERR_CPUM_RAISE_GP_0 \|\| rcStrict == VERR_EM_INTERPRETER \|\| rcStrict == VINF_CPUM_R3_MSR_READ);
1714	return VERR_EM_INTERPRETER;
1715	}
1716	pRegFrame->rax = (uint32_t) uValue;
1717	pRegFrame->rdx = (uint32_t)(uValue >> 32);
1718	LogFlow(("EMInterpretRdmsr %s (%x) -> %RX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx, uValue));
1719	return VINF_SUCCESS;
1720	}
1721
1722
1723	/**
1724	* Interpret WRMSR
1725	*
1726	* @returns VBox status code.
1727	* @param pVM Pointer to the VM.
1728	* @param pVCpu Pointer to the VMCPU.
1729	* @param pRegFrame The register frame.
1730	*/
1731	VMM_INT_DECL(int) EMInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1732	{
1733	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1734
1735	/* Check the current privilege level, this instruction is supervisor only. */
1736	if (CPUMGetGuestCPL(pVCpu) != 0)
1737	{
1738	Log4(("EM: Refuse WRMSR: CPL != 0\n"));
1739	return VERR_EM_INTERPRETER; /** @todo raise \#GP(0) */
1740	}
1741
1742	VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pRegFrame->ecx, RT_MAKE_U64(pRegFrame->eax, pRegFrame->edx));
1743	if (rcStrict != VINF_SUCCESS)
1744	{
1745	Log4(("EM: Refuse WRMSR: CPUMSetGuestMsr returned %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1746	Assert(rcStrict == VERR_CPUM_RAISE_GP_0 \|\| rcStrict == VERR_EM_INTERPRETER \|\| rcStrict == VINF_CPUM_R3_MSR_WRITE);
1747	return VERR_EM_INTERPRETER;
1748	}
1749	LogFlow(("EMInterpretWrmsr %s (%x) val=%RX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx,
1750	RT_MAKE_U64(pRegFrame->eax, pRegFrame->edx)));
1751	NOREF(pVM);
1752	return VINF_SUCCESS;
1753	}
1754
1755
1756	/**
1757	* Interpret CRx read.
1758	*
1759	* @returns VBox status code.
1760	* @param pVM Pointer to the VM.
1761	* @param pVCpu Pointer to the VMCPU.
1762	* @param pRegFrame The register frame.
1763	* @param DestRegGen General purpose register index (USE_REG_E**))
1764	* @param SrcRegCRx CRx register index (DISUSE_REG_CR*)
1765	*
1766	*/
1767	static int emInterpretCRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx)
1768	{
1769	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1770	uint64_t val64;
1771	int rc = CPUMGetGuestCRx(pVCpu, SrcRegCrx, &val64);
1772	AssertMsgRCReturn(rc, ("CPUMGetGuestCRx %d failed\n", SrcRegCrx), VERR_EM_INTERPRETER);
1773	NOREF(pVM);
1774
1775	if (CPUMIsGuestIn64BitCode(pVCpu))
1776	rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
1777	else
1778	rc = DISWriteReg32(pRegFrame, DestRegGen, val64);
1779
1780	if (RT_SUCCESS(rc))
1781	{
1782	LogFlow(("MOV_CR: gen32=%d CR=%d val=%RX64\n", DestRegGen, SrcRegCrx, val64));
1783	return VINF_SUCCESS;
1784	}
1785	return VERR_EM_INTERPRETER;
1786	}
1787
1788
1789	/**
1790	* Interpret DRx write.
1791	*
1792	* @returns VBox status code.
1793	* @param pVM Pointer to the VM.
1794	* @param pVCpu Pointer to the VMCPU.
1795	* @param pRegFrame The register frame.
1796	* @param DestRegDRx DRx register index (USE_REG_DR*)
1797	* @param SrcRegGen General purpose register index (USE_REG_E**))
1798	*
1799	*/
1800	VMM_INT_DECL(int) EMInterpretDRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen)
1801	{
1802	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1803	uint64_t uNewDrX;
1804	int rc;
1805	NOREF(pVM);
1806
1807	if (CPUMIsGuestIn64BitCode(pVCpu))
1808	rc = DISFetchReg64(pRegFrame, SrcRegGen, &uNewDrX);
1809	else
1810	{
1811	uint32_t val32;
1812	rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
1813	uNewDrX = val32;
1814	}
1815
1816	if (RT_SUCCESS(rc))
1817	{
1818	if (DestRegDrx == 6)
1819	{
1820	uNewDrX \|= X86_DR6_RA1_MASK;
1821	uNewDrX &= ~X86_DR6_RAZ_MASK;
1822	}
1823	else if (DestRegDrx == 7)
1824	{
1825	uNewDrX \|= X86_DR7_RA1_MASK;
1826	uNewDrX &= ~X86_DR7_RAZ_MASK;
1827	}
1828
1829	/** @todo we don't fail if illegal bits are set/cleared for e.g. dr7 */
1830	rc = CPUMSetGuestDRx(pVCpu, DestRegDrx, uNewDrX);
1831	if (RT_SUCCESS(rc))
1832	return rc;
1833	AssertMsgFailed(("CPUMSetGuestDRx %d failed\n", DestRegDrx));
1834	}
1835	return VERR_EM_INTERPRETER;
1836	}
1837
1838
1839	/**
1840	* Interpret DRx read.
1841	*
1842	* @returns VBox status code.
1843	* @param pVM Pointer to the VM.
1844	* @param pVCpu Pointer to the VMCPU.
1845	* @param pRegFrame The register frame.
1846	* @param DestRegGen General purpose register index (USE_REG_E**))
1847	* @param SrcRegDRx DRx register index (USE_REG_DR*)
1848	*
1849	*/
1850	VMM_INT_DECL(int) EMInterpretDRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx)
1851	{
1852	uint64_t val64;
1853	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1854	NOREF(pVM);
1855
1856	int rc = CPUMGetGuestDRx(pVCpu, SrcRegDrx, &val64);
1857	AssertMsgRCReturn(rc, ("CPUMGetGuestDRx %d failed\n", SrcRegDrx), VERR_EM_INTERPRETER);
1858	if (CPUMIsGuestIn64BitCode(pVCpu))
1859	rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
1860	else
1861	rc = DISWriteReg32(pRegFrame, DestRegGen, (uint32_t)val64);
1862
1863	if (RT_SUCCESS(rc))
1864	return VINF_SUCCESS;
1865
1866	return VERR_EM_INTERPRETER;
1867	}
1868
1869
1870	#if !defined(VBOX_WITH_IEM) \|\| defined(VBOX_COMPARE_IEM_AND_EM)
1871
1872
1873
1874
1875
1876
1877	/*
1878	*
1879	* The old interpreter.
1880	* The old interpreter.
1881	* The old interpreter.
1882	* The old interpreter.
1883	* The old interpreter.
1884	*
1885	*/
1886
1887	DECLINLINE(int) emRamRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCPTR GCPtrSrc, uint32_t cb)
1888	{
1889	#ifdef IN_RC
1890	int rc = MMGCRamRead(pVM, pvDst, (void *)(uintptr_t)GCPtrSrc, cb);
1891	if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
1892	return rc;
1893	/*
1894	* The page pool cache may end up here in some cases because it
1895	* flushed one of the shadow mappings used by the trapping
1896	* instruction and it either flushed the TLB or the CPU reused it.
1897	*/
1898	#else
1899	NOREF(pVM);
1900	#endif
1901	return PGMPhysInterpretedReadNoHandlers(pVCpu, pCtxCore, pvDst, GCPtrSrc, cb, /fMayTrap/ false);
1902	}
1903
1904
1905	DECLINLINE(int) emRamWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, RTGCPTR GCPtrDst, const void *pvSrc, uint32_t cb)
1906	{
1907	/* Don't use MMGCRamWrite here as it does not respect zero pages, shared
1908	pages or write monitored pages. */
1909	NOREF(pVM);
1910	#if !defined(VBOX_COMPARE_IEM_AND_EM) \|\| !defined(VBOX_COMPARE_IEM_LAST)
1911	int rc = PGMPhysInterpretedWriteNoHandlers(pVCpu, pCtxCore, GCPtrDst, pvSrc, cb, /fMayTrap/ false);
1912	#else
1913	int rc = VINF_SUCCESS;
1914	#endif
1915	#ifdef VBOX_COMPARE_IEM_AND_EM
1916	Log(("EM Wrote: %RGv %.*Rhxs rc=%Rrc\n", GCPtrDst, RT_MAX(RT_MIN(cb, 64), 1), pvSrc, rc));
1917	g_cbEmWrote = cb;
1918	memcpy(g_abEmWrote, pvSrc, RT_MIN(cb, sizeof(g_abEmWrote)));
1919	#endif
1920	return rc;
1921	}
1922
1923
1924	/** Convert sel:addr to a flat GC address. */
1925	DECLINLINE(RTGCPTR) emConvertToFlatAddr(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pDis, PDISOPPARAM pParam, RTGCPTR pvAddr)
1926	{
1927	DISSELREG enmPrefixSeg = DISDetectSegReg(pDis, pParam);
1928	return SELMToFlat(pVM, enmPrefixSeg, pRegFrame, pvAddr);
1929	}
1930
1931
1932	#if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
1933	/**
1934	* Get the mnemonic for the disassembled instruction.
1935	*
1936	* GC/R0 doesn't include the strings in the DIS tables because
1937	* of limited space.
1938	*/
1939	static const char *emGetMnemonic(PDISCPUSTATE pDis)
1940	{
1941	switch (pDis->pCurInstr->uOpcode)
1942	{
1943	case OP_XCHG: return "Xchg";
1944	case OP_DEC: return "Dec";
1945	case OP_INC: return "Inc";
1946	case OP_POP: return "Pop";
1947	case OP_OR: return "Or";
1948	case OP_AND: return "And";
1949	case OP_MOV: return "Mov";
1950	case OP_INVLPG: return "InvlPg";
1951	case OP_CPUID: return "CpuId";
1952	case OP_MOV_CR: return "MovCRx";
1953	case OP_MOV_DR: return "MovDRx";
1954	case OP_LLDT: return "LLdt";
1955	case OP_LGDT: return "LGdt";
1956	case OP_LIDT: return "LIdt";
1957	case OP_CLTS: return "Clts";
1958	case OP_MONITOR: return "Monitor";
1959	case OP_MWAIT: return "MWait";
1960	case OP_RDMSR: return "Rdmsr";
1961	case OP_WRMSR: return "Wrmsr";
1962	case OP_ADD: return "Add";
1963	case OP_ADC: return "Adc";
1964	case OP_SUB: return "Sub";
1965	case OP_SBB: return "Sbb";
1966	case OP_RDTSC: return "Rdtsc";
1967	case OP_STI: return "Sti";
1968	case OP_CLI: return "Cli";
1969	case OP_XADD: return "XAdd";
1970	case OP_HLT: return "Hlt";
1971	case OP_IRET: return "Iret";
1972	case OP_MOVNTPS: return "MovNTPS";
1973	case OP_STOSWD: return "StosWD";
1974	case OP_WBINVD: return "WbInvd";
1975	case OP_XOR: return "Xor";
1976	case OP_BTR: return "Btr";
1977	case OP_BTS: return "Bts";
1978	case OP_BTC: return "Btc";
1979	case OP_LMSW: return "Lmsw";
1980	case OP_SMSW: return "Smsw";
1981	case OP_CMPXCHG: return pDis->fPrefix & DISPREFIX_LOCK ? "Lock CmpXchg" : "CmpXchg";
1982	case OP_CMPXCHG8B: return pDis->fPrefix & DISPREFIX_LOCK ? "Lock CmpXchg8b" : "CmpXchg8b";
1983
1984	default:
1985	Log(("Unknown opcode %d\n", pDis->pCurInstr->uOpcode));
1986	return "???";
1987	}
1988	}
1989	#endif /* VBOX_STRICT \|\| LOG_ENABLED */
1990
1991
1992	/**
1993	* XCHG instruction emulation.
1994	*/
1995	static int emInterpretXchg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1996	{
1997	DISQPVPARAMVAL param1, param2;
1998	NOREF(pvFault);
1999
2000	/* Source to make DISQueryParamVal read the register value - ugly hack */
2001	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
2002	if(RT_FAILURE(rc))
2003	return VERR_EM_INTERPRETER;
2004
2005	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2006	if(RT_FAILURE(rc))
2007	return VERR_EM_INTERPRETER;
2008
2009	#ifdef IN_RC
2010	if (TRPMHasTrap(pVCpu))
2011	{
2012	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2013	{
2014	#endif
2015	RTGCPTR pParam1 = 0, pParam2 = 0;
2016	uint64_t valpar1, valpar2;
2017
2018	AssertReturn(pDis->Param1.cb == pDis->Param2.cb, VERR_EM_INTERPRETER);
2019	switch(param1.type)
2020	{
2021	case DISQPV_TYPE_IMMEDIATE: /* register type is translated to this one too */
2022	valpar1 = param1.val.val64;
2023	break;
2024
2025	case DISQPV_TYPE_ADDRESS:
2026	pParam1 = (RTGCPTR)param1.val.val64;
2027	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2028	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
2029	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
2030	if (RT_FAILURE(rc))
2031	{
2032	AssertMsgFailed(("MMGCRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2033	return VERR_EM_INTERPRETER;
2034	}
2035	break;
2036
2037	default:
2038	AssertFailed();
2039	return VERR_EM_INTERPRETER;
2040	}
2041
2042	switch(param2.type)
2043	{
2044	case DISQPV_TYPE_ADDRESS:
2045	pParam2 = (RTGCPTR)param2.val.val64;
2046	pParam2 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param2, pParam2);
2047	EM_ASSERT_FAULT_RETURN(pParam2 == pvFault, VERR_EM_INTERPRETER);
2048	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar2, pParam2, param2.size);
2049	if (RT_FAILURE(rc))
2050	{
2051	AssertMsgFailed(("MMGCRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2052	}
2053	break;
2054
2055	case DISQPV_TYPE_IMMEDIATE:
2056	valpar2 = param2.val.val64;
2057	break;
2058
2059	default:
2060	AssertFailed();
2061	return VERR_EM_INTERPRETER;
2062	}
2063
2064	/* Write value of parameter 2 to parameter 1 (reg or memory address) */
2065	if (pParam1 == 0)
2066	{
2067	Assert(param1.type == DISQPV_TYPE_IMMEDIATE); /* register actually */
2068	switch(param1.size)
2069	{
2070	case 1: //special case for AH etc
2071	rc = DISWriteReg8(pRegFrame, pDis->Param1.Base.idxGenReg, (uint8_t )valpar2); break;
2072	case 2: rc = DISWriteReg16(pRegFrame, pDis->Param1.Base.idxGenReg, (uint16_t)valpar2); break;
2073	case 4: rc = DISWriteReg32(pRegFrame, pDis->Param1.Base.idxGenReg, (uint32_t)valpar2); break;
2074	case 8: rc = DISWriteReg64(pRegFrame, pDis->Param1.Base.idxGenReg, valpar2); break;
2075	default: AssertFailedReturn(VERR_EM_INTERPRETER);
2076	}
2077	if (RT_FAILURE(rc))
2078	return VERR_EM_INTERPRETER;
2079	}
2080	else
2081	{
2082	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar2, param1.size);
2083	if (RT_FAILURE(rc))
2084	{
2085	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2086	return VERR_EM_INTERPRETER;
2087	}
2088	}
2089
2090	/* Write value of parameter 1 to parameter 2 (reg or memory address) */
2091	if (pParam2 == 0)
2092	{
2093	Assert(param2.type == DISQPV_TYPE_IMMEDIATE); /* register actually */
2094	switch(param2.size)
2095	{
2096	case 1: //special case for AH etc
2097	rc = DISWriteReg8(pRegFrame, pDis->Param2.Base.idxGenReg, (uint8_t )valpar1); break;
2098	case 2: rc = DISWriteReg16(pRegFrame, pDis->Param2.Base.idxGenReg, (uint16_t)valpar1); break;
2099	case 4: rc = DISWriteReg32(pRegFrame, pDis->Param2.Base.idxGenReg, (uint32_t)valpar1); break;
2100	case 8: rc = DISWriteReg64(pRegFrame, pDis->Param2.Base.idxGenReg, valpar1); break;
2101	default: AssertFailedReturn(VERR_EM_INTERPRETER);
2102	}
2103	if (RT_FAILURE(rc))
2104	return VERR_EM_INTERPRETER;
2105	}
2106	else
2107	{
2108	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam2, &valpar1, param2.size);
2109	if (RT_FAILURE(rc))
2110	{
2111	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2112	return VERR_EM_INTERPRETER;
2113	}
2114	}
2115
2116	*pcbSize = param2.size;
2117	return VINF_SUCCESS;
2118	#ifdef IN_RC
2119	}
2120	}
2121	return VERR_EM_INTERPRETER;
2122	#endif
2123	}
2124
2125
2126	/**
2127	* INC and DEC emulation.
2128	*/
2129	static int emInterpretIncDec(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
2130	PFNEMULATEPARAM2 pfnEmulate)
2131	{
2132	DISQPVPARAMVAL param1;
2133	NOREF(pvFault);
2134
2135	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2136	if(RT_FAILURE(rc))
2137	return VERR_EM_INTERPRETER;
2138
2139	#ifdef IN_RC
2140	if (TRPMHasTrap(pVCpu))
2141	{
2142	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2143	{
2144	#endif
2145	RTGCPTR pParam1 = 0;
2146	uint64_t valpar1;
2147
2148	if (param1.type == DISQPV_TYPE_ADDRESS)
2149	{
2150	pParam1 = (RTGCPTR)param1.val.val64;
2151	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2152	#ifdef IN_RC
2153	/* Safety check (in theory it could cross a page boundary and fault there though) */
2154	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
2155	#endif
2156	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
2157	if (RT_FAILURE(rc))
2158	{
2159	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2160	return VERR_EM_INTERPRETER;
2161	}
2162	}
2163	else
2164	{
2165	AssertFailed();
2166	return VERR_EM_INTERPRETER;
2167	}
2168
2169	uint32_t eflags;
2170
2171	eflags = pfnEmulate(&valpar1, param1.size);
2172
2173	/* Write result back */
2174	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, param1.size);
2175	if (RT_FAILURE(rc))
2176	{
2177	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2178	return VERR_EM_INTERPRETER;
2179	}
2180
2181	/* Update guest's eflags and finish. */
2182	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2183	\| (eflags & (X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2184
2185	/* All done! */
2186	*pcbSize = param1.size;
2187	return VINF_SUCCESS;
2188	#ifdef IN_RC
2189	}
2190	}
2191	return VERR_EM_INTERPRETER;
2192	#endif
2193	}
2194
2195
2196	/**
2197	* POP Emulation.
2198	*/
2199	static int emInterpretPop(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2200	{
2201	Assert(pDis->uCpuMode != DISCPUMODE_64BIT); /** @todo check */
2202	DISQPVPARAMVAL param1;
2203	NOREF(pvFault);
2204
2205	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2206	if(RT_FAILURE(rc))
2207	return VERR_EM_INTERPRETER;
2208
2209	#ifdef IN_RC
2210	if (TRPMHasTrap(pVCpu))
2211	{
2212	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2213	{
2214	#endif
2215	RTGCPTR pParam1 = 0;
2216	uint32_t valpar1;
2217	RTGCPTR pStackVal;
2218
2219	/* Read stack value first */
2220	if (CPUMGetGuestCodeBits(pVCpu) == 16)
2221	return VERR_EM_INTERPRETER; /* No legacy 16 bits stuff here, please. */
2222
2223	/* Convert address; don't bother checking limits etc, as we only read here */
2224	pStackVal = SELMToFlat(pVM, DISSELREG_SS, pRegFrame, (RTGCPTR)pRegFrame->esp);
2225	if (pStackVal == 0)
2226	return VERR_EM_INTERPRETER;
2227
2228	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pStackVal, param1.size);
2229	if (RT_FAILURE(rc))
2230	{
2231	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2232	return VERR_EM_INTERPRETER;
2233	}
2234
2235	if (param1.type == DISQPV_TYPE_ADDRESS)
2236	{
2237	pParam1 = (RTGCPTR)param1.val.val64;
2238
2239	/* pop [esp+xx] uses esp after the actual pop! */
2240	AssertCompile(DISGREG_ESP == DISGREG_SP);
2241	if ( (pDis->Param1.fUse & DISUSE_BASE)
2242	&& (pDis->Param1.fUse & (DISUSE_REG_GEN16\|DISUSE_REG_GEN32))
2243	&& pDis->Param1.Base.idxGenReg == DISGREG_ESP
2244	)
2245	pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + param1.size);
2246
2247	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2248	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault \|\| (RTGCPTR)pRegFrame->esp == pvFault, VERR_EM_INTERPRETER);
2249	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, param1.size);
2250	if (RT_FAILURE(rc))
2251	{
2252	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2253	return VERR_EM_INTERPRETER;
2254	}
2255
2256	/* Update ESP as the last step */
2257	pRegFrame->esp += param1.size;
2258	}
2259	else
2260	{
2261	#ifndef DEBUG_bird // annoying assertion.
2262	AssertFailed();
2263	#endif
2264	return VERR_EM_INTERPRETER;
2265	}
2266
2267	/* All done! */
2268	*pcbSize = param1.size;
2269	return VINF_SUCCESS;
2270	#ifdef IN_RC
2271	}
2272	}
2273	return VERR_EM_INTERPRETER;
2274	#endif
2275	}
2276
2277
2278	/**
2279	* XOR/OR/AND Emulation.
2280	*/
2281	static int emInterpretOrXorAnd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
2282	PFNEMULATEPARAM3 pfnEmulate)
2283	{
2284	DISQPVPARAMVAL param1, param2;
2285	NOREF(pvFault);
2286
2287	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2288	if(RT_FAILURE(rc))
2289	return VERR_EM_INTERPRETER;
2290
2291	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2292	if(RT_FAILURE(rc))
2293	return VERR_EM_INTERPRETER;
2294
2295	#ifdef IN_RC
2296	if (TRPMHasTrap(pVCpu))
2297	{
2298	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2299	{
2300	#endif
2301	RTGCPTR pParam1;
2302	uint64_t valpar1, valpar2;
2303
2304	if (pDis->Param1.cb != pDis->Param2.cb)
2305	{
2306	if (pDis->Param1.cb < pDis->Param2.cb)
2307	{
2308	AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip, pDis->Param1.cb, pDis->Param2.cb)); /* should never happen! */
2309	return VERR_EM_INTERPRETER;
2310	}
2311	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
2312	pDis->Param2.cb = pDis->Param1.cb;
2313	param2.size = param1.size;
2314	}
2315
2316	/* The destination is always a virtual address */
2317	if (param1.type == DISQPV_TYPE_ADDRESS)
2318	{
2319	pParam1 = (RTGCPTR)param1.val.val64;
2320	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2321	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
2322	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
2323	if (RT_FAILURE(rc))
2324	{
2325	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2326	return VERR_EM_INTERPRETER;
2327	}
2328	}
2329	else
2330	{
2331	AssertFailed();
2332	return VERR_EM_INTERPRETER;
2333	}
2334
2335	/* Register or immediate data */
2336	switch(param2.type)
2337	{
2338	case DISQPV_TYPE_IMMEDIATE: /* both immediate data and register (ugly) */
2339	valpar2 = param2.val.val64;
2340	break;
2341
2342	default:
2343	AssertFailed();
2344	return VERR_EM_INTERPRETER;
2345	}
2346
2347	LogFlow(("emInterpretOrXorAnd %s %RGv %RX64 - %RX64 size %d (%d)\n", emGetMnemonic(pDis), pParam1, valpar1, valpar2, param2.size, param1.size));
2348
2349	/* Data read, emulate instruction. */
2350	uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
2351
2352	LogFlow(("emInterpretOrXorAnd %s result %RX64\n", emGetMnemonic(pDis), valpar1));
2353
2354	/* Update guest's eflags and finish. */
2355	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2356	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2357
2358	/* And write it back */
2359	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, param1.size);
2360	if (RT_SUCCESS(rc))
2361	{
2362	/* All done! */
2363	*pcbSize = param2.size;
2364	return VINF_SUCCESS;
2365	}
2366	#ifdef IN_RC
2367	}
2368	}
2369	#endif
2370	return VERR_EM_INTERPRETER;
2371	}
2372
2373
2374	#ifndef VBOX_COMPARE_IEM_AND_EM
2375	/**
2376	* LOCK XOR/OR/AND Emulation.
2377	*/
2378	static int emInterpretLockOrXorAnd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
2379	uint32_t *pcbSize, PFNEMULATELOCKPARAM3 pfnEmulate)
2380	{
2381	void *pvParam1;
2382	DISQPVPARAMVAL param1, param2;
2383	NOREF(pvFault);
2384
2385	#if HC_ARCH_BITS == 32
2386	Assert(pDis->Param1.cb <= 4);
2387	#endif
2388
2389	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2390	if(RT_FAILURE(rc))
2391	return VERR_EM_INTERPRETER;
2392
2393	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2394	if(RT_FAILURE(rc))
2395	return VERR_EM_INTERPRETER;
2396
2397	if (pDis->Param1.cb != pDis->Param2.cb)
2398	{
2399	AssertMsgReturn(pDis->Param1.cb >= pDis->Param2.cb, /* should never happen! */
2400	("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip, pDis->Param1.cb, pDis->Param2.cb),
2401	VERR_EM_INTERPRETER);
2402
2403	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
2404	pDis->Param2.cb = pDis->Param1.cb;
2405	param2.size = param1.size;
2406	}
2407
2408	#ifdef IN_RC
2409	/* Safety check (in theory it could cross a page boundary and fault there though) */
2410	Assert( TRPMHasTrap(pVCpu)
2411	&& (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW));
2412	EM_ASSERT_FAULT_RETURN(GCPtrPar1 == pvFault, VERR_EM_INTERPRETER);
2413	#endif
2414
2415	/* Register and immediate data == DISQPV_TYPE_IMMEDIATE */
2416	AssertReturn(param2.type == DISQPV_TYPE_IMMEDIATE, VERR_EM_INTERPRETER);
2417	RTGCUINTREG ValPar2 = param2.val.val64;
2418
2419	/* The destination is always a virtual address */
2420	AssertReturn(param1.type == DISQPV_TYPE_ADDRESS, VERR_EM_INTERPRETER);
2421
2422	RTGCPTR GCPtrPar1 = param1.val.val64;
2423	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, GCPtrPar1);
2424	PGMPAGEMAPLOCK Lock;
2425	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
2426	AssertRCReturn(rc, VERR_EM_INTERPRETER);
2427
2428	/* Try emulate it with a one-shot #PF handler in place. (RC) */
2429	Log2(("%s %RGv imm%d=%RX64\n", emGetMnemonic(pDis), GCPtrPar1, pDis->Param2.cb*8, ValPar2));
2430
2431	RTGCUINTREG32 eflags = 0;
2432	rc = pfnEmulate(pvParam1, ValPar2, pDis->Param2.cb, &eflags);
2433	PGMPhysReleasePageMappingLock(pVM, &Lock);
2434	if (RT_FAILURE(rc))
2435	{
2436	Log(("%s %RGv imm%d=%RX64-> emulation failed due to page fault!\n", emGetMnemonic(pDis), GCPtrPar1, pDis->Param2.cb*8, ValPar2));
2437	return VERR_EM_INTERPRETER;
2438	}
2439
2440	/* Update guest's eflags and finish. */
2441	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2442	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2443
2444	*pcbSize = param2.size;
2445	return VINF_SUCCESS;
2446	}
2447	#endif /* !VBOX_COMPARE_IEM_AND_EM */
2448
2449
2450	/**
2451	* ADD, ADC & SUB Emulation.
2452	*/
2453	static int emInterpretAddSub(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
2454	PFNEMULATEPARAM3 pfnEmulate)
2455	{
2456	NOREF(pvFault);
2457	DISQPVPARAMVAL param1, param2;
2458	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2459	if(RT_FAILURE(rc))
2460	return VERR_EM_INTERPRETER;
2461
2462	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2463	if(RT_FAILURE(rc))
2464	return VERR_EM_INTERPRETER;
2465
2466	#ifdef IN_RC
2467	if (TRPMHasTrap(pVCpu))
2468	{
2469	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2470	{
2471	#endif
2472	RTGCPTR pParam1;
2473	uint64_t valpar1, valpar2;
2474
2475	if (pDis->Param1.cb != pDis->Param2.cb)
2476	{
2477	if (pDis->Param1.cb < pDis->Param2.cb)
2478	{
2479	AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip, pDis->Param1.cb, pDis->Param2.cb)); /* should never happen! */
2480	return VERR_EM_INTERPRETER;
2481	}
2482	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
2483	pDis->Param2.cb = pDis->Param1.cb;
2484	param2.size = param1.size;
2485	}
2486
2487	/* The destination is always a virtual address */
2488	if (param1.type == DISQPV_TYPE_ADDRESS)
2489	{
2490	pParam1 = (RTGCPTR)param1.val.val64;
2491	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2492	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
2493	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
2494	if (RT_FAILURE(rc))
2495	{
2496	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2497	return VERR_EM_INTERPRETER;
2498	}
2499	}
2500	else
2501	{
2502	#ifndef DEBUG_bird
2503	AssertFailed();
2504	#endif
2505	return VERR_EM_INTERPRETER;
2506	}
2507
2508	/* Register or immediate data */
2509	switch(param2.type)
2510	{
2511	case DISQPV_TYPE_IMMEDIATE: /* both immediate data and register (ugly) */
2512	valpar2 = param2.val.val64;
2513	break;
2514
2515	default:
2516	AssertFailed();
2517	return VERR_EM_INTERPRETER;
2518	}
2519
2520	/* Data read, emulate instruction. */
2521	uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
2522
2523	/* Update guest's eflags and finish. */
2524	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2525	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2526
2527	/* And write it back */
2528	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, param1.size);
2529	if (RT_SUCCESS(rc))
2530	{
2531	/* All done! */
2532	*pcbSize = param2.size;
2533	return VINF_SUCCESS;
2534	}
2535	#ifdef IN_RC
2536	}
2537	}
2538	#endif
2539	return VERR_EM_INTERPRETER;
2540	}
2541
2542
2543	/**
2544	* ADC Emulation.
2545	*/
2546	static int emInterpretAdc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2547	{
2548	if (pRegFrame->eflags.Bits.u1CF)
2549	return emInterpretAddSub(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, EMEmulateAdcWithCarrySet);
2550	else
2551	return emInterpretAddSub(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, EMEmulateAdd);
2552	}
2553
2554
2555	/**
2556	* BTR/C/S Emulation.
2557	*/
2558	static int emInterpretBitTest(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
2559	PFNEMULATEPARAM2UINT32 pfnEmulate)
2560	{
2561	DISQPVPARAMVAL param1, param2;
2562	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2563	if(RT_FAILURE(rc))
2564	return VERR_EM_INTERPRETER;
2565
2566	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2567	if(RT_FAILURE(rc))
2568	return VERR_EM_INTERPRETER;
2569
2570	#ifdef IN_RC
2571	if (TRPMHasTrap(pVCpu))
2572	{
2573	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2574	{
2575	#endif
2576	RTGCPTR pParam1;
2577	uint64_t valpar1 = 0, valpar2;
2578	uint32_t eflags;
2579
2580	/* The destination is always a virtual address */
2581	if (param1.type != DISQPV_TYPE_ADDRESS)
2582	return VERR_EM_INTERPRETER;
2583
2584	pParam1 = (RTGCPTR)param1.val.val64;
2585	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2586
2587	/* Register or immediate data */
2588	switch(param2.type)
2589	{
2590	case DISQPV_TYPE_IMMEDIATE: /* both immediate data and register (ugly) */
2591	valpar2 = param2.val.val64;
2592	break;
2593
2594	default:
2595	AssertFailed();
2596	return VERR_EM_INTERPRETER;
2597	}
2598
2599	Log2(("emInterpret%s: pvFault=%RGv pParam1=%RGv val2=%x\n", emGetMnemonic(pDis), pvFault, pParam1, valpar2));
2600	pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + valpar2/8);
2601	EM_ASSERT_FAULT_RETURN((RTGCPTR)((RTGCUINTPTR)pParam1 & ~3) == pvFault, VERR_EM_INTERPRETER); NOREF(pvFault);
2602	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, 1);
2603	if (RT_FAILURE(rc))
2604	{
2605	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2606	return VERR_EM_INTERPRETER;
2607	}
2608
2609	Log2(("emInterpretBtx: val=%x\n", valpar1));
2610	/* Data read, emulate bit test instruction. */
2611	eflags = pfnEmulate(&valpar1, valpar2 & 0x7);
2612
2613	Log2(("emInterpretBtx: val=%x CF=%d\n", valpar1, !!(eflags & X86_EFL_CF)));
2614
2615	/* Update guest's eflags and finish. */
2616	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2617	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2618
2619	/* And write it back */
2620	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, 1);
2621	if (RT_SUCCESS(rc))
2622	{
2623	/* All done! */
2624	*pcbSize = 1;
2625	return VINF_SUCCESS;
2626	}
2627	#ifdef IN_RC
2628	}
2629	}
2630	#endif
2631	return VERR_EM_INTERPRETER;
2632	}
2633
2634
2635	#ifndef VBOX_COMPARE_IEM_AND_EM
2636	/**
2637	* LOCK BTR/C/S Emulation.
2638	*/
2639	static int emInterpretLockBitTest(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
2640	uint32_t *pcbSize, PFNEMULATELOCKPARAM2 pfnEmulate)
2641	{
2642	void *pvParam1;
2643
2644	DISQPVPARAMVAL param1, param2;
2645	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2646	if(RT_FAILURE(rc))
2647	return VERR_EM_INTERPRETER;
2648
2649	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2650	if(RT_FAILURE(rc))
2651	return VERR_EM_INTERPRETER;
2652
2653	/* The destination is always a virtual address */
2654	if (param1.type != DISQPV_TYPE_ADDRESS)
2655	return VERR_EM_INTERPRETER;
2656
2657	/* Register and immediate data == DISQPV_TYPE_IMMEDIATE */
2658	AssertReturn(param2.type == DISQPV_TYPE_IMMEDIATE, VERR_EM_INTERPRETER);
2659	uint64_t ValPar2 = param2.val.val64;
2660
2661	/* Adjust the parameters so what we're dealing with is a bit within the byte pointed to. */
2662	RTGCPTR GCPtrPar1 = param1.val.val64;
2663	GCPtrPar1 = (GCPtrPar1 + ValPar2 / 8);
2664	ValPar2 &= 7;
2665
2666	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, GCPtrPar1);
2667	#ifdef IN_RC
2668	Assert(TRPMHasTrap(pVCpu));
2669	EM_ASSERT_FAULT_RETURN((RTGCPTR)((RTGCUINTPTR)GCPtrPar1 & ~(RTGCUINTPTR)3) == pvFault, VERR_EM_INTERPRETER);
2670	#endif
2671
2672	PGMPAGEMAPLOCK Lock;
2673	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
2674	AssertRCReturn(rc, VERR_EM_INTERPRETER);
2675
2676	Log2(("emInterpretLockBitTest %s: pvFault=%RGv GCPtrPar1=%RGv imm=%RX64\n", emGetMnemonic(pDis), pvFault, GCPtrPar1, ValPar2));
2677	NOREF(pvFault);
2678
2679	/* Try emulate it with a one-shot #PF handler in place. (RC) */
2680	RTGCUINTREG32 eflags = 0;
2681	rc = pfnEmulate(pvParam1, ValPar2, &eflags);
2682	PGMPhysReleasePageMappingLock(pVM, &Lock);
2683	if (RT_FAILURE(rc))
2684	{
2685	Log(("emInterpretLockBitTest %s: %RGv imm%d=%RX64 -> emulation failed due to page fault!\n",
2686	emGetMnemonic(pDis), GCPtrPar1, pDis->Param2.cb*8, ValPar2));
2687	return VERR_EM_INTERPRETER;
2688	}
2689
2690	Log2(("emInterpretLockBitTest %s: GCPtrPar1=%RGv imm=%RX64 CF=%d\n", emGetMnemonic(pDis), GCPtrPar1, ValPar2, !!(eflags & X86_EFL_CF)));
2691
2692	/* Update guest's eflags and finish. */
2693	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2694	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2695
2696	*pcbSize = 1;
2697	return VINF_SUCCESS;
2698	}
2699	#endif /* !VBOX_COMPARE_IEM_AND_EM */
2700
2701
2702	/**
2703	* MOV emulation.
2704	*/
2705	static int emInterpretMov(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2706	{
2707	NOREF(pvFault);
2708	DISQPVPARAMVAL param1, param2;
2709	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2710	if(RT_FAILURE(rc))
2711	return VERR_EM_INTERPRETER;
2712
2713	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2714	if(RT_FAILURE(rc))
2715	return VERR_EM_INTERPRETER;
2716
2717	/* If destination is a segment register, punt. We can't handle it here.
2718	* NB: Source can be a register and still trigger a #PF!
2719	*/
2720	if (RT_UNLIKELY(pDis->Param1.fUse == DISUSE_REG_SEG))
2721	return VERR_EM_INTERPRETER;
2722
2723	if (param1.type == DISQPV_TYPE_ADDRESS)
2724	{
2725	RTGCPTR pDest;
2726	uint64_t val64;
2727
2728	switch(param1.type)
2729	{
2730	case DISQPV_TYPE_IMMEDIATE:
2731	if(!(param1.flags & (DISQPV_FLAG_32\|DISQPV_FLAG_64)))
2732	return VERR_EM_INTERPRETER;
2733	/* fallthru */
2734
2735	case DISQPV_TYPE_ADDRESS:
2736	pDest = (RTGCPTR)param1.val.val64;
2737	pDest = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pDest);
2738	break;
2739
2740	default:
2741	AssertFailed();
2742	return VERR_EM_INTERPRETER;
2743	}
2744
2745	switch(param2.type)
2746	{
2747	case DISQPV_TYPE_IMMEDIATE: /* register type is translated to this one too */
2748	val64 = param2.val.val64;
2749	break;
2750
2751	default:
2752	Log(("emInterpretMov: unexpected type=%d rip=%RGv\n", param2.type, (RTGCPTR)pRegFrame->rip));
2753	return VERR_EM_INTERPRETER;
2754	}
2755	#ifdef LOG_ENABLED
2756	if (pDis->uCpuMode == DISCPUMODE_64BIT)
2757	LogFlow(("EMInterpretInstruction at %RGv: OP_MOV %RGv <- %RX64 (%d) &val64=%RHv\n", (RTGCPTR)pRegFrame->rip, pDest, val64, param2.size, &val64));
2758	else
2759	LogFlow(("EMInterpretInstruction at %08RX64: OP_MOV %RGv <- %08X (%d) &val64=%RHv\n", pRegFrame->rip, pDest, (uint32_t)val64, param2.size, &val64));
2760	#endif
2761
2762	Assert(param2.size <= 8 && param2.size > 0);
2763	EM_ASSERT_FAULT_RETURN(pDest == pvFault, VERR_EM_INTERPRETER);
2764	rc = emRamWrite(pVM, pVCpu, pRegFrame, pDest, &val64, param2.size);
2765	if (RT_FAILURE(rc))
2766	return VERR_EM_INTERPRETER;
2767
2768	*pcbSize = param2.size;
2769	}
2770	#if defined(IN_RC) && defined(VBOX_WITH_RAW_RING1)
2771	/* mov xx, cs instruction is dangerous in raw mode and replaced by an 'int3' by csam/patm. */
2772	else if ( param1.type == DISQPV_TYPE_REGISTER
2773	&& param2.type == DISQPV_TYPE_REGISTER)
2774	{
2775	AssertReturn((pDis->Param1.fUse & (DISUSE_REG_GEN8\|DISUSE_REG_GEN16\|DISUSE_REG_GEN32)), VERR_EM_INTERPRETER);
2776	AssertReturn(pDis->Param2.fUse == DISUSE_REG_SEG, VERR_EM_INTERPRETER);
2777	AssertReturn(pDis->Param2.Base.idxSegReg == DISSELREG_CS, VERR_EM_INTERPRETER);
2778
2779	uint32_t u32Cpl = CPUMRCGetGuestCPL(pVCpu, pRegFrame);
2780	uint32_t uValCS = (pRegFrame->cs.Sel & ~X86_SEL_RPL) \| u32Cpl;
2781
2782	Log(("EMInterpretInstruction: OP_MOV cs=%x->%x\n", pRegFrame->cs.Sel, uValCS));
2783	switch (param1.size)
2784	{
2785	case 1: rc = DISWriteReg8(pRegFrame, pDis->Param1.Base.idxGenReg, (uint8_t) uValCS); break;
2786	case 2: rc = DISWriteReg16(pRegFrame, pDis->Param1.Base.idxGenReg, (uint16_t)uValCS); break;
2787	case 4: rc = DISWriteReg32(pRegFrame, pDis->Param1.Base.idxGenReg, (uint32_t)uValCS); break;
2788	default:
2789	AssertFailed();
2790	return VERR_EM_INTERPRETER;
2791	}
2792	AssertRCReturn(rc, rc);
2793	}
2794	#endif
2795	else
2796	{ /* read fault */
2797	RTGCPTR pSrc;
2798	uint64_t val64;
2799
2800	/* Source */
2801	switch(param2.type)
2802	{
2803	case DISQPV_TYPE_IMMEDIATE:
2804	if(!(param2.flags & (DISQPV_FLAG_32\|DISQPV_FLAG_64)))
2805	return VERR_EM_INTERPRETER;
2806	/* fallthru */
2807
2808	case DISQPV_TYPE_ADDRESS:
2809	pSrc = (RTGCPTR)param2.val.val64;
2810	pSrc = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param2, pSrc);
2811	break;
2812
2813	default:
2814	return VERR_EM_INTERPRETER;
2815	}
2816
2817	Assert(param1.size <= 8 && param1.size > 0);
2818	EM_ASSERT_FAULT_RETURN(pSrc == pvFault, VERR_EM_INTERPRETER);
2819	rc = emRamRead(pVM, pVCpu, pRegFrame, &val64, pSrc, param1.size);
2820	if (RT_FAILURE(rc))
2821	return VERR_EM_INTERPRETER;
2822
2823	/* Destination */
2824	switch(param1.type)
2825	{
2826	case DISQPV_TYPE_REGISTER:
2827	switch(param1.size)
2828	{
2829	case 1: rc = DISWriteReg8(pRegFrame, pDis->Param1.Base.idxGenReg, (uint8_t) val64); break;
2830	case 2: rc = DISWriteReg16(pRegFrame, pDis->Param1.Base.idxGenReg, (uint16_t)val64); break;
2831	case 4: rc = DISWriteReg32(pRegFrame, pDis->Param1.Base.idxGenReg, (uint32_t)val64); break;
2832	case 8: rc = DISWriteReg64(pRegFrame, pDis->Param1.Base.idxGenReg, val64); break;
2833	default:
2834	return VERR_EM_INTERPRETER;
2835	}
2836	if (RT_FAILURE(rc))
2837	return rc;
2838	break;
2839
2840	default:
2841	return VERR_EM_INTERPRETER;
2842	}
2843	#ifdef LOG_ENABLED
2844	if (pDis->uCpuMode == DISCPUMODE_64BIT)
2845	LogFlow(("EMInterpretInstruction: OP_MOV %RGv -> %RX64 (%d)\n", pSrc, val64, param1.size));
2846	else
2847	LogFlow(("EMInterpretInstruction: OP_MOV %RGv -> %08X (%d)\n", pSrc, (uint32_t)val64, param1.size));
2848	#endif
2849	}
2850	return VINF_SUCCESS;
2851	}
2852
2853
2854	#ifndef IN_RC
2855	/**
2856	* [REP] STOSWD emulation
2857	*/
2858	static int emInterpretStosWD(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2859	{
2860	int rc;
2861	RTGCPTR GCDest, GCOffset;
2862	uint32_t cbSize;
2863	uint64_t cTransfers;
2864	int offIncrement;
2865	NOREF(pvFault);
2866
2867	/* Don't support any but these three prefix bytes. */
2868	if ((pDis->fPrefix & ~(DISPREFIX_ADDRSIZE\|DISPREFIX_OPSIZE\|DISPREFIX_REP\|DISPREFIX_REX)))
2869	return VERR_EM_INTERPRETER;
2870
2871	switch (pDis->uAddrMode)
2872	{
2873	case DISCPUMODE_16BIT:
2874	GCOffset = pRegFrame->di;
2875	cTransfers = pRegFrame->cx;
2876	break;
2877	case DISCPUMODE_32BIT:
2878	GCOffset = pRegFrame->edi;
2879	cTransfers = pRegFrame->ecx;
2880	break;
2881	case DISCPUMODE_64BIT:
2882	GCOffset = pRegFrame->rdi;
2883	cTransfers = pRegFrame->rcx;
2884	break;
2885	default:
2886	AssertFailed();
2887	return VERR_EM_INTERPRETER;
2888	}
2889
2890	GCDest = SELMToFlat(pVM, DISSELREG_ES, pRegFrame, GCOffset);
2891	switch (pDis->uOpMode)
2892	{
2893	case DISCPUMODE_16BIT:
2894	cbSize = 2;
2895	break;
2896	case DISCPUMODE_32BIT:
2897	cbSize = 4;
2898	break;
2899	case DISCPUMODE_64BIT:
2900	cbSize = 8;
2901	break;
2902	default:
2903	AssertFailed();
2904	return VERR_EM_INTERPRETER;
2905	}
2906
2907	offIncrement = pRegFrame->eflags.Bits.u1DF ? -(signed)cbSize : (signed)cbSize;
2908
2909	if (!(pDis->fPrefix & DISPREFIX_REP))
2910	{
2911	LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d\n", pRegFrame->es.Sel, GCOffset, GCDest, cbSize));
2912
2913	rc = emRamWrite(pVM, pVCpu, pRegFrame, GCDest, &pRegFrame->rax, cbSize);
2914	if (RT_FAILURE(rc))
2915	return VERR_EM_INTERPRETER;
2916	Assert(rc == VINF_SUCCESS);
2917
2918	/* Update (e/r)di. */
2919	switch (pDis->uAddrMode)
2920	{
2921	case DISCPUMODE_16BIT:
2922	pRegFrame->di += offIncrement;
2923	break;
2924	case DISCPUMODE_32BIT:
2925	pRegFrame->edi += offIncrement;
2926	break;
2927	case DISCPUMODE_64BIT:
2928	pRegFrame->rdi += offIncrement;
2929	break;
2930	default:
2931	AssertFailed();
2932	return VERR_EM_INTERPRETER;
2933	}
2934
2935	}
2936	else
2937	{
2938	if (!cTransfers)
2939	return VINF_SUCCESS;
2940
2941	/*
2942	* Do not try emulate cross page stuff here because we don't know what might
2943	* be waiting for us on the subsequent pages. The caller has only asked us to
2944	* ignore access handlers fro the current page.
2945	* This also fends off big stores which would quickly kill PGMR0DynMap.
2946	*/
2947	if ( cbSize > PAGE_SIZE
2948	\|\| cTransfers > PAGE_SIZE
2949	\|\| (GCDest >> PAGE_SHIFT) != ((GCDest + offIncrement * cTransfers) >> PAGE_SHIFT))
2950	{
2951	Log(("STOSWD is crosses pages, chicken out to the recompiler; GCDest=%RGv cbSize=%#x offIncrement=%d cTransfers=%#x\n",
2952	GCDest, cbSize, offIncrement, cTransfers));
2953	return VERR_EM_INTERPRETER;
2954	}
2955
2956	LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d cTransfers=%x DF=%d\n", pRegFrame->es.Sel, GCOffset, GCDest, cbSize, cTransfers, pRegFrame->eflags.Bits.u1DF));
2957	/* Access verification first; we currently can't recover properly from traps inside this instruction */
2958	rc = PGMVerifyAccess(pVCpu, GCDest - ((offIncrement > 0) ? 0 : ((cTransfers-1) * cbSize)),
2959	cTransfers * cbSize,
2960	X86_PTE_RW \| (CPUMGetGuestCPL(pVCpu) == 3 ? X86_PTE_US : 0));
2961	if (rc != VINF_SUCCESS)
2962	{
2963	Log(("STOSWD will generate a trap -> recompiler, rc=%d\n", rc));
2964	return VERR_EM_INTERPRETER;
2965	}
2966
2967	/* REP case */
2968	while (cTransfers)
2969	{
2970	rc = emRamWrite(pVM, pVCpu, pRegFrame, GCDest, &pRegFrame->rax, cbSize);
2971	if (RT_FAILURE(rc))
2972	{
2973	rc = VERR_EM_INTERPRETER;
2974	break;
2975	}
2976
2977	Assert(rc == VINF_SUCCESS);
2978	GCOffset += offIncrement;
2979	GCDest += offIncrement;
2980	cTransfers--;
2981	}
2982
2983	/* Update the registers. */
2984	switch (pDis->uAddrMode)
2985	{
2986	case DISCPUMODE_16BIT:
2987	pRegFrame->di = GCOffset;
2988	pRegFrame->cx = cTransfers;
2989	break;
2990	case DISCPUMODE_32BIT:
2991	pRegFrame->edi = GCOffset;
2992	pRegFrame->ecx = cTransfers;
2993	break;
2994	case DISCPUMODE_64BIT:
2995	pRegFrame->rdi = GCOffset;
2996	pRegFrame->rcx = cTransfers;
2997	break;
2998	default:
2999	AssertFailed();
3000	return VERR_EM_INTERPRETER;
3001	}
3002	}
3003
3004	*pcbSize = cbSize;
3005	return rc;
3006	}
3007	#endif /* !IN_RC */
3008
3009
3010	/**
3011	* [LOCK] CMPXCHG emulation.
3012	*/
3013	static int emInterpretCmpXchg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3014	{
3015	DISQPVPARAMVAL param1, param2;
3016	NOREF(pvFault);
3017
3018	#if HC_ARCH_BITS == 32
3019	Assert(pDis->Param1.cb <= 4);
3020	#endif
3021
3022	/* Source to make DISQueryParamVal read the register value - ugly hack */
3023	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3024	if(RT_FAILURE(rc))
3025	return VERR_EM_INTERPRETER;
3026
3027	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
3028	if(RT_FAILURE(rc))
3029	return VERR_EM_INTERPRETER;
3030
3031	uint64_t valpar;
3032	switch(param2.type)
3033	{
3034	case DISQPV_TYPE_IMMEDIATE: /* register actually */
3035	valpar = param2.val.val64;
3036	break;
3037
3038	default:
3039	return VERR_EM_INTERPRETER;
3040	}
3041
3042	PGMPAGEMAPLOCK Lock;
3043	RTGCPTR GCPtrPar1;
3044	void *pvParam1;
3045	uint64_t eflags;
3046
3047	AssertReturn(pDis->Param1.cb == pDis->Param2.cb, VERR_EM_INTERPRETER);
3048	switch(param1.type)
3049	{
3050	case DISQPV_TYPE_ADDRESS:
3051	GCPtrPar1 = param1.val.val64;
3052	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, GCPtrPar1);
3053
3054	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
3055	AssertRCReturn(rc, VERR_EM_INTERPRETER);
3056	break;
3057
3058	default:
3059	return VERR_EM_INTERPRETER;
3060	}
3061
3062	LogFlow(("%s %RGv rax=%RX64 %RX64\n", emGetMnemonic(pDis), GCPtrPar1, pRegFrame->rax, valpar));
3063
3064	#ifndef VBOX_COMPARE_IEM_AND_EM
3065	if (pDis->fPrefix & DISPREFIX_LOCK)
3066	eflags = EMEmulateLockCmpXchg(pvParam1, &pRegFrame->rax, valpar, pDis->Param2.cb);
3067	else
3068	eflags = EMEmulateCmpXchg(pvParam1, &pRegFrame->rax, valpar, pDis->Param2.cb);
3069	#else /* VBOX_COMPARE_IEM_AND_EM */
3070	uint64_t u64;
3071	switch (pDis->Param2.cb)
3072	{
3073	case 1: u64 = (uint8_t )pvParam1; break;
3074	case 2: u64 = (uint16_t )pvParam1; break;
3075	case 4: u64 = (uint32_t )pvParam1; break;
3076	default:
3077	case 8: u64 = (uint64_t )pvParam1; break;
3078	}
3079	eflags = EMEmulateCmpXchg(&u64, &pRegFrame->rax, valpar, pDis->Param2.cb);
3080	int rc2 = emRamWrite(pVM, pVCpu, pRegFrame, GCPtrPar1, &u64, pDis->Param2.cb); AssertRCSuccess(rc2);
3081	#endif /* VBOX_COMPARE_IEM_AND_EM */
3082
3083	LogFlow(("%s %RGv rax=%RX64 %RX64 ZF=%d\n", emGetMnemonic(pDis), GCPtrPar1, pRegFrame->rax, valpar, !!(eflags & X86_EFL_ZF)));
3084
3085	/* Update guest's eflags and finish. */
3086	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
3087	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
3088
3089	*pcbSize = param2.size;
3090	PGMPhysReleasePageMappingLock(pVM, &Lock);
3091	return VINF_SUCCESS;
3092	}
3093
3094
3095	/**
3096	* [LOCK] CMPXCHG8B emulation.
3097	*/
3098	static int emInterpretCmpXchg8b(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3099	{
3100	DISQPVPARAMVAL param1;
3101	NOREF(pvFault);
3102
3103	/* Source to make DISQueryParamVal read the register value - ugly hack */
3104	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3105	if(RT_FAILURE(rc))
3106	return VERR_EM_INTERPRETER;
3107
3108	RTGCPTR GCPtrPar1;
3109	void *pvParam1;
3110	uint64_t eflags;
3111	PGMPAGEMAPLOCK Lock;
3112
3113	AssertReturn(pDis->Param1.cb == 8, VERR_EM_INTERPRETER);
3114	switch(param1.type)
3115	{
3116	case DISQPV_TYPE_ADDRESS:
3117	GCPtrPar1 = param1.val.val64;
3118	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, GCPtrPar1);
3119
3120	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
3121	AssertRCReturn(rc, VERR_EM_INTERPRETER);
3122	break;
3123
3124	default:
3125	return VERR_EM_INTERPRETER;
3126	}
3127
3128	LogFlow(("%s %RGv=%p eax=%08x\n", emGetMnemonic(pDis), GCPtrPar1, pvParam1, pRegFrame->eax));
3129
3130	#ifndef VBOX_COMPARE_IEM_AND_EM
3131	if (pDis->fPrefix & DISPREFIX_LOCK)
3132	eflags = EMEmulateLockCmpXchg8b(pvParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
3133	else
3134	eflags = EMEmulateCmpXchg8b(pvParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
3135	#else /* VBOX_COMPARE_IEM_AND_EM */
3136	uint64_t u64 = (uint64_t )pvParam1;
3137	eflags = EMEmulateCmpXchg8b(&u64, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
3138	int rc2 = emRamWrite(pVM, pVCpu, pRegFrame, GCPtrPar1, &u64, sizeof(u64)); AssertRCSuccess(rc2);
3139	#endif /* VBOX_COMPARE_IEM_AND_EM */
3140
3141	LogFlow(("%s %RGv=%p eax=%08x ZF=%d\n", emGetMnemonic(pDis), GCPtrPar1, pvParam1, pRegFrame->eax, !!(eflags & X86_EFL_ZF)));
3142
3143	/* Update guest's eflags and finish; note that only ZF is affected. */
3144	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_ZF))
3145	\| (eflags & (X86_EFL_ZF));
3146
3147	*pcbSize = 8;
3148	PGMPhysReleasePageMappingLock(pVM, &Lock);
3149	return VINF_SUCCESS;
3150	}
3151
3152
3153	#ifdef IN_RC /** @todo test+enable for HM as well. */
3154	/**
3155	* [LOCK] XADD emulation.
3156	*/
3157	static int emInterpretXAdd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3158	{
3159	Assert(pDis->uCpuMode != DISCPUMODE_64BIT); /** @todo check */
3160	DISQPVPARAMVAL param1;
3161	void *pvParamReg2;
3162	size_t cbParamReg2;
3163	NOREF(pvFault);
3164
3165	/* Source to make DISQueryParamVal read the register value - ugly hack */
3166	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3167	if(RT_FAILURE(rc))
3168	return VERR_EM_INTERPRETER;
3169
3170	rc = DISQueryParamRegPtr(pRegFrame, pDis, &pDis->Param2, &pvParamReg2, &cbParamReg2);
3171	Assert(cbParamReg2 <= 4);
3172	if(RT_FAILURE(rc))
3173	return VERR_EM_INTERPRETER;
3174
3175	#ifdef IN_RC
3176	if (TRPMHasTrap(pVCpu))
3177	{
3178	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
3179	{
3180	#endif
3181	RTGCPTR GCPtrPar1;
3182	void *pvParam1;
3183	uint32_t eflags;
3184	PGMPAGEMAPLOCK Lock;
3185
3186	AssertReturn(pDis->Param1.cb == pDis->Param2.cb, VERR_EM_INTERPRETER);
3187	switch(param1.type)
3188	{
3189	case DISQPV_TYPE_ADDRESS:
3190	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, (RTRCUINTPTR)param1.val.val64);
3191	#ifdef IN_RC
3192	EM_ASSERT_FAULT_RETURN(GCPtrPar1 == pvFault, VERR_EM_INTERPRETER);
3193	#endif
3194
3195	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
3196	AssertRCReturn(rc, VERR_EM_INTERPRETER);
3197	break;
3198
3199	default:
3200	return VERR_EM_INTERPRETER;
3201	}
3202
3203	LogFlow(("XAdd %RGv=%p reg=%08llx\n", GCPtrPar1, pvParam1, (uint64_t )pvParamReg2));
3204
3205	#ifndef VBOX_COMPARE_IEM_AND_EM
3206	if (pDis->fPrefix & DISPREFIX_LOCK)
3207	eflags = EMEmulateLockXAdd(pvParam1, pvParamReg2, cbParamReg2);
3208	else
3209	eflags = EMEmulateXAdd(pvParam1, pvParamReg2, cbParamReg2);
3210	#else /* VBOX_COMPARE_IEM_AND_EM */
3211	uint64_t u64;
3212	switch (cbParamReg2)
3213	{
3214	case 1: u64 = (uint8_t )pvParam1; break;
3215	case 2: u64 = (uint16_t )pvParam1; break;
3216	case 4: u64 = (uint32_t )pvParam1; break;
3217	default:
3218	case 8: u64 = (uint64_t )pvParam1; break;
3219	}
3220	eflags = EMEmulateXAdd(&u64, pvParamReg2, cbParamReg2);
3221	int rc2 = emRamWrite(pVM, pVCpu, pRegFrame, GCPtrPar1, &u64, pDis->Param2.cb); AssertRCSuccess(rc2);
3222	#endif /* VBOX_COMPARE_IEM_AND_EM */
3223
3224	LogFlow(("XAdd %RGv=%p reg=%08llx ZF=%d\n", GCPtrPar1, pvParam1, (uint64_t )pvParamReg2, !!(eflags & X86_EFL_ZF) ));
3225
3226	/* Update guest's eflags and finish. */
3227	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
3228	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
3229
3230	*pcbSize = cbParamReg2;
3231	PGMPhysReleasePageMappingLock(pVM, &Lock);
3232	return VINF_SUCCESS;
3233	#ifdef IN_RC
3234	}
3235	}
3236
3237	return VERR_EM_INTERPRETER;
3238	#endif
3239	}
3240	#endif /* IN_RC */
3241
3242
3243	/**
3244	* WBINVD Emulation.
3245	*/
3246	static int emInterpretWbInvd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3247	{
3248	/* Nothing to do. */
3249	NOREF(pVM); NOREF(pVCpu); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
3250	return VINF_SUCCESS;
3251	}
3252
3253
3254	/**
3255	* INVLPG Emulation.
3256	*/
3257	static VBOXSTRICTRC emInterpretInvlPg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3258	{
3259	DISQPVPARAMVAL param1;
3260	RTGCPTR addr;
3261	NOREF(pvFault); NOREF(pVM); NOREF(pcbSize);
3262
3263	VBOXSTRICTRC rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3264	if(RT_FAILURE(rc))
3265	return VERR_EM_INTERPRETER;
3266
3267	switch(param1.type)
3268	{
3269	case DISQPV_TYPE_IMMEDIATE:
3270	case DISQPV_TYPE_ADDRESS:
3271	if(!(param1.flags & (DISQPV_FLAG_32\|DISQPV_FLAG_64)))
3272	return VERR_EM_INTERPRETER;
3273	addr = (RTGCPTR)param1.val.val64;
3274	break;
3275
3276	default:
3277	return VERR_EM_INTERPRETER;
3278	}
3279
3280	/** @todo is addr always a flat linear address or ds based
3281	* (in absence of segment override prefixes)????
3282	*/
3283	#ifdef IN_RC
3284	LogFlow(("RC: EMULATE: invlpg %RGv\n", addr));
3285	#endif
3286	rc = PGMInvalidatePage(pVCpu, addr);
3287	if ( rc == VINF_SUCCESS
3288	\|\| rc == VINF_PGM_SYNC_CR3 /* we can rely on the FF */)
3289	return VINF_SUCCESS;
3290	AssertMsgReturn(rc == VINF_EM_RAW_EMULATE_INSTR,
3291	("%Rrc addr=%RGv\n", VBOXSTRICTRC_VAL(rc), addr),
3292	VERR_EM_INTERPRETER);
3293	return rc;
3294	}
3295
3296	/** @todo change all these EMInterpretXXX methods to VBOXSTRICTRC. */
3297
3298	/**
3299	* CPUID Emulation.
3300	*/
3301	static int emInterpretCpuId(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3302	{
3303	NOREF(pVM); NOREF(pVCpu); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
3304	int rc = EMInterpretCpuId(pVM, pVCpu, pRegFrame);
3305	return rc;
3306	}
3307
3308
3309	/**
3310	* CLTS Emulation.
3311	*/
3312	static int emInterpretClts(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3313	{
3314	NOREF(pVM); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
3315
3316	uint64_t cr0 = CPUMGetGuestCR0(pVCpu);
3317	if (!(cr0 & X86_CR0_TS))
3318	return VINF_SUCCESS;
3319	return CPUMSetGuestCR0(pVCpu, cr0 & ~X86_CR0_TS);
3320	}
3321
3322
3323	/**
3324	* LMSW Emulation.
3325	*/
3326	static int emInterpretLmsw(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3327	{
3328	DISQPVPARAMVAL param1;
3329	uint32_t val;
3330	NOREF(pvFault); NOREF(pcbSize);
3331	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
3332
3333	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3334	if(RT_FAILURE(rc))
3335	return VERR_EM_INTERPRETER;
3336
3337	switch(param1.type)
3338	{
3339	case DISQPV_TYPE_IMMEDIATE:
3340	case DISQPV_TYPE_ADDRESS:
3341	if(!(param1.flags & DISQPV_FLAG_16))
3342	return VERR_EM_INTERPRETER;
3343	val = param1.val.val32;
3344	break;
3345
3346	default:
3347	return VERR_EM_INTERPRETER;
3348	}
3349
3350	LogFlow(("emInterpretLmsw %x\n", val));
3351	uint64_t OldCr0 = CPUMGetGuestCR0(pVCpu);
3352
3353	/* Only PE, MP, EM and TS can be changed; note that PE can't be cleared by this instruction. */
3354	uint64_t NewCr0 = ( OldCr0 & ~( X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
3355	\| (val & (X86_CR0_PE \| X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS));
3356
3357	return emUpdateCRx(pVM, pVCpu, pRegFrame, DISCREG_CR0, NewCr0);
3358
3359	}
3360
3361	#ifdef EM_EMULATE_SMSW
3362	/**
3363	* SMSW Emulation.
3364	*/
3365	static int emInterpretSmsw(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3366	{
3367	NOREF(pvFault); NOREF(pcbSize);
3368	DISQPVPARAMVAL param1;
3369	uint64_t cr0 = CPUMGetGuestCR0(pVCpu);
3370
3371	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3372	if(RT_FAILURE(rc))
3373	return VERR_EM_INTERPRETER;
3374
3375	switch(param1.type)
3376	{
3377	case DISQPV_TYPE_IMMEDIATE:
3378	if(param1.size != sizeof(uint16_t))
3379	return VERR_EM_INTERPRETER;
3380	LogFlow(("emInterpretSmsw %d <- cr0 (%x)\n", pDis->Param1.Base.idxGenReg, cr0));
3381	rc = DISWriteReg16(pRegFrame, pDis->Param1.Base.idxGenReg, cr0);
3382	break;
3383
3384	case DISQPV_TYPE_ADDRESS:
3385	{
3386	RTGCPTR pParam1;
3387
3388	/* Actually forced to 16 bits regardless of the operand size. */
3389	if(param1.size != sizeof(uint16_t))
3390	return VERR_EM_INTERPRETER;
3391
3392	pParam1 = (RTGCPTR)param1.val.val64;
3393	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
3394	LogFlow(("emInterpretSmsw %RGv <- cr0 (%x)\n", pParam1, cr0));
3395
3396	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &cr0, sizeof(uint16_t));
3397	if (RT_FAILURE(rc))
3398	{
3399	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
3400	return VERR_EM_INTERPRETER;
3401	}
3402	break;
3403	}
3404
3405	default:
3406	return VERR_EM_INTERPRETER;
3407	}
3408
3409	LogFlow(("emInterpretSmsw %x\n", cr0));
3410	return rc;
3411	}
3412	#endif
3413
3414	/**
3415	* MOV CRx
3416	*/
3417	static int emInterpretMovCRx(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3418	{
3419	NOREF(pvFault); NOREF(pcbSize);
3420	if ((pDis->Param1.fUse == DISUSE_REG_GEN32 \|\| pDis->Param1.fUse == DISUSE_REG_GEN64) && pDis->Param2.fUse == DISUSE_REG_CR)
3421	return emInterpretCRxRead(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxGenReg, pDis->Param2.Base.idxCtrlReg);
3422
3423	if (pDis->Param1.fUse == DISUSE_REG_CR && (pDis->Param2.fUse == DISUSE_REG_GEN32 \|\| pDis->Param2.fUse == DISUSE_REG_GEN64))
3424	return emInterpretCRxWrite(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxCtrlReg, pDis->Param2.Base.idxGenReg);
3425
3426	AssertMsgFailedReturn(("Unexpected control register move\n"), VERR_EM_INTERPRETER);
3427	}
3428
3429
3430	/**
3431	* MOV DRx
3432	*/
3433	static int emInterpretMovDRx(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3434	{
3435	int rc = VERR_EM_INTERPRETER;
3436	NOREF(pvFault); NOREF(pcbSize);
3437
3438	if((pDis->Param1.fUse == DISUSE_REG_GEN32 \|\| pDis->Param1.fUse == DISUSE_REG_GEN64) && pDis->Param2.fUse == DISUSE_REG_DBG)
3439	{
3440	rc = EMInterpretDRxRead(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxGenReg, pDis->Param2.Base.idxDbgReg);
3441	}
3442	else
3443	if(pDis->Param1.fUse == DISUSE_REG_DBG && (pDis->Param2.fUse == DISUSE_REG_GEN32 \|\| pDis->Param2.fUse == DISUSE_REG_GEN64))
3444	{
3445	rc = EMInterpretDRxWrite(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxDbgReg, pDis->Param2.Base.idxGenReg);
3446	}
3447	else
3448	AssertMsgFailed(("Unexpected debug register move\n"));
3449
3450	return rc;
3451	}
3452
3453
3454	/**
3455	* LLDT Emulation.
3456	*/
3457	static int emInterpretLLdt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3458	{
3459	DISQPVPARAMVAL param1;
3460	RTSEL sel;
3461	NOREF(pVM); NOREF(pvFault); NOREF(pcbSize);
3462
3463	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3464	if(RT_FAILURE(rc))
3465	return VERR_EM_INTERPRETER;
3466
3467	switch(param1.type)
3468	{
3469	case DISQPV_TYPE_ADDRESS:
3470	return VERR_EM_INTERPRETER; //feeling lazy right now
3471
3472	case DISQPV_TYPE_IMMEDIATE:
3473	if(!(param1.flags & DISQPV_FLAG_16))
3474	return VERR_EM_INTERPRETER;
3475	sel = (RTSEL)param1.val.val16;
3476	break;
3477
3478	default:
3479	return VERR_EM_INTERPRETER;
3480	}
3481
3482	#ifdef IN_RING0
3483	/* Only for the VT-x real-mode emulation case. */
3484	AssertReturn(CPUMIsGuestInRealMode(pVCpu), VERR_EM_INTERPRETER);
3485	CPUMSetGuestLDTR(pVCpu, sel);
3486	return VINF_SUCCESS;
3487	#else
3488	if (sel == 0)
3489	{
3490	if (CPUMGetHyperLDTR(pVCpu) == 0)
3491	{
3492	// this simple case is most frequent in Windows 2000 (31k - boot & shutdown)
3493	return VINF_SUCCESS;
3494	}
3495	}
3496	//still feeling lazy
3497	return VERR_EM_INTERPRETER;
3498	#endif
3499	}
3500
3501	#ifdef IN_RING0
3502	/**
3503	* LIDT/LGDT Emulation.
3504	*/
3505	static int emInterpretLIGdt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3506	{
3507	DISQPVPARAMVAL param1;
3508	RTGCPTR pParam1;
3509	X86XDTR32 dtr32;
3510	NOREF(pvFault); NOREF(pcbSize);
3511
3512	Log(("Emulate %s at %RGv\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip));
3513
3514	/* Only for the VT-x real-mode emulation case. */
3515	AssertReturn(CPUMIsGuestInRealMode(pVCpu), VERR_EM_INTERPRETER);
3516
3517	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3518	if(RT_FAILURE(rc))
3519	return VERR_EM_INTERPRETER;
3520
3521	switch(param1.type)
3522	{
3523	case DISQPV_TYPE_ADDRESS:
3524	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, param1.val.val16);
3525	break;
3526
3527	default:
3528	return VERR_EM_INTERPRETER;
3529	}
3530
3531	rc = emRamRead(pVM, pVCpu, pRegFrame, &dtr32, pParam1, sizeof(dtr32));
3532	AssertRCReturn(rc, VERR_EM_INTERPRETER);
3533
3534	if (!(pDis->fPrefix & DISPREFIX_OPSIZE))
3535	dtr32.uAddr &= 0xffffff; /* 16 bits operand size */
3536
3537	if (pDis->pCurInstr->uOpcode == OP_LIDT)
3538	CPUMSetGuestIDTR(pVCpu, dtr32.uAddr, dtr32.cb);
3539	else
3540	CPUMSetGuestGDTR(pVCpu, dtr32.uAddr, dtr32.cb);
3541
3542	return VINF_SUCCESS;
3543	}
3544	#endif
3545
3546
3547	#ifdef IN_RC
3548	/**
3549	* STI Emulation.
3550	*
3551	* @remark the instruction following sti is guaranteed to be executed before any interrupts are dispatched
3552	*/
3553	static int emInterpretSti(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3554	{
3555	NOREF(pcbSize);
3556	PPATMGCSTATE pGCState = PATMGetGCState(pVM);
3557
3558	if(!pGCState)
3559	{
3560	Assert(pGCState);
3561	return VERR_EM_INTERPRETER;
3562	}
3563	pGCState->uVMFlags \|= X86_EFL_IF;
3564
3565	Assert(pRegFrame->eflags.u32 & X86_EFL_IF);
3566	Assert(pvFault == SELMToFlat(pVM, DISSELREG_CS, pRegFrame, (RTGCPTR)pRegFrame->rip));
3567
3568	pVCpu->em.s.GCPtrInhibitInterrupts = pRegFrame->eip + pDis->cbInstr;
3569	VMCPU_FF_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
3570
3571	return VINF_SUCCESS;
3572	}
3573	#endif /* IN_RC */
3574
3575
3576	/**
3577	* HLT Emulation.
3578	*/
3579	static VBOXSTRICTRC
3580	emInterpretHlt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3581	{
3582	NOREF(pVM); NOREF(pVCpu); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
3583	return VINF_EM_HALT;
3584	}
3585
3586
3587	/**
3588	* RDTSC Emulation.
3589	*/
3590	static int emInterpretRdtsc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3591	{
3592	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3593	return EMInterpretRdtsc(pVM, pVCpu, pRegFrame);
3594	}
3595
3596	/**
3597	* RDPMC Emulation
3598	*/
3599	static int emInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3600	{
3601	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3602	return EMInterpretRdpmc(pVM, pVCpu, pRegFrame);
3603	}
3604
3605
3606	static int emInterpretMonitor(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3607	{
3608	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3609	return EMInterpretMonitor(pVM, pVCpu, pRegFrame);
3610	}
3611
3612
3613	static VBOXSTRICTRC emInterpretMWait(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3614	{
3615	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3616	return EMInterpretMWait(pVM, pVCpu, pRegFrame);
3617	}
3618
3619
3620	/**
3621	* RDMSR Emulation.
3622	*/
3623	static int emInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3624	{
3625	/* Note: The Intel manual claims there's a REX version of RDMSR that's slightly
3626	different, so we play safe by completely disassembling the instruction. */
3627	Assert(!(pDis->fPrefix & DISPREFIX_REX));
3628	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3629	return EMInterpretRdmsr(pVM, pVCpu, pRegFrame);
3630	}
3631
3632
3633	/**
3634	* WRMSR Emulation.
3635	*/
3636	static int emInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3637	{
3638	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3639	return EMInterpretWrmsr(pVM, pVCpu, pRegFrame);
3640	}
3641
3642
3643	/**
3644	* Internal worker.
3645	* @copydoc emInterpretInstructionCPUOuter
3646	*/
3647	DECLINLINE(VBOXSTRICTRC) emInterpretInstructionCPU(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
3648	RTGCPTR pvFault, EMCODETYPE enmCodeType, uint32_t *pcbSize)
3649	{
3650	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
3651	Assert(enmCodeType == EMCODETYPE_SUPERVISOR \|\| enmCodeType == EMCODETYPE_ALL);
3652	Assert(pcbSize);
3653	*pcbSize = 0;
3654
3655	if (enmCodeType == EMCODETYPE_SUPERVISOR)
3656	{
3657	/*
3658	* Only supervisor guest code!!
3659	* And no complicated prefixes.
3660	*/
3661	/* Get the current privilege level. */
3662	uint32_t cpl = CPUMGetGuestCPL(pVCpu);
3663	#ifdef VBOX_WITH_RAW_RING1
3664	if ( !EMIsRawRing1Enabled(pVM)
3665	\|\| cpl > 1
3666	\|\| pRegFrame->eflags.Bits.u2IOPL > cpl
3667	)
3668	#endif
3669	{
3670	if ( cpl != 0
3671	&& pDis->pCurInstr->uOpcode != OP_RDTSC) /* rdtsc requires emulation in ring 3 as well */
3672	{
3673	Log(("WARNING: refusing instruction emulation for user-mode code!!\n"));
3674	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedUserMode));
3675	return VERR_EM_INTERPRETER;
3676	}
3677	}
3678	}
3679	else
3680	Log2(("emInterpretInstructionCPU allowed to interpret user-level code!!\n"));
3681
3682	#ifdef IN_RC
3683	if ( (pDis->fPrefix & (DISPREFIX_REPNE \| DISPREFIX_REP))
3684	\|\| ( (pDis->fPrefix & DISPREFIX_LOCK)
3685	&& pDis->pCurInstr->uOpcode != OP_CMPXCHG
3686	&& pDis->pCurInstr->uOpcode != OP_CMPXCHG8B
3687	&& pDis->pCurInstr->uOpcode != OP_XADD
3688	&& pDis->pCurInstr->uOpcode != OP_OR
3689	&& pDis->pCurInstr->uOpcode != OP_AND
3690	&& pDis->pCurInstr->uOpcode != OP_XOR
3691	&& pDis->pCurInstr->uOpcode != OP_BTR
3692	)
3693	)
3694	#else
3695	if ( (pDis->fPrefix & DISPREFIX_REPNE)
3696	\|\| ( (pDis->fPrefix & DISPREFIX_REP)
3697	&& pDis->pCurInstr->uOpcode != OP_STOSWD
3698	)
3699	\|\| ( (pDis->fPrefix & DISPREFIX_LOCK)
3700	&& pDis->pCurInstr->uOpcode != OP_OR
3701	&& pDis->pCurInstr->uOpcode != OP_AND
3702	&& pDis->pCurInstr->uOpcode != OP_XOR
3703	&& pDis->pCurInstr->uOpcode != OP_BTR
3704	&& pDis->pCurInstr->uOpcode != OP_CMPXCHG
3705	&& pDis->pCurInstr->uOpcode != OP_CMPXCHG8B
3706	)
3707	)
3708	#endif
3709	{
3710	//Log(("EMInterpretInstruction: wrong prefix!!\n"));
3711	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedPrefix));
3712	Log4(("EM: Refuse %u on REP/REPNE/LOCK prefix grounds\n", pDis->pCurInstr->uOpcode));
3713	return VERR_EM_INTERPRETER;
3714	}
3715
3716	#if HC_ARCH_BITS == 32
3717	/*
3718	* Unable to emulate most >4 bytes accesses in 32 bits mode.
3719	* Whitelisted instructions are safe.
3720	*/
3721	if ( pDis->Param1.cb > 4
3722	&& CPUMIsGuestIn64BitCode(pVCpu))
3723	{
3724	uint32_t uOpCode = pDis->pCurInstr->uOpcode;
3725	if ( uOpCode != OP_STOSWD
3726	&& uOpCode != OP_MOV
3727	&& uOpCode != OP_CMPXCHG8B
3728	&& uOpCode != OP_XCHG
3729	&& uOpCode != OP_BTS
3730	&& uOpCode != OP_BTR
3731	&& uOpCode != OP_BTC
3732	)
3733	{
3734	# ifdef VBOX_WITH_STATISTICS
3735	switch (pDis->pCurInstr->uOpcode)
3736	{
3737	# define INTERPRET_FAILED_CASE(opcode, Instr) \
3738	case opcode: STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); break;
3739	INTERPRET_FAILED_CASE(OP_XCHG,Xchg);
3740	INTERPRET_FAILED_CASE(OP_DEC,Dec);
3741	INTERPRET_FAILED_CASE(OP_INC,Inc);
3742	INTERPRET_FAILED_CASE(OP_POP,Pop);
3743	INTERPRET_FAILED_CASE(OP_OR, Or);
3744	INTERPRET_FAILED_CASE(OP_XOR,Xor);
3745	INTERPRET_FAILED_CASE(OP_AND,And);
3746	INTERPRET_FAILED_CASE(OP_MOV,Mov);
3747	INTERPRET_FAILED_CASE(OP_STOSWD,StosWD);
3748	INTERPRET_FAILED_CASE(OP_INVLPG,InvlPg);
3749	INTERPRET_FAILED_CASE(OP_CPUID,CpuId);
3750	INTERPRET_FAILED_CASE(OP_MOV_CR,MovCRx);
3751	INTERPRET_FAILED_CASE(OP_MOV_DR,MovDRx);
3752	INTERPRET_FAILED_CASE(OP_LLDT,LLdt);
3753	INTERPRET_FAILED_CASE(OP_LIDT,LIdt);
3754	INTERPRET_FAILED_CASE(OP_LGDT,LGdt);
3755	INTERPRET_FAILED_CASE(OP_LMSW,Lmsw);
3756	INTERPRET_FAILED_CASE(OP_CLTS,Clts);
3757	INTERPRET_FAILED_CASE(OP_MONITOR,Monitor);
3758	INTERPRET_FAILED_CASE(OP_MWAIT,MWait);
3759	INTERPRET_FAILED_CASE(OP_RDMSR,Rdmsr);
3760	INTERPRET_FAILED_CASE(OP_WRMSR,Wrmsr);
3761	INTERPRET_FAILED_CASE(OP_ADD,Add);
3762	INTERPRET_FAILED_CASE(OP_SUB,Sub);
3763	INTERPRET_FAILED_CASE(OP_ADC,Adc);
3764	INTERPRET_FAILED_CASE(OP_BTR,Btr);
3765	INTERPRET_FAILED_CASE(OP_BTS,Bts);
3766	INTERPRET_FAILED_CASE(OP_BTC,Btc);
3767	INTERPRET_FAILED_CASE(OP_RDTSC,Rdtsc);
3768	INTERPRET_FAILED_CASE(OP_CMPXCHG, CmpXchg);
3769	INTERPRET_FAILED_CASE(OP_STI, Sti);
3770	INTERPRET_FAILED_CASE(OP_XADD,XAdd);
3771	INTERPRET_FAILED_CASE(OP_CMPXCHG8B,CmpXchg8b);
3772	INTERPRET_FAILED_CASE(OP_HLT, Hlt);
3773	INTERPRET_FAILED_CASE(OP_IRET,Iret);
3774	INTERPRET_FAILED_CASE(OP_WBINVD,WbInvd);
3775	INTERPRET_FAILED_CASE(OP_MOVNTPS,MovNTPS);
3776	# undef INTERPRET_FAILED_CASE
3777	default:
3778	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedMisc));
3779	break;
3780	}
3781	# endif /* VBOX_WITH_STATISTICS */
3782	Log4(("EM: Refuse %u on grounds of accessing %u bytes\n", pDis->pCurInstr->uOpcode, pDis->Param1.cb));
3783	return VERR_EM_INTERPRETER;
3784	}
3785	}
3786	#endif
3787
3788	VBOXSTRICTRC rc;
3789	#if (defined(VBOX_STRICT) \|\| defined(LOG_ENABLED))
3790	LogFlow(("emInterpretInstructionCPU %s\n", emGetMnemonic(pDis)));
3791	#endif
3792	switch (pDis->pCurInstr->uOpcode)
3793	{
3794	/*
3795	* Macros for generating the right case statements.
3796	*/
3797	# ifndef VBOX_COMPARE_IEM_AND_EM
3798	# define INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
3799	case opcode:\
3800	if (pDis->fPrefix & DISPREFIX_LOCK) \
3801	rc = emInterpretLock##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulateLock); \
3802	else \
3803	rc = emInterpret##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulate); \
3804	if (RT_SUCCESS(rc)) \
3805	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3806	else \
3807	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3808	return rc
3809	# else /* VBOX_COMPARE_IEM_AND_EM */
3810	# define INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
3811	case opcode:\
3812	rc = emInterpret##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulate); \
3813	if (RT_SUCCESS(rc)) \
3814	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3815	else \
3816	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3817	return rc
3818	# endif /* VBOX_COMPARE_IEM_AND_EM */
3819
3820	#define INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate) \
3821	case opcode:\
3822	rc = emInterpret##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulate); \
3823	if (RT_SUCCESS(rc)) \
3824	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3825	else \
3826	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3827	return rc
3828
3829	#define INTERPRET_CASE_EX_PARAM2(opcode, Instr, InstrFn, pfnEmulate) \
3830	INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate)
3831	#define INTERPRET_CASE_EX_LOCK_PARAM2(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
3832	INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock)
3833
3834	#define INTERPRET_CASE(opcode, Instr) \
3835	case opcode:\
3836	rc = emInterpret##Instr(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize); \
3837	if (RT_SUCCESS(rc)) \
3838	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3839	else \
3840	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3841	return rc
3842
3843	#define INTERPRET_CASE_EX_DUAL_PARAM2(opcode, Instr, InstrFn) \
3844	case opcode:\
3845	rc = emInterpret##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize); \
3846	if (RT_SUCCESS(rc)) \
3847	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3848	else \
3849	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3850	return rc
3851
3852	#define INTERPRET_STAT_CASE(opcode, Instr) \
3853	case opcode: STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); return VERR_EM_INTERPRETER;
3854
3855	/*
3856	* The actual case statements.
3857	*/
3858	INTERPRET_CASE(OP_XCHG,Xchg);
3859	INTERPRET_CASE_EX_PARAM2(OP_DEC,Dec, IncDec, EMEmulateDec);
3860	INTERPRET_CASE_EX_PARAM2(OP_INC,Inc, IncDec, EMEmulateInc);
3861	INTERPRET_CASE(OP_POP,Pop);
3862	INTERPRET_CASE_EX_LOCK_PARAM3(OP_OR, Or, OrXorAnd, EMEmulateOr, EMEmulateLockOr);
3863	INTERPRET_CASE_EX_LOCK_PARAM3(OP_XOR,Xor, OrXorAnd, EMEmulateXor, EMEmulateLockXor);
3864	INTERPRET_CASE_EX_LOCK_PARAM3(OP_AND,And, OrXorAnd, EMEmulateAnd, EMEmulateLockAnd);
3865	INTERPRET_CASE(OP_MOV,Mov);
3866	#ifndef IN_RC
3867	INTERPRET_CASE(OP_STOSWD,StosWD);
3868	#endif
3869	INTERPRET_CASE(OP_INVLPG,InvlPg);
3870	INTERPRET_CASE(OP_CPUID,CpuId);
3871	INTERPRET_CASE(OP_MOV_CR,MovCRx);
3872	INTERPRET_CASE(OP_MOV_DR,MovDRx);
3873	#ifdef IN_RING0
3874	INTERPRET_CASE_EX_DUAL_PARAM2(OP_LIDT, LIdt, LIGdt);
3875	INTERPRET_CASE_EX_DUAL_PARAM2(OP_LGDT, LGdt, LIGdt);
3876	#endif
3877	INTERPRET_CASE(OP_LLDT,LLdt);
3878	INTERPRET_CASE(OP_LMSW,Lmsw);
3879	#ifdef EM_EMULATE_SMSW
3880	INTERPRET_CASE(OP_SMSW,Smsw);
3881	#endif
3882	INTERPRET_CASE(OP_CLTS,Clts);
3883	INTERPRET_CASE(OP_MONITOR, Monitor);
3884	INTERPRET_CASE(OP_MWAIT, MWait);
3885	INTERPRET_CASE(OP_RDMSR, Rdmsr);
3886	INTERPRET_CASE(OP_WRMSR, Wrmsr);
3887	INTERPRET_CASE_EX_PARAM3(OP_ADD,Add, AddSub, EMEmulateAdd);
3888	INTERPRET_CASE_EX_PARAM3(OP_SUB,Sub, AddSub, EMEmulateSub);
3889	INTERPRET_CASE(OP_ADC,Adc);
3890	INTERPRET_CASE_EX_LOCK_PARAM2(OP_BTR,Btr, BitTest, EMEmulateBtr, EMEmulateLockBtr);
3891	INTERPRET_CASE_EX_PARAM2(OP_BTS,Bts, BitTest, EMEmulateBts);
3892	INTERPRET_CASE_EX_PARAM2(OP_BTC,Btc, BitTest, EMEmulateBtc);
3893	INTERPRET_CASE(OP_RDPMC,Rdpmc);
3894	INTERPRET_CASE(OP_RDTSC,Rdtsc);
3895	INTERPRET_CASE(OP_CMPXCHG, CmpXchg);
3896	#ifdef IN_RC
3897	INTERPRET_CASE(OP_STI,Sti);
3898	INTERPRET_CASE(OP_XADD, XAdd);
3899	INTERPRET_CASE(OP_IRET,Iret);
3900	#endif
3901	INTERPRET_CASE(OP_CMPXCHG8B, CmpXchg8b);
3902	INTERPRET_CASE(OP_HLT,Hlt);
3903	INTERPRET_CASE(OP_WBINVD,WbInvd);
3904	#ifdef VBOX_WITH_STATISTICS
3905	# ifndef IN_RC
3906	INTERPRET_STAT_CASE(OP_XADD, XAdd);
3907	# endif
3908	INTERPRET_STAT_CASE(OP_MOVNTPS,MovNTPS);
3909	#endif
3910
3911	default:
3912	Log3(("emInterpretInstructionCPU: opcode=%d\n", pDis->pCurInstr->uOpcode));
3913	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedMisc));
3914	return VERR_EM_INTERPRETER;
3915
3916	#undef INTERPRET_CASE_EX_PARAM2
3917	#undef INTERPRET_STAT_CASE
3918	#undef INTERPRET_CASE_EX
3919	#undef INTERPRET_CASE
3920	} /* switch (opcode) */
3921	/* not reached */
3922	}
3923
3924	/**
3925	* Interprets the current instruction using the supplied DISCPUSTATE structure.
3926	*
3927	* EIP is NOT updated!
3928	*
3929	* @returns VBox strict status code.
3930	* @retval VINF_* Scheduling instructions. When these are returned, it
3931	* starts to get a bit tricky to know whether code was
3932	* executed or not... We'll address this when it becomes a problem.
3933	* @retval VERR_EM_INTERPRETER Something we can't cope with.
3934	* @retval VERR_* Fatal errors.
3935	*
3936	* @param pVCpu Pointer to the VMCPU.
3937	* @param pDis The disassembler cpu state for the instruction to be
3938	* interpreted.
3939	* @param pRegFrame The register frame. EIP is NOT changed!
3940	* @param pvFault The fault address (CR2).
3941	* @param pcbSize Size of the write (if applicable).
3942	* @param enmCodeType Code type (user/supervisor)
3943	*
3944	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
3945	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
3946	* to worry about e.g. invalid modrm combinations (!)
3947	*
3948	* @todo At this time we do NOT check if the instruction overwrites vital information.
3949	* Make sure this can't happen!! (will add some assertions/checks later)
3950	*/
3951	DECLINLINE(VBOXSTRICTRC) emInterpretInstructionCPUOuter(PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
3952	RTGCPTR pvFault, EMCODETYPE enmCodeType, uint32_t *pcbSize)
3953	{
3954	STAM_PROFILE_START(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Emulate), a);
3955	VBOXSTRICTRC rc = emInterpretInstructionCPU(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, pRegFrame, pvFault, enmCodeType, pcbSize);
3956	STAM_PROFILE_STOP(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Emulate), a);
3957	if (RT_SUCCESS(rc))
3958	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InterpretSucceeded));
3959	else
3960	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InterpretFailed));
3961	return rc;
3962	}
3963
3964
3965	#endif /* !VBOX_WITH_IEM */

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source: vbox/trunk/src/VBox/VMM/VMMAll/EMAll.cpp@ 57952

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