EMAll.cpp@ 10274

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1	/* $Id: EMAll.cpp 10274 2008-07-05 13:14:52Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor(/Manager) - All contexts
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_EM
26	#include <VBox/em.h>
27	#include <VBox/mm.h>
28	#include <VBox/selm.h>
29	#include <VBox/patm.h>
30	#include <VBox/csam.h>
31	#include <VBox/pgm.h>
32	#include <VBox/iom.h>
33	#include <VBox/stam.h>
34	#include "EMInternal.h"
35	#include <VBox/vm.h>
36	#include <VBox/hwaccm.h>
37	#include <VBox/tm.h>
38	#include <VBox/pdmapi.h>
39
40	#include <VBox/param.h>
41	#include <VBox/err.h>
42	#include <VBox/dis.h>
43	#include <VBox/disopcode.h>
44	#include <VBox/log.h>
45	#include <iprt/assert.h>
46	#include <iprt/asm.h>
47	#include <iprt/string.h>
48
49
50	/*******************************************************************************
51	* Structures and Typedefs *
52	*******************************************************************************/
53	typedef DECLCALLBACK(uint32_t) PFN_EMULATE_PARAM2_UINT32(void *pvParam1, uint64_t val2);
54	typedef DECLCALLBACK(uint32_t) PFN_EMULATE_PARAM2(void *pvParam1, size_t val2);
55	typedef DECLCALLBACK(uint32_t) PFN_EMULATE_PARAM3(void *pvParam1, uint64_t val2, size_t val3);
56	typedef DECLCALLBACK(int) FNEMULATELOCKPARAM2(void pvParam1, uint64_t val2, RTGCUINTREG32 pf);
57	typedef FNEMULATELOCKPARAM2 *PFNEMULATELOCKPARAM2;
58	typedef DECLCALLBACK(int) FNEMULATELOCKPARAM3(void pvParam1, uint64_t val2, size_t cb, RTGCUINTREG32 pf);
59	typedef FNEMULATELOCKPARAM3 *PFNEMULATELOCKPARAM3;
60
61
62	/*******************************************************************************
63	* Internal Functions *
64	*******************************************************************************/
65	DECLINLINE(int) emInterpretInstructionCPU(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize);
66
67
68	/**
69	* Get the current execution manager status.
70	*
71	* @returns Current status.
72	*/
73	EMDECL(EMSTATE) EMGetState(PVM pVM)
74	{
75	return pVM->em.s.enmState;
76	}
77
78
79	#ifndef IN_GC
80	/**
81	* Read callback for disassembly function; supports reading bytes that cross a page boundary
82	*
83	* @returns VBox status code.
84	* @param pSrc GC source pointer
85	* @param pDest HC destination pointer
86	* @param cb Number of bytes to read
87	* @param dwUserdata Callback specific user data (pCpu)
88	*
89	*/
90	DECLCALLBACK(int) EMReadBytes(RTUINTPTR pSrc, uint8_t pDest, unsigned cb, void pvUserdata)
91	{
92	DISCPUSTATE pCpu = (DISCPUSTATE )pvUserdata;
93	PVM pVM = (PVM)pCpu->apvUserData[0];
94	#ifdef IN_RING0
95	int rc = PGMPhysReadGCPtr(pVM, pDest, pSrc, cb);
96	AssertRC(rc);
97	#else
98	if (!PATMIsPatchGCAddr(pVM, pSrc))
99	{
100	int rc = PGMPhysReadGCPtr(pVM, pDest, pSrc, cb);
101	AssertRC(rc);
102	}
103	else
104	{
105	for (uint32_t i = 0; i < cb; i++)
106	{
107	uint8_t opcode;
108	if (VBOX_SUCCESS(PATMR3QueryOpcode(pVM, (RTGCPTR)pSrc + i, &opcode)))
109	{
110	*(pDest+i) = opcode;
111	}
112	}
113	}
114	#endif /* IN_RING0 */
115	return VINF_SUCCESS;
116	}
117
118	DECLINLINE(int) emDisCoreOne(PVM pVM, DISCPUSTATE pCpu, RTGCUINTPTR InstrGC, uint32_t pOpsize)
119	{
120	return DISCoreOneEx(InstrGC, pCpu->mode, EMReadBytes, pVM, pCpu, pOpsize);
121	}
122
123	#else
124
125	DECLINLINE(int) emDisCoreOne(PVM pVM, DISCPUSTATE pCpu, RTGCUINTPTR InstrGC, uint32_t pOpsize)
126	{
127	return DISCoreOne(pCpu, InstrGC, pOpsize);
128	}
129
130	#endif
131
132
133	/**
134	* Disassembles one instruction.
135	*
136	* @param pVM The VM handle.
137	* @param pCtxCore The context core (used for both the mode and instruction).
138	* @param pCpu Where to return the parsed instruction info.
139	* @param pcbInstr Where to return the instruction size. (optional)
140	*/
141	EMDECL(int) EMInterpretDisasOne(PVM pVM, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, unsigned *pcbInstr)
142	{
143	RTGCPTR GCPtrInstr;
144	int rc = SELMToFlatEx(pVM, DIS_SELREG_CS, pCtxCore, pCtxCore->rip, 0, &GCPtrInstr);
145	if (VBOX_FAILURE(rc))
146	{
147	Log(("EMInterpretDisasOne: Failed to convert %RTsel:%VGv (cpl=%d) - rc=%Vrc !!\n",
148	pCtxCore->cs, pCtxCore->rip, pCtxCore->ss & X86_SEL_RPL, rc));
149	return rc;
150	}
151	return EMInterpretDisasOneEx(pVM, (RTGCUINTPTR)GCPtrInstr, pCtxCore, pCpu, pcbInstr);
152	}
153
154
155	/**
156	* Disassembles one instruction.
157	*
158	* This is used by internally by the interpreter and by trap/access handlers.
159	*
160	* @param pVM The VM handle.
161	* @param GCPtrInstr The flat address of the instruction.
162	* @param pCtxCore The context core (used to determin the cpu mode).
163	* @param pCpu Where to return the parsed instruction info.
164	* @param pcbInstr Where to return the instruction size. (optional)
165	*/
166	EMDECL(int) EMInterpretDisasOneEx(PVM pVM, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, unsigned *pcbInstr)
167	{
168	int rc = DISCoreOneEx(GCPtrInstr, SELMGetCpuModeFromSelector(pVM, pCtxCore->eflags, pCtxCore->cs, (PCPUMSELREGHID)&pCtxCore->csHid),
169	#ifdef IN_GC
170	NULL, NULL,
171	#else
172	EMReadBytes, pVM,
173	#endif
174	pCpu, pcbInstr);
175	if (VBOX_SUCCESS(rc))
176	return VINF_SUCCESS;
177	AssertMsgFailed(("DISCoreOne failed to GCPtrInstr=%VGv rc=%Vrc\n", GCPtrInstr, rc));
178	return VERR_INTERNAL_ERROR;
179	}
180
181
182	/**
183	* Interprets the current instruction.
184	*
185	* @returns VBox status code.
186	* @retval VINF_* Scheduling instructions.
187	* @retval VERR_EM_INTERPRETER Something we can't cope with.
188	* @retval VERR_* Fatal errors.
189	*
190	* @param pVM The VM handle.
191	* @param pRegFrame The register frame.
192	* Updates the EIP if an instruction was executed successfully.
193	* @param pvFault The fault address (CR2).
194	* @param pcbSize Size of the write (if applicable).
195	*
196	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
197	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
198	* to worry about e.g. invalid modrm combinations (!)
199	*/
200	EMDECL(int) EMInterpretInstruction(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
201	{
202	RTGCPTR pbCode;
203
204	LogFlow(("EMInterpretInstruction %VGv fault %VGv\n", pRegFrame->rip, pvFault));
205	int rc = SELMToFlatEx(pVM, DIS_SELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
206	if (VBOX_SUCCESS(rc))
207	{
208	uint32_t cbOp;
209	DISCPUSTATE Cpu;
210	Cpu.mode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
211	rc = emDisCoreOne(pVM, &Cpu, (RTGCUINTPTR)pbCode, &cbOp);
212	if (VBOX_SUCCESS(rc))
213	{
214	Assert(cbOp == Cpu.opsize);
215	rc = EMInterpretInstructionCPU(pVM, &Cpu, pRegFrame, pvFault, pcbSize);
216	if (VBOX_SUCCESS(rc))
217	{
218	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
219	}
220	return rc;
221	}
222	}
223	return VERR_EM_INTERPRETER;
224	}
225
226	/**
227	* Interprets the current instruction using the supplied DISCPUSTATE structure.
228	*
229	* EIP is NOT updated!
230	*
231	* @returns VBox status code.
232	* @retval VINF_* Scheduling instructions. When these are returned, it
233	* starts to get a bit tricky to know whether code was
234	* executed or not... We'll address this when it becomes a problem.
235	* @retval VERR_EM_INTERPRETER Something we can't cope with.
236	* @retval VERR_* Fatal errors.
237	*
238	* @param pVM The VM handle.
239	* @param pCpu The disassembler cpu state for the instruction to be interpreted.
240	* @param pRegFrame The register frame. EIP is NOT changed!
241	* @param pvFault The fault address (CR2).
242	* @param pcbSize Size of the write (if applicable).
243	*
244	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
245	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
246	* to worry about e.g. invalid modrm combinations (!)
247	*
248	* @todo At this time we do NOT check if the instruction overwrites vital information.
249	* Make sure this can't happen!! (will add some assertions/checks later)
250	*/
251	EMDECL(int) EMInterpretInstructionCPU(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
252	{
253	STAM_PROFILE_START(&CTXMID(pVM->em.s.CTXSUFF(pStats)->Stat,Emulate), a);
254	int rc = emInterpretInstructionCPU(pVM, pCpu, pRegFrame, pvFault, pcbSize);
255	STAM_PROFILE_STOP(&CTXMID(pVM->em.s.CTXSUFF(pStats)->Stat,Emulate), a);
256	if (VBOX_SUCCESS(rc))
257	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,InterpretSucceeded));
258	else
259	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,InterpretFailed));
260	return rc;
261	}
262
263
264	/**
265	* Interpret a port I/O instruction.
266	*
267	* @returns VBox status code suitable for scheduling.
268	* @param pVM The VM handle.
269	* @param pCtxCore The context core. This will be updated on successful return.
270	* @param pCpu The instruction to interpret.
271	* @param cbOp The size of the instruction.
272	* @remark This may raise exceptions.
273	*/
274	EMDECL(int) EMInterpretPortIO(PVM pVM, PCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, uint32_t cbOp)
275	{
276	/*
277	* Hand it on to IOM.
278	*/
279	#ifdef IN_GC
280	int rc = IOMGCIOPortHandler(pVM, pCtxCore, pCpu);
281	if (IOM_SUCCESS(rc))
282	pCtxCore->rip += cbOp;
283	return rc;
284	#else
285	AssertReleaseMsgFailed(("not implemented\n"));
286	return VERR_NOT_IMPLEMENTED;
287	#endif
288	}
289
290
291	DECLINLINE(int) emRamRead(PVM pVM, void *pDest, RTGCPTR GCSrc, uint32_t cb)
292	{
293	#ifdef IN_GC
294	int rc = MMGCRamRead(pVM, pDest, (void *)GCSrc, cb);
295	if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
296	return rc;
297	/*
298	* The page pool cache may end up here in some cases because it
299	* flushed one of the shadow mappings used by the trapping
300	* instruction and it either flushed the TLB or the CPU reused it.
301	*/
302	RTGCPHYS GCPhys;
303	rc = PGMPhysGCPtr2GCPhys(pVM, GCSrc, &GCPhys);
304	AssertRCReturn(rc, rc);
305	PGMPhysRead(pVM, GCPhys, pDest, cb);
306	return VINF_SUCCESS;
307	#else
308	return PGMPhysReadGCPtrSafe(pVM, pDest, GCSrc, cb);
309	#endif
310	}
311
312	DECLINLINE(int) emRamWrite(PVM pVM, RTGCPTR GCDest, void *pSrc, uint32_t cb)
313	{
314	#ifdef IN_GC
315	int rc = MMGCRamWrite(pVM, (void *)GCDest, pSrc, cb);
316	if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
317	return rc;
318	/*
319	* The page pool cache may end up here in some cases because it
320	* flushed one of the shadow mappings used by the trapping
321	* instruction and it either flushed the TLB or the CPU reused it.
322	* We want to play safe here, verifying that we've got write
323	* access doesn't cost us much (see PGMPhysGCPtr2GCPhys()).
324	*/
325	uint64_t fFlags;
326	RTGCPHYS GCPhys;
327	rc = PGMGstGetPage(pVM, GCDest, &fFlags, &GCPhys);
328	if (RT_FAILURE(rc))
329	return rc;
330	if ( !(fFlags & X86_PTE_RW)
331	&& (CPUMGetGuestCR0(pVM) & X86_CR0_WP))
332	return VERR_ACCESS_DENIED;
333
334	PGMPhysWrite(pVM, GCPhys + ((RTGCUINTPTR)GCDest & PAGE_OFFSET_MASK), pSrc, cb);
335	return VINF_SUCCESS;
336
337	#else
338	return PGMPhysWriteGCPtrSafe(pVM, GCDest, pSrc, cb);
339	#endif
340	}
341
342	/* Convert sel:addr to a flat GC address */
343	static RTGCPTR emConvertToFlatAddr(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, POP_PARAMETER pParam, RTGCPTR pvAddr)
344	{
345	DIS_SELREG enmPrefixSeg = DISDetectSegReg(pCpu, pParam);
346	return SELMToFlat(pVM, enmPrefixSeg, pRegFrame, pvAddr);
347	}
348
349	#if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
350	/**
351	* Get the mnemonic for the disassembled instruction.
352	*
353	* GC/R0 doesn't include the strings in the DIS tables because
354	* of limited space.
355	*/
356	static const char *emGetMnemonic(PDISCPUSTATE pCpu)
357	{
358	switch (pCpu->pCurInstr->opcode)
359	{
360	case OP_XCHG: return "Xchg";
361	case OP_DEC: return "Dec";
362	case OP_INC: return "Inc";
363	case OP_POP: return "Pop";
364	case OP_OR: return "Or";
365	case OP_AND: return "And";
366	case OP_MOV: return "Mov";
367	case OP_INVLPG: return "InvlPg";
368	case OP_CPUID: return "CpuId";
369	case OP_MOV_CR: return "MovCRx";
370	case OP_MOV_DR: return "MovDRx";
371	case OP_LLDT: return "LLdt";
372	case OP_CLTS: return "Clts";
373	case OP_MONITOR: return "Monitor";
374	case OP_MWAIT: return "MWait";
375	case OP_RDMSR: return "Rdmsr";
376	case OP_WRMSR: return "Wrmsr";
377	case OP_ADC: return "Adc";
378	case OP_BTC: return "Btc";
379	case OP_RDTSC: return "Rdtsc";
380	case OP_STI: return "Sti";
381	case OP_XADD: return "XAdd";
382	case OP_HLT: return "Hlt";
383	case OP_IRET: return "Iret";
384	case OP_CMPXCHG: return "CmpXchg";
385	case OP_CMPXCHG8B: return "CmpXchg8b";
386	case OP_MOVNTPS: return "MovNTPS";
387	case OP_STOSWD: return "StosWD";
388	case OP_WBINVD: return "WbInvd";
389	case OP_XOR: return "Xor";
390	case OP_BTR: return "Btr";
391	case OP_BTS: return "Bts";
392	default:
393	Log(("Unknown opcode %d\n", pCpu->pCurInstr->opcode));
394	return "???";
395	}
396	}
397	#endif
398
399	/**
400	* XCHG instruction emulation.
401	*/
402	static int emInterpretXchg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
403	{
404	OP_PARAMVAL param1, param2;
405
406	/* Source to make DISQueryParamVal read the register value - ugly hack */
407	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
408	if(VBOX_FAILURE(rc))
409	return VERR_EM_INTERPRETER;
410
411	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
412	if(VBOX_FAILURE(rc))
413	return VERR_EM_INTERPRETER;
414
415	#ifdef IN_GC
416	if (TRPMHasTrap(pVM))
417	{
418	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
419	{
420	#endif
421	RTGCPTR pParam1 = 0, pParam2 = 0;
422	uint64_t valpar1, valpar2;
423
424	AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
425	switch(param1.type)
426	{
427	case PARMTYPE_IMMEDIATE: /* register type is translated to this one too */
428	valpar1 = param1.val.val64;
429	break;
430
431	case PARMTYPE_ADDRESS:
432	pParam1 = (RTGCPTR)param1.val.val64;
433	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
434	#ifdef IN_GC
435	/* Safety check (in theory it could cross a page boundary and fault there though) */
436	AssertReturn(pParam1 == pvFault, VERR_EM_INTERPRETER);
437	#endif
438	rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
439	if (VBOX_FAILURE(rc))
440	{
441	AssertMsgFailed(("MMGCRamRead %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
442	return VERR_EM_INTERPRETER;
443	}
444	break;
445
446	default:
447	AssertFailed();
448	return VERR_EM_INTERPRETER;
449	}
450
451	switch(param2.type)
452	{
453	case PARMTYPE_ADDRESS:
454	pParam2 = (RTGCPTR)param2.val.val64;
455	pParam2 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param2, pParam2);
456	#ifdef IN_GC
457	/* Safety check (in theory it could cross a page boundary and fault there though) */
458	AssertReturn(pParam2 == pvFault, VERR_EM_INTERPRETER);
459	#endif
460	rc = emRamRead(pVM, &valpar2, pParam2, param2.size);
461	if (VBOX_FAILURE(rc))
462	{
463	AssertMsgFailed(("MMGCRamRead %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
464	}
465	break;
466
467	case PARMTYPE_IMMEDIATE:
468	valpar2 = param2.val.val64;
469	break;
470
471	default:
472	AssertFailed();
473	return VERR_EM_INTERPRETER;
474	}
475
476	/* Write value of parameter 2 to parameter 1 (reg or memory address) */
477	if (pParam1 == 0)
478	{
479	Assert(param1.type == PARMTYPE_IMMEDIATE); /* register actually */
480	switch(param1.size)
481	{
482	case 1: //special case for AH etc
483	rc = DISWriteReg8(pRegFrame, pCpu->param1.base.reg_gen, (uint8_t )valpar2); break;
484	case 2: rc = DISWriteReg16(pRegFrame, pCpu->param1.base.reg_gen, (uint16_t)valpar2); break;
485	case 4: rc = DISWriteReg32(pRegFrame, pCpu->param1.base.reg_gen, (uint32_t)valpar2); break;
486	case 8: rc = DISWriteReg64(pRegFrame, pCpu->param1.base.reg_gen, valpar2); break;
487	default: AssertFailedReturn(VERR_EM_INTERPRETER);
488	}
489	if (VBOX_FAILURE(rc))
490	return VERR_EM_INTERPRETER;
491	}
492	else
493	{
494	rc = emRamWrite(pVM, pParam1, &valpar2, param1.size);
495	if (VBOX_FAILURE(rc))
496	{
497	AssertMsgFailed(("emRamWrite %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
498	return VERR_EM_INTERPRETER;
499	}
500	}
501
502	/* Write value of parameter 1 to parameter 2 (reg or memory address) */
503	if (pParam2 == 0)
504	{
505	Assert(param2.type == PARMTYPE_IMMEDIATE); /* register actually */
506	switch(param2.size)
507	{
508	case 1: //special case for AH etc
509	rc = DISWriteReg8(pRegFrame, pCpu->param2.base.reg_gen, (uint8_t )valpar1); break;
510	case 2: rc = DISWriteReg16(pRegFrame, pCpu->param2.base.reg_gen, (uint16_t)valpar1); break;
511	case 4: rc = DISWriteReg32(pRegFrame, pCpu->param2.base.reg_gen, (uint32_t)valpar1); break;
512	case 8: rc = DISWriteReg64(pRegFrame, pCpu->param2.base.reg_gen, valpar1); break;
513	default: AssertFailedReturn(VERR_EM_INTERPRETER);
514	}
515	if (VBOX_FAILURE(rc))
516	return VERR_EM_INTERPRETER;
517	}
518	else
519	{
520	rc = emRamWrite(pVM, pParam2, &valpar1, param2.size);
521	if (VBOX_FAILURE(rc))
522	{
523	AssertMsgFailed(("emRamWrite %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
524	return VERR_EM_INTERPRETER;
525	}
526	}
527
528	*pcbSize = param2.size;
529	return VINF_SUCCESS;
530	#ifdef IN_GC
531	}
532	}
533	#endif
534	return VERR_EM_INTERPRETER;
535	}
536
537	/**
538	* INC and DEC emulation.
539	*/
540	static int emInterpretIncDec(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
541	PFN_EMULATE_PARAM2 pfnEmulate)
542	{
543	OP_PARAMVAL param1;
544
545	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
546	if(VBOX_FAILURE(rc))
547	return VERR_EM_INTERPRETER;
548
549	#ifdef IN_GC
550	if (TRPMHasTrap(pVM))
551	{
552	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
553	{
554	#endif
555	RTGCPTR pParam1 = 0;
556	uint64_t valpar1;
557
558	if (param1.type == PARMTYPE_ADDRESS)
559	{
560	pParam1 = (RTGCPTR)param1.val.val64;
561	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
562	#ifdef IN_GC
563	/* Safety check (in theory it could cross a page boundary and fault there though) */
564	AssertReturn(pParam1 == pvFault, VERR_EM_INTERPRETER);
565	#endif
566	rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
567	if (VBOX_FAILURE(rc))
568	{
569	AssertMsgFailed(("emRamRead %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
570	return VERR_EM_INTERPRETER;
571	}
572	}
573	else
574	{
575	AssertFailed();
576	return VERR_EM_INTERPRETER;
577	}
578
579	uint32_t eflags;
580
581	eflags = pfnEmulate(&valpar1, param1.size);
582
583	/* Write result back */
584	rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
585	if (VBOX_FAILURE(rc))
586	{
587	AssertMsgFailed(("emRamWrite %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
588	return VERR_EM_INTERPRETER;
589	}
590
591	/* Update guest's eflags and finish. */
592	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
593	\| (eflags & (X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
594
595	/* All done! */
596	*pcbSize = param1.size;
597	return VINF_SUCCESS;
598	#ifdef IN_GC
599	}
600	}
601	#endif
602	return VERR_EM_INTERPRETER;
603	}
604
605	/**
606	* POP Emulation.
607	*/
608	static int emInterpretPop(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
609	{
610	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
611	OP_PARAMVAL param1;
612	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
613	if(VBOX_FAILURE(rc))
614	return VERR_EM_INTERPRETER;
615
616	#ifdef IN_GC
617	if (TRPMHasTrap(pVM))
618	{
619	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
620	{
621	#endif
622	RTGCPTR pParam1 = 0;
623	uint32_t valpar1;
624	RTGCPTR pStackVal;
625
626	/* Read stack value first */
627	if (SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->ss, &pRegFrame->ssHid) == CPUMODE_16BIT)
628	return VERR_EM_INTERPRETER; /* No legacy 16 bits stuff here, please. */
629
630	/* Convert address; don't bother checking limits etc, as we only read here */
631	pStackVal = SELMToFlat(pVM, DIS_SELREG_SS, pRegFrame, (RTGCPTR)pRegFrame->esp);
632	if (pStackVal == 0)
633	return VERR_EM_INTERPRETER;
634
635	rc = emRamRead(pVM, &valpar1, pStackVal, param1.size);
636	if (VBOX_FAILURE(rc))
637	{
638	AssertMsgFailed(("emRamRead %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
639	return VERR_EM_INTERPRETER;
640	}
641
642	if (param1.type == PARMTYPE_ADDRESS)
643	{
644	pParam1 = (RTGCPTR)param1.val.val64;
645
646	/* pop [esp+xx] uses esp after the actual pop! */
647	AssertCompile(USE_REG_ESP == USE_REG_SP);
648	if ( (pCpu->param1.flags & USE_BASE)
649	&& (pCpu->param1.flags & (USE_REG_GEN16\|USE_REG_GEN32))
650	&& pCpu->param1.base.reg_gen == USE_REG_ESP
651	)
652	pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + param1.size);
653
654	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
655
656	#ifdef IN_GC
657	/* Safety check (in theory it could cross a page boundary and fault there though) */
658	AssertMsgReturn(pParam1 == pvFault \|\| (RTGCPTR)pRegFrame->esp == pvFault, ("%VGv != %VGv ss:esp=%04X:%08x\n", pParam1, pvFault, pRegFrame->ss, pRegFrame->esp), VERR_EM_INTERPRETER);
659	#endif
660	rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
661	if (VBOX_FAILURE(rc))
662	{
663	AssertMsgFailed(("emRamWrite %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
664	return VERR_EM_INTERPRETER;
665	}
666
667	/* Update ESP as the last step */
668	pRegFrame->esp += param1.size;
669	}
670	else
671	{
672	#ifndef DEBUG_bird // annoying assertion.
673	AssertFailed();
674	#endif
675	return VERR_EM_INTERPRETER;
676	}
677
678	/* All done! */
679	*pcbSize = param1.size;
680	return VINF_SUCCESS;
681	#ifdef IN_GC
682	}
683	}
684	#endif
685	return VERR_EM_INTERPRETER;
686	}
687
688
689	/**
690	* XOR/OR/AND Emulation.
691	*/
692	static int emInterpretOrXorAnd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
693	PFN_EMULATE_PARAM3 pfnEmulate)
694	{
695	OP_PARAMVAL param1, param2;
696	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
697	if(VBOX_FAILURE(rc))
698	return VERR_EM_INTERPRETER;
699
700	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
701	if(VBOX_FAILURE(rc))
702	return VERR_EM_INTERPRETER;
703
704	#ifdef LOG_ENABLED
705	const char *pszInstr;
706
707	if (pCpu->pCurInstr->opcode == OP_XOR)
708	pszInstr = "Xor";
709	else if (pCpu->pCurInstr->opcode == OP_OR)
710	pszInstr = "Or";
711	else if (pCpu->pCurInstr->opcode == OP_AND)
712	pszInstr = "And";
713	else
714	pszInstr = "OrXorAnd??";
715	#endif
716
717	#ifdef IN_GC
718	if (TRPMHasTrap(pVM))
719	{
720	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
721	{
722	#endif
723	RTGCPTR pParam1;
724	uint64_t valpar1, valpar2;
725
726	if (pCpu->param1.size != pCpu->param2.size)
727	{
728	if (pCpu->param1.size < pCpu->param2.size)
729	{
730	AssertMsgFailed(("%s at %VGv parameter mismatch %d vs %d!!\n", pszInstr, pRegFrame->rip, pCpu->param1.size, pCpu->param2.size)); /* should never happen! */
731	return VERR_EM_INTERPRETER;
732	}
733	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
734	pCpu->param2.size = pCpu->param1.size;
735	param2.size = param1.size;
736	}
737
738	/* The destination is always a virtual address */
739	if (param1.type == PARMTYPE_ADDRESS)
740	{
741	pParam1 = (RTGCPTR)param1.val.val64;
742	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
743
744	#ifdef IN_GC
745	/* Safety check (in theory it could cross a page boundary and fault there though) */
746	AssertMsgReturn(pParam1 == pvFault, ("eip=%VGv, pParam1=%VGv pvFault=%VGv\n", pRegFrame->rip, pParam1, pvFault), VERR_EM_INTERPRETER);
747	#endif
748	rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
749	if (VBOX_FAILURE(rc))
750	{
751	AssertMsgFailed(("emRamRead %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
752	return VERR_EM_INTERPRETER;
753	}
754	}
755	else
756	{
757	AssertFailed();
758	return VERR_EM_INTERPRETER;
759	}
760
761	/* Register or immediate data */
762	switch(param2.type)
763	{
764	case PARMTYPE_IMMEDIATE: /* both immediate data and register (ugly) */
765	valpar2 = param2.val.val64;
766	break;
767
768	default:
769	AssertFailed();
770	return VERR_EM_INTERPRETER;
771	}
772
773	LogFlow(("emInterpretOrXorAnd %s %VGv %RX64 - %RX64 size %d (%d)\n", pszInstr, pParam1, valpar1, valpar2, param2.size, param1.size));
774
775	/* Data read, emulate instruction. */
776	uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
777
778	LogFlow(("emInterpretOrXorAnd %s result %RX64\n", pszInstr, valpar1));
779
780	/* Update guest's eflags and finish. */
781	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
782	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
783
784	/* And write it back */
785	rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
786	if (VBOX_SUCCESS(rc))
787	{
788	/* All done! */
789	*pcbSize = param2.size;
790	return VINF_SUCCESS;
791	}
792	#ifdef IN_GC
793	}
794	}
795	#endif
796	return VERR_EM_INTERPRETER;
797	}
798
799	/**
800	* LOCK XOR/OR/AND Emulation.
801	*/
802	static int emInterpretLockOrXorAnd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
803	uint32_t *pcbSize, PFNEMULATELOCKPARAM3 pfnEmulate)
804	{
805	void *pvParam1;
806
807	OP_PARAMVAL param1, param2;
808	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
809	if(VBOX_FAILURE(rc))
810	return VERR_EM_INTERPRETER;
811
812	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
813	if(VBOX_FAILURE(rc))
814	return VERR_EM_INTERPRETER;
815
816	if (pCpu->param1.size != pCpu->param2.size)
817	{
818	AssertMsgReturn(pCpu->param1.size >= pCpu->param2.size, /* should never happen! */
819	("%s at %VGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pCpu), pRegFrame->rip, pCpu->param1.size, pCpu->param2.size),
820	VERR_EM_INTERPRETER);
821
822	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
823	pCpu->param2.size = pCpu->param1.size;
824	param2.size = param1.size;
825	}
826
827	/* The destination is always a virtual address */
828	AssertReturn(param1.type == PARMTYPE_ADDRESS, VERR_EM_INTERPRETER);
829
830	RTGCPTR GCPtrPar1 = param1.val.val64;
831	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
832	#ifdef IN_GC
833	pvParam1 = (void *)GCPtrPar1;
834	#else
835	rc = PGMPhysGCPtr2HCPtr(pVM, GCPtrPar1, &pvParam1);
836	if (VBOX_FAILURE(rc))
837	{
838	AssertRC(rc);
839	return VERR_EM_INTERPRETER;
840	}
841	#endif
842
843	# ifdef IN_GC
844	/* Safety check (in theory it could cross a page boundary and fault there though) */
845	Assert( TRPMHasTrap(pVM)
846	&& (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW));
847	AssertMsgReturn(GCPtrPar1 == pvFault, ("eip=%VGv, GCPtrPar1=%VGv pvFault=%VGv\n", pRegFrame->rip, GCPtrPar1, pvFault), VERR_EM_INTERPRETER);
848	# endif
849
850	/* Register and immediate data == PARMTYPE_IMMEDIATE */
851	AssertReturn(param2.type == PARMTYPE_IMMEDIATE, VERR_EM_INTERPRETER);
852	RTGCUINTREG ValPar2 = param2.val.val64;
853
854	/* Try emulate it with a one-shot #PF handler in place. */
855	Log2(("%s %VGv imm%d=%RX64\n", emGetMnemonic(pCpu), GCPtrPar1, pCpu->param2.size*8, ValPar2));
856
857	RTGCUINTREG32 eflags = 0;
858	#ifdef IN_GC
859	MMGCRamRegisterTrapHandler(pVM);
860	#endif
861	rc = pfnEmulate(pvParam1, ValPar2, pCpu->param2.size, &eflags);
862	#ifdef IN_GC
863	MMGCRamDeregisterTrapHandler(pVM);
864	#endif
865	if (RT_FAILURE(rc))
866	{
867	Log(("%s %VGv imm%d=%RX64-> emulation failed due to page fault!\n", emGetMnemonic(pCpu), GCPtrPar1, pCpu->param2.size*8, ValPar2));
868	return VERR_EM_INTERPRETER;
869	}
870
871	/* Update guest's eflags and finish. */
872	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
873	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
874
875	*pcbSize = param2.size;
876	return VINF_SUCCESS;
877	}
878
879	/**
880	* ADD, ADC & SUB Emulation.
881	*/
882	static int emInterpretAddSub(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
883	PFN_EMULATE_PARAM3 pfnEmulate)
884	{
885	OP_PARAMVAL param1, param2;
886	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
887	if(VBOX_FAILURE(rc))
888	return VERR_EM_INTERPRETER;
889
890	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
891	if(VBOX_FAILURE(rc))
892	return VERR_EM_INTERPRETER;
893
894	#ifdef LOG_ENABLED
895	const char *pszInstr;
896
897	if (pCpu->pCurInstr->opcode == OP_SUB)
898	pszInstr = "Sub";
899	else if (pCpu->pCurInstr->opcode == OP_ADD)
900	pszInstr = "Add";
901	else if (pCpu->pCurInstr->opcode == OP_ADC)
902	pszInstr = "Adc";
903	else
904	pszInstr = "AddSub??";
905	#endif
906
907	#ifdef IN_GC
908	if (TRPMHasTrap(pVM))
909	{
910	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
911	{
912	#endif
913	RTGCPTR pParam1;
914	uint64_t valpar1, valpar2;
915
916	if (pCpu->param1.size != pCpu->param2.size)
917	{
918	if (pCpu->param1.size < pCpu->param2.size)
919	{
920	AssertMsgFailed(("%s at %VGv parameter mismatch %d vs %d!!\n", pszInstr, pRegFrame->rip, pCpu->param1.size, pCpu->param2.size)); /* should never happen! */
921	return VERR_EM_INTERPRETER;
922	}
923	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
924	pCpu->param2.size = pCpu->param1.size;
925	param2.size = param1.size;
926	}
927
928	/* The destination is always a virtual address */
929	if (param1.type == PARMTYPE_ADDRESS)
930	{
931	pParam1 = (RTGCPTR)param1.val.val64;
932	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
933
934	#ifdef IN_GC
935	/* Safety check (in theory it could cross a page boundary and fault there though) */
936	AssertReturn(pParam1 == pvFault, VERR_EM_INTERPRETER);
937	#endif
938	rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
939	if (VBOX_FAILURE(rc))
940	{
941	AssertMsgFailed(("emRamRead %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
942	return VERR_EM_INTERPRETER;
943	}
944	}
945	else
946	{
947	#ifndef DEBUG_bird
948	AssertFailed();
949	#endif
950	return VERR_EM_INTERPRETER;
951	}
952
953	/* Register or immediate data */
954	switch(param2.type)
955	{
956	case PARMTYPE_IMMEDIATE: /* both immediate data and register (ugly) */
957	valpar2 = param2.val.val64;
958	break;
959
960	default:
961	AssertFailed();
962	return VERR_EM_INTERPRETER;
963	}
964
965	/* Data read, emulate instruction. */
966	uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
967
968	/* Update guest's eflags and finish. */
969	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
970	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
971
972	/* And write it back */
973	rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
974	if (VBOX_SUCCESS(rc))
975	{
976	/* All done! */
977	*pcbSize = param2.size;
978	return VINF_SUCCESS;
979	}
980	#ifdef IN_GC
981	}
982	}
983	#endif
984	return VERR_EM_INTERPRETER;
985	}
986
987	/**
988	* ADC Emulation.
989	*/
990	static int emInterpretAdc(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
991	{
992	if (pRegFrame->eflags.Bits.u1CF)
993	return emInterpretAddSub(pVM, pCpu, pRegFrame, pvFault, pcbSize, EMEmulateAdcWithCarrySet);
994	else
995	return emInterpretAddSub(pVM, pCpu, pRegFrame, pvFault, pcbSize, EMEmulateAdd);
996	}
997
998	/**
999	* BTR/C/S Emulation.
1000	*/
1001	static int emInterpretBitTest(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
1002	PFN_EMULATE_PARAM2_UINT32 pfnEmulate)
1003	{
1004	OP_PARAMVAL param1, param2;
1005	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
1006	if(VBOX_FAILURE(rc))
1007	return VERR_EM_INTERPRETER;
1008
1009	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1010	if(VBOX_FAILURE(rc))
1011	return VERR_EM_INTERPRETER;
1012
1013	#ifdef LOG_ENABLED
1014	const char *pszInstr;
1015
1016	if (pCpu->pCurInstr->opcode == OP_BTR)
1017	pszInstr = "Btr";
1018	else if (pCpu->pCurInstr->opcode == OP_BTS)
1019	pszInstr = "Bts";
1020	else if (pCpu->pCurInstr->opcode == OP_BTC)
1021	pszInstr = "Btc";
1022	else
1023	pszInstr = "Bit??";
1024	#endif
1025
1026	#ifdef IN_GC
1027	if (TRPMHasTrap(pVM))
1028	{
1029	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1030	{
1031	#endif
1032	RTGCPTR pParam1;
1033	uint64_t valpar1 = 0, valpar2;
1034	uint32_t eflags;
1035
1036	/* The destination is always a virtual address */
1037	if (param1.type != PARMTYPE_ADDRESS)
1038	return VERR_EM_INTERPRETER;
1039
1040	pParam1 = (RTGCPTR)param1.val.val64;
1041	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
1042
1043	/* Register or immediate data */
1044	switch(param2.type)
1045	{
1046	case PARMTYPE_IMMEDIATE: /* both immediate data and register (ugly) */
1047	valpar2 = param2.val.val64;
1048	break;
1049
1050	default:
1051	AssertFailed();
1052	return VERR_EM_INTERPRETER;
1053	}
1054
1055	Log2(("emInterpret%s: pvFault=%VGv pParam1=%VGv val2=%x\n", pszInstr, pvFault, pParam1, valpar2));
1056	pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + valpar2/8);
1057	#ifdef IN_GC
1058	/* Safety check. */
1059	AssertMsgReturn((RTGCPTR)((RTGCUINTPTR)pParam1 & ~3) == pvFault, ("pParam1=%VGv pvFault=%VGv\n", pParam1, pvFault), VERR_EM_INTERPRETER);
1060	#endif
1061	rc = emRamRead(pVM, &valpar1, pParam1, 1);
1062	if (VBOX_FAILURE(rc))
1063	{
1064	AssertMsgFailed(("emRamRead %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
1065	return VERR_EM_INTERPRETER;
1066	}
1067
1068	Log2(("emInterpretBtx: val=%x\n", valpar1));
1069	/* Data read, emulate bit test instruction. */
1070	eflags = pfnEmulate(&valpar1, valpar2 & 0x7);
1071
1072	Log2(("emInterpretBtx: val=%x CF=%d\n", valpar1, !!(eflags & X86_EFL_CF)));
1073
1074	/* Update guest's eflags and finish. */
1075	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1076	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1077
1078	/* And write it back */
1079	rc = emRamWrite(pVM, pParam1, &valpar1, 1);
1080	if (VBOX_SUCCESS(rc))
1081	{
1082	/* All done! */
1083	*pcbSize = 1;
1084	return VINF_SUCCESS;
1085	}
1086	#ifdef IN_GC
1087	}
1088	}
1089	#endif
1090	return VERR_EM_INTERPRETER;
1091	}
1092
1093	/**
1094	* LOCK BTR/C/S Emulation.
1095	*/
1096	static int emInterpretLockBitTest(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
1097	uint32_t *pcbSize, PFNEMULATELOCKPARAM2 pfnEmulate)
1098	{
1099	void *pvParam1;
1100
1101	OP_PARAMVAL param1, param2;
1102	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
1103	if(VBOX_FAILURE(rc))
1104	return VERR_EM_INTERPRETER;
1105
1106	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1107	if(VBOX_FAILURE(rc))
1108	return VERR_EM_INTERPRETER;
1109
1110	/* The destination is always a virtual address */
1111	if (param1.type != PARMTYPE_ADDRESS)
1112	return VERR_EM_INTERPRETER;
1113
1114	/* Register and immediate data == PARMTYPE_IMMEDIATE */
1115	AssertReturn(param2.type == PARMTYPE_IMMEDIATE, VERR_EM_INTERPRETER);
1116	uint64_t ValPar2 = param2.val.val64;
1117
1118	/* Adjust the parameters so what we're dealing with is a bit within the byte pointed to. */
1119	RTGCPTR GCPtrPar1 = param1.val.val64;
1120	GCPtrPar1 = (GCPtrPar1 + ValPar2 / 8);
1121	ValPar2 &= 7;
1122
1123	#ifdef IN_GC
1124	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
1125	pvParam1 = (void *)GCPtrPar1;
1126	#else
1127	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
1128	rc = PGMPhysGCPtr2HCPtr(pVM, GCPtrPar1, &pvParam1);
1129	if (VBOX_FAILURE(rc))
1130	{
1131	AssertRC(rc);
1132	return VERR_EM_INTERPRETER;
1133	}
1134	#endif
1135
1136	Log2(("emInterpretLockBitTest %s: pvFault=%VGv GCPtrPar1=%VGv imm=%RX64\n", emGetMnemonic(pCpu), pvFault, GCPtrPar1, ValPar2));
1137
1138	#ifdef IN_GC
1139	Assert(TRPMHasTrap(pVM));
1140	AssertMsgReturn((RTGCPTR)((RTGCUINTPTR)GCPtrPar1 & ~(RTGCUINTPTR)3) == pvFault,
1141	("GCPtrPar1=%VGv pvFault=%VGv\n", GCPtrPar1, pvFault),
1142	VERR_EM_INTERPRETER);
1143	#endif
1144
1145	/* Try emulate it with a one-shot #PF handler in place. */
1146	RTGCUINTREG32 eflags = 0;
1147	#ifdef IN_GC
1148	MMGCRamRegisterTrapHandler(pVM);
1149	#endif
1150	rc = pfnEmulate(pvParam1, ValPar2, &eflags);
1151	#ifdef IN_GC
1152	MMGCRamDeregisterTrapHandler(pVM);
1153	#endif
1154	if (RT_FAILURE(rc))
1155	{
1156	Log(("emInterpretLockBitTest %s: %VGv imm%d=%RX64 -> emulation failed due to page fault!\n",
1157	emGetMnemonic(pCpu), GCPtrPar1, pCpu->param2.size*8, ValPar2));
1158	return VERR_EM_INTERPRETER;
1159	}
1160
1161	Log2(("emInterpretLockBitTest %s: GCPtrPar1=%VGv imm=%VX64 CF=%d\n", emGetMnemonic(pCpu), GCPtrPar1, ValPar2, !!(eflags & X86_EFL_CF)));
1162
1163	/* Update guest's eflags and finish. */
1164	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1165	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1166
1167	*pcbSize = 1;
1168	return VINF_SUCCESS;
1169	}
1170
1171	/**
1172	* MOV emulation.
1173	*/
1174	static int emInterpretMov(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1175	{
1176	OP_PARAMVAL param1, param2;
1177	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
1178	if(VBOX_FAILURE(rc))
1179	return VERR_EM_INTERPRETER;
1180
1181	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1182	if(VBOX_FAILURE(rc))
1183	return VERR_EM_INTERPRETER;
1184
1185	#ifdef IN_GC
1186	if (TRPMHasTrap(pVM))
1187	{
1188	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1189	{
1190	#else
1191	/** @todo Make this the default and don't rely on TRPM information. */
1192	if (param1.type == PARMTYPE_ADDRESS)
1193	{
1194	#endif
1195	RTGCPTR pDest;
1196	uint64_t val64;
1197
1198	switch(param1.type)
1199	{
1200	case PARMTYPE_IMMEDIATE:
1201	if(!(param1.flags & (PARAM_VAL32\|PARAM_VAL64)))
1202	return VERR_EM_INTERPRETER;
1203	/* fallthru */
1204
1205	case PARMTYPE_ADDRESS:
1206	pDest = (RTGCPTR)param1.val.val64;
1207	pDest = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pDest);
1208	break;
1209
1210	default:
1211	AssertFailed();
1212	return VERR_EM_INTERPRETER;
1213	}
1214
1215	switch(param2.type)
1216	{
1217	case PARMTYPE_IMMEDIATE: /* register type is translated to this one too */
1218	val64 = param2.val.val64;
1219	break;
1220
1221	default:
1222	Log(("emInterpretMov: unexpected type=%d eip=%VGv\n", param2.type, pRegFrame->rip));
1223	return VERR_EM_INTERPRETER;
1224	}
1225	#ifdef LOG_ENABLED
1226	if (pCpu->mode == CPUMODE_64BIT)
1227	LogFlow(("EMInterpretInstruction at %VGv: OP_MOV %VGv <- %RX64 (%d) &val32=%VHv\n", pRegFrame->rip, pDest, val64, param2.size, &val64));
1228	else
1229	LogFlow(("EMInterpretInstruction at %VGv: OP_MOV %VGv <- %08X (%d) &val32=%VHv\n", pRegFrame->rip, pDest, (uint32_t)val64, param2.size, &val64));
1230	#endif
1231
1232	Assert(param2.size <= 8 && param2.size > 0);
1233
1234	#if 0 /* CSAM/PATM translates aliases which causes this to incorrectly trigger. See #2609 and #1498. */
1235	#ifdef IN_GC
1236	/* Safety check (in theory it could cross a page boundary and fault there though) */
1237	AssertMsgReturn(pDest == pvFault, ("eip=%VGv pDest=%VGv pvFault=%VGv\n", pRegFrame->rip, pDest, pvFault), VERR_EM_INTERPRETER);
1238	#endif
1239	#endif
1240	rc = emRamWrite(pVM, pDest, &val64, param2.size);
1241	if (VBOX_FAILURE(rc))
1242	return VERR_EM_INTERPRETER;
1243
1244	*pcbSize = param2.size;
1245	}
1246	else
1247	{ /* read fault */
1248	RTGCPTR pSrc;
1249	uint64_t val64;
1250
1251	/* Source */
1252	switch(param2.type)
1253	{
1254	case PARMTYPE_IMMEDIATE:
1255	if(!(param2.flags & (PARAM_VAL32\|PARAM_VAL64)))
1256	return VERR_EM_INTERPRETER;
1257	/* fallthru */
1258
1259	case PARMTYPE_ADDRESS:
1260	pSrc = (RTGCPTR)param2.val.val64;
1261	pSrc = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param2, pSrc);
1262	break;
1263
1264	default:
1265	return VERR_EM_INTERPRETER;
1266	}
1267
1268	Assert(param1.size <= 8 && param1.size > 0);
1269	#ifdef IN_GC
1270	/* Safety check (in theory it could cross a page boundary and fault there though) */
1271	AssertReturn(pSrc == pvFault, VERR_EM_INTERPRETER);
1272	#endif
1273	rc = emRamRead(pVM, &val64, pSrc, param1.size);
1274	if (VBOX_FAILURE(rc))
1275	return VERR_EM_INTERPRETER;
1276
1277	/* Destination */
1278	switch(param1.type)
1279	{
1280	case PARMTYPE_REGISTER:
1281	switch(param1.size)
1282	{
1283	case 1: rc = DISWriteReg8(pRegFrame, pCpu->param1.base.reg_gen, (uint8_t) val64); break;
1284	case 2: rc = DISWriteReg16(pRegFrame, pCpu->param1.base.reg_gen, (uint16_t)val64); break;
1285	case 4: rc = DISWriteReg32(pRegFrame, pCpu->param1.base.reg_gen, (uint32_t)val64); break;
1286	case 8: rc = DISWriteReg64(pRegFrame, pCpu->param1.base.reg_gen, val64); break;
1287	default:
1288	return VERR_EM_INTERPRETER;
1289	}
1290	if (VBOX_FAILURE(rc))
1291	return rc;
1292	break;
1293
1294	default:
1295	return VERR_EM_INTERPRETER;
1296	}
1297	#ifdef LOG_ENABLED
1298	if (pCpu->mode == CPUMODE_64BIT)
1299	LogFlow(("EMInterpretInstruction: OP_MOV %VGv -> %RX64 (%d)\n", pSrc, val64, param1.size));
1300	else
1301	LogFlow(("EMInterpretInstruction: OP_MOV %VGv -> %08X (%d)\n", pSrc, (uint32_t)val64, param1.size));
1302	#endif
1303	}
1304	return VINF_SUCCESS;
1305	#ifdef IN_GC
1306	}
1307	#endif
1308	return VERR_EM_INTERPRETER;
1309	}
1310
1311	/*
1312	* [LOCK] CMPXCHG emulation.
1313	*/
1314	#ifdef IN_GC
1315	static int emInterpretCmpXchg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1316	{
1317	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
1318	OP_PARAMVAL param1, param2;
1319
1320	#ifdef LOG_ENABLED
1321	const char *pszInstr;
1322
1323	if (pCpu->prefix & PREFIX_LOCK)
1324	pszInstr = "Lock CmpXchg";
1325	else
1326	pszInstr = "CmpXchg";
1327	#endif
1328
1329	/* Source to make DISQueryParamVal read the register value - ugly hack */
1330	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1331	if(VBOX_FAILURE(rc))
1332	return VERR_EM_INTERPRETER;
1333
1334	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1335	if(VBOX_FAILURE(rc))
1336	return VERR_EM_INTERPRETER;
1337
1338	if (TRPMHasTrap(pVM))
1339	{
1340	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1341	{
1342	RTRCPTR pParam1;
1343	uint32_t valpar, eflags;
1344	#ifdef VBOX_STRICT
1345	uint32_t valpar1 = 0; /// @todo used uninitialized...
1346	#endif
1347
1348	AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
1349	switch(param1.type)
1350	{
1351	case PARMTYPE_ADDRESS:
1352	pParam1 = (RTRCPTR)param1.val.val64;
1353	pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);
1354
1355	/* Safety check (in theory it could cross a page boundary and fault there though) */
1356	AssertMsgReturn(pParam1 == (RTRCPTR)pvFault, ("eip=%VGv pParam1=%VRv pvFault=%VGv\n", pRegFrame->rip, pParam1, pvFault), VERR_EM_INTERPRETER);
1357	break;
1358
1359	default:
1360	return VERR_EM_INTERPRETER;
1361	}
1362
1363	switch(param2.type)
1364	{
1365	case PARMTYPE_IMMEDIATE: /* register actually */
1366	valpar = param2.val.val32;
1367	break;
1368
1369	default:
1370	return VERR_EM_INTERPRETER;
1371	}
1372
1373	LogFlow(("%s %VRv=%08x eax=%08x %08x\n", pszInstr, pParam1, valpar1, pRegFrame->eax, valpar));
1374
1375	MMGCRamRegisterTrapHandler(pVM);
1376	if (pCpu->prefix & PREFIX_LOCK)
1377	rc = EMGCEmulateLockCmpXchg(pParam1, &pRegFrame->eax, valpar, pCpu->param2.size, &eflags);
1378	else
1379	rc = EMGCEmulateCmpXchg(pParam1, &pRegFrame->eax, valpar, pCpu->param2.size, &eflags);
1380	MMGCRamDeregisterTrapHandler(pVM);
1381
1382	if (VBOX_FAILURE(rc))
1383	{
1384	Log(("%s %VGv=%08x eax=%08x %08x -> emulation failed due to page fault!\n", pszInstr, pParam1, valpar1, pRegFrame->eax, valpar));
1385	return VERR_EM_INTERPRETER;
1386	}
1387
1388	LogFlow(("%s %VRv=%08x eax=%08x %08x ZF=%d\n", pszInstr, pParam1, valpar1, pRegFrame->eax, valpar, !!(eflags & X86_EFL_ZF)));
1389
1390	/* Update guest's eflags and finish. */
1391	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1392	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1393
1394	*pcbSize = param2.size;
1395	return VINF_SUCCESS;
1396	}
1397	}
1398	return VERR_EM_INTERPRETER;
1399	}
1400
1401	/*
1402	* [LOCK] CMPXCHG8B emulation.
1403	*/
1404	static int emInterpretCmpXchg8b(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1405	{
1406	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
1407	OP_PARAMVAL param1;
1408
1409	#ifdef LOG_ENABLED
1410	const char *pszInstr;
1411
1412	if (pCpu->prefix & PREFIX_LOCK)
1413	pszInstr = "Lock CmpXchg8b";
1414	else
1415	pszInstr = "CmpXchg8b";
1416	#endif
1417
1418	/* Source to make DISQueryParamVal read the register value - ugly hack */
1419	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1420	if(VBOX_FAILURE(rc))
1421	return VERR_EM_INTERPRETER;
1422
1423	if (TRPMHasTrap(pVM))
1424	{
1425	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1426	{
1427	RTRCPTR pParam1;
1428	uint32_t eflags;
1429
1430	AssertReturn(pCpu->param1.size == 8, VERR_EM_INTERPRETER);
1431	switch(param1.type)
1432	{
1433	case PARMTYPE_ADDRESS:
1434	pParam1 = (RTRCPTR)param1.val.val64;
1435	pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);
1436
1437	/* Safety check (in theory it could cross a page boundary and fault there though) */
1438	AssertMsgReturn(pParam1 == (RTRCPTR)pvFault, ("eip=%VGv pParam1=%VRv pvFault=%VGv\n", pRegFrame->rip, pParam1, pvFault), VERR_EM_INTERPRETER);
1439	break;
1440
1441	default:
1442	return VERR_EM_INTERPRETER;
1443	}
1444
1445	LogFlow(("%s %VRv=%08x eax=%08x\n", pszInstr, pParam1, pRegFrame->eax));
1446
1447	MMGCRamRegisterTrapHandler(pVM);
1448	if (pCpu->prefix & PREFIX_LOCK)
1449	rc = EMGCEmulateLockCmpXchg8b(pParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx, &eflags);
1450	else
1451	rc = EMGCEmulateCmpXchg8b(pParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx, &eflags);
1452	MMGCRamDeregisterTrapHandler(pVM);
1453
1454	if (VBOX_FAILURE(rc))
1455	{
1456	Log(("%s %VGv=%08x eax=%08x -> emulation failed due to page fault!\n", pszInstr, pParam1, pRegFrame->eax));
1457	return VERR_EM_INTERPRETER;
1458	}
1459
1460	LogFlow(("%s %VGv=%08x eax=%08x ZF=%d\n", pszInstr, pParam1, pRegFrame->eax, !!(eflags & X86_EFL_ZF)));
1461
1462	/* Update guest's eflags and finish; note that only ZF is affected. */
1463	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_ZF))
1464	\| (eflags & (X86_EFL_ZF));
1465
1466	*pcbSize = 8;
1467	return VINF_SUCCESS;
1468	}
1469	}
1470	return VERR_EM_INTERPRETER;
1471	}
1472	#endif
1473
1474	/*
1475	* [LOCK] XADD emulation.
1476	*/
1477	#ifdef IN_GC
1478	static int emInterpretXAdd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1479	{
1480	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
1481	OP_PARAMVAL param1;
1482	uint32_t *pParamReg2;
1483	size_t cbSizeParamReg2;
1484
1485	/* Source to make DISQueryParamVal read the register value - ugly hack */
1486	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1487	if(VBOX_FAILURE(rc))
1488	return VERR_EM_INTERPRETER;
1489
1490	rc = DISQueryParamRegPtr(pRegFrame, pCpu, &pCpu->param2, (void **)&pParamReg2, &cbSizeParamReg2);
1491	Assert(cbSizeParamReg2 <= 4);
1492	if(VBOX_FAILURE(rc))
1493	return VERR_EM_INTERPRETER;
1494
1495	if (TRPMHasTrap(pVM))
1496	{
1497	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1498	{
1499	RTRCPTR pParam1;
1500	uint32_t eflags;
1501	#ifdef VBOX_STRICT
1502	uint32_t valpar1 = 0; /// @todo used uninitialized...
1503	#endif
1504
1505	AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
1506	switch(param1.type)
1507	{
1508	case PARMTYPE_ADDRESS:
1509	pParam1 = (RTRCPTR)param1.val.val64;
1510	pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);
1511
1512	/* Safety check (in theory it could cross a page boundary and fault there though) */
1513	AssertMsgReturn(pParam1 == (RTRCPTR)pvFault, ("eip=%VGv pParam1=%VRv pvFault=%VGv\n", pRegFrame->rip, pParam1, pvFault), VERR_EM_INTERPRETER);
1514	break;
1515
1516	default:
1517	return VERR_EM_INTERPRETER;
1518	}
1519
1520	LogFlow(("XAdd %VRv=%08x reg=%08x\n", pParam1, *pParamReg2));
1521
1522	MMGCRamRegisterTrapHandler(pVM);
1523	if (pCpu->prefix & PREFIX_LOCK)
1524	rc = EMGCEmulateLockXAdd(pParam1, pParamReg2, cbSizeParamReg2, &eflags);
1525	else
1526	rc = EMGCEmulateXAdd(pParam1, pParamReg2, cbSizeParamReg2, &eflags);
1527	MMGCRamDeregisterTrapHandler(pVM);
1528
1529	if (VBOX_FAILURE(rc))
1530	{
1531	Log(("XAdd %VGv=%08x reg=%08x -> emulation failed due to page fault!\n", pParam1, valpar1, *pParamReg2));
1532	return VERR_EM_INTERPRETER;
1533	}
1534
1535	LogFlow(("XAdd %VGv=%08x reg=%08x ZF=%d\n", pParam1, valpar1, *pParamReg2, !!(eflags & X86_EFL_ZF)));
1536
1537	/* Update guest's eflags and finish. */
1538	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1539	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1540
1541	*pcbSize = cbSizeParamReg2;
1542	return VINF_SUCCESS;
1543	}
1544	}
1545	return VERR_EM_INTERPRETER;
1546	}
1547	#endif
1548
1549	#ifdef IN_GC
1550	/**
1551	* Interpret IRET (currently only to V86 code)
1552	*
1553	* @returns VBox status code.
1554	* @param pVM The VM handle.
1555	* @param pRegFrame The register frame.
1556	*
1557	*/
1558	EMDECL(int) EMInterpretIret(PVM pVM, PCPUMCTXCORE pRegFrame)
1559	{
1560	RTGCUINTPTR pIretStack = (RTGCUINTPTR)pRegFrame->esp;
1561	RTGCUINTPTR eip, cs, esp, ss, eflags, ds, es, fs, gs, uMask;
1562	int rc;
1563
1564	Assert(!CPUMIsGuestIn64BitCode(pVM, pRegFrame));
1565
1566	rc = emRamRead(pVM, &eip, (RTGCPTR)pIretStack , 4);
1567	rc \|= emRamRead(pVM, &cs, (RTGCPTR)(pIretStack + 4), 4);
1568	rc \|= emRamRead(pVM, &eflags, (RTGCPTR)(pIretStack + 8), 4);
1569	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1570	AssertReturn(eflags & X86_EFL_VM, VERR_EM_INTERPRETER);
1571
1572	rc \|= emRamRead(pVM, &esp, (RTGCPTR)(pIretStack + 12), 4);
1573	rc \|= emRamRead(pVM, &ss, (RTGCPTR)(pIretStack + 16), 4);
1574	rc \|= emRamRead(pVM, &es, (RTGCPTR)(pIretStack + 20), 4);
1575	rc \|= emRamRead(pVM, &ds, (RTGCPTR)(pIretStack + 24), 4);
1576	rc \|= emRamRead(pVM, &fs, (RTGCPTR)(pIretStack + 28), 4);
1577	rc \|= emRamRead(pVM, &gs, (RTGCPTR)(pIretStack + 32), 4);
1578	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1579
1580	pRegFrame->eip = eip & 0xffff;
1581	pRegFrame->cs = cs;
1582
1583	/* Mask away all reserved bits */
1584	uMask = X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_RF \| X86_EFL_VM \| X86_EFL_AC \| X86_EFL_VIF \| X86_EFL_VIP \| X86_EFL_ID;
1585	eflags &= uMask;
1586
1587	#ifndef IN_RING0
1588	CPUMRawSetEFlags(pVM, pRegFrame, eflags);
1589	#endif
1590	Assert((pRegFrame->eflags.u32 & (X86_EFL_IF\|X86_EFL_IOPL)) == X86_EFL_IF);
1591
1592	pRegFrame->esp = esp;
1593	pRegFrame->ss = ss;
1594	pRegFrame->ds = ds;
1595	pRegFrame->es = es;
1596	pRegFrame->fs = fs;
1597	pRegFrame->gs = gs;
1598
1599	return VINF_SUCCESS;
1600	}
1601	#endif
1602
1603	/**
1604	* IRET Emulation.
1605	*/
1606	static int emInterpretIret(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1607	{
1608	/* only allow direct calls to EMInterpretIret for now */
1609	return VERR_EM_INTERPRETER;
1610	}
1611
1612	/**
1613	* INVLPG Emulation.
1614	*/
1615
1616	/**
1617	* Interpret INVLPG
1618	*
1619	* @returns VBox status code.
1620	* @param pVM The VM handle.
1621	* @param pRegFrame The register frame.
1622	* @param pAddrGC Operand address
1623	*
1624	*/
1625	EMDECL(int) EMInterpretInvlpg(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC)
1626	{
1627	int rc;
1628
1629	/** @todo is addr always a flat linear address or ds based
1630	* (in absence of segment override prefixes)????
1631	*/
1632	#ifdef IN_GC
1633	// Note: we could also use PGMFlushPage here, but it currently doesn't always use invlpg!!!!!!!!!!
1634	LogFlow(("GC: EMULATE: invlpg %08X\n", pAddrGC));
1635	rc = PGMGCInvalidatePage(pVM, pAddrGC);
1636	#else
1637	rc = PGMInvalidatePage(pVM, pAddrGC);
1638	#endif
1639	if (VBOX_SUCCESS(rc))
1640	return VINF_SUCCESS;
1641	Log(("PGMInvalidatePage %VGv returned %VGv (%d)\n", pAddrGC, rc, rc));
1642	Assert(rc == VERR_REM_FLUSHED_PAGES_OVERFLOW);
1643	/** @todo r=bird: we shouldn't ignore returns codes like this... I'm 99% sure the error is fatal. */
1644	return VERR_EM_INTERPRETER;
1645	}
1646
1647	static int emInterpretInvlPg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1648	{
1649	OP_PARAMVAL param1;
1650	RTGCPTR addr;
1651
1652	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1653	if(VBOX_FAILURE(rc))
1654	return VERR_EM_INTERPRETER;
1655
1656	switch(param1.type)
1657	{
1658	case PARMTYPE_IMMEDIATE:
1659	case PARMTYPE_ADDRESS:
1660	if(!(param1.flags & (PARAM_VAL32\|PARAM_VAL64)))
1661	return VERR_EM_INTERPRETER;
1662	addr = (RTGCPTR)param1.val.val64;
1663	break;
1664
1665	default:
1666	return VERR_EM_INTERPRETER;
1667	}
1668
1669	/** @todo is addr always a flat linear address or ds based
1670	* (in absence of segment override prefixes)????
1671	*/
1672	#ifdef IN_GC
1673	// Note: we could also use PGMFlushPage here, but it currently doesn't always use invlpg!!!!!!!!!!
1674	LogFlow(("GC: EMULATE: invlpg %08X\n", addr));
1675	rc = PGMGCInvalidatePage(pVM, addr);
1676	#else
1677	rc = PGMInvalidatePage(pVM, addr);
1678	#endif
1679	if (VBOX_SUCCESS(rc))
1680	return VINF_SUCCESS;
1681	/** @todo r=bird: we shouldn't ignore returns codes like this... I'm 99% sure the error is fatal. */
1682	return VERR_EM_INTERPRETER;
1683	}
1684
1685	/**
1686	* CPUID Emulation.
1687	*/
1688
1689	/**
1690	* Interpret CPUID given the parameters in the CPU context
1691	*
1692	* @returns VBox status code.
1693	* @param pVM The VM handle.
1694	* @param pRegFrame The register frame.
1695	*
1696	*/
1697	EMDECL(int) EMInterpretCpuId(PVM pVM, PCPUMCTXCORE pRegFrame)
1698	{
1699	uint32_t iLeaf = pRegFrame->eax; NOREF(iLeaf);
1700
1701	/* Note: operates the same in 64 and non-64 bits mode. */
1702	CPUMGetGuestCpuId(pVM, pRegFrame->eax, &pRegFrame->eax, &pRegFrame->ebx, &pRegFrame->ecx, &pRegFrame->edx);
1703	Log(("Emulate: CPUID %x -> %08x %08x %08x %08x\n", iLeaf, pRegFrame->eax, pRegFrame->ebx, pRegFrame->ecx, pRegFrame->edx));
1704	return VINF_SUCCESS;
1705	}
1706
1707	static int emInterpretCpuId(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1708	{
1709	int rc = EMInterpretCpuId(pVM, pRegFrame);
1710	return rc;
1711	}
1712
1713	/**
1714	* MOV CRx Emulation.
1715	*/
1716
1717	/**
1718	* Interpret CRx read
1719	*
1720	* @returns VBox status code.
1721	* @param pVM The VM handle.
1722	* @param pRegFrame The register frame.
1723	* @param DestRegGen General purpose register index (USE_REG_E**))
1724	* @param SrcRegCRx CRx register index (USE_REG_CR*)
1725	*
1726	*/
1727	EMDECL(int) EMInterpretCRxRead(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx)
1728	{
1729	uint64_t val64;
1730
1731	int rc = CPUMGetGuestCRx(pVM, SrcRegCrx, &val64);
1732	AssertMsgRCReturn(rc, ("CPUMGetGuestCRx %d failed\n", SrcRegCrx), VERR_EM_INTERPRETER);
1733
1734	if (CPUMIsGuestIn64BitCode(pVM, pRegFrame))
1735	rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
1736	else
1737	rc = DISWriteReg32(pRegFrame, DestRegGen, val64);
1738
1739	if(VBOX_SUCCESS(rc))
1740	{
1741	LogFlow(("MOV_CR: gen32=%d CR=%d val=%VX64\n", DestRegGen, SrcRegCrx, val64));
1742	return VINF_SUCCESS;
1743	}
1744	return VERR_EM_INTERPRETER;
1745	}
1746
1747
1748	/**
1749	* Interpret LMSW
1750	*
1751	* @returns VBox status code.
1752	* @param pVM The VM handle.
1753	* @param u16Data LMSW source data.
1754	*
1755	*/
1756	EMDECL(int) EMInterpretLMSW(PVM pVM, uint16_t u16Data)
1757	{
1758	uint64_t OldCr0 = CPUMGetGuestCR0(pVM);
1759
1760	/* don't use this path to go into protected mode! */
1761	Assert(OldCr0 & X86_CR0_PE);
1762	if (!(OldCr0 & X86_CR0_PE))
1763	return VERR_EM_INTERPRETER;
1764
1765	/* Only PE, MP, EM and TS can be changed; note that PE can't be cleared by this instruction. */
1766	uint64_t NewCr0 = ( OldCr0 & ~( X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
1767	\| (u16Data & (X86_CR0_PE \| X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS));
1768
1769	#ifdef IN_GC
1770	/* Need to change the hyper CR0? Doing it the lazy way then. */
1771	if ( (OldCr0 & (X86_CR0_AM \| X86_CR0_WP))
1772	!= (NewCr0 & (X86_CR0_AM \| X86_CR0_WP)))
1773	{
1774	Log(("EMInterpretLMSW: CR0: %#x->%#x => R3\n", OldCr0, NewCr0));
1775	VM_FF_SET(pVM, VM_FF_TO_R3);
1776	}
1777	#endif
1778
1779	return CPUMSetGuestCR0(pVM, NewCr0);
1780	}
1781
1782
1783	/**
1784	* Interpret CLTS
1785	*
1786	* @returns VBox status code.
1787	* @param pVM The VM handle.
1788	*
1789	*/
1790	EMDECL(int) EMInterpretCLTS(PVM pVM)
1791	{
1792	uint64_t cr0 = CPUMGetGuestCR0(pVM);
1793	if (!(cr0 & X86_CR0_TS))
1794	return VINF_SUCCESS;
1795	return CPUMSetGuestCR0(pVM, cr0 & ~X86_CR0_TS);
1796	}
1797
1798	static int emInterpretClts(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1799	{
1800	return EMInterpretCLTS(pVM);
1801	}
1802
1803	/**
1804	* Interpret CRx write
1805	*
1806	* @returns VBox status code.
1807	* @param pVM The VM handle.
1808	* @param pRegFrame The register frame.
1809	* @param DestRegCRx CRx register index (USE_REG_CR*)
1810	* @param SrcRegGen General purpose register index (USE_REG_E**))
1811	*
1812	*/
1813	EMDECL(int) EMInterpretCRxWrite(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint32_t SrcRegGen)
1814	{
1815	uint64_t val;
1816	uint64_t oldval;
1817	uint64_t msrEFER;
1818	int rc;
1819
1820	/** @todo Clean up this mess. */
1821	if (CPUMIsGuestIn64BitCode(pVM, pRegFrame))
1822	{
1823	rc = DISFetchReg64(pRegFrame, SrcRegGen, &val);
1824	}
1825	else
1826	{
1827	uint32_t val32;
1828	rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
1829	val = val32;
1830	}
1831
1832	if (VBOX_SUCCESS(rc))
1833	{
1834	switch (DestRegCrx)
1835	{
1836	case USE_REG_CR0:
1837	oldval = CPUMGetGuestCR0(pVM);
1838	#ifdef IN_GC
1839	/* CR0.WP and CR0.AM changes require a reschedule run in ring 3. */
1840	if ( (val & (X86_CR0_WP \| X86_CR0_AM))
1841	!= (oldval & (X86_CR0_WP \| X86_CR0_AM)))
1842	return VERR_EM_INTERPRETER;
1843	#endif
1844	CPUMSetGuestCR0(pVM, val);
1845	val = CPUMGetGuestCR0(pVM);
1846	if ( (oldval & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE))
1847	!= (val & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE)))
1848	{
1849	/* global flush */
1850	rc = PGMFlushTLB(pVM, CPUMGetGuestCR3(pVM), true /* global */);
1851	AssertRCReturn(rc, rc);
1852	}
1853
1854	/* Deal with long mode enabling/disabling. */
1855	msrEFER = CPUMGetGuestEFER(pVM);
1856	if (msrEFER & MSR_K6_EFER_LME)
1857	{
1858	if ( !(oldval & X86_CR0_PG)
1859	&& (val & X86_CR0_PG))
1860	{
1861	/* Illegal to have an active 64 bits CS selector (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1862	if (pRegFrame->csHid.Attr.n.u1Long)
1863	{
1864	AssertMsgFailed(("Illegal enabling of paging with CS.u1Long = 1!!\n"));
1865	return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
1866	}
1867
1868	/* Illegal to switch to long mode before activating PAE first (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1869	if (!(CPUMGetGuestCR4(pVM) & X86_CR4_PAE))
1870	{
1871	AssertMsgFailed(("Illegal enabling of paging with PAE disabled!!\n"));
1872	return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
1873	}
1874
1875	msrEFER \|= MSR_K6_EFER_LMA;
1876	}
1877	else
1878	if ( (oldval & X86_CR0_PG)
1879	&& !(val & X86_CR0_PG))
1880	{
1881	msrEFER &= ~MSR_K6_EFER_LMA;
1882	/* @todo Do we need to cut off rip here? High dword of rip is undefined, so it shouldn't really matter. */
1883	}
1884	CPUMSetGuestEFER(pVM, msrEFER);
1885	}
1886	return PGMChangeMode(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR4(pVM), CPUMGetGuestEFER(pVM));
1887
1888	case USE_REG_CR2:
1889	rc = CPUMSetGuestCR2(pVM, val); AssertRC(rc);
1890	return VINF_SUCCESS;
1891
1892	case USE_REG_CR3:
1893	/* Reloading the current CR3 means the guest just wants to flush the TLBs */
1894	rc = CPUMSetGuestCR3(pVM, val); AssertRC(rc);
1895	if (CPUMGetGuestCR0(pVM) & X86_CR0_PG)
1896	{
1897	/* flush */
1898	rc = PGMFlushTLB(pVM, val, !(CPUMGetGuestCR4(pVM) & X86_CR4_PGE));
1899	AssertRCReturn(rc, rc);
1900	}
1901	return VINF_SUCCESS;
1902
1903	case USE_REG_CR4:
1904	oldval = CPUMGetGuestCR4(pVM);
1905	rc = CPUMSetGuestCR4(pVM, val); AssertRC(rc);
1906	val = CPUMGetGuestCR4(pVM);
1907
1908	msrEFER = CPUMGetGuestEFER(pVM);
1909	/* Illegal to disable PAE when long mode is active. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1910	if ( (msrEFER & MSR_K6_EFER_LMA)
1911	&& (oldval & X86_CR4_PAE)
1912	&& !(val & X86_CR4_PAE))
1913	{
1914	return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
1915	}
1916
1917	if ( (oldval & (X86_CR4_PGE\|X86_CR4_PAE\|X86_CR4_PSE))
1918	!= (val & (X86_CR4_PGE\|X86_CR4_PAE\|X86_CR4_PSE)))
1919	{
1920	/* global flush */
1921	rc = PGMFlushTLB(pVM, CPUMGetGuestCR3(pVM), true /* global */);
1922	AssertRCReturn(rc, rc);
1923	}
1924	# ifdef IN_GC
1925	/* Feeling extremely lazy. */
1926	if ( (oldval & (X86_CR4_OSFSXR\|X86_CR4_OSXMMEEXCPT\|X86_CR4_PCE\|X86_CR4_MCE\|X86_CR4_PAE\|X86_CR4_DE\|X86_CR4_TSD\|X86_CR4_PVI\|X86_CR4_VME))
1927	!= (val & (X86_CR4_OSFSXR\|X86_CR4_OSXMMEEXCPT\|X86_CR4_PCE\|X86_CR4_MCE\|X86_CR4_PAE\|X86_CR4_DE\|X86_CR4_TSD\|X86_CR4_PVI\|X86_CR4_VME)))
1928	{
1929	Log(("emInterpretMovCRx: CR4: %#RX64->%#RX64 => R3\n", oldval, val));
1930	VM_FF_SET(pVM, VM_FF_TO_R3);
1931	}
1932	# endif
1933	return PGMChangeMode(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR4(pVM), CPUMGetGuestEFER(pVM));
1934
1935	case USE_REG_CR8:
1936	return PDMApicSetTPR(pVM, val);
1937
1938	default:
1939	AssertFailed();
1940	case USE_REG_CR1: /* illegal op */
1941	break;
1942	}
1943	}
1944	return VERR_EM_INTERPRETER;
1945	}
1946
1947	static int emInterpretMovCRx(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1948	{
1949	if ((pCpu->param1.flags == USE_REG_GEN32 \|\| pCpu->param1.flags == USE_REG_GEN64) && pCpu->param2.flags == USE_REG_CR)
1950	return EMInterpretCRxRead(pVM, pRegFrame, pCpu->param1.base.reg_gen, pCpu->param2.base.reg_ctrl);
1951
1952	if (pCpu->param1.flags == USE_REG_CR && (pCpu->param2.flags == USE_REG_GEN32 \|\| pCpu->param2.flags == USE_REG_GEN64))
1953	return EMInterpretCRxWrite(pVM, pRegFrame, pCpu->param1.base.reg_ctrl, pCpu->param2.base.reg_gen);
1954
1955	AssertMsgFailedReturn(("Unexpected control register move\n"), VERR_EM_INTERPRETER);
1956	return VERR_EM_INTERPRETER;
1957	}
1958
1959	/**
1960	* MOV DRx
1961	*/
1962
1963	/**
1964	* Interpret DRx write
1965	*
1966	* @returns VBox status code.
1967	* @param pVM The VM handle.
1968	* @param pRegFrame The register frame.
1969	* @param DestRegDRx DRx register index (USE_REG_DR*)
1970	* @param SrcRegGen General purpose register index (USE_REG_E**))
1971	*
1972	*/
1973	EMDECL(int) EMInterpretDRxWrite(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen)
1974	{
1975	uint64_t val;
1976	int rc;
1977
1978	if (CPUMIsGuestIn64BitCode(pVM, pRegFrame))
1979	{
1980	rc = DISFetchReg64(pRegFrame, SrcRegGen, &val);
1981	}
1982	else
1983	{
1984	uint32_t val32;
1985	rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
1986	val = val32;
1987	}
1988
1989	if (VBOX_SUCCESS(rc))
1990	{
1991	rc = CPUMSetGuestDRx(pVM, DestRegDrx, val);
1992	if (VBOX_SUCCESS(rc))
1993	return rc;
1994	AssertMsgFailed(("CPUMSetGuestDRx %d failed\n", DestRegDrx));
1995	}
1996	return VERR_EM_INTERPRETER;
1997	}
1998
1999	/**
2000	* Interpret DRx read
2001	*
2002	* @returns VBox status code.
2003	* @param pVM The VM handle.
2004	* @param pRegFrame The register frame.
2005	* @param DestRegGen General purpose register index (USE_REG_E**))
2006	* @param SrcRegDRx DRx register index (USE_REG_DR*)
2007	*
2008	*/
2009	EMDECL(int) EMInterpretDRxRead(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx)
2010	{
2011	uint64_t val64;
2012
2013	int rc = CPUMGetGuestDRx(pVM, SrcRegDrx, &val64);
2014	AssertMsgRCReturn(rc, ("CPUMGetGuestDRx %d failed\n", SrcRegDrx), VERR_EM_INTERPRETER);
2015	if (CPUMIsGuestIn64BitCode(pVM, pRegFrame))
2016	{
2017	rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
2018	}
2019	else
2020	rc = DISWriteReg32(pRegFrame, DestRegGen, (uint32_t)val64);
2021
2022	if (VBOX_SUCCESS(rc))
2023	return VINF_SUCCESS;
2024
2025	return VERR_EM_INTERPRETER;
2026	}
2027
2028	static int emInterpretMovDRx(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2029	{
2030	int rc = VERR_EM_INTERPRETER;
2031
2032	if((pCpu->param1.flags == USE_REG_GEN32 \|\| pCpu->param1.flags == USE_REG_GEN64) && pCpu->param2.flags == USE_REG_DBG)
2033	{
2034	rc = EMInterpretDRxRead(pVM, pRegFrame, pCpu->param1.base.reg_gen, pCpu->param2.base.reg_dbg);
2035	}
2036	else
2037	if(pCpu->param1.flags == USE_REG_DBG && (pCpu->param2.flags == USE_REG_GEN32 \|\| pCpu->param2.flags == USE_REG_GEN64))
2038	{
2039	rc = EMInterpretDRxWrite(pVM, pRegFrame, pCpu->param1.base.reg_dbg, pCpu->param2.base.reg_gen);
2040	}
2041	else
2042	AssertMsgFailed(("Unexpected debug register move\n"));
2043
2044	return rc;
2045	}
2046
2047	/**
2048	* LLDT Emulation.
2049	*/
2050	static int emInterpretLLdt(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2051	{
2052	OP_PARAMVAL param1;
2053	RTSEL sel;
2054
2055	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
2056	if(VBOX_FAILURE(rc))
2057	return VERR_EM_INTERPRETER;
2058
2059	switch(param1.type)
2060	{
2061	case PARMTYPE_ADDRESS:
2062	return VERR_EM_INTERPRETER; //feeling lazy right now
2063
2064	case PARMTYPE_IMMEDIATE:
2065	if(!(param1.flags & PARAM_VAL16))
2066	return VERR_EM_INTERPRETER;
2067	sel = (RTSEL)param1.val.val16;
2068	break;
2069
2070	default:
2071	return VERR_EM_INTERPRETER;
2072	}
2073
2074	if (sel == 0)
2075	{
2076	if (CPUMGetHyperLDTR(pVM) == 0)
2077	{
2078	// this simple case is most frequent in Windows 2000 (31k - boot & shutdown)
2079	return VINF_SUCCESS;
2080	}
2081	}
2082	//still feeling lazy
2083	return VERR_EM_INTERPRETER;
2084	}
2085
2086	#ifdef IN_GC
2087	/**
2088	* STI Emulation.
2089	*
2090	* @remark the instruction following sti is guaranteed to be executed before any interrupts are dispatched
2091	*/
2092	static int emInterpretSti(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2093	{
2094	PPATMGCSTATE pGCState = PATMQueryGCState(pVM);
2095
2096	if(!pGCState)
2097	{
2098	Assert(pGCState);
2099	return VERR_EM_INTERPRETER;
2100	}
2101	pGCState->uVMFlags \|= X86_EFL_IF;
2102
2103	Assert(pRegFrame->eflags.u32 & X86_EFL_IF);
2104	Assert(pvFault == SELMToFlat(pVM, DIS_SELREG_CS, pRegFrame, (RTGCPTR)pRegFrame->rip));
2105
2106	pVM->em.s.GCPtrInhibitInterrupts = pRegFrame->eip + pCpu->opsize;
2107	VM_FF_SET(pVM, VM_FF_INHIBIT_INTERRUPTS);
2108
2109	return VINF_SUCCESS;
2110	}
2111	#endif /* IN_GC */
2112
2113
2114	/**
2115	* HLT Emulation.
2116	*/
2117	static int emInterpretHlt(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2118	{
2119	return VINF_EM_HALT;
2120	}
2121
2122
2123	/**
2124	* RDTSC Emulation.
2125	*/
2126
2127	/**
2128	* Interpret RDTSC
2129	*
2130	* @returns VBox status code.
2131	* @param pVM The VM handle.
2132	* @param pRegFrame The register frame.
2133	*
2134	*/
2135	EMDECL(int) EMInterpretRdtsc(PVM pVM, PCPUMCTXCORE pRegFrame)
2136	{
2137	unsigned uCR4 = CPUMGetGuestCR4(pVM);
2138
2139	if (uCR4 & X86_CR4_TSD)
2140	return VERR_EM_INTERPRETER; /* genuine #GP */
2141
2142	uint64_t uTicks = TMCpuTickGet(pVM);
2143
2144	/* Same behaviour in 32 & 64 bits mode */
2145	pRegFrame->eax = uTicks;
2146	pRegFrame->edx = (uTicks >> 32ULL);
2147
2148	return VINF_SUCCESS;
2149	}
2150
2151	static int emInterpretRdtsc(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2152	{
2153	return EMInterpretRdtsc(pVM, pRegFrame);
2154	}
2155
2156	/**
2157	* MONITOR Emulation.
2158	*/
2159	static int emInterpretMonitor(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2160	{
2161	uint32_t u32Dummy, u32ExtFeatures, cpl;
2162
2163	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
2164	if (pRegFrame->ecx != 0)
2165	return VERR_EM_INTERPRETER; /* illegal value. */
2166
2167	/* Get the current privilege level. */
2168	cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2169	if (cpl != 0)
2170	return VERR_EM_INTERPRETER; /* supervisor only */
2171
2172	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
2173	if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
2174	return VERR_EM_INTERPRETER; /* not supported */
2175
2176	return VINF_SUCCESS;
2177	}
2178
2179
2180	/**
2181	* MWAIT Emulation.
2182	*/
2183	static int emInterpretMWait(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2184	{
2185	uint32_t u32Dummy, u32ExtFeatures, cpl;
2186
2187	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
2188	if (pRegFrame->ecx != 0)
2189	return VERR_EM_INTERPRETER; /* illegal value. */
2190
2191	/* Get the current privilege level. */
2192	cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2193	if (cpl != 0)
2194	return VERR_EM_INTERPRETER; /* supervisor only */
2195
2196	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
2197	if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
2198	return VERR_EM_INTERPRETER; /* not supported */
2199
2200	/** @todo not completely correct */
2201	return VINF_EM_HALT;
2202	}
2203
2204	#ifdef LOG_ENABLED
2205	static const char *emMSRtoString(unsigned uMsr)
2206	{
2207	switch(uMsr)
2208	{
2209	case MSR_IA32_APICBASE:
2210	return "MSR_IA32_APICBASE";
2211	case MSR_IA32_CR_PAT:
2212	return "MSR_IA32_CR_PAT";
2213	case MSR_IA32_SYSENTER_CS:
2214	return "MSR_IA32_SYSENTER_CS";
2215	case MSR_IA32_SYSENTER_EIP:
2216	return "MSR_IA32_SYSENTER_EIP";
2217	case MSR_IA32_SYSENTER_ESP:
2218	return "MSR_IA32_SYSENTER_ESP";
2219	case MSR_K6_EFER:
2220	return "MSR_K6_EFER";
2221	case MSR_K8_SF_MASK:
2222	return "MSR_K8_SF_MASK";
2223	case MSR_K6_STAR:
2224	return "MSR_K6_STAR";
2225	case MSR_K8_LSTAR:
2226	return "MSR_K8_LSTAR";
2227	case MSR_K8_CSTAR:
2228	return "MSR_K8_CSTAR";
2229	case MSR_K8_FS_BASE:
2230	return "MSR_K8_FS_BASE";
2231	case MSR_K8_GS_BASE:
2232	return "MSR_K8_GS_BASE";
2233	case MSR_K8_KERNEL_GS_BASE:
2234	return "MSR_K8_KERNEL_GS_BASE";
2235	case MSR_IA32_TSC:
2236	return "Unsupported MSR_IA32_TSC";
2237	case MSR_IA32_MTRR_CAP:
2238	return "Unsupported MSR_IA32_MTRR_CAP";
2239	case MSR_IA32_MCP_CAP:
2240	return "Unsupported MSR_IA32_MCP_CAP";
2241	case MSR_IA32_MCP_STATUS:
2242	return "Unsupported MSR_IA32_MCP_STATUS";
2243	case MSR_IA32_MCP_CTRL:
2244	return "Unsupported MSR_IA32_MCP_CTRL";
2245	case MSR_IA32_MTRR_DEF_TYPE:
2246	return "Unsupported MSR_IA32_MTRR_DEF_TYPE";
2247	case MSR_K7_EVNTSEL0:
2248	return "Unsupported MSR_K7_EVNTSEL0";
2249	case MSR_K7_EVNTSEL1:
2250	return "Unsupported MSR_K7_EVNTSEL1";
2251	case MSR_K7_EVNTSEL2:
2252	return "Unsupported MSR_K7_EVNTSEL2";
2253	case MSR_K7_EVNTSEL3:
2254	return "Unsupported MSR_K7_EVNTSEL3";
2255	}
2256	return "Unknown MSR";
2257	}
2258	#endif
2259
2260	/**
2261	* Interpret RDMSR
2262	*
2263	* @returns VBox status code.
2264	* @param pVM The VM handle.
2265	* @param pRegFrame The register frame.
2266	*
2267	*/
2268	EMDECL(int) EMInterpretRdmsr(PVM pVM, PCPUMCTXCORE pRegFrame)
2269	{
2270	uint32_t u32Dummy, u32Features, cpl;
2271	uint64_t val;
2272	CPUMCTX *pCtx;
2273	int rc;
2274
2275	/** @todo According to the Intel manuals, there's a REX version of RDMSR that is slightly different.
2276	* That version clears the high dwords of both RDX & RAX */
2277	rc = CPUMQueryGuestCtxPtr(pVM, &pCtx);
2278	AssertRC(rc);
2279
2280	/* Get the current privilege level. */
2281	cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2282	if (cpl != 0)
2283	return VERR_EM_INTERPRETER; /* supervisor only */
2284
2285	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2286	if (!(u32Features & X86_CPUID_FEATURE_EDX_MSR))
2287	return VERR_EM_INTERPRETER; /* not supported */
2288
2289	switch (pRegFrame->ecx)
2290	{
2291	case MSR_IA32_APICBASE:
2292	rc = PDMApicGetBase(pVM, &val);
2293	AssertRC(rc);
2294	break;
2295
2296	case MSR_IA32_CR_PAT:
2297	val = pCtx->msrPAT;
2298	break;
2299
2300	case MSR_IA32_SYSENTER_CS:
2301	val = pCtx->SysEnter.cs;
2302	break;
2303
2304	case MSR_IA32_SYSENTER_EIP:
2305	val = pCtx->SysEnter.eip;
2306	break;
2307
2308	case MSR_IA32_SYSENTER_ESP:
2309	val = pCtx->SysEnter.esp;
2310	break;
2311
2312	case MSR_K6_EFER:
2313	val = pCtx->msrEFER;
2314	break;
2315
2316	case MSR_K8_SF_MASK:
2317	val = pCtx->msrSFMASK;
2318	break;
2319
2320	case MSR_K6_STAR:
2321	val = pCtx->msrSTAR;
2322	break;
2323
2324	case MSR_K8_LSTAR:
2325	val = pCtx->msrLSTAR;
2326	break;
2327
2328	case MSR_K8_CSTAR:
2329	val = pCtx->msrCSTAR;
2330	break;
2331
2332	case MSR_K8_FS_BASE:
2333	val = pCtx->fsHid.u64Base;
2334	break;
2335
2336	case MSR_K8_GS_BASE:
2337	val = pCtx->gsHid.u64Base;
2338	break;
2339
2340	case MSR_K8_KERNEL_GS_BASE:
2341	val = pCtx->msrKERNELGSBASE;
2342	break;
2343
2344	default:
2345	/* We should actually trigger a #GP here, but don't as that might cause more trouble. */
2346	val = 0;
2347	break;
2348	}
2349	Log(("EMInterpretRdmsr %s (%x) -> val=%VX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx, val));
2350	pRegFrame->eax = (uint32_t) val;
2351	pRegFrame->edx = (uint32_t) (val >> 32ULL);
2352	return VINF_SUCCESS;
2353	}
2354
2355	/**
2356	* RDMSR Emulation.
2357	*/
2358	static int emInterpretRdmsr(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2359	{
2360	/* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
2361	Assert(!(pCpu->prefix & PREFIX_REX));
2362	return EMInterpretRdmsr(pVM, pRegFrame);
2363	}
2364
2365	/**
2366	* Interpret WRMSR
2367	*
2368	* @returns VBox status code.
2369	* @param pVM The VM handle.
2370	* @param pRegFrame The register frame.
2371	*
2372	*/
2373	EMDECL(int) EMInterpretWrmsr(PVM pVM, PCPUMCTXCORE pRegFrame)
2374	{
2375	uint32_t u32Dummy, u32Features, cpl;
2376	uint64_t val;
2377	CPUMCTX *pCtx;
2378	int rc;
2379
2380	/* Note: works the same in 32 and 64 bits modes. */
2381	rc = CPUMQueryGuestCtxPtr(pVM, &pCtx);
2382	AssertRC(rc);
2383
2384	/* Get the current privilege level. */
2385	cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2386	if (cpl != 0)
2387	return VERR_EM_INTERPRETER; /* supervisor only */
2388
2389	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2390	if (!(u32Features & X86_CPUID_FEATURE_EDX_MSR))
2391	return VERR_EM_INTERPRETER; /* not supported */
2392
2393	val = (uint64_t)pRegFrame->eax \| ((uint64_t)pRegFrame->edx << 32ULL);
2394	Log(("EMInterpretWrmsr %s (%x) val=%VX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx, val));
2395	switch (pRegFrame->ecx)
2396	{
2397	case MSR_IA32_APICBASE:
2398	rc = PDMApicSetBase(pVM, val);
2399	AssertRC(rc);
2400	break;
2401
2402	case MSR_IA32_CR_PAT:
2403	pCtx->msrPAT = val;
2404	break;
2405
2406	case MSR_IA32_SYSENTER_CS:
2407	pCtx->SysEnter.cs = val;
2408	break;
2409
2410	case MSR_IA32_SYSENTER_EIP:
2411	pCtx->SysEnter.eip = val;
2412	break;
2413
2414	case MSR_IA32_SYSENTER_ESP:
2415	pCtx->SysEnter.esp = val;
2416	break;
2417
2418	case MSR_K6_EFER:
2419	{
2420	uint64_t uMask = 0;
2421	uint64_t oldval = pCtx->msrEFER;
2422
2423	/* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
2424	CPUMGetGuestCpuId(pVM, 0x80000001, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2425	if (u32Features & X86_CPUID_AMD_FEATURE_EDX_NX)
2426	uMask \|= MSR_K6_EFER_NXE;
2427	if (u32Features & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE)
2428	uMask \|= MSR_K6_EFER_LME;
2429	if (u32Features & X86_CPUID_AMD_FEATURE_EDX_SEP)
2430	uMask \|= MSR_K6_EFER_SCE;
2431	if (u32Features & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
2432	uMask \|= MSR_K6_EFER_FFXSR;
2433
2434	/* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
2435	if ( ((pCtx->msrEFER & MSR_K6_EFER_LME) != (val & uMask & MSR_K6_EFER_LME))
2436	&& (pCtx->cr0 & X86_CR0_PG))
2437	{
2438	AssertMsgFailed(("Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
2439	return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
2440	}
2441
2442	/* There are a few more: e.g. MSR_K6_EFER_LMSLE */
2443	AssertMsg(!(val & ~(MSR_K6_EFER_NXE\|MSR_K6_EFER_LME\|MSR_K6_EFER_LMA /* ignored anyway */ \|MSR_K6_EFER_SCE\|MSR_K6_EFER_FFXSR)), ("Unexpected value %RX64\n", val));
2444	pCtx->msrEFER = (pCtx->msrEFER & ~uMask) \| (val & uMask);
2445
2446	/* AMD64 Achitecture Programmer's Manual: 15.15 TLB Control; flush the TLB if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
2447	if ((oldval & (MSR_K6_EFER_NXE\|MSR_K6_EFER_LME\|MSR_K6_EFER_LMA)) != (pCtx->msrEFER & (MSR_K6_EFER_NXE\|MSR_K6_EFER_LME\|MSR_K6_EFER_LMA)))
2448	HWACCMFlushTLB(pVM);
2449
2450	break;
2451	}
2452
2453	case MSR_K8_SF_MASK:
2454	pCtx->msrSFMASK = val;
2455	break;
2456
2457	case MSR_K6_STAR:
2458	pCtx->msrSTAR = val;
2459	break;
2460
2461	case MSR_K8_LSTAR:
2462	pCtx->msrLSTAR = val;
2463	break;
2464
2465	case MSR_K8_CSTAR:
2466	pCtx->msrCSTAR = val;
2467	break;
2468
2469	case MSR_K8_FS_BASE:
2470	pCtx->fsHid.u64Base = val;
2471	break;
2472
2473	case MSR_K8_GS_BASE:
2474	pCtx->gsHid.u64Base = val;
2475	break;
2476
2477	case MSR_K8_KERNEL_GS_BASE:
2478	pCtx->msrKERNELGSBASE = val;
2479	break;
2480
2481	default:
2482	/* We should actually trigger a #GP here, but don't as that might cause more trouble. */
2483	break;
2484	}
2485	return VINF_SUCCESS;
2486	}
2487
2488	/**
2489	* WRMSR Emulation.
2490	*/
2491	static int emInterpretWrmsr(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2492	{
2493	return EMInterpretWrmsr(pVM, pRegFrame);
2494	}
2495
2496	/**
2497	* Internal worker.
2498	* @copydoc EMInterpretInstructionCPU
2499	*/
2500	DECLINLINE(int) emInterpretInstructionCPU(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2501	{
2502	Assert(pcbSize);
2503	*pcbSize = 0;
2504
2505	/*
2506	* Only supervisor guest code!!
2507	* And no complicated prefixes.
2508	*/
2509	/* Get the current privilege level. */
2510	uint32_t cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2511	if ( cpl != 0
2512	&& pCpu->pCurInstr->opcode != OP_RDTSC) /* rdtsc requires emulation in ring 3 as well */
2513	{
2514	Log(("WARNING: refusing instruction emulation for user-mode code!!\n"));
2515	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,FailedUserMode));
2516	return VERR_EM_INTERPRETER;
2517	}
2518
2519	#ifdef IN_GC
2520	if ( (pCpu->prefix & (PREFIX_REPNE \| PREFIX_REP))
2521	\|\| ( (pCpu->prefix & PREFIX_LOCK)
2522	&& pCpu->pCurInstr->opcode != OP_CMPXCHG
2523	&& pCpu->pCurInstr->opcode != OP_CMPXCHG8B
2524	&& pCpu->pCurInstr->opcode != OP_XADD
2525	&& pCpu->pCurInstr->opcode != OP_OR
2526	&& pCpu->pCurInstr->opcode != OP_BTR
2527	)
2528	)
2529	#else
2530	if ( (pCpu->prefix & (PREFIX_REPNE \| PREFIX_REP))
2531	\|\| ( (pCpu->prefix & PREFIX_LOCK)
2532	&& pCpu->pCurInstr->opcode != OP_OR
2533	&& pCpu->pCurInstr->opcode != OP_BTR
2534	)
2535	)
2536	#endif
2537	{
2538	//Log(("EMInterpretInstruction: wrong prefix!!\n"));
2539	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,FailedPrefix));
2540	return VERR_EM_INTERPRETER;
2541	}
2542
2543	int rc;
2544	#if (defined(VBOX_STRICT) \|\| defined(LOG_ENABLED))
2545	LogFlow(("emInterpretInstructionCPU %s\n", emGetMnemonic(pCpu)));
2546	#endif
2547	switch (pCpu->pCurInstr->opcode)
2548	{
2549	# define INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
2550	case opcode:\
2551	if (pCpu->prefix & PREFIX_LOCK) \
2552	rc = emInterpretLock##InstrFn(pVM, pCpu, pRegFrame, pvFault, pcbSize, pfnEmulateLock); \
2553	else \
2554	rc = emInterpret##InstrFn(pVM, pCpu, pRegFrame, pvFault, pcbSize, pfnEmulate); \
2555	if (VBOX_SUCCESS(rc)) \
2556	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,Instr)); \
2557	else \
2558	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,Failed##Instr)); \
2559	return rc
2560	#define INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate) \
2561	case opcode:\
2562	rc = emInterpret##InstrFn(pVM, pCpu, pRegFrame, pvFault, pcbSize, pfnEmulate); \
2563	if (VBOX_SUCCESS(rc)) \
2564	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,Instr)); \
2565	else \
2566	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,Failed##Instr)); \
2567	return rc
2568
2569	#define INTERPRET_CASE_EX_PARAM2(opcode, Instr, InstrFn, pfnEmulate) \
2570	INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate)
2571	#define INTERPRET_CASE_EX_LOCK_PARAM2(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
2572	INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock)
2573
2574	#define INTERPRET_CASE(opcode, Instr) \
2575	case opcode:\
2576	rc = emInterpret##Instr(pVM, pCpu, pRegFrame, pvFault, pcbSize); \
2577	if (VBOX_SUCCESS(rc)) \
2578	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,Instr)); \
2579	else \
2580	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,Failed##Instr)); \
2581	return rc
2582	#define INTERPRET_STAT_CASE(opcode, Instr) \
2583	case opcode: STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,Failed##Instr)); return VERR_EM_INTERPRETER;
2584
2585	INTERPRET_CASE(OP_XCHG,Xchg);
2586	INTERPRET_CASE_EX_PARAM2(OP_DEC,Dec, IncDec, EMEmulateDec);
2587	INTERPRET_CASE_EX_PARAM2(OP_INC,Inc, IncDec, EMEmulateInc);
2588	INTERPRET_CASE(OP_POP,Pop);
2589	INTERPRET_CASE_EX_LOCK_PARAM3(OP_OR, Or, OrXorAnd, EMEmulateOr, EMEmulateLockOr);
2590	INTERPRET_CASE_EX_PARAM3(OP_XOR,Xor, OrXorAnd, EMEmulateXor);
2591	INTERPRET_CASE_EX_PARAM3(OP_AND,And, OrXorAnd, EMEmulateAnd);
2592	INTERPRET_CASE(OP_MOV,Mov);
2593	INTERPRET_CASE(OP_INVLPG,InvlPg);
2594	INTERPRET_CASE(OP_CPUID,CpuId);
2595	INTERPRET_CASE(OP_MOV_CR,MovCRx);
2596	INTERPRET_CASE(OP_MOV_DR,MovDRx);
2597	INTERPRET_CASE(OP_LLDT,LLdt);
2598	INTERPRET_CASE(OP_CLTS,Clts);
2599	INTERPRET_CASE(OP_MONITOR, Monitor);
2600	INTERPRET_CASE(OP_MWAIT, MWait);
2601	INTERPRET_CASE(OP_RDMSR, Rdmsr);
2602	INTERPRET_CASE(OP_WRMSR, Wrmsr);
2603	INTERPRET_CASE_EX_PARAM3(OP_ADD,Add, AddSub, EMEmulateAdd);
2604	INTERPRET_CASE_EX_PARAM3(OP_SUB,Sub, AddSub, EMEmulateSub);
2605	INTERPRET_CASE(OP_ADC,Adc);
2606	INTERPRET_CASE_EX_LOCK_PARAM2(OP_BTR,Btr, BitTest, EMEmulateBtr, EMEmulateLockBtr);
2607	INTERPRET_CASE_EX_PARAM2(OP_BTS,Bts, BitTest, EMEmulateBts);
2608	INTERPRET_CASE_EX_PARAM2(OP_BTC,Btc, BitTest, EMEmulateBtc);
2609	INTERPRET_CASE(OP_RDTSC,Rdtsc);
2610	#ifdef IN_GC
2611	INTERPRET_CASE(OP_STI,Sti);
2612	INTERPRET_CASE(OP_CMPXCHG, CmpXchg);
2613	INTERPRET_CASE(OP_CMPXCHG8B, CmpXchg8b);
2614	INTERPRET_CASE(OP_XADD, XAdd);
2615	#endif
2616	INTERPRET_CASE(OP_HLT,Hlt);
2617	INTERPRET_CASE(OP_IRET,Iret);
2618	#ifdef VBOX_WITH_STATISTICS
2619	#ifndef IN_GC
2620	INTERPRET_STAT_CASE(OP_CMPXCHG,CmpXchg);
2621	INTERPRET_STAT_CASE(OP_CMPXCHG8B, CmpXchg8b);
2622	INTERPRET_STAT_CASE(OP_XADD, XAdd);
2623	#endif
2624	INTERPRET_STAT_CASE(OP_MOVNTPS,MovNTPS);
2625	INTERPRET_STAT_CASE(OP_STOSWD,StosWD);
2626	INTERPRET_STAT_CASE(OP_WBINVD,WbInvd);
2627	#endif
2628	default:
2629	Log3(("emInterpretInstructionCPU: opcode=%d\n", pCpu->pCurInstr->opcode));
2630	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,FailedMisc));
2631	return VERR_EM_INTERPRETER;
2632	#undef INTERPRET_CASE_EX_PARAM2
2633	#undef INTERPRET_STAT_CASE
2634	#undef INTERPRET_CASE_EX
2635	#undef INTERPRET_CASE
2636	}
2637	AssertFailed();
2638	return VERR_INTERNAL_ERROR;
2639	}
2640
2641
2642	/**
2643	* Sets the PC for which interrupts should be inhibited.
2644	*
2645	* @param pVM The VM handle.
2646	* @param PC The PC.
2647	*/
2648	EMDECL(void) EMSetInhibitInterruptsPC(PVM pVM, RTGCUINTPTR PC)
2649	{
2650	pVM->em.s.GCPtrInhibitInterrupts = PC;
2651	VM_FF_SET(pVM, VM_FF_INHIBIT_INTERRUPTS);
2652	}
2653
2654
2655	/**
2656	* Gets the PC for which interrupts should be inhibited.
2657	*
2658	* There are a few instructions which inhibits or delays interrupts
2659	* for the instruction following them. These instructions are:
2660	* - STI
2661	* - MOV SS, r/m16
2662	* - POP SS
2663	*
2664	* @returns The PC for which interrupts should be inhibited.
2665	* @param pVM VM handle.
2666	*
2667	*/
2668	EMDECL(RTGCUINTPTR) EMGetInhibitInterruptsPC(PVM pVM)
2669	{
2670	return pVM->em.s.GCPtrInhibitInterrupts;
2671	}

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source: vbox/trunk/src/VBox/VMM/VMMAll/EMAll.cpp@ 10274

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