EMAll.cpp@ 11450

Last change on this file since 11450 was 11450, checked in by vboxsync, 17 years ago
Access verfication for stoswd emulation.
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File size: 92.7 KB

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1	/* $Id: EMAll.cpp 11450 2008-08-17 17:34:52Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor(/Manager) - All contexts
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_EM
26	#include <VBox/em.h>
27	#include <VBox/mm.h>
28	#include <VBox/selm.h>
29	#include <VBox/patm.h>
30	#include <VBox/csam.h>
31	#include <VBox/pgm.h>
32	#include <VBox/iom.h>
33	#include <VBox/stam.h>
34	#include "EMInternal.h"
35	#include <VBox/vm.h>
36	#include <VBox/hwaccm.h>
37	#include <VBox/tm.h>
38	#include <VBox/pdmapi.h>
39
40	#include <VBox/param.h>
41	#include <VBox/err.h>
42	#include <VBox/dis.h>
43	#include <VBox/disopcode.h>
44	#include <VBox/log.h>
45	#include <iprt/assert.h>
46	#include <iprt/asm.h>
47	#include <iprt/string.h>
48
49
50	/*******************************************************************************
51	* Structures and Typedefs *
52	*******************************************************************************/
53
54
55	/*******************************************************************************
56	* Internal Functions *
57	*******************************************************************************/
58	DECLINLINE(int) emInterpretInstructionCPU(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize);
59
60
61	/**
62	* Get the current execution manager status.
63	*
64	* @returns Current status.
65	*/
66	EMDECL(EMSTATE) EMGetState(PVM pVM)
67	{
68	return pVM->em.s.enmState;
69	}
70
71
72	#ifndef IN_GC
73	/**
74	* Read callback for disassembly function; supports reading bytes that cross a page boundary
75	*
76	* @returns VBox status code.
77	* @param pSrc GC source pointer
78	* @param pDest HC destination pointer
79	* @param cb Number of bytes to read
80	* @param dwUserdata Callback specific user data (pCpu)
81	*
82	*/
83	DECLCALLBACK(int) EMReadBytes(RTUINTPTR pSrc, uint8_t pDest, unsigned cb, void pvUserdata)
84	{
85	DISCPUSTATE pCpu = (DISCPUSTATE )pvUserdata;
86	PVM pVM = (PVM)pCpu->apvUserData[0];
87	#ifdef IN_RING0
88	int rc = PGMPhysReadGCPtr(pVM, pDest, pSrc, cb);
89	AssertMsgRC(rc, ("PGMPhysReadGCPtr failed for pSrc=%VGv cb=%x\n", pSrc, cb));
90	#else
91	if (!PATMIsPatchGCAddr(pVM, pSrc))
92	{
93	int rc = PGMPhysReadGCPtr(pVM, pDest, pSrc, cb);
94	AssertRC(rc);
95	}
96	else
97	{
98	for (uint32_t i = 0; i < cb; i++)
99	{
100	uint8_t opcode;
101	if (VBOX_SUCCESS(PATMR3QueryOpcode(pVM, (RTGCPTR)pSrc + i, &opcode)))
102	{
103	*(pDest+i) = opcode;
104	}
105	}
106	}
107	#endif /* IN_RING0 */
108	return VINF_SUCCESS;
109	}
110
111	DECLINLINE(int) emDisCoreOne(PVM pVM, DISCPUSTATE pCpu, RTGCUINTPTR InstrGC, uint32_t pOpsize)
112	{
113	return DISCoreOneEx(InstrGC, pCpu->mode, EMReadBytes, pVM, pCpu, pOpsize);
114	}
115
116	#else
117
118	DECLINLINE(int) emDisCoreOne(PVM pVM, DISCPUSTATE pCpu, RTGCUINTPTR InstrGC, uint32_t pOpsize)
119	{
120	return DISCoreOne(pCpu, InstrGC, pOpsize);
121	}
122
123	#endif
124
125
126	/**
127	* Disassembles one instruction.
128	*
129	* @param pVM The VM handle.
130	* @param pCtxCore The context core (used for both the mode and instruction).
131	* @param pCpu Where to return the parsed instruction info.
132	* @param pcbInstr Where to return the instruction size. (optional)
133	*/
134	EMDECL(int) EMInterpretDisasOne(PVM pVM, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, unsigned *pcbInstr)
135	{
136	RTGCPTR GCPtrInstr;
137	int rc = SELMToFlatEx(pVM, DIS_SELREG_CS, pCtxCore, pCtxCore->rip, 0, &GCPtrInstr);
138	if (VBOX_FAILURE(rc))
139	{
140	Log(("EMInterpretDisasOne: Failed to convert %RTsel:%VGv (cpl=%d) - rc=%Vrc !!\n",
141	pCtxCore->cs, pCtxCore->rip, pCtxCore->ss & X86_SEL_RPL, rc));
142	return rc;
143	}
144	return EMInterpretDisasOneEx(pVM, (RTGCUINTPTR)GCPtrInstr, pCtxCore, pCpu, pcbInstr);
145	}
146
147
148	/**
149	* Disassembles one instruction.
150	*
151	* This is used by internally by the interpreter and by trap/access handlers.
152	*
153	* @param pVM The VM handle.
154	* @param GCPtrInstr The flat address of the instruction.
155	* @param pCtxCore The context core (used to determin the cpu mode).
156	* @param pCpu Where to return the parsed instruction info.
157	* @param pcbInstr Where to return the instruction size. (optional)
158	*/
159	EMDECL(int) EMInterpretDisasOneEx(PVM pVM, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, unsigned *pcbInstr)
160	{
161	int rc = DISCoreOneEx(GCPtrInstr, SELMGetCpuModeFromSelector(pVM, pCtxCore->eflags, pCtxCore->cs, (PCPUMSELREGHID)&pCtxCore->csHid),
162	#ifdef IN_GC
163	NULL, NULL,
164	#else
165	EMReadBytes, pVM,
166	#endif
167	pCpu, pcbInstr);
168	if (VBOX_SUCCESS(rc))
169	return VINF_SUCCESS;
170	AssertMsgFailed(("DISCoreOne failed to GCPtrInstr=%VGv rc=%Vrc\n", GCPtrInstr, rc));
171	return VERR_INTERNAL_ERROR;
172	}
173
174
175	/**
176	* Interprets the current instruction.
177	*
178	* @returns VBox status code.
179	* @retval VINF_* Scheduling instructions.
180	* @retval VERR_EM_INTERPRETER Something we can't cope with.
181	* @retval VERR_* Fatal errors.
182	*
183	* @param pVM The VM handle.
184	* @param pRegFrame The register frame.
185	* Updates the EIP if an instruction was executed successfully.
186	* @param pvFault The fault address (CR2).
187	* @param pcbSize Size of the write (if applicable).
188	*
189	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
190	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
191	* to worry about e.g. invalid modrm combinations (!)
192	*/
193	EMDECL(int) EMInterpretInstruction(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
194	{
195	RTGCPTR pbCode;
196
197	LogFlow(("EMInterpretInstruction %VGv fault %VGv\n", pRegFrame->rip, pvFault));
198	int rc = SELMToFlatEx(pVM, DIS_SELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
199	if (VBOX_SUCCESS(rc))
200	{
201	uint32_t cbOp;
202	DISCPUSTATE Cpu;
203	Cpu.mode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
204	rc = emDisCoreOne(pVM, &Cpu, (RTGCUINTPTR)pbCode, &cbOp);
205	if (VBOX_SUCCESS(rc))
206	{
207	Assert(cbOp == Cpu.opsize);
208	rc = EMInterpretInstructionCPU(pVM, &Cpu, pRegFrame, pvFault, pcbSize);
209	if (VBOX_SUCCESS(rc))
210	{
211	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
212	}
213	return rc;
214	}
215	}
216	return VERR_EM_INTERPRETER;
217	}
218
219	/**
220	* Interprets the current instruction using the supplied DISCPUSTATE structure.
221	*
222	* EIP is NOT updated!
223	*
224	* @returns VBox status code.
225	* @retval VINF_* Scheduling instructions. When these are returned, it
226	* starts to get a bit tricky to know whether code was
227	* executed or not... We'll address this when it becomes a problem.
228	* @retval VERR_EM_INTERPRETER Something we can't cope with.
229	* @retval VERR_* Fatal errors.
230	*
231	* @param pVM The VM handle.
232	* @param pCpu The disassembler cpu state for the instruction to be interpreted.
233	* @param pRegFrame The register frame. EIP is NOT changed!
234	* @param pvFault The fault address (CR2).
235	* @param pcbSize Size of the write (if applicable).
236	*
237	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
238	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
239	* to worry about e.g. invalid modrm combinations (!)
240	*
241	* @todo At this time we do NOT check if the instruction overwrites vital information.
242	* Make sure this can't happen!! (will add some assertions/checks later)
243	*/
244	EMDECL(int) EMInterpretInstructionCPU(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
245	{
246	STAM_PROFILE_START(&CTXMID(pVM->em.s.CTXSUFF(pStats)->Stat,Emulate), a);
247	int rc = emInterpretInstructionCPU(pVM, pCpu, pRegFrame, pvFault, pcbSize);
248	STAM_PROFILE_STOP(&CTXMID(pVM->em.s.CTXSUFF(pStats)->Stat,Emulate), a);
249	if (VBOX_SUCCESS(rc))
250	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,InterpretSucceeded));
251	else
252	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,InterpretFailed));
253	return rc;
254	}
255
256
257	/**
258	* Interpret a port I/O instruction.
259	*
260	* @returns VBox status code suitable for scheduling.
261	* @param pVM The VM handle.
262	* @param pCtxCore The context core. This will be updated on successful return.
263	* @param pCpu The instruction to interpret.
264	* @param cbOp The size of the instruction.
265	* @remark This may raise exceptions.
266	*/
267	EMDECL(int) EMInterpretPortIO(PVM pVM, PCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, uint32_t cbOp)
268	{
269	/*
270	* Hand it on to IOM.
271	*/
272	#ifdef IN_GC
273	int rc = IOMGCIOPortHandler(pVM, pCtxCore, pCpu);
274	if (IOM_SUCCESS(rc))
275	pCtxCore->rip += cbOp;
276	return rc;
277	#else
278	AssertReleaseMsgFailed(("not implemented\n"));
279	return VERR_NOT_IMPLEMENTED;
280	#endif
281	}
282
283
284	DECLINLINE(int) emRamRead(PVM pVM, void *pDest, RTGCPTR GCSrc, uint32_t cb)
285	{
286	#ifdef IN_GC
287	int rc = MMGCRamRead(pVM, pDest, (void *)GCSrc, cb);
288	if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
289	return rc;
290	/*
291	* The page pool cache may end up here in some cases because it
292	* flushed one of the shadow mappings used by the trapping
293	* instruction and it either flushed the TLB or the CPU reused it.
294	*/
295	RTGCPHYS GCPhys;
296	rc = PGMPhysGCPtr2GCPhys(pVM, GCSrc, &GCPhys);
297	AssertRCReturn(rc, rc);
298	PGMPhysRead(pVM, GCPhys, pDest, cb);
299	return VINF_SUCCESS;
300	#else
301	return PGMPhysReadGCPtrSafe(pVM, pDest, GCSrc, cb);
302	#endif
303	}
304
305	DECLINLINE(int) emRamWrite(PVM pVM, RTGCPTR GCDest, void *pSrc, uint32_t cb)
306	{
307	#ifdef IN_GC
308	int rc = MMGCRamWrite(pVM, (void *)GCDest, pSrc, cb);
309	if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
310	return rc;
311	/*
312	* The page pool cache may end up here in some cases because it
313	* flushed one of the shadow mappings used by the trapping
314	* instruction and it either flushed the TLB or the CPU reused it.
315	* We want to play safe here, verifying that we've got write
316	* access doesn't cost us much (see PGMPhysGCPtr2GCPhys()).
317	*/
318	uint64_t fFlags;
319	RTGCPHYS GCPhys;
320	rc = PGMGstGetPage(pVM, GCDest, &fFlags, &GCPhys);
321	if (RT_FAILURE(rc))
322	return rc;
323	if ( !(fFlags & X86_PTE_RW)
324	&& (CPUMGetGuestCR0(pVM) & X86_CR0_WP))
325	return VERR_ACCESS_DENIED;
326
327	PGMPhysWrite(pVM, GCPhys + ((RTGCUINTPTR)GCDest & PAGE_OFFSET_MASK), pSrc, cb);
328	return VINF_SUCCESS;
329
330	#else
331	return PGMPhysWriteGCPtrSafe(pVM, GCDest, pSrc, cb);
332	#endif
333	}
334
335	/* Convert sel:addr to a flat GC address */
336	static RTGCPTR emConvertToFlatAddr(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, POP_PARAMETER pParam, RTGCPTR pvAddr)
337	{
338	DIS_SELREG enmPrefixSeg = DISDetectSegReg(pCpu, pParam);
339	return SELMToFlat(pVM, enmPrefixSeg, pRegFrame, pvAddr);
340	}
341
342	#if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
343	/**
344	* Get the mnemonic for the disassembled instruction.
345	*
346	* GC/R0 doesn't include the strings in the DIS tables because
347	* of limited space.
348	*/
349	static const char *emGetMnemonic(PDISCPUSTATE pCpu)
350	{
351	switch (pCpu->pCurInstr->opcode)
352	{
353	case OP_XCHG: return "Xchg";
354	case OP_DEC: return "Dec";
355	case OP_INC: return "Inc";
356	case OP_POP: return "Pop";
357	case OP_OR: return "Or";
358	case OP_AND: return "And";
359	case OP_MOV: return "Mov";
360	case OP_INVLPG: return "InvlPg";
361	case OP_CPUID: return "CpuId";
362	case OP_MOV_CR: return "MovCRx";
363	case OP_MOV_DR: return "MovDRx";
364	case OP_LLDT: return "LLdt";
365	case OP_CLTS: return "Clts";
366	case OP_MONITOR: return "Monitor";
367	case OP_MWAIT: return "MWait";
368	case OP_RDMSR: return "Rdmsr";
369	case OP_WRMSR: return "Wrmsr";
370	case OP_ADC: return "Adc";
371	case OP_BTC: return "Btc";
372	case OP_RDTSC: return "Rdtsc";
373	case OP_STI: return "Sti";
374	case OP_XADD: return "XAdd";
375	case OP_HLT: return "Hlt";
376	case OP_IRET: return "Iret";
377	case OP_CMPXCHG: return "CmpXchg";
378	case OP_CMPXCHG8B: return "CmpXchg8b";
379	case OP_MOVNTPS: return "MovNTPS";
380	case OP_STOSWD: return "StosWD";
381	case OP_WBINVD: return "WbInvd";
382	case OP_XOR: return "Xor";
383	case OP_BTR: return "Btr";
384	case OP_BTS: return "Bts";
385	default:
386	Log(("Unknown opcode %d\n", pCpu->pCurInstr->opcode));
387	return "???";
388	}
389	}
390	#endif
391
392	/**
393	* XCHG instruction emulation.
394	*/
395	static int emInterpretXchg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
396	{
397	OP_PARAMVAL param1, param2;
398
399	/* Source to make DISQueryParamVal read the register value - ugly hack */
400	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
401	if(VBOX_FAILURE(rc))
402	return VERR_EM_INTERPRETER;
403
404	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
405	if(VBOX_FAILURE(rc))
406	return VERR_EM_INTERPRETER;
407
408	#ifdef IN_GC
409	if (TRPMHasTrap(pVM))
410	{
411	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
412	{
413	#endif
414	RTGCPTR pParam1 = 0, pParam2 = 0;
415	uint64_t valpar1, valpar2;
416
417	AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
418	switch(param1.type)
419	{
420	case PARMTYPE_IMMEDIATE: /* register type is translated to this one too */
421	valpar1 = param1.val.val64;
422	break;
423
424	case PARMTYPE_ADDRESS:
425	pParam1 = (RTGCPTR)param1.val.val64;
426	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
427	#ifdef IN_GC
428	/* Safety check (in theory it could cross a page boundary and fault there though) */
429	AssertReturn(pParam1 == pvFault, VERR_EM_INTERPRETER);
430	#endif
431	rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
432	if (VBOX_FAILURE(rc))
433	{
434	AssertMsgFailed(("MMGCRamRead %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
435	return VERR_EM_INTERPRETER;
436	}
437	break;
438
439	default:
440	AssertFailed();
441	return VERR_EM_INTERPRETER;
442	}
443
444	switch(param2.type)
445	{
446	case PARMTYPE_ADDRESS:
447	pParam2 = (RTGCPTR)param2.val.val64;
448	pParam2 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param2, pParam2);
449	#ifdef IN_GC
450	/* Safety check (in theory it could cross a page boundary and fault there though) */
451	AssertReturn(pParam2 == pvFault, VERR_EM_INTERPRETER);
452	#endif
453	rc = emRamRead(pVM, &valpar2, pParam2, param2.size);
454	if (VBOX_FAILURE(rc))
455	{
456	AssertMsgFailed(("MMGCRamRead %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
457	}
458	break;
459
460	case PARMTYPE_IMMEDIATE:
461	valpar2 = param2.val.val64;
462	break;
463
464	default:
465	AssertFailed();
466	return VERR_EM_INTERPRETER;
467	}
468
469	/* Write value of parameter 2 to parameter 1 (reg or memory address) */
470	if (pParam1 == 0)
471	{
472	Assert(param1.type == PARMTYPE_IMMEDIATE); /* register actually */
473	switch(param1.size)
474	{
475	case 1: //special case for AH etc
476	rc = DISWriteReg8(pRegFrame, pCpu->param1.base.reg_gen, (uint8_t )valpar2); break;
477	case 2: rc = DISWriteReg16(pRegFrame, pCpu->param1.base.reg_gen, (uint16_t)valpar2); break;
478	case 4: rc = DISWriteReg32(pRegFrame, pCpu->param1.base.reg_gen, (uint32_t)valpar2); break;
479	case 8: rc = DISWriteReg64(pRegFrame, pCpu->param1.base.reg_gen, valpar2); break;
480	default: AssertFailedReturn(VERR_EM_INTERPRETER);
481	}
482	if (VBOX_FAILURE(rc))
483	return VERR_EM_INTERPRETER;
484	}
485	else
486	{
487	rc = emRamWrite(pVM, pParam1, &valpar2, param1.size);
488	if (VBOX_FAILURE(rc))
489	{
490	AssertMsgFailed(("emRamWrite %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
491	return VERR_EM_INTERPRETER;
492	}
493	}
494
495	/* Write value of parameter 1 to parameter 2 (reg or memory address) */
496	if (pParam2 == 0)
497	{
498	Assert(param2.type == PARMTYPE_IMMEDIATE); /* register actually */
499	switch(param2.size)
500	{
501	case 1: //special case for AH etc
502	rc = DISWriteReg8(pRegFrame, pCpu->param2.base.reg_gen, (uint8_t )valpar1); break;
503	case 2: rc = DISWriteReg16(pRegFrame, pCpu->param2.base.reg_gen, (uint16_t)valpar1); break;
504	case 4: rc = DISWriteReg32(pRegFrame, pCpu->param2.base.reg_gen, (uint32_t)valpar1); break;
505	case 8: rc = DISWriteReg64(pRegFrame, pCpu->param2.base.reg_gen, valpar1); break;
506	default: AssertFailedReturn(VERR_EM_INTERPRETER);
507	}
508	if (VBOX_FAILURE(rc))
509	return VERR_EM_INTERPRETER;
510	}
511	else
512	{
513	rc = emRamWrite(pVM, pParam2, &valpar1, param2.size);
514	if (VBOX_FAILURE(rc))
515	{
516	AssertMsgFailed(("emRamWrite %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
517	return VERR_EM_INTERPRETER;
518	}
519	}
520
521	*pcbSize = param2.size;
522	return VINF_SUCCESS;
523	#ifdef IN_GC
524	}
525	}
526	#endif
527	return VERR_EM_INTERPRETER;
528	}
529
530	/**
531	* INC and DEC emulation.
532	*/
533	static int emInterpretIncDec(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
534	PFN_EMULATE_PARAM2 pfnEmulate)
535	{
536	OP_PARAMVAL param1;
537
538	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
539	if(VBOX_FAILURE(rc))
540	return VERR_EM_INTERPRETER;
541
542	#ifdef IN_GC
543	if (TRPMHasTrap(pVM))
544	{
545	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
546	{
547	#endif
548	RTGCPTR pParam1 = 0;
549	uint64_t valpar1;
550
551	if (param1.type == PARMTYPE_ADDRESS)
552	{
553	pParam1 = (RTGCPTR)param1.val.val64;
554	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
555	#ifdef IN_GC
556	/* Safety check (in theory it could cross a page boundary and fault there though) */
557	AssertReturn(pParam1 == pvFault, VERR_EM_INTERPRETER);
558	#endif
559	rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
560	if (VBOX_FAILURE(rc))
561	{
562	AssertMsgFailed(("emRamRead %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
563	return VERR_EM_INTERPRETER;
564	}
565	}
566	else
567	{
568	AssertFailed();
569	return VERR_EM_INTERPRETER;
570	}
571
572	uint32_t eflags;
573
574	eflags = pfnEmulate(&valpar1, param1.size);
575
576	/* Write result back */
577	rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
578	if (VBOX_FAILURE(rc))
579	{
580	AssertMsgFailed(("emRamWrite %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
581	return VERR_EM_INTERPRETER;
582	}
583
584	/* Update guest's eflags and finish. */
585	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
586	\| (eflags & (X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
587
588	/* All done! */
589	*pcbSize = param1.size;
590	return VINF_SUCCESS;
591	#ifdef IN_GC
592	}
593	}
594	#endif
595	return VERR_EM_INTERPRETER;
596	}
597
598	/**
599	* POP Emulation.
600	*/
601	static int emInterpretPop(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
602	{
603	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
604	OP_PARAMVAL param1;
605	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
606	if(VBOX_FAILURE(rc))
607	return VERR_EM_INTERPRETER;
608
609	#ifdef IN_GC
610	if (TRPMHasTrap(pVM))
611	{
612	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
613	{
614	#endif
615	RTGCPTR pParam1 = 0;
616	uint32_t valpar1;
617	RTGCPTR pStackVal;
618
619	/* Read stack value first */
620	if (SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->ss, &pRegFrame->ssHid) == CPUMODE_16BIT)
621	return VERR_EM_INTERPRETER; /* No legacy 16 bits stuff here, please. */
622
623	/* Convert address; don't bother checking limits etc, as we only read here */
624	pStackVal = SELMToFlat(pVM, DIS_SELREG_SS, pRegFrame, (RTGCPTR)pRegFrame->esp);
625	if (pStackVal == 0)
626	return VERR_EM_INTERPRETER;
627
628	rc = emRamRead(pVM, &valpar1, pStackVal, param1.size);
629	if (VBOX_FAILURE(rc))
630	{
631	AssertMsgFailed(("emRamRead %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
632	return VERR_EM_INTERPRETER;
633	}
634
635	if (param1.type == PARMTYPE_ADDRESS)
636	{
637	pParam1 = (RTGCPTR)param1.val.val64;
638
639	/* pop [esp+xx] uses esp after the actual pop! */
640	AssertCompile(USE_REG_ESP == USE_REG_SP);
641	if ( (pCpu->param1.flags & USE_BASE)
642	&& (pCpu->param1.flags & (USE_REG_GEN16\|USE_REG_GEN32))
643	&& pCpu->param1.base.reg_gen == USE_REG_ESP
644	)
645	pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + param1.size);
646
647	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
648
649	#ifdef IN_GC
650	/* Safety check (in theory it could cross a page boundary and fault there though) */
651	AssertMsgReturn(pParam1 == pvFault \|\| (RTGCPTR)pRegFrame->esp == pvFault, ("%VGv != %VGv ss:esp=%04X:%08x\n", pParam1, pvFault, pRegFrame->ss, pRegFrame->esp), VERR_EM_INTERPRETER);
652	#endif
653	rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
654	if (VBOX_FAILURE(rc))
655	{
656	AssertMsgFailed(("emRamWrite %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
657	return VERR_EM_INTERPRETER;
658	}
659
660	/* Update ESP as the last step */
661	pRegFrame->esp += param1.size;
662	}
663	else
664	{
665	#ifndef DEBUG_bird // annoying assertion.
666	AssertFailed();
667	#endif
668	return VERR_EM_INTERPRETER;
669	}
670
671	/* All done! */
672	*pcbSize = param1.size;
673	return VINF_SUCCESS;
674	#ifdef IN_GC
675	}
676	}
677	#endif
678	return VERR_EM_INTERPRETER;
679	}
680
681
682	/**
683	* XOR/OR/AND Emulation.
684	*/
685	static int emInterpretOrXorAnd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
686	PFN_EMULATE_PARAM3 pfnEmulate)
687	{
688	OP_PARAMVAL param1, param2;
689	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
690	if(VBOX_FAILURE(rc))
691	return VERR_EM_INTERPRETER;
692
693	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
694	if(VBOX_FAILURE(rc))
695	return VERR_EM_INTERPRETER;
696
697	#ifdef LOG_ENABLED
698	const char *pszInstr;
699
700	if (pCpu->pCurInstr->opcode == OP_XOR)
701	pszInstr = "Xor";
702	else if (pCpu->pCurInstr->opcode == OP_OR)
703	pszInstr = "Or";
704	else if (pCpu->pCurInstr->opcode == OP_AND)
705	pszInstr = "And";
706	else
707	pszInstr = "OrXorAnd??";
708	#endif
709
710	#ifdef IN_GC
711	if (TRPMHasTrap(pVM))
712	{
713	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
714	{
715	#endif
716	RTGCPTR pParam1;
717	uint64_t valpar1, valpar2;
718
719	if (pCpu->param1.size != pCpu->param2.size)
720	{
721	if (pCpu->param1.size < pCpu->param2.size)
722	{
723	AssertMsgFailed(("%s at %VGv parameter mismatch %d vs %d!!\n", pszInstr, pRegFrame->rip, pCpu->param1.size, pCpu->param2.size)); /* should never happen! */
724	return VERR_EM_INTERPRETER;
725	}
726	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
727	pCpu->param2.size = pCpu->param1.size;
728	param2.size = param1.size;
729	}
730
731	/* The destination is always a virtual address */
732	if (param1.type == PARMTYPE_ADDRESS)
733	{
734	pParam1 = (RTGCPTR)param1.val.val64;
735	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
736
737	#ifdef IN_GC
738	/* Safety check (in theory it could cross a page boundary and fault there though) */
739	AssertMsgReturn(pParam1 == pvFault, ("eip=%VGv, pParam1=%VGv pvFault=%VGv\n", pRegFrame->rip, pParam1, pvFault), VERR_EM_INTERPRETER);
740	#endif
741	rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
742	if (VBOX_FAILURE(rc))
743	{
744	AssertMsgFailed(("emRamRead %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
745	return VERR_EM_INTERPRETER;
746	}
747	}
748	else
749	{
750	AssertFailed();
751	return VERR_EM_INTERPRETER;
752	}
753
754	/* Register or immediate data */
755	switch(param2.type)
756	{
757	case PARMTYPE_IMMEDIATE: /* both immediate data and register (ugly) */
758	valpar2 = param2.val.val64;
759	break;
760
761	default:
762	AssertFailed();
763	return VERR_EM_INTERPRETER;
764	}
765
766	LogFlow(("emInterpretOrXorAnd %s %VGv %RX64 - %RX64 size %d (%d)\n", pszInstr, pParam1, valpar1, valpar2, param2.size, param1.size));
767
768	/* Data read, emulate instruction. */
769	uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
770
771	LogFlow(("emInterpretOrXorAnd %s result %RX64\n", pszInstr, valpar1));
772
773	/* Update guest's eflags and finish. */
774	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
775	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
776
777	/* And write it back */
778	rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
779	if (VBOX_SUCCESS(rc))
780	{
781	/* All done! */
782	*pcbSize = param2.size;
783	return VINF_SUCCESS;
784	}
785	#ifdef IN_GC
786	}
787	}
788	#endif
789	return VERR_EM_INTERPRETER;
790	}
791
792	/**
793	* LOCK XOR/OR/AND Emulation.
794	*/
795	static int emInterpretLockOrXorAnd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
796	uint32_t *pcbSize, PFNEMULATELOCKPARAM3 pfnEmulate)
797	{
798	void *pvParam1;
799
800	OP_PARAMVAL param1, param2;
801	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
802	if(VBOX_FAILURE(rc))
803	return VERR_EM_INTERPRETER;
804
805	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
806	if(VBOX_FAILURE(rc))
807	return VERR_EM_INTERPRETER;
808
809	if (pCpu->param1.size != pCpu->param2.size)
810	{
811	AssertMsgReturn(pCpu->param1.size >= pCpu->param2.size, /* should never happen! */
812	("%s at %VGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pCpu), pRegFrame->rip, pCpu->param1.size, pCpu->param2.size),
813	VERR_EM_INTERPRETER);
814
815	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
816	pCpu->param2.size = pCpu->param1.size;
817	param2.size = param1.size;
818	}
819
820	/* The destination is always a virtual address */
821	AssertReturn(param1.type == PARMTYPE_ADDRESS, VERR_EM_INTERPRETER);
822
823	RTGCPTR GCPtrPar1 = param1.val.val64;
824	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
825	#ifdef IN_GC
826	pvParam1 = (void *)GCPtrPar1;
827	#else
828	rc = PGMPhysGCPtr2HCPtr(pVM, GCPtrPar1, &pvParam1);
829	if (VBOX_FAILURE(rc))
830	{
831	AssertRC(rc);
832	return VERR_EM_INTERPRETER;
833	}
834	#endif
835
836	# ifdef IN_GC
837	/* Safety check (in theory it could cross a page boundary and fault there though) */
838	Assert( TRPMHasTrap(pVM)
839	&& (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW));
840	AssertMsgReturn(GCPtrPar1 == pvFault, ("eip=%VGv, GCPtrPar1=%VGv pvFault=%VGv\n", pRegFrame->rip, GCPtrPar1, pvFault), VERR_EM_INTERPRETER);
841	# endif
842
843	/* Register and immediate data == PARMTYPE_IMMEDIATE */
844	AssertReturn(param2.type == PARMTYPE_IMMEDIATE, VERR_EM_INTERPRETER);
845	RTGCUINTREG ValPar2 = param2.val.val64;
846
847	/* Try emulate it with a one-shot #PF handler in place. */
848	Log2(("%s %VGv imm%d=%RX64\n", emGetMnemonic(pCpu), GCPtrPar1, pCpu->param2.size*8, ValPar2));
849
850	RTGCUINTREG32 eflags = 0;
851	#ifdef IN_GC
852	MMGCRamRegisterTrapHandler(pVM);
853	#endif
854	rc = pfnEmulate(pvParam1, ValPar2, pCpu->param2.size, &eflags);
855	#ifdef IN_GC
856	MMGCRamDeregisterTrapHandler(pVM);
857	#endif
858	if (RT_FAILURE(rc))
859	{
860	Log(("%s %VGv imm%d=%RX64-> emulation failed due to page fault!\n", emGetMnemonic(pCpu), GCPtrPar1, pCpu->param2.size*8, ValPar2));
861	return VERR_EM_INTERPRETER;
862	}
863
864	/* Update guest's eflags and finish. */
865	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
866	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
867
868	*pcbSize = param2.size;
869	return VINF_SUCCESS;
870	}
871
872	/**
873	* ADD, ADC & SUB Emulation.
874	*/
875	static int emInterpretAddSub(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
876	PFN_EMULATE_PARAM3 pfnEmulate)
877	{
878	OP_PARAMVAL param1, param2;
879	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
880	if(VBOX_FAILURE(rc))
881	return VERR_EM_INTERPRETER;
882
883	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
884	if(VBOX_FAILURE(rc))
885	return VERR_EM_INTERPRETER;
886
887	#ifdef LOG_ENABLED
888	const char *pszInstr;
889
890	if (pCpu->pCurInstr->opcode == OP_SUB)
891	pszInstr = "Sub";
892	else if (pCpu->pCurInstr->opcode == OP_ADD)
893	pszInstr = "Add";
894	else if (pCpu->pCurInstr->opcode == OP_ADC)
895	pszInstr = "Adc";
896	else
897	pszInstr = "AddSub??";
898	#endif
899
900	#ifdef IN_GC
901	if (TRPMHasTrap(pVM))
902	{
903	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
904	{
905	#endif
906	RTGCPTR pParam1;
907	uint64_t valpar1, valpar2;
908
909	if (pCpu->param1.size != pCpu->param2.size)
910	{
911	if (pCpu->param1.size < pCpu->param2.size)
912	{
913	AssertMsgFailed(("%s at %VGv parameter mismatch %d vs %d!!\n", pszInstr, pRegFrame->rip, pCpu->param1.size, pCpu->param2.size)); /* should never happen! */
914	return VERR_EM_INTERPRETER;
915	}
916	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
917	pCpu->param2.size = pCpu->param1.size;
918	param2.size = param1.size;
919	}
920
921	/* The destination is always a virtual address */
922	if (param1.type == PARMTYPE_ADDRESS)
923	{
924	pParam1 = (RTGCPTR)param1.val.val64;
925	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
926
927	#ifdef IN_GC
928	/* Safety check (in theory it could cross a page boundary and fault there though) */
929	AssertReturn(pParam1 == pvFault, VERR_EM_INTERPRETER);
930	#endif
931	rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
932	if (VBOX_FAILURE(rc))
933	{
934	AssertMsgFailed(("emRamRead %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
935	return VERR_EM_INTERPRETER;
936	}
937	}
938	else
939	{
940	#ifndef DEBUG_bird
941	AssertFailed();
942	#endif
943	return VERR_EM_INTERPRETER;
944	}
945
946	/* Register or immediate data */
947	switch(param2.type)
948	{
949	case PARMTYPE_IMMEDIATE: /* both immediate data and register (ugly) */
950	valpar2 = param2.val.val64;
951	break;
952
953	default:
954	AssertFailed();
955	return VERR_EM_INTERPRETER;
956	}
957
958	/* Data read, emulate instruction. */
959	uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
960
961	/* Update guest's eflags and finish. */
962	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
963	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
964
965	/* And write it back */
966	rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
967	if (VBOX_SUCCESS(rc))
968	{
969	/* All done! */
970	*pcbSize = param2.size;
971	return VINF_SUCCESS;
972	}
973	#ifdef IN_GC
974	}
975	}
976	#endif
977	return VERR_EM_INTERPRETER;
978	}
979
980	/**
981	* ADC Emulation.
982	*/
983	static int emInterpretAdc(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
984	{
985	if (pRegFrame->eflags.Bits.u1CF)
986	return emInterpretAddSub(pVM, pCpu, pRegFrame, pvFault, pcbSize, EMEmulateAdcWithCarrySet);
987	else
988	return emInterpretAddSub(pVM, pCpu, pRegFrame, pvFault, pcbSize, EMEmulateAdd);
989	}
990
991	/**
992	* BTR/C/S Emulation.
993	*/
994	static int emInterpretBitTest(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
995	PFN_EMULATE_PARAM2_UINT32 pfnEmulate)
996	{
997	OP_PARAMVAL param1, param2;
998	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
999	if(VBOX_FAILURE(rc))
1000	return VERR_EM_INTERPRETER;
1001
1002	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1003	if(VBOX_FAILURE(rc))
1004	return VERR_EM_INTERPRETER;
1005
1006	#ifdef LOG_ENABLED
1007	const char *pszInstr;
1008
1009	if (pCpu->pCurInstr->opcode == OP_BTR)
1010	pszInstr = "Btr";
1011	else if (pCpu->pCurInstr->opcode == OP_BTS)
1012	pszInstr = "Bts";
1013	else if (pCpu->pCurInstr->opcode == OP_BTC)
1014	pszInstr = "Btc";
1015	else
1016	pszInstr = "Bit??";
1017	#endif
1018
1019	#ifdef IN_GC
1020	if (TRPMHasTrap(pVM))
1021	{
1022	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1023	{
1024	#endif
1025	RTGCPTR pParam1;
1026	uint64_t valpar1 = 0, valpar2;
1027	uint32_t eflags;
1028
1029	/* The destination is always a virtual address */
1030	if (param1.type != PARMTYPE_ADDRESS)
1031	return VERR_EM_INTERPRETER;
1032
1033	pParam1 = (RTGCPTR)param1.val.val64;
1034	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
1035
1036	/* Register or immediate data */
1037	switch(param2.type)
1038	{
1039	case PARMTYPE_IMMEDIATE: /* both immediate data and register (ugly) */
1040	valpar2 = param2.val.val64;
1041	break;
1042
1043	default:
1044	AssertFailed();
1045	return VERR_EM_INTERPRETER;
1046	}
1047
1048	Log2(("emInterpret%s: pvFault=%VGv pParam1=%VGv val2=%x\n", pszInstr, pvFault, pParam1, valpar2));
1049	pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + valpar2/8);
1050	#ifdef IN_GC
1051	/* Safety check. */
1052	AssertMsgReturn((RTGCPTR)((RTGCUINTPTR)pParam1 & ~3) == pvFault, ("pParam1=%VGv pvFault=%VGv\n", pParam1, pvFault), VERR_EM_INTERPRETER);
1053	#endif
1054	rc = emRamRead(pVM, &valpar1, pParam1, 1);
1055	if (VBOX_FAILURE(rc))
1056	{
1057	AssertMsgFailed(("emRamRead %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
1058	return VERR_EM_INTERPRETER;
1059	}
1060
1061	Log2(("emInterpretBtx: val=%x\n", valpar1));
1062	/* Data read, emulate bit test instruction. */
1063	eflags = pfnEmulate(&valpar1, valpar2 & 0x7);
1064
1065	Log2(("emInterpretBtx: val=%x CF=%d\n", valpar1, !!(eflags & X86_EFL_CF)));
1066
1067	/* Update guest's eflags and finish. */
1068	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1069	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1070
1071	/* And write it back */
1072	rc = emRamWrite(pVM, pParam1, &valpar1, 1);
1073	if (VBOX_SUCCESS(rc))
1074	{
1075	/* All done! */
1076	*pcbSize = 1;
1077	return VINF_SUCCESS;
1078	}
1079	#ifdef IN_GC
1080	}
1081	}
1082	#endif
1083	return VERR_EM_INTERPRETER;
1084	}
1085
1086	/**
1087	* LOCK BTR/C/S Emulation.
1088	*/
1089	static int emInterpretLockBitTest(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
1090	uint32_t *pcbSize, PFNEMULATELOCKPARAM2 pfnEmulate)
1091	{
1092	void *pvParam1;
1093
1094	OP_PARAMVAL param1, param2;
1095	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
1096	if(VBOX_FAILURE(rc))
1097	return VERR_EM_INTERPRETER;
1098
1099	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1100	if(VBOX_FAILURE(rc))
1101	return VERR_EM_INTERPRETER;
1102
1103	/* The destination is always a virtual address */
1104	if (param1.type != PARMTYPE_ADDRESS)
1105	return VERR_EM_INTERPRETER;
1106
1107	/* Register and immediate data == PARMTYPE_IMMEDIATE */
1108	AssertReturn(param2.type == PARMTYPE_IMMEDIATE, VERR_EM_INTERPRETER);
1109	uint64_t ValPar2 = param2.val.val64;
1110
1111	/* Adjust the parameters so what we're dealing with is a bit within the byte pointed to. */
1112	RTGCPTR GCPtrPar1 = param1.val.val64;
1113	GCPtrPar1 = (GCPtrPar1 + ValPar2 / 8);
1114	ValPar2 &= 7;
1115
1116	#ifdef IN_GC
1117	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
1118	pvParam1 = (void *)GCPtrPar1;
1119	#else
1120	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
1121	rc = PGMPhysGCPtr2HCPtr(pVM, GCPtrPar1, &pvParam1);
1122	if (VBOX_FAILURE(rc))
1123	{
1124	AssertRC(rc);
1125	return VERR_EM_INTERPRETER;
1126	}
1127	#endif
1128
1129	Log2(("emInterpretLockBitTest %s: pvFault=%VGv GCPtrPar1=%VGv imm=%RX64\n", emGetMnemonic(pCpu), pvFault, GCPtrPar1, ValPar2));
1130
1131	#ifdef IN_GC
1132	Assert(TRPMHasTrap(pVM));
1133	AssertMsgReturn((RTGCPTR)((RTGCUINTPTR)GCPtrPar1 & ~(RTGCUINTPTR)3) == pvFault,
1134	("GCPtrPar1=%VGv pvFault=%VGv\n", GCPtrPar1, pvFault),
1135	VERR_EM_INTERPRETER);
1136	#endif
1137
1138	/* Try emulate it with a one-shot #PF handler in place. */
1139	RTGCUINTREG32 eflags = 0;
1140	#ifdef IN_GC
1141	MMGCRamRegisterTrapHandler(pVM);
1142	#endif
1143	rc = pfnEmulate(pvParam1, ValPar2, &eflags);
1144	#ifdef IN_GC
1145	MMGCRamDeregisterTrapHandler(pVM);
1146	#endif
1147	if (RT_FAILURE(rc))
1148	{
1149	Log(("emInterpretLockBitTest %s: %VGv imm%d=%RX64 -> emulation failed due to page fault!\n",
1150	emGetMnemonic(pCpu), GCPtrPar1, pCpu->param2.size*8, ValPar2));
1151	return VERR_EM_INTERPRETER;
1152	}
1153
1154	Log2(("emInterpretLockBitTest %s: GCPtrPar1=%VGv imm=%VX64 CF=%d\n", emGetMnemonic(pCpu), GCPtrPar1, ValPar2, !!(eflags & X86_EFL_CF)));
1155
1156	/* Update guest's eflags and finish. */
1157	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1158	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1159
1160	*pcbSize = 1;
1161	return VINF_SUCCESS;
1162	}
1163
1164	/**
1165	* MOV emulation.
1166	*/
1167	static int emInterpretMov(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1168	{
1169	OP_PARAMVAL param1, param2;
1170	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
1171	if(VBOX_FAILURE(rc))
1172	return VERR_EM_INTERPRETER;
1173
1174	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1175	if(VBOX_FAILURE(rc))
1176	return VERR_EM_INTERPRETER;
1177
1178	#ifdef IN_GC
1179	if (TRPMHasTrap(pVM))
1180	{
1181	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1182	{
1183	#else
1184	/** @todo Make this the default and don't rely on TRPM information. */
1185	if (param1.type == PARMTYPE_ADDRESS)
1186	{
1187	#endif
1188	RTGCPTR pDest;
1189	uint64_t val64;
1190
1191	switch(param1.type)
1192	{
1193	case PARMTYPE_IMMEDIATE:
1194	if(!(param1.flags & (PARAM_VAL32\|PARAM_VAL64)))
1195	return VERR_EM_INTERPRETER;
1196	/* fallthru */
1197
1198	case PARMTYPE_ADDRESS:
1199	pDest = (RTGCPTR)param1.val.val64;
1200	pDest = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pDest);
1201	break;
1202
1203	default:
1204	AssertFailed();
1205	return VERR_EM_INTERPRETER;
1206	}
1207
1208	switch(param2.type)
1209	{
1210	case PARMTYPE_IMMEDIATE: /* register type is translated to this one too */
1211	val64 = param2.val.val64;
1212	break;
1213
1214	default:
1215	Log(("emInterpretMov: unexpected type=%d eip=%VGv\n", param2.type, pRegFrame->rip));
1216	return VERR_EM_INTERPRETER;
1217	}
1218	#ifdef LOG_ENABLED
1219	if (pCpu->mode == CPUMODE_64BIT)
1220	LogFlow(("EMInterpretInstruction at %VGv: OP_MOV %VGv <- %RX64 (%d) &val32=%VHv\n", pRegFrame->rip, pDest, val64, param2.size, &val64));
1221	else
1222	LogFlow(("EMInterpretInstruction at %VGv: OP_MOV %VGv <- %08X (%d) &val32=%VHv\n", pRegFrame->rip, pDest, (uint32_t)val64, param2.size, &val64));
1223	#endif
1224
1225	Assert(param2.size <= 8 && param2.size > 0);
1226
1227	#if 0 /* CSAM/PATM translates aliases which causes this to incorrectly trigger. See #2609 and #1498. */
1228	#ifdef IN_GC
1229	/* Safety check (in theory it could cross a page boundary and fault there though) */
1230	AssertMsgReturn(pDest == pvFault, ("eip=%VGv pDest=%VGv pvFault=%VGv\n", pRegFrame->rip, pDest, pvFault), VERR_EM_INTERPRETER);
1231	#endif
1232	#endif
1233	rc = emRamWrite(pVM, pDest, &val64, param2.size);
1234	if (VBOX_FAILURE(rc))
1235	return VERR_EM_INTERPRETER;
1236
1237	*pcbSize = param2.size;
1238	}
1239	else
1240	{ /* read fault */
1241	RTGCPTR pSrc;
1242	uint64_t val64;
1243
1244	/* Source */
1245	switch(param2.type)
1246	{
1247	case PARMTYPE_IMMEDIATE:
1248	if(!(param2.flags & (PARAM_VAL32\|PARAM_VAL64)))
1249	return VERR_EM_INTERPRETER;
1250	/* fallthru */
1251
1252	case PARMTYPE_ADDRESS:
1253	pSrc = (RTGCPTR)param2.val.val64;
1254	pSrc = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param2, pSrc);
1255	break;
1256
1257	default:
1258	return VERR_EM_INTERPRETER;
1259	}
1260
1261	Assert(param1.size <= 8 && param1.size > 0);
1262	#ifdef IN_GC
1263	/* Safety check (in theory it could cross a page boundary and fault there though) */
1264	AssertReturn(pSrc == pvFault, VERR_EM_INTERPRETER);
1265	#endif
1266	rc = emRamRead(pVM, &val64, pSrc, param1.size);
1267	if (VBOX_FAILURE(rc))
1268	return VERR_EM_INTERPRETER;
1269
1270	/* Destination */
1271	switch(param1.type)
1272	{
1273	case PARMTYPE_REGISTER:
1274	switch(param1.size)
1275	{
1276	case 1: rc = DISWriteReg8(pRegFrame, pCpu->param1.base.reg_gen, (uint8_t) val64); break;
1277	case 2: rc = DISWriteReg16(pRegFrame, pCpu->param1.base.reg_gen, (uint16_t)val64); break;
1278	case 4: rc = DISWriteReg32(pRegFrame, pCpu->param1.base.reg_gen, (uint32_t)val64); break;
1279	case 8: rc = DISWriteReg64(pRegFrame, pCpu->param1.base.reg_gen, val64); break;
1280	default:
1281	return VERR_EM_INTERPRETER;
1282	}
1283	if (VBOX_FAILURE(rc))
1284	return rc;
1285	break;
1286
1287	default:
1288	return VERR_EM_INTERPRETER;
1289	}
1290	#ifdef LOG_ENABLED
1291	if (pCpu->mode == CPUMODE_64BIT)
1292	LogFlow(("EMInterpretInstruction: OP_MOV %VGv -> %RX64 (%d)\n", pSrc, val64, param1.size));
1293	else
1294	LogFlow(("EMInterpretInstruction: OP_MOV %VGv -> %08X (%d)\n", pSrc, (uint32_t)val64, param1.size));
1295	#endif
1296	}
1297	return VINF_SUCCESS;
1298	#ifdef IN_GC
1299	}
1300	#endif
1301	return VERR_EM_INTERPRETER;
1302	}
1303
1304	#ifndef IN_GC
1305	/*
1306	* [REP] STOSWD emulation
1307	*
1308	*/
1309	static int emInterpretStosWD(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1310	{
1311	int rc;
1312	RTGCPTR GCDest, GCOffset;
1313	uint32_t cbSize;
1314	uint64_t cTransfers;
1315
1316	/* Don't support any but these three prefix bytes. */
1317	if ((pCpu->prefix & ~(PREFIX_ADDRSIZE\|PREFIX_OPSIZE\|PREFIX_REP\|PREFIX_REX)))
1318	return VERR_EM_INTERPRETER;
1319
1320	switch (pCpu->addrmode)
1321	{
1322	case CPUMODE_16BIT:
1323	GCOffset = pRegFrame->di;
1324	cTransfers = pRegFrame->cx;
1325	break;
1326	case CPUMODE_32BIT:
1327	GCOffset = pRegFrame->edi;
1328	cTransfers = pRegFrame->ecx;
1329	break;
1330	case CPUMODE_64BIT:
1331	GCOffset = pRegFrame->rdi;
1332	cTransfers = pRegFrame->rcx;
1333	break;
1334	default:
1335	AssertFailed();
1336	return VERR_EM_INTERPRETER;
1337	}
1338
1339	GCDest = SELMToFlat(pVM, DIS_SELREG_ES, pRegFrame, GCOffset);
1340	switch (pCpu->opmode)
1341	{
1342	case CPUMODE_16BIT:
1343	cbSize = 2;
1344	break;
1345	case CPUMODE_32BIT:
1346	cbSize = 4;
1347	break;
1348	case CPUMODE_64BIT:
1349	cbSize = 8;
1350	break;
1351	default:
1352	AssertFailed();
1353	return VERR_EM_INTERPRETER;
1354	}
1355
1356	LogFlow(("emInterpretStosWD dest=%VGv cbSize=%d\n", GCDest, cbSize));
1357
1358	if (!(pCpu->prefix & PREFIX_REP))
1359	{
1360	rc = PGMPhysWriteGCPtrSafe(pVM, GCDest, &pRegFrame->rax, cbSize);
1361	if (VBOX_FAILURE(rc))
1362	return VERR_EM_INTERPRETER;
1363	Assert(rc == VINF_SUCCESS);
1364	}
1365	else
1366	{
1367	/* Access verification first; we currently can't recover properly from traps inside this instruction */
1368	rc = PGMVerifyAccess(pVM, GCDest, cTransfers * cbSize, X86_PTE_RW \| X86_PTE_US);
1369	if (rc != VINF_SUCCESS)
1370	{
1371	Log(("STOSWD will generate a trap -> recompiler, rc=%d\n", rc));
1372	return VERR_EM_INTERPRETER;
1373	}
1374
1375	/* REP case */
1376	while (cTransfers)
1377	{
1378	rc = PGMPhysWriteGCPtrSafe(pVM, GCDest, &pRegFrame->rax, cbSize);
1379	if (VBOX_FAILURE(rc))
1380	{
1381	rc = VERR_EM_INTERPRETER;
1382	break;
1383	}
1384
1385	Assert(rc == VINF_SUCCESS);
1386	GCOffset += cbSize;
1387	GCDest += cbSize;
1388	cTransfers--;
1389	}
1390
1391	/* Update the registers. */
1392	switch (pCpu->addrmode)
1393	{
1394	case CPUMODE_16BIT:
1395	pRegFrame->di = GCOffset;
1396	pRegFrame->cx = cTransfers;
1397	break;
1398	case CPUMODE_32BIT:
1399	pRegFrame->edi = GCOffset;
1400	pRegFrame->ecx = cTransfers;
1401	break;
1402	case CPUMODE_64BIT:
1403	pRegFrame->rdi = GCOffset;
1404	pRegFrame->rcx = cTransfers;
1405	break;
1406	}
1407	}
1408
1409	*pcbSize = cbSize;
1410	return rc;
1411	}
1412	#endif
1413
1414
1415	/*
1416	* [LOCK] CMPXCHG emulation.
1417	*/
1418	#ifdef IN_GC
1419	static int emInterpretCmpXchg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1420	{
1421	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
1422	OP_PARAMVAL param1, param2;
1423
1424	#ifdef LOG_ENABLED
1425	const char *pszInstr;
1426
1427	if (pCpu->prefix & PREFIX_LOCK)
1428	pszInstr = "Lock CmpXchg";
1429	else
1430	pszInstr = "CmpXchg";
1431	#endif
1432
1433	/* Source to make DISQueryParamVal read the register value - ugly hack */
1434	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1435	if(VBOX_FAILURE(rc))
1436	return VERR_EM_INTERPRETER;
1437
1438	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1439	if(VBOX_FAILURE(rc))
1440	return VERR_EM_INTERPRETER;
1441
1442	if (TRPMHasTrap(pVM))
1443	{
1444	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1445	{
1446	RTRCPTR pParam1;
1447	uint32_t valpar, eflags;
1448	#ifdef VBOX_STRICT
1449	uint32_t valpar1 = 0; /// @todo used uninitialized...
1450	#endif
1451
1452	AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
1453	switch(param1.type)
1454	{
1455	case PARMTYPE_ADDRESS:
1456	pParam1 = (RTRCPTR)param1.val.val64;
1457	pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);
1458
1459	/* Safety check (in theory it could cross a page boundary and fault there though) */
1460	AssertMsgReturn(pParam1 == (RTRCPTR)pvFault, ("eip=%VGv pParam1=%VRv pvFault=%VGv\n", pRegFrame->rip, pParam1, pvFault), VERR_EM_INTERPRETER);
1461	break;
1462
1463	default:
1464	return VERR_EM_INTERPRETER;
1465	}
1466
1467	switch(param2.type)
1468	{
1469	case PARMTYPE_IMMEDIATE: /* register actually */
1470	valpar = param2.val.val32;
1471	break;
1472
1473	default:
1474	return VERR_EM_INTERPRETER;
1475	}
1476
1477	LogFlow(("%s %VRv=%08x eax=%08x %08x\n", pszInstr, pParam1, valpar1, pRegFrame->eax, valpar));
1478
1479	MMGCRamRegisterTrapHandler(pVM);
1480	if (pCpu->prefix & PREFIX_LOCK)
1481	rc = EMGCEmulateLockCmpXchg(pParam1, &pRegFrame->eax, valpar, pCpu->param2.size, &eflags);
1482	else
1483	rc = EMGCEmulateCmpXchg(pParam1, &pRegFrame->eax, valpar, pCpu->param2.size, &eflags);
1484	MMGCRamDeregisterTrapHandler(pVM);
1485
1486	if (VBOX_FAILURE(rc))
1487	{
1488	Log(("%s %VGv=%08x eax=%08x %08x -> emulation failed due to page fault!\n", pszInstr, pParam1, valpar1, pRegFrame->eax, valpar));
1489	return VERR_EM_INTERPRETER;
1490	}
1491
1492	LogFlow(("%s %VRv=%08x eax=%08x %08x ZF=%d\n", pszInstr, pParam1, valpar1, pRegFrame->eax, valpar, !!(eflags & X86_EFL_ZF)));
1493
1494	/* Update guest's eflags and finish. */
1495	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1496	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1497
1498	*pcbSize = param2.size;
1499	return VINF_SUCCESS;
1500	}
1501	}
1502	return VERR_EM_INTERPRETER;
1503	}
1504
1505	/*
1506	* [LOCK] CMPXCHG8B emulation.
1507	*/
1508	static int emInterpretCmpXchg8b(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1509	{
1510	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
1511	OP_PARAMVAL param1;
1512
1513	#ifdef LOG_ENABLED
1514	const char *pszInstr;
1515
1516	if (pCpu->prefix & PREFIX_LOCK)
1517	pszInstr = "Lock CmpXchg8b";
1518	else
1519	pszInstr = "CmpXchg8b";
1520	#endif
1521
1522	/* Source to make DISQueryParamVal read the register value - ugly hack */
1523	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1524	if(VBOX_FAILURE(rc))
1525	return VERR_EM_INTERPRETER;
1526
1527	if (TRPMHasTrap(pVM))
1528	{
1529	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1530	{
1531	RTRCPTR pParam1;
1532	uint32_t eflags;
1533
1534	AssertReturn(pCpu->param1.size == 8, VERR_EM_INTERPRETER);
1535	switch(param1.type)
1536	{
1537	case PARMTYPE_ADDRESS:
1538	pParam1 = (RTRCPTR)param1.val.val64;
1539	pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);
1540
1541	/* Safety check (in theory it could cross a page boundary and fault there though) */
1542	AssertMsgReturn(pParam1 == (RTRCPTR)pvFault, ("eip=%VGv pParam1=%VRv pvFault=%VGv\n", pRegFrame->rip, pParam1, pvFault), VERR_EM_INTERPRETER);
1543	break;
1544
1545	default:
1546	return VERR_EM_INTERPRETER;
1547	}
1548
1549	LogFlow(("%s %VRv=%08x eax=%08x\n", pszInstr, pParam1, pRegFrame->eax));
1550
1551	MMGCRamRegisterTrapHandler(pVM);
1552	if (pCpu->prefix & PREFIX_LOCK)
1553	rc = EMGCEmulateLockCmpXchg8b(pParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx, &eflags);
1554	else
1555	rc = EMGCEmulateCmpXchg8b(pParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx, &eflags);
1556	MMGCRamDeregisterTrapHandler(pVM);
1557
1558	if (VBOX_FAILURE(rc))
1559	{
1560	Log(("%s %VGv=%08x eax=%08x -> emulation failed due to page fault!\n", pszInstr, pParam1, pRegFrame->eax));
1561	return VERR_EM_INTERPRETER;
1562	}
1563
1564	LogFlow(("%s %VGv=%08x eax=%08x ZF=%d\n", pszInstr, pParam1, pRegFrame->eax, !!(eflags & X86_EFL_ZF)));
1565
1566	/* Update guest's eflags and finish; note that only ZF is affected. */
1567	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_ZF))
1568	\| (eflags & (X86_EFL_ZF));
1569
1570	*pcbSize = 8;
1571	return VINF_SUCCESS;
1572	}
1573	}
1574	return VERR_EM_INTERPRETER;
1575	}
1576	#endif
1577
1578	/*
1579	* [LOCK] XADD emulation.
1580	*/
1581	#ifdef IN_GC
1582	static int emInterpretXAdd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1583	{
1584	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
1585	OP_PARAMVAL param1;
1586	uint32_t *pParamReg2;
1587	size_t cbSizeParamReg2;
1588
1589	/* Source to make DISQueryParamVal read the register value - ugly hack */
1590	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1591	if(VBOX_FAILURE(rc))
1592	return VERR_EM_INTERPRETER;
1593
1594	rc = DISQueryParamRegPtr(pRegFrame, pCpu, &pCpu->param2, (void **)&pParamReg2, &cbSizeParamReg2);
1595	Assert(cbSizeParamReg2 <= 4);
1596	if(VBOX_FAILURE(rc))
1597	return VERR_EM_INTERPRETER;
1598
1599	if (TRPMHasTrap(pVM))
1600	{
1601	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1602	{
1603	RTRCPTR pParam1;
1604	uint32_t eflags;
1605	#ifdef VBOX_STRICT
1606	uint32_t valpar1 = 0; /// @todo used uninitialized...
1607	#endif
1608
1609	AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
1610	switch(param1.type)
1611	{
1612	case PARMTYPE_ADDRESS:
1613	pParam1 = (RTRCPTR)param1.val.val64;
1614	pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);
1615
1616	/* Safety check (in theory it could cross a page boundary and fault there though) */
1617	AssertMsgReturn(pParam1 == (RTRCPTR)pvFault, ("eip=%VGv pParam1=%VRv pvFault=%VGv\n", pRegFrame->rip, pParam1, pvFault), VERR_EM_INTERPRETER);
1618	break;
1619
1620	default:
1621	return VERR_EM_INTERPRETER;
1622	}
1623
1624	LogFlow(("XAdd %VRv=%08x reg=%08x\n", pParam1, *pParamReg2));
1625
1626	MMGCRamRegisterTrapHandler(pVM);
1627	if (pCpu->prefix & PREFIX_LOCK)
1628	rc = EMGCEmulateLockXAdd(pParam1, pParamReg2, cbSizeParamReg2, &eflags);
1629	else
1630	rc = EMGCEmulateXAdd(pParam1, pParamReg2, cbSizeParamReg2, &eflags);
1631	MMGCRamDeregisterTrapHandler(pVM);
1632
1633	if (VBOX_FAILURE(rc))
1634	{
1635	Log(("XAdd %VGv=%08x reg=%08x -> emulation failed due to page fault!\n", pParam1, valpar1, *pParamReg2));
1636	return VERR_EM_INTERPRETER;
1637	}
1638
1639	LogFlow(("XAdd %VGv=%08x reg=%08x ZF=%d\n", pParam1, valpar1, *pParamReg2, !!(eflags & X86_EFL_ZF)));
1640
1641	/* Update guest's eflags and finish. */
1642	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1643	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1644
1645	*pcbSize = cbSizeParamReg2;
1646	return VINF_SUCCESS;
1647	}
1648	}
1649	return VERR_EM_INTERPRETER;
1650	}
1651	#endif
1652
1653	#ifdef IN_GC
1654	/**
1655	* Interpret IRET (currently only to V86 code)
1656	*
1657	* @returns VBox status code.
1658	* @param pVM The VM handle.
1659	* @param pRegFrame The register frame.
1660	*
1661	*/
1662	EMDECL(int) EMInterpretIret(PVM pVM, PCPUMCTXCORE pRegFrame)
1663	{
1664	RTGCUINTPTR pIretStack = (RTGCUINTPTR)pRegFrame->esp;
1665	RTGCUINTPTR eip, cs, esp, ss, eflags, ds, es, fs, gs, uMask;
1666	int rc;
1667
1668	Assert(!CPUMIsGuestIn64BitCode(pVM, pRegFrame));
1669
1670	rc = emRamRead(pVM, &eip, (RTGCPTR)pIretStack , 4);
1671	rc \|= emRamRead(pVM, &cs, (RTGCPTR)(pIretStack + 4), 4);
1672	rc \|= emRamRead(pVM, &eflags, (RTGCPTR)(pIretStack + 8), 4);
1673	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1674	AssertReturn(eflags & X86_EFL_VM, VERR_EM_INTERPRETER);
1675
1676	rc \|= emRamRead(pVM, &esp, (RTGCPTR)(pIretStack + 12), 4);
1677	rc \|= emRamRead(pVM, &ss, (RTGCPTR)(pIretStack + 16), 4);
1678	rc \|= emRamRead(pVM, &es, (RTGCPTR)(pIretStack + 20), 4);
1679	rc \|= emRamRead(pVM, &ds, (RTGCPTR)(pIretStack + 24), 4);
1680	rc \|= emRamRead(pVM, &fs, (RTGCPTR)(pIretStack + 28), 4);
1681	rc \|= emRamRead(pVM, &gs, (RTGCPTR)(pIretStack + 32), 4);
1682	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1683
1684	pRegFrame->eip = eip & 0xffff;
1685	pRegFrame->cs = cs;
1686
1687	/* Mask away all reserved bits */
1688	uMask = X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_RF \| X86_EFL_VM \| X86_EFL_AC \| X86_EFL_VIF \| X86_EFL_VIP \| X86_EFL_ID;
1689	eflags &= uMask;
1690
1691	#ifndef IN_RING0
1692	CPUMRawSetEFlags(pVM, pRegFrame, eflags);
1693	#endif
1694	Assert((pRegFrame->eflags.u32 & (X86_EFL_IF\|X86_EFL_IOPL)) == X86_EFL_IF);
1695
1696	pRegFrame->esp = esp;
1697	pRegFrame->ss = ss;
1698	pRegFrame->ds = ds;
1699	pRegFrame->es = es;
1700	pRegFrame->fs = fs;
1701	pRegFrame->gs = gs;
1702
1703	return VINF_SUCCESS;
1704	}
1705	#endif
1706
1707	/**
1708	* IRET Emulation.
1709	*/
1710	static int emInterpretIret(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1711	{
1712	/* only allow direct calls to EMInterpretIret for now */
1713	return VERR_EM_INTERPRETER;
1714	}
1715
1716	/**
1717	* INVLPG Emulation.
1718	*/
1719
1720	/**
1721	* Interpret INVLPG
1722	*
1723	* @returns VBox status code.
1724	* @param pVM The VM handle.
1725	* @param pRegFrame The register frame.
1726	* @param pAddrGC Operand address
1727	*
1728	*/
1729	EMDECL(int) EMInterpretInvlpg(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC)
1730	{
1731	int rc;
1732
1733	/** @todo is addr always a flat linear address or ds based
1734	* (in absence of segment override prefixes)????
1735	*/
1736	#ifdef IN_GC
1737	// Note: we could also use PGMFlushPage here, but it currently doesn't always use invlpg!!!!!!!!!!
1738	LogFlow(("GC: EMULATE: invlpg %08X\n", pAddrGC));
1739	rc = PGMGCInvalidatePage(pVM, pAddrGC);
1740	#else
1741	rc = PGMInvalidatePage(pVM, pAddrGC);
1742	#endif
1743	if (VBOX_SUCCESS(rc))
1744	return VINF_SUCCESS;
1745	Log(("PGMInvalidatePage %VGv returned %VGv (%d)\n", pAddrGC, rc, rc));
1746	Assert(rc == VERR_REM_FLUSHED_PAGES_OVERFLOW);
1747	/** @todo r=bird: we shouldn't ignore returns codes like this... I'm 99% sure the error is fatal. */
1748	return VERR_EM_INTERPRETER;
1749	}
1750
1751	static int emInterpretInvlPg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1752	{
1753	OP_PARAMVAL param1;
1754	RTGCPTR addr;
1755
1756	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1757	if(VBOX_FAILURE(rc))
1758	return VERR_EM_INTERPRETER;
1759
1760	switch(param1.type)
1761	{
1762	case PARMTYPE_IMMEDIATE:
1763	case PARMTYPE_ADDRESS:
1764	if(!(param1.flags & (PARAM_VAL32\|PARAM_VAL64)))
1765	return VERR_EM_INTERPRETER;
1766	addr = (RTGCPTR)param1.val.val64;
1767	break;
1768
1769	default:
1770	return VERR_EM_INTERPRETER;
1771	}
1772
1773	/** @todo is addr always a flat linear address or ds based
1774	* (in absence of segment override prefixes)????
1775	*/
1776	#ifdef IN_GC
1777	// Note: we could also use PGMFlushPage here, but it currently doesn't always use invlpg!!!!!!!!!!
1778	LogFlow(("GC: EMULATE: invlpg %08X\n", addr));
1779	rc = PGMGCInvalidatePage(pVM, addr);
1780	#else
1781	rc = PGMInvalidatePage(pVM, addr);
1782	#endif
1783	if (VBOX_SUCCESS(rc))
1784	return VINF_SUCCESS;
1785	/** @todo r=bird: we shouldn't ignore returns codes like this... I'm 99% sure the error is fatal. */
1786	return VERR_EM_INTERPRETER;
1787	}
1788
1789	/**
1790	* CPUID Emulation.
1791	*/
1792
1793	/**
1794	* Interpret CPUID given the parameters in the CPU context
1795	*
1796	* @returns VBox status code.
1797	* @param pVM The VM handle.
1798	* @param pRegFrame The register frame.
1799	*
1800	*/
1801	EMDECL(int) EMInterpretCpuId(PVM pVM, PCPUMCTXCORE pRegFrame)
1802	{
1803	uint32_t iLeaf = pRegFrame->eax; NOREF(iLeaf);
1804
1805	/* Note: operates the same in 64 and non-64 bits mode. */
1806	CPUMGetGuestCpuId(pVM, pRegFrame->eax, &pRegFrame->eax, &pRegFrame->ebx, &pRegFrame->ecx, &pRegFrame->edx);
1807	Log(("Emulate: CPUID %x -> %08x %08x %08x %08x\n", iLeaf, pRegFrame->eax, pRegFrame->ebx, pRegFrame->ecx, pRegFrame->edx));
1808	return VINF_SUCCESS;
1809	}
1810
1811	static int emInterpretCpuId(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1812	{
1813	int rc = EMInterpretCpuId(pVM, pRegFrame);
1814	return rc;
1815	}
1816
1817	/**
1818	* MOV CRx Emulation.
1819	*/
1820
1821	/**
1822	* Interpret CRx read
1823	*
1824	* @returns VBox status code.
1825	* @param pVM The VM handle.
1826	* @param pRegFrame The register frame.
1827	* @param DestRegGen General purpose register index (USE_REG_E**))
1828	* @param SrcRegCRx CRx register index (USE_REG_CR*)
1829	*
1830	*/
1831	EMDECL(int) EMInterpretCRxRead(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx)
1832	{
1833	int rc;
1834	uint64_t val64;
1835
1836	if (SrcRegCrx == USE_REG_CR8)
1837	{
1838	val64 = 0;
1839	rc = PDMApicGetTPR(pVM, (uint8_t *)&val64, NULL);
1840	AssertMsgRCReturn(rc, ("PDMApicGetTPR failed\n"), VERR_EM_INTERPRETER);
1841	}
1842	else
1843	{
1844	rc = CPUMGetGuestCRx(pVM, SrcRegCrx, &val64);
1845	AssertMsgRCReturn(rc, ("CPUMGetGuestCRx %d failed\n", SrcRegCrx), VERR_EM_INTERPRETER);
1846	}
1847
1848	if (CPUMIsGuestIn64BitCode(pVM, pRegFrame))
1849	rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
1850	else
1851	rc = DISWriteReg32(pRegFrame, DestRegGen, val64);
1852
1853	if(VBOX_SUCCESS(rc))
1854	{
1855	LogFlow(("MOV_CR: gen32=%d CR=%d val=%VX64\n", DestRegGen, SrcRegCrx, val64));
1856	return VINF_SUCCESS;
1857	}
1858	return VERR_EM_INTERPRETER;
1859	}
1860
1861
1862	/**
1863	* Interpret LMSW
1864	*
1865	* @returns VBox status code.
1866	* @param pVM The VM handle.
1867	* @param u16Data LMSW source data.
1868	*
1869	*/
1870	EMDECL(int) EMInterpretLMSW(PVM pVM, uint16_t u16Data)
1871	{
1872	uint64_t OldCr0 = CPUMGetGuestCR0(pVM);
1873
1874	/* don't use this path to go into protected mode! */
1875	Assert(OldCr0 & X86_CR0_PE);
1876	if (!(OldCr0 & X86_CR0_PE))
1877	return VERR_EM_INTERPRETER;
1878
1879	/* Only PE, MP, EM and TS can be changed; note that PE can't be cleared by this instruction. */
1880	uint64_t NewCr0 = ( OldCr0 & ~( X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
1881	\| (u16Data & (X86_CR0_PE \| X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS));
1882
1883	#ifdef IN_GC
1884	/* Need to change the hyper CR0? Doing it the lazy way then. */
1885	if ( (OldCr0 & (X86_CR0_AM \| X86_CR0_WP))
1886	!= (NewCr0 & (X86_CR0_AM \| X86_CR0_WP)))
1887	{
1888	Log(("EMInterpretLMSW: CR0: %#x->%#x => R3\n", OldCr0, NewCr0));
1889	VM_FF_SET(pVM, VM_FF_TO_R3);
1890	}
1891	#endif
1892
1893	return CPUMSetGuestCR0(pVM, NewCr0);
1894	}
1895
1896
1897	/**
1898	* Interpret CLTS
1899	*
1900	* @returns VBox status code.
1901	* @param pVM The VM handle.
1902	*
1903	*/
1904	EMDECL(int) EMInterpretCLTS(PVM pVM)
1905	{
1906	uint64_t cr0 = CPUMGetGuestCR0(pVM);
1907	if (!(cr0 & X86_CR0_TS))
1908	return VINF_SUCCESS;
1909	return CPUMSetGuestCR0(pVM, cr0 & ~X86_CR0_TS);
1910	}
1911
1912	static int emInterpretClts(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1913	{
1914	return EMInterpretCLTS(pVM);
1915	}
1916
1917	/**
1918	* Interpret CRx write
1919	*
1920	* @returns VBox status code.
1921	* @param pVM The VM handle.
1922	* @param pRegFrame The register frame.
1923	* @param DestRegCRx CRx register index (USE_REG_CR*)
1924	* @param SrcRegGen General purpose register index (USE_REG_E**))
1925	*
1926	*/
1927	EMDECL(int) EMInterpretCRxWrite(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint32_t SrcRegGen)
1928	{
1929	uint64_t val;
1930	uint64_t oldval;
1931	uint64_t msrEFER;
1932	int rc;
1933
1934	/** @todo Clean up this mess. */
1935	if (CPUMIsGuestIn64BitCode(pVM, pRegFrame))
1936	{
1937	rc = DISFetchReg64(pRegFrame, SrcRegGen, &val);
1938	}
1939	else
1940	{
1941	uint32_t val32;
1942	rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
1943	val = val32;
1944	}
1945
1946	if (VBOX_SUCCESS(rc))
1947	{
1948	switch (DestRegCrx)
1949	{
1950	case USE_REG_CR0:
1951	oldval = CPUMGetGuestCR0(pVM);
1952	#ifdef IN_GC
1953	/* CR0.WP and CR0.AM changes require a reschedule run in ring 3. */
1954	if ( (val & (X86_CR0_WP \| X86_CR0_AM))
1955	!= (oldval & (X86_CR0_WP \| X86_CR0_AM)))
1956	return VERR_EM_INTERPRETER;
1957	#endif
1958	CPUMSetGuestCR0(pVM, val);
1959	val = CPUMGetGuestCR0(pVM);
1960	if ( (oldval & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE))
1961	!= (val & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE)))
1962	{
1963	/* global flush */
1964	rc = PGMFlushTLB(pVM, CPUMGetGuestCR3(pVM), true /* global */);
1965	AssertRCReturn(rc, rc);
1966	}
1967
1968	/* Deal with long mode enabling/disabling. */
1969	msrEFER = CPUMGetGuestEFER(pVM);
1970	if (msrEFER & MSR_K6_EFER_LME)
1971	{
1972	if ( !(oldval & X86_CR0_PG)
1973	&& (val & X86_CR0_PG))
1974	{
1975	/* Illegal to have an active 64 bits CS selector (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1976	if (pRegFrame->csHid.Attr.n.u1Long)
1977	{
1978	AssertMsgFailed(("Illegal enabling of paging with CS.u1Long = 1!!\n"));
1979	return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
1980	}
1981
1982	/* Illegal to switch to long mode before activating PAE first (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1983	if (!(CPUMGetGuestCR4(pVM) & X86_CR4_PAE))
1984	{
1985	AssertMsgFailed(("Illegal enabling of paging with PAE disabled!!\n"));
1986	return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
1987	}
1988
1989	msrEFER \|= MSR_K6_EFER_LMA;
1990	}
1991	else
1992	if ( (oldval & X86_CR0_PG)
1993	&& !(val & X86_CR0_PG))
1994	{
1995	msrEFER &= ~MSR_K6_EFER_LMA;
1996	/* @todo Do we need to cut off rip here? High dword of rip is undefined, so it shouldn't really matter. */
1997	}
1998	CPUMSetGuestEFER(pVM, msrEFER);
1999	}
2000	return PGMChangeMode(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR4(pVM), CPUMGetGuestEFER(pVM));
2001
2002	case USE_REG_CR2:
2003	rc = CPUMSetGuestCR2(pVM, val); AssertRC(rc);
2004	return VINF_SUCCESS;
2005
2006	case USE_REG_CR3:
2007	/* Reloading the current CR3 means the guest just wants to flush the TLBs */
2008	rc = CPUMSetGuestCR3(pVM, val); AssertRC(rc);
2009	if (CPUMGetGuestCR0(pVM) & X86_CR0_PG)
2010	{
2011	/* flush */
2012	rc = PGMFlushTLB(pVM, val, !(CPUMGetGuestCR4(pVM) & X86_CR4_PGE));
2013	AssertRCReturn(rc, rc);
2014	}
2015	return VINF_SUCCESS;
2016
2017	case USE_REG_CR4:
2018	oldval = CPUMGetGuestCR4(pVM);
2019	rc = CPUMSetGuestCR4(pVM, val); AssertRC(rc);
2020	val = CPUMGetGuestCR4(pVM);
2021
2022	msrEFER = CPUMGetGuestEFER(pVM);
2023	/* Illegal to disable PAE when long mode is active. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
2024	if ( (msrEFER & MSR_K6_EFER_LMA)
2025	&& (oldval & X86_CR4_PAE)
2026	&& !(val & X86_CR4_PAE))
2027	{
2028	return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
2029	}
2030
2031	if ( (oldval & (X86_CR4_PGE\|X86_CR4_PAE\|X86_CR4_PSE))
2032	!= (val & (X86_CR4_PGE\|X86_CR4_PAE\|X86_CR4_PSE)))
2033	{
2034	/* global flush */
2035	rc = PGMFlushTLB(pVM, CPUMGetGuestCR3(pVM), true /* global */);
2036	AssertRCReturn(rc, rc);
2037	}
2038	# ifdef IN_GC
2039	/* Feeling extremely lazy. */
2040	if ( (oldval & (X86_CR4_OSFSXR\|X86_CR4_OSXMMEEXCPT\|X86_CR4_PCE\|X86_CR4_MCE\|X86_CR4_PAE\|X86_CR4_DE\|X86_CR4_TSD\|X86_CR4_PVI\|X86_CR4_VME))
2041	!= (val & (X86_CR4_OSFSXR\|X86_CR4_OSXMMEEXCPT\|X86_CR4_PCE\|X86_CR4_MCE\|X86_CR4_PAE\|X86_CR4_DE\|X86_CR4_TSD\|X86_CR4_PVI\|X86_CR4_VME)))
2042	{
2043	Log(("emInterpretMovCRx: CR4: %#RX64->%#RX64 => R3\n", oldval, val));
2044	VM_FF_SET(pVM, VM_FF_TO_R3);
2045	}
2046	# endif
2047	return PGMChangeMode(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR4(pVM), CPUMGetGuestEFER(pVM));
2048
2049	case USE_REG_CR8:
2050	return PDMApicSetTPR(pVM, val);
2051
2052	default:
2053	AssertFailed();
2054	case USE_REG_CR1: /* illegal op */
2055	break;
2056	}
2057	}
2058	return VERR_EM_INTERPRETER;
2059	}
2060
2061	static int emInterpretMovCRx(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2062	{
2063	if ((pCpu->param1.flags == USE_REG_GEN32 \|\| pCpu->param1.flags == USE_REG_GEN64) && pCpu->param2.flags == USE_REG_CR)
2064	return EMInterpretCRxRead(pVM, pRegFrame, pCpu->param1.base.reg_gen, pCpu->param2.base.reg_ctrl);
2065
2066	if (pCpu->param1.flags == USE_REG_CR && (pCpu->param2.flags == USE_REG_GEN32 \|\| pCpu->param2.flags == USE_REG_GEN64))
2067	return EMInterpretCRxWrite(pVM, pRegFrame, pCpu->param1.base.reg_ctrl, pCpu->param2.base.reg_gen);
2068
2069	AssertMsgFailedReturn(("Unexpected control register move\n"), VERR_EM_INTERPRETER);
2070	return VERR_EM_INTERPRETER;
2071	}
2072
2073	/**
2074	* MOV DRx
2075	*/
2076
2077	/**
2078	* Interpret DRx write
2079	*
2080	* @returns VBox status code.
2081	* @param pVM The VM handle.
2082	* @param pRegFrame The register frame.
2083	* @param DestRegDRx DRx register index (USE_REG_DR*)
2084	* @param SrcRegGen General purpose register index (USE_REG_E**))
2085	*
2086	*/
2087	EMDECL(int) EMInterpretDRxWrite(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen)
2088	{
2089	uint64_t val;
2090	int rc;
2091
2092	if (CPUMIsGuestIn64BitCode(pVM, pRegFrame))
2093	{
2094	rc = DISFetchReg64(pRegFrame, SrcRegGen, &val);
2095	}
2096	else
2097	{
2098	uint32_t val32;
2099	rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
2100	val = val32;
2101	}
2102
2103	if (VBOX_SUCCESS(rc))
2104	{
2105	rc = CPUMSetGuestDRx(pVM, DestRegDrx, val);
2106	if (VBOX_SUCCESS(rc))
2107	return rc;
2108	AssertMsgFailed(("CPUMSetGuestDRx %d failed\n", DestRegDrx));
2109	}
2110	return VERR_EM_INTERPRETER;
2111	}
2112
2113	/**
2114	* Interpret DRx read
2115	*
2116	* @returns VBox status code.
2117	* @param pVM The VM handle.
2118	* @param pRegFrame The register frame.
2119	* @param DestRegGen General purpose register index (USE_REG_E**))
2120	* @param SrcRegDRx DRx register index (USE_REG_DR*)
2121	*
2122	*/
2123	EMDECL(int) EMInterpretDRxRead(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx)
2124	{
2125	uint64_t val64;
2126
2127	int rc = CPUMGetGuestDRx(pVM, SrcRegDrx, &val64);
2128	AssertMsgRCReturn(rc, ("CPUMGetGuestDRx %d failed\n", SrcRegDrx), VERR_EM_INTERPRETER);
2129	if (CPUMIsGuestIn64BitCode(pVM, pRegFrame))
2130	{
2131	rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
2132	}
2133	else
2134	rc = DISWriteReg32(pRegFrame, DestRegGen, (uint32_t)val64);
2135
2136	if (VBOX_SUCCESS(rc))
2137	return VINF_SUCCESS;
2138
2139	return VERR_EM_INTERPRETER;
2140	}
2141
2142	static int emInterpretMovDRx(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2143	{
2144	int rc = VERR_EM_INTERPRETER;
2145
2146	if((pCpu->param1.flags == USE_REG_GEN32 \|\| pCpu->param1.flags == USE_REG_GEN64) && pCpu->param2.flags == USE_REG_DBG)
2147	{
2148	rc = EMInterpretDRxRead(pVM, pRegFrame, pCpu->param1.base.reg_gen, pCpu->param2.base.reg_dbg);
2149	}
2150	else
2151	if(pCpu->param1.flags == USE_REG_DBG && (pCpu->param2.flags == USE_REG_GEN32 \|\| pCpu->param2.flags == USE_REG_GEN64))
2152	{
2153	rc = EMInterpretDRxWrite(pVM, pRegFrame, pCpu->param1.base.reg_dbg, pCpu->param2.base.reg_gen);
2154	}
2155	else
2156	AssertMsgFailed(("Unexpected debug register move\n"));
2157
2158	return rc;
2159	}
2160
2161	/**
2162	* LLDT Emulation.
2163	*/
2164	static int emInterpretLLdt(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2165	{
2166	OP_PARAMVAL param1;
2167	RTSEL sel;
2168
2169	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
2170	if(VBOX_FAILURE(rc))
2171	return VERR_EM_INTERPRETER;
2172
2173	switch(param1.type)
2174	{
2175	case PARMTYPE_ADDRESS:
2176	return VERR_EM_INTERPRETER; //feeling lazy right now
2177
2178	case PARMTYPE_IMMEDIATE:
2179	if(!(param1.flags & PARAM_VAL16))
2180	return VERR_EM_INTERPRETER;
2181	sel = (RTSEL)param1.val.val16;
2182	break;
2183
2184	default:
2185	return VERR_EM_INTERPRETER;
2186	}
2187
2188	if (sel == 0)
2189	{
2190	if (CPUMGetHyperLDTR(pVM) == 0)
2191	{
2192	// this simple case is most frequent in Windows 2000 (31k - boot & shutdown)
2193	return VINF_SUCCESS;
2194	}
2195	}
2196	//still feeling lazy
2197	return VERR_EM_INTERPRETER;
2198	}
2199
2200	#ifdef IN_GC
2201	/**
2202	* STI Emulation.
2203	*
2204	* @remark the instruction following sti is guaranteed to be executed before any interrupts are dispatched
2205	*/
2206	static int emInterpretSti(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2207	{
2208	PPATMGCSTATE pGCState = PATMQueryGCState(pVM);
2209
2210	if(!pGCState)
2211	{
2212	Assert(pGCState);
2213	return VERR_EM_INTERPRETER;
2214	}
2215	pGCState->uVMFlags \|= X86_EFL_IF;
2216
2217	Assert(pRegFrame->eflags.u32 & X86_EFL_IF);
2218	Assert(pvFault == SELMToFlat(pVM, DIS_SELREG_CS, pRegFrame, (RTGCPTR)pRegFrame->rip));
2219
2220	pVM->em.s.GCPtrInhibitInterrupts = pRegFrame->eip + pCpu->opsize;
2221	VM_FF_SET(pVM, VM_FF_INHIBIT_INTERRUPTS);
2222
2223	return VINF_SUCCESS;
2224	}
2225	#endif /* IN_GC */
2226
2227
2228	/**
2229	* HLT Emulation.
2230	*/
2231	static int emInterpretHlt(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2232	{
2233	return VINF_EM_HALT;
2234	}
2235
2236
2237	/**
2238	* RDTSC Emulation.
2239	*/
2240
2241	/**
2242	* Interpret RDTSC
2243	*
2244	* @returns VBox status code.
2245	* @param pVM The VM handle.
2246	* @param pRegFrame The register frame.
2247	*
2248	*/
2249	EMDECL(int) EMInterpretRdtsc(PVM pVM, PCPUMCTXCORE pRegFrame)
2250	{
2251	unsigned uCR4 = CPUMGetGuestCR4(pVM);
2252
2253	if (uCR4 & X86_CR4_TSD)
2254	return VERR_EM_INTERPRETER; /* genuine #GP */
2255
2256	uint64_t uTicks = TMCpuTickGet(pVM);
2257
2258	/* Same behaviour in 32 & 64 bits mode */
2259	pRegFrame->eax = uTicks;
2260	pRegFrame->edx = (uTicks >> 32ULL);
2261
2262	return VINF_SUCCESS;
2263	}
2264
2265	static int emInterpretRdtsc(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2266	{
2267	return EMInterpretRdtsc(pVM, pRegFrame);
2268	}
2269
2270	/**
2271	* MONITOR Emulation.
2272	*/
2273	static int emInterpretMonitor(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2274	{
2275	uint32_t u32Dummy, u32ExtFeatures, cpl;
2276
2277	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
2278	if (pRegFrame->ecx != 0)
2279	return VERR_EM_INTERPRETER; /* illegal value. */
2280
2281	/* Get the current privilege level. */
2282	cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2283	if (cpl != 0)
2284	return VERR_EM_INTERPRETER; /* supervisor only */
2285
2286	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
2287	if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
2288	return VERR_EM_INTERPRETER; /* not supported */
2289
2290	return VINF_SUCCESS;
2291	}
2292
2293
2294	/**
2295	* MWAIT Emulation.
2296	*/
2297	static int emInterpretMWait(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2298	{
2299	uint32_t u32Dummy, u32ExtFeatures, cpl;
2300
2301	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
2302	if (pRegFrame->ecx != 0)
2303	return VERR_EM_INTERPRETER; /* illegal value. */
2304
2305	/* Get the current privilege level. */
2306	cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2307	if (cpl != 0)
2308	return VERR_EM_INTERPRETER; /* supervisor only */
2309
2310	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
2311	if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
2312	return VERR_EM_INTERPRETER; /* not supported */
2313
2314	/** @todo not completely correct */
2315	return VINF_EM_HALT;
2316	}
2317
2318	#ifdef LOG_ENABLED
2319	static const char *emMSRtoString(unsigned uMsr)
2320	{
2321	switch(uMsr)
2322	{
2323	case MSR_IA32_APICBASE:
2324	return "MSR_IA32_APICBASE";
2325	case MSR_IA32_CR_PAT:
2326	return "MSR_IA32_CR_PAT";
2327	case MSR_IA32_SYSENTER_CS:
2328	return "MSR_IA32_SYSENTER_CS";
2329	case MSR_IA32_SYSENTER_EIP:
2330	return "MSR_IA32_SYSENTER_EIP";
2331	case MSR_IA32_SYSENTER_ESP:
2332	return "MSR_IA32_SYSENTER_ESP";
2333	case MSR_K6_EFER:
2334	return "MSR_K6_EFER";
2335	case MSR_K8_SF_MASK:
2336	return "MSR_K8_SF_MASK";
2337	case MSR_K6_STAR:
2338	return "MSR_K6_STAR";
2339	case MSR_K8_LSTAR:
2340	return "MSR_K8_LSTAR";
2341	case MSR_K8_CSTAR:
2342	return "MSR_K8_CSTAR";
2343	case MSR_K8_FS_BASE:
2344	return "MSR_K8_FS_BASE";
2345	case MSR_K8_GS_BASE:
2346	return "MSR_K8_GS_BASE";
2347	case MSR_K8_KERNEL_GS_BASE:
2348	return "MSR_K8_KERNEL_GS_BASE";
2349	case MSR_IA32_TSC:
2350	return "Unsupported MSR_IA32_TSC";
2351	case MSR_IA32_MTRR_CAP:
2352	return "Unsupported MSR_IA32_MTRR_CAP";
2353	case MSR_IA32_MCP_CAP:
2354	return "Unsupported MSR_IA32_MCP_CAP";
2355	case MSR_IA32_MCP_STATUS:
2356	return "Unsupported MSR_IA32_MCP_STATUS";
2357	case MSR_IA32_MCP_CTRL:
2358	return "Unsupported MSR_IA32_MCP_CTRL";
2359	case MSR_IA32_MTRR_DEF_TYPE:
2360	return "Unsupported MSR_IA32_MTRR_DEF_TYPE";
2361	case MSR_K7_EVNTSEL0:
2362	return "Unsupported MSR_K7_EVNTSEL0";
2363	case MSR_K7_EVNTSEL1:
2364	return "Unsupported MSR_K7_EVNTSEL1";
2365	case MSR_K7_EVNTSEL2:
2366	return "Unsupported MSR_K7_EVNTSEL2";
2367	case MSR_K7_EVNTSEL3:
2368	return "Unsupported MSR_K7_EVNTSEL3";
2369	}
2370	return "Unknown MSR";
2371	}
2372	#endif
2373
2374	/**
2375	* Interpret RDMSR
2376	*
2377	* @returns VBox status code.
2378	* @param pVM The VM handle.
2379	* @param pRegFrame The register frame.
2380	*
2381	*/
2382	EMDECL(int) EMInterpretRdmsr(PVM pVM, PCPUMCTXCORE pRegFrame)
2383	{
2384	uint32_t u32Dummy, u32Features, cpl;
2385	uint64_t val;
2386	CPUMCTX *pCtx;
2387	int rc;
2388
2389	/** @todo According to the Intel manuals, there's a REX version of RDMSR that is slightly different.
2390	* That version clears the high dwords of both RDX & RAX */
2391	rc = CPUMQueryGuestCtxPtr(pVM, &pCtx);
2392	AssertRC(rc);
2393
2394	/* Get the current privilege level. */
2395	cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2396	if (cpl != 0)
2397	return VERR_EM_INTERPRETER; /* supervisor only */
2398
2399	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2400	if (!(u32Features & X86_CPUID_FEATURE_EDX_MSR))
2401	return VERR_EM_INTERPRETER; /* not supported */
2402
2403	switch (pRegFrame->ecx)
2404	{
2405	case MSR_IA32_APICBASE:
2406	rc = PDMApicGetBase(pVM, &val);
2407	AssertRC(rc);
2408	break;
2409
2410	case MSR_IA32_CR_PAT:
2411	val = pCtx->msrPAT;
2412	break;
2413
2414	case MSR_IA32_SYSENTER_CS:
2415	val = pCtx->SysEnter.cs;
2416	break;
2417
2418	case MSR_IA32_SYSENTER_EIP:
2419	val = pCtx->SysEnter.eip;
2420	break;
2421
2422	case MSR_IA32_SYSENTER_ESP:
2423	val = pCtx->SysEnter.esp;
2424	break;
2425
2426	case MSR_K6_EFER:
2427	val = pCtx->msrEFER;
2428	break;
2429
2430	case MSR_K8_SF_MASK:
2431	val = pCtx->msrSFMASK;
2432	break;
2433
2434	case MSR_K6_STAR:
2435	val = pCtx->msrSTAR;
2436	break;
2437
2438	case MSR_K8_LSTAR:
2439	val = pCtx->msrLSTAR;
2440	break;
2441
2442	case MSR_K8_CSTAR:
2443	val = pCtx->msrCSTAR;
2444	break;
2445
2446	case MSR_K8_FS_BASE:
2447	val = pCtx->fsHid.u64Base;
2448	break;
2449
2450	case MSR_K8_GS_BASE:
2451	val = pCtx->gsHid.u64Base;
2452	break;
2453
2454	case MSR_K8_KERNEL_GS_BASE:
2455	val = pCtx->msrKERNELGSBASE;
2456	break;
2457
2458	default:
2459	/* We should actually trigger a #GP here, but don't as that might cause more trouble. */
2460	val = 0;
2461	break;
2462	}
2463	Log(("EMInterpretRdmsr %s (%x) -> val=%VX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx, val));
2464	pRegFrame->eax = (uint32_t) val;
2465	pRegFrame->edx = (uint32_t) (val >> 32ULL);
2466	return VINF_SUCCESS;
2467	}
2468
2469	/**
2470	* RDMSR Emulation.
2471	*/
2472	static int emInterpretRdmsr(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2473	{
2474	/* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
2475	Assert(!(pCpu->prefix & PREFIX_REX));
2476	return EMInterpretRdmsr(pVM, pRegFrame);
2477	}
2478
2479	/**
2480	* Interpret WRMSR
2481	*
2482	* @returns VBox status code.
2483	* @param pVM The VM handle.
2484	* @param pRegFrame The register frame.
2485	*
2486	*/
2487	EMDECL(int) EMInterpretWrmsr(PVM pVM, PCPUMCTXCORE pRegFrame)
2488	{
2489	uint32_t u32Dummy, u32Features, cpl;
2490	uint64_t val;
2491	CPUMCTX *pCtx;
2492	int rc;
2493
2494	/* Note: works the same in 32 and 64 bits modes. */
2495	rc = CPUMQueryGuestCtxPtr(pVM, &pCtx);
2496	AssertRC(rc);
2497
2498	/* Get the current privilege level. */
2499	cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2500	if (cpl != 0)
2501	return VERR_EM_INTERPRETER; /* supervisor only */
2502
2503	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2504	if (!(u32Features & X86_CPUID_FEATURE_EDX_MSR))
2505	return VERR_EM_INTERPRETER; /* not supported */
2506
2507	val = (uint64_t)pRegFrame->eax \| ((uint64_t)pRegFrame->edx << 32ULL);
2508	Log(("EMInterpretWrmsr %s (%x) val=%VX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx, val));
2509	switch (pRegFrame->ecx)
2510	{
2511	case MSR_IA32_APICBASE:
2512	rc = PDMApicSetBase(pVM, val);
2513	AssertRC(rc);
2514	break;
2515
2516	case MSR_IA32_CR_PAT:
2517	pCtx->msrPAT = val;
2518	break;
2519
2520	case MSR_IA32_SYSENTER_CS:
2521	pCtx->SysEnter.cs = val & 0xffff; /* 16 bits selector */
2522	break;
2523
2524	case MSR_IA32_SYSENTER_EIP:
2525	pCtx->SysEnter.eip = val;
2526	break;
2527
2528	case MSR_IA32_SYSENTER_ESP:
2529	pCtx->SysEnter.esp = val;
2530	break;
2531
2532	case MSR_K6_EFER:
2533	{
2534	uint64_t uMask = 0;
2535	uint64_t oldval = pCtx->msrEFER;
2536
2537	/* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
2538	CPUMGetGuestCpuId(pVM, 0x80000001, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2539	if (u32Features & X86_CPUID_AMD_FEATURE_EDX_NX)
2540	uMask \|= MSR_K6_EFER_NXE;
2541	if (u32Features & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE)
2542	uMask \|= MSR_K6_EFER_LME;
2543	if (u32Features & X86_CPUID_AMD_FEATURE_EDX_SEP)
2544	uMask \|= MSR_K6_EFER_SCE;
2545	if (u32Features & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
2546	uMask \|= MSR_K6_EFER_FFXSR;
2547
2548	/* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
2549	if ( ((pCtx->msrEFER & MSR_K6_EFER_LME) != (val & uMask & MSR_K6_EFER_LME))
2550	&& (pCtx->cr0 & X86_CR0_PG))
2551	{
2552	AssertMsgFailed(("Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
2553	return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
2554	}
2555
2556	/* There are a few more: e.g. MSR_K6_EFER_LMSLE */
2557	AssertMsg(!(val & ~(MSR_K6_EFER_NXE\|MSR_K6_EFER_LME\|MSR_K6_EFER_LMA /* ignored anyway */ \|MSR_K6_EFER_SCE\|MSR_K6_EFER_FFXSR)), ("Unexpected value %RX64\n", val));
2558	pCtx->msrEFER = (pCtx->msrEFER & ~uMask) \| (val & uMask);
2559
2560	/* AMD64 Achitecture Programmer's Manual: 15.15 TLB Control; flush the TLB if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
2561	if ((oldval & (MSR_K6_EFER_NXE\|MSR_K6_EFER_LME\|MSR_K6_EFER_LMA)) != (pCtx->msrEFER & (MSR_K6_EFER_NXE\|MSR_K6_EFER_LME\|MSR_K6_EFER_LMA)))
2562	HWACCMFlushTLB(pVM);
2563
2564	break;
2565	}
2566
2567	case MSR_K8_SF_MASK:
2568	pCtx->msrSFMASK = val;
2569	break;
2570
2571	case MSR_K6_STAR:
2572	pCtx->msrSTAR = val;
2573	break;
2574
2575	case MSR_K8_LSTAR:
2576	pCtx->msrLSTAR = val;
2577	break;
2578
2579	case MSR_K8_CSTAR:
2580	pCtx->msrCSTAR = val;
2581	break;
2582
2583	case MSR_K8_FS_BASE:
2584	pCtx->fsHid.u64Base = val;
2585	break;
2586
2587	case MSR_K8_GS_BASE:
2588	pCtx->gsHid.u64Base = val;
2589	break;
2590
2591	case MSR_K8_KERNEL_GS_BASE:
2592	pCtx->msrKERNELGSBASE = val;
2593	break;
2594
2595	default:
2596	/* We should actually trigger a #GP here, but don't as that might cause more trouble. */
2597	break;
2598	}
2599	return VINF_SUCCESS;
2600	}
2601
2602	/**
2603	* WRMSR Emulation.
2604	*/
2605	static int emInterpretWrmsr(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2606	{
2607	return EMInterpretWrmsr(pVM, pRegFrame);
2608	}
2609
2610	/**
2611	* Internal worker.
2612	* @copydoc EMInterpretInstructionCPU
2613	*/
2614	DECLINLINE(int) emInterpretInstructionCPU(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2615	{
2616	Assert(pcbSize);
2617	*pcbSize = 0;
2618
2619	/*
2620	* Only supervisor guest code!!
2621	* And no complicated prefixes.
2622	*/
2623	/* Get the current privilege level. */
2624	uint32_t cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2625	if ( cpl != 0
2626	&& pCpu->pCurInstr->opcode != OP_RDTSC) /* rdtsc requires emulation in ring 3 as well */
2627	{
2628	Log(("WARNING: refusing instruction emulation for user-mode code!!\n"));
2629	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,FailedUserMode));
2630	return VERR_EM_INTERPRETER;
2631	}
2632
2633	#ifdef IN_GC
2634	if ( (pCpu->prefix & (PREFIX_REPNE \| PREFIX_REP))
2635	\|\| ( (pCpu->prefix & PREFIX_LOCK)
2636	&& pCpu->pCurInstr->opcode != OP_CMPXCHG
2637	&& pCpu->pCurInstr->opcode != OP_CMPXCHG8B
2638	&& pCpu->pCurInstr->opcode != OP_XADD
2639	&& pCpu->pCurInstr->opcode != OP_OR
2640	&& pCpu->pCurInstr->opcode != OP_BTR
2641	)
2642	)
2643	#else
2644	if ( (pCpu->prefix & PREFIX_REPNE)
2645	\|\| ( (pCpu->prefix & PREFIX_REP)
2646	&& pCpu->pCurInstr->opcode != OP_STOSWD
2647	)
2648	\|\| ( (pCpu->prefix & PREFIX_LOCK)
2649	&& pCpu->pCurInstr->opcode != OP_OR
2650	&& pCpu->pCurInstr->opcode != OP_BTR
2651	)
2652	)
2653	#endif
2654	{
2655	//Log(("EMInterpretInstruction: wrong prefix!!\n"));
2656	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,FailedPrefix));
2657	return VERR_EM_INTERPRETER;
2658	}
2659
2660	int rc;
2661	#if (defined(VBOX_STRICT) \|\| defined(LOG_ENABLED))
2662	LogFlow(("emInterpretInstructionCPU %s\n", emGetMnemonic(pCpu)));
2663	#endif
2664	switch (pCpu->pCurInstr->opcode)
2665	{
2666	# define INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
2667	case opcode:\
2668	if (pCpu->prefix & PREFIX_LOCK) \
2669	rc = emInterpretLock##InstrFn(pVM, pCpu, pRegFrame, pvFault, pcbSize, pfnEmulateLock); \
2670	else \
2671	rc = emInterpret##InstrFn(pVM, pCpu, pRegFrame, pvFault, pcbSize, pfnEmulate); \
2672	if (VBOX_SUCCESS(rc)) \
2673	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,Instr)); \
2674	else \
2675	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,Failed##Instr)); \
2676	return rc
2677	#define INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate) \
2678	case opcode:\
2679	rc = emInterpret##InstrFn(pVM, pCpu, pRegFrame, pvFault, pcbSize, pfnEmulate); \
2680	if (VBOX_SUCCESS(rc)) \
2681	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,Instr)); \
2682	else \
2683	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,Failed##Instr)); \
2684	return rc
2685
2686	#define INTERPRET_CASE_EX_PARAM2(opcode, Instr, InstrFn, pfnEmulate) \
2687	INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate)
2688	#define INTERPRET_CASE_EX_LOCK_PARAM2(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
2689	INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock)
2690
2691	#define INTERPRET_CASE(opcode, Instr) \
2692	case opcode:\
2693	rc = emInterpret##Instr(pVM, pCpu, pRegFrame, pvFault, pcbSize); \
2694	if (VBOX_SUCCESS(rc)) \
2695	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,Instr)); \
2696	else \
2697	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,Failed##Instr)); \
2698	return rc
2699	#define INTERPRET_STAT_CASE(opcode, Instr) \
2700	case opcode: STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,Failed##Instr)); return VERR_EM_INTERPRETER;
2701
2702	INTERPRET_CASE(OP_XCHG,Xchg);
2703	INTERPRET_CASE_EX_PARAM2(OP_DEC,Dec, IncDec, EMEmulateDec);
2704	INTERPRET_CASE_EX_PARAM2(OP_INC,Inc, IncDec, EMEmulateInc);
2705	INTERPRET_CASE(OP_POP,Pop);
2706	INTERPRET_CASE_EX_LOCK_PARAM3(OP_OR, Or, OrXorAnd, EMEmulateOr, EMEmulateLockOr);
2707	INTERPRET_CASE_EX_PARAM3(OP_XOR,Xor, OrXorAnd, EMEmulateXor);
2708	INTERPRET_CASE_EX_PARAM3(OP_AND,And, OrXorAnd, EMEmulateAnd);
2709	INTERPRET_CASE(OP_MOV,Mov);
2710	#ifndef IN_GC
2711	INTERPRET_CASE(OP_STOSWD,StosWD);
2712	#endif
2713	INTERPRET_CASE(OP_INVLPG,InvlPg);
2714	INTERPRET_CASE(OP_CPUID,CpuId);
2715	INTERPRET_CASE(OP_MOV_CR,MovCRx);
2716	INTERPRET_CASE(OP_MOV_DR,MovDRx);
2717	INTERPRET_CASE(OP_LLDT,LLdt);
2718	INTERPRET_CASE(OP_CLTS,Clts);
2719	INTERPRET_CASE(OP_MONITOR, Monitor);
2720	INTERPRET_CASE(OP_MWAIT, MWait);
2721	INTERPRET_CASE(OP_RDMSR, Rdmsr);
2722	INTERPRET_CASE(OP_WRMSR, Wrmsr);
2723	INTERPRET_CASE_EX_PARAM3(OP_ADD,Add, AddSub, EMEmulateAdd);
2724	INTERPRET_CASE_EX_PARAM3(OP_SUB,Sub, AddSub, EMEmulateSub);
2725	INTERPRET_CASE(OP_ADC,Adc);
2726	INTERPRET_CASE_EX_LOCK_PARAM2(OP_BTR,Btr, BitTest, EMEmulateBtr, EMEmulateLockBtr);
2727	INTERPRET_CASE_EX_PARAM2(OP_BTS,Bts, BitTest, EMEmulateBts);
2728	INTERPRET_CASE_EX_PARAM2(OP_BTC,Btc, BitTest, EMEmulateBtc);
2729	INTERPRET_CASE(OP_RDTSC,Rdtsc);
2730	#ifdef IN_GC
2731	INTERPRET_CASE(OP_STI,Sti);
2732	INTERPRET_CASE(OP_CMPXCHG, CmpXchg);
2733	INTERPRET_CASE(OP_CMPXCHG8B, CmpXchg8b);
2734	INTERPRET_CASE(OP_XADD, XAdd);
2735	#endif
2736	INTERPRET_CASE(OP_HLT,Hlt);
2737	INTERPRET_CASE(OP_IRET,Iret);
2738	#ifdef VBOX_WITH_STATISTICS
2739	#ifndef IN_GC
2740	INTERPRET_STAT_CASE(OP_CMPXCHG,CmpXchg);
2741	INTERPRET_STAT_CASE(OP_CMPXCHG8B, CmpXchg8b);
2742	INTERPRET_STAT_CASE(OP_XADD, XAdd);
2743	#endif
2744	INTERPRET_STAT_CASE(OP_MOVNTPS,MovNTPS);
2745	INTERPRET_STAT_CASE(OP_WBINVD,WbInvd);
2746	#endif
2747	default:
2748	Log3(("emInterpretInstructionCPU: opcode=%d\n", pCpu->pCurInstr->opcode));
2749	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,FailedMisc));
2750	return VERR_EM_INTERPRETER;
2751	#undef INTERPRET_CASE_EX_PARAM2
2752	#undef INTERPRET_STAT_CASE
2753	#undef INTERPRET_CASE_EX
2754	#undef INTERPRET_CASE
2755	}
2756	AssertFailed();
2757	return VERR_INTERNAL_ERROR;
2758	}
2759
2760
2761	/**
2762	* Sets the PC for which interrupts should be inhibited.
2763	*
2764	* @param pVM The VM handle.
2765	* @param PC The PC.
2766	*/
2767	EMDECL(void) EMSetInhibitInterruptsPC(PVM pVM, RTGCUINTPTR PC)
2768	{
2769	pVM->em.s.GCPtrInhibitInterrupts = PC;
2770	VM_FF_SET(pVM, VM_FF_INHIBIT_INTERRUPTS);
2771	}
2772
2773
2774	/**
2775	* Gets the PC for which interrupts should be inhibited.
2776	*
2777	* There are a few instructions which inhibits or delays interrupts
2778	* for the instruction following them. These instructions are:
2779	* - STI
2780	* - MOV SS, r/m16
2781	* - POP SS
2782	*
2783	* @returns The PC for which interrupts should be inhibited.
2784	* @param pVM VM handle.
2785	*
2786	*/
2787	EMDECL(RTGCUINTPTR) EMGetInhibitInterruptsPC(PVM pVM)
2788	{
2789	return pVM->em.s.GCPtrInhibitInterrupts;
2790	}

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source: vbox/trunk/src/VBox/VMM/VMMAll/EMAll.cpp@ 11450

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