EMAll.cpp@ 11452

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1	/* $Id: EMAll.cpp 11452 2008-08-18 06:45:17Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor(/Manager) - All contexts
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_EM
26	#include <VBox/em.h>
27	#include <VBox/mm.h>
28	#include <VBox/selm.h>
29	#include <VBox/patm.h>
30	#include <VBox/csam.h>
31	#include <VBox/pgm.h>
32	#include <VBox/iom.h>
33	#include <VBox/stam.h>
34	#include "EMInternal.h"
35	#include <VBox/vm.h>
36	#include <VBox/hwaccm.h>
37	#include <VBox/tm.h>
38	#include <VBox/pdmapi.h>
39
40	#include <VBox/param.h>
41	#include <VBox/err.h>
42	#include <VBox/dis.h>
43	#include <VBox/disopcode.h>
44	#include <VBox/log.h>
45	#include <iprt/assert.h>
46	#include <iprt/asm.h>
47	#include <iprt/string.h>
48
49
50	/*******************************************************************************
51	* Structures and Typedefs *
52	*******************************************************************************/
53
54
55	/*******************************************************************************
56	* Internal Functions *
57	*******************************************************************************/
58	DECLINLINE(int) emInterpretInstructionCPU(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize);
59
60
61	/**
62	* Get the current execution manager status.
63	*
64	* @returns Current status.
65	*/
66	EMDECL(EMSTATE) EMGetState(PVM pVM)
67	{
68	return pVM->em.s.enmState;
69	}
70
71
72	#ifndef IN_GC
73	/**
74	* Read callback for disassembly function; supports reading bytes that cross a page boundary
75	*
76	* @returns VBox status code.
77	* @param pSrc GC source pointer
78	* @param pDest HC destination pointer
79	* @param cb Number of bytes to read
80	* @param dwUserdata Callback specific user data (pCpu)
81	*
82	*/
83	DECLCALLBACK(int) EMReadBytes(RTUINTPTR pSrc, uint8_t pDest, unsigned cb, void pvUserdata)
84	{
85	DISCPUSTATE pCpu = (DISCPUSTATE )pvUserdata;
86	PVM pVM = (PVM)pCpu->apvUserData[0];
87	#ifdef IN_RING0
88	int rc = PGMPhysReadGCPtr(pVM, pDest, pSrc, cb);
89	AssertMsgRC(rc, ("PGMPhysReadGCPtr failed for pSrc=%VGv cb=%x\n", pSrc, cb));
90	#else
91	if (!PATMIsPatchGCAddr(pVM, pSrc))
92	{
93	int rc = PGMPhysReadGCPtr(pVM, pDest, pSrc, cb);
94	AssertRC(rc);
95	}
96	else
97	{
98	for (uint32_t i = 0; i < cb; i++)
99	{
100	uint8_t opcode;
101	if (VBOX_SUCCESS(PATMR3QueryOpcode(pVM, (RTGCPTR)pSrc + i, &opcode)))
102	{
103	*(pDest+i) = opcode;
104	}
105	}
106	}
107	#endif /* IN_RING0 */
108	return VINF_SUCCESS;
109	}
110
111	DECLINLINE(int) emDisCoreOne(PVM pVM, DISCPUSTATE pCpu, RTGCUINTPTR InstrGC, uint32_t pOpsize)
112	{
113	return DISCoreOneEx(InstrGC, pCpu->mode, EMReadBytes, pVM, pCpu, pOpsize);
114	}
115
116	#else
117
118	DECLINLINE(int) emDisCoreOne(PVM pVM, DISCPUSTATE pCpu, RTGCUINTPTR InstrGC, uint32_t pOpsize)
119	{
120	return DISCoreOne(pCpu, InstrGC, pOpsize);
121	}
122
123	#endif
124
125
126	/**
127	* Disassembles one instruction.
128	*
129	* @param pVM The VM handle.
130	* @param pCtxCore The context core (used for both the mode and instruction).
131	* @param pCpu Where to return the parsed instruction info.
132	* @param pcbInstr Where to return the instruction size. (optional)
133	*/
134	EMDECL(int) EMInterpretDisasOne(PVM pVM, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, unsigned *pcbInstr)
135	{
136	RTGCPTR GCPtrInstr;
137	int rc = SELMToFlatEx(pVM, DIS_SELREG_CS, pCtxCore, pCtxCore->rip, 0, &GCPtrInstr);
138	if (VBOX_FAILURE(rc))
139	{
140	Log(("EMInterpretDisasOne: Failed to convert %RTsel:%VGv (cpl=%d) - rc=%Vrc !!\n",
141	pCtxCore->cs, pCtxCore->rip, pCtxCore->ss & X86_SEL_RPL, rc));
142	return rc;
143	}
144	return EMInterpretDisasOneEx(pVM, (RTGCUINTPTR)GCPtrInstr, pCtxCore, pCpu, pcbInstr);
145	}
146
147
148	/**
149	* Disassembles one instruction.
150	*
151	* This is used by internally by the interpreter and by trap/access handlers.
152	*
153	* @param pVM The VM handle.
154	* @param GCPtrInstr The flat address of the instruction.
155	* @param pCtxCore The context core (used to determin the cpu mode).
156	* @param pCpu Where to return the parsed instruction info.
157	* @param pcbInstr Where to return the instruction size. (optional)
158	*/
159	EMDECL(int) EMInterpretDisasOneEx(PVM pVM, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, unsigned *pcbInstr)
160	{
161	int rc = DISCoreOneEx(GCPtrInstr, SELMGetCpuModeFromSelector(pVM, pCtxCore->eflags, pCtxCore->cs, (PCPUMSELREGHID)&pCtxCore->csHid),
162	#ifdef IN_GC
163	NULL, NULL,
164	#else
165	EMReadBytes, pVM,
166	#endif
167	pCpu, pcbInstr);
168	if (VBOX_SUCCESS(rc))
169	return VINF_SUCCESS;
170	AssertMsgFailed(("DISCoreOne failed to GCPtrInstr=%VGv rc=%Vrc\n", GCPtrInstr, rc));
171	return VERR_INTERNAL_ERROR;
172	}
173
174
175	/**
176	* Interprets the current instruction.
177	*
178	* @returns VBox status code.
179	* @retval VINF_* Scheduling instructions.
180	* @retval VERR_EM_INTERPRETER Something we can't cope with.
181	* @retval VERR_* Fatal errors.
182	*
183	* @param pVM The VM handle.
184	* @param pRegFrame The register frame.
185	* Updates the EIP if an instruction was executed successfully.
186	* @param pvFault The fault address (CR2).
187	* @param pcbSize Size of the write (if applicable).
188	*
189	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
190	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
191	* to worry about e.g. invalid modrm combinations (!)
192	*/
193	EMDECL(int) EMInterpretInstruction(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
194	{
195	RTGCPTR pbCode;
196
197	LogFlow(("EMInterpretInstruction %VGv fault %VGv\n", pRegFrame->rip, pvFault));
198	int rc = SELMToFlatEx(pVM, DIS_SELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
199	if (VBOX_SUCCESS(rc))
200	{
201	uint32_t cbOp;
202	DISCPUSTATE Cpu;
203	Cpu.mode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
204	rc = emDisCoreOne(pVM, &Cpu, (RTGCUINTPTR)pbCode, &cbOp);
205	if (VBOX_SUCCESS(rc))
206	{
207	Assert(cbOp == Cpu.opsize);
208	rc = EMInterpretInstructionCPU(pVM, &Cpu, pRegFrame, pvFault, pcbSize);
209	if (VBOX_SUCCESS(rc))
210	{
211	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
212	}
213	return rc;
214	}
215	}
216	return VERR_EM_INTERPRETER;
217	}
218
219	/**
220	* Interprets the current instruction using the supplied DISCPUSTATE structure.
221	*
222	* EIP is NOT updated!
223	*
224	* @returns VBox status code.
225	* @retval VINF_* Scheduling instructions. When these are returned, it
226	* starts to get a bit tricky to know whether code was
227	* executed or not... We'll address this when it becomes a problem.
228	* @retval VERR_EM_INTERPRETER Something we can't cope with.
229	* @retval VERR_* Fatal errors.
230	*
231	* @param pVM The VM handle.
232	* @param pCpu The disassembler cpu state for the instruction to be interpreted.
233	* @param pRegFrame The register frame. EIP is NOT changed!
234	* @param pvFault The fault address (CR2).
235	* @param pcbSize Size of the write (if applicable).
236	*
237	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
238	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
239	* to worry about e.g. invalid modrm combinations (!)
240	*
241	* @todo At this time we do NOT check if the instruction overwrites vital information.
242	* Make sure this can't happen!! (will add some assertions/checks later)
243	*/
244	EMDECL(int) EMInterpretInstructionCPU(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
245	{
246	STAM_PROFILE_START(&CTXMID(pVM->em.s.CTXSUFF(pStats)->Stat,Emulate), a);
247	int rc = emInterpretInstructionCPU(pVM, pCpu, pRegFrame, pvFault, pcbSize);
248	STAM_PROFILE_STOP(&CTXMID(pVM->em.s.CTXSUFF(pStats)->Stat,Emulate), a);
249	if (VBOX_SUCCESS(rc))
250	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,InterpretSucceeded));
251	else
252	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,InterpretFailed));
253	return rc;
254	}
255
256
257	/**
258	* Interpret a port I/O instruction.
259	*
260	* @returns VBox status code suitable for scheduling.
261	* @param pVM The VM handle.
262	* @param pCtxCore The context core. This will be updated on successful return.
263	* @param pCpu The instruction to interpret.
264	* @param cbOp The size of the instruction.
265	* @remark This may raise exceptions.
266	*/
267	EMDECL(int) EMInterpretPortIO(PVM pVM, PCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, uint32_t cbOp)
268	{
269	/*
270	* Hand it on to IOM.
271	*/
272	#ifdef IN_GC
273	int rc = IOMGCIOPortHandler(pVM, pCtxCore, pCpu);
274	if (IOM_SUCCESS(rc))
275	pCtxCore->rip += cbOp;
276	return rc;
277	#else
278	AssertReleaseMsgFailed(("not implemented\n"));
279	return VERR_NOT_IMPLEMENTED;
280	#endif
281	}
282
283
284	DECLINLINE(int) emRamRead(PVM pVM, void *pDest, RTGCPTR GCSrc, uint32_t cb)
285	{
286	#ifdef IN_GC
287	int rc = MMGCRamRead(pVM, pDest, (void *)GCSrc, cb);
288	if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
289	return rc;
290	/*
291	* The page pool cache may end up here in some cases because it
292	* flushed one of the shadow mappings used by the trapping
293	* instruction and it either flushed the TLB or the CPU reused it.
294	*/
295	RTGCPHYS GCPhys;
296	rc = PGMPhysGCPtr2GCPhys(pVM, GCSrc, &GCPhys);
297	AssertRCReturn(rc, rc);
298	PGMPhysRead(pVM, GCPhys, pDest, cb);
299	return VINF_SUCCESS;
300	#else
301	return PGMPhysReadGCPtrSafe(pVM, pDest, GCSrc, cb);
302	#endif
303	}
304
305	DECLINLINE(int) emRamWrite(PVM pVM, RTGCPTR GCDest, void *pSrc, uint32_t cb)
306	{
307	#ifdef IN_GC
308	int rc = MMGCRamWrite(pVM, (void *)GCDest, pSrc, cb);
309	if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
310	return rc;
311	/*
312	* The page pool cache may end up here in some cases because it
313	* flushed one of the shadow mappings used by the trapping
314	* instruction and it either flushed the TLB or the CPU reused it.
315	* We want to play safe here, verifying that we've got write
316	* access doesn't cost us much (see PGMPhysGCPtr2GCPhys()).
317	*/
318	uint64_t fFlags;
319	RTGCPHYS GCPhys;
320	rc = PGMGstGetPage(pVM, GCDest, &fFlags, &GCPhys);
321	if (RT_FAILURE(rc))
322	return rc;
323	if ( !(fFlags & X86_PTE_RW)
324	&& (CPUMGetGuestCR0(pVM) & X86_CR0_WP))
325	return VERR_ACCESS_DENIED;
326
327	PGMPhysWrite(pVM, GCPhys + ((RTGCUINTPTR)GCDest & PAGE_OFFSET_MASK), pSrc, cb);
328	return VINF_SUCCESS;
329
330	#else
331	return PGMPhysWriteGCPtrSafe(pVM, GCDest, pSrc, cb);
332	#endif
333	}
334
335	/* Convert sel:addr to a flat GC address */
336	static RTGCPTR emConvertToFlatAddr(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, POP_PARAMETER pParam, RTGCPTR pvAddr)
337	{
338	DIS_SELREG enmPrefixSeg = DISDetectSegReg(pCpu, pParam);
339	return SELMToFlat(pVM, enmPrefixSeg, pRegFrame, pvAddr);
340	}
341
342	#if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
343	/**
344	* Get the mnemonic for the disassembled instruction.
345	*
346	* GC/R0 doesn't include the strings in the DIS tables because
347	* of limited space.
348	*/
349	static const char *emGetMnemonic(PDISCPUSTATE pCpu)
350	{
351	switch (pCpu->pCurInstr->opcode)
352	{
353	case OP_XCHG: return "Xchg";
354	case OP_DEC: return "Dec";
355	case OP_INC: return "Inc";
356	case OP_POP: return "Pop";
357	case OP_OR: return "Or";
358	case OP_AND: return "And";
359	case OP_MOV: return "Mov";
360	case OP_INVLPG: return "InvlPg";
361	case OP_CPUID: return "CpuId";
362	case OP_MOV_CR: return "MovCRx";
363	case OP_MOV_DR: return "MovDRx";
364	case OP_LLDT: return "LLdt";
365	case OP_CLTS: return "Clts";
366	case OP_MONITOR: return "Monitor";
367	case OP_MWAIT: return "MWait";
368	case OP_RDMSR: return "Rdmsr";
369	case OP_WRMSR: return "Wrmsr";
370	case OP_ADC: return "Adc";
371	case OP_BTC: return "Btc";
372	case OP_RDTSC: return "Rdtsc";
373	case OP_STI: return "Sti";
374	case OP_XADD: return "XAdd";
375	case OP_HLT: return "Hlt";
376	case OP_IRET: return "Iret";
377	case OP_CMPXCHG: return "CmpXchg";
378	case OP_CMPXCHG8B: return "CmpXchg8b";
379	case OP_MOVNTPS: return "MovNTPS";
380	case OP_STOSWD: return "StosWD";
381	case OP_WBINVD: return "WbInvd";
382	case OP_XOR: return "Xor";
383	case OP_BTR: return "Btr";
384	case OP_BTS: return "Bts";
385	default:
386	Log(("Unknown opcode %d\n", pCpu->pCurInstr->opcode));
387	return "???";
388	}
389	}
390	#endif
391
392	/**
393	* XCHG instruction emulation.
394	*/
395	static int emInterpretXchg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
396	{
397	OP_PARAMVAL param1, param2;
398
399	/* Source to make DISQueryParamVal read the register value - ugly hack */
400	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
401	if(VBOX_FAILURE(rc))
402	return VERR_EM_INTERPRETER;
403
404	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
405	if(VBOX_FAILURE(rc))
406	return VERR_EM_INTERPRETER;
407
408	#ifdef IN_GC
409	if (TRPMHasTrap(pVM))
410	{
411	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
412	{
413	#endif
414	RTGCPTR pParam1 = 0, pParam2 = 0;
415	uint64_t valpar1, valpar2;
416
417	AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
418	switch(param1.type)
419	{
420	case PARMTYPE_IMMEDIATE: /* register type is translated to this one too */
421	valpar1 = param1.val.val64;
422	break;
423
424	case PARMTYPE_ADDRESS:
425	pParam1 = (RTGCPTR)param1.val.val64;
426	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
427	#ifdef IN_GC
428	/* Safety check (in theory it could cross a page boundary and fault there though) */
429	AssertReturn(pParam1 == pvFault, VERR_EM_INTERPRETER);
430	#endif
431	rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
432	if (VBOX_FAILURE(rc))
433	{
434	AssertMsgFailed(("MMGCRamRead %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
435	return VERR_EM_INTERPRETER;
436	}
437	break;
438
439	default:
440	AssertFailed();
441	return VERR_EM_INTERPRETER;
442	}
443
444	switch(param2.type)
445	{
446	case PARMTYPE_ADDRESS:
447	pParam2 = (RTGCPTR)param2.val.val64;
448	pParam2 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param2, pParam2);
449	#ifdef IN_GC
450	/* Safety check (in theory it could cross a page boundary and fault there though) */
451	AssertReturn(pParam2 == pvFault, VERR_EM_INTERPRETER);
452	#endif
453	rc = emRamRead(pVM, &valpar2, pParam2, param2.size);
454	if (VBOX_FAILURE(rc))
455	{
456	AssertMsgFailed(("MMGCRamRead %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
457	}
458	break;
459
460	case PARMTYPE_IMMEDIATE:
461	valpar2 = param2.val.val64;
462	break;
463
464	default:
465	AssertFailed();
466	return VERR_EM_INTERPRETER;
467	}
468
469	/* Write value of parameter 2 to parameter 1 (reg or memory address) */
470	if (pParam1 == 0)
471	{
472	Assert(param1.type == PARMTYPE_IMMEDIATE); /* register actually */
473	switch(param1.size)
474	{
475	case 1: //special case for AH etc
476	rc = DISWriteReg8(pRegFrame, pCpu->param1.base.reg_gen, (uint8_t )valpar2); break;
477	case 2: rc = DISWriteReg16(pRegFrame, pCpu->param1.base.reg_gen, (uint16_t)valpar2); break;
478	case 4: rc = DISWriteReg32(pRegFrame, pCpu->param1.base.reg_gen, (uint32_t)valpar2); break;
479	case 8: rc = DISWriteReg64(pRegFrame, pCpu->param1.base.reg_gen, valpar2); break;
480	default: AssertFailedReturn(VERR_EM_INTERPRETER);
481	}
482	if (VBOX_FAILURE(rc))
483	return VERR_EM_INTERPRETER;
484	}
485	else
486	{
487	rc = emRamWrite(pVM, pParam1, &valpar2, param1.size);
488	if (VBOX_FAILURE(rc))
489	{
490	AssertMsgFailed(("emRamWrite %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
491	return VERR_EM_INTERPRETER;
492	}
493	}
494
495	/* Write value of parameter 1 to parameter 2 (reg or memory address) */
496	if (pParam2 == 0)
497	{
498	Assert(param2.type == PARMTYPE_IMMEDIATE); /* register actually */
499	switch(param2.size)
500	{
501	case 1: //special case for AH etc
502	rc = DISWriteReg8(pRegFrame, pCpu->param2.base.reg_gen, (uint8_t )valpar1); break;
503	case 2: rc = DISWriteReg16(pRegFrame, pCpu->param2.base.reg_gen, (uint16_t)valpar1); break;
504	case 4: rc = DISWriteReg32(pRegFrame, pCpu->param2.base.reg_gen, (uint32_t)valpar1); break;
505	case 8: rc = DISWriteReg64(pRegFrame, pCpu->param2.base.reg_gen, valpar1); break;
506	default: AssertFailedReturn(VERR_EM_INTERPRETER);
507	}
508	if (VBOX_FAILURE(rc))
509	return VERR_EM_INTERPRETER;
510	}
511	else
512	{
513	rc = emRamWrite(pVM, pParam2, &valpar1, param2.size);
514	if (VBOX_FAILURE(rc))
515	{
516	AssertMsgFailed(("emRamWrite %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
517	return VERR_EM_INTERPRETER;
518	}
519	}
520
521	*pcbSize = param2.size;
522	return VINF_SUCCESS;
523	#ifdef IN_GC
524	}
525	}
526	#endif
527	return VERR_EM_INTERPRETER;
528	}
529
530	/**
531	* INC and DEC emulation.
532	*/
533	static int emInterpretIncDec(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
534	PFN_EMULATE_PARAM2 pfnEmulate)
535	{
536	OP_PARAMVAL param1;
537
538	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
539	if(VBOX_FAILURE(rc))
540	return VERR_EM_INTERPRETER;
541
542	#ifdef IN_GC
543	if (TRPMHasTrap(pVM))
544	{
545	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
546	{
547	#endif
548	RTGCPTR pParam1 = 0;
549	uint64_t valpar1;
550
551	if (param1.type == PARMTYPE_ADDRESS)
552	{
553	pParam1 = (RTGCPTR)param1.val.val64;
554	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
555	#ifdef IN_GC
556	/* Safety check (in theory it could cross a page boundary and fault there though) */
557	AssertReturn(pParam1 == pvFault, VERR_EM_INTERPRETER);
558	#endif
559	rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
560	if (VBOX_FAILURE(rc))
561	{
562	AssertMsgFailed(("emRamRead %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
563	return VERR_EM_INTERPRETER;
564	}
565	}
566	else
567	{
568	AssertFailed();
569	return VERR_EM_INTERPRETER;
570	}
571
572	uint32_t eflags;
573
574	eflags = pfnEmulate(&valpar1, param1.size);
575
576	/* Write result back */
577	rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
578	if (VBOX_FAILURE(rc))
579	{
580	AssertMsgFailed(("emRamWrite %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
581	return VERR_EM_INTERPRETER;
582	}
583
584	/* Update guest's eflags and finish. */
585	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
586	\| (eflags & (X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
587
588	/* All done! */
589	*pcbSize = param1.size;
590	return VINF_SUCCESS;
591	#ifdef IN_GC
592	}
593	}
594	#endif
595	return VERR_EM_INTERPRETER;
596	}
597
598	/**
599	* POP Emulation.
600	*/
601	static int emInterpretPop(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
602	{
603	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
604	OP_PARAMVAL param1;
605	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
606	if(VBOX_FAILURE(rc))
607	return VERR_EM_INTERPRETER;
608
609	#ifdef IN_GC
610	if (TRPMHasTrap(pVM))
611	{
612	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
613	{
614	#endif
615	RTGCPTR pParam1 = 0;
616	uint32_t valpar1;
617	RTGCPTR pStackVal;
618
619	/* Read stack value first */
620	if (SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->ss, &pRegFrame->ssHid) == CPUMODE_16BIT)
621	return VERR_EM_INTERPRETER; /* No legacy 16 bits stuff here, please. */
622
623	/* Convert address; don't bother checking limits etc, as we only read here */
624	pStackVal = SELMToFlat(pVM, DIS_SELREG_SS, pRegFrame, (RTGCPTR)pRegFrame->esp);
625	if (pStackVal == 0)
626	return VERR_EM_INTERPRETER;
627
628	rc = emRamRead(pVM, &valpar1, pStackVal, param1.size);
629	if (VBOX_FAILURE(rc))
630	{
631	AssertMsgFailed(("emRamRead %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
632	return VERR_EM_INTERPRETER;
633	}
634
635	if (param1.type == PARMTYPE_ADDRESS)
636	{
637	pParam1 = (RTGCPTR)param1.val.val64;
638
639	/* pop [esp+xx] uses esp after the actual pop! */
640	AssertCompile(USE_REG_ESP == USE_REG_SP);
641	if ( (pCpu->param1.flags & USE_BASE)
642	&& (pCpu->param1.flags & (USE_REG_GEN16\|USE_REG_GEN32))
643	&& pCpu->param1.base.reg_gen == USE_REG_ESP
644	)
645	pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + param1.size);
646
647	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
648
649	#ifdef IN_GC
650	/* Safety check (in theory it could cross a page boundary and fault there though) */
651	AssertMsgReturn(pParam1 == pvFault \|\| (RTGCPTR)pRegFrame->esp == pvFault, ("%VGv != %VGv ss:esp=%04X:%08x\n", pParam1, pvFault, pRegFrame->ss, pRegFrame->esp), VERR_EM_INTERPRETER);
652	#endif
653	rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
654	if (VBOX_FAILURE(rc))
655	{
656	AssertMsgFailed(("emRamWrite %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
657	return VERR_EM_INTERPRETER;
658	}
659
660	/* Update ESP as the last step */
661	pRegFrame->esp += param1.size;
662	}
663	else
664	{
665	#ifndef DEBUG_bird // annoying assertion.
666	AssertFailed();
667	#endif
668	return VERR_EM_INTERPRETER;
669	}
670
671	/* All done! */
672	*pcbSize = param1.size;
673	return VINF_SUCCESS;
674	#ifdef IN_GC
675	}
676	}
677	#endif
678	return VERR_EM_INTERPRETER;
679	}
680
681
682	/**
683	* XOR/OR/AND Emulation.
684	*/
685	static int emInterpretOrXorAnd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
686	PFN_EMULATE_PARAM3 pfnEmulate)
687	{
688	OP_PARAMVAL param1, param2;
689	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
690	if(VBOX_FAILURE(rc))
691	return VERR_EM_INTERPRETER;
692
693	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
694	if(VBOX_FAILURE(rc))
695	return VERR_EM_INTERPRETER;
696
697	#ifdef LOG_ENABLED
698	const char *pszInstr;
699
700	if (pCpu->pCurInstr->opcode == OP_XOR)
701	pszInstr = "Xor";
702	else if (pCpu->pCurInstr->opcode == OP_OR)
703	pszInstr = "Or";
704	else if (pCpu->pCurInstr->opcode == OP_AND)
705	pszInstr = "And";
706	else
707	pszInstr = "OrXorAnd??";
708	#endif
709
710	#ifdef IN_GC
711	if (TRPMHasTrap(pVM))
712	{
713	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
714	{
715	#endif
716	RTGCPTR pParam1;
717	uint64_t valpar1, valpar2;
718
719	if (pCpu->param1.size != pCpu->param2.size)
720	{
721	if (pCpu->param1.size < pCpu->param2.size)
722	{
723	AssertMsgFailed(("%s at %VGv parameter mismatch %d vs %d!!\n", pszInstr, pRegFrame->rip, pCpu->param1.size, pCpu->param2.size)); /* should never happen! */
724	return VERR_EM_INTERPRETER;
725	}
726	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
727	pCpu->param2.size = pCpu->param1.size;
728	param2.size = param1.size;
729	}
730
731	/* The destination is always a virtual address */
732	if (param1.type == PARMTYPE_ADDRESS)
733	{
734	pParam1 = (RTGCPTR)param1.val.val64;
735	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
736
737	#ifdef IN_GC
738	/* Safety check (in theory it could cross a page boundary and fault there though) */
739	AssertMsgReturn(pParam1 == pvFault, ("eip=%VGv, pParam1=%VGv pvFault=%VGv\n", pRegFrame->rip, pParam1, pvFault), VERR_EM_INTERPRETER);
740	#endif
741	rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
742	if (VBOX_FAILURE(rc))
743	{
744	AssertMsgFailed(("emRamRead %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
745	return VERR_EM_INTERPRETER;
746	}
747	}
748	else
749	{
750	AssertFailed();
751	return VERR_EM_INTERPRETER;
752	}
753
754	/* Register or immediate data */
755	switch(param2.type)
756	{
757	case PARMTYPE_IMMEDIATE: /* both immediate data and register (ugly) */
758	valpar2 = param2.val.val64;
759	break;
760
761	default:
762	AssertFailed();
763	return VERR_EM_INTERPRETER;
764	}
765
766	LogFlow(("emInterpretOrXorAnd %s %VGv %RX64 - %RX64 size %d (%d)\n", pszInstr, pParam1, valpar1, valpar2, param2.size, param1.size));
767
768	/* Data read, emulate instruction. */
769	uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
770
771	LogFlow(("emInterpretOrXorAnd %s result %RX64\n", pszInstr, valpar1));
772
773	/* Update guest's eflags and finish. */
774	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
775	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
776
777	/* And write it back */
778	rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
779	if (VBOX_SUCCESS(rc))
780	{
781	/* All done! */
782	*pcbSize = param2.size;
783	return VINF_SUCCESS;
784	}
785	#ifdef IN_GC
786	}
787	}
788	#endif
789	return VERR_EM_INTERPRETER;
790	}
791
792	/**
793	* LOCK XOR/OR/AND Emulation.
794	*/
795	static int emInterpretLockOrXorAnd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
796	uint32_t *pcbSize, PFNEMULATELOCKPARAM3 pfnEmulate)
797	{
798	void *pvParam1;
799
800	OP_PARAMVAL param1, param2;
801	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
802	if(VBOX_FAILURE(rc))
803	return VERR_EM_INTERPRETER;
804
805	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
806	if(VBOX_FAILURE(rc))
807	return VERR_EM_INTERPRETER;
808
809	if (pCpu->param1.size != pCpu->param2.size)
810	{
811	AssertMsgReturn(pCpu->param1.size >= pCpu->param2.size, /* should never happen! */
812	("%s at %VGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pCpu), pRegFrame->rip, pCpu->param1.size, pCpu->param2.size),
813	VERR_EM_INTERPRETER);
814
815	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
816	pCpu->param2.size = pCpu->param1.size;
817	param2.size = param1.size;
818	}
819
820	/* The destination is always a virtual address */
821	AssertReturn(param1.type == PARMTYPE_ADDRESS, VERR_EM_INTERPRETER);
822
823	RTGCPTR GCPtrPar1 = param1.val.val64;
824	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
825	#ifdef IN_GC
826	pvParam1 = (void *)GCPtrPar1;
827	#else
828	rc = PGMPhysGCPtr2HCPtr(pVM, GCPtrPar1, &pvParam1);
829	if (VBOX_FAILURE(rc))
830	{
831	AssertRC(rc);
832	return VERR_EM_INTERPRETER;
833	}
834	#endif
835
836	# ifdef IN_GC
837	/* Safety check (in theory it could cross a page boundary and fault there though) */
838	Assert( TRPMHasTrap(pVM)
839	&& (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW));
840	AssertMsgReturn(GCPtrPar1 == pvFault, ("eip=%VGv, GCPtrPar1=%VGv pvFault=%VGv\n", pRegFrame->rip, GCPtrPar1, pvFault), VERR_EM_INTERPRETER);
841	# endif
842
843	/* Register and immediate data == PARMTYPE_IMMEDIATE */
844	AssertReturn(param2.type == PARMTYPE_IMMEDIATE, VERR_EM_INTERPRETER);
845	RTGCUINTREG ValPar2 = param2.val.val64;
846
847	/* Try emulate it with a one-shot #PF handler in place. */
848	Log2(("%s %VGv imm%d=%RX64\n", emGetMnemonic(pCpu), GCPtrPar1, pCpu->param2.size*8, ValPar2));
849
850	RTGCUINTREG32 eflags = 0;
851	#ifdef IN_GC
852	MMGCRamRegisterTrapHandler(pVM);
853	#endif
854	rc = pfnEmulate(pvParam1, ValPar2, pCpu->param2.size, &eflags);
855	#ifdef IN_GC
856	MMGCRamDeregisterTrapHandler(pVM);
857	#endif
858	if (RT_FAILURE(rc))
859	{
860	Log(("%s %VGv imm%d=%RX64-> emulation failed due to page fault!\n", emGetMnemonic(pCpu), GCPtrPar1, pCpu->param2.size*8, ValPar2));
861	return VERR_EM_INTERPRETER;
862	}
863
864	/* Update guest's eflags and finish. */
865	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
866	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
867
868	*pcbSize = param2.size;
869	return VINF_SUCCESS;
870	}
871
872	/**
873	* ADD, ADC & SUB Emulation.
874	*/
875	static int emInterpretAddSub(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
876	PFN_EMULATE_PARAM3 pfnEmulate)
877	{
878	OP_PARAMVAL param1, param2;
879	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
880	if(VBOX_FAILURE(rc))
881	return VERR_EM_INTERPRETER;
882
883	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
884	if(VBOX_FAILURE(rc))
885	return VERR_EM_INTERPRETER;
886
887	#ifdef LOG_ENABLED
888	const char *pszInstr;
889
890	if (pCpu->pCurInstr->opcode == OP_SUB)
891	pszInstr = "Sub";
892	else if (pCpu->pCurInstr->opcode == OP_ADD)
893	pszInstr = "Add";
894	else if (pCpu->pCurInstr->opcode == OP_ADC)
895	pszInstr = "Adc";
896	else
897	pszInstr = "AddSub??";
898	#endif
899
900	#ifdef IN_GC
901	if (TRPMHasTrap(pVM))
902	{
903	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
904	{
905	#endif
906	RTGCPTR pParam1;
907	uint64_t valpar1, valpar2;
908
909	if (pCpu->param1.size != pCpu->param2.size)
910	{
911	if (pCpu->param1.size < pCpu->param2.size)
912	{
913	AssertMsgFailed(("%s at %VGv parameter mismatch %d vs %d!!\n", pszInstr, pRegFrame->rip, pCpu->param1.size, pCpu->param2.size)); /* should never happen! */
914	return VERR_EM_INTERPRETER;
915	}
916	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
917	pCpu->param2.size = pCpu->param1.size;
918	param2.size = param1.size;
919	}
920
921	/* The destination is always a virtual address */
922	if (param1.type == PARMTYPE_ADDRESS)
923	{
924	pParam1 = (RTGCPTR)param1.val.val64;
925	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
926
927	#ifdef IN_GC
928	/* Safety check (in theory it could cross a page boundary and fault there though) */
929	AssertReturn(pParam1 == pvFault, VERR_EM_INTERPRETER);
930	#endif
931	rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
932	if (VBOX_FAILURE(rc))
933	{
934	AssertMsgFailed(("emRamRead %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
935	return VERR_EM_INTERPRETER;
936	}
937	}
938	else
939	{
940	#ifndef DEBUG_bird
941	AssertFailed();
942	#endif
943	return VERR_EM_INTERPRETER;
944	}
945
946	/* Register or immediate data */
947	switch(param2.type)
948	{
949	case PARMTYPE_IMMEDIATE: /* both immediate data and register (ugly) */
950	valpar2 = param2.val.val64;
951	break;
952
953	default:
954	AssertFailed();
955	return VERR_EM_INTERPRETER;
956	}
957
958	/* Data read, emulate instruction. */
959	uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
960
961	/* Update guest's eflags and finish. */
962	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
963	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
964
965	/* And write it back */
966	rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
967	if (VBOX_SUCCESS(rc))
968	{
969	/* All done! */
970	*pcbSize = param2.size;
971	return VINF_SUCCESS;
972	}
973	#ifdef IN_GC
974	}
975	}
976	#endif
977	return VERR_EM_INTERPRETER;
978	}
979
980	/**
981	* ADC Emulation.
982	*/
983	static int emInterpretAdc(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
984	{
985	if (pRegFrame->eflags.Bits.u1CF)
986	return emInterpretAddSub(pVM, pCpu, pRegFrame, pvFault, pcbSize, EMEmulateAdcWithCarrySet);
987	else
988	return emInterpretAddSub(pVM, pCpu, pRegFrame, pvFault, pcbSize, EMEmulateAdd);
989	}
990
991	/**
992	* BTR/C/S Emulation.
993	*/
994	static int emInterpretBitTest(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
995	PFN_EMULATE_PARAM2_UINT32 pfnEmulate)
996	{
997	OP_PARAMVAL param1, param2;
998	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
999	if(VBOX_FAILURE(rc))
1000	return VERR_EM_INTERPRETER;
1001
1002	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1003	if(VBOX_FAILURE(rc))
1004	return VERR_EM_INTERPRETER;
1005
1006	#ifdef LOG_ENABLED
1007	const char *pszInstr;
1008
1009	if (pCpu->pCurInstr->opcode == OP_BTR)
1010	pszInstr = "Btr";
1011	else if (pCpu->pCurInstr->opcode == OP_BTS)
1012	pszInstr = "Bts";
1013	else if (pCpu->pCurInstr->opcode == OP_BTC)
1014	pszInstr = "Btc";
1015	else
1016	pszInstr = "Bit??";
1017	#endif
1018
1019	#ifdef IN_GC
1020	if (TRPMHasTrap(pVM))
1021	{
1022	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1023	{
1024	#endif
1025	RTGCPTR pParam1;
1026	uint64_t valpar1 = 0, valpar2;
1027	uint32_t eflags;
1028
1029	/* The destination is always a virtual address */
1030	if (param1.type != PARMTYPE_ADDRESS)
1031	return VERR_EM_INTERPRETER;
1032
1033	pParam1 = (RTGCPTR)param1.val.val64;
1034	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
1035
1036	/* Register or immediate data */
1037	switch(param2.type)
1038	{
1039	case PARMTYPE_IMMEDIATE: /* both immediate data and register (ugly) */
1040	valpar2 = param2.val.val64;
1041	break;
1042
1043	default:
1044	AssertFailed();
1045	return VERR_EM_INTERPRETER;
1046	}
1047
1048	Log2(("emInterpret%s: pvFault=%VGv pParam1=%VGv val2=%x\n", pszInstr, pvFault, pParam1, valpar2));
1049	pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + valpar2/8);
1050	#ifdef IN_GC
1051	/* Safety check. */
1052	AssertMsgReturn((RTGCPTR)((RTGCUINTPTR)pParam1 & ~3) == pvFault, ("pParam1=%VGv pvFault=%VGv\n", pParam1, pvFault), VERR_EM_INTERPRETER);
1053	#endif
1054	rc = emRamRead(pVM, &valpar1, pParam1, 1);
1055	if (VBOX_FAILURE(rc))
1056	{
1057	AssertMsgFailed(("emRamRead %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
1058	return VERR_EM_INTERPRETER;
1059	}
1060
1061	Log2(("emInterpretBtx: val=%x\n", valpar1));
1062	/* Data read, emulate bit test instruction. */
1063	eflags = pfnEmulate(&valpar1, valpar2 & 0x7);
1064
1065	Log2(("emInterpretBtx: val=%x CF=%d\n", valpar1, !!(eflags & X86_EFL_CF)));
1066
1067	/* Update guest's eflags and finish. */
1068	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1069	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1070
1071	/* And write it back */
1072	rc = emRamWrite(pVM, pParam1, &valpar1, 1);
1073	if (VBOX_SUCCESS(rc))
1074	{
1075	/* All done! */
1076	*pcbSize = 1;
1077	return VINF_SUCCESS;
1078	}
1079	#ifdef IN_GC
1080	}
1081	}
1082	#endif
1083	return VERR_EM_INTERPRETER;
1084	}
1085
1086	/**
1087	* LOCK BTR/C/S Emulation.
1088	*/
1089	static int emInterpretLockBitTest(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
1090	uint32_t *pcbSize, PFNEMULATELOCKPARAM2 pfnEmulate)
1091	{
1092	void *pvParam1;
1093
1094	OP_PARAMVAL param1, param2;
1095	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
1096	if(VBOX_FAILURE(rc))
1097	return VERR_EM_INTERPRETER;
1098
1099	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1100	if(VBOX_FAILURE(rc))
1101	return VERR_EM_INTERPRETER;
1102
1103	/* The destination is always a virtual address */
1104	if (param1.type != PARMTYPE_ADDRESS)
1105	return VERR_EM_INTERPRETER;
1106
1107	/* Register and immediate data == PARMTYPE_IMMEDIATE */
1108	AssertReturn(param2.type == PARMTYPE_IMMEDIATE, VERR_EM_INTERPRETER);
1109	uint64_t ValPar2 = param2.val.val64;
1110
1111	/* Adjust the parameters so what we're dealing with is a bit within the byte pointed to. */
1112	RTGCPTR GCPtrPar1 = param1.val.val64;
1113	GCPtrPar1 = (GCPtrPar1 + ValPar2 / 8);
1114	ValPar2 &= 7;
1115
1116	#ifdef IN_GC
1117	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
1118	pvParam1 = (void *)GCPtrPar1;
1119	#else
1120	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
1121	rc = PGMPhysGCPtr2HCPtr(pVM, GCPtrPar1, &pvParam1);
1122	if (VBOX_FAILURE(rc))
1123	{
1124	AssertRC(rc);
1125	return VERR_EM_INTERPRETER;
1126	}
1127	#endif
1128
1129	Log2(("emInterpretLockBitTest %s: pvFault=%VGv GCPtrPar1=%VGv imm=%RX64\n", emGetMnemonic(pCpu), pvFault, GCPtrPar1, ValPar2));
1130
1131	#ifdef IN_GC
1132	Assert(TRPMHasTrap(pVM));
1133	AssertMsgReturn((RTGCPTR)((RTGCUINTPTR)GCPtrPar1 & ~(RTGCUINTPTR)3) == pvFault,
1134	("GCPtrPar1=%VGv pvFault=%VGv\n", GCPtrPar1, pvFault),
1135	VERR_EM_INTERPRETER);
1136	#endif
1137
1138	/* Try emulate it with a one-shot #PF handler in place. */
1139	RTGCUINTREG32 eflags = 0;
1140	#ifdef IN_GC
1141	MMGCRamRegisterTrapHandler(pVM);
1142	#endif
1143	rc = pfnEmulate(pvParam1, ValPar2, &eflags);
1144	#ifdef IN_GC
1145	MMGCRamDeregisterTrapHandler(pVM);
1146	#endif
1147	if (RT_FAILURE(rc))
1148	{
1149	Log(("emInterpretLockBitTest %s: %VGv imm%d=%RX64 -> emulation failed due to page fault!\n",
1150	emGetMnemonic(pCpu), GCPtrPar1, pCpu->param2.size*8, ValPar2));
1151	return VERR_EM_INTERPRETER;
1152	}
1153
1154	Log2(("emInterpretLockBitTest %s: GCPtrPar1=%VGv imm=%VX64 CF=%d\n", emGetMnemonic(pCpu), GCPtrPar1, ValPar2, !!(eflags & X86_EFL_CF)));
1155
1156	/* Update guest's eflags and finish. */
1157	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1158	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1159
1160	*pcbSize = 1;
1161	return VINF_SUCCESS;
1162	}
1163
1164	/**
1165	* MOV emulation.
1166	*/
1167	static int emInterpretMov(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1168	{
1169	OP_PARAMVAL param1, param2;
1170	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
1171	if(VBOX_FAILURE(rc))
1172	return VERR_EM_INTERPRETER;
1173
1174	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1175	if(VBOX_FAILURE(rc))
1176	return VERR_EM_INTERPRETER;
1177
1178	#ifdef IN_GC
1179	if (TRPMHasTrap(pVM))
1180	{
1181	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1182	{
1183	#else
1184	/** @todo Make this the default and don't rely on TRPM information. */
1185	if (param1.type == PARMTYPE_ADDRESS)
1186	{
1187	#endif
1188	RTGCPTR pDest;
1189	uint64_t val64;
1190
1191	switch(param1.type)
1192	{
1193	case PARMTYPE_IMMEDIATE:
1194	if(!(param1.flags & (PARAM_VAL32\|PARAM_VAL64)))
1195	return VERR_EM_INTERPRETER;
1196	/* fallthru */
1197
1198	case PARMTYPE_ADDRESS:
1199	pDest = (RTGCPTR)param1.val.val64;
1200	pDest = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pDest);
1201	break;
1202
1203	default:
1204	AssertFailed();
1205	return VERR_EM_INTERPRETER;
1206	}
1207
1208	switch(param2.type)
1209	{
1210	case PARMTYPE_IMMEDIATE: /* register type is translated to this one too */
1211	val64 = param2.val.val64;
1212	break;
1213
1214	default:
1215	Log(("emInterpretMov: unexpected type=%d eip=%VGv\n", param2.type, pRegFrame->rip));
1216	return VERR_EM_INTERPRETER;
1217	}
1218	#ifdef LOG_ENABLED
1219	if (pCpu->mode == CPUMODE_64BIT)
1220	LogFlow(("EMInterpretInstruction at %VGv: OP_MOV %VGv <- %RX64 (%d) &val32=%VHv\n", pRegFrame->rip, pDest, val64, param2.size, &val64));
1221	else
1222	LogFlow(("EMInterpretInstruction at %VGv: OP_MOV %VGv <- %08X (%d) &val32=%VHv\n", pRegFrame->rip, pDest, (uint32_t)val64, param2.size, &val64));
1223	#endif
1224
1225	Assert(param2.size <= 8 && param2.size > 0);
1226
1227	#if 0 /* CSAM/PATM translates aliases which causes this to incorrectly trigger. See #2609 and #1498. */
1228	#ifdef IN_GC
1229	/* Safety check (in theory it could cross a page boundary and fault there though) */
1230	AssertMsgReturn(pDest == pvFault, ("eip=%VGv pDest=%VGv pvFault=%VGv\n", pRegFrame->rip, pDest, pvFault), VERR_EM_INTERPRETER);
1231	#endif
1232	#endif
1233	rc = emRamWrite(pVM, pDest, &val64, param2.size);
1234	if (VBOX_FAILURE(rc))
1235	return VERR_EM_INTERPRETER;
1236
1237	*pcbSize = param2.size;
1238	}
1239	else
1240	{ /* read fault */
1241	RTGCPTR pSrc;
1242	uint64_t val64;
1243
1244	/* Source */
1245	switch(param2.type)
1246	{
1247	case PARMTYPE_IMMEDIATE:
1248	if(!(param2.flags & (PARAM_VAL32\|PARAM_VAL64)))
1249	return VERR_EM_INTERPRETER;
1250	/* fallthru */
1251
1252	case PARMTYPE_ADDRESS:
1253	pSrc = (RTGCPTR)param2.val.val64;
1254	pSrc = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param2, pSrc);
1255	break;
1256
1257	default:
1258	return VERR_EM_INTERPRETER;
1259	}
1260
1261	Assert(param1.size <= 8 && param1.size > 0);
1262	#ifdef IN_GC
1263	/* Safety check (in theory it could cross a page boundary and fault there though) */
1264	AssertReturn(pSrc == pvFault, VERR_EM_INTERPRETER);
1265	#endif
1266	rc = emRamRead(pVM, &val64, pSrc, param1.size);
1267	if (VBOX_FAILURE(rc))
1268	return VERR_EM_INTERPRETER;
1269
1270	/* Destination */
1271	switch(param1.type)
1272	{
1273	case PARMTYPE_REGISTER:
1274	switch(param1.size)
1275	{
1276	case 1: rc = DISWriteReg8(pRegFrame, pCpu->param1.base.reg_gen, (uint8_t) val64); break;
1277	case 2: rc = DISWriteReg16(pRegFrame, pCpu->param1.base.reg_gen, (uint16_t)val64); break;
1278	case 4: rc = DISWriteReg32(pRegFrame, pCpu->param1.base.reg_gen, (uint32_t)val64); break;
1279	case 8: rc = DISWriteReg64(pRegFrame, pCpu->param1.base.reg_gen, val64); break;
1280	default:
1281	return VERR_EM_INTERPRETER;
1282	}
1283	if (VBOX_FAILURE(rc))
1284	return rc;
1285	break;
1286
1287	default:
1288	return VERR_EM_INTERPRETER;
1289	}
1290	#ifdef LOG_ENABLED
1291	if (pCpu->mode == CPUMODE_64BIT)
1292	LogFlow(("EMInterpretInstruction: OP_MOV %VGv -> %RX64 (%d)\n", pSrc, val64, param1.size));
1293	else
1294	LogFlow(("EMInterpretInstruction: OP_MOV %VGv -> %08X (%d)\n", pSrc, (uint32_t)val64, param1.size));
1295	#endif
1296	}
1297	return VINF_SUCCESS;
1298	#ifdef IN_GC
1299	}
1300	#endif
1301	return VERR_EM_INTERPRETER;
1302	}
1303
1304	#ifndef IN_GC
1305	/*
1306	* [REP] STOSWD emulation
1307	*
1308	*/
1309	static int emInterpretStosWD(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1310	{
1311	int rc;
1312	RTGCPTR GCDest, GCOffset;
1313	uint32_t cbSize;
1314	uint64_t cTransfers;
1315
1316	/* Don't support any but these three prefix bytes. */
1317	if ((pCpu->prefix & ~(PREFIX_ADDRSIZE\|PREFIX_OPSIZE\|PREFIX_REP\|PREFIX_REX)))
1318	return VERR_EM_INTERPRETER;
1319
1320	switch (pCpu->addrmode)
1321	{
1322	case CPUMODE_16BIT:
1323	GCOffset = pRegFrame->di;
1324	cTransfers = pRegFrame->cx;
1325	break;
1326	case CPUMODE_32BIT:
1327	GCOffset = pRegFrame->edi;
1328	cTransfers = pRegFrame->ecx;
1329	break;
1330	case CPUMODE_64BIT:
1331	GCOffset = pRegFrame->rdi;
1332	cTransfers = pRegFrame->rcx;
1333	break;
1334	default:
1335	AssertFailed();
1336	return VERR_EM_INTERPRETER;
1337	}
1338
1339	GCDest = SELMToFlat(pVM, DIS_SELREG_ES, pRegFrame, GCOffset);
1340	switch (pCpu->opmode)
1341	{
1342	case CPUMODE_16BIT:
1343	cbSize = 2;
1344	break;
1345	case CPUMODE_32BIT:
1346	cbSize = 4;
1347	break;
1348	case CPUMODE_64BIT:
1349	cbSize = 8;
1350	break;
1351	default:
1352	AssertFailed();
1353	return VERR_EM_INTERPRETER;
1354	}
1355
1356	LogFlow(("emInterpretStosWD dest=%VGv cbSize=%d\n", GCDest, cbSize));
1357
1358	if (!(pCpu->prefix & PREFIX_REP))
1359	{
1360	rc = PGMPhysWriteGCPtrSafe(pVM, GCDest, &pRegFrame->rax, cbSize);
1361	if (VBOX_FAILURE(rc))
1362	return VERR_EM_INTERPRETER;
1363	Assert(rc == VINF_SUCCESS);
1364	}
1365	else
1366	{
1367	/* Access verification first; we currently can't recover properly from traps inside this instruction */
1368	rc = PGMVerifyAccess(pVM, GCDest, cTransfers * cbSize, X86_PTE_RW \| X86_PTE_US);
1369	if (rc != VINF_SUCCESS)
1370	{
1371	Log(("STOSWD will generate a trap -> recompiler, rc=%d\n", rc));
1372	return VERR_EM_INTERPRETER;
1373	}
1374
1375	/* REP case */
1376	while (cTransfers)
1377	{
1378	rc = PGMPhysWriteGCPtrSafe(pVM, GCDest, &pRegFrame->rax, cbSize);
1379	if (VBOX_FAILURE(rc))
1380	{
1381	rc = VERR_EM_INTERPRETER;
1382	break;
1383	}
1384
1385	Assert(rc == VINF_SUCCESS);
1386	GCOffset += cbSize;
1387	GCDest += cbSize;
1388	cTransfers--;
1389	}
1390
1391	/* Update the registers. */
1392	switch (pCpu->addrmode)
1393	{
1394	case CPUMODE_16BIT:
1395	pRegFrame->di = GCOffset;
1396	pRegFrame->cx = cTransfers;
1397	break;
1398	case CPUMODE_32BIT:
1399	pRegFrame->edi = GCOffset;
1400	pRegFrame->ecx = cTransfers;
1401	break;
1402	case CPUMODE_64BIT:
1403	pRegFrame->rdi = GCOffset;
1404	pRegFrame->rcx = cTransfers;
1405	break;
1406	}
1407	}
1408
1409	*pcbSize = cbSize;
1410	return rc;
1411	}
1412	#endif
1413
1414
1415	/*
1416	* [LOCK] CMPXCHG emulation.
1417	*/
1418	#ifdef IN_GC
1419	static int emInterpretCmpXchg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1420	{
1421	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
1422	OP_PARAMVAL param1, param2;
1423
1424	#ifdef LOG_ENABLED
1425	const char *pszInstr;
1426
1427	if (pCpu->prefix & PREFIX_LOCK)
1428	pszInstr = "Lock CmpXchg";
1429	else
1430	pszInstr = "CmpXchg";
1431	#endif
1432
1433	/* Source to make DISQueryParamVal read the register value - ugly hack */
1434	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1435	if(VBOX_FAILURE(rc))
1436	return VERR_EM_INTERPRETER;
1437
1438	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1439	if(VBOX_FAILURE(rc))
1440	return VERR_EM_INTERPRETER;
1441
1442	if (TRPMHasTrap(pVM))
1443	{
1444	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1445	{
1446	RTRCPTR pParam1;
1447	uint32_t valpar, eflags;
1448
1449	AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
1450	switch(param1.type)
1451	{
1452	case PARMTYPE_ADDRESS:
1453	pParam1 = (RTRCPTR)param1.val.val64;
1454	pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);
1455
1456	/* Safety check (in theory it could cross a page boundary and fault there though) */
1457	AssertMsgReturn(pParam1 == (RTRCPTR)pvFault, ("eip=%VGv pParam1=%VRv pvFault=%VGv\n", pRegFrame->rip, pParam1, pvFault), VERR_EM_INTERPRETER);
1458	break;
1459
1460	default:
1461	return VERR_EM_INTERPRETER;
1462	}
1463
1464	switch(param2.type)
1465	{
1466	case PARMTYPE_IMMEDIATE: /* register actually */
1467	valpar = param2.val.val32;
1468	break;
1469
1470	default:
1471	return VERR_EM_INTERPRETER;
1472	}
1473
1474	LogFlow(("%s %VRv eax=%08x %08x\n", pszInstr, pParam1, pRegFrame->eax, valpar));
1475
1476	MMGCRamRegisterTrapHandler(pVM);
1477	if (pCpu->prefix & PREFIX_LOCK)
1478	rc = EMGCEmulateLockCmpXchg(pParam1, &pRegFrame->eax, valpar, pCpu->param2.size, &eflags);
1479	else
1480	rc = EMGCEmulateCmpXchg(pParam1, &pRegFrame->eax, valpar, pCpu->param2.size, &eflags);
1481	MMGCRamDeregisterTrapHandler(pVM);
1482
1483	if (VBOX_FAILURE(rc))
1484	{
1485	Log(("%s %VGv=%08x eax=%08x %08x -> emulation failed due to page fault!\n", pszInstr, pParam1, valpar1, pRegFrame->eax, valpar));
1486	return VERR_EM_INTERPRETER;
1487	}
1488
1489	LogFlow(("%s %VRv=%08x eax=%08x %08x ZF=%d\n", pszInstr, pParam1, valpar1, pRegFrame->eax, valpar, !!(eflags & X86_EFL_ZF)));
1490
1491	/* Update guest's eflags and finish. */
1492	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1493	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1494
1495	*pcbSize = param2.size;
1496	return VINF_SUCCESS;
1497	}
1498	}
1499	return VERR_EM_INTERPRETER;
1500	}
1501
1502	/*
1503	* [LOCK] CMPXCHG8B emulation.
1504	*/
1505	static int emInterpretCmpXchg8b(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1506	{
1507	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
1508	OP_PARAMVAL param1;
1509
1510	#ifdef LOG_ENABLED
1511	const char *pszInstr;
1512
1513	if (pCpu->prefix & PREFIX_LOCK)
1514	pszInstr = "Lock CmpXchg8b";
1515	else
1516	pszInstr = "CmpXchg8b";
1517	#endif
1518
1519	/* Source to make DISQueryParamVal read the register value - ugly hack */
1520	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1521	if(VBOX_FAILURE(rc))
1522	return VERR_EM_INTERPRETER;
1523
1524	if (TRPMHasTrap(pVM))
1525	{
1526	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1527	{
1528	RTRCPTR pParam1;
1529	uint32_t eflags;
1530
1531	AssertReturn(pCpu->param1.size == 8, VERR_EM_INTERPRETER);
1532	switch(param1.type)
1533	{
1534	case PARMTYPE_ADDRESS:
1535	pParam1 = (RTRCPTR)param1.val.val64;
1536	pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);
1537
1538	/* Safety check (in theory it could cross a page boundary and fault there though) */
1539	AssertMsgReturn(pParam1 == (RTRCPTR)pvFault, ("eip=%VGv pParam1=%VRv pvFault=%VGv\n", pRegFrame->rip, pParam1, pvFault), VERR_EM_INTERPRETER);
1540	break;
1541
1542	default:
1543	return VERR_EM_INTERPRETER;
1544	}
1545
1546	LogFlow(("%s %VRv=%08x eax=%08x\n", pszInstr, pParam1, pRegFrame->eax));
1547
1548	MMGCRamRegisterTrapHandler(pVM);
1549	if (pCpu->prefix & PREFIX_LOCK)
1550	rc = EMGCEmulateLockCmpXchg8b(pParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx, &eflags);
1551	else
1552	rc = EMGCEmulateCmpXchg8b(pParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx, &eflags);
1553	MMGCRamDeregisterTrapHandler(pVM);
1554
1555	if (VBOX_FAILURE(rc))
1556	{
1557	Log(("%s %VGv=%08x eax=%08x -> emulation failed due to page fault!\n", pszInstr, pParam1, pRegFrame->eax));
1558	return VERR_EM_INTERPRETER;
1559	}
1560
1561	LogFlow(("%s %VGv=%08x eax=%08x ZF=%d\n", pszInstr, pParam1, pRegFrame->eax, !!(eflags & X86_EFL_ZF)));
1562
1563	/* Update guest's eflags and finish; note that only ZF is affected. */
1564	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_ZF))
1565	\| (eflags & (X86_EFL_ZF));
1566
1567	*pcbSize = 8;
1568	return VINF_SUCCESS;
1569	}
1570	}
1571	return VERR_EM_INTERPRETER;
1572	}
1573	#endif
1574
1575	/*
1576	* [LOCK] XADD emulation.
1577	*/
1578	#ifdef IN_GC
1579	static int emInterpretXAdd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1580	{
1581	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
1582	OP_PARAMVAL param1;
1583	uint32_t *pParamReg2;
1584	size_t cbSizeParamReg2;
1585
1586	/* Source to make DISQueryParamVal read the register value - ugly hack */
1587	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1588	if(VBOX_FAILURE(rc))
1589	return VERR_EM_INTERPRETER;
1590
1591	rc = DISQueryParamRegPtr(pRegFrame, pCpu, &pCpu->param2, (void **)&pParamReg2, &cbSizeParamReg2);
1592	Assert(cbSizeParamReg2 <= 4);
1593	if(VBOX_FAILURE(rc))
1594	return VERR_EM_INTERPRETER;
1595
1596	if (TRPMHasTrap(pVM))
1597	{
1598	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1599	{
1600	RTRCPTR pParam1;
1601	uint32_t eflags;
1602	#ifdef VBOX_STRICT
1603	uint32_t valpar1 = 0; /// @todo used uninitialized...
1604	#endif
1605
1606	AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
1607	switch(param1.type)
1608	{
1609	case PARMTYPE_ADDRESS:
1610	pParam1 = (RTRCPTR)param1.val.val64;
1611	pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);
1612
1613	/* Safety check (in theory it could cross a page boundary and fault there though) */
1614	AssertMsgReturn(pParam1 == (RTRCPTR)pvFault, ("eip=%VGv pParam1=%VRv pvFault=%VGv\n", pRegFrame->rip, pParam1, pvFault), VERR_EM_INTERPRETER);
1615	break;
1616
1617	default:
1618	return VERR_EM_INTERPRETER;
1619	}
1620
1621	LogFlow(("XAdd %VRv=%08x reg=%08x\n", pParam1, *pParamReg2));
1622
1623	MMGCRamRegisterTrapHandler(pVM);
1624	if (pCpu->prefix & PREFIX_LOCK)
1625	rc = EMGCEmulateLockXAdd(pParam1, pParamReg2, cbSizeParamReg2, &eflags);
1626	else
1627	rc = EMGCEmulateXAdd(pParam1, pParamReg2, cbSizeParamReg2, &eflags);
1628	MMGCRamDeregisterTrapHandler(pVM);
1629
1630	if (VBOX_FAILURE(rc))
1631	{
1632	Log(("XAdd %VGv=%08x reg=%08x -> emulation failed due to page fault!\n", pParam1, valpar1, *pParamReg2));
1633	return VERR_EM_INTERPRETER;
1634	}
1635
1636	LogFlow(("XAdd %VGv=%08x reg=%08x ZF=%d\n", pParam1, valpar1, *pParamReg2, !!(eflags & X86_EFL_ZF)));
1637
1638	/* Update guest's eflags and finish. */
1639	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1640	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1641
1642	*pcbSize = cbSizeParamReg2;
1643	return VINF_SUCCESS;
1644	}
1645	}
1646	return VERR_EM_INTERPRETER;
1647	}
1648	#endif
1649
1650	#ifdef IN_GC
1651	/**
1652	* Interpret IRET (currently only to V86 code)
1653	*
1654	* @returns VBox status code.
1655	* @param pVM The VM handle.
1656	* @param pRegFrame The register frame.
1657	*
1658	*/
1659	EMDECL(int) EMInterpretIret(PVM pVM, PCPUMCTXCORE pRegFrame)
1660	{
1661	RTGCUINTPTR pIretStack = (RTGCUINTPTR)pRegFrame->esp;
1662	RTGCUINTPTR eip, cs, esp, ss, eflags, ds, es, fs, gs, uMask;
1663	int rc;
1664
1665	Assert(!CPUMIsGuestIn64BitCode(pVM, pRegFrame));
1666
1667	rc = emRamRead(pVM, &eip, (RTGCPTR)pIretStack , 4);
1668	rc \|= emRamRead(pVM, &cs, (RTGCPTR)(pIretStack + 4), 4);
1669	rc \|= emRamRead(pVM, &eflags, (RTGCPTR)(pIretStack + 8), 4);
1670	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1671	AssertReturn(eflags & X86_EFL_VM, VERR_EM_INTERPRETER);
1672
1673	rc \|= emRamRead(pVM, &esp, (RTGCPTR)(pIretStack + 12), 4);
1674	rc \|= emRamRead(pVM, &ss, (RTGCPTR)(pIretStack + 16), 4);
1675	rc \|= emRamRead(pVM, &es, (RTGCPTR)(pIretStack + 20), 4);
1676	rc \|= emRamRead(pVM, &ds, (RTGCPTR)(pIretStack + 24), 4);
1677	rc \|= emRamRead(pVM, &fs, (RTGCPTR)(pIretStack + 28), 4);
1678	rc \|= emRamRead(pVM, &gs, (RTGCPTR)(pIretStack + 32), 4);
1679	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1680
1681	pRegFrame->eip = eip & 0xffff;
1682	pRegFrame->cs = cs;
1683
1684	/* Mask away all reserved bits */
1685	uMask = X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_RF \| X86_EFL_VM \| X86_EFL_AC \| X86_EFL_VIF \| X86_EFL_VIP \| X86_EFL_ID;
1686	eflags &= uMask;
1687
1688	#ifndef IN_RING0
1689	CPUMRawSetEFlags(pVM, pRegFrame, eflags);
1690	#endif
1691	Assert((pRegFrame->eflags.u32 & (X86_EFL_IF\|X86_EFL_IOPL)) == X86_EFL_IF);
1692
1693	pRegFrame->esp = esp;
1694	pRegFrame->ss = ss;
1695	pRegFrame->ds = ds;
1696	pRegFrame->es = es;
1697	pRegFrame->fs = fs;
1698	pRegFrame->gs = gs;
1699
1700	return VINF_SUCCESS;
1701	}
1702	#endif
1703
1704	/**
1705	* IRET Emulation.
1706	*/
1707	static int emInterpretIret(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1708	{
1709	/* only allow direct calls to EMInterpretIret for now */
1710	return VERR_EM_INTERPRETER;
1711	}
1712
1713	/**
1714	* INVLPG Emulation.
1715	*/
1716
1717	/**
1718	* Interpret INVLPG
1719	*
1720	* @returns VBox status code.
1721	* @param pVM The VM handle.
1722	* @param pRegFrame The register frame.
1723	* @param pAddrGC Operand address
1724	*
1725	*/
1726	EMDECL(int) EMInterpretInvlpg(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC)
1727	{
1728	int rc;
1729
1730	/** @todo is addr always a flat linear address or ds based
1731	* (in absence of segment override prefixes)????
1732	*/
1733	#ifdef IN_GC
1734	// Note: we could also use PGMFlushPage here, but it currently doesn't always use invlpg!!!!!!!!!!
1735	LogFlow(("GC: EMULATE: invlpg %08X\n", pAddrGC));
1736	rc = PGMGCInvalidatePage(pVM, pAddrGC);
1737	#else
1738	rc = PGMInvalidatePage(pVM, pAddrGC);
1739	#endif
1740	if (VBOX_SUCCESS(rc))
1741	return VINF_SUCCESS;
1742	Log(("PGMInvalidatePage %VGv returned %VGv (%d)\n", pAddrGC, rc, rc));
1743	Assert(rc == VERR_REM_FLUSHED_PAGES_OVERFLOW);
1744	/** @todo r=bird: we shouldn't ignore returns codes like this... I'm 99% sure the error is fatal. */
1745	return VERR_EM_INTERPRETER;
1746	}
1747
1748	static int emInterpretInvlPg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1749	{
1750	OP_PARAMVAL param1;
1751	RTGCPTR addr;
1752
1753	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1754	if(VBOX_FAILURE(rc))
1755	return VERR_EM_INTERPRETER;
1756
1757	switch(param1.type)
1758	{
1759	case PARMTYPE_IMMEDIATE:
1760	case PARMTYPE_ADDRESS:
1761	if(!(param1.flags & (PARAM_VAL32\|PARAM_VAL64)))
1762	return VERR_EM_INTERPRETER;
1763	addr = (RTGCPTR)param1.val.val64;
1764	break;
1765
1766	default:
1767	return VERR_EM_INTERPRETER;
1768	}
1769
1770	/** @todo is addr always a flat linear address or ds based
1771	* (in absence of segment override prefixes)????
1772	*/
1773	#ifdef IN_GC
1774	// Note: we could also use PGMFlushPage here, but it currently doesn't always use invlpg!!!!!!!!!!
1775	LogFlow(("GC: EMULATE: invlpg %08X\n", addr));
1776	rc = PGMGCInvalidatePage(pVM, addr);
1777	#else
1778	rc = PGMInvalidatePage(pVM, addr);
1779	#endif
1780	if (VBOX_SUCCESS(rc))
1781	return VINF_SUCCESS;
1782	/** @todo r=bird: we shouldn't ignore returns codes like this... I'm 99% sure the error is fatal. */
1783	return VERR_EM_INTERPRETER;
1784	}
1785
1786	/**
1787	* CPUID Emulation.
1788	*/
1789
1790	/**
1791	* Interpret CPUID given the parameters in the CPU context
1792	*
1793	* @returns VBox status code.
1794	* @param pVM The VM handle.
1795	* @param pRegFrame The register frame.
1796	*
1797	*/
1798	EMDECL(int) EMInterpretCpuId(PVM pVM, PCPUMCTXCORE pRegFrame)
1799	{
1800	uint32_t iLeaf = pRegFrame->eax; NOREF(iLeaf);
1801
1802	/* Note: operates the same in 64 and non-64 bits mode. */
1803	CPUMGetGuestCpuId(pVM, pRegFrame->eax, &pRegFrame->eax, &pRegFrame->ebx, &pRegFrame->ecx, &pRegFrame->edx);
1804	Log(("Emulate: CPUID %x -> %08x %08x %08x %08x\n", iLeaf, pRegFrame->eax, pRegFrame->ebx, pRegFrame->ecx, pRegFrame->edx));
1805	return VINF_SUCCESS;
1806	}
1807
1808	static int emInterpretCpuId(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1809	{
1810	int rc = EMInterpretCpuId(pVM, pRegFrame);
1811	return rc;
1812	}
1813
1814	/**
1815	* MOV CRx Emulation.
1816	*/
1817
1818	/**
1819	* Interpret CRx read
1820	*
1821	* @returns VBox status code.
1822	* @param pVM The VM handle.
1823	* @param pRegFrame The register frame.
1824	* @param DestRegGen General purpose register index (USE_REG_E**))
1825	* @param SrcRegCRx CRx register index (USE_REG_CR*)
1826	*
1827	*/
1828	EMDECL(int) EMInterpretCRxRead(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx)
1829	{
1830	int rc;
1831	uint64_t val64;
1832
1833	if (SrcRegCrx == USE_REG_CR8)
1834	{
1835	val64 = 0;
1836	rc = PDMApicGetTPR(pVM, (uint8_t *)&val64, NULL);
1837	AssertMsgRCReturn(rc, ("PDMApicGetTPR failed\n"), VERR_EM_INTERPRETER);
1838	}
1839	else
1840	{
1841	rc = CPUMGetGuestCRx(pVM, SrcRegCrx, &val64);
1842	AssertMsgRCReturn(rc, ("CPUMGetGuestCRx %d failed\n", SrcRegCrx), VERR_EM_INTERPRETER);
1843	}
1844
1845	if (CPUMIsGuestIn64BitCode(pVM, pRegFrame))
1846	rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
1847	else
1848	rc = DISWriteReg32(pRegFrame, DestRegGen, val64);
1849
1850	if(VBOX_SUCCESS(rc))
1851	{
1852	LogFlow(("MOV_CR: gen32=%d CR=%d val=%VX64\n", DestRegGen, SrcRegCrx, val64));
1853	return VINF_SUCCESS;
1854	}
1855	return VERR_EM_INTERPRETER;
1856	}
1857
1858
1859	/**
1860	* Interpret LMSW
1861	*
1862	* @returns VBox status code.
1863	* @param pVM The VM handle.
1864	* @param u16Data LMSW source data.
1865	*
1866	*/
1867	EMDECL(int) EMInterpretLMSW(PVM pVM, uint16_t u16Data)
1868	{
1869	uint64_t OldCr0 = CPUMGetGuestCR0(pVM);
1870
1871	/* don't use this path to go into protected mode! */
1872	Assert(OldCr0 & X86_CR0_PE);
1873	if (!(OldCr0 & X86_CR0_PE))
1874	return VERR_EM_INTERPRETER;
1875
1876	/* Only PE, MP, EM and TS can be changed; note that PE can't be cleared by this instruction. */
1877	uint64_t NewCr0 = ( OldCr0 & ~( X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
1878	\| (u16Data & (X86_CR0_PE \| X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS));
1879
1880	#ifdef IN_GC
1881	/* Need to change the hyper CR0? Doing it the lazy way then. */
1882	if ( (OldCr0 & (X86_CR0_AM \| X86_CR0_WP))
1883	!= (NewCr0 & (X86_CR0_AM \| X86_CR0_WP)))
1884	{
1885	Log(("EMInterpretLMSW: CR0: %#x->%#x => R3\n", OldCr0, NewCr0));
1886	VM_FF_SET(pVM, VM_FF_TO_R3);
1887	}
1888	#endif
1889
1890	return CPUMSetGuestCR0(pVM, NewCr0);
1891	}
1892
1893
1894	/**
1895	* Interpret CLTS
1896	*
1897	* @returns VBox status code.
1898	* @param pVM The VM handle.
1899	*
1900	*/
1901	EMDECL(int) EMInterpretCLTS(PVM pVM)
1902	{
1903	uint64_t cr0 = CPUMGetGuestCR0(pVM);
1904	if (!(cr0 & X86_CR0_TS))
1905	return VINF_SUCCESS;
1906	return CPUMSetGuestCR0(pVM, cr0 & ~X86_CR0_TS);
1907	}
1908
1909	static int emInterpretClts(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1910	{
1911	return EMInterpretCLTS(pVM);
1912	}
1913
1914	/**
1915	* Interpret CRx write
1916	*
1917	* @returns VBox status code.
1918	* @param pVM The VM handle.
1919	* @param pRegFrame The register frame.
1920	* @param DestRegCRx CRx register index (USE_REG_CR*)
1921	* @param SrcRegGen General purpose register index (USE_REG_E**))
1922	*
1923	*/
1924	EMDECL(int) EMInterpretCRxWrite(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint32_t SrcRegGen)
1925	{
1926	uint64_t val;
1927	uint64_t oldval;
1928	uint64_t msrEFER;
1929	int rc;
1930
1931	/** @todo Clean up this mess. */
1932	if (CPUMIsGuestIn64BitCode(pVM, pRegFrame))
1933	{
1934	rc = DISFetchReg64(pRegFrame, SrcRegGen, &val);
1935	}
1936	else
1937	{
1938	uint32_t val32;
1939	rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
1940	val = val32;
1941	}
1942
1943	if (VBOX_SUCCESS(rc))
1944	{
1945	switch (DestRegCrx)
1946	{
1947	case USE_REG_CR0:
1948	oldval = CPUMGetGuestCR0(pVM);
1949	#ifdef IN_GC
1950	/* CR0.WP and CR0.AM changes require a reschedule run in ring 3. */
1951	if ( (val & (X86_CR0_WP \| X86_CR0_AM))
1952	!= (oldval & (X86_CR0_WP \| X86_CR0_AM)))
1953	return VERR_EM_INTERPRETER;
1954	#endif
1955	CPUMSetGuestCR0(pVM, val);
1956	val = CPUMGetGuestCR0(pVM);
1957	if ( (oldval & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE))
1958	!= (val & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE)))
1959	{
1960	/* global flush */
1961	rc = PGMFlushTLB(pVM, CPUMGetGuestCR3(pVM), true /* global */);
1962	AssertRCReturn(rc, rc);
1963	}
1964
1965	/* Deal with long mode enabling/disabling. */
1966	msrEFER = CPUMGetGuestEFER(pVM);
1967	if (msrEFER & MSR_K6_EFER_LME)
1968	{
1969	if ( !(oldval & X86_CR0_PG)
1970	&& (val & X86_CR0_PG))
1971	{
1972	/* Illegal to have an active 64 bits CS selector (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1973	if (pRegFrame->csHid.Attr.n.u1Long)
1974	{
1975	AssertMsgFailed(("Illegal enabling of paging with CS.u1Long = 1!!\n"));
1976	return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
1977	}
1978
1979	/* Illegal to switch to long mode before activating PAE first (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1980	if (!(CPUMGetGuestCR4(pVM) & X86_CR4_PAE))
1981	{
1982	AssertMsgFailed(("Illegal enabling of paging with PAE disabled!!\n"));
1983	return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
1984	}
1985
1986	msrEFER \|= MSR_K6_EFER_LMA;
1987	}
1988	else
1989	if ( (oldval & X86_CR0_PG)
1990	&& !(val & X86_CR0_PG))
1991	{
1992	msrEFER &= ~MSR_K6_EFER_LMA;
1993	/* @todo Do we need to cut off rip here? High dword of rip is undefined, so it shouldn't really matter. */
1994	}
1995	CPUMSetGuestEFER(pVM, msrEFER);
1996	}
1997	return PGMChangeMode(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR4(pVM), CPUMGetGuestEFER(pVM));
1998
1999	case USE_REG_CR2:
2000	rc = CPUMSetGuestCR2(pVM, val); AssertRC(rc);
2001	return VINF_SUCCESS;
2002
2003	case USE_REG_CR3:
2004	/* Reloading the current CR3 means the guest just wants to flush the TLBs */
2005	rc = CPUMSetGuestCR3(pVM, val); AssertRC(rc);
2006	if (CPUMGetGuestCR0(pVM) & X86_CR0_PG)
2007	{
2008	/* flush */
2009	rc = PGMFlushTLB(pVM, val, !(CPUMGetGuestCR4(pVM) & X86_CR4_PGE));
2010	AssertRCReturn(rc, rc);
2011	}
2012	return VINF_SUCCESS;
2013
2014	case USE_REG_CR4:
2015	oldval = CPUMGetGuestCR4(pVM);
2016	rc = CPUMSetGuestCR4(pVM, val); AssertRC(rc);
2017	val = CPUMGetGuestCR4(pVM);
2018
2019	msrEFER = CPUMGetGuestEFER(pVM);
2020	/* Illegal to disable PAE when long mode is active. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
2021	if ( (msrEFER & MSR_K6_EFER_LMA)
2022	&& (oldval & X86_CR4_PAE)
2023	&& !(val & X86_CR4_PAE))
2024	{
2025	return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
2026	}
2027
2028	if ( (oldval & (X86_CR4_PGE\|X86_CR4_PAE\|X86_CR4_PSE))
2029	!= (val & (X86_CR4_PGE\|X86_CR4_PAE\|X86_CR4_PSE)))
2030	{
2031	/* global flush */
2032	rc = PGMFlushTLB(pVM, CPUMGetGuestCR3(pVM), true /* global */);
2033	AssertRCReturn(rc, rc);
2034	}
2035	# ifdef IN_GC
2036	/* Feeling extremely lazy. */
2037	if ( (oldval & (X86_CR4_OSFSXR\|X86_CR4_OSXMMEEXCPT\|X86_CR4_PCE\|X86_CR4_MCE\|X86_CR4_PAE\|X86_CR4_DE\|X86_CR4_TSD\|X86_CR4_PVI\|X86_CR4_VME))
2038	!= (val & (X86_CR4_OSFSXR\|X86_CR4_OSXMMEEXCPT\|X86_CR4_PCE\|X86_CR4_MCE\|X86_CR4_PAE\|X86_CR4_DE\|X86_CR4_TSD\|X86_CR4_PVI\|X86_CR4_VME)))
2039	{
2040	Log(("emInterpretMovCRx: CR4: %#RX64->%#RX64 => R3\n", oldval, val));
2041	VM_FF_SET(pVM, VM_FF_TO_R3);
2042	}
2043	# endif
2044	return PGMChangeMode(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR4(pVM), CPUMGetGuestEFER(pVM));
2045
2046	case USE_REG_CR8:
2047	return PDMApicSetTPR(pVM, val);
2048
2049	default:
2050	AssertFailed();
2051	case USE_REG_CR1: /* illegal op */
2052	break;
2053	}
2054	}
2055	return VERR_EM_INTERPRETER;
2056	}
2057
2058	static int emInterpretMovCRx(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2059	{
2060	if ((pCpu->param1.flags == USE_REG_GEN32 \|\| pCpu->param1.flags == USE_REG_GEN64) && pCpu->param2.flags == USE_REG_CR)
2061	return EMInterpretCRxRead(pVM, pRegFrame, pCpu->param1.base.reg_gen, pCpu->param2.base.reg_ctrl);
2062
2063	if (pCpu->param1.flags == USE_REG_CR && (pCpu->param2.flags == USE_REG_GEN32 \|\| pCpu->param2.flags == USE_REG_GEN64))
2064	return EMInterpretCRxWrite(pVM, pRegFrame, pCpu->param1.base.reg_ctrl, pCpu->param2.base.reg_gen);
2065
2066	AssertMsgFailedReturn(("Unexpected control register move\n"), VERR_EM_INTERPRETER);
2067	return VERR_EM_INTERPRETER;
2068	}
2069
2070	/**
2071	* MOV DRx
2072	*/
2073
2074	/**
2075	* Interpret DRx write
2076	*
2077	* @returns VBox status code.
2078	* @param pVM The VM handle.
2079	* @param pRegFrame The register frame.
2080	* @param DestRegDRx DRx register index (USE_REG_DR*)
2081	* @param SrcRegGen General purpose register index (USE_REG_E**))
2082	*
2083	*/
2084	EMDECL(int) EMInterpretDRxWrite(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen)
2085	{
2086	uint64_t val;
2087	int rc;
2088
2089	if (CPUMIsGuestIn64BitCode(pVM, pRegFrame))
2090	{
2091	rc = DISFetchReg64(pRegFrame, SrcRegGen, &val);
2092	}
2093	else
2094	{
2095	uint32_t val32;
2096	rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
2097	val = val32;
2098	}
2099
2100	if (VBOX_SUCCESS(rc))
2101	{
2102	rc = CPUMSetGuestDRx(pVM, DestRegDrx, val);
2103	if (VBOX_SUCCESS(rc))
2104	return rc;
2105	AssertMsgFailed(("CPUMSetGuestDRx %d failed\n", DestRegDrx));
2106	}
2107	return VERR_EM_INTERPRETER;
2108	}
2109
2110	/**
2111	* Interpret DRx read
2112	*
2113	* @returns VBox status code.
2114	* @param pVM The VM handle.
2115	* @param pRegFrame The register frame.
2116	* @param DestRegGen General purpose register index (USE_REG_E**))
2117	* @param SrcRegDRx DRx register index (USE_REG_DR*)
2118	*
2119	*/
2120	EMDECL(int) EMInterpretDRxRead(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx)
2121	{
2122	uint64_t val64;
2123
2124	int rc = CPUMGetGuestDRx(pVM, SrcRegDrx, &val64);
2125	AssertMsgRCReturn(rc, ("CPUMGetGuestDRx %d failed\n", SrcRegDrx), VERR_EM_INTERPRETER);
2126	if (CPUMIsGuestIn64BitCode(pVM, pRegFrame))
2127	{
2128	rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
2129	}
2130	else
2131	rc = DISWriteReg32(pRegFrame, DestRegGen, (uint32_t)val64);
2132
2133	if (VBOX_SUCCESS(rc))
2134	return VINF_SUCCESS;
2135
2136	return VERR_EM_INTERPRETER;
2137	}
2138
2139	static int emInterpretMovDRx(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2140	{
2141	int rc = VERR_EM_INTERPRETER;
2142
2143	if((pCpu->param1.flags == USE_REG_GEN32 \|\| pCpu->param1.flags == USE_REG_GEN64) && pCpu->param2.flags == USE_REG_DBG)
2144	{
2145	rc = EMInterpretDRxRead(pVM, pRegFrame, pCpu->param1.base.reg_gen, pCpu->param2.base.reg_dbg);
2146	}
2147	else
2148	if(pCpu->param1.flags == USE_REG_DBG && (pCpu->param2.flags == USE_REG_GEN32 \|\| pCpu->param2.flags == USE_REG_GEN64))
2149	{
2150	rc = EMInterpretDRxWrite(pVM, pRegFrame, pCpu->param1.base.reg_dbg, pCpu->param2.base.reg_gen);
2151	}
2152	else
2153	AssertMsgFailed(("Unexpected debug register move\n"));
2154
2155	return rc;
2156	}
2157
2158	/**
2159	* LLDT Emulation.
2160	*/
2161	static int emInterpretLLdt(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2162	{
2163	OP_PARAMVAL param1;
2164	RTSEL sel;
2165
2166	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
2167	if(VBOX_FAILURE(rc))
2168	return VERR_EM_INTERPRETER;
2169
2170	switch(param1.type)
2171	{
2172	case PARMTYPE_ADDRESS:
2173	return VERR_EM_INTERPRETER; //feeling lazy right now
2174
2175	case PARMTYPE_IMMEDIATE:
2176	if(!(param1.flags & PARAM_VAL16))
2177	return VERR_EM_INTERPRETER;
2178	sel = (RTSEL)param1.val.val16;
2179	break;
2180
2181	default:
2182	return VERR_EM_INTERPRETER;
2183	}
2184
2185	if (sel == 0)
2186	{
2187	if (CPUMGetHyperLDTR(pVM) == 0)
2188	{
2189	// this simple case is most frequent in Windows 2000 (31k - boot & shutdown)
2190	return VINF_SUCCESS;
2191	}
2192	}
2193	//still feeling lazy
2194	return VERR_EM_INTERPRETER;
2195	}
2196
2197	#ifdef IN_GC
2198	/**
2199	* STI Emulation.
2200	*
2201	* @remark the instruction following sti is guaranteed to be executed before any interrupts are dispatched
2202	*/
2203	static int emInterpretSti(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2204	{
2205	PPATMGCSTATE pGCState = PATMQueryGCState(pVM);
2206
2207	if(!pGCState)
2208	{
2209	Assert(pGCState);
2210	return VERR_EM_INTERPRETER;
2211	}
2212	pGCState->uVMFlags \|= X86_EFL_IF;
2213
2214	Assert(pRegFrame->eflags.u32 & X86_EFL_IF);
2215	Assert(pvFault == SELMToFlat(pVM, DIS_SELREG_CS, pRegFrame, (RTGCPTR)pRegFrame->rip));
2216
2217	pVM->em.s.GCPtrInhibitInterrupts = pRegFrame->eip + pCpu->opsize;
2218	VM_FF_SET(pVM, VM_FF_INHIBIT_INTERRUPTS);
2219
2220	return VINF_SUCCESS;
2221	}
2222	#endif /* IN_GC */
2223
2224
2225	/**
2226	* HLT Emulation.
2227	*/
2228	static int emInterpretHlt(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2229	{
2230	return VINF_EM_HALT;
2231	}
2232
2233
2234	/**
2235	* RDTSC Emulation.
2236	*/
2237
2238	/**
2239	* Interpret RDTSC
2240	*
2241	* @returns VBox status code.
2242	* @param pVM The VM handle.
2243	* @param pRegFrame The register frame.
2244	*
2245	*/
2246	EMDECL(int) EMInterpretRdtsc(PVM pVM, PCPUMCTXCORE pRegFrame)
2247	{
2248	unsigned uCR4 = CPUMGetGuestCR4(pVM);
2249
2250	if (uCR4 & X86_CR4_TSD)
2251	return VERR_EM_INTERPRETER; /* genuine #GP */
2252
2253	uint64_t uTicks = TMCpuTickGet(pVM);
2254
2255	/* Same behaviour in 32 & 64 bits mode */
2256	pRegFrame->eax = uTicks;
2257	pRegFrame->edx = (uTicks >> 32ULL);
2258
2259	return VINF_SUCCESS;
2260	}
2261
2262	static int emInterpretRdtsc(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2263	{
2264	return EMInterpretRdtsc(pVM, pRegFrame);
2265	}
2266
2267	/**
2268	* MONITOR Emulation.
2269	*/
2270	static int emInterpretMonitor(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2271	{
2272	uint32_t u32Dummy, u32ExtFeatures, cpl;
2273
2274	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
2275	if (pRegFrame->ecx != 0)
2276	return VERR_EM_INTERPRETER; /* illegal value. */
2277
2278	/* Get the current privilege level. */
2279	cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2280	if (cpl != 0)
2281	return VERR_EM_INTERPRETER; /* supervisor only */
2282
2283	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
2284	if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
2285	return VERR_EM_INTERPRETER; /* not supported */
2286
2287	return VINF_SUCCESS;
2288	}
2289
2290
2291	/**
2292	* MWAIT Emulation.
2293	*/
2294	static int emInterpretMWait(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2295	{
2296	uint32_t u32Dummy, u32ExtFeatures, cpl;
2297
2298	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
2299	if (pRegFrame->ecx != 0)
2300	return VERR_EM_INTERPRETER; /* illegal value. */
2301
2302	/* Get the current privilege level. */
2303	cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2304	if (cpl != 0)
2305	return VERR_EM_INTERPRETER; /* supervisor only */
2306
2307	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
2308	if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
2309	return VERR_EM_INTERPRETER; /* not supported */
2310
2311	/** @todo not completely correct */
2312	return VINF_EM_HALT;
2313	}
2314
2315	#ifdef LOG_ENABLED
2316	static const char *emMSRtoString(unsigned uMsr)
2317	{
2318	switch(uMsr)
2319	{
2320	case MSR_IA32_APICBASE:
2321	return "MSR_IA32_APICBASE";
2322	case MSR_IA32_CR_PAT:
2323	return "MSR_IA32_CR_PAT";
2324	case MSR_IA32_SYSENTER_CS:
2325	return "MSR_IA32_SYSENTER_CS";
2326	case MSR_IA32_SYSENTER_EIP:
2327	return "MSR_IA32_SYSENTER_EIP";
2328	case MSR_IA32_SYSENTER_ESP:
2329	return "MSR_IA32_SYSENTER_ESP";
2330	case MSR_K6_EFER:
2331	return "MSR_K6_EFER";
2332	case MSR_K8_SF_MASK:
2333	return "MSR_K8_SF_MASK";
2334	case MSR_K6_STAR:
2335	return "MSR_K6_STAR";
2336	case MSR_K8_LSTAR:
2337	return "MSR_K8_LSTAR";
2338	case MSR_K8_CSTAR:
2339	return "MSR_K8_CSTAR";
2340	case MSR_K8_FS_BASE:
2341	return "MSR_K8_FS_BASE";
2342	case MSR_K8_GS_BASE:
2343	return "MSR_K8_GS_BASE";
2344	case MSR_K8_KERNEL_GS_BASE:
2345	return "MSR_K8_KERNEL_GS_BASE";
2346	case MSR_IA32_TSC:
2347	return "Unsupported MSR_IA32_TSC";
2348	case MSR_IA32_MTRR_CAP:
2349	return "Unsupported MSR_IA32_MTRR_CAP";
2350	case MSR_IA32_MCP_CAP:
2351	return "Unsupported MSR_IA32_MCP_CAP";
2352	case MSR_IA32_MCP_STATUS:
2353	return "Unsupported MSR_IA32_MCP_STATUS";
2354	case MSR_IA32_MCP_CTRL:
2355	return "Unsupported MSR_IA32_MCP_CTRL";
2356	case MSR_IA32_MTRR_DEF_TYPE:
2357	return "Unsupported MSR_IA32_MTRR_DEF_TYPE";
2358	case MSR_K7_EVNTSEL0:
2359	return "Unsupported MSR_K7_EVNTSEL0";
2360	case MSR_K7_EVNTSEL1:
2361	return "Unsupported MSR_K7_EVNTSEL1";
2362	case MSR_K7_EVNTSEL2:
2363	return "Unsupported MSR_K7_EVNTSEL2";
2364	case MSR_K7_EVNTSEL3:
2365	return "Unsupported MSR_K7_EVNTSEL3";
2366	}
2367	return "Unknown MSR";
2368	}
2369	#endif
2370
2371	/**
2372	* Interpret RDMSR
2373	*
2374	* @returns VBox status code.
2375	* @param pVM The VM handle.
2376	* @param pRegFrame The register frame.
2377	*
2378	*/
2379	EMDECL(int) EMInterpretRdmsr(PVM pVM, PCPUMCTXCORE pRegFrame)
2380	{
2381	uint32_t u32Dummy, u32Features, cpl;
2382	uint64_t val;
2383	CPUMCTX *pCtx;
2384	int rc;
2385
2386	/** @todo According to the Intel manuals, there's a REX version of RDMSR that is slightly different.
2387	* That version clears the high dwords of both RDX & RAX */
2388	rc = CPUMQueryGuestCtxPtr(pVM, &pCtx);
2389	AssertRC(rc);
2390
2391	/* Get the current privilege level. */
2392	cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2393	if (cpl != 0)
2394	return VERR_EM_INTERPRETER; /* supervisor only */
2395
2396	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2397	if (!(u32Features & X86_CPUID_FEATURE_EDX_MSR))
2398	return VERR_EM_INTERPRETER; /* not supported */
2399
2400	switch (pRegFrame->ecx)
2401	{
2402	case MSR_IA32_APICBASE:
2403	rc = PDMApicGetBase(pVM, &val);
2404	AssertRC(rc);
2405	break;
2406
2407	case MSR_IA32_CR_PAT:
2408	val = pCtx->msrPAT;
2409	break;
2410
2411	case MSR_IA32_SYSENTER_CS:
2412	val = pCtx->SysEnter.cs;
2413	break;
2414
2415	case MSR_IA32_SYSENTER_EIP:
2416	val = pCtx->SysEnter.eip;
2417	break;
2418
2419	case MSR_IA32_SYSENTER_ESP:
2420	val = pCtx->SysEnter.esp;
2421	break;
2422
2423	case MSR_K6_EFER:
2424	val = pCtx->msrEFER;
2425	break;
2426
2427	case MSR_K8_SF_MASK:
2428	val = pCtx->msrSFMASK;
2429	break;
2430
2431	case MSR_K6_STAR:
2432	val = pCtx->msrSTAR;
2433	break;
2434
2435	case MSR_K8_LSTAR:
2436	val = pCtx->msrLSTAR;
2437	break;
2438
2439	case MSR_K8_CSTAR:
2440	val = pCtx->msrCSTAR;
2441	break;
2442
2443	case MSR_K8_FS_BASE:
2444	val = pCtx->fsHid.u64Base;
2445	break;
2446
2447	case MSR_K8_GS_BASE:
2448	val = pCtx->gsHid.u64Base;
2449	break;
2450
2451	case MSR_K8_KERNEL_GS_BASE:
2452	val = pCtx->msrKERNELGSBASE;
2453	break;
2454
2455	default:
2456	/* We should actually trigger a #GP here, but don't as that might cause more trouble. */
2457	val = 0;
2458	break;
2459	}
2460	Log(("EMInterpretRdmsr %s (%x) -> val=%VX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx, val));
2461	pRegFrame->eax = (uint32_t) val;
2462	pRegFrame->edx = (uint32_t) (val >> 32ULL);
2463	return VINF_SUCCESS;
2464	}
2465
2466	/**
2467	* RDMSR Emulation.
2468	*/
2469	static int emInterpretRdmsr(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2470	{
2471	/* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
2472	Assert(!(pCpu->prefix & PREFIX_REX));
2473	return EMInterpretRdmsr(pVM, pRegFrame);
2474	}
2475
2476	/**
2477	* Interpret WRMSR
2478	*
2479	* @returns VBox status code.
2480	* @param pVM The VM handle.
2481	* @param pRegFrame The register frame.
2482	*
2483	*/
2484	EMDECL(int) EMInterpretWrmsr(PVM pVM, PCPUMCTXCORE pRegFrame)
2485	{
2486	uint32_t u32Dummy, u32Features, cpl;
2487	uint64_t val;
2488	CPUMCTX *pCtx;
2489	int rc;
2490
2491	/* Note: works the same in 32 and 64 bits modes. */
2492	rc = CPUMQueryGuestCtxPtr(pVM, &pCtx);
2493	AssertRC(rc);
2494
2495	/* Get the current privilege level. */
2496	cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2497	if (cpl != 0)
2498	return VERR_EM_INTERPRETER; /* supervisor only */
2499
2500	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2501	if (!(u32Features & X86_CPUID_FEATURE_EDX_MSR))
2502	return VERR_EM_INTERPRETER; /* not supported */
2503
2504	val = (uint64_t)pRegFrame->eax \| ((uint64_t)pRegFrame->edx << 32ULL);
2505	Log(("EMInterpretWrmsr %s (%x) val=%VX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx, val));
2506	switch (pRegFrame->ecx)
2507	{
2508	case MSR_IA32_APICBASE:
2509	rc = PDMApicSetBase(pVM, val);
2510	AssertRC(rc);
2511	break;
2512
2513	case MSR_IA32_CR_PAT:
2514	pCtx->msrPAT = val;
2515	break;
2516
2517	case MSR_IA32_SYSENTER_CS:
2518	pCtx->SysEnter.cs = val & 0xffff; /* 16 bits selector */
2519	break;
2520
2521	case MSR_IA32_SYSENTER_EIP:
2522	pCtx->SysEnter.eip = val;
2523	break;
2524
2525	case MSR_IA32_SYSENTER_ESP:
2526	pCtx->SysEnter.esp = val;
2527	break;
2528
2529	case MSR_K6_EFER:
2530	{
2531	uint64_t uMask = 0;
2532	uint64_t oldval = pCtx->msrEFER;
2533
2534	/* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
2535	CPUMGetGuestCpuId(pVM, 0x80000001, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2536	if (u32Features & X86_CPUID_AMD_FEATURE_EDX_NX)
2537	uMask \|= MSR_K6_EFER_NXE;
2538	if (u32Features & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE)
2539	uMask \|= MSR_K6_EFER_LME;
2540	if (u32Features & X86_CPUID_AMD_FEATURE_EDX_SEP)
2541	uMask \|= MSR_K6_EFER_SCE;
2542	if (u32Features & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
2543	uMask \|= MSR_K6_EFER_FFXSR;
2544
2545	/* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
2546	if ( ((pCtx->msrEFER & MSR_K6_EFER_LME) != (val & uMask & MSR_K6_EFER_LME))
2547	&& (pCtx->cr0 & X86_CR0_PG))
2548	{
2549	AssertMsgFailed(("Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
2550	return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
2551	}
2552
2553	/* There are a few more: e.g. MSR_K6_EFER_LMSLE */
2554	AssertMsg(!(val & ~(MSR_K6_EFER_NXE\|MSR_K6_EFER_LME\|MSR_K6_EFER_LMA /* ignored anyway */ \|MSR_K6_EFER_SCE\|MSR_K6_EFER_FFXSR)), ("Unexpected value %RX64\n", val));
2555	pCtx->msrEFER = (pCtx->msrEFER & ~uMask) \| (val & uMask);
2556
2557	/* AMD64 Achitecture Programmer's Manual: 15.15 TLB Control; flush the TLB if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
2558	if ((oldval & (MSR_K6_EFER_NXE\|MSR_K6_EFER_LME\|MSR_K6_EFER_LMA)) != (pCtx->msrEFER & (MSR_K6_EFER_NXE\|MSR_K6_EFER_LME\|MSR_K6_EFER_LMA)))
2559	HWACCMFlushTLB(pVM);
2560
2561	break;
2562	}
2563
2564	case MSR_K8_SF_MASK:
2565	pCtx->msrSFMASK = val;
2566	break;
2567
2568	case MSR_K6_STAR:
2569	pCtx->msrSTAR = val;
2570	break;
2571
2572	case MSR_K8_LSTAR:
2573	pCtx->msrLSTAR = val;
2574	break;
2575
2576	case MSR_K8_CSTAR:
2577	pCtx->msrCSTAR = val;
2578	break;
2579
2580	case MSR_K8_FS_BASE:
2581	pCtx->fsHid.u64Base = val;
2582	break;
2583
2584	case MSR_K8_GS_BASE:
2585	pCtx->gsHid.u64Base = val;
2586	break;
2587
2588	case MSR_K8_KERNEL_GS_BASE:
2589	pCtx->msrKERNELGSBASE = val;
2590	break;
2591
2592	default:
2593	/* We should actually trigger a #GP here, but don't as that might cause more trouble. */
2594	break;
2595	}
2596	return VINF_SUCCESS;
2597	}
2598
2599	/**
2600	* WRMSR Emulation.
2601	*/
2602	static int emInterpretWrmsr(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2603	{
2604	return EMInterpretWrmsr(pVM, pRegFrame);
2605	}
2606
2607	/**
2608	* Internal worker.
2609	* @copydoc EMInterpretInstructionCPU
2610	*/
2611	DECLINLINE(int) emInterpretInstructionCPU(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2612	{
2613	Assert(pcbSize);
2614	*pcbSize = 0;
2615
2616	/*
2617	* Only supervisor guest code!!
2618	* And no complicated prefixes.
2619	*/
2620	/* Get the current privilege level. */
2621	uint32_t cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2622	if ( cpl != 0
2623	&& pCpu->pCurInstr->opcode != OP_RDTSC) /* rdtsc requires emulation in ring 3 as well */
2624	{
2625	Log(("WARNING: refusing instruction emulation for user-mode code!!\n"));
2626	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,FailedUserMode));
2627	return VERR_EM_INTERPRETER;
2628	}
2629
2630	#ifdef IN_GC
2631	if ( (pCpu->prefix & (PREFIX_REPNE \| PREFIX_REP))
2632	\|\| ( (pCpu->prefix & PREFIX_LOCK)
2633	&& pCpu->pCurInstr->opcode != OP_CMPXCHG
2634	&& pCpu->pCurInstr->opcode != OP_CMPXCHG8B
2635	&& pCpu->pCurInstr->opcode != OP_XADD
2636	&& pCpu->pCurInstr->opcode != OP_OR
2637	&& pCpu->pCurInstr->opcode != OP_BTR
2638	)
2639	)
2640	#else
2641	if ( (pCpu->prefix & PREFIX_REPNE)
2642	\|\| ( (pCpu->prefix & PREFIX_REP)
2643	&& pCpu->pCurInstr->opcode != OP_STOSWD
2644	)
2645	\|\| ( (pCpu->prefix & PREFIX_LOCK)
2646	&& pCpu->pCurInstr->opcode != OP_OR
2647	&& pCpu->pCurInstr->opcode != OP_BTR
2648	)
2649	)
2650	#endif
2651	{
2652	//Log(("EMInterpretInstruction: wrong prefix!!\n"));
2653	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,FailedPrefix));
2654	return VERR_EM_INTERPRETER;
2655	}
2656
2657	int rc;
2658	#if (defined(VBOX_STRICT) \|\| defined(LOG_ENABLED))
2659	LogFlow(("emInterpretInstructionCPU %s\n", emGetMnemonic(pCpu)));
2660	#endif
2661	switch (pCpu->pCurInstr->opcode)
2662	{
2663	# define INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
2664	case opcode:\
2665	if (pCpu->prefix & PREFIX_LOCK) \
2666	rc = emInterpretLock##InstrFn(pVM, pCpu, pRegFrame, pvFault, pcbSize, pfnEmulateLock); \
2667	else \
2668	rc = emInterpret##InstrFn(pVM, pCpu, pRegFrame, pvFault, pcbSize, pfnEmulate); \
2669	if (VBOX_SUCCESS(rc)) \
2670	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,Instr)); \
2671	else \
2672	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,Failed##Instr)); \
2673	return rc
2674	#define INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate) \
2675	case opcode:\
2676	rc = emInterpret##InstrFn(pVM, pCpu, pRegFrame, pvFault, pcbSize, pfnEmulate); \
2677	if (VBOX_SUCCESS(rc)) \
2678	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,Instr)); \
2679	else \
2680	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,Failed##Instr)); \
2681	return rc
2682
2683	#define INTERPRET_CASE_EX_PARAM2(opcode, Instr, InstrFn, pfnEmulate) \
2684	INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate)
2685	#define INTERPRET_CASE_EX_LOCK_PARAM2(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
2686	INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock)
2687
2688	#define INTERPRET_CASE(opcode, Instr) \
2689	case opcode:\
2690	rc = emInterpret##Instr(pVM, pCpu, pRegFrame, pvFault, pcbSize); \
2691	if (VBOX_SUCCESS(rc)) \
2692	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,Instr)); \
2693	else \
2694	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,Failed##Instr)); \
2695	return rc
2696	#define INTERPRET_STAT_CASE(opcode, Instr) \
2697	case opcode: STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,Failed##Instr)); return VERR_EM_INTERPRETER;
2698
2699	INTERPRET_CASE(OP_XCHG,Xchg);
2700	INTERPRET_CASE_EX_PARAM2(OP_DEC,Dec, IncDec, EMEmulateDec);
2701	INTERPRET_CASE_EX_PARAM2(OP_INC,Inc, IncDec, EMEmulateInc);
2702	INTERPRET_CASE(OP_POP,Pop);
2703	INTERPRET_CASE_EX_LOCK_PARAM3(OP_OR, Or, OrXorAnd, EMEmulateOr, EMEmulateLockOr);
2704	INTERPRET_CASE_EX_PARAM3(OP_XOR,Xor, OrXorAnd, EMEmulateXor);
2705	INTERPRET_CASE_EX_PARAM3(OP_AND,And, OrXorAnd, EMEmulateAnd);
2706	INTERPRET_CASE(OP_MOV,Mov);
2707	#ifndef IN_GC
2708	INTERPRET_CASE(OP_STOSWD,StosWD);
2709	#endif
2710	INTERPRET_CASE(OP_INVLPG,InvlPg);
2711	INTERPRET_CASE(OP_CPUID,CpuId);
2712	INTERPRET_CASE(OP_MOV_CR,MovCRx);
2713	INTERPRET_CASE(OP_MOV_DR,MovDRx);
2714	INTERPRET_CASE(OP_LLDT,LLdt);
2715	INTERPRET_CASE(OP_CLTS,Clts);
2716	INTERPRET_CASE(OP_MONITOR, Monitor);
2717	INTERPRET_CASE(OP_MWAIT, MWait);
2718	INTERPRET_CASE(OP_RDMSR, Rdmsr);
2719	INTERPRET_CASE(OP_WRMSR, Wrmsr);
2720	INTERPRET_CASE_EX_PARAM3(OP_ADD,Add, AddSub, EMEmulateAdd);
2721	INTERPRET_CASE_EX_PARAM3(OP_SUB,Sub, AddSub, EMEmulateSub);
2722	INTERPRET_CASE(OP_ADC,Adc);
2723	INTERPRET_CASE_EX_LOCK_PARAM2(OP_BTR,Btr, BitTest, EMEmulateBtr, EMEmulateLockBtr);
2724	INTERPRET_CASE_EX_PARAM2(OP_BTS,Bts, BitTest, EMEmulateBts);
2725	INTERPRET_CASE_EX_PARAM2(OP_BTC,Btc, BitTest, EMEmulateBtc);
2726	INTERPRET_CASE(OP_RDTSC,Rdtsc);
2727	#ifdef IN_GC
2728	INTERPRET_CASE(OP_STI,Sti);
2729	INTERPRET_CASE(OP_CMPXCHG, CmpXchg);
2730	INTERPRET_CASE(OP_CMPXCHG8B, CmpXchg8b);
2731	INTERPRET_CASE(OP_XADD, XAdd);
2732	#endif
2733	INTERPRET_CASE(OP_HLT,Hlt);
2734	INTERPRET_CASE(OP_IRET,Iret);
2735	#ifdef VBOX_WITH_STATISTICS
2736	#ifndef IN_GC
2737	INTERPRET_STAT_CASE(OP_CMPXCHG,CmpXchg);
2738	INTERPRET_STAT_CASE(OP_CMPXCHG8B, CmpXchg8b);
2739	INTERPRET_STAT_CASE(OP_XADD, XAdd);
2740	#endif
2741	INTERPRET_STAT_CASE(OP_MOVNTPS,MovNTPS);
2742	INTERPRET_STAT_CASE(OP_WBINVD,WbInvd);
2743	#endif
2744	default:
2745	Log3(("emInterpretInstructionCPU: opcode=%d\n", pCpu->pCurInstr->opcode));
2746	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,FailedMisc));
2747	return VERR_EM_INTERPRETER;
2748	#undef INTERPRET_CASE_EX_PARAM2
2749	#undef INTERPRET_STAT_CASE
2750	#undef INTERPRET_CASE_EX
2751	#undef INTERPRET_CASE
2752	}
2753	AssertFailed();
2754	return VERR_INTERNAL_ERROR;
2755	}
2756
2757
2758	/**
2759	* Sets the PC for which interrupts should be inhibited.
2760	*
2761	* @param pVM The VM handle.
2762	* @param PC The PC.
2763	*/
2764	EMDECL(void) EMSetInhibitInterruptsPC(PVM pVM, RTGCUINTPTR PC)
2765	{
2766	pVM->em.s.GCPtrInhibitInterrupts = PC;
2767	VM_FF_SET(pVM, VM_FF_INHIBIT_INTERRUPTS);
2768	}
2769
2770
2771	/**
2772	* Gets the PC for which interrupts should be inhibited.
2773	*
2774	* There are a few instructions which inhibits or delays interrupts
2775	* for the instruction following them. These instructions are:
2776	* - STI
2777	* - MOV SS, r/m16
2778	* - POP SS
2779	*
2780	* @returns The PC for which interrupts should be inhibited.
2781	* @param pVM VM handle.
2782	*
2783	*/
2784	EMDECL(RTGCUINTPTR) EMGetInhibitInterruptsPC(PVM pVM)
2785	{
2786	return pVM->em.s.GCPtrInhibitInterrupts;
2787	}

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source: vbox/trunk/src/VBox/VMM/VMMAll/EMAll.cpp@ 11452

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