VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/EMAll.cpp@ 11764

Last change on this file since 11764 was 11764, checked in by vboxsync, 16 years ago

Got rid of PAT cpuid feature hack. Properly fixed now.
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File size: 96.6 KB
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1/* $Id: EMAll.cpp 11764 2008-08-28 14:28:50Z vboxsync $ */
2/** @file
3 * EM - Execution Monitor(/Manager) - All contexts
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_EM
26#include <VBox/em.h>
27#include <VBox/mm.h>
28#include <VBox/selm.h>
29#include <VBox/patm.h>
30#include <VBox/csam.h>
31#include <VBox/pgm.h>
32#include <VBox/iom.h>
33#include <VBox/stam.h>
34#include "EMInternal.h"
35#include <VBox/vm.h>
36#include <VBox/hwaccm.h>
37#include <VBox/tm.h>
38#include <VBox/pdmapi.h>
39
40#include <VBox/param.h>
41#include <VBox/err.h>
42#include <VBox/dis.h>
43#include <VBox/disopcode.h>
44#include <VBox/log.h>
45#include <iprt/assert.h>
46#include <iprt/asm.h>
47#include <iprt/string.h>
48
49
50/*******************************************************************************
51* Structures and Typedefs *
52*******************************************************************************/
53
54
55/*******************************************************************************
56* Internal Functions *
57*******************************************************************************/
58DECLINLINE(int) emInterpretInstructionCPU(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize);
59
60
61/**
62 * Get the current execution manager status.
63 *
64 * @returns Current status.
65 */
66EMDECL(EMSTATE) EMGetState(PVM pVM)
67{
68 return pVM->em.s.enmState;
69}
70
71
72#ifndef IN_GC
73/**
74 * Read callback for disassembly function; supports reading bytes that cross a page boundary
75 *
76 * @returns VBox status code.
77 * @param pSrc GC source pointer
78 * @param pDest HC destination pointer
79 * @param cb Number of bytes to read
80 * @param dwUserdata Callback specific user data (pCpu)
81 *
82 */
83DECLCALLBACK(int) EMReadBytes(RTUINTPTR pSrc, uint8_t *pDest, unsigned cb, void *pvUserdata)
84{
85 DISCPUSTATE *pCpu = (DISCPUSTATE *)pvUserdata;
86 PVM pVM = (PVM)pCpu->apvUserData[0];
87#ifdef IN_RING0
88 int rc = PGMPhysReadGCPtr(pVM, pDest, pSrc, cb);
89 AssertMsgRC(rc, ("PGMPhysReadGCPtr failed for pSrc=%VGv cb=%x\n", pSrc, cb));
90#else
91 if (!PATMIsPatchGCAddr(pVM, pSrc))
92 {
93 int rc = PGMPhysReadGCPtr(pVM, pDest, pSrc, cb);
94 AssertRC(rc);
95 }
96 else
97 {
98 for (uint32_t i = 0; i < cb; i++)
99 {
100 uint8_t opcode;
101 if (VBOX_SUCCESS(PATMR3QueryOpcode(pVM, (RTGCPTR)pSrc + i, &opcode)))
102 {
103 *(pDest+i) = opcode;
104 }
105 }
106 }
107#endif /* IN_RING0 */
108 return VINF_SUCCESS;
109}
110
111DECLINLINE(int) emDisCoreOne(PVM pVM, DISCPUSTATE *pCpu, RTGCUINTPTR InstrGC, uint32_t *pOpsize)
112{
113 return DISCoreOneEx(InstrGC, pCpu->mode, EMReadBytes, pVM, pCpu, pOpsize);
114}
115
116#else
117
118DECLINLINE(int) emDisCoreOne(PVM pVM, DISCPUSTATE *pCpu, RTGCUINTPTR InstrGC, uint32_t *pOpsize)
119{
120 return DISCoreOne(pCpu, InstrGC, pOpsize);
121}
122
123#endif
124
125
126/**
127 * Disassembles one instruction.
128 *
129 * @param pVM The VM handle.
130 * @param pCtxCore The context core (used for both the mode and instruction).
131 * @param pCpu Where to return the parsed instruction info.
132 * @param pcbInstr Where to return the instruction size. (optional)
133 */
134EMDECL(int) EMInterpretDisasOne(PVM pVM, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, unsigned *pcbInstr)
135{
136 RTGCPTR GCPtrInstr;
137 int rc = SELMToFlatEx(pVM, DIS_SELREG_CS, pCtxCore, pCtxCore->rip, 0, &GCPtrInstr);
138 if (VBOX_FAILURE(rc))
139 {
140 Log(("EMInterpretDisasOne: Failed to convert %RTsel:%VGv (cpl=%d) - rc=%Vrc !!\n",
141 pCtxCore->cs, pCtxCore->rip, pCtxCore->ss & X86_SEL_RPL, rc));
142 return rc;
143 }
144 return EMInterpretDisasOneEx(pVM, (RTGCUINTPTR)GCPtrInstr, pCtxCore, pCpu, pcbInstr);
145}
146
147
148/**
149 * Disassembles one instruction.
150 *
151 * This is used by internally by the interpreter and by trap/access handlers.
152 *
153 * @param pVM The VM handle.
154 * @param GCPtrInstr The flat address of the instruction.
155 * @param pCtxCore The context core (used to determin the cpu mode).
156 * @param pCpu Where to return the parsed instruction info.
157 * @param pcbInstr Where to return the instruction size. (optional)
158 */
159EMDECL(int) EMInterpretDisasOneEx(PVM pVM, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, unsigned *pcbInstr)
160{
161 int rc = DISCoreOneEx(GCPtrInstr, SELMGetCpuModeFromSelector(pVM, pCtxCore->eflags, pCtxCore->cs, (PCPUMSELREGHID)&pCtxCore->csHid),
162#ifdef IN_GC
163 NULL, NULL,
164#else
165 EMReadBytes, pVM,
166#endif
167 pCpu, pcbInstr);
168 if (VBOX_SUCCESS(rc))
169 return VINF_SUCCESS;
170 AssertMsgFailed(("DISCoreOne failed to GCPtrInstr=%VGv rc=%Vrc\n", GCPtrInstr, rc));
171 return VERR_INTERNAL_ERROR;
172}
173
174
175/**
176 * Interprets the current instruction.
177 *
178 * @returns VBox status code.
179 * @retval VINF_* Scheduling instructions.
180 * @retval VERR_EM_INTERPRETER Something we can't cope with.
181 * @retval VERR_* Fatal errors.
182 *
183 * @param pVM The VM handle.
184 * @param pRegFrame The register frame.
185 * Updates the EIP if an instruction was executed successfully.
186 * @param pvFault The fault address (CR2).
187 * @param pcbSize Size of the write (if applicable).
188 *
189 * @remark Invalid opcode exceptions have a higher priority than GP (see Intel
190 * Architecture System Developers Manual, Vol 3, 5.5) so we don't need
191 * to worry about e.g. invalid modrm combinations (!)
192 */
193EMDECL(int) EMInterpretInstruction(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
194{
195 RTGCPTR pbCode;
196
197 LogFlow(("EMInterpretInstruction %VGv fault %VGv\n", pRegFrame->rip, pvFault));
198 int rc = SELMToFlatEx(pVM, DIS_SELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
199 if (VBOX_SUCCESS(rc))
200 {
201 uint32_t cbOp;
202 DISCPUSTATE Cpu;
203 Cpu.mode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
204 rc = emDisCoreOne(pVM, &Cpu, (RTGCUINTPTR)pbCode, &cbOp);
205 if (VBOX_SUCCESS(rc))
206 {
207 Assert(cbOp == Cpu.opsize);
208 rc = EMInterpretInstructionCPU(pVM, &Cpu, pRegFrame, pvFault, pcbSize);
209 if (VBOX_SUCCESS(rc))
210 {
211 pRegFrame->rip += cbOp; /* Move on to the next instruction. */
212 }
213 return rc;
214 }
215 }
216 return VERR_EM_INTERPRETER;
217}
218
219/**
220 * Interprets the current instruction using the supplied DISCPUSTATE structure.
221 *
222 * EIP is *NOT* updated!
223 *
224 * @returns VBox status code.
225 * @retval VINF_* Scheduling instructions. When these are returned, it
226 * starts to get a bit tricky to know whether code was
227 * executed or not... We'll address this when it becomes a problem.
228 * @retval VERR_EM_INTERPRETER Something we can't cope with.
229 * @retval VERR_* Fatal errors.
230 *
231 * @param pVM The VM handle.
232 * @param pCpu The disassembler cpu state for the instruction to be interpreted.
233 * @param pRegFrame The register frame. EIP is *NOT* changed!
234 * @param pvFault The fault address (CR2).
235 * @param pcbSize Size of the write (if applicable).
236 *
237 * @remark Invalid opcode exceptions have a higher priority than GP (see Intel
238 * Architecture System Developers Manual, Vol 3, 5.5) so we don't need
239 * to worry about e.g. invalid modrm combinations (!)
240 *
241 * @todo At this time we do NOT check if the instruction overwrites vital information.
242 * Make sure this can't happen!! (will add some assertions/checks later)
243 */
244EMDECL(int) EMInterpretInstructionCPU(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
245{
246 STAM_PROFILE_START(&CTXMID(pVM->em.s.CTXSUFF(pStats)->Stat,Emulate), a);
247 int rc = emInterpretInstructionCPU(pVM, pCpu, pRegFrame, pvFault, pcbSize);
248 STAM_PROFILE_STOP(&CTXMID(pVM->em.s.CTXSUFF(pStats)->Stat,Emulate), a);
249 if (VBOX_SUCCESS(rc))
250 STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,InterpretSucceeded));
251 else
252 STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,InterpretFailed));
253 return rc;
254}
255
256
257/**
258 * Interpret a port I/O instruction.
259 *
260 * @returns VBox status code suitable for scheduling.
261 * @param pVM The VM handle.
262 * @param pCtxCore The context core. This will be updated on successful return.
263 * @param pCpu The instruction to interpret.
264 * @param cbOp The size of the instruction.
265 * @remark This may raise exceptions.
266 */
267EMDECL(int) EMInterpretPortIO(PVM pVM, PCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, uint32_t cbOp)
268{
269 /*
270 * Hand it on to IOM.
271 */
272#ifdef IN_GC
273 int rc = IOMGCIOPortHandler(pVM, pCtxCore, pCpu);
274 if (IOM_SUCCESS(rc))
275 pCtxCore->rip += cbOp;
276 return rc;
277#else
278 AssertReleaseMsgFailed(("not implemented\n"));
279 return VERR_NOT_IMPLEMENTED;
280#endif
281}
282
283
284DECLINLINE(int) emRamRead(PVM pVM, void *pDest, RTGCPTR GCSrc, uint32_t cb)
285{
286#ifdef IN_GC
287 int rc = MMGCRamRead(pVM, pDest, (void *)GCSrc, cb);
288 if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
289 return rc;
290 /*
291 * The page pool cache may end up here in some cases because it
292 * flushed one of the shadow mappings used by the trapping
293 * instruction and it either flushed the TLB or the CPU reused it.
294 */
295 RTGCPHYS GCPhys;
296 rc = PGMPhysGCPtr2GCPhys(pVM, GCSrc, &GCPhys);
297 AssertRCReturn(rc, rc);
298 PGMPhysRead(pVM, GCPhys, pDest, cb);
299 return VINF_SUCCESS;
300#else
301 return PGMPhysReadGCPtrSafe(pVM, pDest, GCSrc, cb);
302#endif
303}
304
305DECLINLINE(int) emRamWrite(PVM pVM, RTGCPTR GCDest, void *pSrc, uint32_t cb)
306{
307#ifdef IN_GC
308 int rc = MMGCRamWrite(pVM, (void *)GCDest, pSrc, cb);
309 if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
310 return rc;
311 /*
312 * The page pool cache may end up here in some cases because it
313 * flushed one of the shadow mappings used by the trapping
314 * instruction and it either flushed the TLB or the CPU reused it.
315 * We want to play safe here, verifying that we've got write
316 * access doesn't cost us much (see PGMPhysGCPtr2GCPhys()).
317 */
318 uint64_t fFlags;
319 RTGCPHYS GCPhys;
320 rc = PGMGstGetPage(pVM, GCDest, &fFlags, &GCPhys);
321 if (RT_FAILURE(rc))
322 return rc;
323 if ( !(fFlags & X86_PTE_RW)
324 && (CPUMGetGuestCR0(pVM) & X86_CR0_WP))
325 return VERR_ACCESS_DENIED;
326
327 PGMPhysWrite(pVM, GCPhys + ((RTGCUINTPTR)GCDest & PAGE_OFFSET_MASK), pSrc, cb);
328 return VINF_SUCCESS;
329
330#else
331 return PGMPhysWriteGCPtrSafe(pVM, GCDest, pSrc, cb);
332#endif
333}
334
335/* Convert sel:addr to a flat GC address */
336static RTGCPTR emConvertToFlatAddr(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, POP_PARAMETER pParam, RTGCPTR pvAddr)
337{
338 DIS_SELREG enmPrefixSeg = DISDetectSegReg(pCpu, pParam);
339 return SELMToFlat(pVM, enmPrefixSeg, pRegFrame, pvAddr);
340}
341
342#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
343/**
344 * Get the mnemonic for the disassembled instruction.
345 *
346 * GC/R0 doesn't include the strings in the DIS tables because
347 * of limited space.
348 */
349static const char *emGetMnemonic(PDISCPUSTATE pCpu)
350{
351 switch (pCpu->pCurInstr->opcode)
352 {
353 case OP_XCHG: return "Xchg";
354 case OP_DEC: return "Dec";
355 case OP_INC: return "Inc";
356 case OP_POP: return "Pop";
357 case OP_OR: return "Or";
358 case OP_AND: return "And";
359 case OP_MOV: return "Mov";
360 case OP_INVLPG: return "InvlPg";
361 case OP_CPUID: return "CpuId";
362 case OP_MOV_CR: return "MovCRx";
363 case OP_MOV_DR: return "MovDRx";
364 case OP_LLDT: return "LLdt";
365 case OP_CLTS: return "Clts";
366 case OP_MONITOR: return "Monitor";
367 case OP_MWAIT: return "MWait";
368 case OP_RDMSR: return "Rdmsr";
369 case OP_WRMSR: return "Wrmsr";
370 case OP_ADC: return "Adc";
371 case OP_BTC: return "Btc";
372 case OP_RDTSC: return "Rdtsc";
373 case OP_STI: return "Sti";
374 case OP_XADD: return "XAdd";
375 case OP_HLT: return "Hlt";
376 case OP_IRET: return "Iret";
377 case OP_CMPXCHG: return "CmpXchg";
378 case OP_CMPXCHG8B: return "CmpXchg8b";
379 case OP_MOVNTPS: return "MovNTPS";
380 case OP_STOSWD: return "StosWD";
381 case OP_WBINVD: return "WbInvd";
382 case OP_XOR: return "Xor";
383 case OP_BTR: return "Btr";
384 case OP_BTS: return "Bts";
385 default:
386 Log(("Unknown opcode %d\n", pCpu->pCurInstr->opcode));
387 return "???";
388 }
389}
390#endif
391
392/**
393 * XCHG instruction emulation.
394 */
395static int emInterpretXchg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
396{
397 OP_PARAMVAL param1, param2;
398
399 /* Source to make DISQueryParamVal read the register value - ugly hack */
400 int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
401 if(VBOX_FAILURE(rc))
402 return VERR_EM_INTERPRETER;
403
404 rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
405 if(VBOX_FAILURE(rc))
406 return VERR_EM_INTERPRETER;
407
408#ifdef IN_GC
409 if (TRPMHasTrap(pVM))
410 {
411 if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
412 {
413#endif
414 RTGCPTR pParam1 = 0, pParam2 = 0;
415 uint64_t valpar1, valpar2;
416
417 AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
418 switch(param1.type)
419 {
420 case PARMTYPE_IMMEDIATE: /* register type is translated to this one too */
421 valpar1 = param1.val.val64;
422 break;
423
424 case PARMTYPE_ADDRESS:
425 pParam1 = (RTGCPTR)param1.val.val64;
426 pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
427#ifdef IN_GC
428 /* Safety check (in theory it could cross a page boundary and fault there though) */
429 AssertReturn(pParam1 == pvFault, VERR_EM_INTERPRETER);
430#endif
431 rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
432 if (VBOX_FAILURE(rc))
433 {
434 AssertMsgFailed(("MMGCRamRead %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
435 return VERR_EM_INTERPRETER;
436 }
437 break;
438
439 default:
440 AssertFailed();
441 return VERR_EM_INTERPRETER;
442 }
443
444 switch(param2.type)
445 {
446 case PARMTYPE_ADDRESS:
447 pParam2 = (RTGCPTR)param2.val.val64;
448 pParam2 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param2, pParam2);
449#ifdef IN_GC
450 /* Safety check (in theory it could cross a page boundary and fault there though) */
451 AssertReturn(pParam2 == pvFault, VERR_EM_INTERPRETER);
452#endif
453 rc = emRamRead(pVM, &valpar2, pParam2, param2.size);
454 if (VBOX_FAILURE(rc))
455 {
456 AssertMsgFailed(("MMGCRamRead %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
457 }
458 break;
459
460 case PARMTYPE_IMMEDIATE:
461 valpar2 = param2.val.val64;
462 break;
463
464 default:
465 AssertFailed();
466 return VERR_EM_INTERPRETER;
467 }
468
469 /* Write value of parameter 2 to parameter 1 (reg or memory address) */
470 if (pParam1 == 0)
471 {
472 Assert(param1.type == PARMTYPE_IMMEDIATE); /* register actually */
473 switch(param1.size)
474 {
475 case 1: //special case for AH etc
476 rc = DISWriteReg8(pRegFrame, pCpu->param1.base.reg_gen, (uint8_t )valpar2); break;
477 case 2: rc = DISWriteReg16(pRegFrame, pCpu->param1.base.reg_gen, (uint16_t)valpar2); break;
478 case 4: rc = DISWriteReg32(pRegFrame, pCpu->param1.base.reg_gen, (uint32_t)valpar2); break;
479 case 8: rc = DISWriteReg64(pRegFrame, pCpu->param1.base.reg_gen, valpar2); break;
480 default: AssertFailedReturn(VERR_EM_INTERPRETER);
481 }
482 if (VBOX_FAILURE(rc))
483 return VERR_EM_INTERPRETER;
484 }
485 else
486 {
487 rc = emRamWrite(pVM, pParam1, &valpar2, param1.size);
488 if (VBOX_FAILURE(rc))
489 {
490 AssertMsgFailed(("emRamWrite %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
491 return VERR_EM_INTERPRETER;
492 }
493 }
494
495 /* Write value of parameter 1 to parameter 2 (reg or memory address) */
496 if (pParam2 == 0)
497 {
498 Assert(param2.type == PARMTYPE_IMMEDIATE); /* register actually */
499 switch(param2.size)
500 {
501 case 1: //special case for AH etc
502 rc = DISWriteReg8(pRegFrame, pCpu->param2.base.reg_gen, (uint8_t )valpar1); break;
503 case 2: rc = DISWriteReg16(pRegFrame, pCpu->param2.base.reg_gen, (uint16_t)valpar1); break;
504 case 4: rc = DISWriteReg32(pRegFrame, pCpu->param2.base.reg_gen, (uint32_t)valpar1); break;
505 case 8: rc = DISWriteReg64(pRegFrame, pCpu->param2.base.reg_gen, valpar1); break;
506 default: AssertFailedReturn(VERR_EM_INTERPRETER);
507 }
508 if (VBOX_FAILURE(rc))
509 return VERR_EM_INTERPRETER;
510 }
511 else
512 {
513 rc = emRamWrite(pVM, pParam2, &valpar1, param2.size);
514 if (VBOX_FAILURE(rc))
515 {
516 AssertMsgFailed(("emRamWrite %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
517 return VERR_EM_INTERPRETER;
518 }
519 }
520
521 *pcbSize = param2.size;
522 return VINF_SUCCESS;
523#ifdef IN_GC
524 }
525 }
526#endif
527 return VERR_EM_INTERPRETER;
528}
529
530/**
531 * INC and DEC emulation.
532 */
533static int emInterpretIncDec(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
534 PFN_EMULATE_PARAM2 pfnEmulate)
535{
536 OP_PARAMVAL param1;
537
538 int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
539 if(VBOX_FAILURE(rc))
540 return VERR_EM_INTERPRETER;
541
542#ifdef IN_GC
543 if (TRPMHasTrap(pVM))
544 {
545 if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
546 {
547#endif
548 RTGCPTR pParam1 = 0;
549 uint64_t valpar1;
550
551 if (param1.type == PARMTYPE_ADDRESS)
552 {
553 pParam1 = (RTGCPTR)param1.val.val64;
554 pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
555#ifdef IN_GC
556 /* Safety check (in theory it could cross a page boundary and fault there though) */
557 AssertReturn(pParam1 == pvFault, VERR_EM_INTERPRETER);
558#endif
559 rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
560 if (VBOX_FAILURE(rc))
561 {
562 AssertMsgFailed(("emRamRead %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
563 return VERR_EM_INTERPRETER;
564 }
565 }
566 else
567 {
568 AssertFailed();
569 return VERR_EM_INTERPRETER;
570 }
571
572 uint32_t eflags;
573
574 eflags = pfnEmulate(&valpar1, param1.size);
575
576 /* Write result back */
577 rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
578 if (VBOX_FAILURE(rc))
579 {
580 AssertMsgFailed(("emRamWrite %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
581 return VERR_EM_INTERPRETER;
582 }
583
584 /* Update guest's eflags and finish. */
585 pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF))
586 | (eflags & (X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF));
587
588 /* All done! */
589 *pcbSize = param1.size;
590 return VINF_SUCCESS;
591#ifdef IN_GC
592 }
593 }
594#endif
595 return VERR_EM_INTERPRETER;
596}
597
598/**
599 * POP Emulation.
600 */
601static int emInterpretPop(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
602{
603 Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
604 OP_PARAMVAL param1;
605 int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
606 if(VBOX_FAILURE(rc))
607 return VERR_EM_INTERPRETER;
608
609#ifdef IN_GC
610 if (TRPMHasTrap(pVM))
611 {
612 if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
613 {
614#endif
615 RTGCPTR pParam1 = 0;
616 uint32_t valpar1;
617 RTGCPTR pStackVal;
618
619 /* Read stack value first */
620 if (SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->ss, &pRegFrame->ssHid) == CPUMODE_16BIT)
621 return VERR_EM_INTERPRETER; /* No legacy 16 bits stuff here, please. */
622
623 /* Convert address; don't bother checking limits etc, as we only read here */
624 pStackVal = SELMToFlat(pVM, DIS_SELREG_SS, pRegFrame, (RTGCPTR)pRegFrame->esp);
625 if (pStackVal == 0)
626 return VERR_EM_INTERPRETER;
627
628 rc = emRamRead(pVM, &valpar1, pStackVal, param1.size);
629 if (VBOX_FAILURE(rc))
630 {
631 AssertMsgFailed(("emRamRead %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
632 return VERR_EM_INTERPRETER;
633 }
634
635 if (param1.type == PARMTYPE_ADDRESS)
636 {
637 pParam1 = (RTGCPTR)param1.val.val64;
638
639 /* pop [esp+xx] uses esp after the actual pop! */
640 AssertCompile(USE_REG_ESP == USE_REG_SP);
641 if ( (pCpu->param1.flags & USE_BASE)
642 && (pCpu->param1.flags & (USE_REG_GEN16|USE_REG_GEN32))
643 && pCpu->param1.base.reg_gen == USE_REG_ESP
644 )
645 pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + param1.size);
646
647 pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
648
649#ifdef IN_GC
650 /* Safety check (in theory it could cross a page boundary and fault there though) */
651 AssertMsgReturn(pParam1 == pvFault || (RTGCPTR)pRegFrame->esp == pvFault, ("%VGv != %VGv ss:esp=%04X:%08x\n", pParam1, pvFault, pRegFrame->ss, pRegFrame->esp), VERR_EM_INTERPRETER);
652#endif
653 rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
654 if (VBOX_FAILURE(rc))
655 {
656 AssertMsgFailed(("emRamWrite %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
657 return VERR_EM_INTERPRETER;
658 }
659
660 /* Update ESP as the last step */
661 pRegFrame->esp += param1.size;
662 }
663 else
664 {
665#ifndef DEBUG_bird // annoying assertion.
666 AssertFailed();
667#endif
668 return VERR_EM_INTERPRETER;
669 }
670
671 /* All done! */
672 *pcbSize = param1.size;
673 return VINF_SUCCESS;
674#ifdef IN_GC
675 }
676 }
677#endif
678 return VERR_EM_INTERPRETER;
679}
680
681
682/**
683 * XOR/OR/AND Emulation.
684 */
685static int emInterpretOrXorAnd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
686 PFN_EMULATE_PARAM3 pfnEmulate)
687{
688 OP_PARAMVAL param1, param2;
689 int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
690 if(VBOX_FAILURE(rc))
691 return VERR_EM_INTERPRETER;
692
693 rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
694 if(VBOX_FAILURE(rc))
695 return VERR_EM_INTERPRETER;
696
697#ifdef LOG_ENABLED
698 const char *pszInstr;
699
700 if (pCpu->pCurInstr->opcode == OP_XOR)
701 pszInstr = "Xor";
702 else if (pCpu->pCurInstr->opcode == OP_OR)
703 pszInstr = "Or";
704 else if (pCpu->pCurInstr->opcode == OP_AND)
705 pszInstr = "And";
706 else
707 pszInstr = "OrXorAnd??";
708#endif
709
710#ifdef IN_GC
711 if (TRPMHasTrap(pVM))
712 {
713 if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
714 {
715#endif
716 RTGCPTR pParam1;
717 uint64_t valpar1, valpar2;
718
719 if (pCpu->param1.size != pCpu->param2.size)
720 {
721 if (pCpu->param1.size < pCpu->param2.size)
722 {
723 AssertMsgFailed(("%s at %VGv parameter mismatch %d vs %d!!\n", pszInstr, pRegFrame->rip, pCpu->param1.size, pCpu->param2.size)); /* should never happen! */
724 return VERR_EM_INTERPRETER;
725 }
726 /* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
727 pCpu->param2.size = pCpu->param1.size;
728 param2.size = param1.size;
729 }
730
731 /* The destination is always a virtual address */
732 if (param1.type == PARMTYPE_ADDRESS)
733 {
734 pParam1 = (RTGCPTR)param1.val.val64;
735 pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
736
737#ifdef IN_GC
738 /* Safety check (in theory it could cross a page boundary and fault there though) */
739 AssertMsgReturn(pParam1 == pvFault, ("eip=%VGv, pParam1=%VGv pvFault=%VGv\n", pRegFrame->rip, pParam1, pvFault), VERR_EM_INTERPRETER);
740#endif
741 rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
742 if (VBOX_FAILURE(rc))
743 {
744 AssertMsgFailed(("emRamRead %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
745 return VERR_EM_INTERPRETER;
746 }
747 }
748 else
749 {
750 AssertFailed();
751 return VERR_EM_INTERPRETER;
752 }
753
754 /* Register or immediate data */
755 switch(param2.type)
756 {
757 case PARMTYPE_IMMEDIATE: /* both immediate data and register (ugly) */
758 valpar2 = param2.val.val64;
759 break;
760
761 default:
762 AssertFailed();
763 return VERR_EM_INTERPRETER;
764 }
765
766 LogFlow(("emInterpretOrXorAnd %s %VGv %RX64 - %RX64 size %d (%d)\n", pszInstr, pParam1, valpar1, valpar2, param2.size, param1.size));
767
768 /* Data read, emulate instruction. */
769 uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
770
771 LogFlow(("emInterpretOrXorAnd %s result %RX64\n", pszInstr, valpar1));
772
773 /* Update guest's eflags and finish. */
774 pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF))
775 | (eflags & (X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF));
776
777 /* And write it back */
778 rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
779 if (VBOX_SUCCESS(rc))
780 {
781 /* All done! */
782 *pcbSize = param2.size;
783 return VINF_SUCCESS;
784 }
785#ifdef IN_GC
786 }
787 }
788#endif
789 return VERR_EM_INTERPRETER;
790}
791
792/**
793 * LOCK XOR/OR/AND Emulation.
794 */
795static int emInterpretLockOrXorAnd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
796 uint32_t *pcbSize, PFNEMULATELOCKPARAM3 pfnEmulate)
797{
798 void *pvParam1;
799
800 OP_PARAMVAL param1, param2;
801 int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
802 if(VBOX_FAILURE(rc))
803 return VERR_EM_INTERPRETER;
804
805 rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
806 if(VBOX_FAILURE(rc))
807 return VERR_EM_INTERPRETER;
808
809 if (pCpu->param1.size != pCpu->param2.size)
810 {
811 AssertMsgReturn(pCpu->param1.size >= pCpu->param2.size, /* should never happen! */
812 ("%s at %VGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pCpu), pRegFrame->rip, pCpu->param1.size, pCpu->param2.size),
813 VERR_EM_INTERPRETER);
814
815 /* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
816 pCpu->param2.size = pCpu->param1.size;
817 param2.size = param1.size;
818 }
819
820 /* The destination is always a virtual address */
821 AssertReturn(param1.type == PARMTYPE_ADDRESS, VERR_EM_INTERPRETER);
822
823 RTGCPTR GCPtrPar1 = param1.val.val64;
824 GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
825#ifdef IN_GC
826 pvParam1 = (void *)GCPtrPar1;
827#else
828 rc = PGMPhysGCPtr2HCPtr(pVM, GCPtrPar1, &pvParam1);
829 if (VBOX_FAILURE(rc))
830 {
831 AssertRC(rc);
832 return VERR_EM_INTERPRETER;
833 }
834#endif
835
836# ifdef IN_GC
837 /* Safety check (in theory it could cross a page boundary and fault there though) */
838 Assert( TRPMHasTrap(pVM)
839 && (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW));
840 AssertMsgReturn(GCPtrPar1 == pvFault, ("eip=%VGv, GCPtrPar1=%VGv pvFault=%VGv\n", pRegFrame->rip, GCPtrPar1, pvFault), VERR_EM_INTERPRETER);
841# endif
842
843 /* Register and immediate data == PARMTYPE_IMMEDIATE */
844 AssertReturn(param2.type == PARMTYPE_IMMEDIATE, VERR_EM_INTERPRETER);
845 RTGCUINTREG ValPar2 = param2.val.val64;
846
847 /* Try emulate it with a one-shot #PF handler in place. */
848 Log2(("%s %VGv imm%d=%RX64\n", emGetMnemonic(pCpu), GCPtrPar1, pCpu->param2.size*8, ValPar2));
849
850 RTGCUINTREG32 eflags = 0;
851#ifdef IN_GC
852 MMGCRamRegisterTrapHandler(pVM);
853#endif
854 rc = pfnEmulate(pvParam1, ValPar2, pCpu->param2.size, &eflags);
855#ifdef IN_GC
856 MMGCRamDeregisterTrapHandler(pVM);
857#endif
858 if (RT_FAILURE(rc))
859 {
860 Log(("%s %VGv imm%d=%RX64-> emulation failed due to page fault!\n", emGetMnemonic(pCpu), GCPtrPar1, pCpu->param2.size*8, ValPar2));
861 return VERR_EM_INTERPRETER;
862 }
863
864 /* Update guest's eflags and finish. */
865 pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF))
866 | (eflags & (X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF));
867
868 *pcbSize = param2.size;
869 return VINF_SUCCESS;
870}
871
872/**
873 * ADD, ADC & SUB Emulation.
874 */
875static int emInterpretAddSub(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
876 PFN_EMULATE_PARAM3 pfnEmulate)
877{
878 OP_PARAMVAL param1, param2;
879 int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
880 if(VBOX_FAILURE(rc))
881 return VERR_EM_INTERPRETER;
882
883 rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
884 if(VBOX_FAILURE(rc))
885 return VERR_EM_INTERPRETER;
886
887#ifdef LOG_ENABLED
888 const char *pszInstr;
889
890 if (pCpu->pCurInstr->opcode == OP_SUB)
891 pszInstr = "Sub";
892 else if (pCpu->pCurInstr->opcode == OP_ADD)
893 pszInstr = "Add";
894 else if (pCpu->pCurInstr->opcode == OP_ADC)
895 pszInstr = "Adc";
896 else
897 pszInstr = "AddSub??";
898#endif
899
900#ifdef IN_GC
901 if (TRPMHasTrap(pVM))
902 {
903 if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
904 {
905#endif
906 RTGCPTR pParam1;
907 uint64_t valpar1, valpar2;
908
909 if (pCpu->param1.size != pCpu->param2.size)
910 {
911 if (pCpu->param1.size < pCpu->param2.size)
912 {
913 AssertMsgFailed(("%s at %VGv parameter mismatch %d vs %d!!\n", pszInstr, pRegFrame->rip, pCpu->param1.size, pCpu->param2.size)); /* should never happen! */
914 return VERR_EM_INTERPRETER;
915 }
916 /* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
917 pCpu->param2.size = pCpu->param1.size;
918 param2.size = param1.size;
919 }
920
921 /* The destination is always a virtual address */
922 if (param1.type == PARMTYPE_ADDRESS)
923 {
924 pParam1 = (RTGCPTR)param1.val.val64;
925 pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
926
927#ifdef IN_GC
928 /* Safety check (in theory it could cross a page boundary and fault there though) */
929 AssertReturn(pParam1 == pvFault, VERR_EM_INTERPRETER);
930#endif
931 rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
932 if (VBOX_FAILURE(rc))
933 {
934 AssertMsgFailed(("emRamRead %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
935 return VERR_EM_INTERPRETER;
936 }
937 }
938 else
939 {
940#ifndef DEBUG_bird
941 AssertFailed();
942#endif
943 return VERR_EM_INTERPRETER;
944 }
945
946 /* Register or immediate data */
947 switch(param2.type)
948 {
949 case PARMTYPE_IMMEDIATE: /* both immediate data and register (ugly) */
950 valpar2 = param2.val.val64;
951 break;
952
953 default:
954 AssertFailed();
955 return VERR_EM_INTERPRETER;
956 }
957
958 /* Data read, emulate instruction. */
959 uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
960
961 /* Update guest's eflags and finish. */
962 pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF))
963 | (eflags & (X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF));
964
965 /* And write it back */
966 rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
967 if (VBOX_SUCCESS(rc))
968 {
969 /* All done! */
970 *pcbSize = param2.size;
971 return VINF_SUCCESS;
972 }
973#ifdef IN_GC
974 }
975 }
976#endif
977 return VERR_EM_INTERPRETER;
978}
979
980/**
981 * ADC Emulation.
982 */
983static int emInterpretAdc(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
984{
985 if (pRegFrame->eflags.Bits.u1CF)
986 return emInterpretAddSub(pVM, pCpu, pRegFrame, pvFault, pcbSize, EMEmulateAdcWithCarrySet);
987 else
988 return emInterpretAddSub(pVM, pCpu, pRegFrame, pvFault, pcbSize, EMEmulateAdd);
989}
990
991/**
992 * BTR/C/S Emulation.
993 */
994static int emInterpretBitTest(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
995 PFN_EMULATE_PARAM2_UINT32 pfnEmulate)
996{
997 OP_PARAMVAL param1, param2;
998 int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
999 if(VBOX_FAILURE(rc))
1000 return VERR_EM_INTERPRETER;
1001
1002 rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1003 if(VBOX_FAILURE(rc))
1004 return VERR_EM_INTERPRETER;
1005
1006#ifdef LOG_ENABLED
1007 const char *pszInstr;
1008
1009 if (pCpu->pCurInstr->opcode == OP_BTR)
1010 pszInstr = "Btr";
1011 else if (pCpu->pCurInstr->opcode == OP_BTS)
1012 pszInstr = "Bts";
1013 else if (pCpu->pCurInstr->opcode == OP_BTC)
1014 pszInstr = "Btc";
1015 else
1016 pszInstr = "Bit??";
1017#endif
1018
1019#ifdef IN_GC
1020 if (TRPMHasTrap(pVM))
1021 {
1022 if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1023 {
1024#endif
1025 RTGCPTR pParam1;
1026 uint64_t valpar1 = 0, valpar2;
1027 uint32_t eflags;
1028
1029 /* The destination is always a virtual address */
1030 if (param1.type != PARMTYPE_ADDRESS)
1031 return VERR_EM_INTERPRETER;
1032
1033 pParam1 = (RTGCPTR)param1.val.val64;
1034 pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
1035
1036 /* Register or immediate data */
1037 switch(param2.type)
1038 {
1039 case PARMTYPE_IMMEDIATE: /* both immediate data and register (ugly) */
1040 valpar2 = param2.val.val64;
1041 break;
1042
1043 default:
1044 AssertFailed();
1045 return VERR_EM_INTERPRETER;
1046 }
1047
1048 Log2(("emInterpret%s: pvFault=%VGv pParam1=%VGv val2=%x\n", pszInstr, pvFault, pParam1, valpar2));
1049 pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + valpar2/8);
1050#ifdef IN_GC
1051 /* Safety check. */
1052 AssertMsgReturn((RTGCPTR)((RTGCUINTPTR)pParam1 & ~3) == pvFault, ("pParam1=%VGv pvFault=%VGv\n", pParam1, pvFault), VERR_EM_INTERPRETER);
1053#endif
1054 rc = emRamRead(pVM, &valpar1, pParam1, 1);
1055 if (VBOX_FAILURE(rc))
1056 {
1057 AssertMsgFailed(("emRamRead %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
1058 return VERR_EM_INTERPRETER;
1059 }
1060
1061 Log2(("emInterpretBtx: val=%x\n", valpar1));
1062 /* Data read, emulate bit test instruction. */
1063 eflags = pfnEmulate(&valpar1, valpar2 & 0x7);
1064
1065 Log2(("emInterpretBtx: val=%x CF=%d\n", valpar1, !!(eflags & X86_EFL_CF)));
1066
1067 /* Update guest's eflags and finish. */
1068 pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF))
1069 | (eflags & (X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF));
1070
1071 /* And write it back */
1072 rc = emRamWrite(pVM, pParam1, &valpar1, 1);
1073 if (VBOX_SUCCESS(rc))
1074 {
1075 /* All done! */
1076 *pcbSize = 1;
1077 return VINF_SUCCESS;
1078 }
1079#ifdef IN_GC
1080 }
1081 }
1082#endif
1083 return VERR_EM_INTERPRETER;
1084}
1085
1086/**
1087 * LOCK BTR/C/S Emulation.
1088 */
1089static int emInterpretLockBitTest(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
1090 uint32_t *pcbSize, PFNEMULATELOCKPARAM2 pfnEmulate)
1091{
1092 void *pvParam1;
1093
1094 OP_PARAMVAL param1, param2;
1095 int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
1096 if(VBOX_FAILURE(rc))
1097 return VERR_EM_INTERPRETER;
1098
1099 rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1100 if(VBOX_FAILURE(rc))
1101 return VERR_EM_INTERPRETER;
1102
1103 /* The destination is always a virtual address */
1104 if (param1.type != PARMTYPE_ADDRESS)
1105 return VERR_EM_INTERPRETER;
1106
1107 /* Register and immediate data == PARMTYPE_IMMEDIATE */
1108 AssertReturn(param2.type == PARMTYPE_IMMEDIATE, VERR_EM_INTERPRETER);
1109 uint64_t ValPar2 = param2.val.val64;
1110
1111 /* Adjust the parameters so what we're dealing with is a bit within the byte pointed to. */
1112 RTGCPTR GCPtrPar1 = param1.val.val64;
1113 GCPtrPar1 = (GCPtrPar1 + ValPar2 / 8);
1114 ValPar2 &= 7;
1115
1116#ifdef IN_GC
1117 GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
1118 pvParam1 = (void *)GCPtrPar1;
1119#else
1120 GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
1121 rc = PGMPhysGCPtr2HCPtr(pVM, GCPtrPar1, &pvParam1);
1122 if (VBOX_FAILURE(rc))
1123 {
1124 AssertRC(rc);
1125 return VERR_EM_INTERPRETER;
1126 }
1127#endif
1128
1129 Log2(("emInterpretLockBitTest %s: pvFault=%VGv GCPtrPar1=%VGv imm=%RX64\n", emGetMnemonic(pCpu), pvFault, GCPtrPar1, ValPar2));
1130
1131#ifdef IN_GC
1132 Assert(TRPMHasTrap(pVM));
1133 AssertMsgReturn((RTGCPTR)((RTGCUINTPTR)GCPtrPar1 & ~(RTGCUINTPTR)3) == pvFault,
1134 ("GCPtrPar1=%VGv pvFault=%VGv\n", GCPtrPar1, pvFault),
1135 VERR_EM_INTERPRETER);
1136#endif
1137
1138 /* Try emulate it with a one-shot #PF handler in place. */
1139 RTGCUINTREG32 eflags = 0;
1140#ifdef IN_GC
1141 MMGCRamRegisterTrapHandler(pVM);
1142#endif
1143 rc = pfnEmulate(pvParam1, ValPar2, &eflags);
1144#ifdef IN_GC
1145 MMGCRamDeregisterTrapHandler(pVM);
1146#endif
1147 if (RT_FAILURE(rc))
1148 {
1149 Log(("emInterpretLockBitTest %s: %VGv imm%d=%RX64 -> emulation failed due to page fault!\n",
1150 emGetMnemonic(pCpu), GCPtrPar1, pCpu->param2.size*8, ValPar2));
1151 return VERR_EM_INTERPRETER;
1152 }
1153
1154 Log2(("emInterpretLockBitTest %s: GCPtrPar1=%VGv imm=%VX64 CF=%d\n", emGetMnemonic(pCpu), GCPtrPar1, ValPar2, !!(eflags & X86_EFL_CF)));
1155
1156 /* Update guest's eflags and finish. */
1157 pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF))
1158 | (eflags & (X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF));
1159
1160 *pcbSize = 1;
1161 return VINF_SUCCESS;
1162}
1163
1164/**
1165 * MOV emulation.
1166 */
1167static int emInterpretMov(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1168{
1169 OP_PARAMVAL param1, param2;
1170 int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
1171 if(VBOX_FAILURE(rc))
1172 return VERR_EM_INTERPRETER;
1173
1174 rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1175 if(VBOX_FAILURE(rc))
1176 return VERR_EM_INTERPRETER;
1177
1178#ifdef IN_GC
1179 if (TRPMHasTrap(pVM))
1180 {
1181 if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1182 {
1183#else
1184 /** @todo Make this the default and don't rely on TRPM information. */
1185 if (param1.type == PARMTYPE_ADDRESS)
1186 {
1187#endif
1188 RTGCPTR pDest;
1189 uint64_t val64;
1190
1191 switch(param1.type)
1192 {
1193 case PARMTYPE_IMMEDIATE:
1194 if(!(param1.flags & (PARAM_VAL32|PARAM_VAL64)))
1195 return VERR_EM_INTERPRETER;
1196 /* fallthru */
1197
1198 case PARMTYPE_ADDRESS:
1199 pDest = (RTGCPTR)param1.val.val64;
1200 pDest = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pDest);
1201 break;
1202
1203 default:
1204 AssertFailed();
1205 return VERR_EM_INTERPRETER;
1206 }
1207
1208 switch(param2.type)
1209 {
1210 case PARMTYPE_IMMEDIATE: /* register type is translated to this one too */
1211 val64 = param2.val.val64;
1212 break;
1213
1214 default:
1215 Log(("emInterpretMov: unexpected type=%d eip=%VGv\n", param2.type, pRegFrame->rip));
1216 return VERR_EM_INTERPRETER;
1217 }
1218#ifdef LOG_ENABLED
1219 if (pCpu->mode == CPUMODE_64BIT)
1220 LogFlow(("EMInterpretInstruction at %VGv: OP_MOV %VGv <- %RX64 (%d) &val32=%VHv\n", pRegFrame->rip, pDest, val64, param2.size, &val64));
1221 else
1222 LogFlow(("EMInterpretInstruction at %VGv: OP_MOV %VGv <- %08X (%d) &val32=%VHv\n", pRegFrame->rip, pDest, (uint32_t)val64, param2.size, &val64));
1223#endif
1224
1225 Assert(param2.size <= 8 && param2.size > 0);
1226
1227#if 0 /* CSAM/PATM translates aliases which causes this to incorrectly trigger. See #2609 and #1498. */
1228#ifdef IN_GC
1229 /* Safety check (in theory it could cross a page boundary and fault there though) */
1230 AssertMsgReturn(pDest == pvFault, ("eip=%VGv pDest=%VGv pvFault=%VGv\n", pRegFrame->rip, pDest, pvFault), VERR_EM_INTERPRETER);
1231#endif
1232#endif
1233 rc = emRamWrite(pVM, pDest, &val64, param2.size);
1234 if (VBOX_FAILURE(rc))
1235 return VERR_EM_INTERPRETER;
1236
1237 *pcbSize = param2.size;
1238 }
1239 else
1240 { /* read fault */
1241 RTGCPTR pSrc;
1242 uint64_t val64;
1243
1244 /* Source */
1245 switch(param2.type)
1246 {
1247 case PARMTYPE_IMMEDIATE:
1248 if(!(param2.flags & (PARAM_VAL32|PARAM_VAL64)))
1249 return VERR_EM_INTERPRETER;
1250 /* fallthru */
1251
1252 case PARMTYPE_ADDRESS:
1253 pSrc = (RTGCPTR)param2.val.val64;
1254 pSrc = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param2, pSrc);
1255 break;
1256
1257 default:
1258 return VERR_EM_INTERPRETER;
1259 }
1260
1261 Assert(param1.size <= 8 && param1.size > 0);
1262#ifdef IN_GC
1263 /* Safety check (in theory it could cross a page boundary and fault there though) */
1264 AssertReturn(pSrc == pvFault, VERR_EM_INTERPRETER);
1265#endif
1266 rc = emRamRead(pVM, &val64, pSrc, param1.size);
1267 if (VBOX_FAILURE(rc))
1268 return VERR_EM_INTERPRETER;
1269
1270 /* Destination */
1271 switch(param1.type)
1272 {
1273 case PARMTYPE_REGISTER:
1274 switch(param1.size)
1275 {
1276 case 1: rc = DISWriteReg8(pRegFrame, pCpu->param1.base.reg_gen, (uint8_t) val64); break;
1277 case 2: rc = DISWriteReg16(pRegFrame, pCpu->param1.base.reg_gen, (uint16_t)val64); break;
1278 case 4: rc = DISWriteReg32(pRegFrame, pCpu->param1.base.reg_gen, (uint32_t)val64); break;
1279 case 8: rc = DISWriteReg64(pRegFrame, pCpu->param1.base.reg_gen, val64); break;
1280 default:
1281 return VERR_EM_INTERPRETER;
1282 }
1283 if (VBOX_FAILURE(rc))
1284 return rc;
1285 break;
1286
1287 default:
1288 return VERR_EM_INTERPRETER;
1289 }
1290#ifdef LOG_ENABLED
1291 if (pCpu->mode == CPUMODE_64BIT)
1292 LogFlow(("EMInterpretInstruction: OP_MOV %VGv -> %RX64 (%d)\n", pSrc, val64, param1.size));
1293 else
1294 LogFlow(("EMInterpretInstruction: OP_MOV %VGv -> %08X (%d)\n", pSrc, (uint32_t)val64, param1.size));
1295#endif
1296 }
1297 return VINF_SUCCESS;
1298#ifdef IN_GC
1299 }
1300#endif
1301 return VERR_EM_INTERPRETER;
1302}
1303
1304#ifndef IN_GC
1305/*
1306 * [REP] STOSWD emulation
1307 *
1308 */
1309static int emInterpretStosWD(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1310{
1311 int rc;
1312 RTGCPTR GCDest, GCOffset;
1313 uint32_t cbSize;
1314 uint64_t cTransfers;
1315 int offIncrement;
1316
1317 /* Don't support any but these three prefix bytes. */
1318 if ((pCpu->prefix & ~(PREFIX_ADDRSIZE|PREFIX_OPSIZE|PREFIX_REP|PREFIX_REX)))
1319 return VERR_EM_INTERPRETER;
1320
1321 switch (pCpu->addrmode)
1322 {
1323 case CPUMODE_16BIT:
1324 GCOffset = pRegFrame->di;
1325 cTransfers = pRegFrame->cx;
1326 break;
1327 case CPUMODE_32BIT:
1328 GCOffset = pRegFrame->edi;
1329 cTransfers = pRegFrame->ecx;
1330 break;
1331 case CPUMODE_64BIT:
1332 GCOffset = pRegFrame->rdi;
1333 cTransfers = pRegFrame->rcx;
1334 break;
1335 default:
1336 AssertFailed();
1337 return VERR_EM_INTERPRETER;
1338 }
1339
1340 GCDest = SELMToFlat(pVM, DIS_SELREG_ES, pRegFrame, GCOffset);
1341 switch (pCpu->opmode)
1342 {
1343 case CPUMODE_16BIT:
1344 cbSize = 2;
1345 break;
1346 case CPUMODE_32BIT:
1347 cbSize = 4;
1348 break;
1349 case CPUMODE_64BIT:
1350 cbSize = 8;
1351 break;
1352 default:
1353 AssertFailed();
1354 return VERR_EM_INTERPRETER;
1355 }
1356
1357 offIncrement = pRegFrame->eflags.Bits.u1DF ? -(signed)cbSize : (signed)cbSize;
1358
1359 if (!(pCpu->prefix & PREFIX_REP))
1360 {
1361 LogFlow(("emInterpretStosWD dest=%04X:%VGv (%VGv) cbSize=%d\n", pRegFrame->es, GCOffset, GCDest, cbSize));
1362
1363 rc = PGMPhysWriteGCPtrSafe(pVM, GCDest, &pRegFrame->rax, cbSize);
1364 if (VBOX_FAILURE(rc))
1365 return VERR_EM_INTERPRETER;
1366 Assert(rc == VINF_SUCCESS);
1367
1368 /* Update (e/r)di. */
1369 switch (pCpu->addrmode)
1370 {
1371 case CPUMODE_16BIT:
1372 pRegFrame->di += offIncrement;
1373 break;
1374 case CPUMODE_32BIT:
1375 pRegFrame->edi += offIncrement;
1376 break;
1377 case CPUMODE_64BIT:
1378 pRegFrame->rdi += offIncrement;
1379 break;
1380 default:
1381 AssertFailed();
1382 return VERR_EM_INTERPRETER;
1383 }
1384
1385 }
1386 else
1387 {
1388 if (!cTransfers)
1389 return VINF_SUCCESS;
1390
1391 LogFlow(("emInterpretStosWD dest=%04X:%VGv (%VGv) cbSize=%d cTransfers=%x DF=%d\n", pRegFrame->es, GCOffset, GCDest, cbSize, cTransfers, pRegFrame->eflags.Bits.u1DF));
1392
1393 /* Access verification first; we currently can't recover properly from traps inside this instruction */
1394 rc = PGMVerifyAccess(pVM, GCDest - (offIncrement > 0) ? 0 : ((cTransfers-1) * cbSize), cTransfers * cbSize, X86_PTE_RW | X86_PTE_US);
1395 if (rc != VINF_SUCCESS)
1396 {
1397 Log(("STOSWD will generate a trap -> recompiler, rc=%d\n", rc));
1398 return VERR_EM_INTERPRETER;
1399 }
1400
1401 /* REP case */
1402 while (cTransfers)
1403 {
1404 rc = PGMPhysWriteGCPtrSafe(pVM, GCDest, &pRegFrame->rax, cbSize);
1405 if (VBOX_FAILURE(rc))
1406 {
1407 rc = VERR_EM_INTERPRETER;
1408 break;
1409 }
1410
1411 Assert(rc == VINF_SUCCESS);
1412 GCOffset += offIncrement;
1413 GCDest += offIncrement;
1414 cTransfers--;
1415 }
1416
1417 /* Update the registers. */
1418 switch (pCpu->addrmode)
1419 {
1420 case CPUMODE_16BIT:
1421 pRegFrame->di = GCOffset;
1422 pRegFrame->cx = cTransfers;
1423 break;
1424 case CPUMODE_32BIT:
1425 pRegFrame->edi = GCOffset;
1426 pRegFrame->ecx = cTransfers;
1427 break;
1428 case CPUMODE_64BIT:
1429 pRegFrame->rdi = GCOffset;
1430 pRegFrame->rcx = cTransfers;
1431 break;
1432 default:
1433 AssertFailed();
1434 return VERR_EM_INTERPRETER;
1435 }
1436 }
1437
1438 *pcbSize = cbSize;
1439 return rc;
1440}
1441#endif
1442
1443
1444/*
1445 * [LOCK] CMPXCHG emulation.
1446 */
1447#ifndef IN_GC
1448static int emInterpretCmpXchg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1449{
1450 OP_PARAMVAL param1, param2;
1451
1452#ifdef LOG_ENABLED
1453 const char *pszInstr;
1454
1455 if (pCpu->prefix & PREFIX_LOCK)
1456 pszInstr = "Lock CmpXchg";
1457 else
1458 pszInstr = "CmpXchg";
1459#endif
1460
1461 /* Source to make DISQueryParamVal read the register value - ugly hack */
1462 int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1463 if(VBOX_FAILURE(rc))
1464 return VERR_EM_INTERPRETER;
1465
1466 rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1467 if(VBOX_FAILURE(rc))
1468 return VERR_EM_INTERPRETER;
1469
1470 RTGCPTR GCPtrPar1;
1471 void *pvParam1;
1472 uint64_t valpar, eflags;
1473
1474 AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
1475 switch(param1.type)
1476 {
1477 case PARMTYPE_ADDRESS:
1478 GCPtrPar1 = param1.val.val64;
1479 GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
1480
1481 rc = PGMPhysGCPtr2HCPtr(pVM, GCPtrPar1, &pvParam1);
1482 if (VBOX_FAILURE(rc))
1483 {
1484 AssertRC(rc);
1485 return VERR_EM_INTERPRETER;
1486 }
1487 break;
1488
1489 default:
1490 return VERR_EM_INTERPRETER;
1491 }
1492
1493 switch(param2.type)
1494 {
1495 case PARMTYPE_IMMEDIATE: /* register actually */
1496 valpar = param2.val.val64;
1497 break;
1498
1499 default:
1500 return VERR_EM_INTERPRETER;
1501 }
1502
1503 LogFlow(("%s %VGv rax=%RX64 %RX64\n", pszInstr, GCPtrPar1, pRegFrame->rax, valpar));
1504
1505 if (pCpu->prefix & PREFIX_LOCK)
1506 eflags = EMEmulateLockCmpXchg(pvParam1, &pRegFrame->rax, valpar, pCpu->param2.size);
1507 else
1508 eflags = EMEmulateCmpXchg(pvParam1, &pRegFrame->rax, valpar, pCpu->param2.size);
1509
1510 LogFlow(("%s %VGv rax=%RX64 %RX64 ZF=%d\n", pszInstr, GCPtrPar1, pRegFrame->rax, valpar, !!(eflags & X86_EFL_ZF)));
1511
1512 /* Update guest's eflags and finish. */
1513 pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF))
1514 | (eflags & (X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF));
1515
1516 *pcbSize = param2.size;
1517 return VINF_SUCCESS;
1518}
1519
1520#else
1521static int emInterpretCmpXchg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1522{
1523 Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
1524 OP_PARAMVAL param1, param2;
1525
1526#ifdef LOG_ENABLED
1527 const char *pszInstr;
1528
1529 if (pCpu->prefix & PREFIX_LOCK)
1530 pszInstr = "Lock CmpXchg";
1531 else
1532 pszInstr = "CmpXchg";
1533#endif
1534
1535 /* Source to make DISQueryParamVal read the register value - ugly hack */
1536 int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1537 if(VBOX_FAILURE(rc))
1538 return VERR_EM_INTERPRETER;
1539
1540 rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1541 if(VBOX_FAILURE(rc))
1542 return VERR_EM_INTERPRETER;
1543
1544 if (TRPMHasTrap(pVM))
1545 {
1546 if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1547 {
1548 RTRCPTR pParam1;
1549 uint32_t valpar, eflags;
1550
1551 AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
1552 switch(param1.type)
1553 {
1554 case PARMTYPE_ADDRESS:
1555 pParam1 = (RTRCPTR)param1.val.val64;
1556 pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);
1557
1558 /* Safety check (in theory it could cross a page boundary and fault there though) */
1559 AssertMsgReturn(pParam1 == (RTRCPTR)pvFault, ("eip=%VGv pParam1=%VRv pvFault=%VGv\n", pRegFrame->rip, pParam1, pvFault), VERR_EM_INTERPRETER);
1560 break;
1561
1562 default:
1563 return VERR_EM_INTERPRETER;
1564 }
1565
1566 switch(param2.type)
1567 {
1568 case PARMTYPE_IMMEDIATE: /* register actually */
1569 valpar = param2.val.val32;
1570 break;
1571
1572 default:
1573 return VERR_EM_INTERPRETER;
1574 }
1575
1576 LogFlow(("%s %VRv eax=%08x %08x\n", pszInstr, pParam1, pRegFrame->eax, valpar));
1577
1578 MMGCRamRegisterTrapHandler(pVM);
1579 if (pCpu->prefix & PREFIX_LOCK)
1580 rc = EMGCEmulateLockCmpXchg(pParam1, &pRegFrame->eax, valpar, pCpu->param2.size, &eflags);
1581 else
1582 rc = EMGCEmulateCmpXchg(pParam1, &pRegFrame->eax, valpar, pCpu->param2.size, &eflags);
1583 MMGCRamDeregisterTrapHandler(pVM);
1584
1585 if (VBOX_FAILURE(rc))
1586 {
1587 Log(("%s %VGv eax=%08x %08x -> emulation failed due to page fault!\n", pszInstr, pParam1, pRegFrame->eax, valpar));
1588 return VERR_EM_INTERPRETER;
1589 }
1590
1591 LogFlow(("%s %VRv eax=%08x %08x ZF=%d\n", pszInstr, pParam1, pRegFrame->eax, valpar, !!(eflags & X86_EFL_ZF)));
1592
1593 /* Update guest's eflags and finish. */
1594 pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF))
1595 | (eflags & (X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF));
1596
1597 *pcbSize = param2.size;
1598 return VINF_SUCCESS;
1599 }
1600 }
1601 return VERR_EM_INTERPRETER;
1602}
1603
1604/*
1605 * [LOCK] CMPXCHG8B emulation.
1606 */
1607static int emInterpretCmpXchg8b(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1608{
1609 Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
1610 OP_PARAMVAL param1;
1611
1612#ifdef LOG_ENABLED
1613 const char *pszInstr;
1614
1615 if (pCpu->prefix & PREFIX_LOCK)
1616 pszInstr = "Lock CmpXchg8b";
1617 else
1618 pszInstr = "CmpXchg8b";
1619#endif
1620
1621 /* Source to make DISQueryParamVal read the register value - ugly hack */
1622 int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1623 if(VBOX_FAILURE(rc))
1624 return VERR_EM_INTERPRETER;
1625
1626 if (TRPMHasTrap(pVM))
1627 {
1628 if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1629 {
1630 RTRCPTR pParam1;
1631 uint32_t eflags;
1632
1633 AssertReturn(pCpu->param1.size == 8, VERR_EM_INTERPRETER);
1634 switch(param1.type)
1635 {
1636 case PARMTYPE_ADDRESS:
1637 pParam1 = (RTRCPTR)param1.val.val64;
1638 pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);
1639
1640 /* Safety check (in theory it could cross a page boundary and fault there though) */
1641 AssertMsgReturn(pParam1 == (RTRCPTR)pvFault, ("eip=%VGv pParam1=%VRv pvFault=%VGv\n", pRegFrame->rip, pParam1, pvFault), VERR_EM_INTERPRETER);
1642 break;
1643
1644 default:
1645 return VERR_EM_INTERPRETER;
1646 }
1647
1648 LogFlow(("%s %VRv=%08x eax=%08x\n", pszInstr, pParam1, pRegFrame->eax));
1649
1650 MMGCRamRegisterTrapHandler(pVM);
1651 if (pCpu->prefix & PREFIX_LOCK)
1652 rc = EMGCEmulateLockCmpXchg8b(pParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx, &eflags);
1653 else
1654 rc = EMGCEmulateCmpXchg8b(pParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx, &eflags);
1655 MMGCRamDeregisterTrapHandler(pVM);
1656
1657 if (VBOX_FAILURE(rc))
1658 {
1659 Log(("%s %VGv=%08x eax=%08x -> emulation failed due to page fault!\n", pszInstr, pParam1, pRegFrame->eax));
1660 return VERR_EM_INTERPRETER;
1661 }
1662
1663 LogFlow(("%s %VGv=%08x eax=%08x ZF=%d\n", pszInstr, pParam1, pRegFrame->eax, !!(eflags & X86_EFL_ZF)));
1664
1665 /* Update guest's eflags and finish; note that *only* ZF is affected. */
1666 pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_ZF))
1667 | (eflags & (X86_EFL_ZF));
1668
1669 *pcbSize = 8;
1670 return VINF_SUCCESS;
1671 }
1672 }
1673 return VERR_EM_INTERPRETER;
1674}
1675#endif
1676
1677/*
1678 * [LOCK] XADD emulation.
1679 */
1680#ifdef IN_GC
1681static int emInterpretXAdd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1682{
1683 Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
1684 OP_PARAMVAL param1;
1685 uint32_t *pParamReg2;
1686 size_t cbSizeParamReg2;
1687
1688 /* Source to make DISQueryParamVal read the register value - ugly hack */
1689 int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1690 if(VBOX_FAILURE(rc))
1691 return VERR_EM_INTERPRETER;
1692
1693 rc = DISQueryParamRegPtr(pRegFrame, pCpu, &pCpu->param2, (void **)&pParamReg2, &cbSizeParamReg2);
1694 Assert(cbSizeParamReg2 <= 4);
1695 if(VBOX_FAILURE(rc))
1696 return VERR_EM_INTERPRETER;
1697
1698 if (TRPMHasTrap(pVM))
1699 {
1700 if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1701 {
1702 RTRCPTR pParam1;
1703 uint32_t eflags;
1704
1705 AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
1706 switch(param1.type)
1707 {
1708 case PARMTYPE_ADDRESS:
1709 pParam1 = (RTRCPTR)param1.val.val64;
1710 pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);
1711
1712 /* Safety check (in theory it could cross a page boundary and fault there though) */
1713 AssertMsgReturn(pParam1 == (RTRCPTR)pvFault, ("eip=%VGv pParam1=%VRv pvFault=%VGv\n", pRegFrame->rip, pParam1, pvFault), VERR_EM_INTERPRETER);
1714 break;
1715
1716 default:
1717 return VERR_EM_INTERPRETER;
1718 }
1719
1720 LogFlow(("XAdd %VRv=%08x reg=%08x\n", pParam1, *pParamReg2));
1721
1722 MMGCRamRegisterTrapHandler(pVM);
1723 if (pCpu->prefix & PREFIX_LOCK)
1724 rc = EMGCEmulateLockXAdd(pParam1, pParamReg2, cbSizeParamReg2, &eflags);
1725 else
1726 rc = EMGCEmulateXAdd(pParam1, pParamReg2, cbSizeParamReg2, &eflags);
1727 MMGCRamDeregisterTrapHandler(pVM);
1728
1729 if (VBOX_FAILURE(rc))
1730 {
1731 Log(("XAdd %VGv reg=%08x -> emulation failed due to page fault!\n", pParam1, *pParamReg2));
1732 return VERR_EM_INTERPRETER;
1733 }
1734
1735 LogFlow(("XAdd %VGv reg=%08x ZF=%d\n", pParam1, *pParamReg2, !!(eflags & X86_EFL_ZF)));
1736
1737 /* Update guest's eflags and finish. */
1738 pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF))
1739 | (eflags & (X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF));
1740
1741 *pcbSize = cbSizeParamReg2;
1742 return VINF_SUCCESS;
1743 }
1744 }
1745 return VERR_EM_INTERPRETER;
1746}
1747#endif
1748
1749#ifdef IN_GC
1750/**
1751 * Interpret IRET (currently only to V86 code)
1752 *
1753 * @returns VBox status code.
1754 * @param pVM The VM handle.
1755 * @param pRegFrame The register frame.
1756 *
1757 */
1758EMDECL(int) EMInterpretIret(PVM pVM, PCPUMCTXCORE pRegFrame)
1759{
1760 RTGCUINTPTR pIretStack = (RTGCUINTPTR)pRegFrame->esp;
1761 RTGCUINTPTR eip, cs, esp, ss, eflags, ds, es, fs, gs, uMask;
1762 int rc;
1763
1764 Assert(!CPUMIsGuestIn64BitCode(pVM, pRegFrame));
1765
1766 rc = emRamRead(pVM, &eip, (RTGCPTR)pIretStack , 4);
1767 rc |= emRamRead(pVM, &cs, (RTGCPTR)(pIretStack + 4), 4);
1768 rc |= emRamRead(pVM, &eflags, (RTGCPTR)(pIretStack + 8), 4);
1769 AssertRCReturn(rc, VERR_EM_INTERPRETER);
1770 AssertReturn(eflags & X86_EFL_VM, VERR_EM_INTERPRETER);
1771
1772 rc |= emRamRead(pVM, &esp, (RTGCPTR)(pIretStack + 12), 4);
1773 rc |= emRamRead(pVM, &ss, (RTGCPTR)(pIretStack + 16), 4);
1774 rc |= emRamRead(pVM, &es, (RTGCPTR)(pIretStack + 20), 4);
1775 rc |= emRamRead(pVM, &ds, (RTGCPTR)(pIretStack + 24), 4);
1776 rc |= emRamRead(pVM, &fs, (RTGCPTR)(pIretStack + 28), 4);
1777 rc |= emRamRead(pVM, &gs, (RTGCPTR)(pIretStack + 32), 4);
1778 AssertRCReturn(rc, VERR_EM_INTERPRETER);
1779
1780 pRegFrame->eip = eip & 0xffff;
1781 pRegFrame->cs = cs;
1782
1783 /* Mask away all reserved bits */
1784 uMask = X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_RF | X86_EFL_VM | X86_EFL_AC | X86_EFL_VIF | X86_EFL_VIP | X86_EFL_ID;
1785 eflags &= uMask;
1786
1787#ifndef IN_RING0
1788 CPUMRawSetEFlags(pVM, pRegFrame, eflags);
1789#endif
1790 Assert((pRegFrame->eflags.u32 & (X86_EFL_IF|X86_EFL_IOPL)) == X86_EFL_IF);
1791
1792 pRegFrame->esp = esp;
1793 pRegFrame->ss = ss;
1794 pRegFrame->ds = ds;
1795 pRegFrame->es = es;
1796 pRegFrame->fs = fs;
1797 pRegFrame->gs = gs;
1798
1799 return VINF_SUCCESS;
1800}
1801#endif
1802
1803/**
1804 * IRET Emulation.
1805 */
1806static int emInterpretIret(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1807{
1808 /* only allow direct calls to EMInterpretIret for now */
1809 return VERR_EM_INTERPRETER;
1810}
1811
1812/**
1813 * INVLPG Emulation.
1814 */
1815
1816/**
1817 * Interpret INVLPG
1818 *
1819 * @returns VBox status code.
1820 * @param pVM The VM handle.
1821 * @param pRegFrame The register frame.
1822 * @param pAddrGC Operand address
1823 *
1824 */
1825EMDECL(int) EMInterpretInvlpg(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC)
1826{
1827 int rc;
1828
1829 /** @todo is addr always a flat linear address or ds based
1830 * (in absence of segment override prefixes)????
1831 */
1832#ifdef IN_GC
1833 // Note: we could also use PGMFlushPage here, but it currently doesn't always use invlpg!!!!!!!!!!
1834 LogFlow(("GC: EMULATE: invlpg %08X\n", pAddrGC));
1835 rc = PGMGCInvalidatePage(pVM, pAddrGC);
1836#else
1837 rc = PGMInvalidatePage(pVM, pAddrGC);
1838#endif
1839 if (VBOX_SUCCESS(rc))
1840 return VINF_SUCCESS;
1841 Log(("PGMInvalidatePage %VGv returned %VGv (%d)\n", pAddrGC, rc, rc));
1842 Assert(rc == VERR_REM_FLUSHED_PAGES_OVERFLOW);
1843 /** @todo r=bird: we shouldn't ignore returns codes like this... I'm 99% sure the error is fatal. */
1844 return VERR_EM_INTERPRETER;
1845}
1846
1847static int emInterpretInvlPg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1848{
1849 OP_PARAMVAL param1;
1850 RTGCPTR addr;
1851
1852 int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1853 if(VBOX_FAILURE(rc))
1854 return VERR_EM_INTERPRETER;
1855
1856 switch(param1.type)
1857 {
1858 case PARMTYPE_IMMEDIATE:
1859 case PARMTYPE_ADDRESS:
1860 if(!(param1.flags & (PARAM_VAL32|PARAM_VAL64)))
1861 return VERR_EM_INTERPRETER;
1862 addr = (RTGCPTR)param1.val.val64;
1863 break;
1864
1865 default:
1866 return VERR_EM_INTERPRETER;
1867 }
1868
1869 /** @todo is addr always a flat linear address or ds based
1870 * (in absence of segment override prefixes)????
1871 */
1872#ifdef IN_GC
1873 // Note: we could also use PGMFlushPage here, but it currently doesn't always use invlpg!!!!!!!!!!
1874 LogFlow(("GC: EMULATE: invlpg %08X\n", addr));
1875 rc = PGMGCInvalidatePage(pVM, addr);
1876#else
1877 rc = PGMInvalidatePage(pVM, addr);
1878#endif
1879 if (VBOX_SUCCESS(rc))
1880 return VINF_SUCCESS;
1881 /** @todo r=bird: we shouldn't ignore returns codes like this... I'm 99% sure the error is fatal. */
1882 return VERR_EM_INTERPRETER;
1883}
1884
1885/**
1886 * CPUID Emulation.
1887 */
1888
1889/**
1890 * Interpret CPUID given the parameters in the CPU context
1891 *
1892 * @returns VBox status code.
1893 * @param pVM The VM handle.
1894 * @param pRegFrame The register frame.
1895 *
1896 */
1897EMDECL(int) EMInterpretCpuId(PVM pVM, PCPUMCTXCORE pRegFrame)
1898{
1899 uint32_t iLeaf = pRegFrame->eax; NOREF(iLeaf);
1900
1901 /* Note: operates the same in 64 and non-64 bits mode. */
1902 CPUMGetGuestCpuId(pVM, pRegFrame->eax, &pRegFrame->eax, &pRegFrame->ebx, &pRegFrame->ecx, &pRegFrame->edx);
1903 Log(("Emulate: CPUID %x -> %08x %08x %08x %08x\n", iLeaf, pRegFrame->eax, pRegFrame->ebx, pRegFrame->ecx, pRegFrame->edx));
1904 return VINF_SUCCESS;
1905}
1906
1907static int emInterpretCpuId(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1908{
1909 int rc = EMInterpretCpuId(pVM, pRegFrame);
1910 return rc;
1911}
1912
1913/**
1914 * MOV CRx Emulation.
1915 */
1916
1917/**
1918 * Interpret CRx read
1919 *
1920 * @returns VBox status code.
1921 * @param pVM The VM handle.
1922 * @param pRegFrame The register frame.
1923 * @param DestRegGen General purpose register index (USE_REG_E**))
1924 * @param SrcRegCRx CRx register index (USE_REG_CR*)
1925 *
1926 */
1927EMDECL(int) EMInterpretCRxRead(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx)
1928{
1929 int rc;
1930 uint64_t val64;
1931
1932 if (SrcRegCrx == USE_REG_CR8)
1933 {
1934 val64 = 0;
1935 rc = PDMApicGetTPR(pVM, (uint8_t *)&val64, NULL);
1936 AssertMsgRCReturn(rc, ("PDMApicGetTPR failed\n"), VERR_EM_INTERPRETER);
1937 }
1938 else
1939 {
1940 rc = CPUMGetGuestCRx(pVM, SrcRegCrx, &val64);
1941 AssertMsgRCReturn(rc, ("CPUMGetGuestCRx %d failed\n", SrcRegCrx), VERR_EM_INTERPRETER);
1942 }
1943
1944 if (CPUMIsGuestIn64BitCode(pVM, pRegFrame))
1945 rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
1946 else
1947 rc = DISWriteReg32(pRegFrame, DestRegGen, val64);
1948
1949 if(VBOX_SUCCESS(rc))
1950 {
1951 LogFlow(("MOV_CR: gen32=%d CR=%d val=%VX64\n", DestRegGen, SrcRegCrx, val64));
1952 return VINF_SUCCESS;
1953 }
1954 return VERR_EM_INTERPRETER;
1955}
1956
1957
1958/**
1959 * Interpret LMSW
1960 *
1961 * @returns VBox status code.
1962 * @param pVM The VM handle.
1963 * @param u16Data LMSW source data.
1964 *
1965 */
1966EMDECL(int) EMInterpretLMSW(PVM pVM, uint16_t u16Data)
1967{
1968 uint64_t OldCr0 = CPUMGetGuestCR0(pVM);
1969
1970 /* don't use this path to go into protected mode! */
1971 Assert(OldCr0 & X86_CR0_PE);
1972 if (!(OldCr0 & X86_CR0_PE))
1973 return VERR_EM_INTERPRETER;
1974
1975 /* Only PE, MP, EM and TS can be changed; note that PE can't be cleared by this instruction. */
1976 uint64_t NewCr0 = ( OldCr0 & ~( X86_CR0_MP | X86_CR0_EM | X86_CR0_TS))
1977 | (u16Data & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS));
1978
1979#ifdef IN_GC
1980 /* Need to change the hyper CR0? Doing it the lazy way then. */
1981 if ( (OldCr0 & (X86_CR0_AM | X86_CR0_WP))
1982 != (NewCr0 & (X86_CR0_AM | X86_CR0_WP)))
1983 {
1984 Log(("EMInterpretLMSW: CR0: %#x->%#x => R3\n", OldCr0, NewCr0));
1985 VM_FF_SET(pVM, VM_FF_TO_R3);
1986 }
1987#endif
1988
1989 return CPUMSetGuestCR0(pVM, NewCr0);
1990}
1991
1992
1993/**
1994 * Interpret CLTS
1995 *
1996 * @returns VBox status code.
1997 * @param pVM The VM handle.
1998 *
1999 */
2000EMDECL(int) EMInterpretCLTS(PVM pVM)
2001{
2002 uint64_t cr0 = CPUMGetGuestCR0(pVM);
2003 if (!(cr0 & X86_CR0_TS))
2004 return VINF_SUCCESS;
2005 return CPUMSetGuestCR0(pVM, cr0 & ~X86_CR0_TS);
2006}
2007
2008static int emInterpretClts(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2009{
2010 return EMInterpretCLTS(pVM);
2011}
2012
2013/**
2014 * Interpret CRx write
2015 *
2016 * @returns VBox status code.
2017 * @param pVM The VM handle.
2018 * @param pRegFrame The register frame.
2019 * @param DestRegCRx CRx register index (USE_REG_CR*)
2020 * @param SrcRegGen General purpose register index (USE_REG_E**))
2021 *
2022 */
2023EMDECL(int) EMInterpretCRxWrite(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint32_t SrcRegGen)
2024{
2025 uint64_t val;
2026 uint64_t oldval;
2027 uint64_t msrEFER;
2028 int rc;
2029
2030 /** @todo Clean up this mess. */
2031 if (CPUMIsGuestIn64BitCode(pVM, pRegFrame))
2032 {
2033 rc = DISFetchReg64(pRegFrame, SrcRegGen, &val);
2034 }
2035 else
2036 {
2037 uint32_t val32;
2038 rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
2039 val = val32;
2040 }
2041
2042 if (VBOX_SUCCESS(rc))
2043 {
2044 LogFlow(("EMInterpretCRxWrite at %VGv CR%d <- %VX64\n", pRegFrame->rip, DestRegCrx, val));
2045 switch (DestRegCrx)
2046 {
2047 case USE_REG_CR0:
2048 oldval = CPUMGetGuestCR0(pVM);
2049#ifdef IN_GC
2050 /* CR0.WP and CR0.AM changes require a reschedule run in ring 3. */
2051 if ( (val & (X86_CR0_WP | X86_CR0_AM))
2052 != (oldval & (X86_CR0_WP | X86_CR0_AM)))
2053 return VERR_EM_INTERPRETER;
2054#endif
2055 CPUMSetGuestCR0(pVM, val);
2056 val = CPUMGetGuestCR0(pVM);
2057 if ( (oldval & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE))
2058 != (val & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)))
2059 {
2060 /* global flush */
2061 rc = PGMFlushTLB(pVM, CPUMGetGuestCR3(pVM), true /* global */);
2062 AssertRCReturn(rc, rc);
2063 }
2064
2065 /* Deal with long mode enabling/disabling. */
2066 msrEFER = CPUMGetGuestEFER(pVM);
2067 if (msrEFER & MSR_K6_EFER_LME)
2068 {
2069 if ( !(oldval & X86_CR0_PG)
2070 && (val & X86_CR0_PG))
2071 {
2072 /* Illegal to have an active 64 bits CS selector (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
2073 if (pRegFrame->csHid.Attr.n.u1Long)
2074 {
2075 AssertMsgFailed(("Illegal enabling of paging with CS.u1Long = 1!!\n"));
2076 return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
2077 }
2078
2079 /* Illegal to switch to long mode before activating PAE first (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
2080 if (!(CPUMGetGuestCR4(pVM) & X86_CR4_PAE))
2081 {
2082 AssertMsgFailed(("Illegal enabling of paging with PAE disabled!!\n"));
2083 return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
2084 }
2085 msrEFER |= MSR_K6_EFER_LMA;
2086 }
2087 else
2088 if ( (oldval & X86_CR0_PG)
2089 && !(val & X86_CR0_PG))
2090 {
2091 msrEFER &= ~MSR_K6_EFER_LMA;
2092 /* @todo Do we need to cut off rip here? High dword of rip is undefined, so it shouldn't really matter. */
2093 }
2094 CPUMSetGuestEFER(pVM, msrEFER);
2095 }
2096 return PGMChangeMode(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR4(pVM), CPUMGetGuestEFER(pVM));
2097
2098 case USE_REG_CR2:
2099 rc = CPUMSetGuestCR2(pVM, val); AssertRC(rc);
2100 return VINF_SUCCESS;
2101
2102 case USE_REG_CR3:
2103 /* Reloading the current CR3 means the guest just wants to flush the TLBs */
2104 rc = CPUMSetGuestCR3(pVM, val); AssertRC(rc);
2105 if (CPUMGetGuestCR0(pVM) & X86_CR0_PG)
2106 {
2107 /* flush */
2108 rc = PGMFlushTLB(pVM, val, !(CPUMGetGuestCR4(pVM) & X86_CR4_PGE));
2109 AssertRCReturn(rc, rc);
2110 }
2111 return VINF_SUCCESS;
2112
2113 case USE_REG_CR4:
2114 oldval = CPUMGetGuestCR4(pVM);
2115 rc = CPUMSetGuestCR4(pVM, val); AssertRC(rc);
2116 val = CPUMGetGuestCR4(pVM);
2117
2118 msrEFER = CPUMGetGuestEFER(pVM);
2119 /* Illegal to disable PAE when long mode is active. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
2120 if ( (msrEFER & MSR_K6_EFER_LMA)
2121 && (oldval & X86_CR4_PAE)
2122 && !(val & X86_CR4_PAE))
2123 {
2124 return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
2125 }
2126
2127 if ( (oldval & (X86_CR4_PGE|X86_CR4_PAE|X86_CR4_PSE))
2128 != (val & (X86_CR4_PGE|X86_CR4_PAE|X86_CR4_PSE)))
2129 {
2130 /* global flush */
2131 rc = PGMFlushTLB(pVM, CPUMGetGuestCR3(pVM), true /* global */);
2132 AssertRCReturn(rc, rc);
2133 }
2134# ifdef IN_GC
2135 /* Feeling extremely lazy. */
2136 if ( (oldval & (X86_CR4_OSFSXR|X86_CR4_OSXMMEEXCPT|X86_CR4_PCE|X86_CR4_MCE|X86_CR4_PAE|X86_CR4_DE|X86_CR4_TSD|X86_CR4_PVI|X86_CR4_VME))
2137 != (val & (X86_CR4_OSFSXR|X86_CR4_OSXMMEEXCPT|X86_CR4_PCE|X86_CR4_MCE|X86_CR4_PAE|X86_CR4_DE|X86_CR4_TSD|X86_CR4_PVI|X86_CR4_VME)))
2138 {
2139 Log(("emInterpretMovCRx: CR4: %#RX64->%#RX64 => R3\n", oldval, val));
2140 VM_FF_SET(pVM, VM_FF_TO_R3);
2141 }
2142# endif
2143 return PGMChangeMode(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR4(pVM), CPUMGetGuestEFER(pVM));
2144
2145 case USE_REG_CR8:
2146 return PDMApicSetTPR(pVM, val);
2147
2148 default:
2149 AssertFailed();
2150 case USE_REG_CR1: /* illegal op */
2151 break;
2152 }
2153 }
2154 return VERR_EM_INTERPRETER;
2155}
2156
2157static int emInterpretMovCRx(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2158{
2159 if ((pCpu->param1.flags == USE_REG_GEN32 || pCpu->param1.flags == USE_REG_GEN64) && pCpu->param2.flags == USE_REG_CR)
2160 return EMInterpretCRxRead(pVM, pRegFrame, pCpu->param1.base.reg_gen, pCpu->param2.base.reg_ctrl);
2161
2162 if (pCpu->param1.flags == USE_REG_CR && (pCpu->param2.flags == USE_REG_GEN32 || pCpu->param2.flags == USE_REG_GEN64))
2163 return EMInterpretCRxWrite(pVM, pRegFrame, pCpu->param1.base.reg_ctrl, pCpu->param2.base.reg_gen);
2164
2165 AssertMsgFailedReturn(("Unexpected control register move\n"), VERR_EM_INTERPRETER);
2166 return VERR_EM_INTERPRETER;
2167}
2168
2169/**
2170 * MOV DRx
2171 */
2172
2173/**
2174 * Interpret DRx write
2175 *
2176 * @returns VBox status code.
2177 * @param pVM The VM handle.
2178 * @param pRegFrame The register frame.
2179 * @param DestRegDRx DRx register index (USE_REG_DR*)
2180 * @param SrcRegGen General purpose register index (USE_REG_E**))
2181 *
2182 */
2183EMDECL(int) EMInterpretDRxWrite(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen)
2184{
2185 uint64_t val;
2186 int rc;
2187
2188 if (CPUMIsGuestIn64BitCode(pVM, pRegFrame))
2189 {
2190 rc = DISFetchReg64(pRegFrame, SrcRegGen, &val);
2191 }
2192 else
2193 {
2194 uint32_t val32;
2195 rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
2196 val = val32;
2197 }
2198
2199 if (VBOX_SUCCESS(rc))
2200 {
2201 rc = CPUMSetGuestDRx(pVM, DestRegDrx, val);
2202 if (VBOX_SUCCESS(rc))
2203 return rc;
2204 AssertMsgFailed(("CPUMSetGuestDRx %d failed\n", DestRegDrx));
2205 }
2206 return VERR_EM_INTERPRETER;
2207}
2208
2209/**
2210 * Interpret DRx read
2211 *
2212 * @returns VBox status code.
2213 * @param pVM The VM handle.
2214 * @param pRegFrame The register frame.
2215 * @param DestRegGen General purpose register index (USE_REG_E**))
2216 * @param SrcRegDRx DRx register index (USE_REG_DR*)
2217 *
2218 */
2219EMDECL(int) EMInterpretDRxRead(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx)
2220{
2221 uint64_t val64;
2222
2223 int rc = CPUMGetGuestDRx(pVM, SrcRegDrx, &val64);
2224 AssertMsgRCReturn(rc, ("CPUMGetGuestDRx %d failed\n", SrcRegDrx), VERR_EM_INTERPRETER);
2225 if (CPUMIsGuestIn64BitCode(pVM, pRegFrame))
2226 {
2227 rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
2228 }
2229 else
2230 rc = DISWriteReg32(pRegFrame, DestRegGen, (uint32_t)val64);
2231
2232 if (VBOX_SUCCESS(rc))
2233 return VINF_SUCCESS;
2234
2235 return VERR_EM_INTERPRETER;
2236}
2237
2238static int emInterpretMovDRx(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2239{
2240 int rc = VERR_EM_INTERPRETER;
2241
2242 if((pCpu->param1.flags == USE_REG_GEN32 || pCpu->param1.flags == USE_REG_GEN64) && pCpu->param2.flags == USE_REG_DBG)
2243 {
2244 rc = EMInterpretDRxRead(pVM, pRegFrame, pCpu->param1.base.reg_gen, pCpu->param2.base.reg_dbg);
2245 }
2246 else
2247 if(pCpu->param1.flags == USE_REG_DBG && (pCpu->param2.flags == USE_REG_GEN32 || pCpu->param2.flags == USE_REG_GEN64))
2248 {
2249 rc = EMInterpretDRxWrite(pVM, pRegFrame, pCpu->param1.base.reg_dbg, pCpu->param2.base.reg_gen);
2250 }
2251 else
2252 AssertMsgFailed(("Unexpected debug register move\n"));
2253
2254 return rc;
2255}
2256
2257/**
2258 * LLDT Emulation.
2259 */
2260static int emInterpretLLdt(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2261{
2262 OP_PARAMVAL param1;
2263 RTSEL sel;
2264
2265 int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
2266 if(VBOX_FAILURE(rc))
2267 return VERR_EM_INTERPRETER;
2268
2269 switch(param1.type)
2270 {
2271 case PARMTYPE_ADDRESS:
2272 return VERR_EM_INTERPRETER; //feeling lazy right now
2273
2274 case PARMTYPE_IMMEDIATE:
2275 if(!(param1.flags & PARAM_VAL16))
2276 return VERR_EM_INTERPRETER;
2277 sel = (RTSEL)param1.val.val16;
2278 break;
2279
2280 default:
2281 return VERR_EM_INTERPRETER;
2282 }
2283
2284 if (sel == 0)
2285 {
2286 if (CPUMGetHyperLDTR(pVM) == 0)
2287 {
2288 // this simple case is most frequent in Windows 2000 (31k - boot & shutdown)
2289 return VINF_SUCCESS;
2290 }
2291 }
2292 //still feeling lazy
2293 return VERR_EM_INTERPRETER;
2294}
2295
2296#ifdef IN_GC
2297/**
2298 * STI Emulation.
2299 *
2300 * @remark the instruction following sti is guaranteed to be executed before any interrupts are dispatched
2301 */
2302static int emInterpretSti(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2303{
2304 PPATMGCSTATE pGCState = PATMQueryGCState(pVM);
2305
2306 if(!pGCState)
2307 {
2308 Assert(pGCState);
2309 return VERR_EM_INTERPRETER;
2310 }
2311 pGCState->uVMFlags |= X86_EFL_IF;
2312
2313 Assert(pRegFrame->eflags.u32 & X86_EFL_IF);
2314 Assert(pvFault == SELMToFlat(pVM, DIS_SELREG_CS, pRegFrame, (RTGCPTR)pRegFrame->rip));
2315
2316 pVM->em.s.GCPtrInhibitInterrupts = pRegFrame->eip + pCpu->opsize;
2317 VM_FF_SET(pVM, VM_FF_INHIBIT_INTERRUPTS);
2318
2319 return VINF_SUCCESS;
2320}
2321#endif /* IN_GC */
2322
2323
2324/**
2325 * HLT Emulation.
2326 */
2327static int emInterpretHlt(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2328{
2329 return VINF_EM_HALT;
2330}
2331
2332
2333/**
2334 * RDTSC Emulation.
2335 */
2336
2337/**
2338 * Interpret RDTSC
2339 *
2340 * @returns VBox status code.
2341 * @param pVM The VM handle.
2342 * @param pRegFrame The register frame.
2343 *
2344 */
2345EMDECL(int) EMInterpretRdtsc(PVM pVM, PCPUMCTXCORE pRegFrame)
2346{
2347 unsigned uCR4 = CPUMGetGuestCR4(pVM);
2348
2349 if (uCR4 & X86_CR4_TSD)
2350 return VERR_EM_INTERPRETER; /* genuine #GP */
2351
2352 uint64_t uTicks = TMCpuTickGet(pVM);
2353
2354 /* Same behaviour in 32 & 64 bits mode */
2355 pRegFrame->eax = uTicks;
2356 pRegFrame->edx = (uTicks >> 32ULL);
2357
2358 return VINF_SUCCESS;
2359}
2360
2361static int emInterpretRdtsc(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2362{
2363 return EMInterpretRdtsc(pVM, pRegFrame);
2364}
2365
2366/**
2367 * MONITOR Emulation.
2368 */
2369static int emInterpretMonitor(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2370{
2371 uint32_t u32Dummy, u32ExtFeatures, cpl;
2372
2373 Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
2374 if (pRegFrame->ecx != 0)
2375 return VERR_EM_INTERPRETER; /* illegal value. */
2376
2377 /* Get the current privilege level. */
2378 cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2379 if (cpl != 0)
2380 return VERR_EM_INTERPRETER; /* supervisor only */
2381
2382 CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
2383 if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
2384 return VERR_EM_INTERPRETER; /* not supported */
2385
2386 return VINF_SUCCESS;
2387}
2388
2389
2390/**
2391 * MWAIT Emulation.
2392 */
2393static int emInterpretMWait(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2394{
2395 uint32_t u32Dummy, u32ExtFeatures, cpl;
2396
2397 Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
2398 if (pRegFrame->ecx != 0)
2399 return VERR_EM_INTERPRETER; /* illegal value. */
2400
2401 /* Get the current privilege level. */
2402 cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2403 if (cpl != 0)
2404 return VERR_EM_INTERPRETER; /* supervisor only */
2405
2406 CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
2407 if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
2408 return VERR_EM_INTERPRETER; /* not supported */
2409
2410 /** @todo not completely correct */
2411 return VINF_EM_HALT;
2412}
2413
2414#ifdef LOG_ENABLED
2415static const char *emMSRtoString(unsigned uMsr)
2416{
2417 switch(uMsr)
2418 {
2419 case MSR_IA32_APICBASE:
2420 return "MSR_IA32_APICBASE";
2421 case MSR_IA32_CR_PAT:
2422 return "MSR_IA32_CR_PAT";
2423 case MSR_IA32_SYSENTER_CS:
2424 return "MSR_IA32_SYSENTER_CS";
2425 case MSR_IA32_SYSENTER_EIP:
2426 return "MSR_IA32_SYSENTER_EIP";
2427 case MSR_IA32_SYSENTER_ESP:
2428 return "MSR_IA32_SYSENTER_ESP";
2429 case MSR_K6_EFER:
2430 return "MSR_K6_EFER";
2431 case MSR_K8_SF_MASK:
2432 return "MSR_K8_SF_MASK";
2433 case MSR_K6_STAR:
2434 return "MSR_K6_STAR";
2435 case MSR_K8_LSTAR:
2436 return "MSR_K8_LSTAR";
2437 case MSR_K8_CSTAR:
2438 return "MSR_K8_CSTAR";
2439 case MSR_K8_FS_BASE:
2440 return "MSR_K8_FS_BASE";
2441 case MSR_K8_GS_BASE:
2442 return "MSR_K8_GS_BASE";
2443 case MSR_K8_KERNEL_GS_BASE:
2444 return "MSR_K8_KERNEL_GS_BASE";
2445 case MSR_IA32_BIOS_SIGN_ID:
2446 return "Unsupported MSR_IA32_BIOS_SIGN_ID";
2447 case MSR_IA32_PLATFORM_ID:
2448 return "Unsupported MSR_IA32_PLATFORM_ID";
2449 case MSR_IA32_BIOS_UPDT_TRIG:
2450 return "Unsupported MSR_IA32_BIOS_UPDT_TRIG";
2451 case MSR_IA32_TSC:
2452 return "Unsupported MSR_IA32_TSC";
2453 case MSR_IA32_MTRR_CAP:
2454 return "Unsupported MSR_IA32_MTRR_CAP";
2455 case MSR_IA32_MCP_CAP:
2456 return "Unsupported MSR_IA32_MCP_CAP";
2457 case MSR_IA32_MCP_STATUS:
2458 return "Unsupported MSR_IA32_MCP_STATUS";
2459 case MSR_IA32_MCP_CTRL:
2460 return "Unsupported MSR_IA32_MCP_CTRL";
2461 case MSR_IA32_MTRR_DEF_TYPE:
2462 return "Unsupported MSR_IA32_MTRR_DEF_TYPE";
2463 case MSR_K7_EVNTSEL0:
2464 return "Unsupported MSR_K7_EVNTSEL0";
2465 case MSR_K7_EVNTSEL1:
2466 return "Unsupported MSR_K7_EVNTSEL1";
2467 case MSR_K7_EVNTSEL2:
2468 return "Unsupported MSR_K7_EVNTSEL2";
2469 case MSR_K7_EVNTSEL3:
2470 return "Unsupported MSR_K7_EVNTSEL3";
2471 case MSR_IA32_MC0_CTL:
2472 return "Unsupported MSR_IA32_MC0_CTL";
2473 case MSR_IA32_MC0_STATUS:
2474 return "Unsupported MSR_IA32_MC0_STATUS";
2475 }
2476 return "Unknown MSR";
2477}
2478#endif
2479
2480/**
2481 * Interpret RDMSR
2482 *
2483 * @returns VBox status code.
2484 * @param pVM The VM handle.
2485 * @param pRegFrame The register frame.
2486 *
2487 */
2488EMDECL(int) EMInterpretRdmsr(PVM pVM, PCPUMCTXCORE pRegFrame)
2489{
2490 uint32_t u32Dummy, u32Features, cpl;
2491 uint64_t val;
2492 CPUMCTX *pCtx;
2493 int rc;
2494
2495 /** @todo According to the Intel manuals, there's a REX version of RDMSR that is slightly different.
2496 * That version clears the high dwords of both RDX & RAX */
2497 rc = CPUMQueryGuestCtxPtr(pVM, &pCtx);
2498 AssertRC(rc);
2499
2500 /* Get the current privilege level. */
2501 cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2502 if (cpl != 0)
2503 return VERR_EM_INTERPRETER; /* supervisor only */
2504
2505 CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2506 if (!(u32Features & X86_CPUID_FEATURE_EDX_MSR))
2507 return VERR_EM_INTERPRETER; /* not supported */
2508
2509 switch (pRegFrame->ecx)
2510 {
2511 case MSR_IA32_APICBASE:
2512 rc = PDMApicGetBase(pVM, &val);
2513 AssertRC(rc);
2514 break;
2515
2516 case MSR_IA32_CR_PAT:
2517 val = pCtx->msrPAT;
2518 break;
2519
2520 case MSR_IA32_SYSENTER_CS:
2521 val = pCtx->SysEnter.cs;
2522 break;
2523
2524 case MSR_IA32_SYSENTER_EIP:
2525 val = pCtx->SysEnter.eip;
2526 break;
2527
2528 case MSR_IA32_SYSENTER_ESP:
2529 val = pCtx->SysEnter.esp;
2530 break;
2531
2532 case MSR_K6_EFER:
2533 val = pCtx->msrEFER;
2534 break;
2535
2536 case MSR_K8_SF_MASK:
2537 val = pCtx->msrSFMASK;
2538 break;
2539
2540 case MSR_K6_STAR:
2541 val = pCtx->msrSTAR;
2542 break;
2543
2544 case MSR_K8_LSTAR:
2545 val = pCtx->msrLSTAR;
2546 break;
2547
2548 case MSR_K8_CSTAR:
2549 val = pCtx->msrCSTAR;
2550 break;
2551
2552 case MSR_K8_FS_BASE:
2553 val = pCtx->fsHid.u64Base;
2554 break;
2555
2556 case MSR_K8_GS_BASE:
2557 val = pCtx->gsHid.u64Base;
2558 break;
2559
2560 case MSR_K8_KERNEL_GS_BASE:
2561 val = pCtx->msrKERNELGSBASE;
2562 break;
2563
2564#if 0 /*def IN_RING0 */
2565 case MSR_IA32_PLATFORM_ID:
2566 case MSR_IA32_BIOS_SIGN_ID:
2567 if (CPUMGetCPUVendor(pVM) == CPUMCPUVENDOR_INTEL)
2568 {
2569 /* Available since the P6 family. VT-x implies that this feature is present. */
2570 if (pRegFrame->ecx == MSR_IA32_PLATFORM_ID)
2571 val = ASMRdMsr(MSR_IA32_PLATFORM_ID);
2572 else
2573 if (pRegFrame->ecx == MSR_IA32_BIOS_SIGN_ID)
2574 val = ASMRdMsr(MSR_IA32_BIOS_SIGN_ID);
2575 break;
2576 }
2577 /* no break */
2578#endif
2579 default:
2580 /* We should actually trigger a #GP here, but don't as that might cause more trouble. */
2581 val = 0;
2582 break;
2583 }
2584 Log(("EMInterpretRdmsr %s (%x) -> val=%VX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx, val));
2585 pRegFrame->eax = (uint32_t) val;
2586 pRegFrame->edx = (uint32_t) (val >> 32ULL);
2587 return VINF_SUCCESS;
2588}
2589
2590/**
2591 * RDMSR Emulation.
2592 */
2593static int emInterpretRdmsr(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2594{
2595 /* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
2596 Assert(!(pCpu->prefix & PREFIX_REX));
2597 return EMInterpretRdmsr(pVM, pRegFrame);
2598}
2599
2600/**
2601 * Interpret WRMSR
2602 *
2603 * @returns VBox status code.
2604 * @param pVM The VM handle.
2605 * @param pRegFrame The register frame.
2606 *
2607 */
2608EMDECL(int) EMInterpretWrmsr(PVM pVM, PCPUMCTXCORE pRegFrame)
2609{
2610 uint32_t u32Dummy, u32Features, cpl;
2611 uint64_t val;
2612 CPUMCTX *pCtx;
2613 int rc;
2614
2615 /* Note: works the same in 32 and 64 bits modes. */
2616 rc = CPUMQueryGuestCtxPtr(pVM, &pCtx);
2617 AssertRC(rc);
2618
2619 /* Get the current privilege level. */
2620 cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2621 if (cpl != 0)
2622 return VERR_EM_INTERPRETER; /* supervisor only */
2623
2624 CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2625 if (!(u32Features & X86_CPUID_FEATURE_EDX_MSR))
2626 return VERR_EM_INTERPRETER; /* not supported */
2627
2628 val = (uint64_t)pRegFrame->eax | ((uint64_t)pRegFrame->edx << 32ULL);
2629 Log(("EMInterpretWrmsr %s (%x) val=%VX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx, val));
2630 switch (pRegFrame->ecx)
2631 {
2632 case MSR_IA32_APICBASE:
2633 rc = PDMApicSetBase(pVM, val);
2634 AssertRC(rc);
2635 break;
2636
2637 case MSR_IA32_CR_PAT:
2638 pCtx->msrPAT = val;
2639 break;
2640
2641 case MSR_IA32_SYSENTER_CS:
2642 pCtx->SysEnter.cs = val & 0xffff; /* 16 bits selector */
2643 break;
2644
2645 case MSR_IA32_SYSENTER_EIP:
2646 pCtx->SysEnter.eip = val;
2647 break;
2648
2649 case MSR_IA32_SYSENTER_ESP:
2650 pCtx->SysEnter.esp = val;
2651 break;
2652
2653 case MSR_K6_EFER:
2654 {
2655 uint64_t uMask = 0;
2656 uint64_t oldval = pCtx->msrEFER;
2657
2658 /* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
2659 CPUMGetGuestCpuId(pVM, 0x80000001, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2660 if (u32Features & X86_CPUID_AMD_FEATURE_EDX_NX)
2661 uMask |= MSR_K6_EFER_NXE;
2662 if (u32Features & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE)
2663 uMask |= MSR_K6_EFER_LME;
2664 if (u32Features & X86_CPUID_AMD_FEATURE_EDX_SEP)
2665 uMask |= MSR_K6_EFER_SCE;
2666 if (u32Features & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
2667 uMask |= MSR_K6_EFER_FFXSR;
2668
2669 /* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
2670 if ( ((pCtx->msrEFER & MSR_K6_EFER_LME) != (val & uMask & MSR_K6_EFER_LME))
2671 && (pCtx->cr0 & X86_CR0_PG))
2672 {
2673 AssertMsgFailed(("Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
2674 return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
2675 }
2676
2677 /* There are a few more: e.g. MSR_K6_EFER_LMSLE */
2678 AssertMsg(!(val & ~(MSR_K6_EFER_NXE|MSR_K6_EFER_LME|MSR_K6_EFER_LMA /* ignored anyway */ |MSR_K6_EFER_SCE|MSR_K6_EFER_FFXSR)), ("Unexpected value %RX64\n", val));
2679 pCtx->msrEFER = (pCtx->msrEFER & ~uMask) | (val & uMask);
2680
2681 /* AMD64 Achitecture Programmer's Manual: 15.15 TLB Control; flush the TLB if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
2682 if ((oldval & (MSR_K6_EFER_NXE|MSR_K6_EFER_LME|MSR_K6_EFER_LMA)) != (pCtx->msrEFER & (MSR_K6_EFER_NXE|MSR_K6_EFER_LME|MSR_K6_EFER_LMA)))
2683 HWACCMFlushTLB(pVM);
2684
2685 break;
2686 }
2687
2688 case MSR_K8_SF_MASK:
2689 pCtx->msrSFMASK = val;
2690 break;
2691
2692 case MSR_K6_STAR:
2693 pCtx->msrSTAR = val;
2694 break;
2695
2696 case MSR_K8_LSTAR:
2697 pCtx->msrLSTAR = val;
2698 break;
2699
2700 case MSR_K8_CSTAR:
2701 pCtx->msrCSTAR = val;
2702 break;
2703
2704 case MSR_K8_FS_BASE:
2705 pCtx->fsHid.u64Base = val;
2706 break;
2707
2708 case MSR_K8_GS_BASE:
2709 pCtx->gsHid.u64Base = val;
2710 break;
2711
2712 case MSR_K8_KERNEL_GS_BASE:
2713 pCtx->msrKERNELGSBASE = val;
2714 break;
2715
2716 default:
2717 /* We should actually trigger a #GP here, but don't as that might cause more trouble. */
2718 break;
2719 }
2720 return VINF_SUCCESS;
2721}
2722
2723/**
2724 * WRMSR Emulation.
2725 */
2726static int emInterpretWrmsr(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2727{
2728 return EMInterpretWrmsr(pVM, pRegFrame);
2729}
2730
2731/**
2732 * Internal worker.
2733 * @copydoc EMInterpretInstructionCPU
2734 */
2735DECLINLINE(int) emInterpretInstructionCPU(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2736{
2737 Assert(pcbSize);
2738 *pcbSize = 0;
2739
2740 /*
2741 * Only supervisor guest code!!
2742 * And no complicated prefixes.
2743 */
2744 /* Get the current privilege level. */
2745 uint32_t cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2746 if ( cpl != 0
2747 && pCpu->pCurInstr->opcode != OP_RDTSC) /* rdtsc requires emulation in ring 3 as well */
2748 {
2749 Log(("WARNING: refusing instruction emulation for user-mode code!!\n"));
2750 STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,FailedUserMode));
2751 return VERR_EM_INTERPRETER;
2752 }
2753
2754#ifdef IN_GC
2755 if ( (pCpu->prefix & (PREFIX_REPNE | PREFIX_REP))
2756 || ( (pCpu->prefix & PREFIX_LOCK)
2757 && pCpu->pCurInstr->opcode != OP_CMPXCHG
2758 && pCpu->pCurInstr->opcode != OP_CMPXCHG8B
2759 && pCpu->pCurInstr->opcode != OP_XADD
2760 && pCpu->pCurInstr->opcode != OP_OR
2761 && pCpu->pCurInstr->opcode != OP_BTR
2762 )
2763 )
2764#else
2765 if ( (pCpu->prefix & PREFIX_REPNE)
2766 || ( (pCpu->prefix & PREFIX_REP)
2767 && pCpu->pCurInstr->opcode != OP_STOSWD
2768 )
2769 || ( (pCpu->prefix & PREFIX_LOCK)
2770 && pCpu->pCurInstr->opcode != OP_OR
2771 && pCpu->pCurInstr->opcode != OP_BTR
2772 )
2773 )
2774#endif
2775 {
2776 //Log(("EMInterpretInstruction: wrong prefix!!\n"));
2777 STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,FailedPrefix));
2778 return VERR_EM_INTERPRETER;
2779 }
2780
2781 int rc;
2782#if (defined(VBOX_STRICT) || defined(LOG_ENABLED))
2783 LogFlow(("emInterpretInstructionCPU %s\n", emGetMnemonic(pCpu)));
2784#endif
2785 switch (pCpu->pCurInstr->opcode)
2786 {
2787# define INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
2788 case opcode:\
2789 if (pCpu->prefix & PREFIX_LOCK) \
2790 rc = emInterpretLock##InstrFn(pVM, pCpu, pRegFrame, pvFault, pcbSize, pfnEmulateLock); \
2791 else \
2792 rc = emInterpret##InstrFn(pVM, pCpu, pRegFrame, pvFault, pcbSize, pfnEmulate); \
2793 if (VBOX_SUCCESS(rc)) \
2794 STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,Instr)); \
2795 else \
2796 STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,Failed##Instr)); \
2797 return rc
2798#define INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate) \
2799 case opcode:\
2800 rc = emInterpret##InstrFn(pVM, pCpu, pRegFrame, pvFault, pcbSize, pfnEmulate); \
2801 if (VBOX_SUCCESS(rc)) \
2802 STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,Instr)); \
2803 else \
2804 STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,Failed##Instr)); \
2805 return rc
2806
2807#define INTERPRET_CASE_EX_PARAM2(opcode, Instr, InstrFn, pfnEmulate) \
2808 INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate)
2809#define INTERPRET_CASE_EX_LOCK_PARAM2(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
2810 INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock)
2811
2812#define INTERPRET_CASE(opcode, Instr) \
2813 case opcode:\
2814 rc = emInterpret##Instr(pVM, pCpu, pRegFrame, pvFault, pcbSize); \
2815 if (VBOX_SUCCESS(rc)) \
2816 STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,Instr)); \
2817 else \
2818 STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,Failed##Instr)); \
2819 return rc
2820#define INTERPRET_STAT_CASE(opcode, Instr) \
2821 case opcode: STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,Failed##Instr)); return VERR_EM_INTERPRETER;
2822
2823 INTERPRET_CASE(OP_XCHG,Xchg);
2824 INTERPRET_CASE_EX_PARAM2(OP_DEC,Dec, IncDec, EMEmulateDec);
2825 INTERPRET_CASE_EX_PARAM2(OP_INC,Inc, IncDec, EMEmulateInc);
2826 INTERPRET_CASE(OP_POP,Pop);
2827 INTERPRET_CASE_EX_LOCK_PARAM3(OP_OR, Or, OrXorAnd, EMEmulateOr, EMEmulateLockOr);
2828 INTERPRET_CASE_EX_PARAM3(OP_XOR,Xor, OrXorAnd, EMEmulateXor);
2829 INTERPRET_CASE_EX_PARAM3(OP_AND,And, OrXorAnd, EMEmulateAnd);
2830 INTERPRET_CASE(OP_MOV,Mov);
2831#ifndef IN_GC
2832 INTERPRET_CASE(OP_STOSWD,StosWD);
2833#endif
2834 INTERPRET_CASE(OP_INVLPG,InvlPg);
2835 INTERPRET_CASE(OP_CPUID,CpuId);
2836 INTERPRET_CASE(OP_MOV_CR,MovCRx);
2837 INTERPRET_CASE(OP_MOV_DR,MovDRx);
2838 INTERPRET_CASE(OP_LLDT,LLdt);
2839 INTERPRET_CASE(OP_CLTS,Clts);
2840 INTERPRET_CASE(OP_MONITOR, Monitor);
2841 INTERPRET_CASE(OP_MWAIT, MWait);
2842 INTERPRET_CASE(OP_RDMSR, Rdmsr);
2843 INTERPRET_CASE(OP_WRMSR, Wrmsr);
2844 INTERPRET_CASE_EX_PARAM3(OP_ADD,Add, AddSub, EMEmulateAdd);
2845 INTERPRET_CASE_EX_PARAM3(OP_SUB,Sub, AddSub, EMEmulateSub);
2846 INTERPRET_CASE(OP_ADC,Adc);
2847 INTERPRET_CASE_EX_LOCK_PARAM2(OP_BTR,Btr, BitTest, EMEmulateBtr, EMEmulateLockBtr);
2848 INTERPRET_CASE_EX_PARAM2(OP_BTS,Bts, BitTest, EMEmulateBts);
2849 INTERPRET_CASE_EX_PARAM2(OP_BTC,Btc, BitTest, EMEmulateBtc);
2850 INTERPRET_CASE(OP_RDTSC,Rdtsc);
2851 INTERPRET_CASE(OP_CMPXCHG, CmpXchg);
2852#ifdef IN_GC
2853 INTERPRET_CASE(OP_STI,Sti);
2854 INTERPRET_CASE(OP_CMPXCHG8B, CmpXchg8b);
2855 INTERPRET_CASE(OP_XADD, XAdd);
2856#endif
2857 INTERPRET_CASE(OP_HLT,Hlt);
2858 INTERPRET_CASE(OP_IRET,Iret);
2859#ifdef VBOX_WITH_STATISTICS
2860#ifndef IN_GC
2861 INTERPRET_STAT_CASE(OP_CMPXCHG8B, CmpXchg8b);
2862 INTERPRET_STAT_CASE(OP_XADD, XAdd);
2863#endif
2864 INTERPRET_STAT_CASE(OP_MOVNTPS,MovNTPS);
2865 INTERPRET_STAT_CASE(OP_WBINVD,WbInvd);
2866#endif
2867 default:
2868 Log3(("emInterpretInstructionCPU: opcode=%d\n", pCpu->pCurInstr->opcode));
2869 STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,FailedMisc));
2870 return VERR_EM_INTERPRETER;
2871#undef INTERPRET_CASE_EX_PARAM2
2872#undef INTERPRET_STAT_CASE
2873#undef INTERPRET_CASE_EX
2874#undef INTERPRET_CASE
2875 }
2876 AssertFailed();
2877 return VERR_INTERNAL_ERROR;
2878}
2879
2880
2881/**
2882 * Sets the PC for which interrupts should be inhibited.
2883 *
2884 * @param pVM The VM handle.
2885 * @param PC The PC.
2886 */
2887EMDECL(void) EMSetInhibitInterruptsPC(PVM pVM, RTGCUINTPTR PC)
2888{
2889 pVM->em.s.GCPtrInhibitInterrupts = PC;
2890 VM_FF_SET(pVM, VM_FF_INHIBIT_INTERRUPTS);
2891}
2892
2893
2894/**
2895 * Gets the PC for which interrupts should be inhibited.
2896 *
2897 * There are a few instructions which inhibits or delays interrupts
2898 * for the instruction following them. These instructions are:
2899 * - STI
2900 * - MOV SS, r/m16
2901 * - POP SS
2902 *
2903 * @returns The PC for which interrupts should be inhibited.
2904 * @param pVM VM handle.
2905 *
2906 */
2907EMDECL(RTGCUINTPTR) EMGetInhibitInterruptsPC(PVM pVM)
2908{
2909 return pVM->em.s.GCPtrInhibitInterrupts;
2910}
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