EMAll.cpp@ 12305

Last change on this file since 12305 was 12305, checked in by vboxsync, 16 years ago
Flush the recompiler's TB cache each time we detect writes to PATM/CSAM monitored pages.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 96.9 KB

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1	/* $Id: EMAll.cpp 12305 2008-09-09 15:50:15Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor(/Manager) - All contexts
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_EM
26	#include <VBox/em.h>
27	#include <VBox/mm.h>
28	#include <VBox/selm.h>
29	#include <VBox/patm.h>
30	#include <VBox/csam.h>
31	#include <VBox/pgm.h>
32	#include <VBox/iom.h>
33	#include <VBox/stam.h>
34	#include "EMInternal.h"
35	#include <VBox/vm.h>
36	#include <VBox/hwaccm.h>
37	#include <VBox/tm.h>
38	#include <VBox/pdmapi.h>
39
40	#include <VBox/param.h>
41	#include <VBox/err.h>
42	#include <VBox/dis.h>
43	#include <VBox/disopcode.h>
44	#include <VBox/log.h>
45	#include <iprt/assert.h>
46	#include <iprt/asm.h>
47	#include <iprt/string.h>
48
49
50	/*******************************************************************************
51	* Structures and Typedefs *
52	*******************************************************************************/
53
54
55	/*******************************************************************************
56	* Internal Functions *
57	*******************************************************************************/
58	DECLINLINE(int) emInterpretInstructionCPU(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize);
59
60
61	/**
62	* Get the current execution manager status.
63	*
64	* @returns Current status.
65	*/
66	EMDECL(EMSTATE) EMGetState(PVM pVM)
67	{
68	return pVM->em.s.enmState;
69	}
70
71	/**
72	* Flushes the REM translation blocks the next time we execute code there.
73	*
74	* @param pVM The VM handle.
75	*/
76	EMDECL(void) EMFlushREMTBs(PVM pVM)
77	{
78	pVM->em.s.fREMFlushTBs = true;
79	}
80
81	#ifndef IN_GC
82	/**
83	* Read callback for disassembly function; supports reading bytes that cross a page boundary
84	*
85	* @returns VBox status code.
86	* @param pSrc GC source pointer
87	* @param pDest HC destination pointer
88	* @param cb Number of bytes to read
89	* @param dwUserdata Callback specific user data (pCpu)
90	*
91	*/
92	DECLCALLBACK(int) EMReadBytes(RTUINTPTR pSrc, uint8_t pDest, unsigned cb, void pvUserdata)
93	{
94	DISCPUSTATE pCpu = (DISCPUSTATE )pvUserdata;
95	PVM pVM = (PVM)pCpu->apvUserData[0];
96	#ifdef IN_RING0
97	int rc = PGMPhysReadGCPtr(pVM, pDest, pSrc, cb);
98	AssertMsgRC(rc, ("PGMPhysReadGCPtr failed for pSrc=%VGv cb=%x\n", pSrc, cb));
99	#else
100	if (!PATMIsPatchGCAddr(pVM, pSrc))
101	{
102	int rc = PGMPhysReadGCPtr(pVM, pDest, pSrc, cb);
103	AssertRC(rc);
104	}
105	else
106	{
107	for (uint32_t i = 0; i < cb; i++)
108	{
109	uint8_t opcode;
110	if (VBOX_SUCCESS(PATMR3QueryOpcode(pVM, (RTGCPTR)pSrc + i, &opcode)))
111	{
112	*(pDest+i) = opcode;
113	}
114	}
115	}
116	#endif /* IN_RING0 */
117	return VINF_SUCCESS;
118	}
119
120	DECLINLINE(int) emDisCoreOne(PVM pVM, DISCPUSTATE pCpu, RTGCUINTPTR InstrGC, uint32_t pOpsize)
121	{
122	return DISCoreOneEx(InstrGC, pCpu->mode, EMReadBytes, pVM, pCpu, pOpsize);
123	}
124
125	#else
126
127	DECLINLINE(int) emDisCoreOne(PVM pVM, DISCPUSTATE pCpu, RTGCUINTPTR InstrGC, uint32_t pOpsize)
128	{
129	return DISCoreOne(pCpu, InstrGC, pOpsize);
130	}
131
132	#endif
133
134
135	/**
136	* Disassembles one instruction.
137	*
138	* @param pVM The VM handle.
139	* @param pCtxCore The context core (used for both the mode and instruction).
140	* @param pCpu Where to return the parsed instruction info.
141	* @param pcbInstr Where to return the instruction size. (optional)
142	*/
143	EMDECL(int) EMInterpretDisasOne(PVM pVM, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, unsigned *pcbInstr)
144	{
145	RTGCPTR GCPtrInstr;
146	int rc = SELMToFlatEx(pVM, DIS_SELREG_CS, pCtxCore, pCtxCore->rip, 0, &GCPtrInstr);
147	if (VBOX_FAILURE(rc))
148	{
149	Log(("EMInterpretDisasOne: Failed to convert %RTsel:%VGv (cpl=%d) - rc=%Vrc !!\n",
150	pCtxCore->cs, pCtxCore->rip, pCtxCore->ss & X86_SEL_RPL, rc));
151	return rc;
152	}
153	return EMInterpretDisasOneEx(pVM, (RTGCUINTPTR)GCPtrInstr, pCtxCore, pCpu, pcbInstr);
154	}
155
156
157	/**
158	* Disassembles one instruction.
159	*
160	* This is used by internally by the interpreter and by trap/access handlers.
161	*
162	* @param pVM The VM handle.
163	* @param GCPtrInstr The flat address of the instruction.
164	* @param pCtxCore The context core (used to determin the cpu mode).
165	* @param pCpu Where to return the parsed instruction info.
166	* @param pcbInstr Where to return the instruction size. (optional)
167	*/
168	EMDECL(int) EMInterpretDisasOneEx(PVM pVM, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, unsigned *pcbInstr)
169	{
170	int rc = DISCoreOneEx(GCPtrInstr, SELMGetCpuModeFromSelector(pVM, pCtxCore->eflags, pCtxCore->cs, (PCPUMSELREGHID)&pCtxCore->csHid),
171	#ifdef IN_GC
172	NULL, NULL,
173	#else
174	EMReadBytes, pVM,
175	#endif
176	pCpu, pcbInstr);
177	if (VBOX_SUCCESS(rc))
178	return VINF_SUCCESS;
179	AssertMsgFailed(("DISCoreOne failed to GCPtrInstr=%VGv rc=%Vrc\n", GCPtrInstr, rc));
180	return VERR_INTERNAL_ERROR;
181	}
182
183
184	/**
185	* Interprets the current instruction.
186	*
187	* @returns VBox status code.
188	* @retval VINF_* Scheduling instructions.
189	* @retval VERR_EM_INTERPRETER Something we can't cope with.
190	* @retval VERR_* Fatal errors.
191	*
192	* @param pVM The VM handle.
193	* @param pRegFrame The register frame.
194	* Updates the EIP if an instruction was executed successfully.
195	* @param pvFault The fault address (CR2).
196	* @param pcbSize Size of the write (if applicable).
197	*
198	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
199	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
200	* to worry about e.g. invalid modrm combinations (!)
201	*/
202	EMDECL(int) EMInterpretInstruction(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
203	{
204	RTGCPTR pbCode;
205
206	LogFlow(("EMInterpretInstruction %VGv fault %VGv\n", pRegFrame->rip, pvFault));
207	int rc = SELMToFlatEx(pVM, DIS_SELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
208	if (VBOX_SUCCESS(rc))
209	{
210	uint32_t cbOp;
211	DISCPUSTATE Cpu;
212	Cpu.mode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
213	rc = emDisCoreOne(pVM, &Cpu, (RTGCUINTPTR)pbCode, &cbOp);
214	if (VBOX_SUCCESS(rc))
215	{
216	Assert(cbOp == Cpu.opsize);
217	rc = EMInterpretInstructionCPU(pVM, &Cpu, pRegFrame, pvFault, pcbSize);
218	if (VBOX_SUCCESS(rc))
219	{
220	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
221	}
222	return rc;
223	}
224	}
225	return VERR_EM_INTERPRETER;
226	}
227
228	/**
229	* Interprets the current instruction using the supplied DISCPUSTATE structure.
230	*
231	* EIP is NOT updated!
232	*
233	* @returns VBox status code.
234	* @retval VINF_* Scheduling instructions. When these are returned, it
235	* starts to get a bit tricky to know whether code was
236	* executed or not... We'll address this when it becomes a problem.
237	* @retval VERR_EM_INTERPRETER Something we can't cope with.
238	* @retval VERR_* Fatal errors.
239	*
240	* @param pVM The VM handle.
241	* @param pCpu The disassembler cpu state for the instruction to be interpreted.
242	* @param pRegFrame The register frame. EIP is NOT changed!
243	* @param pvFault The fault address (CR2).
244	* @param pcbSize Size of the write (if applicable).
245	*
246	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
247	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
248	* to worry about e.g. invalid modrm combinations (!)
249	*
250	* @todo At this time we do NOT check if the instruction overwrites vital information.
251	* Make sure this can't happen!! (will add some assertions/checks later)
252	*/
253	EMDECL(int) EMInterpretInstructionCPU(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
254	{
255	STAM_PROFILE_START(&CTXMID(pVM->em.s.CTXSUFF(pStats)->Stat,Emulate), a);
256	int rc = emInterpretInstructionCPU(pVM, pCpu, pRegFrame, pvFault, pcbSize);
257	STAM_PROFILE_STOP(&CTXMID(pVM->em.s.CTXSUFF(pStats)->Stat,Emulate), a);
258	if (VBOX_SUCCESS(rc))
259	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,InterpretSucceeded));
260	else
261	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,InterpretFailed));
262	return rc;
263	}
264
265
266	/**
267	* Interpret a port I/O instruction.
268	*
269	* @returns VBox status code suitable for scheduling.
270	* @param pVM The VM handle.
271	* @param pCtxCore The context core. This will be updated on successful return.
272	* @param pCpu The instruction to interpret.
273	* @param cbOp The size of the instruction.
274	* @remark This may raise exceptions.
275	*/
276	EMDECL(int) EMInterpretPortIO(PVM pVM, PCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, uint32_t cbOp)
277	{
278	/*
279	* Hand it on to IOM.
280	*/
281	#ifdef IN_GC
282	int rc = IOMGCIOPortHandler(pVM, pCtxCore, pCpu);
283	if (IOM_SUCCESS(rc))
284	pCtxCore->rip += cbOp;
285	return rc;
286	#else
287	AssertReleaseMsgFailed(("not implemented\n"));
288	return VERR_NOT_IMPLEMENTED;
289	#endif
290	}
291
292
293	DECLINLINE(int) emRamRead(PVM pVM, void *pDest, RTGCPTR GCSrc, uint32_t cb)
294	{
295	#ifdef IN_GC
296	int rc = MMGCRamRead(pVM, pDest, (void *)GCSrc, cb);
297	if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
298	return rc;
299	/*
300	* The page pool cache may end up here in some cases because it
301	* flushed one of the shadow mappings used by the trapping
302	* instruction and it either flushed the TLB or the CPU reused it.
303	*/
304	RTGCPHYS GCPhys;
305	rc = PGMPhysGCPtr2GCPhys(pVM, GCSrc, &GCPhys);
306	AssertRCReturn(rc, rc);
307	PGMPhysRead(pVM, GCPhys, pDest, cb);
308	return VINF_SUCCESS;
309	#else
310	return PGMPhysReadGCPtrSafe(pVM, pDest, GCSrc, cb);
311	#endif
312	}
313
314	DECLINLINE(int) emRamWrite(PVM pVM, RTGCPTR GCDest, void *pSrc, uint32_t cb)
315	{
316	#ifdef IN_GC
317	int rc = MMGCRamWrite(pVM, (void *)GCDest, pSrc, cb);
318	if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
319	return rc;
320	/*
321	* The page pool cache may end up here in some cases because it
322	* flushed one of the shadow mappings used by the trapping
323	* instruction and it either flushed the TLB or the CPU reused it.
324	* We want to play safe here, verifying that we've got write
325	* access doesn't cost us much (see PGMPhysGCPtr2GCPhys()).
326	*/
327	uint64_t fFlags;
328	RTGCPHYS GCPhys;
329	rc = PGMGstGetPage(pVM, GCDest, &fFlags, &GCPhys);
330	if (RT_FAILURE(rc))
331	return rc;
332	if ( !(fFlags & X86_PTE_RW)
333	&& (CPUMGetGuestCR0(pVM) & X86_CR0_WP))
334	return VERR_ACCESS_DENIED;
335
336	PGMPhysWrite(pVM, GCPhys + ((RTGCUINTPTR)GCDest & PAGE_OFFSET_MASK), pSrc, cb);
337	return VINF_SUCCESS;
338
339	#else
340	return PGMPhysWriteGCPtrSafe(pVM, GCDest, pSrc, cb);
341	#endif
342	}
343
344	/* Convert sel:addr to a flat GC address */
345	static RTGCPTR emConvertToFlatAddr(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, POP_PARAMETER pParam, RTGCPTR pvAddr)
346	{
347	DIS_SELREG enmPrefixSeg = DISDetectSegReg(pCpu, pParam);
348	return SELMToFlat(pVM, enmPrefixSeg, pRegFrame, pvAddr);
349	}
350
351	#if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
352	/**
353	* Get the mnemonic for the disassembled instruction.
354	*
355	* GC/R0 doesn't include the strings in the DIS tables because
356	* of limited space.
357	*/
358	static const char *emGetMnemonic(PDISCPUSTATE pCpu)
359	{
360	switch (pCpu->pCurInstr->opcode)
361	{
362	case OP_XCHG: return "Xchg";
363	case OP_DEC: return "Dec";
364	case OP_INC: return "Inc";
365	case OP_POP: return "Pop";
366	case OP_OR: return "Or";
367	case OP_AND: return "And";
368	case OP_MOV: return "Mov";
369	case OP_INVLPG: return "InvlPg";
370	case OP_CPUID: return "CpuId";
371	case OP_MOV_CR: return "MovCRx";
372	case OP_MOV_DR: return "MovDRx";
373	case OP_LLDT: return "LLdt";
374	case OP_CLTS: return "Clts";
375	case OP_MONITOR: return "Monitor";
376	case OP_MWAIT: return "MWait";
377	case OP_RDMSR: return "Rdmsr";
378	case OP_WRMSR: return "Wrmsr";
379	case OP_ADC: return "Adc";
380	case OP_BTC: return "Btc";
381	case OP_RDTSC: return "Rdtsc";
382	case OP_STI: return "Sti";
383	case OP_XADD: return "XAdd";
384	case OP_HLT: return "Hlt";
385	case OP_IRET: return "Iret";
386	case OP_CMPXCHG: return "CmpXchg";
387	case OP_CMPXCHG8B: return "CmpXchg8b";
388	case OP_MOVNTPS: return "MovNTPS";
389	case OP_STOSWD: return "StosWD";
390	case OP_WBINVD: return "WbInvd";
391	case OP_XOR: return "Xor";
392	case OP_BTR: return "Btr";
393	case OP_BTS: return "Bts";
394	default:
395	Log(("Unknown opcode %d\n", pCpu->pCurInstr->opcode));
396	return "???";
397	}
398	}
399	#endif
400
401	/**
402	* XCHG instruction emulation.
403	*/
404	static int emInterpretXchg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
405	{
406	OP_PARAMVAL param1, param2;
407
408	/* Source to make DISQueryParamVal read the register value - ugly hack */
409	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
410	if(VBOX_FAILURE(rc))
411	return VERR_EM_INTERPRETER;
412
413	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
414	if(VBOX_FAILURE(rc))
415	return VERR_EM_INTERPRETER;
416
417	#ifdef IN_GC
418	if (TRPMHasTrap(pVM))
419	{
420	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
421	{
422	#endif
423	RTGCPTR pParam1 = 0, pParam2 = 0;
424	uint64_t valpar1, valpar2;
425
426	AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
427	switch(param1.type)
428	{
429	case PARMTYPE_IMMEDIATE: /* register type is translated to this one too */
430	valpar1 = param1.val.val64;
431	break;
432
433	case PARMTYPE_ADDRESS:
434	pParam1 = (RTGCPTR)param1.val.val64;
435	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
436	#ifdef IN_GC
437	/* Safety check (in theory it could cross a page boundary and fault there though) */
438	AssertReturn(pParam1 == pvFault, VERR_EM_INTERPRETER);
439	#endif
440	rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
441	if (VBOX_FAILURE(rc))
442	{
443	AssertMsgFailed(("MMGCRamRead %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
444	return VERR_EM_INTERPRETER;
445	}
446	break;
447
448	default:
449	AssertFailed();
450	return VERR_EM_INTERPRETER;
451	}
452
453	switch(param2.type)
454	{
455	case PARMTYPE_ADDRESS:
456	pParam2 = (RTGCPTR)param2.val.val64;
457	pParam2 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param2, pParam2);
458	#ifdef IN_GC
459	/* Safety check (in theory it could cross a page boundary and fault there though) */
460	AssertReturn(pParam2 == pvFault, VERR_EM_INTERPRETER);
461	#endif
462	rc = emRamRead(pVM, &valpar2, pParam2, param2.size);
463	if (VBOX_FAILURE(rc))
464	{
465	AssertMsgFailed(("MMGCRamRead %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
466	}
467	break;
468
469	case PARMTYPE_IMMEDIATE:
470	valpar2 = param2.val.val64;
471	break;
472
473	default:
474	AssertFailed();
475	return VERR_EM_INTERPRETER;
476	}
477
478	/* Write value of parameter 2 to parameter 1 (reg or memory address) */
479	if (pParam1 == 0)
480	{
481	Assert(param1.type == PARMTYPE_IMMEDIATE); /* register actually */
482	switch(param1.size)
483	{
484	case 1: //special case for AH etc
485	rc = DISWriteReg8(pRegFrame, pCpu->param1.base.reg_gen, (uint8_t )valpar2); break;
486	case 2: rc = DISWriteReg16(pRegFrame, pCpu->param1.base.reg_gen, (uint16_t)valpar2); break;
487	case 4: rc = DISWriteReg32(pRegFrame, pCpu->param1.base.reg_gen, (uint32_t)valpar2); break;
488	case 8: rc = DISWriteReg64(pRegFrame, pCpu->param1.base.reg_gen, valpar2); break;
489	default: AssertFailedReturn(VERR_EM_INTERPRETER);
490	}
491	if (VBOX_FAILURE(rc))
492	return VERR_EM_INTERPRETER;
493	}
494	else
495	{
496	rc = emRamWrite(pVM, pParam1, &valpar2, param1.size);
497	if (VBOX_FAILURE(rc))
498	{
499	AssertMsgFailed(("emRamWrite %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
500	return VERR_EM_INTERPRETER;
501	}
502	}
503
504	/* Write value of parameter 1 to parameter 2 (reg or memory address) */
505	if (pParam2 == 0)
506	{
507	Assert(param2.type == PARMTYPE_IMMEDIATE); /* register actually */
508	switch(param2.size)
509	{
510	case 1: //special case for AH etc
511	rc = DISWriteReg8(pRegFrame, pCpu->param2.base.reg_gen, (uint8_t )valpar1); break;
512	case 2: rc = DISWriteReg16(pRegFrame, pCpu->param2.base.reg_gen, (uint16_t)valpar1); break;
513	case 4: rc = DISWriteReg32(pRegFrame, pCpu->param2.base.reg_gen, (uint32_t)valpar1); break;
514	case 8: rc = DISWriteReg64(pRegFrame, pCpu->param2.base.reg_gen, valpar1); break;
515	default: AssertFailedReturn(VERR_EM_INTERPRETER);
516	}
517	if (VBOX_FAILURE(rc))
518	return VERR_EM_INTERPRETER;
519	}
520	else
521	{
522	rc = emRamWrite(pVM, pParam2, &valpar1, param2.size);
523	if (VBOX_FAILURE(rc))
524	{
525	AssertMsgFailed(("emRamWrite %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
526	return VERR_EM_INTERPRETER;
527	}
528	}
529
530	*pcbSize = param2.size;
531	return VINF_SUCCESS;
532	#ifdef IN_GC
533	}
534	}
535	#endif
536	return VERR_EM_INTERPRETER;
537	}
538
539	/**
540	* INC and DEC emulation.
541	*/
542	static int emInterpretIncDec(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
543	PFN_EMULATE_PARAM2 pfnEmulate)
544	{
545	OP_PARAMVAL param1;
546
547	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
548	if(VBOX_FAILURE(rc))
549	return VERR_EM_INTERPRETER;
550
551	#ifdef IN_GC
552	if (TRPMHasTrap(pVM))
553	{
554	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
555	{
556	#endif
557	RTGCPTR pParam1 = 0;
558	uint64_t valpar1;
559
560	if (param1.type == PARMTYPE_ADDRESS)
561	{
562	pParam1 = (RTGCPTR)param1.val.val64;
563	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
564	#ifdef IN_GC
565	/* Safety check (in theory it could cross a page boundary and fault there though) */
566	AssertReturn(pParam1 == pvFault, VERR_EM_INTERPRETER);
567	#endif
568	rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
569	if (VBOX_FAILURE(rc))
570	{
571	AssertMsgFailed(("emRamRead %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
572	return VERR_EM_INTERPRETER;
573	}
574	}
575	else
576	{
577	AssertFailed();
578	return VERR_EM_INTERPRETER;
579	}
580
581	uint32_t eflags;
582
583	eflags = pfnEmulate(&valpar1, param1.size);
584
585	/* Write result back */
586	rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
587	if (VBOX_FAILURE(rc))
588	{
589	AssertMsgFailed(("emRamWrite %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
590	return VERR_EM_INTERPRETER;
591	}
592
593	/* Update guest's eflags and finish. */
594	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
595	\| (eflags & (X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
596
597	/* All done! */
598	*pcbSize = param1.size;
599	return VINF_SUCCESS;
600	#ifdef IN_GC
601	}
602	}
603	#endif
604	return VERR_EM_INTERPRETER;
605	}
606
607	/**
608	* POP Emulation.
609	*/
610	static int emInterpretPop(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
611	{
612	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
613	OP_PARAMVAL param1;
614	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
615	if(VBOX_FAILURE(rc))
616	return VERR_EM_INTERPRETER;
617
618	#ifdef IN_GC
619	if (TRPMHasTrap(pVM))
620	{
621	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
622	{
623	#endif
624	RTGCPTR pParam1 = 0;
625	uint32_t valpar1;
626	RTGCPTR pStackVal;
627
628	/* Read stack value first */
629	if (SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->ss, &pRegFrame->ssHid) == CPUMODE_16BIT)
630	return VERR_EM_INTERPRETER; /* No legacy 16 bits stuff here, please. */
631
632	/* Convert address; don't bother checking limits etc, as we only read here */
633	pStackVal = SELMToFlat(pVM, DIS_SELREG_SS, pRegFrame, (RTGCPTR)pRegFrame->esp);
634	if (pStackVal == 0)
635	return VERR_EM_INTERPRETER;
636
637	rc = emRamRead(pVM, &valpar1, pStackVal, param1.size);
638	if (VBOX_FAILURE(rc))
639	{
640	AssertMsgFailed(("emRamRead %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
641	return VERR_EM_INTERPRETER;
642	}
643
644	if (param1.type == PARMTYPE_ADDRESS)
645	{
646	pParam1 = (RTGCPTR)param1.val.val64;
647
648	/* pop [esp+xx] uses esp after the actual pop! */
649	AssertCompile(USE_REG_ESP == USE_REG_SP);
650	if ( (pCpu->param1.flags & USE_BASE)
651	&& (pCpu->param1.flags & (USE_REG_GEN16\|USE_REG_GEN32))
652	&& pCpu->param1.base.reg_gen == USE_REG_ESP
653	)
654	pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + param1.size);
655
656	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
657
658	#ifdef IN_GC
659	/* Safety check (in theory it could cross a page boundary and fault there though) */
660	AssertMsgReturn(pParam1 == pvFault \|\| (RTGCPTR)pRegFrame->esp == pvFault, ("%VGv != %VGv ss:esp=%04X:%08x\n", pParam1, pvFault, pRegFrame->ss, pRegFrame->esp), VERR_EM_INTERPRETER);
661	#endif
662	rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
663	if (VBOX_FAILURE(rc))
664	{
665	AssertMsgFailed(("emRamWrite %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
666	return VERR_EM_INTERPRETER;
667	}
668
669	/* Update ESP as the last step */
670	pRegFrame->esp += param1.size;
671	}
672	else
673	{
674	#ifndef DEBUG_bird // annoying assertion.
675	AssertFailed();
676	#endif
677	return VERR_EM_INTERPRETER;
678	}
679
680	/* All done! */
681	*pcbSize = param1.size;
682	return VINF_SUCCESS;
683	#ifdef IN_GC
684	}
685	}
686	#endif
687	return VERR_EM_INTERPRETER;
688	}
689
690
691	/**
692	* XOR/OR/AND Emulation.
693	*/
694	static int emInterpretOrXorAnd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
695	PFN_EMULATE_PARAM3 pfnEmulate)
696	{
697	OP_PARAMVAL param1, param2;
698	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
699	if(VBOX_FAILURE(rc))
700	return VERR_EM_INTERPRETER;
701
702	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
703	if(VBOX_FAILURE(rc))
704	return VERR_EM_INTERPRETER;
705
706	#ifdef LOG_ENABLED
707	const char *pszInstr;
708
709	if (pCpu->pCurInstr->opcode == OP_XOR)
710	pszInstr = "Xor";
711	else if (pCpu->pCurInstr->opcode == OP_OR)
712	pszInstr = "Or";
713	else if (pCpu->pCurInstr->opcode == OP_AND)
714	pszInstr = "And";
715	else
716	pszInstr = "OrXorAnd??";
717	#endif
718
719	#ifdef IN_GC
720	if (TRPMHasTrap(pVM))
721	{
722	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
723	{
724	#endif
725	RTGCPTR pParam1;
726	uint64_t valpar1, valpar2;
727
728	if (pCpu->param1.size != pCpu->param2.size)
729	{
730	if (pCpu->param1.size < pCpu->param2.size)
731	{
732	AssertMsgFailed(("%s at %VGv parameter mismatch %d vs %d!!\n", pszInstr, pRegFrame->rip, pCpu->param1.size, pCpu->param2.size)); /* should never happen! */
733	return VERR_EM_INTERPRETER;
734	}
735	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
736	pCpu->param2.size = pCpu->param1.size;
737	param2.size = param1.size;
738	}
739
740	/* The destination is always a virtual address */
741	if (param1.type == PARMTYPE_ADDRESS)
742	{
743	pParam1 = (RTGCPTR)param1.val.val64;
744	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
745
746	#ifdef IN_GC
747	/* Safety check (in theory it could cross a page boundary and fault there though) */
748	AssertMsgReturn(pParam1 == pvFault, ("eip=%VGv, pParam1=%VGv pvFault=%VGv\n", pRegFrame->rip, pParam1, pvFault), VERR_EM_INTERPRETER);
749	#endif
750	rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
751	if (VBOX_FAILURE(rc))
752	{
753	AssertMsgFailed(("emRamRead %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
754	return VERR_EM_INTERPRETER;
755	}
756	}
757	else
758	{
759	AssertFailed();
760	return VERR_EM_INTERPRETER;
761	}
762
763	/* Register or immediate data */
764	switch(param2.type)
765	{
766	case PARMTYPE_IMMEDIATE: /* both immediate data and register (ugly) */
767	valpar2 = param2.val.val64;
768	break;
769
770	default:
771	AssertFailed();
772	return VERR_EM_INTERPRETER;
773	}
774
775	LogFlow(("emInterpretOrXorAnd %s %VGv %RX64 - %RX64 size %d (%d)\n", pszInstr, pParam1, valpar1, valpar2, param2.size, param1.size));
776
777	/* Data read, emulate instruction. */
778	uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
779
780	LogFlow(("emInterpretOrXorAnd %s result %RX64\n", pszInstr, valpar1));
781
782	/* Update guest's eflags and finish. */
783	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
784	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
785
786	/* And write it back */
787	rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
788	if (VBOX_SUCCESS(rc))
789	{
790	/* All done! */
791	*pcbSize = param2.size;
792	return VINF_SUCCESS;
793	}
794	#ifdef IN_GC
795	}
796	}
797	#endif
798	return VERR_EM_INTERPRETER;
799	}
800
801	/**
802	* LOCK XOR/OR/AND Emulation.
803	*/
804	static int emInterpretLockOrXorAnd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
805	uint32_t *pcbSize, PFNEMULATELOCKPARAM3 pfnEmulate)
806	{
807	void *pvParam1;
808
809	OP_PARAMVAL param1, param2;
810	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
811	if(VBOX_FAILURE(rc))
812	return VERR_EM_INTERPRETER;
813
814	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
815	if(VBOX_FAILURE(rc))
816	return VERR_EM_INTERPRETER;
817
818	if (pCpu->param1.size != pCpu->param2.size)
819	{
820	AssertMsgReturn(pCpu->param1.size >= pCpu->param2.size, /* should never happen! */
821	("%s at %VGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pCpu), pRegFrame->rip, pCpu->param1.size, pCpu->param2.size),
822	VERR_EM_INTERPRETER);
823
824	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
825	pCpu->param2.size = pCpu->param1.size;
826	param2.size = param1.size;
827	}
828
829	/* The destination is always a virtual address */
830	AssertReturn(param1.type == PARMTYPE_ADDRESS, VERR_EM_INTERPRETER);
831
832	RTGCPTR GCPtrPar1 = param1.val.val64;
833	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
834	#ifdef IN_GC
835	pvParam1 = (void *)GCPtrPar1;
836	#else
837	rc = PGMPhysGCPtr2HCPtr(pVM, GCPtrPar1, &pvParam1);
838	if (VBOX_FAILURE(rc))
839	{
840	AssertRC(rc);
841	return VERR_EM_INTERPRETER;
842	}
843	#endif
844
845	# ifdef IN_GC
846	/* Safety check (in theory it could cross a page boundary and fault there though) */
847	Assert( TRPMHasTrap(pVM)
848	&& (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW));
849	AssertMsgReturn(GCPtrPar1 == pvFault, ("eip=%VGv, GCPtrPar1=%VGv pvFault=%VGv\n", pRegFrame->rip, GCPtrPar1, pvFault), VERR_EM_INTERPRETER);
850	# endif
851
852	/* Register and immediate data == PARMTYPE_IMMEDIATE */
853	AssertReturn(param2.type == PARMTYPE_IMMEDIATE, VERR_EM_INTERPRETER);
854	RTGCUINTREG ValPar2 = param2.val.val64;
855
856	/* Try emulate it with a one-shot #PF handler in place. */
857	Log2(("%s %VGv imm%d=%RX64\n", emGetMnemonic(pCpu), GCPtrPar1, pCpu->param2.size*8, ValPar2));
858
859	RTGCUINTREG32 eflags = 0;
860	#ifdef IN_GC
861	MMGCRamRegisterTrapHandler(pVM);
862	#endif
863	rc = pfnEmulate(pvParam1, ValPar2, pCpu->param2.size, &eflags);
864	#ifdef IN_GC
865	MMGCRamDeregisterTrapHandler(pVM);
866	#endif
867	if (RT_FAILURE(rc))
868	{
869	Log(("%s %VGv imm%d=%RX64-> emulation failed due to page fault!\n", emGetMnemonic(pCpu), GCPtrPar1, pCpu->param2.size*8, ValPar2));
870	return VERR_EM_INTERPRETER;
871	}
872
873	/* Update guest's eflags and finish. */
874	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
875	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
876
877	*pcbSize = param2.size;
878	return VINF_SUCCESS;
879	}
880
881	/**
882	* ADD, ADC & SUB Emulation.
883	*/
884	static int emInterpretAddSub(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
885	PFN_EMULATE_PARAM3 pfnEmulate)
886	{
887	OP_PARAMVAL param1, param2;
888	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
889	if(VBOX_FAILURE(rc))
890	return VERR_EM_INTERPRETER;
891
892	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
893	if(VBOX_FAILURE(rc))
894	return VERR_EM_INTERPRETER;
895
896	#ifdef LOG_ENABLED
897	const char *pszInstr;
898
899	if (pCpu->pCurInstr->opcode == OP_SUB)
900	pszInstr = "Sub";
901	else if (pCpu->pCurInstr->opcode == OP_ADD)
902	pszInstr = "Add";
903	else if (pCpu->pCurInstr->opcode == OP_ADC)
904	pszInstr = "Adc";
905	else
906	pszInstr = "AddSub??";
907	#endif
908
909	#ifdef IN_GC
910	if (TRPMHasTrap(pVM))
911	{
912	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
913	{
914	#endif
915	RTGCPTR pParam1;
916	uint64_t valpar1, valpar2;
917
918	if (pCpu->param1.size != pCpu->param2.size)
919	{
920	if (pCpu->param1.size < pCpu->param2.size)
921	{
922	AssertMsgFailed(("%s at %VGv parameter mismatch %d vs %d!!\n", pszInstr, pRegFrame->rip, pCpu->param1.size, pCpu->param2.size)); /* should never happen! */
923	return VERR_EM_INTERPRETER;
924	}
925	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
926	pCpu->param2.size = pCpu->param1.size;
927	param2.size = param1.size;
928	}
929
930	/* The destination is always a virtual address */
931	if (param1.type == PARMTYPE_ADDRESS)
932	{
933	pParam1 = (RTGCPTR)param1.val.val64;
934	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
935
936	#ifdef IN_GC
937	/* Safety check (in theory it could cross a page boundary and fault there though) */
938	AssertReturn(pParam1 == pvFault, VERR_EM_INTERPRETER);
939	#endif
940	rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
941	if (VBOX_FAILURE(rc))
942	{
943	AssertMsgFailed(("emRamRead %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
944	return VERR_EM_INTERPRETER;
945	}
946	}
947	else
948	{
949	#ifndef DEBUG_bird
950	AssertFailed();
951	#endif
952	return VERR_EM_INTERPRETER;
953	}
954
955	/* Register or immediate data */
956	switch(param2.type)
957	{
958	case PARMTYPE_IMMEDIATE: /* both immediate data and register (ugly) */
959	valpar2 = param2.val.val64;
960	break;
961
962	default:
963	AssertFailed();
964	return VERR_EM_INTERPRETER;
965	}
966
967	/* Data read, emulate instruction. */
968	uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
969
970	/* Update guest's eflags and finish. */
971	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
972	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
973
974	/* And write it back */
975	rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
976	if (VBOX_SUCCESS(rc))
977	{
978	/* All done! */
979	*pcbSize = param2.size;
980	return VINF_SUCCESS;
981	}
982	#ifdef IN_GC
983	}
984	}
985	#endif
986	return VERR_EM_INTERPRETER;
987	}
988
989	/**
990	* ADC Emulation.
991	*/
992	static int emInterpretAdc(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
993	{
994	if (pRegFrame->eflags.Bits.u1CF)
995	return emInterpretAddSub(pVM, pCpu, pRegFrame, pvFault, pcbSize, EMEmulateAdcWithCarrySet);
996	else
997	return emInterpretAddSub(pVM, pCpu, pRegFrame, pvFault, pcbSize, EMEmulateAdd);
998	}
999
1000	/**
1001	* BTR/C/S Emulation.
1002	*/
1003	static int emInterpretBitTest(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
1004	PFN_EMULATE_PARAM2_UINT32 pfnEmulate)
1005	{
1006	OP_PARAMVAL param1, param2;
1007	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
1008	if(VBOX_FAILURE(rc))
1009	return VERR_EM_INTERPRETER;
1010
1011	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1012	if(VBOX_FAILURE(rc))
1013	return VERR_EM_INTERPRETER;
1014
1015	#ifdef LOG_ENABLED
1016	const char *pszInstr;
1017
1018	if (pCpu->pCurInstr->opcode == OP_BTR)
1019	pszInstr = "Btr";
1020	else if (pCpu->pCurInstr->opcode == OP_BTS)
1021	pszInstr = "Bts";
1022	else if (pCpu->pCurInstr->opcode == OP_BTC)
1023	pszInstr = "Btc";
1024	else
1025	pszInstr = "Bit??";
1026	#endif
1027
1028	#ifdef IN_GC
1029	if (TRPMHasTrap(pVM))
1030	{
1031	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1032	{
1033	#endif
1034	RTGCPTR pParam1;
1035	uint64_t valpar1 = 0, valpar2;
1036	uint32_t eflags;
1037
1038	/* The destination is always a virtual address */
1039	if (param1.type != PARMTYPE_ADDRESS)
1040	return VERR_EM_INTERPRETER;
1041
1042	pParam1 = (RTGCPTR)param1.val.val64;
1043	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
1044
1045	/* Register or immediate data */
1046	switch(param2.type)
1047	{
1048	case PARMTYPE_IMMEDIATE: /* both immediate data and register (ugly) */
1049	valpar2 = param2.val.val64;
1050	break;
1051
1052	default:
1053	AssertFailed();
1054	return VERR_EM_INTERPRETER;
1055	}
1056
1057	Log2(("emInterpret%s: pvFault=%VGv pParam1=%VGv val2=%x\n", pszInstr, pvFault, pParam1, valpar2));
1058	pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + valpar2/8);
1059	#ifdef IN_GC
1060	/* Safety check. */
1061	AssertMsgReturn((RTGCPTR)((RTGCUINTPTR)pParam1 & ~3) == pvFault, ("pParam1=%VGv pvFault=%VGv\n", pParam1, pvFault), VERR_EM_INTERPRETER);
1062	#endif
1063	rc = emRamRead(pVM, &valpar1, pParam1, 1);
1064	if (VBOX_FAILURE(rc))
1065	{
1066	AssertMsgFailed(("emRamRead %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
1067	return VERR_EM_INTERPRETER;
1068	}
1069
1070	Log2(("emInterpretBtx: val=%x\n", valpar1));
1071	/* Data read, emulate bit test instruction. */
1072	eflags = pfnEmulate(&valpar1, valpar2 & 0x7);
1073
1074	Log2(("emInterpretBtx: val=%x CF=%d\n", valpar1, !!(eflags & X86_EFL_CF)));
1075
1076	/* Update guest's eflags and finish. */
1077	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1078	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1079
1080	/* And write it back */
1081	rc = emRamWrite(pVM, pParam1, &valpar1, 1);
1082	if (VBOX_SUCCESS(rc))
1083	{
1084	/* All done! */
1085	*pcbSize = 1;
1086	return VINF_SUCCESS;
1087	}
1088	#ifdef IN_GC
1089	}
1090	}
1091	#endif
1092	return VERR_EM_INTERPRETER;
1093	}
1094
1095	/**
1096	* LOCK BTR/C/S Emulation.
1097	*/
1098	static int emInterpretLockBitTest(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
1099	uint32_t *pcbSize, PFNEMULATELOCKPARAM2 pfnEmulate)
1100	{
1101	void *pvParam1;
1102
1103	OP_PARAMVAL param1, param2;
1104	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
1105	if(VBOX_FAILURE(rc))
1106	return VERR_EM_INTERPRETER;
1107
1108	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1109	if(VBOX_FAILURE(rc))
1110	return VERR_EM_INTERPRETER;
1111
1112	/* The destination is always a virtual address */
1113	if (param1.type != PARMTYPE_ADDRESS)
1114	return VERR_EM_INTERPRETER;
1115
1116	/* Register and immediate data == PARMTYPE_IMMEDIATE */
1117	AssertReturn(param2.type == PARMTYPE_IMMEDIATE, VERR_EM_INTERPRETER);
1118	uint64_t ValPar2 = param2.val.val64;
1119
1120	/* Adjust the parameters so what we're dealing with is a bit within the byte pointed to. */
1121	RTGCPTR GCPtrPar1 = param1.val.val64;
1122	GCPtrPar1 = (GCPtrPar1 + ValPar2 / 8);
1123	ValPar2 &= 7;
1124
1125	#ifdef IN_GC
1126	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
1127	pvParam1 = (void *)GCPtrPar1;
1128	#else
1129	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
1130	rc = PGMPhysGCPtr2HCPtr(pVM, GCPtrPar1, &pvParam1);
1131	if (VBOX_FAILURE(rc))
1132	{
1133	AssertRC(rc);
1134	return VERR_EM_INTERPRETER;
1135	}
1136	#endif
1137
1138	Log2(("emInterpretLockBitTest %s: pvFault=%VGv GCPtrPar1=%VGv imm=%RX64\n", emGetMnemonic(pCpu), pvFault, GCPtrPar1, ValPar2));
1139
1140	#ifdef IN_GC
1141	Assert(TRPMHasTrap(pVM));
1142	AssertMsgReturn((RTGCPTR)((RTGCUINTPTR)GCPtrPar1 & ~(RTGCUINTPTR)3) == pvFault,
1143	("GCPtrPar1=%VGv pvFault=%VGv\n", GCPtrPar1, pvFault),
1144	VERR_EM_INTERPRETER);
1145	#endif
1146
1147	/* Try emulate it with a one-shot #PF handler in place. */
1148	RTGCUINTREG32 eflags = 0;
1149	#ifdef IN_GC
1150	MMGCRamRegisterTrapHandler(pVM);
1151	#endif
1152	rc = pfnEmulate(pvParam1, ValPar2, &eflags);
1153	#ifdef IN_GC
1154	MMGCRamDeregisterTrapHandler(pVM);
1155	#endif
1156	if (RT_FAILURE(rc))
1157	{
1158	Log(("emInterpretLockBitTest %s: %VGv imm%d=%RX64 -> emulation failed due to page fault!\n",
1159	emGetMnemonic(pCpu), GCPtrPar1, pCpu->param2.size*8, ValPar2));
1160	return VERR_EM_INTERPRETER;
1161	}
1162
1163	Log2(("emInterpretLockBitTest %s: GCPtrPar1=%VGv imm=%VX64 CF=%d\n", emGetMnemonic(pCpu), GCPtrPar1, ValPar2, !!(eflags & X86_EFL_CF)));
1164
1165	/* Update guest's eflags and finish. */
1166	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1167	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1168
1169	*pcbSize = 1;
1170	return VINF_SUCCESS;
1171	}
1172
1173	/**
1174	* MOV emulation.
1175	*/
1176	static int emInterpretMov(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1177	{
1178	OP_PARAMVAL param1, param2;
1179	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
1180	if(VBOX_FAILURE(rc))
1181	return VERR_EM_INTERPRETER;
1182
1183	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1184	if(VBOX_FAILURE(rc))
1185	return VERR_EM_INTERPRETER;
1186
1187	#ifdef IN_GC
1188	if (TRPMHasTrap(pVM))
1189	{
1190	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1191	{
1192	#else
1193	/** @todo Make this the default and don't rely on TRPM information. */
1194	if (param1.type == PARMTYPE_ADDRESS)
1195	{
1196	#endif
1197	RTGCPTR pDest;
1198	uint64_t val64;
1199
1200	switch(param1.type)
1201	{
1202	case PARMTYPE_IMMEDIATE:
1203	if(!(param1.flags & (PARAM_VAL32\|PARAM_VAL64)))
1204	return VERR_EM_INTERPRETER;
1205	/* fallthru */
1206
1207	case PARMTYPE_ADDRESS:
1208	pDest = (RTGCPTR)param1.val.val64;
1209	pDest = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pDest);
1210	break;
1211
1212	default:
1213	AssertFailed();
1214	return VERR_EM_INTERPRETER;
1215	}
1216
1217	switch(param2.type)
1218	{
1219	case PARMTYPE_IMMEDIATE: /* register type is translated to this one too */
1220	val64 = param2.val.val64;
1221	break;
1222
1223	default:
1224	Log(("emInterpretMov: unexpected type=%d eip=%VGv\n", param2.type, pRegFrame->rip));
1225	return VERR_EM_INTERPRETER;
1226	}
1227	#ifdef LOG_ENABLED
1228	if (pCpu->mode == CPUMODE_64BIT)
1229	LogFlow(("EMInterpretInstruction at %VGv: OP_MOV %VGv <- %RX64 (%d) &val32=%VHv\n", pRegFrame->rip, pDest, val64, param2.size, &val64));
1230	else
1231	LogFlow(("EMInterpretInstruction at %VGv: OP_MOV %VGv <- %08X (%d) &val32=%VHv\n", pRegFrame->rip, pDest, (uint32_t)val64, param2.size, &val64));
1232	#endif
1233
1234	Assert(param2.size <= 8 && param2.size > 0);
1235
1236	#if 0 /* CSAM/PATM translates aliases which causes this to incorrectly trigger. See #2609 and #1498. */
1237	#ifdef IN_GC
1238	/* Safety check (in theory it could cross a page boundary and fault there though) */
1239	AssertMsgReturn(pDest == pvFault, ("eip=%VGv pDest=%VGv pvFault=%VGv\n", pRegFrame->rip, pDest, pvFault), VERR_EM_INTERPRETER);
1240	#endif
1241	#endif
1242	rc = emRamWrite(pVM, pDest, &val64, param2.size);
1243	if (VBOX_FAILURE(rc))
1244	return VERR_EM_INTERPRETER;
1245
1246	*pcbSize = param2.size;
1247	}
1248	else
1249	{ /* read fault */
1250	RTGCPTR pSrc;
1251	uint64_t val64;
1252
1253	/* Source */
1254	switch(param2.type)
1255	{
1256	case PARMTYPE_IMMEDIATE:
1257	if(!(param2.flags & (PARAM_VAL32\|PARAM_VAL64)))
1258	return VERR_EM_INTERPRETER;
1259	/* fallthru */
1260
1261	case PARMTYPE_ADDRESS:
1262	pSrc = (RTGCPTR)param2.val.val64;
1263	pSrc = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param2, pSrc);
1264	break;
1265
1266	default:
1267	return VERR_EM_INTERPRETER;
1268	}
1269
1270	Assert(param1.size <= 8 && param1.size > 0);
1271	#ifdef IN_GC
1272	/* Safety check (in theory it could cross a page boundary and fault there though) */
1273	AssertReturn(pSrc == pvFault, VERR_EM_INTERPRETER);
1274	#endif
1275	rc = emRamRead(pVM, &val64, pSrc, param1.size);
1276	if (VBOX_FAILURE(rc))
1277	return VERR_EM_INTERPRETER;
1278
1279	/* Destination */
1280	switch(param1.type)
1281	{
1282	case PARMTYPE_REGISTER:
1283	switch(param1.size)
1284	{
1285	case 1: rc = DISWriteReg8(pRegFrame, pCpu->param1.base.reg_gen, (uint8_t) val64); break;
1286	case 2: rc = DISWriteReg16(pRegFrame, pCpu->param1.base.reg_gen, (uint16_t)val64); break;
1287	case 4: rc = DISWriteReg32(pRegFrame, pCpu->param1.base.reg_gen, (uint32_t)val64); break;
1288	case 8: rc = DISWriteReg64(pRegFrame, pCpu->param1.base.reg_gen, val64); break;
1289	default:
1290	return VERR_EM_INTERPRETER;
1291	}
1292	if (VBOX_FAILURE(rc))
1293	return rc;
1294	break;
1295
1296	default:
1297	return VERR_EM_INTERPRETER;
1298	}
1299	#ifdef LOG_ENABLED
1300	if (pCpu->mode == CPUMODE_64BIT)
1301	LogFlow(("EMInterpretInstruction: OP_MOV %VGv -> %RX64 (%d)\n", pSrc, val64, param1.size));
1302	else
1303	LogFlow(("EMInterpretInstruction: OP_MOV %VGv -> %08X (%d)\n", pSrc, (uint32_t)val64, param1.size));
1304	#endif
1305	}
1306	return VINF_SUCCESS;
1307	#ifdef IN_GC
1308	}
1309	#endif
1310	return VERR_EM_INTERPRETER;
1311	}
1312
1313	#ifndef IN_GC
1314	/*
1315	* [REP] STOSWD emulation
1316	*
1317	*/
1318	static int emInterpretStosWD(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1319	{
1320	int rc;
1321	RTGCPTR GCDest, GCOffset;
1322	uint32_t cbSize;
1323	uint64_t cTransfers;
1324	int offIncrement;
1325
1326	/* Don't support any but these three prefix bytes. */
1327	if ((pCpu->prefix & ~(PREFIX_ADDRSIZE\|PREFIX_OPSIZE\|PREFIX_REP\|PREFIX_REX)))
1328	return VERR_EM_INTERPRETER;
1329
1330	switch (pCpu->addrmode)
1331	{
1332	case CPUMODE_16BIT:
1333	GCOffset = pRegFrame->di;
1334	cTransfers = pRegFrame->cx;
1335	break;
1336	case CPUMODE_32BIT:
1337	GCOffset = pRegFrame->edi;
1338	cTransfers = pRegFrame->ecx;
1339	break;
1340	case CPUMODE_64BIT:
1341	GCOffset = pRegFrame->rdi;
1342	cTransfers = pRegFrame->rcx;
1343	break;
1344	default:
1345	AssertFailed();
1346	return VERR_EM_INTERPRETER;
1347	}
1348
1349	GCDest = SELMToFlat(pVM, DIS_SELREG_ES, pRegFrame, GCOffset);
1350	switch (pCpu->opmode)
1351	{
1352	case CPUMODE_16BIT:
1353	cbSize = 2;
1354	break;
1355	case CPUMODE_32BIT:
1356	cbSize = 4;
1357	break;
1358	case CPUMODE_64BIT:
1359	cbSize = 8;
1360	break;
1361	default:
1362	AssertFailed();
1363	return VERR_EM_INTERPRETER;
1364	}
1365
1366	offIncrement = pRegFrame->eflags.Bits.u1DF ? -(signed)cbSize : (signed)cbSize;
1367
1368	if (!(pCpu->prefix & PREFIX_REP))
1369	{
1370	LogFlow(("emInterpretStosWD dest=%04X:%VGv (%VGv) cbSize=%d\n", pRegFrame->es, GCOffset, GCDest, cbSize));
1371
1372	rc = PGMPhysWriteGCPtrSafe(pVM, GCDest, &pRegFrame->rax, cbSize);
1373	if (VBOX_FAILURE(rc))
1374	return VERR_EM_INTERPRETER;
1375	Assert(rc == VINF_SUCCESS);
1376
1377	/* Update (e/r)di. */
1378	switch (pCpu->addrmode)
1379	{
1380	case CPUMODE_16BIT:
1381	pRegFrame->di += offIncrement;
1382	break;
1383	case CPUMODE_32BIT:
1384	pRegFrame->edi += offIncrement;
1385	break;
1386	case CPUMODE_64BIT:
1387	pRegFrame->rdi += offIncrement;
1388	break;
1389	default:
1390	AssertFailed();
1391	return VERR_EM_INTERPRETER;
1392	}
1393
1394	}
1395	else
1396	{
1397	if (!cTransfers)
1398	return VINF_SUCCESS;
1399
1400	LogFlow(("emInterpretStosWD dest=%04X:%VGv (%VGv) cbSize=%d cTransfers=%x DF=%d\n", pRegFrame->es, GCOffset, GCDest, cbSize, cTransfers, pRegFrame->eflags.Bits.u1DF));
1401
1402	/* Access verification first; we currently can't recover properly from traps inside this instruction */
1403	rc = PGMVerifyAccess(pVM, GCDest - (offIncrement > 0) ? 0 : ((cTransfers-1) * cbSize), cTransfers * cbSize, X86_PTE_RW \| X86_PTE_US);
1404	if (rc != VINF_SUCCESS)
1405	{
1406	Log(("STOSWD will generate a trap -> recompiler, rc=%d\n", rc));
1407	return VERR_EM_INTERPRETER;
1408	}
1409
1410	/* REP case */
1411	while (cTransfers)
1412	{
1413	rc = PGMPhysWriteGCPtrSafe(pVM, GCDest, &pRegFrame->rax, cbSize);
1414	if (VBOX_FAILURE(rc))
1415	{
1416	rc = VERR_EM_INTERPRETER;
1417	break;
1418	}
1419
1420	Assert(rc == VINF_SUCCESS);
1421	GCOffset += offIncrement;
1422	GCDest += offIncrement;
1423	cTransfers--;
1424	}
1425
1426	/* Update the registers. */
1427	switch (pCpu->addrmode)
1428	{
1429	case CPUMODE_16BIT:
1430	pRegFrame->di = GCOffset;
1431	pRegFrame->cx = cTransfers;
1432	break;
1433	case CPUMODE_32BIT:
1434	pRegFrame->edi = GCOffset;
1435	pRegFrame->ecx = cTransfers;
1436	break;
1437	case CPUMODE_64BIT:
1438	pRegFrame->rdi = GCOffset;
1439	pRegFrame->rcx = cTransfers;
1440	break;
1441	default:
1442	AssertFailed();
1443	return VERR_EM_INTERPRETER;
1444	}
1445	}
1446
1447	*pcbSize = cbSize;
1448	return rc;
1449	}
1450	#endif
1451
1452
1453	/*
1454	* [LOCK] CMPXCHG emulation.
1455	*/
1456	#ifndef IN_GC
1457	static int emInterpretCmpXchg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1458	{
1459	OP_PARAMVAL param1, param2;
1460
1461	#ifdef LOG_ENABLED
1462	const char *pszInstr;
1463
1464	if (pCpu->prefix & PREFIX_LOCK)
1465	pszInstr = "Lock CmpXchg";
1466	else
1467	pszInstr = "CmpXchg";
1468	#endif
1469
1470	/* Source to make DISQueryParamVal read the register value - ugly hack */
1471	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1472	if(VBOX_FAILURE(rc))
1473	return VERR_EM_INTERPRETER;
1474
1475	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1476	if(VBOX_FAILURE(rc))
1477	return VERR_EM_INTERPRETER;
1478
1479	RTGCPTR GCPtrPar1;
1480	void *pvParam1;
1481	uint64_t valpar, eflags;
1482
1483	AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
1484	switch(param1.type)
1485	{
1486	case PARMTYPE_ADDRESS:
1487	GCPtrPar1 = param1.val.val64;
1488	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
1489
1490	rc = PGMPhysGCPtr2HCPtr(pVM, GCPtrPar1, &pvParam1);
1491	if (VBOX_FAILURE(rc))
1492	{
1493	AssertRC(rc);
1494	return VERR_EM_INTERPRETER;
1495	}
1496	break;
1497
1498	default:
1499	return VERR_EM_INTERPRETER;
1500	}
1501
1502	switch(param2.type)
1503	{
1504	case PARMTYPE_IMMEDIATE: /* register actually */
1505	valpar = param2.val.val64;
1506	break;
1507
1508	default:
1509	return VERR_EM_INTERPRETER;
1510	}
1511
1512	LogFlow(("%s %VGv rax=%RX64 %RX64\n", pszInstr, GCPtrPar1, pRegFrame->rax, valpar));
1513
1514	if (pCpu->prefix & PREFIX_LOCK)
1515	eflags = EMEmulateLockCmpXchg(pvParam1, &pRegFrame->rax, valpar, pCpu->param2.size);
1516	else
1517	eflags = EMEmulateCmpXchg(pvParam1, &pRegFrame->rax, valpar, pCpu->param2.size);
1518
1519	LogFlow(("%s %VGv rax=%RX64 %RX64 ZF=%d\n", pszInstr, GCPtrPar1, pRegFrame->rax, valpar, !!(eflags & X86_EFL_ZF)));
1520
1521	/* Update guest's eflags and finish. */
1522	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1523	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1524
1525	*pcbSize = param2.size;
1526	return VINF_SUCCESS;
1527	}
1528
1529	#else
1530	static int emInterpretCmpXchg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1531	{
1532	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
1533	OP_PARAMVAL param1, param2;
1534
1535	#ifdef LOG_ENABLED
1536	const char *pszInstr;
1537
1538	if (pCpu->prefix & PREFIX_LOCK)
1539	pszInstr = "Lock CmpXchg";
1540	else
1541	pszInstr = "CmpXchg";
1542	#endif
1543
1544	/* Source to make DISQueryParamVal read the register value - ugly hack */
1545	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1546	if(VBOX_FAILURE(rc))
1547	return VERR_EM_INTERPRETER;
1548
1549	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1550	if(VBOX_FAILURE(rc))
1551	return VERR_EM_INTERPRETER;
1552
1553	if (TRPMHasTrap(pVM))
1554	{
1555	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1556	{
1557	RTRCPTR pParam1;
1558	uint32_t valpar, eflags;
1559
1560	AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
1561	switch(param1.type)
1562	{
1563	case PARMTYPE_ADDRESS:
1564	pParam1 = (RTRCPTR)param1.val.val64;
1565	pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);
1566
1567	/* Safety check (in theory it could cross a page boundary and fault there though) */
1568	AssertMsgReturn(pParam1 == (RTRCPTR)pvFault, ("eip=%VGv pParam1=%VRv pvFault=%VGv\n", pRegFrame->rip, pParam1, pvFault), VERR_EM_INTERPRETER);
1569	break;
1570
1571	default:
1572	return VERR_EM_INTERPRETER;
1573	}
1574
1575	switch(param2.type)
1576	{
1577	case PARMTYPE_IMMEDIATE: /* register actually */
1578	valpar = param2.val.val32;
1579	break;
1580
1581	default:
1582	return VERR_EM_INTERPRETER;
1583	}
1584
1585	LogFlow(("%s %VRv eax=%08x %08x\n", pszInstr, pParam1, pRegFrame->eax, valpar));
1586
1587	MMGCRamRegisterTrapHandler(pVM);
1588	if (pCpu->prefix & PREFIX_LOCK)
1589	rc = EMGCEmulateLockCmpXchg(pParam1, &pRegFrame->eax, valpar, pCpu->param2.size, &eflags);
1590	else
1591	rc = EMGCEmulateCmpXchg(pParam1, &pRegFrame->eax, valpar, pCpu->param2.size, &eflags);
1592	MMGCRamDeregisterTrapHandler(pVM);
1593
1594	if (VBOX_FAILURE(rc))
1595	{
1596	Log(("%s %VGv eax=%08x %08x -> emulation failed due to page fault!\n", pszInstr, pParam1, pRegFrame->eax, valpar));
1597	return VERR_EM_INTERPRETER;
1598	}
1599
1600	LogFlow(("%s %VRv eax=%08x %08x ZF=%d\n", pszInstr, pParam1, pRegFrame->eax, valpar, !!(eflags & X86_EFL_ZF)));
1601
1602	/* Update guest's eflags and finish. */
1603	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1604	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1605
1606	*pcbSize = param2.size;
1607	return VINF_SUCCESS;
1608	}
1609	}
1610	return VERR_EM_INTERPRETER;
1611	}
1612
1613	/*
1614	* [LOCK] CMPXCHG8B emulation.
1615	*/
1616	static int emInterpretCmpXchg8b(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1617	{
1618	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
1619	OP_PARAMVAL param1;
1620
1621	#ifdef LOG_ENABLED
1622	const char *pszInstr;
1623
1624	if (pCpu->prefix & PREFIX_LOCK)
1625	pszInstr = "Lock CmpXchg8b";
1626	else
1627	pszInstr = "CmpXchg8b";
1628	#endif
1629
1630	/* Source to make DISQueryParamVal read the register value - ugly hack */
1631	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1632	if(VBOX_FAILURE(rc))
1633	return VERR_EM_INTERPRETER;
1634
1635	if (TRPMHasTrap(pVM))
1636	{
1637	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1638	{
1639	RTRCPTR pParam1;
1640	uint32_t eflags;
1641
1642	AssertReturn(pCpu->param1.size == 8, VERR_EM_INTERPRETER);
1643	switch(param1.type)
1644	{
1645	case PARMTYPE_ADDRESS:
1646	pParam1 = (RTRCPTR)param1.val.val64;
1647	pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);
1648
1649	/* Safety check (in theory it could cross a page boundary and fault there though) */
1650	AssertMsgReturn(pParam1 == (RTRCPTR)pvFault, ("eip=%VGv pParam1=%VRv pvFault=%VGv\n", pRegFrame->rip, pParam1, pvFault), VERR_EM_INTERPRETER);
1651	break;
1652
1653	default:
1654	return VERR_EM_INTERPRETER;
1655	}
1656
1657	LogFlow(("%s %VRv=%08x eax=%08x\n", pszInstr, pParam1, pRegFrame->eax));
1658
1659	MMGCRamRegisterTrapHandler(pVM);
1660	if (pCpu->prefix & PREFIX_LOCK)
1661	rc = EMGCEmulateLockCmpXchg8b(pParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx, &eflags);
1662	else
1663	rc = EMGCEmulateCmpXchg8b(pParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx, &eflags);
1664	MMGCRamDeregisterTrapHandler(pVM);
1665
1666	if (VBOX_FAILURE(rc))
1667	{
1668	Log(("%s %VGv=%08x eax=%08x -> emulation failed due to page fault!\n", pszInstr, pParam1, pRegFrame->eax));
1669	return VERR_EM_INTERPRETER;
1670	}
1671
1672	LogFlow(("%s %VGv=%08x eax=%08x ZF=%d\n", pszInstr, pParam1, pRegFrame->eax, !!(eflags & X86_EFL_ZF)));
1673
1674	/* Update guest's eflags and finish; note that only ZF is affected. */
1675	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_ZF))
1676	\| (eflags & (X86_EFL_ZF));
1677
1678	*pcbSize = 8;
1679	return VINF_SUCCESS;
1680	}
1681	}
1682	return VERR_EM_INTERPRETER;
1683	}
1684	#endif
1685
1686	/*
1687	* [LOCK] XADD emulation.
1688	*/
1689	#ifdef IN_GC
1690	static int emInterpretXAdd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1691	{
1692	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
1693	OP_PARAMVAL param1;
1694	uint32_t *pParamReg2;
1695	size_t cbSizeParamReg2;
1696
1697	/* Source to make DISQueryParamVal read the register value - ugly hack */
1698	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1699	if(VBOX_FAILURE(rc))
1700	return VERR_EM_INTERPRETER;
1701
1702	rc = DISQueryParamRegPtr(pRegFrame, pCpu, &pCpu->param2, (void **)&pParamReg2, &cbSizeParamReg2);
1703	Assert(cbSizeParamReg2 <= 4);
1704	if(VBOX_FAILURE(rc))
1705	return VERR_EM_INTERPRETER;
1706
1707	if (TRPMHasTrap(pVM))
1708	{
1709	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1710	{
1711	RTRCPTR pParam1;
1712	uint32_t eflags;
1713
1714	AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
1715	switch(param1.type)
1716	{
1717	case PARMTYPE_ADDRESS:
1718	pParam1 = (RTRCPTR)param1.val.val64;
1719	pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);
1720
1721	/* Safety check (in theory it could cross a page boundary and fault there though) */
1722	AssertMsgReturn(pParam1 == (RTRCPTR)pvFault, ("eip=%VGv pParam1=%VRv pvFault=%VGv\n", pRegFrame->rip, pParam1, pvFault), VERR_EM_INTERPRETER);
1723	break;
1724
1725	default:
1726	return VERR_EM_INTERPRETER;
1727	}
1728
1729	LogFlow(("XAdd %VRv=%08x reg=%08x\n", pParam1, *pParamReg2));
1730
1731	MMGCRamRegisterTrapHandler(pVM);
1732	if (pCpu->prefix & PREFIX_LOCK)
1733	rc = EMGCEmulateLockXAdd(pParam1, pParamReg2, cbSizeParamReg2, &eflags);
1734	else
1735	rc = EMGCEmulateXAdd(pParam1, pParamReg2, cbSizeParamReg2, &eflags);
1736	MMGCRamDeregisterTrapHandler(pVM);
1737
1738	if (VBOX_FAILURE(rc))
1739	{
1740	Log(("XAdd %VGv reg=%08x -> emulation failed due to page fault!\n", pParam1, *pParamReg2));
1741	return VERR_EM_INTERPRETER;
1742	}
1743
1744	LogFlow(("XAdd %VGv reg=%08x ZF=%d\n", pParam1, *pParamReg2, !!(eflags & X86_EFL_ZF)));
1745
1746	/* Update guest's eflags and finish. */
1747	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1748	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1749
1750	*pcbSize = cbSizeParamReg2;
1751	return VINF_SUCCESS;
1752	}
1753	}
1754	return VERR_EM_INTERPRETER;
1755	}
1756	#endif
1757
1758	#ifdef IN_GC
1759	/**
1760	* Interpret IRET (currently only to V86 code)
1761	*
1762	* @returns VBox status code.
1763	* @param pVM The VM handle.
1764	* @param pRegFrame The register frame.
1765	*
1766	*/
1767	EMDECL(int) EMInterpretIret(PVM pVM, PCPUMCTXCORE pRegFrame)
1768	{
1769	RTGCUINTPTR pIretStack = (RTGCUINTPTR)pRegFrame->esp;
1770	RTGCUINTPTR eip, cs, esp, ss, eflags, ds, es, fs, gs, uMask;
1771	int rc;
1772
1773	Assert(!CPUMIsGuestIn64BitCode(pVM, pRegFrame));
1774
1775	rc = emRamRead(pVM, &eip, (RTGCPTR)pIretStack , 4);
1776	rc \|= emRamRead(pVM, &cs, (RTGCPTR)(pIretStack + 4), 4);
1777	rc \|= emRamRead(pVM, &eflags, (RTGCPTR)(pIretStack + 8), 4);
1778	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1779	AssertReturn(eflags & X86_EFL_VM, VERR_EM_INTERPRETER);
1780
1781	rc \|= emRamRead(pVM, &esp, (RTGCPTR)(pIretStack + 12), 4);
1782	rc \|= emRamRead(pVM, &ss, (RTGCPTR)(pIretStack + 16), 4);
1783	rc \|= emRamRead(pVM, &es, (RTGCPTR)(pIretStack + 20), 4);
1784	rc \|= emRamRead(pVM, &ds, (RTGCPTR)(pIretStack + 24), 4);
1785	rc \|= emRamRead(pVM, &fs, (RTGCPTR)(pIretStack + 28), 4);
1786	rc \|= emRamRead(pVM, &gs, (RTGCPTR)(pIretStack + 32), 4);
1787	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1788
1789	pRegFrame->eip = eip & 0xffff;
1790	pRegFrame->cs = cs;
1791
1792	/* Mask away all reserved bits */
1793	uMask = X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_RF \| X86_EFL_VM \| X86_EFL_AC \| X86_EFL_VIF \| X86_EFL_VIP \| X86_EFL_ID;
1794	eflags &= uMask;
1795
1796	#ifndef IN_RING0
1797	CPUMRawSetEFlags(pVM, pRegFrame, eflags);
1798	#endif
1799	Assert((pRegFrame->eflags.u32 & (X86_EFL_IF\|X86_EFL_IOPL)) == X86_EFL_IF);
1800
1801	pRegFrame->esp = esp;
1802	pRegFrame->ss = ss;
1803	pRegFrame->ds = ds;
1804	pRegFrame->es = es;
1805	pRegFrame->fs = fs;
1806	pRegFrame->gs = gs;
1807
1808	return VINF_SUCCESS;
1809	}
1810	#endif
1811
1812	/**
1813	* IRET Emulation.
1814	*/
1815	static int emInterpretIret(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1816	{
1817	/* only allow direct calls to EMInterpretIret for now */
1818	return VERR_EM_INTERPRETER;
1819	}
1820
1821	/**
1822	* INVLPG Emulation.
1823	*/
1824
1825	/**
1826	* Interpret INVLPG
1827	*
1828	* @returns VBox status code.
1829	* @param pVM The VM handle.
1830	* @param pRegFrame The register frame.
1831	* @param pAddrGC Operand address
1832	*
1833	*/
1834	EMDECL(int) EMInterpretInvlpg(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC)
1835	{
1836	int rc;
1837
1838	/** @todo is addr always a flat linear address or ds based
1839	* (in absence of segment override prefixes)????
1840	*/
1841	#ifdef IN_GC
1842	// Note: we could also use PGMFlushPage here, but it currently doesn't always use invlpg!!!!!!!!!!
1843	LogFlow(("GC: EMULATE: invlpg %08X\n", pAddrGC));
1844	rc = PGMGCInvalidatePage(pVM, pAddrGC);
1845	#else
1846	rc = PGMInvalidatePage(pVM, pAddrGC);
1847	#endif
1848	if (VBOX_SUCCESS(rc))
1849	return VINF_SUCCESS;
1850	Log(("PGMInvalidatePage %VGv returned %VGv (%d)\n", pAddrGC, rc, rc));
1851	Assert(rc == VERR_REM_FLUSHED_PAGES_OVERFLOW);
1852	/** @todo r=bird: we shouldn't ignore returns codes like this... I'm 99% sure the error is fatal. */
1853	return VERR_EM_INTERPRETER;
1854	}
1855
1856	static int emInterpretInvlPg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1857	{
1858	OP_PARAMVAL param1;
1859	RTGCPTR addr;
1860
1861	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1862	if(VBOX_FAILURE(rc))
1863	return VERR_EM_INTERPRETER;
1864
1865	switch(param1.type)
1866	{
1867	case PARMTYPE_IMMEDIATE:
1868	case PARMTYPE_ADDRESS:
1869	if(!(param1.flags & (PARAM_VAL32\|PARAM_VAL64)))
1870	return VERR_EM_INTERPRETER;
1871	addr = (RTGCPTR)param1.val.val64;
1872	break;
1873
1874	default:
1875	return VERR_EM_INTERPRETER;
1876	}
1877
1878	/** @todo is addr always a flat linear address or ds based
1879	* (in absence of segment override prefixes)????
1880	*/
1881	#ifdef IN_GC
1882	// Note: we could also use PGMFlushPage here, but it currently doesn't always use invlpg!!!!!!!!!!
1883	LogFlow(("GC: EMULATE: invlpg %08X\n", addr));
1884	rc = PGMGCInvalidatePage(pVM, addr);
1885	#else
1886	rc = PGMInvalidatePage(pVM, addr);
1887	#endif
1888	if (VBOX_SUCCESS(rc))
1889	return VINF_SUCCESS;
1890	/** @todo r=bird: we shouldn't ignore returns codes like this... I'm 99% sure the error is fatal. */
1891	return VERR_EM_INTERPRETER;
1892	}
1893
1894	/**
1895	* CPUID Emulation.
1896	*/
1897
1898	/**
1899	* Interpret CPUID given the parameters in the CPU context
1900	*
1901	* @returns VBox status code.
1902	* @param pVM The VM handle.
1903	* @param pRegFrame The register frame.
1904	*
1905	*/
1906	EMDECL(int) EMInterpretCpuId(PVM pVM, PCPUMCTXCORE pRegFrame)
1907	{
1908	uint32_t iLeaf = pRegFrame->eax; NOREF(iLeaf);
1909
1910	/* Note: operates the same in 64 and non-64 bits mode. */
1911	CPUMGetGuestCpuId(pVM, pRegFrame->eax, &pRegFrame->eax, &pRegFrame->ebx, &pRegFrame->ecx, &pRegFrame->edx);
1912	Log(("Emulate: CPUID %x -> %08x %08x %08x %08x\n", iLeaf, pRegFrame->eax, pRegFrame->ebx, pRegFrame->ecx, pRegFrame->edx));
1913	return VINF_SUCCESS;
1914	}
1915
1916	static int emInterpretCpuId(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1917	{
1918	int rc = EMInterpretCpuId(pVM, pRegFrame);
1919	return rc;
1920	}
1921
1922	/**
1923	* MOV CRx Emulation.
1924	*/
1925
1926	/**
1927	* Interpret CRx read
1928	*
1929	* @returns VBox status code.
1930	* @param pVM The VM handle.
1931	* @param pRegFrame The register frame.
1932	* @param DestRegGen General purpose register index (USE_REG_E**))
1933	* @param SrcRegCRx CRx register index (USE_REG_CR*)
1934	*
1935	*/
1936	EMDECL(int) EMInterpretCRxRead(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx)
1937	{
1938	int rc;
1939	uint64_t val64;
1940
1941	if (SrcRegCrx == USE_REG_CR8)
1942	{
1943	val64 = 0;
1944	rc = PDMApicGetTPR(pVM, (uint8_t *)&val64, NULL);
1945	AssertMsgRCReturn(rc, ("PDMApicGetTPR failed\n"), VERR_EM_INTERPRETER);
1946	}
1947	else
1948	{
1949	rc = CPUMGetGuestCRx(pVM, SrcRegCrx, &val64);
1950	AssertMsgRCReturn(rc, ("CPUMGetGuestCRx %d failed\n", SrcRegCrx), VERR_EM_INTERPRETER);
1951	}
1952
1953	if (CPUMIsGuestIn64BitCode(pVM, pRegFrame))
1954	rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
1955	else
1956	rc = DISWriteReg32(pRegFrame, DestRegGen, val64);
1957
1958	if(VBOX_SUCCESS(rc))
1959	{
1960	LogFlow(("MOV_CR: gen32=%d CR=%d val=%VX64\n", DestRegGen, SrcRegCrx, val64));
1961	return VINF_SUCCESS;
1962	}
1963	return VERR_EM_INTERPRETER;
1964	}
1965
1966
1967	/**
1968	* Interpret LMSW
1969	*
1970	* @returns VBox status code.
1971	* @param pVM The VM handle.
1972	* @param u16Data LMSW source data.
1973	*
1974	*/
1975	EMDECL(int) EMInterpretLMSW(PVM pVM, uint16_t u16Data)
1976	{
1977	uint64_t OldCr0 = CPUMGetGuestCR0(pVM);
1978
1979	/* don't use this path to go into protected mode! */
1980	Assert(OldCr0 & X86_CR0_PE);
1981	if (!(OldCr0 & X86_CR0_PE))
1982	return VERR_EM_INTERPRETER;
1983
1984	/* Only PE, MP, EM and TS can be changed; note that PE can't be cleared by this instruction. */
1985	uint64_t NewCr0 = ( OldCr0 & ~( X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
1986	\| (u16Data & (X86_CR0_PE \| X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS));
1987
1988	#ifdef IN_GC
1989	/* Need to change the hyper CR0? Doing it the lazy way then. */
1990	if ( (OldCr0 & (X86_CR0_AM \| X86_CR0_WP))
1991	!= (NewCr0 & (X86_CR0_AM \| X86_CR0_WP)))
1992	{
1993	Log(("EMInterpretLMSW: CR0: %#x->%#x => R3\n", OldCr0, NewCr0));
1994	VM_FF_SET(pVM, VM_FF_TO_R3);
1995	}
1996	#endif
1997
1998	return CPUMSetGuestCR0(pVM, NewCr0);
1999	}
2000
2001
2002	/**
2003	* Interpret CLTS
2004	*
2005	* @returns VBox status code.
2006	* @param pVM The VM handle.
2007	*
2008	*/
2009	EMDECL(int) EMInterpretCLTS(PVM pVM)
2010	{
2011	uint64_t cr0 = CPUMGetGuestCR0(pVM);
2012	if (!(cr0 & X86_CR0_TS))
2013	return VINF_SUCCESS;
2014	return CPUMSetGuestCR0(pVM, cr0 & ~X86_CR0_TS);
2015	}
2016
2017	static int emInterpretClts(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2018	{
2019	return EMInterpretCLTS(pVM);
2020	}
2021
2022	/**
2023	* Interpret CRx write
2024	*
2025	* @returns VBox status code.
2026	* @param pVM The VM handle.
2027	* @param pRegFrame The register frame.
2028	* @param DestRegCRx CRx register index (USE_REG_CR*)
2029	* @param SrcRegGen General purpose register index (USE_REG_E**))
2030	*
2031	*/
2032	EMDECL(int) EMInterpretCRxWrite(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint32_t SrcRegGen)
2033	{
2034	uint64_t val;
2035	uint64_t oldval;
2036	uint64_t msrEFER;
2037	int rc;
2038
2039	/** @todo Clean up this mess. */
2040	if (CPUMIsGuestIn64BitCode(pVM, pRegFrame))
2041	{
2042	rc = DISFetchReg64(pRegFrame, SrcRegGen, &val);
2043	}
2044	else
2045	{
2046	uint32_t val32;
2047	rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
2048	val = val32;
2049	}
2050
2051	if (VBOX_SUCCESS(rc))
2052	{
2053	LogFlow(("EMInterpretCRxWrite at %VGv CR%d <- %VX64\n", pRegFrame->rip, DestRegCrx, val));
2054	switch (DestRegCrx)
2055	{
2056	case USE_REG_CR0:
2057	oldval = CPUMGetGuestCR0(pVM);
2058	#ifdef IN_GC
2059	/* CR0.WP and CR0.AM changes require a reschedule run in ring 3. */
2060	if ( (val & (X86_CR0_WP \| X86_CR0_AM))
2061	!= (oldval & (X86_CR0_WP \| X86_CR0_AM)))
2062	return VERR_EM_INTERPRETER;
2063	#endif
2064	CPUMSetGuestCR0(pVM, val);
2065	val = CPUMGetGuestCR0(pVM);
2066	if ( (oldval & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE))
2067	!= (val & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE)))
2068	{
2069	/* global flush */
2070	rc = PGMFlushTLB(pVM, CPUMGetGuestCR3(pVM), true /* global */);
2071	AssertRCReturn(rc, rc);
2072	}
2073
2074	/* Deal with long mode enabling/disabling. */
2075	msrEFER = CPUMGetGuestEFER(pVM);
2076	if (msrEFER & MSR_K6_EFER_LME)
2077	{
2078	if ( !(oldval & X86_CR0_PG)
2079	&& (val & X86_CR0_PG))
2080	{
2081	/* Illegal to have an active 64 bits CS selector (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
2082	if (pRegFrame->csHid.Attr.n.u1Long)
2083	{
2084	AssertMsgFailed(("Illegal enabling of paging with CS.u1Long = 1!!\n"));
2085	return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
2086	}
2087
2088	/* Illegal to switch to long mode before activating PAE first (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
2089	if (!(CPUMGetGuestCR4(pVM) & X86_CR4_PAE))
2090	{
2091	AssertMsgFailed(("Illegal enabling of paging with PAE disabled!!\n"));
2092	return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
2093	}
2094	msrEFER \|= MSR_K6_EFER_LMA;
2095	}
2096	else
2097	if ( (oldval & X86_CR0_PG)
2098	&& !(val & X86_CR0_PG))
2099	{
2100	msrEFER &= ~MSR_K6_EFER_LMA;
2101	/* @todo Do we need to cut off rip here? High dword of rip is undefined, so it shouldn't really matter. */
2102	}
2103	CPUMSetGuestEFER(pVM, msrEFER);
2104	}
2105	return PGMChangeMode(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR4(pVM), CPUMGetGuestEFER(pVM));
2106
2107	case USE_REG_CR2:
2108	rc = CPUMSetGuestCR2(pVM, val); AssertRC(rc);
2109	return VINF_SUCCESS;
2110
2111	case USE_REG_CR3:
2112	/* Reloading the current CR3 means the guest just wants to flush the TLBs */
2113	rc = CPUMSetGuestCR3(pVM, val); AssertRC(rc);
2114	if (CPUMGetGuestCR0(pVM) & X86_CR0_PG)
2115	{
2116	/* flush */
2117	rc = PGMFlushTLB(pVM, val, !(CPUMGetGuestCR4(pVM) & X86_CR4_PGE));
2118	AssertRCReturn(rc, rc);
2119	}
2120	return VINF_SUCCESS;
2121
2122	case USE_REG_CR4:
2123	oldval = CPUMGetGuestCR4(pVM);
2124	rc = CPUMSetGuestCR4(pVM, val); AssertRC(rc);
2125	val = CPUMGetGuestCR4(pVM);
2126
2127	msrEFER = CPUMGetGuestEFER(pVM);
2128	/* Illegal to disable PAE when long mode is active. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
2129	if ( (msrEFER & MSR_K6_EFER_LMA)
2130	&& (oldval & X86_CR4_PAE)
2131	&& !(val & X86_CR4_PAE))
2132	{
2133	return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
2134	}
2135
2136	if ( (oldval & (X86_CR4_PGE\|X86_CR4_PAE\|X86_CR4_PSE))
2137	!= (val & (X86_CR4_PGE\|X86_CR4_PAE\|X86_CR4_PSE)))
2138	{
2139	/* global flush */
2140	rc = PGMFlushTLB(pVM, CPUMGetGuestCR3(pVM), true /* global */);
2141	AssertRCReturn(rc, rc);
2142	}
2143	# ifdef IN_GC
2144	/* Feeling extremely lazy. */
2145	if ( (oldval & (X86_CR4_OSFSXR\|X86_CR4_OSXMMEEXCPT\|X86_CR4_PCE\|X86_CR4_MCE\|X86_CR4_PAE\|X86_CR4_DE\|X86_CR4_TSD\|X86_CR4_PVI\|X86_CR4_VME))
2146	!= (val & (X86_CR4_OSFSXR\|X86_CR4_OSXMMEEXCPT\|X86_CR4_PCE\|X86_CR4_MCE\|X86_CR4_PAE\|X86_CR4_DE\|X86_CR4_TSD\|X86_CR4_PVI\|X86_CR4_VME)))
2147	{
2148	Log(("emInterpretMovCRx: CR4: %#RX64->%#RX64 => R3\n", oldval, val));
2149	VM_FF_SET(pVM, VM_FF_TO_R3);
2150	}
2151	# endif
2152	return PGMChangeMode(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR4(pVM), CPUMGetGuestEFER(pVM));
2153
2154	case USE_REG_CR8:
2155	return PDMApicSetTPR(pVM, val);
2156
2157	default:
2158	AssertFailed();
2159	case USE_REG_CR1: /* illegal op */
2160	break;
2161	}
2162	}
2163	return VERR_EM_INTERPRETER;
2164	}
2165
2166	static int emInterpretMovCRx(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2167	{
2168	if ((pCpu->param1.flags == USE_REG_GEN32 \|\| pCpu->param1.flags == USE_REG_GEN64) && pCpu->param2.flags == USE_REG_CR)
2169	return EMInterpretCRxRead(pVM, pRegFrame, pCpu->param1.base.reg_gen, pCpu->param2.base.reg_ctrl);
2170
2171	if (pCpu->param1.flags == USE_REG_CR && (pCpu->param2.flags == USE_REG_GEN32 \|\| pCpu->param2.flags == USE_REG_GEN64))
2172	return EMInterpretCRxWrite(pVM, pRegFrame, pCpu->param1.base.reg_ctrl, pCpu->param2.base.reg_gen);
2173
2174	AssertMsgFailedReturn(("Unexpected control register move\n"), VERR_EM_INTERPRETER);
2175	return VERR_EM_INTERPRETER;
2176	}
2177
2178	/**
2179	* MOV DRx
2180	*/
2181
2182	/**
2183	* Interpret DRx write
2184	*
2185	* @returns VBox status code.
2186	* @param pVM The VM handle.
2187	* @param pRegFrame The register frame.
2188	* @param DestRegDRx DRx register index (USE_REG_DR*)
2189	* @param SrcRegGen General purpose register index (USE_REG_E**))
2190	*
2191	*/
2192	EMDECL(int) EMInterpretDRxWrite(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen)
2193	{
2194	uint64_t val;
2195	int rc;
2196
2197	if (CPUMIsGuestIn64BitCode(pVM, pRegFrame))
2198	{
2199	rc = DISFetchReg64(pRegFrame, SrcRegGen, &val);
2200	}
2201	else
2202	{
2203	uint32_t val32;
2204	rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
2205	val = val32;
2206	}
2207
2208	if (VBOX_SUCCESS(rc))
2209	{
2210	/* @todo: we don't fail if illegal bits are set/cleared for e.g. dr7 */
2211	rc = CPUMSetGuestDRx(pVM, DestRegDrx, val);
2212	if (VBOX_SUCCESS(rc))
2213	return rc;
2214	AssertMsgFailed(("CPUMSetGuestDRx %d failed\n", DestRegDrx));
2215	}
2216	return VERR_EM_INTERPRETER;
2217	}
2218
2219	/**
2220	* Interpret DRx read
2221	*
2222	* @returns VBox status code.
2223	* @param pVM The VM handle.
2224	* @param pRegFrame The register frame.
2225	* @param DestRegGen General purpose register index (USE_REG_E**))
2226	* @param SrcRegDRx DRx register index (USE_REG_DR*)
2227	*
2228	*/
2229	EMDECL(int) EMInterpretDRxRead(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx)
2230	{
2231	uint64_t val64;
2232
2233	int rc = CPUMGetGuestDRx(pVM, SrcRegDrx, &val64);
2234	AssertMsgRCReturn(rc, ("CPUMGetGuestDRx %d failed\n", SrcRegDrx), VERR_EM_INTERPRETER);
2235	if (CPUMIsGuestIn64BitCode(pVM, pRegFrame))
2236	{
2237	rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
2238	}
2239	else
2240	rc = DISWriteReg32(pRegFrame, DestRegGen, (uint32_t)val64);
2241
2242	if (VBOX_SUCCESS(rc))
2243	return VINF_SUCCESS;
2244
2245	return VERR_EM_INTERPRETER;
2246	}
2247
2248	static int emInterpretMovDRx(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2249	{
2250	int rc = VERR_EM_INTERPRETER;
2251
2252	if((pCpu->param1.flags == USE_REG_GEN32 \|\| pCpu->param1.flags == USE_REG_GEN64) && pCpu->param2.flags == USE_REG_DBG)
2253	{
2254	rc = EMInterpretDRxRead(pVM, pRegFrame, pCpu->param1.base.reg_gen, pCpu->param2.base.reg_dbg);
2255	}
2256	else
2257	if(pCpu->param1.flags == USE_REG_DBG && (pCpu->param2.flags == USE_REG_GEN32 \|\| pCpu->param2.flags == USE_REG_GEN64))
2258	{
2259	rc = EMInterpretDRxWrite(pVM, pRegFrame, pCpu->param1.base.reg_dbg, pCpu->param2.base.reg_gen);
2260	}
2261	else
2262	AssertMsgFailed(("Unexpected debug register move\n"));
2263
2264	return rc;
2265	}
2266
2267	/**
2268	* LLDT Emulation.
2269	*/
2270	static int emInterpretLLdt(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2271	{
2272	OP_PARAMVAL param1;
2273	RTSEL sel;
2274
2275	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
2276	if(VBOX_FAILURE(rc))
2277	return VERR_EM_INTERPRETER;
2278
2279	switch(param1.type)
2280	{
2281	case PARMTYPE_ADDRESS:
2282	return VERR_EM_INTERPRETER; //feeling lazy right now
2283
2284	case PARMTYPE_IMMEDIATE:
2285	if(!(param1.flags & PARAM_VAL16))
2286	return VERR_EM_INTERPRETER;
2287	sel = (RTSEL)param1.val.val16;
2288	break;
2289
2290	default:
2291	return VERR_EM_INTERPRETER;
2292	}
2293
2294	if (sel == 0)
2295	{
2296	if (CPUMGetHyperLDTR(pVM) == 0)
2297	{
2298	// this simple case is most frequent in Windows 2000 (31k - boot & shutdown)
2299	return VINF_SUCCESS;
2300	}
2301	}
2302	//still feeling lazy
2303	return VERR_EM_INTERPRETER;
2304	}
2305
2306	#ifdef IN_GC
2307	/**
2308	* STI Emulation.
2309	*
2310	* @remark the instruction following sti is guaranteed to be executed before any interrupts are dispatched
2311	*/
2312	static int emInterpretSti(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2313	{
2314	PPATMGCSTATE pGCState = PATMQueryGCState(pVM);
2315
2316	if(!pGCState)
2317	{
2318	Assert(pGCState);
2319	return VERR_EM_INTERPRETER;
2320	}
2321	pGCState->uVMFlags \|= X86_EFL_IF;
2322
2323	Assert(pRegFrame->eflags.u32 & X86_EFL_IF);
2324	Assert(pvFault == SELMToFlat(pVM, DIS_SELREG_CS, pRegFrame, (RTGCPTR)pRegFrame->rip));
2325
2326	pVM->em.s.GCPtrInhibitInterrupts = pRegFrame->eip + pCpu->opsize;
2327	VM_FF_SET(pVM, VM_FF_INHIBIT_INTERRUPTS);
2328
2329	return VINF_SUCCESS;
2330	}
2331	#endif /* IN_GC */
2332
2333
2334	/**
2335	* HLT Emulation.
2336	*/
2337	static int emInterpretHlt(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2338	{
2339	return VINF_EM_HALT;
2340	}
2341
2342
2343	/**
2344	* RDTSC Emulation.
2345	*/
2346
2347	/**
2348	* Interpret RDTSC
2349	*
2350	* @returns VBox status code.
2351	* @param pVM The VM handle.
2352	* @param pRegFrame The register frame.
2353	*
2354	*/
2355	EMDECL(int) EMInterpretRdtsc(PVM pVM, PCPUMCTXCORE pRegFrame)
2356	{
2357	unsigned uCR4 = CPUMGetGuestCR4(pVM);
2358
2359	if (uCR4 & X86_CR4_TSD)
2360	return VERR_EM_INTERPRETER; /* genuine #GP */
2361
2362	uint64_t uTicks = TMCpuTickGet(pVM);
2363
2364	/* Same behaviour in 32 & 64 bits mode */
2365	pRegFrame->eax = uTicks;
2366	pRegFrame->edx = (uTicks >> 32ULL);
2367
2368	return VINF_SUCCESS;
2369	}
2370
2371	static int emInterpretRdtsc(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2372	{
2373	return EMInterpretRdtsc(pVM, pRegFrame);
2374	}
2375
2376	/**
2377	* MONITOR Emulation.
2378	*/
2379	static int emInterpretMonitor(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2380	{
2381	uint32_t u32Dummy, u32ExtFeatures, cpl;
2382
2383	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
2384	if (pRegFrame->ecx != 0)
2385	return VERR_EM_INTERPRETER; /* illegal value. */
2386
2387	/* Get the current privilege level. */
2388	cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2389	if (cpl != 0)
2390	return VERR_EM_INTERPRETER; /* supervisor only */
2391
2392	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
2393	if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
2394	return VERR_EM_INTERPRETER; /* not supported */
2395
2396	return VINF_SUCCESS;
2397	}
2398
2399
2400	/**
2401	* MWAIT Emulation.
2402	*/
2403	static int emInterpretMWait(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2404	{
2405	uint32_t u32Dummy, u32ExtFeatures, cpl;
2406
2407	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
2408	if (pRegFrame->ecx != 0)
2409	return VERR_EM_INTERPRETER; /* illegal value. */
2410
2411	/* Get the current privilege level. */
2412	cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2413	if (cpl != 0)
2414	return VERR_EM_INTERPRETER; /* supervisor only */
2415
2416	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
2417	if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
2418	return VERR_EM_INTERPRETER; /* not supported */
2419
2420	/** @todo not completely correct */
2421	return VINF_EM_HALT;
2422	}
2423
2424	#ifdef LOG_ENABLED
2425	static const char *emMSRtoString(unsigned uMsr)
2426	{
2427	switch(uMsr)
2428	{
2429	case MSR_IA32_APICBASE:
2430	return "MSR_IA32_APICBASE";
2431	case MSR_IA32_CR_PAT:
2432	return "MSR_IA32_CR_PAT";
2433	case MSR_IA32_SYSENTER_CS:
2434	return "MSR_IA32_SYSENTER_CS";
2435	case MSR_IA32_SYSENTER_EIP:
2436	return "MSR_IA32_SYSENTER_EIP";
2437	case MSR_IA32_SYSENTER_ESP:
2438	return "MSR_IA32_SYSENTER_ESP";
2439	case MSR_K6_EFER:
2440	return "MSR_K6_EFER";
2441	case MSR_K8_SF_MASK:
2442	return "MSR_K8_SF_MASK";
2443	case MSR_K6_STAR:
2444	return "MSR_K6_STAR";
2445	case MSR_K8_LSTAR:
2446	return "MSR_K8_LSTAR";
2447	case MSR_K8_CSTAR:
2448	return "MSR_K8_CSTAR";
2449	case MSR_K8_FS_BASE:
2450	return "MSR_K8_FS_BASE";
2451	case MSR_K8_GS_BASE:
2452	return "MSR_K8_GS_BASE";
2453	case MSR_K8_KERNEL_GS_BASE:
2454	return "MSR_K8_KERNEL_GS_BASE";
2455	case MSR_IA32_BIOS_SIGN_ID:
2456	return "Unsupported MSR_IA32_BIOS_SIGN_ID";
2457	case MSR_IA32_PLATFORM_ID:
2458	return "Unsupported MSR_IA32_PLATFORM_ID";
2459	case MSR_IA32_BIOS_UPDT_TRIG:
2460	return "Unsupported MSR_IA32_BIOS_UPDT_TRIG";
2461	case MSR_IA32_TSC:
2462	return "Unsupported MSR_IA32_TSC";
2463	case MSR_IA32_MTRR_CAP:
2464	return "Unsupported MSR_IA32_MTRR_CAP";
2465	case MSR_IA32_MCP_CAP:
2466	return "Unsupported MSR_IA32_MCP_CAP";
2467	case MSR_IA32_MCP_STATUS:
2468	return "Unsupported MSR_IA32_MCP_STATUS";
2469	case MSR_IA32_MCP_CTRL:
2470	return "Unsupported MSR_IA32_MCP_CTRL";
2471	case MSR_IA32_MTRR_DEF_TYPE:
2472	return "Unsupported MSR_IA32_MTRR_DEF_TYPE";
2473	case MSR_K7_EVNTSEL0:
2474	return "Unsupported MSR_K7_EVNTSEL0";
2475	case MSR_K7_EVNTSEL1:
2476	return "Unsupported MSR_K7_EVNTSEL1";
2477	case MSR_K7_EVNTSEL2:
2478	return "Unsupported MSR_K7_EVNTSEL2";
2479	case MSR_K7_EVNTSEL3:
2480	return "Unsupported MSR_K7_EVNTSEL3";
2481	case MSR_IA32_MC0_CTL:
2482	return "Unsupported MSR_IA32_MC0_CTL";
2483	case MSR_IA32_MC0_STATUS:
2484	return "Unsupported MSR_IA32_MC0_STATUS";
2485	}
2486	return "Unknown MSR";
2487	}
2488	#endif
2489
2490	/**
2491	* Interpret RDMSR
2492	*
2493	* @returns VBox status code.
2494	* @param pVM The VM handle.
2495	* @param pRegFrame The register frame.
2496	*
2497	*/
2498	EMDECL(int) EMInterpretRdmsr(PVM pVM, PCPUMCTXCORE pRegFrame)
2499	{
2500	uint32_t u32Dummy, u32Features, cpl;
2501	uint64_t val;
2502	CPUMCTX *pCtx;
2503	int rc;
2504
2505	/** @todo According to the Intel manuals, there's a REX version of RDMSR that is slightly different.
2506	* That version clears the high dwords of both RDX & RAX */
2507	rc = CPUMQueryGuestCtxPtr(pVM, &pCtx);
2508	AssertRC(rc);
2509
2510	/* Get the current privilege level. */
2511	cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2512	if (cpl != 0)
2513	return VERR_EM_INTERPRETER; /* supervisor only */
2514
2515	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2516	if (!(u32Features & X86_CPUID_FEATURE_EDX_MSR))
2517	return VERR_EM_INTERPRETER; /* not supported */
2518
2519	switch (pRegFrame->ecx)
2520	{
2521	case MSR_IA32_APICBASE:
2522	rc = PDMApicGetBase(pVM, &val);
2523	AssertRC(rc);
2524	break;
2525
2526	case MSR_IA32_CR_PAT:
2527	val = pCtx->msrPAT;
2528	break;
2529
2530	case MSR_IA32_SYSENTER_CS:
2531	val = pCtx->SysEnter.cs;
2532	break;
2533
2534	case MSR_IA32_SYSENTER_EIP:
2535	val = pCtx->SysEnter.eip;
2536	break;
2537
2538	case MSR_IA32_SYSENTER_ESP:
2539	val = pCtx->SysEnter.esp;
2540	break;
2541
2542	case MSR_K6_EFER:
2543	val = pCtx->msrEFER;
2544	break;
2545
2546	case MSR_K8_SF_MASK:
2547	val = pCtx->msrSFMASK;
2548	break;
2549
2550	case MSR_K6_STAR:
2551	val = pCtx->msrSTAR;
2552	break;
2553
2554	case MSR_K8_LSTAR:
2555	val = pCtx->msrLSTAR;
2556	break;
2557
2558	case MSR_K8_CSTAR:
2559	val = pCtx->msrCSTAR;
2560	break;
2561
2562	case MSR_K8_FS_BASE:
2563	val = pCtx->fsHid.u64Base;
2564	break;
2565
2566	case MSR_K8_GS_BASE:
2567	val = pCtx->gsHid.u64Base;
2568	break;
2569
2570	case MSR_K8_KERNEL_GS_BASE:
2571	val = pCtx->msrKERNELGSBASE;
2572	break;
2573
2574	#if 0 /def IN_RING0 /
2575	case MSR_IA32_PLATFORM_ID:
2576	case MSR_IA32_BIOS_SIGN_ID:
2577	if (CPUMGetCPUVendor(pVM) == CPUMCPUVENDOR_INTEL)
2578	{
2579	/* Available since the P6 family. VT-x implies that this feature is present. */
2580	if (pRegFrame->ecx == MSR_IA32_PLATFORM_ID)
2581	val = ASMRdMsr(MSR_IA32_PLATFORM_ID);
2582	else
2583	if (pRegFrame->ecx == MSR_IA32_BIOS_SIGN_ID)
2584	val = ASMRdMsr(MSR_IA32_BIOS_SIGN_ID);
2585	break;
2586	}
2587	/* no break */
2588	#endif
2589	default:
2590	/* We should actually trigger a #GP here, but don't as that might cause more trouble. */
2591	val = 0;
2592	break;
2593	}
2594	Log(("EMInterpretRdmsr %s (%x) -> val=%VX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx, val));
2595	pRegFrame->eax = (uint32_t) val;
2596	pRegFrame->edx = (uint32_t) (val >> 32ULL);
2597	return VINF_SUCCESS;
2598	}
2599
2600	/**
2601	* RDMSR Emulation.
2602	*/
2603	static int emInterpretRdmsr(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2604	{
2605	/* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
2606	Assert(!(pCpu->prefix & PREFIX_REX));
2607	return EMInterpretRdmsr(pVM, pRegFrame);
2608	}
2609
2610	/**
2611	* Interpret WRMSR
2612	*
2613	* @returns VBox status code.
2614	* @param pVM The VM handle.
2615	* @param pRegFrame The register frame.
2616	*
2617	*/
2618	EMDECL(int) EMInterpretWrmsr(PVM pVM, PCPUMCTXCORE pRegFrame)
2619	{
2620	uint32_t u32Dummy, u32Features, cpl;
2621	uint64_t val;
2622	CPUMCTX *pCtx;
2623	int rc;
2624
2625	/* Note: works the same in 32 and 64 bits modes. */
2626	rc = CPUMQueryGuestCtxPtr(pVM, &pCtx);
2627	AssertRC(rc);
2628
2629	/* Get the current privilege level. */
2630	cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2631	if (cpl != 0)
2632	return VERR_EM_INTERPRETER; /* supervisor only */
2633
2634	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2635	if (!(u32Features & X86_CPUID_FEATURE_EDX_MSR))
2636	return VERR_EM_INTERPRETER; /* not supported */
2637
2638	val = (uint64_t)pRegFrame->eax \| ((uint64_t)pRegFrame->edx << 32ULL);
2639	Log(("EMInterpretWrmsr %s (%x) val=%VX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx, val));
2640	switch (pRegFrame->ecx)
2641	{
2642	case MSR_IA32_APICBASE:
2643	rc = PDMApicSetBase(pVM, val);
2644	AssertRC(rc);
2645	break;
2646
2647	case MSR_IA32_CR_PAT:
2648	pCtx->msrPAT = val;
2649	break;
2650
2651	case MSR_IA32_SYSENTER_CS:
2652	pCtx->SysEnter.cs = val & 0xffff; /* 16 bits selector */
2653	break;
2654
2655	case MSR_IA32_SYSENTER_EIP:
2656	pCtx->SysEnter.eip = val;
2657	break;
2658
2659	case MSR_IA32_SYSENTER_ESP:
2660	pCtx->SysEnter.esp = val;
2661	break;
2662
2663	case MSR_K6_EFER:
2664	{
2665	uint64_t uMask = 0;
2666	uint64_t oldval = pCtx->msrEFER;
2667
2668	/* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
2669	CPUMGetGuestCpuId(pVM, 0x80000001, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2670	if (u32Features & X86_CPUID_AMD_FEATURE_EDX_NX)
2671	uMask \|= MSR_K6_EFER_NXE;
2672	if (u32Features & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE)
2673	uMask \|= MSR_K6_EFER_LME;
2674	if (u32Features & X86_CPUID_AMD_FEATURE_EDX_SEP)
2675	uMask \|= MSR_K6_EFER_SCE;
2676	if (u32Features & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
2677	uMask \|= MSR_K6_EFER_FFXSR;
2678
2679	/* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
2680	if ( ((pCtx->msrEFER & MSR_K6_EFER_LME) != (val & uMask & MSR_K6_EFER_LME))
2681	&& (pCtx->cr0 & X86_CR0_PG))
2682	{
2683	AssertMsgFailed(("Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
2684	return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
2685	}
2686
2687	/* There are a few more: e.g. MSR_K6_EFER_LMSLE */
2688	AssertMsg(!(val & ~(MSR_K6_EFER_NXE\|MSR_K6_EFER_LME\|MSR_K6_EFER_LMA /* ignored anyway */ \|MSR_K6_EFER_SCE\|MSR_K6_EFER_FFXSR)), ("Unexpected value %RX64\n", val));
2689	pCtx->msrEFER = (pCtx->msrEFER & ~uMask) \| (val & uMask);
2690
2691	/* AMD64 Achitecture Programmer's Manual: 15.15 TLB Control; flush the TLB if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
2692	if ((oldval & (MSR_K6_EFER_NXE\|MSR_K6_EFER_LME\|MSR_K6_EFER_LMA)) != (pCtx->msrEFER & (MSR_K6_EFER_NXE\|MSR_K6_EFER_LME\|MSR_K6_EFER_LMA)))
2693	HWACCMFlushTLB(pVM);
2694
2695	break;
2696	}
2697
2698	case MSR_K8_SF_MASK:
2699	pCtx->msrSFMASK = val;
2700	break;
2701
2702	case MSR_K6_STAR:
2703	pCtx->msrSTAR = val;
2704	break;
2705
2706	case MSR_K8_LSTAR:
2707	pCtx->msrLSTAR = val;
2708	break;
2709
2710	case MSR_K8_CSTAR:
2711	pCtx->msrCSTAR = val;
2712	break;
2713
2714	case MSR_K8_FS_BASE:
2715	pCtx->fsHid.u64Base = val;
2716	break;
2717
2718	case MSR_K8_GS_BASE:
2719	pCtx->gsHid.u64Base = val;
2720	break;
2721
2722	case MSR_K8_KERNEL_GS_BASE:
2723	pCtx->msrKERNELGSBASE = val;
2724	break;
2725
2726	default:
2727	/* We should actually trigger a #GP here, but don't as that might cause more trouble. */
2728	break;
2729	}
2730	return VINF_SUCCESS;
2731	}
2732
2733	/**
2734	* WRMSR Emulation.
2735	*/
2736	static int emInterpretWrmsr(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2737	{
2738	return EMInterpretWrmsr(pVM, pRegFrame);
2739	}
2740
2741	/**
2742	* Internal worker.
2743	* @copydoc EMInterpretInstructionCPU
2744	*/
2745	DECLINLINE(int) emInterpretInstructionCPU(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2746	{
2747	Assert(pcbSize);
2748	*pcbSize = 0;
2749
2750	/*
2751	* Only supervisor guest code!!
2752	* And no complicated prefixes.
2753	*/
2754	/* Get the current privilege level. */
2755	uint32_t cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2756	if ( cpl != 0
2757	&& pCpu->pCurInstr->opcode != OP_RDTSC) /* rdtsc requires emulation in ring 3 as well */
2758	{
2759	Log(("WARNING: refusing instruction emulation for user-mode code!!\n"));
2760	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,FailedUserMode));
2761	return VERR_EM_INTERPRETER;
2762	}
2763
2764	#ifdef IN_GC
2765	if ( (pCpu->prefix & (PREFIX_REPNE \| PREFIX_REP))
2766	\|\| ( (pCpu->prefix & PREFIX_LOCK)
2767	&& pCpu->pCurInstr->opcode != OP_CMPXCHG
2768	&& pCpu->pCurInstr->opcode != OP_CMPXCHG8B
2769	&& pCpu->pCurInstr->opcode != OP_XADD
2770	&& pCpu->pCurInstr->opcode != OP_OR
2771	&& pCpu->pCurInstr->opcode != OP_BTR
2772	)
2773	)
2774	#else
2775	if ( (pCpu->prefix & PREFIX_REPNE)
2776	\|\| ( (pCpu->prefix & PREFIX_REP)
2777	&& pCpu->pCurInstr->opcode != OP_STOSWD
2778	)
2779	\|\| ( (pCpu->prefix & PREFIX_LOCK)
2780	&& pCpu->pCurInstr->opcode != OP_OR
2781	&& pCpu->pCurInstr->opcode != OP_BTR
2782	)
2783	)
2784	#endif
2785	{
2786	//Log(("EMInterpretInstruction: wrong prefix!!\n"));
2787	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,FailedPrefix));
2788	return VERR_EM_INTERPRETER;
2789	}
2790
2791	int rc;
2792	#if (defined(VBOX_STRICT) \|\| defined(LOG_ENABLED))
2793	LogFlow(("emInterpretInstructionCPU %s\n", emGetMnemonic(pCpu)));
2794	#endif
2795	switch (pCpu->pCurInstr->opcode)
2796	{
2797	# define INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
2798	case opcode:\
2799	if (pCpu->prefix & PREFIX_LOCK) \
2800	rc = emInterpretLock##InstrFn(pVM, pCpu, pRegFrame, pvFault, pcbSize, pfnEmulateLock); \
2801	else \
2802	rc = emInterpret##InstrFn(pVM, pCpu, pRegFrame, pvFault, pcbSize, pfnEmulate); \
2803	if (VBOX_SUCCESS(rc)) \
2804	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,Instr)); \
2805	else \
2806	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,Failed##Instr)); \
2807	return rc
2808	#define INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate) \
2809	case opcode:\
2810	rc = emInterpret##InstrFn(pVM, pCpu, pRegFrame, pvFault, pcbSize, pfnEmulate); \
2811	if (VBOX_SUCCESS(rc)) \
2812	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,Instr)); \
2813	else \
2814	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,Failed##Instr)); \
2815	return rc
2816
2817	#define INTERPRET_CASE_EX_PARAM2(opcode, Instr, InstrFn, pfnEmulate) \
2818	INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate)
2819	#define INTERPRET_CASE_EX_LOCK_PARAM2(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
2820	INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock)
2821
2822	#define INTERPRET_CASE(opcode, Instr) \
2823	case opcode:\
2824	rc = emInterpret##Instr(pVM, pCpu, pRegFrame, pvFault, pcbSize); \
2825	if (VBOX_SUCCESS(rc)) \
2826	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,Instr)); \
2827	else \
2828	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,Failed##Instr)); \
2829	return rc
2830	#define INTERPRET_STAT_CASE(opcode, Instr) \
2831	case opcode: STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,Failed##Instr)); return VERR_EM_INTERPRETER;
2832
2833	INTERPRET_CASE(OP_XCHG,Xchg);
2834	INTERPRET_CASE_EX_PARAM2(OP_DEC,Dec, IncDec, EMEmulateDec);
2835	INTERPRET_CASE_EX_PARAM2(OP_INC,Inc, IncDec, EMEmulateInc);
2836	INTERPRET_CASE(OP_POP,Pop);
2837	INTERPRET_CASE_EX_LOCK_PARAM3(OP_OR, Or, OrXorAnd, EMEmulateOr, EMEmulateLockOr);
2838	INTERPRET_CASE_EX_PARAM3(OP_XOR,Xor, OrXorAnd, EMEmulateXor);
2839	INTERPRET_CASE_EX_PARAM3(OP_AND,And, OrXorAnd, EMEmulateAnd);
2840	INTERPRET_CASE(OP_MOV,Mov);
2841	#ifndef IN_GC
2842	INTERPRET_CASE(OP_STOSWD,StosWD);
2843	#endif
2844	INTERPRET_CASE(OP_INVLPG,InvlPg);
2845	INTERPRET_CASE(OP_CPUID,CpuId);
2846	INTERPRET_CASE(OP_MOV_CR,MovCRx);
2847	INTERPRET_CASE(OP_MOV_DR,MovDRx);
2848	INTERPRET_CASE(OP_LLDT,LLdt);
2849	INTERPRET_CASE(OP_CLTS,Clts);
2850	INTERPRET_CASE(OP_MONITOR, Monitor);
2851	INTERPRET_CASE(OP_MWAIT, MWait);
2852	INTERPRET_CASE(OP_RDMSR, Rdmsr);
2853	INTERPRET_CASE(OP_WRMSR, Wrmsr);
2854	INTERPRET_CASE_EX_PARAM3(OP_ADD,Add, AddSub, EMEmulateAdd);
2855	INTERPRET_CASE_EX_PARAM3(OP_SUB,Sub, AddSub, EMEmulateSub);
2856	INTERPRET_CASE(OP_ADC,Adc);
2857	INTERPRET_CASE_EX_LOCK_PARAM2(OP_BTR,Btr, BitTest, EMEmulateBtr, EMEmulateLockBtr);
2858	INTERPRET_CASE_EX_PARAM2(OP_BTS,Bts, BitTest, EMEmulateBts);
2859	INTERPRET_CASE_EX_PARAM2(OP_BTC,Btc, BitTest, EMEmulateBtc);
2860	INTERPRET_CASE(OP_RDTSC,Rdtsc);
2861	INTERPRET_CASE(OP_CMPXCHG, CmpXchg);
2862	#ifdef IN_GC
2863	INTERPRET_CASE(OP_STI,Sti);
2864	INTERPRET_CASE(OP_CMPXCHG8B, CmpXchg8b);
2865	INTERPRET_CASE(OP_XADD, XAdd);
2866	#endif
2867	INTERPRET_CASE(OP_HLT,Hlt);
2868	INTERPRET_CASE(OP_IRET,Iret);
2869	#ifdef VBOX_WITH_STATISTICS
2870	#ifndef IN_GC
2871	INTERPRET_STAT_CASE(OP_CMPXCHG8B, CmpXchg8b);
2872	INTERPRET_STAT_CASE(OP_XADD, XAdd);
2873	#endif
2874	INTERPRET_STAT_CASE(OP_MOVNTPS,MovNTPS);
2875	INTERPRET_STAT_CASE(OP_WBINVD,WbInvd);
2876	#endif
2877	default:
2878	Log3(("emInterpretInstructionCPU: opcode=%d\n", pCpu->pCurInstr->opcode));
2879	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,FailedMisc));
2880	return VERR_EM_INTERPRETER;
2881	#undef INTERPRET_CASE_EX_PARAM2
2882	#undef INTERPRET_STAT_CASE
2883	#undef INTERPRET_CASE_EX
2884	#undef INTERPRET_CASE
2885	}
2886	AssertFailed();
2887	return VERR_INTERNAL_ERROR;
2888	}
2889
2890
2891	/**
2892	* Sets the PC for which interrupts should be inhibited.
2893	*
2894	* @param pVM The VM handle.
2895	* @param PC The PC.
2896	*/
2897	EMDECL(void) EMSetInhibitInterruptsPC(PVM pVM, RTGCUINTPTR PC)
2898	{
2899	pVM->em.s.GCPtrInhibitInterrupts = PC;
2900	VM_FF_SET(pVM, VM_FF_INHIBIT_INTERRUPTS);
2901	}
2902
2903
2904	/**
2905	* Gets the PC for which interrupts should be inhibited.
2906	*
2907	* There are a few instructions which inhibits or delays interrupts
2908	* for the instruction following them. These instructions are:
2909	* - STI
2910	* - MOV SS, r/m16
2911	* - POP SS
2912	*
2913	* @returns The PC for which interrupts should be inhibited.
2914	* @param pVM VM handle.
2915	*
2916	*/
2917	EMDECL(RTGCUINTPTR) EMGetInhibitInterruptsPC(PVM pVM)
2918	{
2919	return pVM->em.s.GCPtrInhibitInterrupts;
2920	}

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source: vbox/trunk/src/VBox/VMM/VMMAll/EMAll.cpp@ 12305

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