EMAll.cpp@ 14411

Last change on this file since 14411 was 14411, checked in by vboxsync, 16 years ago
RDTSCP support added. Enabled only for AMD-V guests.
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1	/* $Id: EMAll.cpp 14411 2008-11-20 13:26:47Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor(/Manager) - All contexts
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_EM
26	#include <VBox/em.h>
27	#include <VBox/mm.h>
28	#include <VBox/selm.h>
29	#include <VBox/patm.h>
30	#include <VBox/csam.h>
31	#include <VBox/pgm.h>
32	#include <VBox/iom.h>
33	#include <VBox/stam.h>
34	#include "EMInternal.h"
35	#include <VBox/vm.h>
36	#include <VBox/vmm.h>
37	#include <VBox/hwaccm.h>
38	#include <VBox/tm.h>
39	#include <VBox/pdmapi.h>
40
41	#include <VBox/param.h>
42	#include <VBox/err.h>
43	#include <VBox/dis.h>
44	#include <VBox/disopcode.h>
45	#include <VBox/log.h>
46	#include <iprt/assert.h>
47	#include <iprt/asm.h>
48	#include <iprt/string.h>
49
50
51	/*******************************************************************************
52	* Defined Constants And Macros *
53	*******************************************************************************/
54	/** @def EM_ASSERT_FAULT_RETURN
55	* Safety check.
56	*
57	* Could in theory it misfire on a cross page boundary access...
58	*
59	* Currently disabled because the CSAM (+ PATM) patch monitoring occationally
60	* turns up an alias page instead of the original faulting one and annoying the
61	* heck out of anyone running a debug build. See @bugref{2609} and @bugref{1931}.
62	*/
63	#if 0
64	# define EM_ASSERT_FAULT_RETURN(expr, rc) AssertReturn(expr, rc)
65	#else
66	# define EM_ASSERT_FAULT_RETURN(expr, rc) do { } while (0)
67	#endif
68
69
70	/*******************************************************************************
71	* Internal Functions *
72	*******************************************************************************/
73	DECLINLINE(int) emInterpretInstructionCPU(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize);
74
75
76
77	/**
78	* Get the current execution manager status.
79	*
80	* @returns Current status.
81	*/
82	VMMDECL(EMSTATE) EMGetState(PVM pVM)
83	{
84	return pVM->em.s.enmState;
85	}
86
87	#ifndef IN_RC
88
89	/**
90	* Read callback for disassembly function; supports reading bytes that cross a page boundary
91	*
92	* @returns VBox status code.
93	* @param pSrc GC source pointer
94	* @param pDest HC destination pointer
95	* @param cb Number of bytes to read
96	* @param dwUserdata Callback specific user data (pCpu)
97	*
98	*/
99	DECLCALLBACK(int) EMReadBytes(RTUINTPTR pSrc, uint8_t pDest, unsigned cb, void pvUserdata)
100	{
101	DISCPUSTATE pCpu = (DISCPUSTATE )pvUserdata;
102	PVM pVM = (PVM)pCpu->apvUserData[0];
103	# ifdef IN_RING0
104	int rc = PGMPhysSimpleReadGCPtr(pVM, pDest, pSrc, cb);
105	AssertMsgRC(rc, ("PGMPhysSimpleReadGCPtr failed for pSrc=%RGv cb=%x\n", pSrc, cb));
106	# else /* IN_RING3 */
107	if (!PATMIsPatchGCAddr(pVM, pSrc))
108	{
109	int rc = PGMPhysSimpleReadGCPtr(pVM, pDest, pSrc, cb);
110	AssertRC(rc);
111	}
112	else
113	{
114	for (uint32_t i = 0; i < cb; i++)
115	{
116	uint8_t opcode;
117	if (RT_SUCCESS(PATMR3QueryOpcode(pVM, (RTGCPTR)pSrc + i, &opcode)))
118	{
119	*(pDest+i) = opcode;
120	}
121	}
122	}
123	# endif /* IN_RING3 */
124	return VINF_SUCCESS;
125	}
126
127	DECLINLINE(int) emDisCoreOne(PVM pVM, DISCPUSTATE pCpu, RTGCUINTPTR InstrGC, uint32_t pOpsize)
128	{
129	return DISCoreOneEx(InstrGC, pCpu->mode, EMReadBytes, pVM, pCpu, pOpsize);
130	}
131
132	#else /* IN_RC */
133
134	DECLINLINE(int) emDisCoreOne(PVM pVM, DISCPUSTATE pCpu, RTGCUINTPTR InstrGC, uint32_t pOpsize)
135	{
136	return DISCoreOne(pCpu, InstrGC, pOpsize);
137	}
138
139	#endif /* IN_RC */
140
141
142	/**
143	* Disassembles one instruction.
144	*
145	* @param pVM The VM handle.
146	* @param pCtxCore The context core (used for both the mode and instruction).
147	* @param pCpu Where to return the parsed instruction info.
148	* @param pcbInstr Where to return the instruction size. (optional)
149	*/
150	VMMDECL(int) EMInterpretDisasOne(PVM pVM, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, unsigned *pcbInstr)
151	{
152	RTGCPTR GCPtrInstr;
153	int rc = SELMToFlatEx(pVM, DIS_SELREG_CS, pCtxCore, pCtxCore->rip, 0, &GCPtrInstr);
154	if (RT_FAILURE(rc))
155	{
156	Log(("EMInterpretDisasOne: Failed to convert %RTsel:%RGv (cpl=%d) - rc=%Rrc !!\n",
157	pCtxCore->cs, (RTGCPTR)pCtxCore->rip, pCtxCore->ss & X86_SEL_RPL, rc));
158	return rc;
159	}
160	return EMInterpretDisasOneEx(pVM, (RTGCUINTPTR)GCPtrInstr, pCtxCore, pCpu, pcbInstr);
161	}
162
163
164	/**
165	* Disassembles one instruction.
166	*
167	* This is used by internally by the interpreter and by trap/access handlers.
168	*
169	* @param pVM The VM handle.
170	* @param GCPtrInstr The flat address of the instruction.
171	* @param pCtxCore The context core (used to determin the cpu mode).
172	* @param pCpu Where to return the parsed instruction info.
173	* @param pcbInstr Where to return the instruction size. (optional)
174	*/
175	VMMDECL(int) EMInterpretDisasOneEx(PVM pVM, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, unsigned *pcbInstr)
176	{
177	int rc = DISCoreOneEx(GCPtrInstr, SELMGetCpuModeFromSelector(pVM, pCtxCore->eflags, pCtxCore->cs, (PCPUMSELREGHID)&pCtxCore->csHid),
178	#ifdef IN_RC
179	NULL, NULL,
180	#else
181	EMReadBytes, pVM,
182	#endif
183	pCpu, pcbInstr);
184	if (RT_SUCCESS(rc))
185	return VINF_SUCCESS;
186	AssertMsgFailed(("DISCoreOne failed to GCPtrInstr=%RGv rc=%Rrc\n", GCPtrInstr, rc));
187	return VERR_INTERNAL_ERROR;
188	}
189
190
191	/**
192	* Interprets the current instruction.
193	*
194	* @returns VBox status code.
195	* @retval VINF_* Scheduling instructions.
196	* @retval VERR_EM_INTERPRETER Something we can't cope with.
197	* @retval VERR_* Fatal errors.
198	*
199	* @param pVM The VM handle.
200	* @param pRegFrame The register frame.
201	* Updates the EIP if an instruction was executed successfully.
202	* @param pvFault The fault address (CR2).
203	* @param pcbSize Size of the write (if applicable).
204	*
205	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
206	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
207	* to worry about e.g. invalid modrm combinations (!)
208	*/
209	VMMDECL(int) EMInterpretInstruction(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
210	{
211	RTGCPTR pbCode;
212
213	LogFlow(("EMInterpretInstruction %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
214	int rc = SELMToFlatEx(pVM, DIS_SELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
215	if (RT_SUCCESS(rc))
216	{
217	uint32_t cbOp;
218	DISCPUSTATE Cpu;
219	Cpu.mode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
220	rc = emDisCoreOne(pVM, &Cpu, (RTGCUINTPTR)pbCode, &cbOp);
221	if (RT_SUCCESS(rc))
222	{
223	Assert(cbOp == Cpu.opsize);
224	rc = EMInterpretInstructionCPU(pVM, &Cpu, pRegFrame, pvFault, pcbSize);
225	if (RT_SUCCESS(rc))
226	{
227	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
228	}
229	return rc;
230	}
231	}
232	return VERR_EM_INTERPRETER;
233	}
234
235
236	/**
237	* Interprets the current instruction using the supplied DISCPUSTATE structure.
238	*
239	* EIP is NOT updated!
240	*
241	* @returns VBox status code.
242	* @retval VINF_* Scheduling instructions. When these are returned, it
243	* starts to get a bit tricky to know whether code was
244	* executed or not... We'll address this when it becomes a problem.
245	* @retval VERR_EM_INTERPRETER Something we can't cope with.
246	* @retval VERR_* Fatal errors.
247	*
248	* @param pVM The VM handle.
249	* @param pCpu The disassembler cpu state for the instruction to be interpreted.
250	* @param pRegFrame The register frame. EIP is NOT changed!
251	* @param pvFault The fault address (CR2).
252	* @param pcbSize Size of the write (if applicable).
253	*
254	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
255	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
256	* to worry about e.g. invalid modrm combinations (!)
257	*
258	* @todo At this time we do NOT check if the instruction overwrites vital information.
259	* Make sure this can't happen!! (will add some assertions/checks later)
260	*/
261	VMMDECL(int) EMInterpretInstructionCPU(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
262	{
263	STAM_PROFILE_START(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Emulate), a);
264	int rc = emInterpretInstructionCPU(pVM, pCpu, pRegFrame, pvFault, pcbSize);
265	STAM_PROFILE_STOP(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Emulate), a);
266	if (RT_SUCCESS(rc))
267	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InterpretSucceeded));
268	else
269	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InterpretFailed));
270	return rc;
271	}
272
273
274	/**
275	* Interpret a port I/O instruction.
276	*
277	* @returns VBox status code suitable for scheduling.
278	* @param pVM The VM handle.
279	* @param pCtxCore The context core. This will be updated on successful return.
280	* @param pCpu The instruction to interpret.
281	* @param cbOp The size of the instruction.
282	* @remark This may raise exceptions.
283	*/
284	VMMDECL(int) EMInterpretPortIO(PVM pVM, PCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, uint32_t cbOp)
285	{
286	/*
287	* Hand it on to IOM.
288	*/
289	#ifdef IN_RC
290	int rc = IOMGCIOPortHandler(pVM, pCtxCore, pCpu);
291	if (IOM_SUCCESS(rc))
292	pCtxCore->rip += cbOp;
293	return rc;
294	#else
295	AssertReleaseMsgFailed(("not implemented\n"));
296	return VERR_NOT_IMPLEMENTED;
297	#endif
298	}
299
300
301	DECLINLINE(int) emRamRead(PVM pVM, void *pDest, RTGCPTR GCSrc, uint32_t cb)
302	{
303	#ifdef IN_RC
304	int rc = MMGCRamRead(pVM, pDest, (void *)GCSrc, cb);
305	if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
306	return rc;
307	/*
308	* The page pool cache may end up here in some cases because it
309	* flushed one of the shadow mappings used by the trapping
310	* instruction and it either flushed the TLB or the CPU reused it.
311	*/
312	RTGCPHYS GCPhys;
313	rc = PGMPhysGCPtr2GCPhys(pVM, GCSrc, &GCPhys);
314	AssertRCReturn(rc, rc);
315	PGMPhysRead(pVM, GCPhys, pDest, cb);
316	return VINF_SUCCESS;
317	#else
318	return PGMPhysReadGCPtr(pVM, pDest, GCSrc, cb);
319	#endif
320	}
321
322
323	DECLINLINE(int) emRamWrite(PVM pVM, RTGCPTR GCDest, void *pSrc, uint32_t cb)
324	{
325	#ifdef IN_RC
326	int rc = MMGCRamWrite(pVM, (void *)GCDest, pSrc, cb);
327	if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
328	return rc;
329	/*
330	* The page pool cache may end up here in some cases because it
331	* flushed one of the shadow mappings used by the trapping
332	* instruction and it either flushed the TLB or the CPU reused it.
333	* We want to play safe here, verifying that we've got write
334	* access doesn't cost us much (see PGMPhysGCPtr2GCPhys()).
335	*/
336	uint64_t fFlags;
337	RTGCPHYS GCPhys;
338	rc = PGMGstGetPage(pVM, GCDest, &fFlags, &GCPhys);
339	if (RT_FAILURE(rc))
340	return rc;
341	if ( !(fFlags & X86_PTE_RW)
342	&& (CPUMGetGuestCR0(pVM) & X86_CR0_WP))
343	return VERR_ACCESS_DENIED;
344
345	PGMPhysWrite(pVM, GCPhys + ((RTGCUINTPTR)GCDest & PAGE_OFFSET_MASK), pSrc, cb);
346	return VINF_SUCCESS;
347
348	#else
349	return PGMPhysWriteGCPtr(pVM, GCDest, pSrc, cb);
350	#endif
351	}
352
353
354	/* Convert sel:addr to a flat GC address */
355	static RTGCPTR emConvertToFlatAddr(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, POP_PARAMETER pParam, RTGCPTR pvAddr)
356	{
357	DIS_SELREG enmPrefixSeg = DISDetectSegReg(pCpu, pParam);
358	return SELMToFlat(pVM, enmPrefixSeg, pRegFrame, pvAddr);
359	}
360
361
362	#if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
363	/**
364	* Get the mnemonic for the disassembled instruction.
365	*
366	* GC/R0 doesn't include the strings in the DIS tables because
367	* of limited space.
368	*/
369	static const char *emGetMnemonic(PDISCPUSTATE pCpu)
370	{
371	switch (pCpu->pCurInstr->opcode)
372	{
373	case OP_XCHG: return "Xchg";
374	case OP_DEC: return "Dec";
375	case OP_INC: return "Inc";
376	case OP_POP: return "Pop";
377	case OP_OR: return "Or";
378	case OP_AND: return "And";
379	case OP_MOV: return "Mov";
380	case OP_INVLPG: return "InvlPg";
381	case OP_CPUID: return "CpuId";
382	case OP_MOV_CR: return "MovCRx";
383	case OP_MOV_DR: return "MovDRx";
384	case OP_LLDT: return "LLdt";
385	case OP_LGDT: return "LGdt";
386	case OP_LIDT: return "LGdt";
387	case OP_CLTS: return "Clts";
388	case OP_MONITOR: return "Monitor";
389	case OP_MWAIT: return "MWait";
390	case OP_RDMSR: return "Rdmsr";
391	case OP_WRMSR: return "Wrmsr";
392	case OP_ADD: return "Add";
393	case OP_ADC: return "Adc";
394	case OP_SUB: return "Sub";
395	case OP_SBB: return "Sbb";
396	case OP_RDTSC: return "Rdtsc";
397	case OP_STI: return "Sti";
398	case OP_XADD: return "XAdd";
399	case OP_HLT: return "Hlt";
400	case OP_IRET: return "Iret";
401	case OP_MOVNTPS: return "MovNTPS";
402	case OP_STOSWD: return "StosWD";
403	case OP_WBINVD: return "WbInvd";
404	case OP_XOR: return "Xor";
405	case OP_BTR: return "Btr";
406	case OP_BTS: return "Bts";
407	case OP_BTC: return "Btc";
408	case OP_LMSW: return "Lmsw";
409	case OP_CMPXCHG: return pCpu->prefix & PREFIX_LOCK ? "Lock CmpXchg" : "CmpXchg";
410	case OP_CMPXCHG8B: return pCpu->prefix & PREFIX_LOCK ? "Lock CmpXchg8b" : "CmpXchg8b";
411
412	default:
413	Log(("Unknown opcode %d\n", pCpu->pCurInstr->opcode));
414	return "???";
415	}
416	}
417	#endif /* VBOX_STRICT \|\| LOG_ENABLED */
418
419
420	/**
421	* XCHG instruction emulation.
422	*/
423	static int emInterpretXchg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
424	{
425	OP_PARAMVAL param1, param2;
426
427	/* Source to make DISQueryParamVal read the register value - ugly hack */
428	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
429	if(RT_FAILURE(rc))
430	return VERR_EM_INTERPRETER;
431
432	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
433	if(RT_FAILURE(rc))
434	return VERR_EM_INTERPRETER;
435
436	#ifdef IN_RC
437	if (TRPMHasTrap(pVM))
438	{
439	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
440	{
441	#endif
442	RTGCPTR pParam1 = 0, pParam2 = 0;
443	uint64_t valpar1, valpar2;
444
445	AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
446	switch(param1.type)
447	{
448	case PARMTYPE_IMMEDIATE: /* register type is translated to this one too */
449	valpar1 = param1.val.val64;
450	break;
451
452	case PARMTYPE_ADDRESS:
453	pParam1 = (RTGCPTR)param1.val.val64;
454	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
455	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
456	rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
457	if (RT_FAILURE(rc))
458	{
459	AssertMsgFailed(("MMGCRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
460	return VERR_EM_INTERPRETER;
461	}
462	break;
463
464	default:
465	AssertFailed();
466	return VERR_EM_INTERPRETER;
467	}
468
469	switch(param2.type)
470	{
471	case PARMTYPE_ADDRESS:
472	pParam2 = (RTGCPTR)param2.val.val64;
473	pParam2 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param2, pParam2);
474	EM_ASSERT_FAULT_RETURN(pParam2 == pvFault, VERR_EM_INTERPRETER);
475	rc = emRamRead(pVM, &valpar2, pParam2, param2.size);
476	if (RT_FAILURE(rc))
477	{
478	AssertMsgFailed(("MMGCRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
479	}
480	break;
481
482	case PARMTYPE_IMMEDIATE:
483	valpar2 = param2.val.val64;
484	break;
485
486	default:
487	AssertFailed();
488	return VERR_EM_INTERPRETER;
489	}
490
491	/* Write value of parameter 2 to parameter 1 (reg or memory address) */
492	if (pParam1 == 0)
493	{
494	Assert(param1.type == PARMTYPE_IMMEDIATE); /* register actually */
495	switch(param1.size)
496	{
497	case 1: //special case for AH etc
498	rc = DISWriteReg8(pRegFrame, pCpu->param1.base.reg_gen, (uint8_t )valpar2); break;
499	case 2: rc = DISWriteReg16(pRegFrame, pCpu->param1.base.reg_gen, (uint16_t)valpar2); break;
500	case 4: rc = DISWriteReg32(pRegFrame, pCpu->param1.base.reg_gen, (uint32_t)valpar2); break;
501	case 8: rc = DISWriteReg64(pRegFrame, pCpu->param1.base.reg_gen, valpar2); break;
502	default: AssertFailedReturn(VERR_EM_INTERPRETER);
503	}
504	if (RT_FAILURE(rc))
505	return VERR_EM_INTERPRETER;
506	}
507	else
508	{
509	rc = emRamWrite(pVM, pParam1, &valpar2, param1.size);
510	if (RT_FAILURE(rc))
511	{
512	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
513	return VERR_EM_INTERPRETER;
514	}
515	}
516
517	/* Write value of parameter 1 to parameter 2 (reg or memory address) */
518	if (pParam2 == 0)
519	{
520	Assert(param2.type == PARMTYPE_IMMEDIATE); /* register actually */
521	switch(param2.size)
522	{
523	case 1: //special case for AH etc
524	rc = DISWriteReg8(pRegFrame, pCpu->param2.base.reg_gen, (uint8_t )valpar1); break;
525	case 2: rc = DISWriteReg16(pRegFrame, pCpu->param2.base.reg_gen, (uint16_t)valpar1); break;
526	case 4: rc = DISWriteReg32(pRegFrame, pCpu->param2.base.reg_gen, (uint32_t)valpar1); break;
527	case 8: rc = DISWriteReg64(pRegFrame, pCpu->param2.base.reg_gen, valpar1); break;
528	default: AssertFailedReturn(VERR_EM_INTERPRETER);
529	}
530	if (RT_FAILURE(rc))
531	return VERR_EM_INTERPRETER;
532	}
533	else
534	{
535	rc = emRamWrite(pVM, pParam2, &valpar1, param2.size);
536	if (RT_FAILURE(rc))
537	{
538	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
539	return VERR_EM_INTERPRETER;
540	}
541	}
542
543	*pcbSize = param2.size;
544	return VINF_SUCCESS;
545	#ifdef IN_RC
546	}
547	}
548	#endif
549	return VERR_EM_INTERPRETER;
550	}
551
552
553	/**
554	* INC and DEC emulation.
555	*/
556	static int emInterpretIncDec(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
557	PFNEMULATEPARAM2 pfnEmulate)
558	{
559	OP_PARAMVAL param1;
560
561	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
562	if(RT_FAILURE(rc))
563	return VERR_EM_INTERPRETER;
564
565	#ifdef IN_RC
566	if (TRPMHasTrap(pVM))
567	{
568	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
569	{
570	#endif
571	RTGCPTR pParam1 = 0;
572	uint64_t valpar1;
573
574	if (param1.type == PARMTYPE_ADDRESS)
575	{
576	pParam1 = (RTGCPTR)param1.val.val64;
577	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
578	#ifdef IN_RC
579	/* Safety check (in theory it could cross a page boundary and fault there though) */
580	AssertReturn(pParam1 == pvFault, VERR_EM_INTERPRETER);
581	#endif
582	rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
583	if (RT_FAILURE(rc))
584	{
585	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
586	return VERR_EM_INTERPRETER;
587	}
588	}
589	else
590	{
591	AssertFailed();
592	return VERR_EM_INTERPRETER;
593	}
594
595	uint32_t eflags;
596
597	eflags = pfnEmulate(&valpar1, param1.size);
598
599	/* Write result back */
600	rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
601	if (RT_FAILURE(rc))
602	{
603	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
604	return VERR_EM_INTERPRETER;
605	}
606
607	/* Update guest's eflags and finish. */
608	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
609	\| (eflags & (X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
610
611	/* All done! */
612	*pcbSize = param1.size;
613	return VINF_SUCCESS;
614	#ifdef IN_RC
615	}
616	}
617	#endif
618	return VERR_EM_INTERPRETER;
619	}
620
621
622	/**
623	* POP Emulation.
624	*/
625	static int emInterpretPop(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
626	{
627	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
628	OP_PARAMVAL param1;
629	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
630	if(RT_FAILURE(rc))
631	return VERR_EM_INTERPRETER;
632
633	#ifdef IN_RC
634	if (TRPMHasTrap(pVM))
635	{
636	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
637	{
638	#endif
639	RTGCPTR pParam1 = 0;
640	uint32_t valpar1;
641	RTGCPTR pStackVal;
642
643	/* Read stack value first */
644	if (SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->ss, &pRegFrame->ssHid) == CPUMODE_16BIT)
645	return VERR_EM_INTERPRETER; /* No legacy 16 bits stuff here, please. */
646
647	/* Convert address; don't bother checking limits etc, as we only read here */
648	pStackVal = SELMToFlat(pVM, DIS_SELREG_SS, pRegFrame, (RTGCPTR)pRegFrame->esp);
649	if (pStackVal == 0)
650	return VERR_EM_INTERPRETER;
651
652	rc = emRamRead(pVM, &valpar1, pStackVal, param1.size);
653	if (RT_FAILURE(rc))
654	{
655	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
656	return VERR_EM_INTERPRETER;
657	}
658
659	if (param1.type == PARMTYPE_ADDRESS)
660	{
661	pParam1 = (RTGCPTR)param1.val.val64;
662
663	/* pop [esp+xx] uses esp after the actual pop! */
664	AssertCompile(USE_REG_ESP == USE_REG_SP);
665	if ( (pCpu->param1.flags & USE_BASE)
666	&& (pCpu->param1.flags & (USE_REG_GEN16\|USE_REG_GEN32))
667	&& pCpu->param1.base.reg_gen == USE_REG_ESP
668	)
669	pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + param1.size);
670
671	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
672	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault \|\| (RTGCPTR)pRegFrame->esp == pvFault, VERR_EM_INTERPRETER);
673	rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
674	if (RT_FAILURE(rc))
675	{
676	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
677	return VERR_EM_INTERPRETER;
678	}
679
680	/* Update ESP as the last step */
681	pRegFrame->esp += param1.size;
682	}
683	else
684	{
685	#ifndef DEBUG_bird // annoying assertion.
686	AssertFailed();
687	#endif
688	return VERR_EM_INTERPRETER;
689	}
690
691	/* All done! */
692	*pcbSize = param1.size;
693	return VINF_SUCCESS;
694	#ifdef IN_RC
695	}
696	}
697	#endif
698	return VERR_EM_INTERPRETER;
699	}
700
701
702	/**
703	* XOR/OR/AND Emulation.
704	*/
705	static int emInterpretOrXorAnd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
706	PFNEMULATEPARAM3 pfnEmulate)
707	{
708	OP_PARAMVAL param1, param2;
709	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
710	if(RT_FAILURE(rc))
711	return VERR_EM_INTERPRETER;
712
713	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
714	if(RT_FAILURE(rc))
715	return VERR_EM_INTERPRETER;
716
717	#ifdef IN_RC
718	if (TRPMHasTrap(pVM))
719	{
720	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
721	{
722	#endif
723	RTGCPTR pParam1;
724	uint64_t valpar1, valpar2;
725
726	if (pCpu->param1.size != pCpu->param2.size)
727	{
728	if (pCpu->param1.size < pCpu->param2.size)
729	{
730	AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pCpu), (RTGCPTR)pRegFrame->rip, pCpu->param1.size, pCpu->param2.size)); /* should never happen! */
731	return VERR_EM_INTERPRETER;
732	}
733	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
734	pCpu->param2.size = pCpu->param1.size;
735	param2.size = param1.size;
736	}
737
738	/* The destination is always a virtual address */
739	if (param1.type == PARMTYPE_ADDRESS)
740	{
741	pParam1 = (RTGCPTR)param1.val.val64;
742	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
743	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
744	rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
745	if (RT_FAILURE(rc))
746	{
747	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
748	return VERR_EM_INTERPRETER;
749	}
750	}
751	else
752	{
753	AssertFailed();
754	return VERR_EM_INTERPRETER;
755	}
756
757	/* Register or immediate data */
758	switch(param2.type)
759	{
760	case PARMTYPE_IMMEDIATE: /* both immediate data and register (ugly) */
761	valpar2 = param2.val.val64;
762	break;
763
764	default:
765	AssertFailed();
766	return VERR_EM_INTERPRETER;
767	}
768
769	LogFlow(("emInterpretOrXorAnd %s %RGv %RX64 - %RX64 size %d (%d)\n", emGetMnemonic(pCpu), pParam1, valpar1, valpar2, param2.size, param1.size));
770
771	/* Data read, emulate instruction. */
772	uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
773
774	LogFlow(("emInterpretOrXorAnd %s result %RX64\n", emGetMnemonic(pCpu), valpar1));
775
776	/* Update guest's eflags and finish. */
777	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
778	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
779
780	/* And write it back */
781	rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
782	if (RT_SUCCESS(rc))
783	{
784	/* All done! */
785	*pcbSize = param2.size;
786	return VINF_SUCCESS;
787	}
788	#ifdef IN_RC
789	}
790	}
791	#endif
792	return VERR_EM_INTERPRETER;
793	}
794
795
796	/**
797	* LOCK XOR/OR/AND Emulation.
798	*/
799	static int emInterpretLockOrXorAnd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
800	uint32_t *pcbSize, PFNEMULATELOCKPARAM3 pfnEmulate)
801	{
802	void *pvParam1;
803
804	OP_PARAMVAL param1, param2;
805	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
806	if(RT_FAILURE(rc))
807	return VERR_EM_INTERPRETER;
808
809	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
810	if(RT_FAILURE(rc))
811	return VERR_EM_INTERPRETER;
812
813	if (pCpu->param1.size != pCpu->param2.size)
814	{
815	AssertMsgReturn(pCpu->param1.size >= pCpu->param2.size, /* should never happen! */
816	("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pCpu), (RTGCPTR)pRegFrame->rip, pCpu->param1.size, pCpu->param2.size),
817	VERR_EM_INTERPRETER);
818
819	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
820	pCpu->param2.size = pCpu->param1.size;
821	param2.size = param1.size;
822	}
823
824	/* The destination is always a virtual address */
825	AssertReturn(param1.type == PARMTYPE_ADDRESS, VERR_EM_INTERPRETER);
826
827	RTGCPTR GCPtrPar1 = param1.val.val64;
828	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
829	#ifdef IN_RC
830	pvParam1 = (void *)GCPtrPar1;
831	#else
832	rc = PGMPhysGCPtr2HCPtr(pVM, GCPtrPar1, &pvParam1);
833	if (RT_FAILURE(rc))
834	{
835	AssertRC(rc);
836	return VERR_EM_INTERPRETER;
837	}
838	#endif
839
840	#ifdef IN_RC
841	/* Safety check (in theory it could cross a page boundary and fault there though) */
842	Assert( TRPMHasTrap(pVM)
843	&& (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW));
844	EM_ASSERT_FAULT_RETURN(GCPtrPar1 == pvFault, VERR_EM_INTERPRETER);
845	#endif
846
847	/* Register and immediate data == PARMTYPE_IMMEDIATE */
848	AssertReturn(param2.type == PARMTYPE_IMMEDIATE, VERR_EM_INTERPRETER);
849	RTGCUINTREG ValPar2 = param2.val.val64;
850
851	/* Try emulate it with a one-shot #PF handler in place. */
852	Log2(("%s %RGv imm%d=%RX64\n", emGetMnemonic(pCpu), GCPtrPar1, pCpu->param2.size*8, ValPar2));
853
854	RTGCUINTREG32 eflags = 0;
855	#ifdef IN_RC
856	MMGCRamRegisterTrapHandler(pVM);
857	#endif
858	rc = pfnEmulate(pvParam1, ValPar2, pCpu->param2.size, &eflags);
859	#ifdef IN_RC
860	MMGCRamDeregisterTrapHandler(pVM);
861	#endif
862	if (RT_FAILURE(rc))
863	{
864	Log(("%s %RGv imm%d=%RX64-> emulation failed due to page fault!\n", emGetMnemonic(pCpu), GCPtrPar1, pCpu->param2.size*8, ValPar2));
865	return VERR_EM_INTERPRETER;
866	}
867
868	/* Update guest's eflags and finish. */
869	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
870	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
871
872	*pcbSize = param2.size;
873	return VINF_SUCCESS;
874	}
875
876
877	/**
878	* ADD, ADC & SUB Emulation.
879	*/
880	static int emInterpretAddSub(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
881	PFNEMULATEPARAM3 pfnEmulate)
882	{
883	OP_PARAMVAL param1, param2;
884	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
885	if(RT_FAILURE(rc))
886	return VERR_EM_INTERPRETER;
887
888	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
889	if(RT_FAILURE(rc))
890	return VERR_EM_INTERPRETER;
891
892	#ifdef IN_RC
893	if (TRPMHasTrap(pVM))
894	{
895	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
896	{
897	#endif
898	RTGCPTR pParam1;
899	uint64_t valpar1, valpar2;
900
901	if (pCpu->param1.size != pCpu->param2.size)
902	{
903	if (pCpu->param1.size < pCpu->param2.size)
904	{
905	AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pCpu), (RTGCPTR)pRegFrame->rip, pCpu->param1.size, pCpu->param2.size)); /* should never happen! */
906	return VERR_EM_INTERPRETER;
907	}
908	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
909	pCpu->param2.size = pCpu->param1.size;
910	param2.size = param1.size;
911	}
912
913	/* The destination is always a virtual address */
914	if (param1.type == PARMTYPE_ADDRESS)
915	{
916	pParam1 = (RTGCPTR)param1.val.val64;
917	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
918	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
919	rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
920	if (RT_FAILURE(rc))
921	{
922	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
923	return VERR_EM_INTERPRETER;
924	}
925	}
926	else
927	{
928	#ifndef DEBUG_bird
929	AssertFailed();
930	#endif
931	return VERR_EM_INTERPRETER;
932	}
933
934	/* Register or immediate data */
935	switch(param2.type)
936	{
937	case PARMTYPE_IMMEDIATE: /* both immediate data and register (ugly) */
938	valpar2 = param2.val.val64;
939	break;
940
941	default:
942	AssertFailed();
943	return VERR_EM_INTERPRETER;
944	}
945
946	/* Data read, emulate instruction. */
947	uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
948
949	/* Update guest's eflags and finish. */
950	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
951	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
952
953	/* And write it back */
954	rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
955	if (RT_SUCCESS(rc))
956	{
957	/* All done! */
958	*pcbSize = param2.size;
959	return VINF_SUCCESS;
960	}
961	#ifdef IN_RC
962	}
963	}
964	#endif
965	return VERR_EM_INTERPRETER;
966	}
967
968
969	/**
970	* ADC Emulation.
971	*/
972	static int emInterpretAdc(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
973	{
974	if (pRegFrame->eflags.Bits.u1CF)
975	return emInterpretAddSub(pVM, pCpu, pRegFrame, pvFault, pcbSize, EMEmulateAdcWithCarrySet);
976	else
977	return emInterpretAddSub(pVM, pCpu, pRegFrame, pvFault, pcbSize, EMEmulateAdd);
978	}
979
980
981	/**
982	* BTR/C/S Emulation.
983	*/
984	static int emInterpretBitTest(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
985	PFNEMULATEPARAM2UINT32 pfnEmulate)
986	{
987	OP_PARAMVAL param1, param2;
988	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
989	if(RT_FAILURE(rc))
990	return VERR_EM_INTERPRETER;
991
992	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
993	if(RT_FAILURE(rc))
994	return VERR_EM_INTERPRETER;
995
996	#ifdef IN_RC
997	if (TRPMHasTrap(pVM))
998	{
999	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1000	{
1001	#endif
1002	RTGCPTR pParam1;
1003	uint64_t valpar1 = 0, valpar2;
1004	uint32_t eflags;
1005
1006	/* The destination is always a virtual address */
1007	if (param1.type != PARMTYPE_ADDRESS)
1008	return VERR_EM_INTERPRETER;
1009
1010	pParam1 = (RTGCPTR)param1.val.val64;
1011	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
1012
1013	/* Register or immediate data */
1014	switch(param2.type)
1015	{
1016	case PARMTYPE_IMMEDIATE: /* both immediate data and register (ugly) */
1017	valpar2 = param2.val.val64;
1018	break;
1019
1020	default:
1021	AssertFailed();
1022	return VERR_EM_INTERPRETER;
1023	}
1024
1025	Log2(("emInterpret%s: pvFault=%RGv pParam1=%RGv val2=%x\n", emGetMnemonic(pCpu), pvFault, pParam1, valpar2));
1026	pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + valpar2/8);
1027	EM_ASSERT_FAULT_RETURN((RTGCPTR)((RTGCUINTPTR)pParam1 & ~3) == pvFault, VERR_EM_INTERPRETER);
1028	rc = emRamRead(pVM, &valpar1, pParam1, 1);
1029	if (RT_FAILURE(rc))
1030	{
1031	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
1032	return VERR_EM_INTERPRETER;
1033	}
1034
1035	Log2(("emInterpretBtx: val=%x\n", valpar1));
1036	/* Data read, emulate bit test instruction. */
1037	eflags = pfnEmulate(&valpar1, valpar2 & 0x7);
1038
1039	Log2(("emInterpretBtx: val=%x CF=%d\n", valpar1, !!(eflags & X86_EFL_CF)));
1040
1041	/* Update guest's eflags and finish. */
1042	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1043	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1044
1045	/* And write it back */
1046	rc = emRamWrite(pVM, pParam1, &valpar1, 1);
1047	if (RT_SUCCESS(rc))
1048	{
1049	/* All done! */
1050	*pcbSize = 1;
1051	return VINF_SUCCESS;
1052	}
1053	#ifdef IN_RC
1054	}
1055	}
1056	#endif
1057	return VERR_EM_INTERPRETER;
1058	}
1059
1060
1061	/**
1062	* LOCK BTR/C/S Emulation.
1063	*/
1064	static int emInterpretLockBitTest(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
1065	uint32_t *pcbSize, PFNEMULATELOCKPARAM2 pfnEmulate)
1066	{
1067	void *pvParam1;
1068
1069	OP_PARAMVAL param1, param2;
1070	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
1071	if(RT_FAILURE(rc))
1072	return VERR_EM_INTERPRETER;
1073
1074	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1075	if(RT_FAILURE(rc))
1076	return VERR_EM_INTERPRETER;
1077
1078	/* The destination is always a virtual address */
1079	if (param1.type != PARMTYPE_ADDRESS)
1080	return VERR_EM_INTERPRETER;
1081
1082	/* Register and immediate data == PARMTYPE_IMMEDIATE */
1083	AssertReturn(param2.type == PARMTYPE_IMMEDIATE, VERR_EM_INTERPRETER);
1084	uint64_t ValPar2 = param2.val.val64;
1085
1086	/* Adjust the parameters so what we're dealing with is a bit within the byte pointed to. */
1087	RTGCPTR GCPtrPar1 = param1.val.val64;
1088	GCPtrPar1 = (GCPtrPar1 + ValPar2 / 8);
1089	ValPar2 &= 7;
1090
1091	#ifdef IN_RC
1092	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
1093	pvParam1 = (void *)GCPtrPar1;
1094	#else
1095	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
1096	rc = PGMPhysGCPtr2HCPtr(pVM, GCPtrPar1, &pvParam1);
1097	if (RT_FAILURE(rc))
1098	{
1099	AssertRC(rc);
1100	return VERR_EM_INTERPRETER;
1101	}
1102	#endif
1103
1104	Log2(("emInterpretLockBitTest %s: pvFault=%RGv GCPtrPar1=%RGv imm=%RX64\n", emGetMnemonic(pCpu), pvFault, GCPtrPar1, ValPar2));
1105
1106	#ifdef IN_RC
1107	Assert(TRPMHasTrap(pVM));
1108	EM_ASSERT_FAULT_RETURN((RTGCPTR)((RTGCUINTPTR)GCPtrPar1 & ~(RTGCUINTPTR)3) == pvFault, VERR_EM_INTERPRETER);
1109	#endif
1110
1111	/* Try emulate it with a one-shot #PF handler in place. */
1112	RTGCUINTREG32 eflags = 0;
1113	#ifdef IN_RC
1114	MMGCRamRegisterTrapHandler(pVM);
1115	#endif
1116	rc = pfnEmulate(pvParam1, ValPar2, &eflags);
1117	#ifdef IN_RC
1118	MMGCRamDeregisterTrapHandler(pVM);
1119	#endif
1120	if (RT_FAILURE(rc))
1121	{
1122	Log(("emInterpretLockBitTest %s: %RGv imm%d=%RX64 -> emulation failed due to page fault!\n",
1123	emGetMnemonic(pCpu), GCPtrPar1, pCpu->param2.size*8, ValPar2));
1124	return VERR_EM_INTERPRETER;
1125	}
1126
1127	Log2(("emInterpretLockBitTest %s: GCPtrPar1=%RGv imm=%RX64 CF=%d\n", emGetMnemonic(pCpu), GCPtrPar1, ValPar2, !!(eflags & X86_EFL_CF)));
1128
1129	/* Update guest's eflags and finish. */
1130	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1131	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1132
1133	*pcbSize = 1;
1134	return VINF_SUCCESS;
1135	}
1136
1137
1138	/**
1139	* MOV emulation.
1140	*/
1141	static int emInterpretMov(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1142	{
1143	OP_PARAMVAL param1, param2;
1144	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
1145	if(RT_FAILURE(rc))
1146	return VERR_EM_INTERPRETER;
1147
1148	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1149	if(RT_FAILURE(rc))
1150	return VERR_EM_INTERPRETER;
1151
1152	#ifdef IN_RC
1153	if (TRPMHasTrap(pVM))
1154	{
1155	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1156	{
1157	#else
1158	/** @todo Make this the default and don't rely on TRPM information. */
1159	if (param1.type == PARMTYPE_ADDRESS)
1160	{
1161	#endif
1162	RTGCPTR pDest;
1163	uint64_t val64;
1164
1165	switch(param1.type)
1166	{
1167	case PARMTYPE_IMMEDIATE:
1168	if(!(param1.flags & (PARAM_VAL32\|PARAM_VAL64)))
1169	return VERR_EM_INTERPRETER;
1170	/* fallthru */
1171
1172	case PARMTYPE_ADDRESS:
1173	pDest = (RTGCPTR)param1.val.val64;
1174	pDest = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pDest);
1175	break;
1176
1177	default:
1178	AssertFailed();
1179	return VERR_EM_INTERPRETER;
1180	}
1181
1182	switch(param2.type)
1183	{
1184	case PARMTYPE_IMMEDIATE: /* register type is translated to this one too */
1185	val64 = param2.val.val64;
1186	break;
1187
1188	default:
1189	Log(("emInterpretMov: unexpected type=%d rip=%RGv\n", param2.type, (RTGCPTR)pRegFrame->rip));
1190	return VERR_EM_INTERPRETER;
1191	}
1192	#ifdef LOG_ENABLED
1193	if (pCpu->mode == CPUMODE_64BIT)
1194	LogFlow(("EMInterpretInstruction at %RGv: OP_MOV %RGv <- %RX64 (%d) &val64=%RHv\n", (RTGCPTR)pRegFrame->rip, pDest, val64, param2.size, &val64));
1195	else
1196	LogFlow(("EMInterpretInstruction at %08RX64: OP_MOV %RGv <- %08X (%d) &val64=%RHv\n", pRegFrame->rip, pDest, (uint32_t)val64, param2.size, &val64));
1197	#endif
1198
1199	Assert(param2.size <= 8 && param2.size > 0);
1200	EM_ASSERT_FAULT_RETURN(pDest == pvFault, VERR_EM_INTERPRETER);
1201	rc = emRamWrite(pVM, pDest, &val64, param2.size);
1202	if (RT_FAILURE(rc))
1203	return VERR_EM_INTERPRETER;
1204
1205	*pcbSize = param2.size;
1206	}
1207	else
1208	{ /* read fault */
1209	RTGCPTR pSrc;
1210	uint64_t val64;
1211
1212	/* Source */
1213	switch(param2.type)
1214	{
1215	case PARMTYPE_IMMEDIATE:
1216	if(!(param2.flags & (PARAM_VAL32\|PARAM_VAL64)))
1217	return VERR_EM_INTERPRETER;
1218	/* fallthru */
1219
1220	case PARMTYPE_ADDRESS:
1221	pSrc = (RTGCPTR)param2.val.val64;
1222	pSrc = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param2, pSrc);
1223	break;
1224
1225	default:
1226	return VERR_EM_INTERPRETER;
1227	}
1228
1229	Assert(param1.size <= 8 && param1.size > 0);
1230	EM_ASSERT_FAULT_RETURN(pSrc == pvFault, VERR_EM_INTERPRETER);
1231	rc = emRamRead(pVM, &val64, pSrc, param1.size);
1232	if (RT_FAILURE(rc))
1233	return VERR_EM_INTERPRETER;
1234
1235	/* Destination */
1236	switch(param1.type)
1237	{
1238	case PARMTYPE_REGISTER:
1239	switch(param1.size)
1240	{
1241	case 1: rc = DISWriteReg8(pRegFrame, pCpu->param1.base.reg_gen, (uint8_t) val64); break;
1242	case 2: rc = DISWriteReg16(pRegFrame, pCpu->param1.base.reg_gen, (uint16_t)val64); break;
1243	case 4: rc = DISWriteReg32(pRegFrame, pCpu->param1.base.reg_gen, (uint32_t)val64); break;
1244	case 8: rc = DISWriteReg64(pRegFrame, pCpu->param1.base.reg_gen, val64); break;
1245	default:
1246	return VERR_EM_INTERPRETER;
1247	}
1248	if (RT_FAILURE(rc))
1249	return rc;
1250	break;
1251
1252	default:
1253	return VERR_EM_INTERPRETER;
1254	}
1255	#ifdef LOG_ENABLED
1256	if (pCpu->mode == CPUMODE_64BIT)
1257	LogFlow(("EMInterpretInstruction: OP_MOV %RGv -> %RX64 (%d)\n", pSrc, val64, param1.size));
1258	else
1259	LogFlow(("EMInterpretInstruction: OP_MOV %RGv -> %08X (%d)\n", pSrc, (uint32_t)val64, param1.size));
1260	#endif
1261	}
1262	return VINF_SUCCESS;
1263	#ifdef IN_RC
1264	}
1265	#endif
1266	return VERR_EM_INTERPRETER;
1267	}
1268
1269
1270	#ifndef IN_RC
1271	/**
1272	* [REP] STOSWD emulation
1273	*/
1274	static int emInterpretStosWD(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1275	{
1276	int rc;
1277	RTGCPTR GCDest, GCOffset;
1278	uint32_t cbSize;
1279	uint64_t cTransfers;
1280	int offIncrement;
1281
1282	/* Don't support any but these three prefix bytes. */
1283	if ((pCpu->prefix & ~(PREFIX_ADDRSIZE\|PREFIX_OPSIZE\|PREFIX_REP\|PREFIX_REX)))
1284	return VERR_EM_INTERPRETER;
1285
1286	switch (pCpu->addrmode)
1287	{
1288	case CPUMODE_16BIT:
1289	GCOffset = pRegFrame->di;
1290	cTransfers = pRegFrame->cx;
1291	break;
1292	case CPUMODE_32BIT:
1293	GCOffset = pRegFrame->edi;
1294	cTransfers = pRegFrame->ecx;
1295	break;
1296	case CPUMODE_64BIT:
1297	GCOffset = pRegFrame->rdi;
1298	cTransfers = pRegFrame->rcx;
1299	break;
1300	default:
1301	AssertFailed();
1302	return VERR_EM_INTERPRETER;
1303	}
1304
1305	GCDest = SELMToFlat(pVM, DIS_SELREG_ES, pRegFrame, GCOffset);
1306	switch (pCpu->opmode)
1307	{
1308	case CPUMODE_16BIT:
1309	cbSize = 2;
1310	break;
1311	case CPUMODE_32BIT:
1312	cbSize = 4;
1313	break;
1314	case CPUMODE_64BIT:
1315	cbSize = 8;
1316	break;
1317	default:
1318	AssertFailed();
1319	return VERR_EM_INTERPRETER;
1320	}
1321
1322	offIncrement = pRegFrame->eflags.Bits.u1DF ? -(signed)cbSize : (signed)cbSize;
1323
1324	if (!(pCpu->prefix & PREFIX_REP))
1325	{
1326	LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d\n", pRegFrame->es, GCOffset, GCDest, cbSize));
1327
1328	rc = PGMPhysWriteGCPtr(pVM, GCDest, &pRegFrame->rax, cbSize);
1329	if (RT_FAILURE(rc))
1330	return VERR_EM_INTERPRETER;
1331	Assert(rc == VINF_SUCCESS);
1332
1333	/* Update (e/r)di. */
1334	switch (pCpu->addrmode)
1335	{
1336	case CPUMODE_16BIT:
1337	pRegFrame->di += offIncrement;
1338	break;
1339	case CPUMODE_32BIT:
1340	pRegFrame->edi += offIncrement;
1341	break;
1342	case CPUMODE_64BIT:
1343	pRegFrame->rdi += offIncrement;
1344	break;
1345	default:
1346	AssertFailed();
1347	return VERR_EM_INTERPRETER;
1348	}
1349
1350	}
1351	else
1352	{
1353	if (!cTransfers)
1354	return VINF_SUCCESS;
1355
1356	LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d cTransfers=%x DF=%d\n", pRegFrame->es, GCOffset, GCDest, cbSize, cTransfers, pRegFrame->eflags.Bits.u1DF));
1357
1358	/* Access verification first; we currently can't recover properly from traps inside this instruction */
1359	rc = PGMVerifyAccess(pVM, GCDest - (offIncrement > 0) ? 0 : ((cTransfers-1) * cbSize), cTransfers * cbSize, X86_PTE_RW \| X86_PTE_US);
1360	if (rc != VINF_SUCCESS)
1361	{
1362	Log(("STOSWD will generate a trap -> recompiler, rc=%d\n", rc));
1363	return VERR_EM_INTERPRETER;
1364	}
1365
1366	/* REP case */
1367	while (cTransfers)
1368	{
1369	rc = PGMPhysWriteGCPtr(pVM, GCDest, &pRegFrame->rax, cbSize);
1370	if (RT_FAILURE(rc))
1371	{
1372	rc = VERR_EM_INTERPRETER;
1373	break;
1374	}
1375
1376	Assert(rc == VINF_SUCCESS);
1377	GCOffset += offIncrement;
1378	GCDest += offIncrement;
1379	cTransfers--;
1380	}
1381
1382	/* Update the registers. */
1383	switch (pCpu->addrmode)
1384	{
1385	case CPUMODE_16BIT:
1386	pRegFrame->di = GCOffset;
1387	pRegFrame->cx = cTransfers;
1388	break;
1389	case CPUMODE_32BIT:
1390	pRegFrame->edi = GCOffset;
1391	pRegFrame->ecx = cTransfers;
1392	break;
1393	case CPUMODE_64BIT:
1394	pRegFrame->rdi = GCOffset;
1395	pRegFrame->rcx = cTransfers;
1396	break;
1397	default:
1398	AssertFailed();
1399	return VERR_EM_INTERPRETER;
1400	}
1401	}
1402
1403	*pcbSize = cbSize;
1404	return rc;
1405	}
1406	#endif /* !IN_RC */
1407
1408	#ifndef IN_RC
1409
1410	/**
1411	* [LOCK] CMPXCHG emulation.
1412	*/
1413	static int emInterpretCmpXchg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1414	{
1415	OP_PARAMVAL param1, param2;
1416
1417	/* Source to make DISQueryParamVal read the register value - ugly hack */
1418	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1419	if(RT_FAILURE(rc))
1420	return VERR_EM_INTERPRETER;
1421
1422	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1423	if(RT_FAILURE(rc))
1424	return VERR_EM_INTERPRETER;
1425
1426	RTGCPTR GCPtrPar1;
1427	void *pvParam1;
1428	uint64_t valpar, eflags;
1429
1430	AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
1431	switch(param1.type)
1432	{
1433	case PARMTYPE_ADDRESS:
1434	GCPtrPar1 = param1.val.val64;
1435	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
1436
1437	rc = PGMPhysGCPtr2HCPtr(pVM, GCPtrPar1, &pvParam1);
1438	if (RT_FAILURE(rc))
1439	{
1440	AssertRC(rc);
1441	return VERR_EM_INTERPRETER;
1442	}
1443	break;
1444
1445	default:
1446	return VERR_EM_INTERPRETER;
1447	}
1448
1449	switch(param2.type)
1450	{
1451	case PARMTYPE_IMMEDIATE: /* register actually */
1452	valpar = param2.val.val64;
1453	break;
1454
1455	default:
1456	return VERR_EM_INTERPRETER;
1457	}
1458
1459	LogFlow(("%s %RGv rax=%RX64 %RX64\n", emGetMnemonic(pCpu), GCPtrPar1, pRegFrame->rax, valpar));
1460
1461	if (pCpu->prefix & PREFIX_LOCK)
1462	eflags = EMEmulateLockCmpXchg(pvParam1, &pRegFrame->rax, valpar, pCpu->param2.size);
1463	else
1464	eflags = EMEmulateCmpXchg(pvParam1, &pRegFrame->rax, valpar, pCpu->param2.size);
1465
1466	LogFlow(("%s %RGv rax=%RX64 %RX64 ZF=%d\n", emGetMnemonic(pCpu), GCPtrPar1, pRegFrame->rax, valpar, !!(eflags & X86_EFL_ZF)));
1467
1468	/* Update guest's eflags and finish. */
1469	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1470	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1471
1472	*pcbSize = param2.size;
1473	return VINF_SUCCESS;
1474	}
1475
1476
1477	/**
1478	* [LOCK] CMPXCHG8B emulation.
1479	*/
1480	static int emInterpretCmpXchg8b(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1481	{
1482	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
1483	OP_PARAMVAL param1;
1484
1485	/* Source to make DISQueryParamVal read the register value - ugly hack */
1486	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1487	if(RT_FAILURE(rc))
1488	return VERR_EM_INTERPRETER;
1489
1490	RTGCPTR GCPtrPar1;
1491	void *pvParam1;
1492	uint64_t eflags;
1493
1494	AssertReturn(pCpu->param1.size == 8, VERR_EM_INTERPRETER);
1495	switch(param1.type)
1496	{
1497	case PARMTYPE_ADDRESS:
1498	GCPtrPar1 = param1.val.val64;
1499	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
1500
1501	rc = PGMPhysGCPtr2HCPtr(pVM, GCPtrPar1, &pvParam1);
1502	if (RT_FAILURE(rc))
1503	{
1504	AssertRC(rc);
1505	return VERR_EM_INTERPRETER;
1506	}
1507	break;
1508
1509	default:
1510	return VERR_EM_INTERPRETER;
1511	}
1512
1513	LogFlow(("%s %RGv=%08x eax=%08x\n", emGetMnemonic(pCpu), pvParam1, pRegFrame->eax));
1514
1515	if (pCpu->prefix & PREFIX_LOCK)
1516	eflags = EMEmulateLockCmpXchg8b(pvParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
1517	else
1518	eflags = EMEmulateCmpXchg8b(pvParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
1519
1520	LogFlow(("%s %RGv=%08x eax=%08x ZF=%d\n", emGetMnemonic(pCpu), pvParam1, pRegFrame->eax, !!(eflags & X86_EFL_ZF)));
1521
1522	/* Update guest's eflags and finish; note that only ZF is affected. */
1523	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_ZF))
1524	\| (eflags & (X86_EFL_ZF));
1525
1526	*pcbSize = 8;
1527	return VINF_SUCCESS;
1528	}
1529
1530	#else /* IN_RC */
1531
1532	/**
1533	* [LOCK] CMPXCHG emulation.
1534	*/
1535	static int emInterpretCmpXchg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1536	{
1537	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
1538	OP_PARAMVAL param1, param2;
1539
1540	/* Source to make DISQueryParamVal read the register value - ugly hack */
1541	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1542	if(RT_FAILURE(rc))
1543	return VERR_EM_INTERPRETER;
1544
1545	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1546	if(RT_FAILURE(rc))
1547	return VERR_EM_INTERPRETER;
1548
1549	if (TRPMHasTrap(pVM))
1550	{
1551	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1552	{
1553	RTRCPTR pParam1;
1554	uint32_t valpar, eflags;
1555
1556	AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
1557	switch(param1.type)
1558	{
1559	case PARMTYPE_ADDRESS:
1560	pParam1 = (RTRCPTR)param1.val.val64;
1561	pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);
1562	EM_ASSERT_FAULT_RETURN(pParam1 == (RTRCPTR)pvFault, VERR_EM_INTERPRETER);
1563	break;
1564
1565	default:
1566	return VERR_EM_INTERPRETER;
1567	}
1568
1569	switch(param2.type)
1570	{
1571	case PARMTYPE_IMMEDIATE: /* register actually */
1572	valpar = param2.val.val32;
1573	break;
1574
1575	default:
1576	return VERR_EM_INTERPRETER;
1577	}
1578
1579	LogFlow(("%s %RRv eax=%08x %08x\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax, valpar));
1580
1581	MMGCRamRegisterTrapHandler(pVM);
1582	if (pCpu->prefix & PREFIX_LOCK)
1583	rc = EMGCEmulateLockCmpXchg(pParam1, &pRegFrame->eax, valpar, pCpu->param2.size, &eflags);
1584	else
1585	rc = EMGCEmulateCmpXchg(pParam1, &pRegFrame->eax, valpar, pCpu->param2.size, &eflags);
1586	MMGCRamDeregisterTrapHandler(pVM);
1587
1588	if (RT_FAILURE(rc))
1589	{
1590	Log(("%s %RGv eax=%08x %08x -> emulation failed due to page fault!\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax, valpar));
1591	return VERR_EM_INTERPRETER;
1592	}
1593
1594	LogFlow(("%s %RRv eax=%08x %08x ZF=%d\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax, valpar, !!(eflags & X86_EFL_ZF)));
1595
1596	/* Update guest's eflags and finish. */
1597	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1598	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1599
1600	*pcbSize = param2.size;
1601	return VINF_SUCCESS;
1602	}
1603	}
1604	return VERR_EM_INTERPRETER;
1605	}
1606
1607
1608	/**
1609	* [LOCK] CMPXCHG8B emulation.
1610	*/
1611	static int emInterpretCmpXchg8b(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1612	{
1613	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
1614	OP_PARAMVAL param1;
1615
1616	/* Source to make DISQueryParamVal read the register value - ugly hack */
1617	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1618	if(RT_FAILURE(rc))
1619	return VERR_EM_INTERPRETER;
1620
1621	if (TRPMHasTrap(pVM))
1622	{
1623	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1624	{
1625	RTRCPTR pParam1;
1626	uint32_t eflags;
1627
1628	AssertReturn(pCpu->param1.size == 8, VERR_EM_INTERPRETER);
1629	switch(param1.type)
1630	{
1631	case PARMTYPE_ADDRESS:
1632	pParam1 = (RTRCPTR)param1.val.val64;
1633	pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);
1634	EM_ASSERT_FAULT_RETURN(pParam1 == (RTRCPTR)pvFault, VERR_EM_INTERPRETER);
1635	break;
1636
1637	default:
1638	return VERR_EM_INTERPRETER;
1639	}
1640
1641	LogFlow(("%s %RRv=%08x eax=%08x\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax));
1642
1643	MMGCRamRegisterTrapHandler(pVM);
1644	if (pCpu->prefix & PREFIX_LOCK)
1645	rc = EMGCEmulateLockCmpXchg8b(pParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx, &eflags);
1646	else
1647	rc = EMGCEmulateCmpXchg8b(pParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx, &eflags);
1648	MMGCRamDeregisterTrapHandler(pVM);
1649
1650	if (RT_FAILURE(rc))
1651	{
1652	Log(("%s %RGv=%08x eax=%08x -> emulation failed due to page fault!\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax));
1653	return VERR_EM_INTERPRETER;
1654	}
1655
1656	LogFlow(("%s %RGv=%08x eax=%08x ZF=%d\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax, !!(eflags & X86_EFL_ZF)));
1657
1658	/* Update guest's eflags and finish; note that only ZF is affected. */
1659	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_ZF))
1660	\| (eflags & (X86_EFL_ZF));
1661
1662	*pcbSize = 8;
1663	return VINF_SUCCESS;
1664	}
1665	}
1666	return VERR_EM_INTERPRETER;
1667	}
1668
1669	#endif /* IN_RC */
1670
1671	#ifdef IN_RC
1672	/**
1673	* [LOCK] XADD emulation.
1674	*/
1675	static int emInterpretXAdd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1676	{
1677	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
1678	OP_PARAMVAL param1;
1679	uint32_t *pParamReg2;
1680	size_t cbSizeParamReg2;
1681
1682	/* Source to make DISQueryParamVal read the register value - ugly hack */
1683	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1684	if(RT_FAILURE(rc))
1685	return VERR_EM_INTERPRETER;
1686
1687	rc = DISQueryParamRegPtr(pRegFrame, pCpu, &pCpu->param2, (void **)&pParamReg2, &cbSizeParamReg2);
1688	Assert(cbSizeParamReg2 <= 4);
1689	if(RT_FAILURE(rc))
1690	return VERR_EM_INTERPRETER;
1691
1692	if (TRPMHasTrap(pVM))
1693	{
1694	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1695	{
1696	RTRCPTR pParam1;
1697	uint32_t eflags;
1698
1699	AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
1700	switch(param1.type)
1701	{
1702	case PARMTYPE_ADDRESS:
1703	pParam1 = (RTRCPTR)param1.val.val64;
1704	pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);
1705	EM_ASSERT_FAULT_RETURN(pParam1 == (RTRCPTR)pvFault, VERR_EM_INTERPRETER);
1706	break;
1707
1708	default:
1709	return VERR_EM_INTERPRETER;
1710	}
1711
1712	LogFlow(("XAdd %RRv=%08x reg=%08x\n", pParam1, *pParamReg2));
1713
1714	MMGCRamRegisterTrapHandler(pVM);
1715	if (pCpu->prefix & PREFIX_LOCK)
1716	rc = EMGCEmulateLockXAdd(pParam1, pParamReg2, cbSizeParamReg2, &eflags);
1717	else
1718	rc = EMGCEmulateXAdd(pParam1, pParamReg2, cbSizeParamReg2, &eflags);
1719	MMGCRamDeregisterTrapHandler(pVM);
1720
1721	if (RT_FAILURE(rc))
1722	{
1723	Log(("XAdd %RGv reg=%08x -> emulation failed due to page fault!\n", pParam1, *pParamReg2));
1724	return VERR_EM_INTERPRETER;
1725	}
1726
1727	LogFlow(("XAdd %RGv reg=%08x ZF=%d\n", pParam1, *pParamReg2, !!(eflags & X86_EFL_ZF)));
1728
1729	/* Update guest's eflags and finish. */
1730	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1731	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1732
1733	*pcbSize = cbSizeParamReg2;
1734	return VINF_SUCCESS;
1735	}
1736	}
1737	return VERR_EM_INTERPRETER;
1738	}
1739	#endif /* IN_RC */
1740
1741
1742	#ifdef IN_RC
1743	/**
1744	* Interpret IRET (currently only to V86 code)
1745	*
1746	* @returns VBox status code.
1747	* @param pVM The VM handle.
1748	* @param pRegFrame The register frame.
1749	*
1750	*/
1751	VMMDECL(int) EMInterpretIret(PVM pVM, PCPUMCTXCORE pRegFrame)
1752	{
1753	RTGCUINTPTR pIretStack = (RTGCUINTPTR)pRegFrame->esp;
1754	RTGCUINTPTR eip, cs, esp, ss, eflags, ds, es, fs, gs, uMask;
1755	int rc;
1756
1757	Assert(!CPUMIsGuestIn64BitCode(pVM, pRegFrame));
1758
1759	rc = emRamRead(pVM, &eip, (RTGCPTR)pIretStack , 4);
1760	rc \|= emRamRead(pVM, &cs, (RTGCPTR)(pIretStack + 4), 4);
1761	rc \|= emRamRead(pVM, &eflags, (RTGCPTR)(pIretStack + 8), 4);
1762	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1763	AssertReturn(eflags & X86_EFL_VM, VERR_EM_INTERPRETER);
1764
1765	rc \|= emRamRead(pVM, &esp, (RTGCPTR)(pIretStack + 12), 4);
1766	rc \|= emRamRead(pVM, &ss, (RTGCPTR)(pIretStack + 16), 4);
1767	rc \|= emRamRead(pVM, &es, (RTGCPTR)(pIretStack + 20), 4);
1768	rc \|= emRamRead(pVM, &ds, (RTGCPTR)(pIretStack + 24), 4);
1769	rc \|= emRamRead(pVM, &fs, (RTGCPTR)(pIretStack + 28), 4);
1770	rc \|= emRamRead(pVM, &gs, (RTGCPTR)(pIretStack + 32), 4);
1771	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1772
1773	pRegFrame->eip = eip & 0xffff;
1774	pRegFrame->cs = cs;
1775
1776	/* Mask away all reserved bits */
1777	uMask = X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_RF \| X86_EFL_VM \| X86_EFL_AC \| X86_EFL_VIF \| X86_EFL_VIP \| X86_EFL_ID;
1778	eflags &= uMask;
1779
1780	#ifndef IN_RING0
1781	CPUMRawSetEFlags(pVM, pRegFrame, eflags);
1782	#endif
1783	Assert((pRegFrame->eflags.u32 & (X86_EFL_IF\|X86_EFL_IOPL)) == X86_EFL_IF);
1784
1785	pRegFrame->esp = esp;
1786	pRegFrame->ss = ss;
1787	pRegFrame->ds = ds;
1788	pRegFrame->es = es;
1789	pRegFrame->fs = fs;
1790	pRegFrame->gs = gs;
1791
1792	return VINF_SUCCESS;
1793	}
1794	#endif /* IN_RC */
1795
1796
1797	/**
1798	* IRET Emulation.
1799	*/
1800	static int emInterpretIret(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1801	{
1802	/* only allow direct calls to EMInterpretIret for now */
1803	return VERR_EM_INTERPRETER;
1804	}
1805
1806	/**
1807	* WBINVD Emulation.
1808	*/
1809	static int emInterpretWbInvd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1810	{
1811	/* Nothing to do. */
1812	return VINF_SUCCESS;
1813	}
1814
1815
1816	/**
1817	* Interpret INVLPG
1818	*
1819	* @returns VBox status code.
1820	* @param pVM The VM handle.
1821	* @param pRegFrame The register frame.
1822	* @param pAddrGC Operand address
1823	*
1824	*/
1825	VMMDECL(int) EMInterpretInvlpg(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC)
1826	{
1827	int rc;
1828
1829	/** @todo is addr always a flat linear address or ds based
1830	* (in absence of segment override prefixes)????
1831	*/
1832	#ifdef IN_RC
1833	LogFlow(("RC: EMULATE: invlpg %RGv\n", pAddrGC));
1834	#endif
1835	rc = PGMInvalidatePage(pVM, pAddrGC);
1836	if ( rc == VINF_SUCCESS
1837	\|\| rc == VINF_PGM_SYNC_CR3 /* we can rely on the FF */)
1838	return VINF_SUCCESS;
1839	AssertMsgReturn( rc == VERR_REM_FLUSHED_PAGES_OVERFLOW
1840	\|\| rc == VINF_EM_RAW_EMULATE_INSTR,
1841	("%Rrc addr=%RGv\n", rc, pAddrGC),
1842	VERR_EM_INTERPRETER);
1843	return rc;
1844	}
1845
1846
1847	/**
1848	* INVLPG Emulation.
1849	*/
1850	static int emInterpretInvlPg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1851	{
1852	OP_PARAMVAL param1;
1853	RTGCPTR addr;
1854
1855	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1856	if(RT_FAILURE(rc))
1857	return VERR_EM_INTERPRETER;
1858
1859	switch(param1.type)
1860	{
1861	case PARMTYPE_IMMEDIATE:
1862	case PARMTYPE_ADDRESS:
1863	if(!(param1.flags & (PARAM_VAL32\|PARAM_VAL64)))
1864	return VERR_EM_INTERPRETER;
1865	addr = (RTGCPTR)param1.val.val64;
1866	break;
1867
1868	default:
1869	return VERR_EM_INTERPRETER;
1870	}
1871
1872	/** @todo is addr always a flat linear address or ds based
1873	* (in absence of segment override prefixes)????
1874	*/
1875	#ifdef IN_RC
1876	LogFlow(("RC: EMULATE: invlpg %RGv\n", addr));
1877	#endif
1878	rc = PGMInvalidatePage(pVM, addr);
1879	if ( rc == VINF_SUCCESS
1880	\|\| rc == VINF_PGM_SYNC_CR3 /* we can rely on the FF */)
1881	return VINF_SUCCESS;
1882	AssertMsgReturn( rc == VERR_REM_FLUSHED_PAGES_OVERFLOW
1883	\|\| rc == VINF_EM_RAW_EMULATE_INSTR,
1884	("%Rrc addr=%RGv\n", rc, addr),
1885	VERR_EM_INTERPRETER);
1886	return rc;
1887	}
1888
1889
1890	/**
1891	* Interpret CPUID given the parameters in the CPU context
1892	*
1893	* @returns VBox status code.
1894	* @param pVM The VM handle.
1895	* @param pRegFrame The register frame.
1896	*
1897	*/
1898	VMMDECL(int) EMInterpretCpuId(PVM pVM, PCPUMCTXCORE pRegFrame)
1899	{
1900	uint32_t iLeaf = pRegFrame->eax;
1901
1902	/* cpuid clears the high dwords of the affected 64 bits registers. */
1903	pRegFrame->rax = 0;
1904	pRegFrame->rbx = 0;
1905	pRegFrame->rcx = 0;
1906	pRegFrame->rdx = 0;
1907
1908	/* Note: operates the same in 64 and non-64 bits mode. */
1909	CPUMGetGuestCpuId(pVM, iLeaf, &pRegFrame->eax, &pRegFrame->ebx, &pRegFrame->ecx, &pRegFrame->edx);
1910	Log(("Emulate: CPUID %x -> %08x %08x %08x %08x\n", iLeaf, pRegFrame->eax, pRegFrame->ebx, pRegFrame->ecx, pRegFrame->edx));
1911	return VINF_SUCCESS;
1912	}
1913
1914
1915	/**
1916	* CPUID Emulation.
1917	*/
1918	static int emInterpretCpuId(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1919	{
1920	int rc = EMInterpretCpuId(pVM, pRegFrame);
1921	return rc;
1922	}
1923
1924
1925	/**
1926	* Interpret CRx read
1927	*
1928	* @returns VBox status code.
1929	* @param pVM The VM handle.
1930	* @param pRegFrame The register frame.
1931	* @param DestRegGen General purpose register index (USE_REG_E**))
1932	* @param SrcRegCRx CRx register index (USE_REG_CR*)
1933	*
1934	*/
1935	VMMDECL(int) EMInterpretCRxRead(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx)
1936	{
1937	int rc;
1938	uint64_t val64;
1939
1940	if (SrcRegCrx == USE_REG_CR8)
1941	{
1942	val64 = 0;
1943	rc = PDMApicGetTPR(pVM, (uint8_t *)&val64, NULL);
1944	AssertMsgRCReturn(rc, ("PDMApicGetTPR failed\n"), VERR_EM_INTERPRETER);
1945	}
1946	else
1947	{
1948	rc = CPUMGetGuestCRx(pVM, SrcRegCrx, &val64);
1949	AssertMsgRCReturn(rc, ("CPUMGetGuestCRx %d failed\n", SrcRegCrx), VERR_EM_INTERPRETER);
1950	}
1951
1952	if (CPUMIsGuestIn64BitCode(pVM, pRegFrame))
1953	rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
1954	else
1955	rc = DISWriteReg32(pRegFrame, DestRegGen, val64);
1956
1957	if(RT_SUCCESS(rc))
1958	{
1959	LogFlow(("MOV_CR: gen32=%d CR=%d val=%RX64\n", DestRegGen, SrcRegCrx, val64));
1960	return VINF_SUCCESS;
1961	}
1962	return VERR_EM_INTERPRETER;
1963	}
1964
1965
1966
1967	/**
1968	* Interpret CLTS
1969	*
1970	* @returns VBox status code.
1971	* @param pVM The VM handle.
1972	*
1973	*/
1974	VMMDECL(int) EMInterpretCLTS(PVM pVM)
1975	{
1976	uint64_t cr0 = CPUMGetGuestCR0(pVM);
1977	if (!(cr0 & X86_CR0_TS))
1978	return VINF_SUCCESS;
1979	return CPUMSetGuestCR0(pVM, cr0 & ~X86_CR0_TS);
1980	}
1981
1982	/**
1983	* CLTS Emulation.
1984	*/
1985	static int emInterpretClts(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1986	{
1987	return EMInterpretCLTS(pVM);
1988	}
1989
1990
1991	/**
1992	* Update CRx
1993	*
1994	* @returns VBox status code.
1995	* @param pVM The VM handle.
1996	* @param pRegFrame The register frame.
1997	* @param DestRegCRx CRx register index (USE_REG_CR*)
1998	* @param val New CRx value
1999	*
2000	*/
2001	static int EMUpdateCRx(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint64_t val)
2002	{
2003	uint64_t oldval;
2004	uint64_t msrEFER;
2005	int rc;
2006
2007	/** @todo Clean up this mess. */
2008	LogFlow(("EMInterpretCRxWrite at %RGv CR%d <- %RX64\n", (RTGCPTR)pRegFrame->rip, DestRegCrx, val));
2009	switch (DestRegCrx)
2010	{
2011	case USE_REG_CR0:
2012	oldval = CPUMGetGuestCR0(pVM);
2013	#ifdef IN_RC
2014	/* CR0.WP and CR0.AM changes require a reschedule run in ring 3. */
2015	if ( (val & (X86_CR0_WP \| X86_CR0_AM))
2016	!= (oldval & (X86_CR0_WP \| X86_CR0_AM)))
2017	return VERR_EM_INTERPRETER;
2018	#endif
2019	CPUMSetGuestCR0(pVM, val);
2020	val = CPUMGetGuestCR0(pVM);
2021	if ( (oldval & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE))
2022	!= (val & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE)))
2023	{
2024	/* global flush */
2025	rc = PGMFlushTLB(pVM, CPUMGetGuestCR3(pVM), true /* global */);
2026	AssertRCReturn(rc, rc);
2027	}
2028
2029	/* Deal with long mode enabling/disabling. */
2030	msrEFER = CPUMGetGuestEFER(pVM);
2031	if (msrEFER & MSR_K6_EFER_LME)
2032	{
2033	if ( !(oldval & X86_CR0_PG)
2034	&& (val & X86_CR0_PG))
2035	{
2036	/* Illegal to have an active 64 bits CS selector (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
2037	if (pRegFrame->csHid.Attr.n.u1Long)
2038	{
2039	AssertMsgFailed(("Illegal enabling of paging with CS.u1Long = 1!!\n"));
2040	return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
2041	}
2042
2043	/* Illegal to switch to long mode before activating PAE first (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
2044	if (!(CPUMGetGuestCR4(pVM) & X86_CR4_PAE))
2045	{
2046	AssertMsgFailed(("Illegal enabling of paging with PAE disabled!!\n"));
2047	return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
2048	}
2049	msrEFER \|= MSR_K6_EFER_LMA;
2050	}
2051	else
2052	if ( (oldval & X86_CR0_PG)
2053	&& !(val & X86_CR0_PG))
2054	{
2055	msrEFER &= ~MSR_K6_EFER_LMA;
2056	/* @todo Do we need to cut off rip here? High dword of rip is undefined, so it shouldn't really matter. */
2057	}
2058	CPUMSetGuestEFER(pVM, msrEFER);
2059	}
2060	return PGMChangeMode(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR4(pVM), CPUMGetGuestEFER(pVM));
2061
2062	case USE_REG_CR2:
2063	rc = CPUMSetGuestCR2(pVM, val); AssertRC(rc);
2064	return VINF_SUCCESS;
2065
2066	case USE_REG_CR3:
2067	/* Reloading the current CR3 means the guest just wants to flush the TLBs */
2068	rc = CPUMSetGuestCR3(pVM, val); AssertRC(rc);
2069	if (CPUMGetGuestCR0(pVM) & X86_CR0_PG)
2070	{
2071	/* flush */
2072	rc = PGMFlushTLB(pVM, val, !(CPUMGetGuestCR4(pVM) & X86_CR4_PGE));
2073	AssertRCReturn(rc, rc);
2074	}
2075	return VINF_SUCCESS;
2076
2077	case USE_REG_CR4:
2078	oldval = CPUMGetGuestCR4(pVM);
2079	rc = CPUMSetGuestCR4(pVM, val); AssertRC(rc);
2080	val = CPUMGetGuestCR4(pVM);
2081
2082	msrEFER = CPUMGetGuestEFER(pVM);
2083	/* Illegal to disable PAE when long mode is active. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
2084	if ( (msrEFER & MSR_K6_EFER_LMA)
2085	&& (oldval & X86_CR4_PAE)
2086	&& !(val & X86_CR4_PAE))
2087	{
2088	return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
2089	}
2090
2091	if ( (oldval & (X86_CR4_PGE\|X86_CR4_PAE\|X86_CR4_PSE))
2092	!= (val & (X86_CR4_PGE\|X86_CR4_PAE\|X86_CR4_PSE)))
2093	{
2094	/* global flush */
2095	rc = PGMFlushTLB(pVM, CPUMGetGuestCR3(pVM), true /* global */);
2096	AssertRCReturn(rc, rc);
2097	}
2098	# ifdef IN_RC
2099	/* Feeling extremely lazy. */
2100	if ( (oldval & (X86_CR4_OSFSXR\|X86_CR4_OSXMMEEXCPT\|X86_CR4_PCE\|X86_CR4_MCE\|X86_CR4_PAE\|X86_CR4_DE\|X86_CR4_TSD\|X86_CR4_PVI\|X86_CR4_VME))
2101	!= (val & (X86_CR4_OSFSXR\|X86_CR4_OSXMMEEXCPT\|X86_CR4_PCE\|X86_CR4_MCE\|X86_CR4_PAE\|X86_CR4_DE\|X86_CR4_TSD\|X86_CR4_PVI\|X86_CR4_VME)))
2102	{
2103	Log(("emInterpretMovCRx: CR4: %#RX64->%#RX64 => R3\n", oldval, val));
2104	VM_FF_SET(pVM, VM_FF_TO_R3);
2105	}
2106	# endif
2107	return PGMChangeMode(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR4(pVM), CPUMGetGuestEFER(pVM));
2108
2109	case USE_REG_CR8:
2110	return PDMApicSetTPR(pVM, val);
2111
2112	default:
2113	AssertFailed();
2114	case USE_REG_CR1: /* illegal op */
2115	break;
2116	}
2117	return VERR_EM_INTERPRETER;
2118	}
2119
2120	/**
2121	* Interpret CRx write
2122	*
2123	* @returns VBox status code.
2124	* @param pVM The VM handle.
2125	* @param pRegFrame The register frame.
2126	* @param DestRegCRx CRx register index (USE_REG_CR*)
2127	* @param SrcRegGen General purpose register index (USE_REG_E**))
2128	*
2129	*/
2130	VMMDECL(int) EMInterpretCRxWrite(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint32_t SrcRegGen)
2131	{
2132	uint64_t val;
2133	int rc;
2134
2135	if (CPUMIsGuestIn64BitCode(pVM, pRegFrame))
2136	{
2137	rc = DISFetchReg64(pRegFrame, SrcRegGen, &val);
2138	}
2139	else
2140	{
2141	uint32_t val32;
2142	rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
2143	val = val32;
2144	}
2145
2146	if (RT_SUCCESS(rc))
2147	return EMUpdateCRx(pVM, pRegFrame, DestRegCrx, val);
2148
2149	return VERR_EM_INTERPRETER;
2150	}
2151
2152	/**
2153	* Interpret LMSW
2154	*
2155	* @returns VBox status code.
2156	* @param pVM The VM handle.
2157	* @param pRegFrame The register frame.
2158	* @param u16Data LMSW source data.
2159	*
2160	*/
2161	VMMDECL(int) EMInterpretLMSW(PVM pVM, PCPUMCTXCORE pRegFrame, uint16_t u16Data)
2162	{
2163	uint64_t OldCr0 = CPUMGetGuestCR0(pVM);
2164
2165	/* Only PE, MP, EM and TS can be changed; note that PE can't be cleared by this instruction. */
2166	uint64_t NewCr0 = ( OldCr0 & ~( X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
2167	\| (u16Data & (X86_CR0_PE \| X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS));
2168
2169	return EMUpdateCRx(pVM, pRegFrame, USE_REG_CR0, NewCr0);
2170	}
2171
2172	/**
2173	* LMSW Emulation.
2174	*/
2175	static int emInterpretLmsw(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2176	{
2177	OP_PARAMVAL param1;
2178	uint32_t val;
2179
2180	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
2181	if(RT_FAILURE(rc))
2182	return VERR_EM_INTERPRETER;
2183
2184	switch(param1.type)
2185	{
2186	case PARMTYPE_IMMEDIATE:
2187	case PARMTYPE_ADDRESS:
2188	if(!(param1.flags & PARAM_VAL16))
2189	return VERR_EM_INTERPRETER;
2190	val = param1.val.val32;
2191	break;
2192
2193	default:
2194	return VERR_EM_INTERPRETER;
2195	}
2196
2197	LogFlow(("emInterpretLmsw %x\n", val));
2198	return EMInterpretLMSW(pVM, pRegFrame, val);
2199	}
2200
2201	/**
2202	* MOV CRx
2203	*/
2204	static int emInterpretMovCRx(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2205	{
2206	if ((pCpu->param1.flags == USE_REG_GEN32 \|\| pCpu->param1.flags == USE_REG_GEN64) && pCpu->param2.flags == USE_REG_CR)
2207	return EMInterpretCRxRead(pVM, pRegFrame, pCpu->param1.base.reg_gen, pCpu->param2.base.reg_ctrl);
2208
2209	if (pCpu->param1.flags == USE_REG_CR && (pCpu->param2.flags == USE_REG_GEN32 \|\| pCpu->param2.flags == USE_REG_GEN64))
2210	return EMInterpretCRxWrite(pVM, pRegFrame, pCpu->param1.base.reg_ctrl, pCpu->param2.base.reg_gen);
2211
2212	AssertMsgFailedReturn(("Unexpected control register move\n"), VERR_EM_INTERPRETER);
2213	return VERR_EM_INTERPRETER;
2214	}
2215
2216
2217	/**
2218	* Interpret DRx write
2219	*
2220	* @returns VBox status code.
2221	* @param pVM The VM handle.
2222	* @param pRegFrame The register frame.
2223	* @param DestRegDRx DRx register index (USE_REG_DR*)
2224	* @param SrcRegGen General purpose register index (USE_REG_E**))
2225	*
2226	*/
2227	VMMDECL(int) EMInterpretDRxWrite(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen)
2228	{
2229	uint64_t val;
2230	int rc;
2231
2232	if (CPUMIsGuestIn64BitCode(pVM, pRegFrame))
2233	{
2234	rc = DISFetchReg64(pRegFrame, SrcRegGen, &val);
2235	}
2236	else
2237	{
2238	uint32_t val32;
2239	rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
2240	val = val32;
2241	}
2242
2243	if (RT_SUCCESS(rc))
2244	{
2245	/** @todo we don't fail if illegal bits are set/cleared for e.g. dr7 */
2246	rc = CPUMSetGuestDRx(pVM, DestRegDrx, val);
2247	if (RT_SUCCESS(rc))
2248	return rc;
2249	AssertMsgFailed(("CPUMSetGuestDRx %d failed\n", DestRegDrx));
2250	}
2251	return VERR_EM_INTERPRETER;
2252	}
2253
2254
2255	/**
2256	* Interpret DRx read
2257	*
2258	* @returns VBox status code.
2259	* @param pVM The VM handle.
2260	* @param pRegFrame The register frame.
2261	* @param DestRegGen General purpose register index (USE_REG_E**))
2262	* @param SrcRegDRx DRx register index (USE_REG_DR*)
2263	*
2264	*/
2265	VMMDECL(int) EMInterpretDRxRead(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx)
2266	{
2267	uint64_t val64;
2268
2269	int rc = CPUMGetGuestDRx(pVM, SrcRegDrx, &val64);
2270	AssertMsgRCReturn(rc, ("CPUMGetGuestDRx %d failed\n", SrcRegDrx), VERR_EM_INTERPRETER);
2271	if (CPUMIsGuestIn64BitCode(pVM, pRegFrame))
2272	{
2273	rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
2274	}
2275	else
2276	rc = DISWriteReg32(pRegFrame, DestRegGen, (uint32_t)val64);
2277
2278	if (RT_SUCCESS(rc))
2279	return VINF_SUCCESS;
2280
2281	return VERR_EM_INTERPRETER;
2282	}
2283
2284
2285	/**
2286	* MOV DRx
2287	*/
2288	static int emInterpretMovDRx(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2289	{
2290	int rc = VERR_EM_INTERPRETER;
2291
2292	if((pCpu->param1.flags == USE_REG_GEN32 \|\| pCpu->param1.flags == USE_REG_GEN64) && pCpu->param2.flags == USE_REG_DBG)
2293	{
2294	rc = EMInterpretDRxRead(pVM, pRegFrame, pCpu->param1.base.reg_gen, pCpu->param2.base.reg_dbg);
2295	}
2296	else
2297	if(pCpu->param1.flags == USE_REG_DBG && (pCpu->param2.flags == USE_REG_GEN32 \|\| pCpu->param2.flags == USE_REG_GEN64))
2298	{
2299	rc = EMInterpretDRxWrite(pVM, pRegFrame, pCpu->param1.base.reg_dbg, pCpu->param2.base.reg_gen);
2300	}
2301	else
2302	AssertMsgFailed(("Unexpected debug register move\n"));
2303
2304	return rc;
2305	}
2306
2307
2308	/**
2309	* LLDT Emulation.
2310	*/
2311	static int emInterpretLLdt(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2312	{
2313	OP_PARAMVAL param1;
2314	RTSEL sel;
2315
2316	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
2317	if(RT_FAILURE(rc))
2318	return VERR_EM_INTERPRETER;
2319
2320	switch(param1.type)
2321	{
2322	case PARMTYPE_ADDRESS:
2323	return VERR_EM_INTERPRETER; //feeling lazy right now
2324
2325	case PARMTYPE_IMMEDIATE:
2326	if(!(param1.flags & PARAM_VAL16))
2327	return VERR_EM_INTERPRETER;
2328	sel = (RTSEL)param1.val.val16;
2329	break;
2330
2331	default:
2332	return VERR_EM_INTERPRETER;
2333	}
2334
2335	if (sel == 0)
2336	{
2337	if (CPUMGetHyperLDTR(pVM) == 0)
2338	{
2339	// this simple case is most frequent in Windows 2000 (31k - boot & shutdown)
2340	return VINF_SUCCESS;
2341	}
2342	}
2343	//still feeling lazy
2344	return VERR_EM_INTERPRETER;
2345	}
2346
2347	#ifdef IN_RING0
2348	/**
2349	* LIDT/LGDT Emulation.
2350	*/
2351	static int emInterpretLIGdt(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2352	{
2353	OP_PARAMVAL param1;
2354	RTGCPTR pParam1;
2355	X86XDTR32 dtr32;
2356
2357	Log(("Emulate %s at %RGv\n", emGetMnemonic(pCpu), (RTGCPTR)pRegFrame->rip));
2358
2359	/* Only for the VT-x real-mode emulation case. */
2360	if (!CPUMIsGuestInRealMode(pVM))
2361	return VERR_EM_INTERPRETER;
2362
2363	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
2364	if(RT_FAILURE(rc))
2365	return VERR_EM_INTERPRETER;
2366
2367	switch(param1.type)
2368	{
2369	case PARMTYPE_ADDRESS:
2370	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, param1.val.val16);
2371	break;
2372
2373	default:
2374	return VERR_EM_INTERPRETER;
2375	}
2376
2377	rc = emRamRead(pVM, &dtr32, pParam1, sizeof(dtr32));
2378	AssertRCReturn(rc, VERR_EM_INTERPRETER);
2379
2380	if (!(pCpu->prefix & PREFIX_OPSIZE))
2381	dtr32.uAddr &= 0xffffff; /* 16 bits operand size */
2382
2383	if (pCpu->pCurInstr->opcode == OP_LIDT)
2384	CPUMSetGuestIDTR(pVM, dtr32.uAddr, dtr32.cb);
2385	else
2386	CPUMSetGuestGDTR(pVM, dtr32.uAddr, dtr32.cb);
2387
2388	return VINF_SUCCESS;
2389	}
2390	#endif
2391
2392
2393	#ifdef IN_RC
2394	/**
2395	* STI Emulation.
2396	*
2397	* @remark the instruction following sti is guaranteed to be executed before any interrupts are dispatched
2398	*/
2399	static int emInterpretSti(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2400	{
2401	PPATMGCSTATE pGCState = PATMQueryGCState(pVM);
2402
2403	if(!pGCState)
2404	{
2405	Assert(pGCState);
2406	return VERR_EM_INTERPRETER;
2407	}
2408	pGCState->uVMFlags \|= X86_EFL_IF;
2409
2410	Assert(pRegFrame->eflags.u32 & X86_EFL_IF);
2411	Assert(pvFault == SELMToFlat(pVM, DIS_SELREG_CS, pRegFrame, (RTGCPTR)pRegFrame->rip));
2412
2413	pVM->em.s.GCPtrInhibitInterrupts = pRegFrame->eip + pCpu->opsize;
2414	VM_FF_SET(pVM, VM_FF_INHIBIT_INTERRUPTS);
2415
2416	return VINF_SUCCESS;
2417	}
2418	#endif /* IN_RC */
2419
2420
2421	/**
2422	* HLT Emulation.
2423	*/
2424	static int emInterpretHlt(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2425	{
2426	return VINF_EM_HALT;
2427	}
2428
2429
2430	/**
2431	* Interpret RDTSC
2432	*
2433	* @returns VBox status code.
2434	* @param pVM The VM handle.
2435	* @param pRegFrame The register frame.
2436	*
2437	*/
2438	VMMDECL(int) EMInterpretRdtsc(PVM pVM, PCPUMCTXCORE pRegFrame)
2439	{
2440	unsigned uCR4 = CPUMGetGuestCR4(pVM);
2441
2442	if (uCR4 & X86_CR4_TSD)
2443	return VERR_EM_INTERPRETER; /* genuine #GP */
2444
2445	uint64_t uTicks = TMCpuTickGet(pVM);
2446
2447	/* Same behaviour in 32 & 64 bits mode */
2448	pRegFrame->rax = (uint32_t)uTicks;
2449	pRegFrame->rdx = (uTicks >> 32ULL);
2450
2451	return VINF_SUCCESS;
2452	}
2453
2454	VMMDECL(int) EMInterpretRdtscp(PVM pVM, PCPUMCTX pCtx)
2455	{
2456	unsigned uCR4 = CPUMGetGuestCR4(pVM);
2457
2458	if (!CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
2459	{
2460	AssertFailed();
2461	return VERR_EM_INTERPRETER; /* genuine #UD */
2462	}
2463
2464	if (uCR4 & X86_CR4_TSD)
2465	return VERR_EM_INTERPRETER; /* genuine #GP */
2466
2467	uint64_t uTicks = TMCpuTickGet(pVM);
2468
2469	/* Same behaviour in 32 & 64 bits mode */
2470	pCtx->rax = (uint32_t)uTicks;
2471	pCtx->rdx = (uTicks >> 32ULL);
2472	/* Low dword of the TSC_AUX msr only. */
2473	pCtx->rcx = (uint32_t)CPUMGetGuestMsr(pVM, MSR_K8_TSC_AUX);
2474
2475	return VINF_SUCCESS;
2476	}
2477
2478	/**
2479	* RDTSC Emulation.
2480	*/
2481	static int emInterpretRdtsc(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2482	{
2483	return EMInterpretRdtsc(pVM, pRegFrame);
2484	}
2485
2486
2487	/**
2488	* MONITOR Emulation.
2489	*/
2490	static int emInterpretMonitor(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2491	{
2492	uint32_t u32Dummy, u32ExtFeatures, cpl;
2493
2494	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
2495	if (pRegFrame->ecx != 0)
2496	return VERR_EM_INTERPRETER; /* illegal value. */
2497
2498	/* Get the current privilege level. */
2499	cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2500	if (cpl != 0)
2501	return VERR_EM_INTERPRETER; /* supervisor only */
2502
2503	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
2504	if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
2505	return VERR_EM_INTERPRETER; /* not supported */
2506
2507	return VINF_SUCCESS;
2508	}
2509
2510
2511	/**
2512	* MWAIT Emulation.
2513	*/
2514	static int emInterpretMWait(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2515	{
2516	uint32_t u32Dummy, u32ExtFeatures, cpl;
2517
2518	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
2519	if (pRegFrame->ecx != 0)
2520	return VERR_EM_INTERPRETER; /* illegal value. */
2521
2522	/* Get the current privilege level. */
2523	cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2524	if (cpl != 0)
2525	return VERR_EM_INTERPRETER; /* supervisor only */
2526
2527	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
2528	if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
2529	return VERR_EM_INTERPRETER; /* not supported */
2530
2531	/** @todo not completely correct */
2532	return VINF_EM_HALT;
2533	}
2534
2535
2536	#ifdef LOG_ENABLED
2537	static const char *emMSRtoString(uint32_t uMsr)
2538	{
2539	switch (uMsr)
2540	{
2541	case MSR_IA32_APICBASE:
2542	return "MSR_IA32_APICBASE";
2543	case MSR_IA32_CR_PAT:
2544	return "MSR_IA32_CR_PAT";
2545	case MSR_IA32_SYSENTER_CS:
2546	return "MSR_IA32_SYSENTER_CS";
2547	case MSR_IA32_SYSENTER_EIP:
2548	return "MSR_IA32_SYSENTER_EIP";
2549	case MSR_IA32_SYSENTER_ESP:
2550	return "MSR_IA32_SYSENTER_ESP";
2551	case MSR_K6_EFER:
2552	return "MSR_K6_EFER";
2553	case MSR_K8_SF_MASK:
2554	return "MSR_K8_SF_MASK";
2555	case MSR_K6_STAR:
2556	return "MSR_K6_STAR";
2557	case MSR_K8_LSTAR:
2558	return "MSR_K8_LSTAR";
2559	case MSR_K8_CSTAR:
2560	return "MSR_K8_CSTAR";
2561	case MSR_K8_FS_BASE:
2562	return "MSR_K8_FS_BASE";
2563	case MSR_K8_GS_BASE:
2564	return "MSR_K8_GS_BASE";
2565	case MSR_K8_KERNEL_GS_BASE:
2566	return "MSR_K8_KERNEL_GS_BASE";
2567	case MSR_K8_TSC_AUX:
2568	return "MSR_K8_TSC_AUX";
2569	case MSR_IA32_BIOS_SIGN_ID:
2570	return "Unsupported MSR_IA32_BIOS_SIGN_ID";
2571	case MSR_IA32_PLATFORM_ID:
2572	return "Unsupported MSR_IA32_PLATFORM_ID";
2573	case MSR_IA32_BIOS_UPDT_TRIG:
2574	return "Unsupported MSR_IA32_BIOS_UPDT_TRIG";
2575	case MSR_IA32_TSC:
2576	return "Unsupported MSR_IA32_TSC";
2577	case MSR_IA32_MTRR_CAP:
2578	return "Unsupported MSR_IA32_MTRR_CAP";
2579	case MSR_IA32_MCP_CAP:
2580	return "Unsupported MSR_IA32_MCP_CAP";
2581	case MSR_IA32_MCP_STATUS:
2582	return "Unsupported MSR_IA32_MCP_STATUS";
2583	case MSR_IA32_MCP_CTRL:
2584	return "Unsupported MSR_IA32_MCP_CTRL";
2585	case MSR_IA32_MTRR_DEF_TYPE:
2586	return "Unsupported MSR_IA32_MTRR_DEF_TYPE";
2587	case MSR_K7_EVNTSEL0:
2588	return "Unsupported MSR_K7_EVNTSEL0";
2589	case MSR_K7_EVNTSEL1:
2590	return "Unsupported MSR_K7_EVNTSEL1";
2591	case MSR_K7_EVNTSEL2:
2592	return "Unsupported MSR_K7_EVNTSEL2";
2593	case MSR_K7_EVNTSEL3:
2594	return "Unsupported MSR_K7_EVNTSEL3";
2595	case MSR_IA32_MC0_CTL:
2596	return "Unsupported MSR_IA32_MC0_CTL";
2597	case MSR_IA32_MC0_STATUS:
2598	return "Unsupported MSR_IA32_MC0_STATUS";
2599	}
2600	return "Unknown MSR";
2601	}
2602	#endif /* LOG_ENABLED */
2603
2604
2605	/**
2606	* Interpret RDMSR
2607	*
2608	* @returns VBox status code.
2609	* @param pVM The VM handle.
2610	* @param pRegFrame The register frame.
2611	*
2612	*/
2613	VMMDECL(int) EMInterpretRdmsr(PVM pVM, PCPUMCTXCORE pRegFrame)
2614	{
2615	uint32_t u32Dummy, u32Features, cpl;
2616	uint64_t val;
2617	CPUMCTX *pCtx;
2618	int rc = VINF_SUCCESS;
2619
2620	/** @todo According to the Intel manuals, there's a REX version of RDMSR that is slightly different.
2621	* That version clears the high dwords of both RDX & RAX */
2622	pCtx = CPUMQueryGuestCtxPtr(pVM);
2623
2624	/* Get the current privilege level. */
2625	cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2626	if (cpl != 0)
2627	return VERR_EM_INTERPRETER; /* supervisor only */
2628
2629	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2630	if (!(u32Features & X86_CPUID_FEATURE_EDX_MSR))
2631	return VERR_EM_INTERPRETER; /* not supported */
2632
2633	switch (pRegFrame->ecx)
2634	{
2635	case MSR_IA32_APICBASE:
2636	rc = PDMApicGetBase(pVM, &val);
2637	AssertRC(rc);
2638	break;
2639
2640	case MSR_IA32_CR_PAT:
2641	val = pCtx->msrPAT;
2642	break;
2643
2644	case MSR_IA32_SYSENTER_CS:
2645	val = pCtx->SysEnter.cs;
2646	break;
2647
2648	case MSR_IA32_SYSENTER_EIP:
2649	val = pCtx->SysEnter.eip;
2650	break;
2651
2652	case MSR_IA32_SYSENTER_ESP:
2653	val = pCtx->SysEnter.esp;
2654	break;
2655
2656	case MSR_K6_EFER:
2657	val = pCtx->msrEFER;
2658	break;
2659
2660	case MSR_K8_SF_MASK:
2661	val = pCtx->msrSFMASK;
2662	break;
2663
2664	case MSR_K6_STAR:
2665	val = pCtx->msrSTAR;
2666	break;
2667
2668	case MSR_K8_LSTAR:
2669	val = pCtx->msrLSTAR;
2670	break;
2671
2672	case MSR_K8_CSTAR:
2673	val = pCtx->msrCSTAR;
2674	break;
2675
2676	case MSR_K8_FS_BASE:
2677	val = pCtx->fsHid.u64Base;
2678	break;
2679
2680	case MSR_K8_GS_BASE:
2681	val = pCtx->gsHid.u64Base;
2682	break;
2683
2684	case MSR_K8_KERNEL_GS_BASE:
2685	val = pCtx->msrKERNELGSBASE;
2686	break;
2687
2688	case MSR_K8_TSC_AUX:
2689	val = CPUMGetGuestMsr(pVM, MSR_K8_TSC_AUX);
2690	break;
2691
2692	#if 0 /def IN_RING0 /
2693	case MSR_IA32_PLATFORM_ID:
2694	case MSR_IA32_BIOS_SIGN_ID:
2695	if (CPUMGetCPUVendor(pVM) == CPUMCPUVENDOR_INTEL)
2696	{
2697	/* Available since the P6 family. VT-x implies that this feature is present. */
2698	if (pRegFrame->ecx == MSR_IA32_PLATFORM_ID)
2699	val = ASMRdMsr(MSR_IA32_PLATFORM_ID);
2700	else
2701	if (pRegFrame->ecx == MSR_IA32_BIOS_SIGN_ID)
2702	val = ASMRdMsr(MSR_IA32_BIOS_SIGN_ID);
2703	break;
2704	}
2705	/* no break */
2706	#endif
2707	default:
2708	/* In X2APIC specification this range is reserved for APIC control. */
2709	if ((pRegFrame->ecx >= MSR_IA32_APIC_START) && (pRegFrame->ecx < MSR_IA32_APIC_END))
2710	rc = PDMApicReadMSR(pVM, VMMGetCpuId(pVM), pRegFrame->ecx, &val);
2711	else
2712	/* We should actually trigger a #GP here, but don't as that might cause more trouble. */
2713	val = 0;
2714	break;
2715	}
2716	LogFlow(("EMInterpretRdmsr %s (%x) -> val=%RX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx, val));
2717	if (rc == VINF_SUCCESS)
2718	{
2719	pRegFrame->rax = (uint32_t) val;
2720	pRegFrame->rdx = (uint32_t) (val >> 32ULL);
2721	}
2722	return rc;
2723	}
2724
2725
2726	/**
2727	* RDMSR Emulation.
2728	*/
2729	static int emInterpretRdmsr(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2730	{
2731	/* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
2732	Assert(!(pCpu->prefix & PREFIX_REX));
2733	return EMInterpretRdmsr(pVM, pRegFrame);
2734	}
2735
2736
2737	/**
2738	* Interpret WRMSR
2739	*
2740	* @returns VBox status code.
2741	* @param pVM The VM handle.
2742	* @param pRegFrame The register frame.
2743	*/
2744	VMMDECL(int) EMInterpretWrmsr(PVM pVM, PCPUMCTXCORE pRegFrame)
2745	{
2746	uint32_t u32Dummy, u32Features, cpl;
2747	uint64_t val;
2748	CPUMCTX *pCtx;
2749
2750	/* Note: works the same in 32 and 64 bits modes. */
2751	pCtx = CPUMQueryGuestCtxPtr(pVM);
2752
2753	/* Get the current privilege level. */
2754	cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2755	if (cpl != 0)
2756	return VERR_EM_INTERPRETER; /* supervisor only */
2757
2758	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2759	if (!(u32Features & X86_CPUID_FEATURE_EDX_MSR))
2760	return VERR_EM_INTERPRETER; /* not supported */
2761
2762	val = RT_MAKE_U64(pRegFrame->eax, pRegFrame->edx);
2763	LogFlow(("EMInterpretWrmsr %s (%x) val=%RX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx, val));
2764	switch (pRegFrame->ecx)
2765	{
2766	case MSR_IA32_APICBASE:
2767	{
2768	int rc = PDMApicSetBase(pVM, val);
2769	AssertRC(rc);
2770	break;
2771	}
2772
2773	case MSR_IA32_CR_PAT:
2774	pCtx->msrPAT = val;
2775	break;
2776
2777	case MSR_IA32_SYSENTER_CS:
2778	pCtx->SysEnter.cs = val & 0xffff; /* 16 bits selector */
2779	break;
2780
2781	case MSR_IA32_SYSENTER_EIP:
2782	pCtx->SysEnter.eip = val;
2783	break;
2784
2785	case MSR_IA32_SYSENTER_ESP:
2786	pCtx->SysEnter.esp = val;
2787	break;
2788
2789	case MSR_K6_EFER:
2790	{
2791	uint64_t uMask = 0;
2792	uint64_t oldval = pCtx->msrEFER;
2793
2794	/* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
2795	CPUMGetGuestCpuId(pVM, 0x80000001, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2796	if (u32Features & X86_CPUID_AMD_FEATURE_EDX_NX)
2797	uMask \|= MSR_K6_EFER_NXE;
2798	if (u32Features & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE)
2799	uMask \|= MSR_K6_EFER_LME;
2800	if (u32Features & X86_CPUID_AMD_FEATURE_EDX_SEP)
2801	uMask \|= MSR_K6_EFER_SCE;
2802	if (u32Features & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
2803	uMask \|= MSR_K6_EFER_FFXSR;
2804
2805	/* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
2806	if ( ((pCtx->msrEFER & MSR_K6_EFER_LME) != (val & uMask & MSR_K6_EFER_LME))
2807	&& (pCtx->cr0 & X86_CR0_PG))
2808	{
2809	AssertMsgFailed(("Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
2810	return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
2811	}
2812
2813	/* There are a few more: e.g. MSR_K6_EFER_LMSLE */
2814	AssertMsg(!(val & ~(MSR_K6_EFER_NXE\|MSR_K6_EFER_LME\|MSR_K6_EFER_LMA /* ignored anyway */ \|MSR_K6_EFER_SCE\|MSR_K6_EFER_FFXSR)), ("Unexpected value %RX64\n", val));
2815	pCtx->msrEFER = (pCtx->msrEFER & ~uMask) \| (val & uMask);
2816
2817	/* AMD64 Achitecture Programmer's Manual: 15.15 TLB Control; flush the TLB if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
2818	if ((oldval & (MSR_K6_EFER_NXE\|MSR_K6_EFER_LME\|MSR_K6_EFER_LMA)) != (pCtx->msrEFER & (MSR_K6_EFER_NXE\|MSR_K6_EFER_LME\|MSR_K6_EFER_LMA)))
2819	HWACCMFlushTLB(pVM);
2820
2821	break;
2822	}
2823
2824	case MSR_K8_SF_MASK:
2825	pCtx->msrSFMASK = val;
2826	break;
2827
2828	case MSR_K6_STAR:
2829	pCtx->msrSTAR = val;
2830	break;
2831
2832	case MSR_K8_LSTAR:
2833	pCtx->msrLSTAR = val;
2834	break;
2835
2836	case MSR_K8_CSTAR:
2837	pCtx->msrCSTAR = val;
2838	break;
2839
2840	case MSR_K8_FS_BASE:
2841	pCtx->fsHid.u64Base = val;
2842	break;
2843
2844	case MSR_K8_GS_BASE:
2845	pCtx->gsHid.u64Base = val;
2846	break;
2847
2848	case MSR_K8_KERNEL_GS_BASE:
2849	pCtx->msrKERNELGSBASE = val;
2850	break;
2851
2852	case MSR_K8_TSC_AUX:
2853	CPUMSetGuestMsr(pVM, MSR_K8_TSC_AUX, val);
2854	break;
2855
2856	default:
2857	/* In X2APIC specification this range is reserved for APIC control. */
2858	if ((pRegFrame->ecx >= MSR_IA32_APIC_START) && (pRegFrame->ecx < MSR_IA32_APIC_END))
2859	return PDMApicWriteMSR(pVM, VMMGetCpuId(pVM), pRegFrame->ecx, val);
2860
2861	/* We should actually trigger a #GP here, but don't as that might cause more trouble. */
2862	break;
2863	}
2864	return VINF_SUCCESS;
2865	}
2866
2867
2868	/**
2869	* WRMSR Emulation.
2870	*/
2871	static int emInterpretWrmsr(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2872	{
2873	return EMInterpretWrmsr(pVM, pRegFrame);
2874	}
2875
2876
2877	/**
2878	* Internal worker.
2879	* @copydoc EMInterpretInstructionCPU
2880	*/
2881	DECLINLINE(int) emInterpretInstructionCPU(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2882	{
2883	Assert(pcbSize);
2884	*pcbSize = 0;
2885
2886	/*
2887	* Only supervisor guest code!!
2888	* And no complicated prefixes.
2889	*/
2890	/* Get the current privilege level. */
2891	uint32_t cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2892	if ( cpl != 0
2893	&& pCpu->pCurInstr->opcode != OP_RDTSC) /* rdtsc requires emulation in ring 3 as well */
2894	{
2895	Log(("WARNING: refusing instruction emulation for user-mode code!!\n"));
2896	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedUserMode));
2897	return VERR_EM_INTERPRETER;
2898	}
2899
2900	#ifdef IN_RC
2901	if ( (pCpu->prefix & (PREFIX_REPNE \| PREFIX_REP))
2902	\|\| ( (pCpu->prefix & PREFIX_LOCK)
2903	&& pCpu->pCurInstr->opcode != OP_CMPXCHG
2904	&& pCpu->pCurInstr->opcode != OP_CMPXCHG8B
2905	&& pCpu->pCurInstr->opcode != OP_XADD
2906	&& pCpu->pCurInstr->opcode != OP_OR
2907	&& pCpu->pCurInstr->opcode != OP_BTR
2908	)
2909	)
2910	#else
2911	if ( (pCpu->prefix & PREFIX_REPNE)
2912	\|\| ( (pCpu->prefix & PREFIX_REP)
2913	&& pCpu->pCurInstr->opcode != OP_STOSWD
2914	)
2915	\|\| ( (pCpu->prefix & PREFIX_LOCK)
2916	&& pCpu->pCurInstr->opcode != OP_OR
2917	&& pCpu->pCurInstr->opcode != OP_BTR
2918	&& pCpu->pCurInstr->opcode != OP_CMPXCHG
2919	&& pCpu->pCurInstr->opcode != OP_CMPXCHG8B
2920	)
2921	)
2922	#endif
2923	{
2924	//Log(("EMInterpretInstruction: wrong prefix!!\n"));
2925	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedPrefix));
2926	return VERR_EM_INTERPRETER;
2927	}
2928
2929	int rc;
2930	#if (defined(VBOX_STRICT) \|\| defined(LOG_ENABLED))
2931	LogFlow(("emInterpretInstructionCPU %s\n", emGetMnemonic(pCpu)));
2932	#endif
2933	switch (pCpu->pCurInstr->opcode)
2934	{
2935	# define INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
2936	case opcode:\
2937	if (pCpu->prefix & PREFIX_LOCK) \
2938	rc = emInterpretLock##InstrFn(pVM, pCpu, pRegFrame, pvFault, pcbSize, pfnEmulateLock); \
2939	else \
2940	rc = emInterpret##InstrFn(pVM, pCpu, pRegFrame, pvFault, pcbSize, pfnEmulate); \
2941	if (RT_SUCCESS(rc)) \
2942	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
2943	else \
2944	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
2945	return rc
2946	#define INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate) \
2947	case opcode:\
2948	rc = emInterpret##InstrFn(pVM, pCpu, pRegFrame, pvFault, pcbSize, pfnEmulate); \
2949	if (RT_SUCCESS(rc)) \
2950	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
2951	else \
2952	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
2953	return rc
2954
2955	#define INTERPRET_CASE_EX_PARAM2(opcode, Instr, InstrFn, pfnEmulate) \
2956	INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate)
2957	#define INTERPRET_CASE_EX_LOCK_PARAM2(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
2958	INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock)
2959
2960	#define INTERPRET_CASE(opcode, Instr) \
2961	case opcode:\
2962	rc = emInterpret##Instr(pVM, pCpu, pRegFrame, pvFault, pcbSize); \
2963	if (RT_SUCCESS(rc)) \
2964	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
2965	else \
2966	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
2967	return rc
2968
2969	#define INTERPRET_CASE_EX_DUAL_PARAM2(opcode, Instr, InstrFn) \
2970	case opcode:\
2971	rc = emInterpret##InstrFn(pVM, pCpu, pRegFrame, pvFault, pcbSize); \
2972	if (RT_SUCCESS(rc)) \
2973	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
2974	else \
2975	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
2976	return rc
2977
2978	#define INTERPRET_STAT_CASE(opcode, Instr) \
2979	case opcode: STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); return VERR_EM_INTERPRETER;
2980
2981	INTERPRET_CASE(OP_XCHG,Xchg);
2982	INTERPRET_CASE_EX_PARAM2(OP_DEC,Dec, IncDec, EMEmulateDec);
2983	INTERPRET_CASE_EX_PARAM2(OP_INC,Inc, IncDec, EMEmulateInc);
2984	INTERPRET_CASE(OP_POP,Pop);
2985	INTERPRET_CASE_EX_LOCK_PARAM3(OP_OR, Or, OrXorAnd, EMEmulateOr, EMEmulateLockOr);
2986	INTERPRET_CASE_EX_PARAM3(OP_XOR,Xor, OrXorAnd, EMEmulateXor);
2987	INTERPRET_CASE_EX_PARAM3(OP_AND,And, OrXorAnd, EMEmulateAnd);
2988	INTERPRET_CASE(OP_MOV,Mov);
2989	#ifndef IN_RC
2990	INTERPRET_CASE(OP_STOSWD,StosWD);
2991	#endif
2992	INTERPRET_CASE(OP_INVLPG,InvlPg);
2993	INTERPRET_CASE(OP_CPUID,CpuId);
2994	INTERPRET_CASE(OP_MOV_CR,MovCRx);
2995	INTERPRET_CASE(OP_MOV_DR,MovDRx);
2996	INTERPRET_CASE(OP_LLDT,LLdt);
2997	#ifdef IN_RING0
2998	INTERPRET_CASE_EX_DUAL_PARAM2(OP_LIDT, LIdt, LIGdt);
2999	INTERPRET_CASE_EX_DUAL_PARAM2(OP_LGDT, LGdt, LIGdt);
3000	#endif
3001	INTERPRET_CASE(OP_LMSW,Lmsw);
3002	INTERPRET_CASE(OP_CLTS,Clts);
3003	INTERPRET_CASE(OP_MONITOR, Monitor);
3004	INTERPRET_CASE(OP_MWAIT, MWait);
3005	INTERPRET_CASE(OP_RDMSR, Rdmsr);
3006	INTERPRET_CASE(OP_WRMSR, Wrmsr);
3007	INTERPRET_CASE_EX_PARAM3(OP_ADD,Add, AddSub, EMEmulateAdd);
3008	INTERPRET_CASE_EX_PARAM3(OP_SUB,Sub, AddSub, EMEmulateSub);
3009	INTERPRET_CASE(OP_ADC,Adc);
3010	INTERPRET_CASE_EX_LOCK_PARAM2(OP_BTR,Btr, BitTest, EMEmulateBtr, EMEmulateLockBtr);
3011	INTERPRET_CASE_EX_PARAM2(OP_BTS,Bts, BitTest, EMEmulateBts);
3012	INTERPRET_CASE_EX_PARAM2(OP_BTC,Btc, BitTest, EMEmulateBtc);
3013	INTERPRET_CASE(OP_RDTSC,Rdtsc);
3014	INTERPRET_CASE(OP_CMPXCHG, CmpXchg);
3015	#ifdef IN_RC
3016	INTERPRET_CASE(OP_STI,Sti);
3017	INTERPRET_CASE(OP_XADD, XAdd);
3018	#endif
3019	INTERPRET_CASE(OP_CMPXCHG8B, CmpXchg8b);
3020	INTERPRET_CASE(OP_HLT,Hlt);
3021	INTERPRET_CASE(OP_IRET,Iret);
3022	INTERPRET_CASE(OP_WBINVD,WbInvd);
3023	#ifdef VBOX_WITH_STATISTICS
3024	#ifndef IN_RC
3025	INTERPRET_STAT_CASE(OP_XADD, XAdd);
3026	#endif
3027	INTERPRET_STAT_CASE(OP_MOVNTPS,MovNTPS);
3028	#endif
3029	default:
3030	Log3(("emInterpretInstructionCPU: opcode=%d\n", pCpu->pCurInstr->opcode));
3031	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedMisc));
3032	return VERR_EM_INTERPRETER;
3033	#undef INTERPRET_CASE_EX_PARAM2
3034	#undef INTERPRET_STAT_CASE
3035	#undef INTERPRET_CASE_EX
3036	#undef INTERPRET_CASE
3037	}
3038	AssertFailed();
3039	return VERR_INTERNAL_ERROR;
3040	}
3041
3042
3043	/**
3044	* Sets the PC for which interrupts should be inhibited.
3045	*
3046	* @param pVM The VM handle.
3047	* @param PC The PC.
3048	*/
3049	VMMDECL(void) EMSetInhibitInterruptsPC(PVM pVM, RTGCUINTPTR PC)
3050	{
3051	pVM->em.s.GCPtrInhibitInterrupts = PC;
3052	VM_FF_SET(pVM, VM_FF_INHIBIT_INTERRUPTS);
3053	}
3054
3055
3056	/**
3057	* Gets the PC for which interrupts should be inhibited.
3058	*
3059	* There are a few instructions which inhibits or delays interrupts
3060	* for the instruction following them. These instructions are:
3061	* - STI
3062	* - MOV SS, r/m16
3063	* - POP SS
3064	*
3065	* @returns The PC for which interrupts should be inhibited.
3066	* @param pVM VM handle.
3067	*
3068	*/
3069	VMMDECL(RTGCUINTPTR) EMGetInhibitInterruptsPC(PVM pVM)
3070	{
3071	return pVM->em.s.GCPtrInhibitInterrupts;
3072	}
3073

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source: vbox/trunk/src/VBox/VMM/VMMAll/EMAll.cpp@ 14411

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