EMAll.cpp@ 14740

Last change on this file since 14740 was 14562, checked in by vboxsync, 16 years ago
Corrected wrong pointer calculation
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File size: 100.2 KB

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1	/* $Id: EMAll.cpp 14562 2008-11-25 10:21:24Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor(/Manager) - All contexts
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_EM
26	#include <VBox/em.h>
27	#include <VBox/mm.h>
28	#include <VBox/selm.h>
29	#include <VBox/patm.h>
30	#include <VBox/csam.h>
31	#include <VBox/pgm.h>
32	#include <VBox/iom.h>
33	#include <VBox/stam.h>
34	#include "EMInternal.h"
35	#include <VBox/vm.h>
36	#include <VBox/vmm.h>
37	#include <VBox/hwaccm.h>
38	#include <VBox/tm.h>
39	#include <VBox/pdmapi.h>
40
41	#include <VBox/param.h>
42	#include <VBox/err.h>
43	#include <VBox/dis.h>
44	#include <VBox/disopcode.h>
45	#include <VBox/log.h>
46	#include <iprt/assert.h>
47	#include <iprt/asm.h>
48	#include <iprt/string.h>
49
50
51	/*******************************************************************************
52	* Defined Constants And Macros *
53	*******************************************************************************/
54	/** @def EM_ASSERT_FAULT_RETURN
55	* Safety check.
56	*
57	* Could in theory it misfire on a cross page boundary access...
58	*
59	* Currently disabled because the CSAM (+ PATM) patch monitoring occationally
60	* turns up an alias page instead of the original faulting one and annoying the
61	* heck out of anyone running a debug build. See @bugref{2609} and @bugref{1931}.
62	*/
63	#if 0
64	# define EM_ASSERT_FAULT_RETURN(expr, rc) AssertReturn(expr, rc)
65	#else
66	# define EM_ASSERT_FAULT_RETURN(expr, rc) do { } while (0)
67	#endif
68
69
70	/*******************************************************************************
71	* Internal Functions *
72	*******************************************************************************/
73	DECLINLINE(int) emInterpretInstructionCPU(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize);
74
75
76
77	/**
78	* Get the current execution manager status.
79	*
80	* @returns Current status.
81	*/
82	VMMDECL(EMSTATE) EMGetState(PVM pVM)
83	{
84	return pVM->em.s.enmState;
85	}
86
87	#ifndef IN_RC
88
89	/**
90	* Read callback for disassembly function; supports reading bytes that cross a page boundary
91	*
92	* @returns VBox status code.
93	* @param pSrc GC source pointer
94	* @param pDest HC destination pointer
95	* @param cb Number of bytes to read
96	* @param dwUserdata Callback specific user data (pCpu)
97	*
98	*/
99	DECLCALLBACK(int) EMReadBytes(RTUINTPTR pSrc, uint8_t pDest, unsigned cb, void pvUserdata)
100	{
101	DISCPUSTATE pCpu = (DISCPUSTATE )pvUserdata;
102	PVM pVM = (PVM)pCpu->apvUserData[0];
103	# ifdef IN_RING0
104	int rc = PGMPhysSimpleReadGCPtr(pVM, pDest, pSrc, cb);
105	AssertMsgRC(rc, ("PGMPhysSimpleReadGCPtr failed for pSrc=%RGv cb=%x\n", pSrc, cb));
106	# else /* IN_RING3 */
107	if (!PATMIsPatchGCAddr(pVM, pSrc))
108	{
109	int rc = PGMPhysSimpleReadGCPtr(pVM, pDest, pSrc, cb);
110	AssertRC(rc);
111	}
112	else
113	{
114	for (uint32_t i = 0; i < cb; i++)
115	{
116	uint8_t opcode;
117	if (RT_SUCCESS(PATMR3QueryOpcode(pVM, (RTGCPTR)pSrc + i, &opcode)))
118	{
119	*(pDest+i) = opcode;
120	}
121	}
122	}
123	# endif /* IN_RING3 */
124	return VINF_SUCCESS;
125	}
126
127	DECLINLINE(int) emDisCoreOne(PVM pVM, DISCPUSTATE pCpu, RTGCUINTPTR InstrGC, uint32_t pOpsize)
128	{
129	return DISCoreOneEx(InstrGC, pCpu->mode, EMReadBytes, pVM, pCpu, pOpsize);
130	}
131
132	#else /* IN_RC */
133
134	DECLINLINE(int) emDisCoreOne(PVM pVM, DISCPUSTATE pCpu, RTGCUINTPTR InstrGC, uint32_t pOpsize)
135	{
136	return DISCoreOne(pCpu, InstrGC, pOpsize);
137	}
138
139	#endif /* IN_RC */
140
141
142	/**
143	* Disassembles one instruction.
144	*
145	* @param pVM The VM handle.
146	* @param pCtxCore The context core (used for both the mode and instruction).
147	* @param pCpu Where to return the parsed instruction info.
148	* @param pcbInstr Where to return the instruction size. (optional)
149	*/
150	VMMDECL(int) EMInterpretDisasOne(PVM pVM, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, unsigned *pcbInstr)
151	{
152	RTGCPTR GCPtrInstr;
153	int rc = SELMToFlatEx(pVM, DIS_SELREG_CS, pCtxCore, pCtxCore->rip, 0, &GCPtrInstr);
154	if (RT_FAILURE(rc))
155	{
156	Log(("EMInterpretDisasOne: Failed to convert %RTsel:%RGv (cpl=%d) - rc=%Rrc !!\n",
157	pCtxCore->cs, (RTGCPTR)pCtxCore->rip, pCtxCore->ss & X86_SEL_RPL, rc));
158	return rc;
159	}
160	return EMInterpretDisasOneEx(pVM, (RTGCUINTPTR)GCPtrInstr, pCtxCore, pCpu, pcbInstr);
161	}
162
163
164	/**
165	* Disassembles one instruction.
166	*
167	* This is used by internally by the interpreter and by trap/access handlers.
168	*
169	* @param pVM The VM handle.
170	* @param GCPtrInstr The flat address of the instruction.
171	* @param pCtxCore The context core (used to determin the cpu mode).
172	* @param pCpu Where to return the parsed instruction info.
173	* @param pcbInstr Where to return the instruction size. (optional)
174	*/
175	VMMDECL(int) EMInterpretDisasOneEx(PVM pVM, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, unsigned *pcbInstr)
176	{
177	int rc = DISCoreOneEx(GCPtrInstr, SELMGetCpuModeFromSelector(pVM, pCtxCore->eflags, pCtxCore->cs, (PCPUMSELREGHID)&pCtxCore->csHid),
178	#ifdef IN_RC
179	NULL, NULL,
180	#else
181	EMReadBytes, pVM,
182	#endif
183	pCpu, pcbInstr);
184	if (RT_SUCCESS(rc))
185	return VINF_SUCCESS;
186	AssertMsgFailed(("DISCoreOne failed to GCPtrInstr=%RGv rc=%Rrc\n", GCPtrInstr, rc));
187	return VERR_INTERNAL_ERROR;
188	}
189
190
191	/**
192	* Interprets the current instruction.
193	*
194	* @returns VBox status code.
195	* @retval VINF_* Scheduling instructions.
196	* @retval VERR_EM_INTERPRETER Something we can't cope with.
197	* @retval VERR_* Fatal errors.
198	*
199	* @param pVM The VM handle.
200	* @param pRegFrame The register frame.
201	* Updates the EIP if an instruction was executed successfully.
202	* @param pvFault The fault address (CR2).
203	* @param pcbSize Size of the write (if applicable).
204	*
205	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
206	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
207	* to worry about e.g. invalid modrm combinations (!)
208	*/
209	VMMDECL(int) EMInterpretInstruction(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
210	{
211	RTGCPTR pbCode;
212
213	LogFlow(("EMInterpretInstruction %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
214	int rc = SELMToFlatEx(pVM, DIS_SELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
215	if (RT_SUCCESS(rc))
216	{
217	uint32_t cbOp;
218	DISCPUSTATE Cpu;
219	Cpu.mode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
220	rc = emDisCoreOne(pVM, &Cpu, (RTGCUINTPTR)pbCode, &cbOp);
221	if (RT_SUCCESS(rc))
222	{
223	Assert(cbOp == Cpu.opsize);
224	rc = EMInterpretInstructionCPU(pVM, &Cpu, pRegFrame, pvFault, pcbSize);
225	if (RT_SUCCESS(rc))
226	{
227	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
228	}
229	return rc;
230	}
231	}
232	return VERR_EM_INTERPRETER;
233	}
234
235
236	/**
237	* Interprets the current instruction using the supplied DISCPUSTATE structure.
238	*
239	* EIP is NOT updated!
240	*
241	* @returns VBox status code.
242	* @retval VINF_* Scheduling instructions. When these are returned, it
243	* starts to get a bit tricky to know whether code was
244	* executed or not... We'll address this when it becomes a problem.
245	* @retval VERR_EM_INTERPRETER Something we can't cope with.
246	* @retval VERR_* Fatal errors.
247	*
248	* @param pVM The VM handle.
249	* @param pCpu The disassembler cpu state for the instruction to be interpreted.
250	* @param pRegFrame The register frame. EIP is NOT changed!
251	* @param pvFault The fault address (CR2).
252	* @param pcbSize Size of the write (if applicable).
253	*
254	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
255	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
256	* to worry about e.g. invalid modrm combinations (!)
257	*
258	* @todo At this time we do NOT check if the instruction overwrites vital information.
259	* Make sure this can't happen!! (will add some assertions/checks later)
260	*/
261	VMMDECL(int) EMInterpretInstructionCPU(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
262	{
263	STAM_PROFILE_START(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Emulate), a);
264	int rc = emInterpretInstructionCPU(pVM, pCpu, pRegFrame, pvFault, pcbSize);
265	STAM_PROFILE_STOP(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Emulate), a);
266	if (RT_SUCCESS(rc))
267	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InterpretSucceeded));
268	else
269	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InterpretFailed));
270	return rc;
271	}
272
273
274	/**
275	* Interpret a port I/O instruction.
276	*
277	* @returns VBox status code suitable for scheduling.
278	* @param pVM The VM handle.
279	* @param pCtxCore The context core. This will be updated on successful return.
280	* @param pCpu The instruction to interpret.
281	* @param cbOp The size of the instruction.
282	* @remark This may raise exceptions.
283	*/
284	VMMDECL(int) EMInterpretPortIO(PVM pVM, PCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, uint32_t cbOp)
285	{
286	/*
287	* Hand it on to IOM.
288	*/
289	#ifdef IN_RC
290	int rc = IOMGCIOPortHandler(pVM, pCtxCore, pCpu);
291	if (IOM_SUCCESS(rc))
292	pCtxCore->rip += cbOp;
293	return rc;
294	#else
295	AssertReleaseMsgFailed(("not implemented\n"));
296	return VERR_NOT_IMPLEMENTED;
297	#endif
298	}
299
300
301	DECLINLINE(int) emRamRead(PVM pVM, void *pDest, RTGCPTR GCSrc, uint32_t cb)
302	{
303	#ifdef IN_RC
304	int rc = MMGCRamRead(pVM, pDest, (void *)GCSrc, cb);
305	if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
306	return rc;
307	/*
308	* The page pool cache may end up here in some cases because it
309	* flushed one of the shadow mappings used by the trapping
310	* instruction and it either flushed the TLB or the CPU reused it.
311	*/
312	RTGCPHYS GCPhys;
313	rc = PGMPhysGCPtr2GCPhys(pVM, GCSrc, &GCPhys);
314	AssertRCReturn(rc, rc);
315	PGMPhysRead(pVM, GCPhys, pDest, cb);
316	return VINF_SUCCESS;
317	#else
318	return PGMPhysReadGCPtr(pVM, pDest, GCSrc, cb);
319	#endif
320	}
321
322
323	DECLINLINE(int) emRamWrite(PVM pVM, RTGCPTR GCDest, void *pSrc, uint32_t cb)
324	{
325	#ifdef IN_RC
326	int rc = MMGCRamWrite(pVM, (void *)GCDest, pSrc, cb);
327	if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
328	return rc;
329	/*
330	* The page pool cache may end up here in some cases because it
331	* flushed one of the shadow mappings used by the trapping
332	* instruction and it either flushed the TLB or the CPU reused it.
333	* We want to play safe here, verifying that we've got write
334	* access doesn't cost us much (see PGMPhysGCPtr2GCPhys()).
335	*/
336	uint64_t fFlags;
337	RTGCPHYS GCPhys;
338	rc = PGMGstGetPage(pVM, GCDest, &fFlags, &GCPhys);
339	if (RT_FAILURE(rc))
340	return rc;
341	if ( !(fFlags & X86_PTE_RW)
342	&& (CPUMGetGuestCR0(pVM) & X86_CR0_WP))
343	return VERR_ACCESS_DENIED;
344
345	PGMPhysWrite(pVM, GCPhys + ((RTGCUINTPTR)GCDest & PAGE_OFFSET_MASK), pSrc, cb);
346	return VINF_SUCCESS;
347
348	#else
349	return PGMPhysWriteGCPtr(pVM, GCDest, pSrc, cb);
350	#endif
351	}
352
353
354	/* Convert sel:addr to a flat GC address */
355	static RTGCPTR emConvertToFlatAddr(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, POP_PARAMETER pParam, RTGCPTR pvAddr)
356	{
357	DIS_SELREG enmPrefixSeg = DISDetectSegReg(pCpu, pParam);
358	return SELMToFlat(pVM, enmPrefixSeg, pRegFrame, pvAddr);
359	}
360
361
362	#if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
363	/**
364	* Get the mnemonic for the disassembled instruction.
365	*
366	* GC/R0 doesn't include the strings in the DIS tables because
367	* of limited space.
368	*/
369	static const char *emGetMnemonic(PDISCPUSTATE pCpu)
370	{
371	switch (pCpu->pCurInstr->opcode)
372	{
373	case OP_XCHG: return "Xchg";
374	case OP_DEC: return "Dec";
375	case OP_INC: return "Inc";
376	case OP_POP: return "Pop";
377	case OP_OR: return "Or";
378	case OP_AND: return "And";
379	case OP_MOV: return "Mov";
380	case OP_INVLPG: return "InvlPg";
381	case OP_CPUID: return "CpuId";
382	case OP_MOV_CR: return "MovCRx";
383	case OP_MOV_DR: return "MovDRx";
384	case OP_LLDT: return "LLdt";
385	case OP_LGDT: return "LGdt";
386	case OP_LIDT: return "LGdt";
387	case OP_CLTS: return "Clts";
388	case OP_MONITOR: return "Monitor";
389	case OP_MWAIT: return "MWait";
390	case OP_RDMSR: return "Rdmsr";
391	case OP_WRMSR: return "Wrmsr";
392	case OP_ADD: return "Add";
393	case OP_ADC: return "Adc";
394	case OP_SUB: return "Sub";
395	case OP_SBB: return "Sbb";
396	case OP_RDTSC: return "Rdtsc";
397	case OP_STI: return "Sti";
398	case OP_XADD: return "XAdd";
399	case OP_HLT: return "Hlt";
400	case OP_IRET: return "Iret";
401	case OP_MOVNTPS: return "MovNTPS";
402	case OP_STOSWD: return "StosWD";
403	case OP_WBINVD: return "WbInvd";
404	case OP_XOR: return "Xor";
405	case OP_BTR: return "Btr";
406	case OP_BTS: return "Bts";
407	case OP_BTC: return "Btc";
408	case OP_LMSW: return "Lmsw";
409	case OP_CMPXCHG: return pCpu->prefix & PREFIX_LOCK ? "Lock CmpXchg" : "CmpXchg";
410	case OP_CMPXCHG8B: return pCpu->prefix & PREFIX_LOCK ? "Lock CmpXchg8b" : "CmpXchg8b";
411
412	default:
413	Log(("Unknown opcode %d\n", pCpu->pCurInstr->opcode));
414	return "???";
415	}
416	}
417	#endif /* VBOX_STRICT \|\| LOG_ENABLED */
418
419
420	/**
421	* XCHG instruction emulation.
422	*/
423	static int emInterpretXchg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
424	{
425	OP_PARAMVAL param1, param2;
426
427	/* Source to make DISQueryParamVal read the register value - ugly hack */
428	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
429	if(RT_FAILURE(rc))
430	return VERR_EM_INTERPRETER;
431
432	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
433	if(RT_FAILURE(rc))
434	return VERR_EM_INTERPRETER;
435
436	#ifdef IN_RC
437	if (TRPMHasTrap(pVM))
438	{
439	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
440	{
441	#endif
442	RTGCPTR pParam1 = 0, pParam2 = 0;
443	uint64_t valpar1, valpar2;
444
445	AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
446	switch(param1.type)
447	{
448	case PARMTYPE_IMMEDIATE: /* register type is translated to this one too */
449	valpar1 = param1.val.val64;
450	break;
451
452	case PARMTYPE_ADDRESS:
453	pParam1 = (RTGCPTR)param1.val.val64;
454	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
455	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
456	rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
457	if (RT_FAILURE(rc))
458	{
459	AssertMsgFailed(("MMGCRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
460	return VERR_EM_INTERPRETER;
461	}
462	break;
463
464	default:
465	AssertFailed();
466	return VERR_EM_INTERPRETER;
467	}
468
469	switch(param2.type)
470	{
471	case PARMTYPE_ADDRESS:
472	pParam2 = (RTGCPTR)param2.val.val64;
473	pParam2 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param2, pParam2);
474	EM_ASSERT_FAULT_RETURN(pParam2 == pvFault, VERR_EM_INTERPRETER);
475	rc = emRamRead(pVM, &valpar2, pParam2, param2.size);
476	if (RT_FAILURE(rc))
477	{
478	AssertMsgFailed(("MMGCRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
479	}
480	break;
481
482	case PARMTYPE_IMMEDIATE:
483	valpar2 = param2.val.val64;
484	break;
485
486	default:
487	AssertFailed();
488	return VERR_EM_INTERPRETER;
489	}
490
491	/* Write value of parameter 2 to parameter 1 (reg or memory address) */
492	if (pParam1 == 0)
493	{
494	Assert(param1.type == PARMTYPE_IMMEDIATE); /* register actually */
495	switch(param1.size)
496	{
497	case 1: //special case for AH etc
498	rc = DISWriteReg8(pRegFrame, pCpu->param1.base.reg_gen, (uint8_t )valpar2); break;
499	case 2: rc = DISWriteReg16(pRegFrame, pCpu->param1.base.reg_gen, (uint16_t)valpar2); break;
500	case 4: rc = DISWriteReg32(pRegFrame, pCpu->param1.base.reg_gen, (uint32_t)valpar2); break;
501	case 8: rc = DISWriteReg64(pRegFrame, pCpu->param1.base.reg_gen, valpar2); break;
502	default: AssertFailedReturn(VERR_EM_INTERPRETER);
503	}
504	if (RT_FAILURE(rc))
505	return VERR_EM_INTERPRETER;
506	}
507	else
508	{
509	rc = emRamWrite(pVM, pParam1, &valpar2, param1.size);
510	if (RT_FAILURE(rc))
511	{
512	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
513	return VERR_EM_INTERPRETER;
514	}
515	}
516
517	/* Write value of parameter 1 to parameter 2 (reg or memory address) */
518	if (pParam2 == 0)
519	{
520	Assert(param2.type == PARMTYPE_IMMEDIATE); /* register actually */
521	switch(param2.size)
522	{
523	case 1: //special case for AH etc
524	rc = DISWriteReg8(pRegFrame, pCpu->param2.base.reg_gen, (uint8_t )valpar1); break;
525	case 2: rc = DISWriteReg16(pRegFrame, pCpu->param2.base.reg_gen, (uint16_t)valpar1); break;
526	case 4: rc = DISWriteReg32(pRegFrame, pCpu->param2.base.reg_gen, (uint32_t)valpar1); break;
527	case 8: rc = DISWriteReg64(pRegFrame, pCpu->param2.base.reg_gen, valpar1); break;
528	default: AssertFailedReturn(VERR_EM_INTERPRETER);
529	}
530	if (RT_FAILURE(rc))
531	return VERR_EM_INTERPRETER;
532	}
533	else
534	{
535	rc = emRamWrite(pVM, pParam2, &valpar1, param2.size);
536	if (RT_FAILURE(rc))
537	{
538	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
539	return VERR_EM_INTERPRETER;
540	}
541	}
542
543	*pcbSize = param2.size;
544	return VINF_SUCCESS;
545	#ifdef IN_RC
546	}
547	}
548	#endif
549	return VERR_EM_INTERPRETER;
550	}
551
552
553	/**
554	* INC and DEC emulation.
555	*/
556	static int emInterpretIncDec(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
557	PFNEMULATEPARAM2 pfnEmulate)
558	{
559	OP_PARAMVAL param1;
560
561	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
562	if(RT_FAILURE(rc))
563	return VERR_EM_INTERPRETER;
564
565	#ifdef IN_RC
566	if (TRPMHasTrap(pVM))
567	{
568	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
569	{
570	#endif
571	RTGCPTR pParam1 = 0;
572	uint64_t valpar1;
573
574	if (param1.type == PARMTYPE_ADDRESS)
575	{
576	pParam1 = (RTGCPTR)param1.val.val64;
577	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
578	#ifdef IN_RC
579	/* Safety check (in theory it could cross a page boundary and fault there though) */
580	AssertReturn(pParam1 == pvFault, VERR_EM_INTERPRETER);
581	#endif
582	rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
583	if (RT_FAILURE(rc))
584	{
585	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
586	return VERR_EM_INTERPRETER;
587	}
588	}
589	else
590	{
591	AssertFailed();
592	return VERR_EM_INTERPRETER;
593	}
594
595	uint32_t eflags;
596
597	eflags = pfnEmulate(&valpar1, param1.size);
598
599	/* Write result back */
600	rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
601	if (RT_FAILURE(rc))
602	{
603	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
604	return VERR_EM_INTERPRETER;
605	}
606
607	/* Update guest's eflags and finish. */
608	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
609	\| (eflags & (X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
610
611	/* All done! */
612	*pcbSize = param1.size;
613	return VINF_SUCCESS;
614	#ifdef IN_RC
615	}
616	}
617	#endif
618	return VERR_EM_INTERPRETER;
619	}
620
621
622	/**
623	* POP Emulation.
624	*/
625	static int emInterpretPop(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
626	{
627	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
628	OP_PARAMVAL param1;
629	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
630	if(RT_FAILURE(rc))
631	return VERR_EM_INTERPRETER;
632
633	#ifdef IN_RC
634	if (TRPMHasTrap(pVM))
635	{
636	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
637	{
638	#endif
639	RTGCPTR pParam1 = 0;
640	uint32_t valpar1;
641	RTGCPTR pStackVal;
642
643	/* Read stack value first */
644	if (SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->ss, &pRegFrame->ssHid) == CPUMODE_16BIT)
645	return VERR_EM_INTERPRETER; /* No legacy 16 bits stuff here, please. */
646
647	/* Convert address; don't bother checking limits etc, as we only read here */
648	pStackVal = SELMToFlat(pVM, DIS_SELREG_SS, pRegFrame, (RTGCPTR)pRegFrame->esp);
649	if (pStackVal == 0)
650	return VERR_EM_INTERPRETER;
651
652	rc = emRamRead(pVM, &valpar1, pStackVal, param1.size);
653	if (RT_FAILURE(rc))
654	{
655	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
656	return VERR_EM_INTERPRETER;
657	}
658
659	if (param1.type == PARMTYPE_ADDRESS)
660	{
661	pParam1 = (RTGCPTR)param1.val.val64;
662
663	/* pop [esp+xx] uses esp after the actual pop! */
664	AssertCompile(USE_REG_ESP == USE_REG_SP);
665	if ( (pCpu->param1.flags & USE_BASE)
666	&& (pCpu->param1.flags & (USE_REG_GEN16\|USE_REG_GEN32))
667	&& pCpu->param1.base.reg_gen == USE_REG_ESP
668	)
669	pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + param1.size);
670
671	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
672	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault \|\| (RTGCPTR)pRegFrame->esp == pvFault, VERR_EM_INTERPRETER);
673	rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
674	if (RT_FAILURE(rc))
675	{
676	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
677	return VERR_EM_INTERPRETER;
678	}
679
680	/* Update ESP as the last step */
681	pRegFrame->esp += param1.size;
682	}
683	else
684	{
685	#ifndef DEBUG_bird // annoying assertion.
686	AssertFailed();
687	#endif
688	return VERR_EM_INTERPRETER;
689	}
690
691	/* All done! */
692	*pcbSize = param1.size;
693	return VINF_SUCCESS;
694	#ifdef IN_RC
695	}
696	}
697	#endif
698	return VERR_EM_INTERPRETER;
699	}
700
701
702	/**
703	* XOR/OR/AND Emulation.
704	*/
705	static int emInterpretOrXorAnd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
706	PFNEMULATEPARAM3 pfnEmulate)
707	{
708	OP_PARAMVAL param1, param2;
709	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
710	if(RT_FAILURE(rc))
711	return VERR_EM_INTERPRETER;
712
713	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
714	if(RT_FAILURE(rc))
715	return VERR_EM_INTERPRETER;
716
717	#ifdef IN_RC
718	if (TRPMHasTrap(pVM))
719	{
720	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
721	{
722	#endif
723	RTGCPTR pParam1;
724	uint64_t valpar1, valpar2;
725
726	if (pCpu->param1.size != pCpu->param2.size)
727	{
728	if (pCpu->param1.size < pCpu->param2.size)
729	{
730	AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pCpu), (RTGCPTR)pRegFrame->rip, pCpu->param1.size, pCpu->param2.size)); /* should never happen! */
731	return VERR_EM_INTERPRETER;
732	}
733	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
734	pCpu->param2.size = pCpu->param1.size;
735	param2.size = param1.size;
736	}
737
738	/* The destination is always a virtual address */
739	if (param1.type == PARMTYPE_ADDRESS)
740	{
741	pParam1 = (RTGCPTR)param1.val.val64;
742	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
743	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
744	rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
745	if (RT_FAILURE(rc))
746	{
747	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
748	return VERR_EM_INTERPRETER;
749	}
750	}
751	else
752	{
753	AssertFailed();
754	return VERR_EM_INTERPRETER;
755	}
756
757	/* Register or immediate data */
758	switch(param2.type)
759	{
760	case PARMTYPE_IMMEDIATE: /* both immediate data and register (ugly) */
761	valpar2 = param2.val.val64;
762	break;
763
764	default:
765	AssertFailed();
766	return VERR_EM_INTERPRETER;
767	}
768
769	LogFlow(("emInterpretOrXorAnd %s %RGv %RX64 - %RX64 size %d (%d)\n", emGetMnemonic(pCpu), pParam1, valpar1, valpar2, param2.size, param1.size));
770
771	/* Data read, emulate instruction. */
772	uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
773
774	LogFlow(("emInterpretOrXorAnd %s result %RX64\n", emGetMnemonic(pCpu), valpar1));
775
776	/* Update guest's eflags and finish. */
777	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
778	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
779
780	/* And write it back */
781	rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
782	if (RT_SUCCESS(rc))
783	{
784	/* All done! */
785	*pcbSize = param2.size;
786	return VINF_SUCCESS;
787	}
788	#ifdef IN_RC
789	}
790	}
791	#endif
792	return VERR_EM_INTERPRETER;
793	}
794
795
796	/**
797	* LOCK XOR/OR/AND Emulation.
798	*/
799	static int emInterpretLockOrXorAnd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
800	uint32_t *pcbSize, PFNEMULATELOCKPARAM3 pfnEmulate)
801	{
802	void *pvParam1;
803
804	OP_PARAMVAL param1, param2;
805	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
806	if(RT_FAILURE(rc))
807	return VERR_EM_INTERPRETER;
808
809	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
810	if(RT_FAILURE(rc))
811	return VERR_EM_INTERPRETER;
812
813	if (pCpu->param1.size != pCpu->param2.size)
814	{
815	AssertMsgReturn(pCpu->param1.size >= pCpu->param2.size, /* should never happen! */
816	("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pCpu), (RTGCPTR)pRegFrame->rip, pCpu->param1.size, pCpu->param2.size),
817	VERR_EM_INTERPRETER);
818
819	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
820	pCpu->param2.size = pCpu->param1.size;
821	param2.size = param1.size;
822	}
823
824	/* The destination is always a virtual address */
825	AssertReturn(param1.type == PARMTYPE_ADDRESS, VERR_EM_INTERPRETER);
826
827	RTGCPTR GCPtrPar1 = param1.val.val64;
828	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
829	#ifdef IN_RC
830	pvParam1 = (void *)GCPtrPar1;
831	#else
832	rc = PGMPhysGCPtr2HCPtr(pVM, GCPtrPar1, &pvParam1);
833	if (RT_FAILURE(rc))
834	{
835	AssertRC(rc);
836	return VERR_EM_INTERPRETER;
837	}
838	#endif
839
840	#ifdef IN_RC
841	/* Safety check (in theory it could cross a page boundary and fault there though) */
842	Assert( TRPMHasTrap(pVM)
843	&& (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW));
844	EM_ASSERT_FAULT_RETURN(GCPtrPar1 == pvFault, VERR_EM_INTERPRETER);
845	#endif
846
847	/* Register and immediate data == PARMTYPE_IMMEDIATE */
848	AssertReturn(param2.type == PARMTYPE_IMMEDIATE, VERR_EM_INTERPRETER);
849	RTGCUINTREG ValPar2 = param2.val.val64;
850
851	/* Try emulate it with a one-shot #PF handler in place. */
852	Log2(("%s %RGv imm%d=%RX64\n", emGetMnemonic(pCpu), GCPtrPar1, pCpu->param2.size*8, ValPar2));
853
854	RTGCUINTREG32 eflags = 0;
855	#ifdef IN_RC
856	MMGCRamRegisterTrapHandler(pVM);
857	#endif
858	rc = pfnEmulate(pvParam1, ValPar2, pCpu->param2.size, &eflags);
859	#ifdef IN_RC
860	MMGCRamDeregisterTrapHandler(pVM);
861	#endif
862	if (RT_FAILURE(rc))
863	{
864	Log(("%s %RGv imm%d=%RX64-> emulation failed due to page fault!\n", emGetMnemonic(pCpu), GCPtrPar1, pCpu->param2.size*8, ValPar2));
865	return VERR_EM_INTERPRETER;
866	}
867
868	/* Update guest's eflags and finish. */
869	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
870	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
871
872	*pcbSize = param2.size;
873	return VINF_SUCCESS;
874	}
875
876
877	/**
878	* ADD, ADC & SUB Emulation.
879	*/
880	static int emInterpretAddSub(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
881	PFNEMULATEPARAM3 pfnEmulate)
882	{
883	OP_PARAMVAL param1, param2;
884	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
885	if(RT_FAILURE(rc))
886	return VERR_EM_INTERPRETER;
887
888	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
889	if(RT_FAILURE(rc))
890	return VERR_EM_INTERPRETER;
891
892	#ifdef IN_RC
893	if (TRPMHasTrap(pVM))
894	{
895	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
896	{
897	#endif
898	RTGCPTR pParam1;
899	uint64_t valpar1, valpar2;
900
901	if (pCpu->param1.size != pCpu->param2.size)
902	{
903	if (pCpu->param1.size < pCpu->param2.size)
904	{
905	AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pCpu), (RTGCPTR)pRegFrame->rip, pCpu->param1.size, pCpu->param2.size)); /* should never happen! */
906	return VERR_EM_INTERPRETER;
907	}
908	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
909	pCpu->param2.size = pCpu->param1.size;
910	param2.size = param1.size;
911	}
912
913	/* The destination is always a virtual address */
914	if (param1.type == PARMTYPE_ADDRESS)
915	{
916	pParam1 = (RTGCPTR)param1.val.val64;
917	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
918	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
919	rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
920	if (RT_FAILURE(rc))
921	{
922	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
923	return VERR_EM_INTERPRETER;
924	}
925	}
926	else
927	{
928	#ifndef DEBUG_bird
929	AssertFailed();
930	#endif
931	return VERR_EM_INTERPRETER;
932	}
933
934	/* Register or immediate data */
935	switch(param2.type)
936	{
937	case PARMTYPE_IMMEDIATE: /* both immediate data and register (ugly) */
938	valpar2 = param2.val.val64;
939	break;
940
941	default:
942	AssertFailed();
943	return VERR_EM_INTERPRETER;
944	}
945
946	/* Data read, emulate instruction. */
947	uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
948
949	/* Update guest's eflags and finish. */
950	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
951	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
952
953	/* And write it back */
954	rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
955	if (RT_SUCCESS(rc))
956	{
957	/* All done! */
958	*pcbSize = param2.size;
959	return VINF_SUCCESS;
960	}
961	#ifdef IN_RC
962	}
963	}
964	#endif
965	return VERR_EM_INTERPRETER;
966	}
967
968
969	/**
970	* ADC Emulation.
971	*/
972	static int emInterpretAdc(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
973	{
974	if (pRegFrame->eflags.Bits.u1CF)
975	return emInterpretAddSub(pVM, pCpu, pRegFrame, pvFault, pcbSize, EMEmulateAdcWithCarrySet);
976	else
977	return emInterpretAddSub(pVM, pCpu, pRegFrame, pvFault, pcbSize, EMEmulateAdd);
978	}
979
980
981	/**
982	* BTR/C/S Emulation.
983	*/
984	static int emInterpretBitTest(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
985	PFNEMULATEPARAM2UINT32 pfnEmulate)
986	{
987	OP_PARAMVAL param1, param2;
988	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
989	if(RT_FAILURE(rc))
990	return VERR_EM_INTERPRETER;
991
992	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
993	if(RT_FAILURE(rc))
994	return VERR_EM_INTERPRETER;
995
996	#ifdef IN_RC
997	if (TRPMHasTrap(pVM))
998	{
999	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1000	{
1001	#endif
1002	RTGCPTR pParam1;
1003	uint64_t valpar1 = 0, valpar2;
1004	uint32_t eflags;
1005
1006	/* The destination is always a virtual address */
1007	if (param1.type != PARMTYPE_ADDRESS)
1008	return VERR_EM_INTERPRETER;
1009
1010	pParam1 = (RTGCPTR)param1.val.val64;
1011	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
1012
1013	/* Register or immediate data */
1014	switch(param2.type)
1015	{
1016	case PARMTYPE_IMMEDIATE: /* both immediate data and register (ugly) */
1017	valpar2 = param2.val.val64;
1018	break;
1019
1020	default:
1021	AssertFailed();
1022	return VERR_EM_INTERPRETER;
1023	}
1024
1025	Log2(("emInterpret%s: pvFault=%RGv pParam1=%RGv val2=%x\n", emGetMnemonic(pCpu), pvFault, pParam1, valpar2));
1026	pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + valpar2/8);
1027	EM_ASSERT_FAULT_RETURN((RTGCPTR)((RTGCUINTPTR)pParam1 & ~3) == pvFault, VERR_EM_INTERPRETER);
1028	rc = emRamRead(pVM, &valpar1, pParam1, 1);
1029	if (RT_FAILURE(rc))
1030	{
1031	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
1032	return VERR_EM_INTERPRETER;
1033	}
1034
1035	Log2(("emInterpretBtx: val=%x\n", valpar1));
1036	/* Data read, emulate bit test instruction. */
1037	eflags = pfnEmulate(&valpar1, valpar2 & 0x7);
1038
1039	Log2(("emInterpretBtx: val=%x CF=%d\n", valpar1, !!(eflags & X86_EFL_CF)));
1040
1041	/* Update guest's eflags and finish. */
1042	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1043	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1044
1045	/* And write it back */
1046	rc = emRamWrite(pVM, pParam1, &valpar1, 1);
1047	if (RT_SUCCESS(rc))
1048	{
1049	/* All done! */
1050	*pcbSize = 1;
1051	return VINF_SUCCESS;
1052	}
1053	#ifdef IN_RC
1054	}
1055	}
1056	#endif
1057	return VERR_EM_INTERPRETER;
1058	}
1059
1060
1061	/**
1062	* LOCK BTR/C/S Emulation.
1063	*/
1064	static int emInterpretLockBitTest(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
1065	uint32_t *pcbSize, PFNEMULATELOCKPARAM2 pfnEmulate)
1066	{
1067	void *pvParam1;
1068
1069	OP_PARAMVAL param1, param2;
1070	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
1071	if(RT_FAILURE(rc))
1072	return VERR_EM_INTERPRETER;
1073
1074	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1075	if(RT_FAILURE(rc))
1076	return VERR_EM_INTERPRETER;
1077
1078	/* The destination is always a virtual address */
1079	if (param1.type != PARMTYPE_ADDRESS)
1080	return VERR_EM_INTERPRETER;
1081
1082	/* Register and immediate data == PARMTYPE_IMMEDIATE */
1083	AssertReturn(param2.type == PARMTYPE_IMMEDIATE, VERR_EM_INTERPRETER);
1084	uint64_t ValPar2 = param2.val.val64;
1085
1086	/* Adjust the parameters so what we're dealing with is a bit within the byte pointed to. */
1087	RTGCPTR GCPtrPar1 = param1.val.val64;
1088	GCPtrPar1 = (GCPtrPar1 + ValPar2 / 8);
1089	ValPar2 &= 7;
1090
1091	#ifdef IN_RC
1092	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
1093	pvParam1 = (void *)GCPtrPar1;
1094	#else
1095	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
1096	rc = PGMPhysGCPtr2HCPtr(pVM, GCPtrPar1, &pvParam1);
1097	if (RT_FAILURE(rc))
1098	{
1099	AssertRC(rc);
1100	return VERR_EM_INTERPRETER;
1101	}
1102	#endif
1103
1104	Log2(("emInterpretLockBitTest %s: pvFault=%RGv GCPtrPar1=%RGv imm=%RX64\n", emGetMnemonic(pCpu), pvFault, GCPtrPar1, ValPar2));
1105
1106	#ifdef IN_RC
1107	Assert(TRPMHasTrap(pVM));
1108	EM_ASSERT_FAULT_RETURN((RTGCPTR)((RTGCUINTPTR)GCPtrPar1 & ~(RTGCUINTPTR)3) == pvFault, VERR_EM_INTERPRETER);
1109	#endif
1110
1111	/* Try emulate it with a one-shot #PF handler in place. */
1112	RTGCUINTREG32 eflags = 0;
1113	#ifdef IN_RC
1114	MMGCRamRegisterTrapHandler(pVM);
1115	#endif
1116	rc = pfnEmulate(pvParam1, ValPar2, &eflags);
1117	#ifdef IN_RC
1118	MMGCRamDeregisterTrapHandler(pVM);
1119	#endif
1120	if (RT_FAILURE(rc))
1121	{
1122	Log(("emInterpretLockBitTest %s: %RGv imm%d=%RX64 -> emulation failed due to page fault!\n",
1123	emGetMnemonic(pCpu), GCPtrPar1, pCpu->param2.size*8, ValPar2));
1124	return VERR_EM_INTERPRETER;
1125	}
1126
1127	Log2(("emInterpretLockBitTest %s: GCPtrPar1=%RGv imm=%RX64 CF=%d\n", emGetMnemonic(pCpu), GCPtrPar1, ValPar2, !!(eflags & X86_EFL_CF)));
1128
1129	/* Update guest's eflags and finish. */
1130	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1131	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1132
1133	*pcbSize = 1;
1134	return VINF_SUCCESS;
1135	}
1136
1137
1138	/**
1139	* MOV emulation.
1140	*/
1141	static int emInterpretMov(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1142	{
1143	OP_PARAMVAL param1, param2;
1144	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
1145	if(RT_FAILURE(rc))
1146	return VERR_EM_INTERPRETER;
1147
1148	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1149	if(RT_FAILURE(rc))
1150	return VERR_EM_INTERPRETER;
1151
1152	#ifdef IN_RC
1153	if (TRPMHasTrap(pVM))
1154	{
1155	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1156	{
1157	#else
1158	/** @todo Make this the default and don't rely on TRPM information. */
1159	if (param1.type == PARMTYPE_ADDRESS)
1160	{
1161	#endif
1162	RTGCPTR pDest;
1163	uint64_t val64;
1164
1165	switch(param1.type)
1166	{
1167	case PARMTYPE_IMMEDIATE:
1168	if(!(param1.flags & (PARAM_VAL32\|PARAM_VAL64)))
1169	return VERR_EM_INTERPRETER;
1170	/* fallthru */
1171
1172	case PARMTYPE_ADDRESS:
1173	pDest = (RTGCPTR)param1.val.val64;
1174	pDest = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pDest);
1175	break;
1176
1177	default:
1178	AssertFailed();
1179	return VERR_EM_INTERPRETER;
1180	}
1181
1182	switch(param2.type)
1183	{
1184	case PARMTYPE_IMMEDIATE: /* register type is translated to this one too */
1185	val64 = param2.val.val64;
1186	break;
1187
1188	default:
1189	Log(("emInterpretMov: unexpected type=%d rip=%RGv\n", param2.type, (RTGCPTR)pRegFrame->rip));
1190	return VERR_EM_INTERPRETER;
1191	}
1192	#ifdef LOG_ENABLED
1193	if (pCpu->mode == CPUMODE_64BIT)
1194	LogFlow(("EMInterpretInstruction at %RGv: OP_MOV %RGv <- %RX64 (%d) &val64=%RHv\n", (RTGCPTR)pRegFrame->rip, pDest, val64, param2.size, &val64));
1195	else
1196	LogFlow(("EMInterpretInstruction at %08RX64: OP_MOV %RGv <- %08X (%d) &val64=%RHv\n", pRegFrame->rip, pDest, (uint32_t)val64, param2.size, &val64));
1197	#endif
1198
1199	Assert(param2.size <= 8 && param2.size > 0);
1200	EM_ASSERT_FAULT_RETURN(pDest == pvFault, VERR_EM_INTERPRETER);
1201	rc = emRamWrite(pVM, pDest, &val64, param2.size);
1202	if (RT_FAILURE(rc))
1203	return VERR_EM_INTERPRETER;
1204
1205	*pcbSize = param2.size;
1206	}
1207	else
1208	{ /* read fault */
1209	RTGCPTR pSrc;
1210	uint64_t val64;
1211
1212	/* Source */
1213	switch(param2.type)
1214	{
1215	case PARMTYPE_IMMEDIATE:
1216	if(!(param2.flags & (PARAM_VAL32\|PARAM_VAL64)))
1217	return VERR_EM_INTERPRETER;
1218	/* fallthru */
1219
1220	case PARMTYPE_ADDRESS:
1221	pSrc = (RTGCPTR)param2.val.val64;
1222	pSrc = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param2, pSrc);
1223	break;
1224
1225	default:
1226	return VERR_EM_INTERPRETER;
1227	}
1228
1229	Assert(param1.size <= 8 && param1.size > 0);
1230	EM_ASSERT_FAULT_RETURN(pSrc == pvFault, VERR_EM_INTERPRETER);
1231	rc = emRamRead(pVM, &val64, pSrc, param1.size);
1232	if (RT_FAILURE(rc))
1233	return VERR_EM_INTERPRETER;
1234
1235	/* Destination */
1236	switch(param1.type)
1237	{
1238	case PARMTYPE_REGISTER:
1239	switch(param1.size)
1240	{
1241	case 1: rc = DISWriteReg8(pRegFrame, pCpu->param1.base.reg_gen, (uint8_t) val64); break;
1242	case 2: rc = DISWriteReg16(pRegFrame, pCpu->param1.base.reg_gen, (uint16_t)val64); break;
1243	case 4: rc = DISWriteReg32(pRegFrame, pCpu->param1.base.reg_gen, (uint32_t)val64); break;
1244	case 8: rc = DISWriteReg64(pRegFrame, pCpu->param1.base.reg_gen, val64); break;
1245	default:
1246	return VERR_EM_INTERPRETER;
1247	}
1248	if (RT_FAILURE(rc))
1249	return rc;
1250	break;
1251
1252	default:
1253	return VERR_EM_INTERPRETER;
1254	}
1255	#ifdef LOG_ENABLED
1256	if (pCpu->mode == CPUMODE_64BIT)
1257	LogFlow(("EMInterpretInstruction: OP_MOV %RGv -> %RX64 (%d)\n", pSrc, val64, param1.size));
1258	else
1259	LogFlow(("EMInterpretInstruction: OP_MOV %RGv -> %08X (%d)\n", pSrc, (uint32_t)val64, param1.size));
1260	#endif
1261	}
1262	return VINF_SUCCESS;
1263	#ifdef IN_RC
1264	}
1265	#endif
1266	return VERR_EM_INTERPRETER;
1267	}
1268
1269
1270	#ifndef IN_RC
1271	/**
1272	* [REP] STOSWD emulation
1273	*/
1274	static int emInterpretStosWD(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1275	{
1276	int rc;
1277	RTGCPTR GCDest, GCOffset;
1278	uint32_t cbSize;
1279	uint64_t cTransfers;
1280	int offIncrement;
1281
1282	/* Don't support any but these three prefix bytes. */
1283	if ((pCpu->prefix & ~(PREFIX_ADDRSIZE\|PREFIX_OPSIZE\|PREFIX_REP\|PREFIX_REX)))
1284	return VERR_EM_INTERPRETER;
1285
1286	switch (pCpu->addrmode)
1287	{
1288	case CPUMODE_16BIT:
1289	GCOffset = pRegFrame->di;
1290	cTransfers = pRegFrame->cx;
1291	break;
1292	case CPUMODE_32BIT:
1293	GCOffset = pRegFrame->edi;
1294	cTransfers = pRegFrame->ecx;
1295	break;
1296	case CPUMODE_64BIT:
1297	GCOffset = pRegFrame->rdi;
1298	cTransfers = pRegFrame->rcx;
1299	break;
1300	default:
1301	AssertFailed();
1302	return VERR_EM_INTERPRETER;
1303	}
1304
1305	GCDest = SELMToFlat(pVM, DIS_SELREG_ES, pRegFrame, GCOffset);
1306	switch (pCpu->opmode)
1307	{
1308	case CPUMODE_16BIT:
1309	cbSize = 2;
1310	break;
1311	case CPUMODE_32BIT:
1312	cbSize = 4;
1313	break;
1314	case CPUMODE_64BIT:
1315	cbSize = 8;
1316	break;
1317	default:
1318	AssertFailed();
1319	return VERR_EM_INTERPRETER;
1320	}
1321
1322	offIncrement = pRegFrame->eflags.Bits.u1DF ? -(signed)cbSize : (signed)cbSize;
1323
1324	if (!(pCpu->prefix & PREFIX_REP))
1325	{
1326	LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d\n", pRegFrame->es, GCOffset, GCDest, cbSize));
1327
1328	rc = PGMPhysWriteGCPtr(pVM, GCDest, &pRegFrame->rax, cbSize);
1329	if (RT_FAILURE(rc))
1330	return VERR_EM_INTERPRETER;
1331	Assert(rc == VINF_SUCCESS);
1332
1333	/* Update (e/r)di. */
1334	switch (pCpu->addrmode)
1335	{
1336	case CPUMODE_16BIT:
1337	pRegFrame->di += offIncrement;
1338	break;
1339	case CPUMODE_32BIT:
1340	pRegFrame->edi += offIncrement;
1341	break;
1342	case CPUMODE_64BIT:
1343	pRegFrame->rdi += offIncrement;
1344	break;
1345	default:
1346	AssertFailed();
1347	return VERR_EM_INTERPRETER;
1348	}
1349
1350	}
1351	else
1352	{
1353	if (!cTransfers)
1354	return VINF_SUCCESS;
1355
1356	LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d cTransfers=%x DF=%d\n", pRegFrame->es, GCOffset, GCDest, cbSize, cTransfers, pRegFrame->eflags.Bits.u1DF));
1357	/* Access verification first; we currently can't recover properly from traps inside this instruction */
1358	rc = PGMVerifyAccess(pVM, GCDest - ((offIncrement > 0) ? 0 : ((cTransfers-1) * cbSize)), cTransfers * cbSize, X86_PTE_RW \| X86_PTE_US);
1359	if (rc != VINF_SUCCESS)
1360	{
1361	Log(("STOSWD will generate a trap -> recompiler, rc=%d\n", rc));
1362	return VERR_EM_INTERPRETER;
1363	}
1364
1365	/* REP case */
1366	while (cTransfers)
1367	{
1368	rc = PGMPhysWriteGCPtr(pVM, GCDest, &pRegFrame->rax, cbSize);
1369	if (RT_FAILURE(rc))
1370	{
1371	rc = VERR_EM_INTERPRETER;
1372	break;
1373	}
1374
1375	Assert(rc == VINF_SUCCESS);
1376	GCOffset += offIncrement;
1377	GCDest += offIncrement;
1378	cTransfers--;
1379	}
1380
1381	/* Update the registers. */
1382	switch (pCpu->addrmode)
1383	{
1384	case CPUMODE_16BIT:
1385	pRegFrame->di = GCOffset;
1386	pRegFrame->cx = cTransfers;
1387	break;
1388	case CPUMODE_32BIT:
1389	pRegFrame->edi = GCOffset;
1390	pRegFrame->ecx = cTransfers;
1391	break;
1392	case CPUMODE_64BIT:
1393	pRegFrame->rdi = GCOffset;
1394	pRegFrame->rcx = cTransfers;
1395	break;
1396	default:
1397	AssertFailed();
1398	return VERR_EM_INTERPRETER;
1399	}
1400	}
1401
1402	*pcbSize = cbSize;
1403	return rc;
1404	}
1405	#endif /* !IN_RC */
1406
1407	#ifndef IN_RC
1408
1409	/**
1410	* [LOCK] CMPXCHG emulation.
1411	*/
1412	static int emInterpretCmpXchg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1413	{
1414	OP_PARAMVAL param1, param2;
1415
1416	/* Source to make DISQueryParamVal read the register value - ugly hack */
1417	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1418	if(RT_FAILURE(rc))
1419	return VERR_EM_INTERPRETER;
1420
1421	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1422	if(RT_FAILURE(rc))
1423	return VERR_EM_INTERPRETER;
1424
1425	RTGCPTR GCPtrPar1;
1426	void *pvParam1;
1427	uint64_t valpar, eflags;
1428
1429	AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
1430	switch(param1.type)
1431	{
1432	case PARMTYPE_ADDRESS:
1433	GCPtrPar1 = param1.val.val64;
1434	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
1435
1436	rc = PGMPhysGCPtr2HCPtr(pVM, GCPtrPar1, &pvParam1);
1437	if (RT_FAILURE(rc))
1438	{
1439	AssertRC(rc);
1440	return VERR_EM_INTERPRETER;
1441	}
1442	break;
1443
1444	default:
1445	return VERR_EM_INTERPRETER;
1446	}
1447
1448	switch(param2.type)
1449	{
1450	case PARMTYPE_IMMEDIATE: /* register actually */
1451	valpar = param2.val.val64;
1452	break;
1453
1454	default:
1455	return VERR_EM_INTERPRETER;
1456	}
1457
1458	LogFlow(("%s %RGv rax=%RX64 %RX64\n", emGetMnemonic(pCpu), GCPtrPar1, pRegFrame->rax, valpar));
1459
1460	if (pCpu->prefix & PREFIX_LOCK)
1461	eflags = EMEmulateLockCmpXchg(pvParam1, &pRegFrame->rax, valpar, pCpu->param2.size);
1462	else
1463	eflags = EMEmulateCmpXchg(pvParam1, &pRegFrame->rax, valpar, pCpu->param2.size);
1464
1465	LogFlow(("%s %RGv rax=%RX64 %RX64 ZF=%d\n", emGetMnemonic(pCpu), GCPtrPar1, pRegFrame->rax, valpar, !!(eflags & X86_EFL_ZF)));
1466
1467	/* Update guest's eflags and finish. */
1468	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1469	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1470
1471	*pcbSize = param2.size;
1472	return VINF_SUCCESS;
1473	}
1474
1475
1476	/**
1477	* [LOCK] CMPXCHG8B emulation.
1478	*/
1479	static int emInterpretCmpXchg8b(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1480	{
1481	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
1482	OP_PARAMVAL param1;
1483
1484	/* Source to make DISQueryParamVal read the register value - ugly hack */
1485	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1486	if(RT_FAILURE(rc))
1487	return VERR_EM_INTERPRETER;
1488
1489	RTGCPTR GCPtrPar1;
1490	void *pvParam1;
1491	uint64_t eflags;
1492
1493	AssertReturn(pCpu->param1.size == 8, VERR_EM_INTERPRETER);
1494	switch(param1.type)
1495	{
1496	case PARMTYPE_ADDRESS:
1497	GCPtrPar1 = param1.val.val64;
1498	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
1499
1500	rc = PGMPhysGCPtr2HCPtr(pVM, GCPtrPar1, &pvParam1);
1501	if (RT_FAILURE(rc))
1502	{
1503	AssertRC(rc);
1504	return VERR_EM_INTERPRETER;
1505	}
1506	break;
1507
1508	default:
1509	return VERR_EM_INTERPRETER;
1510	}
1511
1512	LogFlow(("%s %RGv=%08x eax=%08x\n", emGetMnemonic(pCpu), pvParam1, pRegFrame->eax));
1513
1514	if (pCpu->prefix & PREFIX_LOCK)
1515	eflags = EMEmulateLockCmpXchg8b(pvParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
1516	else
1517	eflags = EMEmulateCmpXchg8b(pvParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
1518
1519	LogFlow(("%s %RGv=%08x eax=%08x ZF=%d\n", emGetMnemonic(pCpu), pvParam1, pRegFrame->eax, !!(eflags & X86_EFL_ZF)));
1520
1521	/* Update guest's eflags and finish; note that only ZF is affected. */
1522	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_ZF))
1523	\| (eflags & (X86_EFL_ZF));
1524
1525	*pcbSize = 8;
1526	return VINF_SUCCESS;
1527	}
1528
1529	#else /* IN_RC */
1530
1531	/**
1532	* [LOCK] CMPXCHG emulation.
1533	*/
1534	static int emInterpretCmpXchg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1535	{
1536	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
1537	OP_PARAMVAL param1, param2;
1538
1539	/* Source to make DISQueryParamVal read the register value - ugly hack */
1540	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1541	if(RT_FAILURE(rc))
1542	return VERR_EM_INTERPRETER;
1543
1544	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1545	if(RT_FAILURE(rc))
1546	return VERR_EM_INTERPRETER;
1547
1548	if (TRPMHasTrap(pVM))
1549	{
1550	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1551	{
1552	RTRCPTR pParam1;
1553	uint32_t valpar, eflags;
1554
1555	AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
1556	switch(param1.type)
1557	{
1558	case PARMTYPE_ADDRESS:
1559	pParam1 = (RTRCPTR)param1.val.val64;
1560	pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);
1561	EM_ASSERT_FAULT_RETURN(pParam1 == (RTRCPTR)pvFault, VERR_EM_INTERPRETER);
1562	break;
1563
1564	default:
1565	return VERR_EM_INTERPRETER;
1566	}
1567
1568	switch(param2.type)
1569	{
1570	case PARMTYPE_IMMEDIATE: /* register actually */
1571	valpar = param2.val.val32;
1572	break;
1573
1574	default:
1575	return VERR_EM_INTERPRETER;
1576	}
1577
1578	LogFlow(("%s %RRv eax=%08x %08x\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax, valpar));
1579
1580	MMGCRamRegisterTrapHandler(pVM);
1581	if (pCpu->prefix & PREFIX_LOCK)
1582	rc = EMGCEmulateLockCmpXchg(pParam1, &pRegFrame->eax, valpar, pCpu->param2.size, &eflags);
1583	else
1584	rc = EMGCEmulateCmpXchg(pParam1, &pRegFrame->eax, valpar, pCpu->param2.size, &eflags);
1585	MMGCRamDeregisterTrapHandler(pVM);
1586
1587	if (RT_FAILURE(rc))
1588	{
1589	Log(("%s %RGv eax=%08x %08x -> emulation failed due to page fault!\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax, valpar));
1590	return VERR_EM_INTERPRETER;
1591	}
1592
1593	LogFlow(("%s %RRv eax=%08x %08x ZF=%d\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax, valpar, !!(eflags & X86_EFL_ZF)));
1594
1595	/* Update guest's eflags and finish. */
1596	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1597	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1598
1599	*pcbSize = param2.size;
1600	return VINF_SUCCESS;
1601	}
1602	}
1603	return VERR_EM_INTERPRETER;
1604	}
1605
1606
1607	/**
1608	* [LOCK] CMPXCHG8B emulation.
1609	*/
1610	static int emInterpretCmpXchg8b(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1611	{
1612	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
1613	OP_PARAMVAL param1;
1614
1615	/* Source to make DISQueryParamVal read the register value - ugly hack */
1616	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1617	if(RT_FAILURE(rc))
1618	return VERR_EM_INTERPRETER;
1619
1620	if (TRPMHasTrap(pVM))
1621	{
1622	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1623	{
1624	RTRCPTR pParam1;
1625	uint32_t eflags;
1626
1627	AssertReturn(pCpu->param1.size == 8, VERR_EM_INTERPRETER);
1628	switch(param1.type)
1629	{
1630	case PARMTYPE_ADDRESS:
1631	pParam1 = (RTRCPTR)param1.val.val64;
1632	pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);
1633	EM_ASSERT_FAULT_RETURN(pParam1 == (RTRCPTR)pvFault, VERR_EM_INTERPRETER);
1634	break;
1635
1636	default:
1637	return VERR_EM_INTERPRETER;
1638	}
1639
1640	LogFlow(("%s %RRv=%08x eax=%08x\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax));
1641
1642	MMGCRamRegisterTrapHandler(pVM);
1643	if (pCpu->prefix & PREFIX_LOCK)
1644	rc = EMGCEmulateLockCmpXchg8b(pParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx, &eflags);
1645	else
1646	rc = EMGCEmulateCmpXchg8b(pParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx, &eflags);
1647	MMGCRamDeregisterTrapHandler(pVM);
1648
1649	if (RT_FAILURE(rc))
1650	{
1651	Log(("%s %RGv=%08x eax=%08x -> emulation failed due to page fault!\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax));
1652	return VERR_EM_INTERPRETER;
1653	}
1654
1655	LogFlow(("%s %RGv=%08x eax=%08x ZF=%d\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax, !!(eflags & X86_EFL_ZF)));
1656
1657	/* Update guest's eflags and finish; note that only ZF is affected. */
1658	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_ZF))
1659	\| (eflags & (X86_EFL_ZF));
1660
1661	*pcbSize = 8;
1662	return VINF_SUCCESS;
1663	}
1664	}
1665	return VERR_EM_INTERPRETER;
1666	}
1667
1668	#endif /* IN_RC */
1669
1670	#ifdef IN_RC
1671	/**
1672	* [LOCK] XADD emulation.
1673	*/
1674	static int emInterpretXAdd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1675	{
1676	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
1677	OP_PARAMVAL param1;
1678	uint32_t *pParamReg2;
1679	size_t cbSizeParamReg2;
1680
1681	/* Source to make DISQueryParamVal read the register value - ugly hack */
1682	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1683	if(RT_FAILURE(rc))
1684	return VERR_EM_INTERPRETER;
1685
1686	rc = DISQueryParamRegPtr(pRegFrame, pCpu, &pCpu->param2, (void **)&pParamReg2, &cbSizeParamReg2);
1687	Assert(cbSizeParamReg2 <= 4);
1688	if(RT_FAILURE(rc))
1689	return VERR_EM_INTERPRETER;
1690
1691	if (TRPMHasTrap(pVM))
1692	{
1693	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1694	{
1695	RTRCPTR pParam1;
1696	uint32_t eflags;
1697
1698	AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
1699	switch(param1.type)
1700	{
1701	case PARMTYPE_ADDRESS:
1702	pParam1 = (RTRCPTR)param1.val.val64;
1703	pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);
1704	EM_ASSERT_FAULT_RETURN(pParam1 == (RTRCPTR)pvFault, VERR_EM_INTERPRETER);
1705	break;
1706
1707	default:
1708	return VERR_EM_INTERPRETER;
1709	}
1710
1711	LogFlow(("XAdd %RRv=%08x reg=%08x\n", pParam1, *pParamReg2));
1712
1713	MMGCRamRegisterTrapHandler(pVM);
1714	if (pCpu->prefix & PREFIX_LOCK)
1715	rc = EMGCEmulateLockXAdd(pParam1, pParamReg2, cbSizeParamReg2, &eflags);
1716	else
1717	rc = EMGCEmulateXAdd(pParam1, pParamReg2, cbSizeParamReg2, &eflags);
1718	MMGCRamDeregisterTrapHandler(pVM);
1719
1720	if (RT_FAILURE(rc))
1721	{
1722	Log(("XAdd %RGv reg=%08x -> emulation failed due to page fault!\n", pParam1, *pParamReg2));
1723	return VERR_EM_INTERPRETER;
1724	}
1725
1726	LogFlow(("XAdd %RGv reg=%08x ZF=%d\n", pParam1, *pParamReg2, !!(eflags & X86_EFL_ZF)));
1727
1728	/* Update guest's eflags and finish. */
1729	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1730	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1731
1732	*pcbSize = cbSizeParamReg2;
1733	return VINF_SUCCESS;
1734	}
1735	}
1736	return VERR_EM_INTERPRETER;
1737	}
1738	#endif /* IN_RC */
1739
1740
1741	#ifdef IN_RC
1742	/**
1743	* Interpret IRET (currently only to V86 code)
1744	*
1745	* @returns VBox status code.
1746	* @param pVM The VM handle.
1747	* @param pRegFrame The register frame.
1748	*
1749	*/
1750	VMMDECL(int) EMInterpretIret(PVM pVM, PCPUMCTXCORE pRegFrame)
1751	{
1752	RTGCUINTPTR pIretStack = (RTGCUINTPTR)pRegFrame->esp;
1753	RTGCUINTPTR eip, cs, esp, ss, eflags, ds, es, fs, gs, uMask;
1754	int rc;
1755
1756	Assert(!CPUMIsGuestIn64BitCode(pVM, pRegFrame));
1757
1758	rc = emRamRead(pVM, &eip, (RTGCPTR)pIretStack , 4);
1759	rc \|= emRamRead(pVM, &cs, (RTGCPTR)(pIretStack + 4), 4);
1760	rc \|= emRamRead(pVM, &eflags, (RTGCPTR)(pIretStack + 8), 4);
1761	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1762	AssertReturn(eflags & X86_EFL_VM, VERR_EM_INTERPRETER);
1763
1764	rc \|= emRamRead(pVM, &esp, (RTGCPTR)(pIretStack + 12), 4);
1765	rc \|= emRamRead(pVM, &ss, (RTGCPTR)(pIretStack + 16), 4);
1766	rc \|= emRamRead(pVM, &es, (RTGCPTR)(pIretStack + 20), 4);
1767	rc \|= emRamRead(pVM, &ds, (RTGCPTR)(pIretStack + 24), 4);
1768	rc \|= emRamRead(pVM, &fs, (RTGCPTR)(pIretStack + 28), 4);
1769	rc \|= emRamRead(pVM, &gs, (RTGCPTR)(pIretStack + 32), 4);
1770	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1771
1772	pRegFrame->eip = eip & 0xffff;
1773	pRegFrame->cs = cs;
1774
1775	/* Mask away all reserved bits */
1776	uMask = X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_RF \| X86_EFL_VM \| X86_EFL_AC \| X86_EFL_VIF \| X86_EFL_VIP \| X86_EFL_ID;
1777	eflags &= uMask;
1778
1779	#ifndef IN_RING0
1780	CPUMRawSetEFlags(pVM, pRegFrame, eflags);
1781	#endif
1782	Assert((pRegFrame->eflags.u32 & (X86_EFL_IF\|X86_EFL_IOPL)) == X86_EFL_IF);
1783
1784	pRegFrame->esp = esp;
1785	pRegFrame->ss = ss;
1786	pRegFrame->ds = ds;
1787	pRegFrame->es = es;
1788	pRegFrame->fs = fs;
1789	pRegFrame->gs = gs;
1790
1791	return VINF_SUCCESS;
1792	}
1793	#endif /* IN_RC */
1794
1795
1796	/**
1797	* IRET Emulation.
1798	*/
1799	static int emInterpretIret(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1800	{
1801	/* only allow direct calls to EMInterpretIret for now */
1802	return VERR_EM_INTERPRETER;
1803	}
1804
1805	/**
1806	* WBINVD Emulation.
1807	*/
1808	static int emInterpretWbInvd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1809	{
1810	/* Nothing to do. */
1811	return VINF_SUCCESS;
1812	}
1813
1814
1815	/**
1816	* Interpret INVLPG
1817	*
1818	* @returns VBox status code.
1819	* @param pVM The VM handle.
1820	* @param pRegFrame The register frame.
1821	* @param pAddrGC Operand address
1822	*
1823	*/
1824	VMMDECL(int) EMInterpretInvlpg(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC)
1825	{
1826	int rc;
1827
1828	/** @todo is addr always a flat linear address or ds based
1829	* (in absence of segment override prefixes)????
1830	*/
1831	#ifdef IN_RC
1832	LogFlow(("RC: EMULATE: invlpg %RGv\n", pAddrGC));
1833	#endif
1834	rc = PGMInvalidatePage(pVM, pAddrGC);
1835	if ( rc == VINF_SUCCESS
1836	\|\| rc == VINF_PGM_SYNC_CR3 /* we can rely on the FF */)
1837	return VINF_SUCCESS;
1838	AssertMsgReturn( rc == VERR_REM_FLUSHED_PAGES_OVERFLOW
1839	\|\| rc == VINF_EM_RAW_EMULATE_INSTR,
1840	("%Rrc addr=%RGv\n", rc, pAddrGC),
1841	VERR_EM_INTERPRETER);
1842	return rc;
1843	}
1844
1845
1846	/**
1847	* INVLPG Emulation.
1848	*/
1849	static int emInterpretInvlPg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1850	{
1851	OP_PARAMVAL param1;
1852	RTGCPTR addr;
1853
1854	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1855	if(RT_FAILURE(rc))
1856	return VERR_EM_INTERPRETER;
1857
1858	switch(param1.type)
1859	{
1860	case PARMTYPE_IMMEDIATE:
1861	case PARMTYPE_ADDRESS:
1862	if(!(param1.flags & (PARAM_VAL32\|PARAM_VAL64)))
1863	return VERR_EM_INTERPRETER;
1864	addr = (RTGCPTR)param1.val.val64;
1865	break;
1866
1867	default:
1868	return VERR_EM_INTERPRETER;
1869	}
1870
1871	/** @todo is addr always a flat linear address or ds based
1872	* (in absence of segment override prefixes)????
1873	*/
1874	#ifdef IN_RC
1875	LogFlow(("RC: EMULATE: invlpg %RGv\n", addr));
1876	#endif
1877	rc = PGMInvalidatePage(pVM, addr);
1878	if ( rc == VINF_SUCCESS
1879	\|\| rc == VINF_PGM_SYNC_CR3 /* we can rely on the FF */)
1880	return VINF_SUCCESS;
1881	AssertMsgReturn( rc == VERR_REM_FLUSHED_PAGES_OVERFLOW
1882	\|\| rc == VINF_EM_RAW_EMULATE_INSTR,
1883	("%Rrc addr=%RGv\n", rc, addr),
1884	VERR_EM_INTERPRETER);
1885	return rc;
1886	}
1887
1888
1889	/**
1890	* Interpret CPUID given the parameters in the CPU context
1891	*
1892	* @returns VBox status code.
1893	* @param pVM The VM handle.
1894	* @param pRegFrame The register frame.
1895	*
1896	*/
1897	VMMDECL(int) EMInterpretCpuId(PVM pVM, PCPUMCTXCORE pRegFrame)
1898	{
1899	uint32_t iLeaf = pRegFrame->eax;
1900
1901	/* cpuid clears the high dwords of the affected 64 bits registers. */
1902	pRegFrame->rax = 0;
1903	pRegFrame->rbx = 0;
1904	pRegFrame->rcx = 0;
1905	pRegFrame->rdx = 0;
1906
1907	/* Note: operates the same in 64 and non-64 bits mode. */
1908	CPUMGetGuestCpuId(pVM, iLeaf, &pRegFrame->eax, &pRegFrame->ebx, &pRegFrame->ecx, &pRegFrame->edx);
1909	Log(("Emulate: CPUID %x -> %08x %08x %08x %08x\n", iLeaf, pRegFrame->eax, pRegFrame->ebx, pRegFrame->ecx, pRegFrame->edx));
1910	return VINF_SUCCESS;
1911	}
1912
1913
1914	/**
1915	* CPUID Emulation.
1916	*/
1917	static int emInterpretCpuId(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1918	{
1919	int rc = EMInterpretCpuId(pVM, pRegFrame);
1920	return rc;
1921	}
1922
1923
1924	/**
1925	* Interpret CRx read
1926	*
1927	* @returns VBox status code.
1928	* @param pVM The VM handle.
1929	* @param pRegFrame The register frame.
1930	* @param DestRegGen General purpose register index (USE_REG_E**))
1931	* @param SrcRegCRx CRx register index (USE_REG_CR*)
1932	*
1933	*/
1934	VMMDECL(int) EMInterpretCRxRead(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx)
1935	{
1936	int rc;
1937	uint64_t val64;
1938
1939	if (SrcRegCrx == USE_REG_CR8)
1940	{
1941	val64 = 0;
1942	rc = PDMApicGetTPR(pVM, (uint8_t *)&val64, NULL);
1943	AssertMsgRCReturn(rc, ("PDMApicGetTPR failed\n"), VERR_EM_INTERPRETER);
1944	}
1945	else
1946	{
1947	rc = CPUMGetGuestCRx(pVM, SrcRegCrx, &val64);
1948	AssertMsgRCReturn(rc, ("CPUMGetGuestCRx %d failed\n", SrcRegCrx), VERR_EM_INTERPRETER);
1949	}
1950
1951	if (CPUMIsGuestIn64BitCode(pVM, pRegFrame))
1952	rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
1953	else
1954	rc = DISWriteReg32(pRegFrame, DestRegGen, val64);
1955
1956	if(RT_SUCCESS(rc))
1957	{
1958	LogFlow(("MOV_CR: gen32=%d CR=%d val=%RX64\n", DestRegGen, SrcRegCrx, val64));
1959	return VINF_SUCCESS;
1960	}
1961	return VERR_EM_INTERPRETER;
1962	}
1963
1964
1965
1966	/**
1967	* Interpret CLTS
1968	*
1969	* @returns VBox status code.
1970	* @param pVM The VM handle.
1971	*
1972	*/
1973	VMMDECL(int) EMInterpretCLTS(PVM pVM)
1974	{
1975	uint64_t cr0 = CPUMGetGuestCR0(pVM);
1976	if (!(cr0 & X86_CR0_TS))
1977	return VINF_SUCCESS;
1978	return CPUMSetGuestCR0(pVM, cr0 & ~X86_CR0_TS);
1979	}
1980
1981	/**
1982	* CLTS Emulation.
1983	*/
1984	static int emInterpretClts(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1985	{
1986	return EMInterpretCLTS(pVM);
1987	}
1988
1989
1990	/**
1991	* Update CRx
1992	*
1993	* @returns VBox status code.
1994	* @param pVM The VM handle.
1995	* @param pRegFrame The register frame.
1996	* @param DestRegCRx CRx register index (USE_REG_CR*)
1997	* @param val New CRx value
1998	*
1999	*/
2000	static int EMUpdateCRx(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint64_t val)
2001	{
2002	uint64_t oldval;
2003	uint64_t msrEFER;
2004	int rc;
2005
2006	/** @todo Clean up this mess. */
2007	LogFlow(("EMInterpretCRxWrite at %RGv CR%d <- %RX64\n", (RTGCPTR)pRegFrame->rip, DestRegCrx, val));
2008	switch (DestRegCrx)
2009	{
2010	case USE_REG_CR0:
2011	oldval = CPUMGetGuestCR0(pVM);
2012	#ifdef IN_RC
2013	/* CR0.WP and CR0.AM changes require a reschedule run in ring 3. */
2014	if ( (val & (X86_CR0_WP \| X86_CR0_AM))
2015	!= (oldval & (X86_CR0_WP \| X86_CR0_AM)))
2016	return VERR_EM_INTERPRETER;
2017	#endif
2018	CPUMSetGuestCR0(pVM, val);
2019	val = CPUMGetGuestCR0(pVM);
2020	if ( (oldval & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE))
2021	!= (val & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE)))
2022	{
2023	/* global flush */
2024	rc = PGMFlushTLB(pVM, CPUMGetGuestCR3(pVM), true /* global */);
2025	AssertRCReturn(rc, rc);
2026	}
2027
2028	/* Deal with long mode enabling/disabling. */
2029	msrEFER = CPUMGetGuestEFER(pVM);
2030	if (msrEFER & MSR_K6_EFER_LME)
2031	{
2032	if ( !(oldval & X86_CR0_PG)
2033	&& (val & X86_CR0_PG))
2034	{
2035	/* Illegal to have an active 64 bits CS selector (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
2036	if (pRegFrame->csHid.Attr.n.u1Long)
2037	{
2038	AssertMsgFailed(("Illegal enabling of paging with CS.u1Long = 1!!\n"));
2039	return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
2040	}
2041
2042	/* Illegal to switch to long mode before activating PAE first (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
2043	if (!(CPUMGetGuestCR4(pVM) & X86_CR4_PAE))
2044	{
2045	AssertMsgFailed(("Illegal enabling of paging with PAE disabled!!\n"));
2046	return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
2047	}
2048	msrEFER \|= MSR_K6_EFER_LMA;
2049	}
2050	else
2051	if ( (oldval & X86_CR0_PG)
2052	&& !(val & X86_CR0_PG))
2053	{
2054	msrEFER &= ~MSR_K6_EFER_LMA;
2055	/* @todo Do we need to cut off rip here? High dword of rip is undefined, so it shouldn't really matter. */
2056	}
2057	CPUMSetGuestEFER(pVM, msrEFER);
2058	}
2059	return PGMChangeMode(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR4(pVM), CPUMGetGuestEFER(pVM));
2060
2061	case USE_REG_CR2:
2062	rc = CPUMSetGuestCR2(pVM, val); AssertRC(rc);
2063	return VINF_SUCCESS;
2064
2065	case USE_REG_CR3:
2066	/* Reloading the current CR3 means the guest just wants to flush the TLBs */
2067	rc = CPUMSetGuestCR3(pVM, val); AssertRC(rc);
2068	if (CPUMGetGuestCR0(pVM) & X86_CR0_PG)
2069	{
2070	/* flush */
2071	rc = PGMFlushTLB(pVM, val, !(CPUMGetGuestCR4(pVM) & X86_CR4_PGE));
2072	AssertRCReturn(rc, rc);
2073	}
2074	return VINF_SUCCESS;
2075
2076	case USE_REG_CR4:
2077	oldval = CPUMGetGuestCR4(pVM);
2078	rc = CPUMSetGuestCR4(pVM, val); AssertRC(rc);
2079	val = CPUMGetGuestCR4(pVM);
2080
2081	msrEFER = CPUMGetGuestEFER(pVM);
2082	/* Illegal to disable PAE when long mode is active. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
2083	if ( (msrEFER & MSR_K6_EFER_LMA)
2084	&& (oldval & X86_CR4_PAE)
2085	&& !(val & X86_CR4_PAE))
2086	{
2087	return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
2088	}
2089
2090	if ( (oldval & (X86_CR4_PGE\|X86_CR4_PAE\|X86_CR4_PSE))
2091	!= (val & (X86_CR4_PGE\|X86_CR4_PAE\|X86_CR4_PSE)))
2092	{
2093	/* global flush */
2094	rc = PGMFlushTLB(pVM, CPUMGetGuestCR3(pVM), true /* global */);
2095	AssertRCReturn(rc, rc);
2096	}
2097	# ifdef IN_RC
2098	/* Feeling extremely lazy. */
2099	if ( (oldval & (X86_CR4_OSFSXR\|X86_CR4_OSXMMEEXCPT\|X86_CR4_PCE\|X86_CR4_MCE\|X86_CR4_PAE\|X86_CR4_DE\|X86_CR4_TSD\|X86_CR4_PVI\|X86_CR4_VME))
2100	!= (val & (X86_CR4_OSFSXR\|X86_CR4_OSXMMEEXCPT\|X86_CR4_PCE\|X86_CR4_MCE\|X86_CR4_PAE\|X86_CR4_DE\|X86_CR4_TSD\|X86_CR4_PVI\|X86_CR4_VME)))
2101	{
2102	Log(("emInterpretMovCRx: CR4: %#RX64->%#RX64 => R3\n", oldval, val));
2103	VM_FF_SET(pVM, VM_FF_TO_R3);
2104	}
2105	# endif
2106	return PGMChangeMode(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR4(pVM), CPUMGetGuestEFER(pVM));
2107
2108	case USE_REG_CR8:
2109	return PDMApicSetTPR(pVM, val);
2110
2111	default:
2112	AssertFailed();
2113	case USE_REG_CR1: /* illegal op */
2114	break;
2115	}
2116	return VERR_EM_INTERPRETER;
2117	}
2118
2119	/**
2120	* Interpret CRx write
2121	*
2122	* @returns VBox status code.
2123	* @param pVM The VM handle.
2124	* @param pRegFrame The register frame.
2125	* @param DestRegCRx CRx register index (USE_REG_CR*)
2126	* @param SrcRegGen General purpose register index (USE_REG_E**))
2127	*
2128	*/
2129	VMMDECL(int) EMInterpretCRxWrite(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint32_t SrcRegGen)
2130	{
2131	uint64_t val;
2132	int rc;
2133
2134	if (CPUMIsGuestIn64BitCode(pVM, pRegFrame))
2135	{
2136	rc = DISFetchReg64(pRegFrame, SrcRegGen, &val);
2137	}
2138	else
2139	{
2140	uint32_t val32;
2141	rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
2142	val = val32;
2143	}
2144
2145	if (RT_SUCCESS(rc))
2146	return EMUpdateCRx(pVM, pRegFrame, DestRegCrx, val);
2147
2148	return VERR_EM_INTERPRETER;
2149	}
2150
2151	/**
2152	* Interpret LMSW
2153	*
2154	* @returns VBox status code.
2155	* @param pVM The VM handle.
2156	* @param pRegFrame The register frame.
2157	* @param u16Data LMSW source data.
2158	*
2159	*/
2160	VMMDECL(int) EMInterpretLMSW(PVM pVM, PCPUMCTXCORE pRegFrame, uint16_t u16Data)
2161	{
2162	uint64_t OldCr0 = CPUMGetGuestCR0(pVM);
2163
2164	/* Only PE, MP, EM and TS can be changed; note that PE can't be cleared by this instruction. */
2165	uint64_t NewCr0 = ( OldCr0 & ~( X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
2166	\| (u16Data & (X86_CR0_PE \| X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS));
2167
2168	return EMUpdateCRx(pVM, pRegFrame, USE_REG_CR0, NewCr0);
2169	}
2170
2171	/**
2172	* LMSW Emulation.
2173	*/
2174	static int emInterpretLmsw(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2175	{
2176	OP_PARAMVAL param1;
2177	uint32_t val;
2178
2179	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
2180	if(RT_FAILURE(rc))
2181	return VERR_EM_INTERPRETER;
2182
2183	switch(param1.type)
2184	{
2185	case PARMTYPE_IMMEDIATE:
2186	case PARMTYPE_ADDRESS:
2187	if(!(param1.flags & PARAM_VAL16))
2188	return VERR_EM_INTERPRETER;
2189	val = param1.val.val32;
2190	break;
2191
2192	default:
2193	return VERR_EM_INTERPRETER;
2194	}
2195
2196	LogFlow(("emInterpretLmsw %x\n", val));
2197	return EMInterpretLMSW(pVM, pRegFrame, val);
2198	}
2199
2200	/**
2201	* MOV CRx
2202	*/
2203	static int emInterpretMovCRx(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2204	{
2205	if ((pCpu->param1.flags == USE_REG_GEN32 \|\| pCpu->param1.flags == USE_REG_GEN64) && pCpu->param2.flags == USE_REG_CR)
2206	return EMInterpretCRxRead(pVM, pRegFrame, pCpu->param1.base.reg_gen, pCpu->param2.base.reg_ctrl);
2207
2208	if (pCpu->param1.flags == USE_REG_CR && (pCpu->param2.flags == USE_REG_GEN32 \|\| pCpu->param2.flags == USE_REG_GEN64))
2209	return EMInterpretCRxWrite(pVM, pRegFrame, pCpu->param1.base.reg_ctrl, pCpu->param2.base.reg_gen);
2210
2211	AssertMsgFailedReturn(("Unexpected control register move\n"), VERR_EM_INTERPRETER);
2212	return VERR_EM_INTERPRETER;
2213	}
2214
2215
2216	/**
2217	* Interpret DRx write
2218	*
2219	* @returns VBox status code.
2220	* @param pVM The VM handle.
2221	* @param pRegFrame The register frame.
2222	* @param DestRegDRx DRx register index (USE_REG_DR*)
2223	* @param SrcRegGen General purpose register index (USE_REG_E**))
2224	*
2225	*/
2226	VMMDECL(int) EMInterpretDRxWrite(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen)
2227	{
2228	uint64_t val;
2229	int rc;
2230
2231	if (CPUMIsGuestIn64BitCode(pVM, pRegFrame))
2232	{
2233	rc = DISFetchReg64(pRegFrame, SrcRegGen, &val);
2234	}
2235	else
2236	{
2237	uint32_t val32;
2238	rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
2239	val = val32;
2240	}
2241
2242	if (RT_SUCCESS(rc))
2243	{
2244	/** @todo we don't fail if illegal bits are set/cleared for e.g. dr7 */
2245	rc = CPUMSetGuestDRx(pVM, DestRegDrx, val);
2246	if (RT_SUCCESS(rc))
2247	return rc;
2248	AssertMsgFailed(("CPUMSetGuestDRx %d failed\n", DestRegDrx));
2249	}
2250	return VERR_EM_INTERPRETER;
2251	}
2252
2253
2254	/**
2255	* Interpret DRx read
2256	*
2257	* @returns VBox status code.
2258	* @param pVM The VM handle.
2259	* @param pRegFrame The register frame.
2260	* @param DestRegGen General purpose register index (USE_REG_E**))
2261	* @param SrcRegDRx DRx register index (USE_REG_DR*)
2262	*
2263	*/
2264	VMMDECL(int) EMInterpretDRxRead(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx)
2265	{
2266	uint64_t val64;
2267
2268	int rc = CPUMGetGuestDRx(pVM, SrcRegDrx, &val64);
2269	AssertMsgRCReturn(rc, ("CPUMGetGuestDRx %d failed\n", SrcRegDrx), VERR_EM_INTERPRETER);
2270	if (CPUMIsGuestIn64BitCode(pVM, pRegFrame))
2271	{
2272	rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
2273	}
2274	else
2275	rc = DISWriteReg32(pRegFrame, DestRegGen, (uint32_t)val64);
2276
2277	if (RT_SUCCESS(rc))
2278	return VINF_SUCCESS;
2279
2280	return VERR_EM_INTERPRETER;
2281	}
2282
2283
2284	/**
2285	* MOV DRx
2286	*/
2287	static int emInterpretMovDRx(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2288	{
2289	int rc = VERR_EM_INTERPRETER;
2290
2291	if((pCpu->param1.flags == USE_REG_GEN32 \|\| pCpu->param1.flags == USE_REG_GEN64) && pCpu->param2.flags == USE_REG_DBG)
2292	{
2293	rc = EMInterpretDRxRead(pVM, pRegFrame, pCpu->param1.base.reg_gen, pCpu->param2.base.reg_dbg);
2294	}
2295	else
2296	if(pCpu->param1.flags == USE_REG_DBG && (pCpu->param2.flags == USE_REG_GEN32 \|\| pCpu->param2.flags == USE_REG_GEN64))
2297	{
2298	rc = EMInterpretDRxWrite(pVM, pRegFrame, pCpu->param1.base.reg_dbg, pCpu->param2.base.reg_gen);
2299	}
2300	else
2301	AssertMsgFailed(("Unexpected debug register move\n"));
2302
2303	return rc;
2304	}
2305
2306
2307	/**
2308	* LLDT Emulation.
2309	*/
2310	static int emInterpretLLdt(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2311	{
2312	OP_PARAMVAL param1;
2313	RTSEL sel;
2314
2315	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
2316	if(RT_FAILURE(rc))
2317	return VERR_EM_INTERPRETER;
2318
2319	switch(param1.type)
2320	{
2321	case PARMTYPE_ADDRESS:
2322	return VERR_EM_INTERPRETER; //feeling lazy right now
2323
2324	case PARMTYPE_IMMEDIATE:
2325	if(!(param1.flags & PARAM_VAL16))
2326	return VERR_EM_INTERPRETER;
2327	sel = (RTSEL)param1.val.val16;
2328	break;
2329
2330	default:
2331	return VERR_EM_INTERPRETER;
2332	}
2333
2334	if (sel == 0)
2335	{
2336	if (CPUMGetHyperLDTR(pVM) == 0)
2337	{
2338	// this simple case is most frequent in Windows 2000 (31k - boot & shutdown)
2339	return VINF_SUCCESS;
2340	}
2341	}
2342	//still feeling lazy
2343	return VERR_EM_INTERPRETER;
2344	}
2345
2346	#ifdef IN_RING0
2347	/**
2348	* LIDT/LGDT Emulation.
2349	*/
2350	static int emInterpretLIGdt(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2351	{
2352	OP_PARAMVAL param1;
2353	RTGCPTR pParam1;
2354	X86XDTR32 dtr32;
2355
2356	Log(("Emulate %s at %RGv\n", emGetMnemonic(pCpu), (RTGCPTR)pRegFrame->rip));
2357
2358	/* Only for the VT-x real-mode emulation case. */
2359	if (!CPUMIsGuestInRealMode(pVM))
2360	return VERR_EM_INTERPRETER;
2361
2362	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
2363	if(RT_FAILURE(rc))
2364	return VERR_EM_INTERPRETER;
2365
2366	switch(param1.type)
2367	{
2368	case PARMTYPE_ADDRESS:
2369	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, param1.val.val16);
2370	break;
2371
2372	default:
2373	return VERR_EM_INTERPRETER;
2374	}
2375
2376	rc = emRamRead(pVM, &dtr32, pParam1, sizeof(dtr32));
2377	AssertRCReturn(rc, VERR_EM_INTERPRETER);
2378
2379	if (!(pCpu->prefix & PREFIX_OPSIZE))
2380	dtr32.uAddr &= 0xffffff; /* 16 bits operand size */
2381
2382	if (pCpu->pCurInstr->opcode == OP_LIDT)
2383	CPUMSetGuestIDTR(pVM, dtr32.uAddr, dtr32.cb);
2384	else
2385	CPUMSetGuestGDTR(pVM, dtr32.uAddr, dtr32.cb);
2386
2387	return VINF_SUCCESS;
2388	}
2389	#endif
2390
2391
2392	#ifdef IN_RC
2393	/**
2394	* STI Emulation.
2395	*
2396	* @remark the instruction following sti is guaranteed to be executed before any interrupts are dispatched
2397	*/
2398	static int emInterpretSti(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2399	{
2400	PPATMGCSTATE pGCState = PATMQueryGCState(pVM);
2401
2402	if(!pGCState)
2403	{
2404	Assert(pGCState);
2405	return VERR_EM_INTERPRETER;
2406	}
2407	pGCState->uVMFlags \|= X86_EFL_IF;
2408
2409	Assert(pRegFrame->eflags.u32 & X86_EFL_IF);
2410	Assert(pvFault == SELMToFlat(pVM, DIS_SELREG_CS, pRegFrame, (RTGCPTR)pRegFrame->rip));
2411
2412	pVM->em.s.GCPtrInhibitInterrupts = pRegFrame->eip + pCpu->opsize;
2413	VM_FF_SET(pVM, VM_FF_INHIBIT_INTERRUPTS);
2414
2415	return VINF_SUCCESS;
2416	}
2417	#endif /* IN_RC */
2418
2419
2420	/**
2421	* HLT Emulation.
2422	*/
2423	static int emInterpretHlt(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2424	{
2425	return VINF_EM_HALT;
2426	}
2427
2428
2429	/**
2430	* Interpret RDTSC
2431	*
2432	* @returns VBox status code.
2433	* @param pVM The VM handle.
2434	* @param pRegFrame The register frame.
2435	*
2436	*/
2437	VMMDECL(int) EMInterpretRdtsc(PVM pVM, PCPUMCTXCORE pRegFrame)
2438	{
2439	unsigned uCR4 = CPUMGetGuestCR4(pVM);
2440
2441	if (uCR4 & X86_CR4_TSD)
2442	return VERR_EM_INTERPRETER; /* genuine #GP */
2443
2444	uint64_t uTicks = TMCpuTickGet(pVM);
2445
2446	/* Same behaviour in 32 & 64 bits mode */
2447	pRegFrame->rax = (uint32_t)uTicks;
2448	pRegFrame->rdx = (uTicks >> 32ULL);
2449
2450	return VINF_SUCCESS;
2451	}
2452
2453	VMMDECL(int) EMInterpretRdtscp(PVM pVM, PCPUMCTX pCtx)
2454	{
2455	unsigned uCR4 = CPUMGetGuestCR4(pVM);
2456
2457	if (!CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
2458	{
2459	AssertFailed();
2460	return VERR_EM_INTERPRETER; /* genuine #UD */
2461	}
2462
2463	if (uCR4 & X86_CR4_TSD)
2464	return VERR_EM_INTERPRETER; /* genuine #GP */
2465
2466	uint64_t uTicks = TMCpuTickGet(pVM);
2467
2468	/* Same behaviour in 32 & 64 bits mode */
2469	pCtx->rax = (uint32_t)uTicks;
2470	pCtx->rdx = (uTicks >> 32ULL);
2471	/* Low dword of the TSC_AUX msr only. */
2472	pCtx->rcx = (uint32_t)CPUMGetGuestMsr(pVM, MSR_K8_TSC_AUX);
2473
2474	return VINF_SUCCESS;
2475	}
2476
2477	/**
2478	* RDTSC Emulation.
2479	*/
2480	static int emInterpretRdtsc(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2481	{
2482	return EMInterpretRdtsc(pVM, pRegFrame);
2483	}
2484
2485
2486	/**
2487	* MONITOR Emulation.
2488	*/
2489	static int emInterpretMonitor(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2490	{
2491	uint32_t u32Dummy, u32ExtFeatures, cpl;
2492
2493	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
2494	if (pRegFrame->ecx != 0)
2495	return VERR_EM_INTERPRETER; /* illegal value. */
2496
2497	/* Get the current privilege level. */
2498	cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2499	if (cpl != 0)
2500	return VERR_EM_INTERPRETER; /* supervisor only */
2501
2502	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
2503	if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
2504	return VERR_EM_INTERPRETER; /* not supported */
2505
2506	return VINF_SUCCESS;
2507	}
2508
2509
2510	/**
2511	* MWAIT Emulation.
2512	*/
2513	static int emInterpretMWait(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2514	{
2515	uint32_t u32Dummy, u32ExtFeatures, cpl;
2516
2517	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
2518	if (pRegFrame->ecx != 0)
2519	return VERR_EM_INTERPRETER; /* illegal value. */
2520
2521	/* Get the current privilege level. */
2522	cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2523	if (cpl != 0)
2524	return VERR_EM_INTERPRETER; /* supervisor only */
2525
2526	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
2527	if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
2528	return VERR_EM_INTERPRETER; /* not supported */
2529
2530	/** @todo not completely correct */
2531	return VINF_EM_HALT;
2532	}
2533
2534
2535	#ifdef LOG_ENABLED
2536	static const char *emMSRtoString(uint32_t uMsr)
2537	{
2538	switch (uMsr)
2539	{
2540	case MSR_IA32_APICBASE:
2541	return "MSR_IA32_APICBASE";
2542	case MSR_IA32_CR_PAT:
2543	return "MSR_IA32_CR_PAT";
2544	case MSR_IA32_SYSENTER_CS:
2545	return "MSR_IA32_SYSENTER_CS";
2546	case MSR_IA32_SYSENTER_EIP:
2547	return "MSR_IA32_SYSENTER_EIP";
2548	case MSR_IA32_SYSENTER_ESP:
2549	return "MSR_IA32_SYSENTER_ESP";
2550	case MSR_K6_EFER:
2551	return "MSR_K6_EFER";
2552	case MSR_K8_SF_MASK:
2553	return "MSR_K8_SF_MASK";
2554	case MSR_K6_STAR:
2555	return "MSR_K6_STAR";
2556	case MSR_K8_LSTAR:
2557	return "MSR_K8_LSTAR";
2558	case MSR_K8_CSTAR:
2559	return "MSR_K8_CSTAR";
2560	case MSR_K8_FS_BASE:
2561	return "MSR_K8_FS_BASE";
2562	case MSR_K8_GS_BASE:
2563	return "MSR_K8_GS_BASE";
2564	case MSR_K8_KERNEL_GS_BASE:
2565	return "MSR_K8_KERNEL_GS_BASE";
2566	case MSR_K8_TSC_AUX:
2567	return "MSR_K8_TSC_AUX";
2568	case MSR_IA32_BIOS_SIGN_ID:
2569	return "Unsupported MSR_IA32_BIOS_SIGN_ID";
2570	case MSR_IA32_PLATFORM_ID:
2571	return "Unsupported MSR_IA32_PLATFORM_ID";
2572	case MSR_IA32_BIOS_UPDT_TRIG:
2573	return "Unsupported MSR_IA32_BIOS_UPDT_TRIG";
2574	case MSR_IA32_TSC:
2575	return "Unsupported MSR_IA32_TSC";
2576	case MSR_IA32_MTRR_CAP:
2577	return "Unsupported MSR_IA32_MTRR_CAP";
2578	case MSR_IA32_MCP_CAP:
2579	return "Unsupported MSR_IA32_MCP_CAP";
2580	case MSR_IA32_MCP_STATUS:
2581	return "Unsupported MSR_IA32_MCP_STATUS";
2582	case MSR_IA32_MCP_CTRL:
2583	return "Unsupported MSR_IA32_MCP_CTRL";
2584	case MSR_IA32_MTRR_DEF_TYPE:
2585	return "Unsupported MSR_IA32_MTRR_DEF_TYPE";
2586	case MSR_K7_EVNTSEL0:
2587	return "Unsupported MSR_K7_EVNTSEL0";
2588	case MSR_K7_EVNTSEL1:
2589	return "Unsupported MSR_K7_EVNTSEL1";
2590	case MSR_K7_EVNTSEL2:
2591	return "Unsupported MSR_K7_EVNTSEL2";
2592	case MSR_K7_EVNTSEL3:
2593	return "Unsupported MSR_K7_EVNTSEL3";
2594	case MSR_IA32_MC0_CTL:
2595	return "Unsupported MSR_IA32_MC0_CTL";
2596	case MSR_IA32_MC0_STATUS:
2597	return "Unsupported MSR_IA32_MC0_STATUS";
2598	}
2599	return "Unknown MSR";
2600	}
2601	#endif /* LOG_ENABLED */
2602
2603
2604	/**
2605	* Interpret RDMSR
2606	*
2607	* @returns VBox status code.
2608	* @param pVM The VM handle.
2609	* @param pRegFrame The register frame.
2610	*
2611	*/
2612	VMMDECL(int) EMInterpretRdmsr(PVM pVM, PCPUMCTXCORE pRegFrame)
2613	{
2614	uint32_t u32Dummy, u32Features, cpl;
2615	uint64_t val;
2616	CPUMCTX *pCtx;
2617	int rc = VINF_SUCCESS;
2618
2619	/** @todo According to the Intel manuals, there's a REX version of RDMSR that is slightly different.
2620	* That version clears the high dwords of both RDX & RAX */
2621	pCtx = CPUMQueryGuestCtxPtr(pVM);
2622
2623	/* Get the current privilege level. */
2624	cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2625	if (cpl != 0)
2626	return VERR_EM_INTERPRETER; /* supervisor only */
2627
2628	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2629	if (!(u32Features & X86_CPUID_FEATURE_EDX_MSR))
2630	return VERR_EM_INTERPRETER; /* not supported */
2631
2632	switch (pRegFrame->ecx)
2633	{
2634	case MSR_IA32_APICBASE:
2635	rc = PDMApicGetBase(pVM, &val);
2636	AssertRC(rc);
2637	break;
2638
2639	case MSR_IA32_CR_PAT:
2640	val = pCtx->msrPAT;
2641	break;
2642
2643	case MSR_IA32_SYSENTER_CS:
2644	val = pCtx->SysEnter.cs;
2645	break;
2646
2647	case MSR_IA32_SYSENTER_EIP:
2648	val = pCtx->SysEnter.eip;
2649	break;
2650
2651	case MSR_IA32_SYSENTER_ESP:
2652	val = pCtx->SysEnter.esp;
2653	break;
2654
2655	case MSR_K6_EFER:
2656	val = pCtx->msrEFER;
2657	break;
2658
2659	case MSR_K8_SF_MASK:
2660	val = pCtx->msrSFMASK;
2661	break;
2662
2663	case MSR_K6_STAR:
2664	val = pCtx->msrSTAR;
2665	break;
2666
2667	case MSR_K8_LSTAR:
2668	val = pCtx->msrLSTAR;
2669	break;
2670
2671	case MSR_K8_CSTAR:
2672	val = pCtx->msrCSTAR;
2673	break;
2674
2675	case MSR_K8_FS_BASE:
2676	val = pCtx->fsHid.u64Base;
2677	break;
2678
2679	case MSR_K8_GS_BASE:
2680	val = pCtx->gsHid.u64Base;
2681	break;
2682
2683	case MSR_K8_KERNEL_GS_BASE:
2684	val = pCtx->msrKERNELGSBASE;
2685	break;
2686
2687	case MSR_K8_TSC_AUX:
2688	val = CPUMGetGuestMsr(pVM, MSR_K8_TSC_AUX);
2689	break;
2690
2691	#if 0 /def IN_RING0 /
2692	case MSR_IA32_PLATFORM_ID:
2693	case MSR_IA32_BIOS_SIGN_ID:
2694	if (CPUMGetCPUVendor(pVM) == CPUMCPUVENDOR_INTEL)
2695	{
2696	/* Available since the P6 family. VT-x implies that this feature is present. */
2697	if (pRegFrame->ecx == MSR_IA32_PLATFORM_ID)
2698	val = ASMRdMsr(MSR_IA32_PLATFORM_ID);
2699	else
2700	if (pRegFrame->ecx == MSR_IA32_BIOS_SIGN_ID)
2701	val = ASMRdMsr(MSR_IA32_BIOS_SIGN_ID);
2702	break;
2703	}
2704	/* no break */
2705	#endif
2706	default:
2707	/* In X2APIC specification this range is reserved for APIC control. */
2708	if ((pRegFrame->ecx >= MSR_IA32_APIC_START) && (pRegFrame->ecx < MSR_IA32_APIC_END))
2709	rc = PDMApicReadMSR(pVM, VMMGetCpuId(pVM), pRegFrame->ecx, &val);
2710	else
2711	/* We should actually trigger a #GP here, but don't as that might cause more trouble. */
2712	val = 0;
2713	break;
2714	}
2715	LogFlow(("EMInterpretRdmsr %s (%x) -> val=%RX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx, val));
2716	if (rc == VINF_SUCCESS)
2717	{
2718	pRegFrame->rax = (uint32_t) val;
2719	pRegFrame->rdx = (uint32_t) (val >> 32ULL);
2720	}
2721	return rc;
2722	}
2723
2724
2725	/**
2726	* RDMSR Emulation.
2727	*/
2728	static int emInterpretRdmsr(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2729	{
2730	/* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
2731	Assert(!(pCpu->prefix & PREFIX_REX));
2732	return EMInterpretRdmsr(pVM, pRegFrame);
2733	}
2734
2735
2736	/**
2737	* Interpret WRMSR
2738	*
2739	* @returns VBox status code.
2740	* @param pVM The VM handle.
2741	* @param pRegFrame The register frame.
2742	*/
2743	VMMDECL(int) EMInterpretWrmsr(PVM pVM, PCPUMCTXCORE pRegFrame)
2744	{
2745	uint32_t u32Dummy, u32Features, cpl;
2746	uint64_t val;
2747	CPUMCTX *pCtx;
2748
2749	/* Note: works the same in 32 and 64 bits modes. */
2750	pCtx = CPUMQueryGuestCtxPtr(pVM);
2751
2752	/* Get the current privilege level. */
2753	cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2754	if (cpl != 0)
2755	return VERR_EM_INTERPRETER; /* supervisor only */
2756
2757	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2758	if (!(u32Features & X86_CPUID_FEATURE_EDX_MSR))
2759	return VERR_EM_INTERPRETER; /* not supported */
2760
2761	val = RT_MAKE_U64(pRegFrame->eax, pRegFrame->edx);
2762	LogFlow(("EMInterpretWrmsr %s (%x) val=%RX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx, val));
2763	switch (pRegFrame->ecx)
2764	{
2765	case MSR_IA32_APICBASE:
2766	{
2767	int rc = PDMApicSetBase(pVM, val);
2768	AssertRC(rc);
2769	break;
2770	}
2771
2772	case MSR_IA32_CR_PAT:
2773	pCtx->msrPAT = val;
2774	break;
2775
2776	case MSR_IA32_SYSENTER_CS:
2777	pCtx->SysEnter.cs = val & 0xffff; /* 16 bits selector */
2778	break;
2779
2780	case MSR_IA32_SYSENTER_EIP:
2781	pCtx->SysEnter.eip = val;
2782	break;
2783
2784	case MSR_IA32_SYSENTER_ESP:
2785	pCtx->SysEnter.esp = val;
2786	break;
2787
2788	case MSR_K6_EFER:
2789	{
2790	uint64_t uMask = 0;
2791	uint64_t oldval = pCtx->msrEFER;
2792
2793	/* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
2794	CPUMGetGuestCpuId(pVM, 0x80000001, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2795	if (u32Features & X86_CPUID_AMD_FEATURE_EDX_NX)
2796	uMask \|= MSR_K6_EFER_NXE;
2797	if (u32Features & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE)
2798	uMask \|= MSR_K6_EFER_LME;
2799	if (u32Features & X86_CPUID_AMD_FEATURE_EDX_SEP)
2800	uMask \|= MSR_K6_EFER_SCE;
2801	if (u32Features & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
2802	uMask \|= MSR_K6_EFER_FFXSR;
2803
2804	/* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
2805	if ( ((pCtx->msrEFER & MSR_K6_EFER_LME) != (val & uMask & MSR_K6_EFER_LME))
2806	&& (pCtx->cr0 & X86_CR0_PG))
2807	{
2808	AssertMsgFailed(("Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
2809	return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
2810	}
2811
2812	/* There are a few more: e.g. MSR_K6_EFER_LMSLE */
2813	AssertMsg(!(val & ~(MSR_K6_EFER_NXE\|MSR_K6_EFER_LME\|MSR_K6_EFER_LMA /* ignored anyway */ \|MSR_K6_EFER_SCE\|MSR_K6_EFER_FFXSR)), ("Unexpected value %RX64\n", val));
2814	pCtx->msrEFER = (pCtx->msrEFER & ~uMask) \| (val & uMask);
2815
2816	/* AMD64 Achitecture Programmer's Manual: 15.15 TLB Control; flush the TLB if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
2817	if ((oldval & (MSR_K6_EFER_NXE\|MSR_K6_EFER_LME\|MSR_K6_EFER_LMA)) != (pCtx->msrEFER & (MSR_K6_EFER_NXE\|MSR_K6_EFER_LME\|MSR_K6_EFER_LMA)))
2818	HWACCMFlushTLB(pVM);
2819
2820	break;
2821	}
2822
2823	case MSR_K8_SF_MASK:
2824	pCtx->msrSFMASK = val;
2825	break;
2826
2827	case MSR_K6_STAR:
2828	pCtx->msrSTAR = val;
2829	break;
2830
2831	case MSR_K8_LSTAR:
2832	pCtx->msrLSTAR = val;
2833	break;
2834
2835	case MSR_K8_CSTAR:
2836	pCtx->msrCSTAR = val;
2837	break;
2838
2839	case MSR_K8_FS_BASE:
2840	pCtx->fsHid.u64Base = val;
2841	break;
2842
2843	case MSR_K8_GS_BASE:
2844	pCtx->gsHid.u64Base = val;
2845	break;
2846
2847	case MSR_K8_KERNEL_GS_BASE:
2848	pCtx->msrKERNELGSBASE = val;
2849	break;
2850
2851	case MSR_K8_TSC_AUX:
2852	CPUMSetGuestMsr(pVM, MSR_K8_TSC_AUX, val);
2853	break;
2854
2855	default:
2856	/* In X2APIC specification this range is reserved for APIC control. */
2857	if ((pRegFrame->ecx >= MSR_IA32_APIC_START) && (pRegFrame->ecx < MSR_IA32_APIC_END))
2858	return PDMApicWriteMSR(pVM, VMMGetCpuId(pVM), pRegFrame->ecx, val);
2859
2860	/* We should actually trigger a #GP here, but don't as that might cause more trouble. */
2861	break;
2862	}
2863	return VINF_SUCCESS;
2864	}
2865
2866
2867	/**
2868	* WRMSR Emulation.
2869	*/
2870	static int emInterpretWrmsr(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2871	{
2872	return EMInterpretWrmsr(pVM, pRegFrame);
2873	}
2874
2875
2876	/**
2877	* Internal worker.
2878	* @copydoc EMInterpretInstructionCPU
2879	*/
2880	DECLINLINE(int) emInterpretInstructionCPU(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2881	{
2882	Assert(pcbSize);
2883	*pcbSize = 0;
2884
2885	/*
2886	* Only supervisor guest code!!
2887	* And no complicated prefixes.
2888	*/
2889	/* Get the current privilege level. */
2890	uint32_t cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2891	if ( cpl != 0
2892	&& pCpu->pCurInstr->opcode != OP_RDTSC) /* rdtsc requires emulation in ring 3 as well */
2893	{
2894	Log(("WARNING: refusing instruction emulation for user-mode code!!\n"));
2895	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedUserMode));
2896	return VERR_EM_INTERPRETER;
2897	}
2898
2899	#ifdef IN_RC
2900	if ( (pCpu->prefix & (PREFIX_REPNE \| PREFIX_REP))
2901	\|\| ( (pCpu->prefix & PREFIX_LOCK)
2902	&& pCpu->pCurInstr->opcode != OP_CMPXCHG
2903	&& pCpu->pCurInstr->opcode != OP_CMPXCHG8B
2904	&& pCpu->pCurInstr->opcode != OP_XADD
2905	&& pCpu->pCurInstr->opcode != OP_OR
2906	&& pCpu->pCurInstr->opcode != OP_BTR
2907	)
2908	)
2909	#else
2910	if ( (pCpu->prefix & PREFIX_REPNE)
2911	\|\| ( (pCpu->prefix & PREFIX_REP)
2912	&& pCpu->pCurInstr->opcode != OP_STOSWD
2913	)
2914	\|\| ( (pCpu->prefix & PREFIX_LOCK)
2915	&& pCpu->pCurInstr->opcode != OP_OR
2916	&& pCpu->pCurInstr->opcode != OP_BTR
2917	&& pCpu->pCurInstr->opcode != OP_CMPXCHG
2918	&& pCpu->pCurInstr->opcode != OP_CMPXCHG8B
2919	)
2920	)
2921	#endif
2922	{
2923	//Log(("EMInterpretInstruction: wrong prefix!!\n"));
2924	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedPrefix));
2925	return VERR_EM_INTERPRETER;
2926	}
2927
2928	int rc;
2929	#if (defined(VBOX_STRICT) \|\| defined(LOG_ENABLED))
2930	LogFlow(("emInterpretInstructionCPU %s\n", emGetMnemonic(pCpu)));
2931	#endif
2932	switch (pCpu->pCurInstr->opcode)
2933	{
2934	# define INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
2935	case opcode:\
2936	if (pCpu->prefix & PREFIX_LOCK) \
2937	rc = emInterpretLock##InstrFn(pVM, pCpu, pRegFrame, pvFault, pcbSize, pfnEmulateLock); \
2938	else \
2939	rc = emInterpret##InstrFn(pVM, pCpu, pRegFrame, pvFault, pcbSize, pfnEmulate); \
2940	if (RT_SUCCESS(rc)) \
2941	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
2942	else \
2943	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
2944	return rc
2945	#define INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate) \
2946	case opcode:\
2947	rc = emInterpret##InstrFn(pVM, pCpu, pRegFrame, pvFault, pcbSize, pfnEmulate); \
2948	if (RT_SUCCESS(rc)) \
2949	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
2950	else \
2951	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
2952	return rc
2953
2954	#define INTERPRET_CASE_EX_PARAM2(opcode, Instr, InstrFn, pfnEmulate) \
2955	INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate)
2956	#define INTERPRET_CASE_EX_LOCK_PARAM2(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
2957	INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock)
2958
2959	#define INTERPRET_CASE(opcode, Instr) \
2960	case opcode:\
2961	rc = emInterpret##Instr(pVM, pCpu, pRegFrame, pvFault, pcbSize); \
2962	if (RT_SUCCESS(rc)) \
2963	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
2964	else \
2965	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
2966	return rc
2967
2968	#define INTERPRET_CASE_EX_DUAL_PARAM2(opcode, Instr, InstrFn) \
2969	case opcode:\
2970	rc = emInterpret##InstrFn(pVM, pCpu, pRegFrame, pvFault, pcbSize); \
2971	if (RT_SUCCESS(rc)) \
2972	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
2973	else \
2974	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
2975	return rc
2976
2977	#define INTERPRET_STAT_CASE(opcode, Instr) \
2978	case opcode: STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); return VERR_EM_INTERPRETER;
2979
2980	INTERPRET_CASE(OP_XCHG,Xchg);
2981	INTERPRET_CASE_EX_PARAM2(OP_DEC,Dec, IncDec, EMEmulateDec);
2982	INTERPRET_CASE_EX_PARAM2(OP_INC,Inc, IncDec, EMEmulateInc);
2983	INTERPRET_CASE(OP_POP,Pop);
2984	INTERPRET_CASE_EX_LOCK_PARAM3(OP_OR, Or, OrXorAnd, EMEmulateOr, EMEmulateLockOr);
2985	INTERPRET_CASE_EX_PARAM3(OP_XOR,Xor, OrXorAnd, EMEmulateXor);
2986	INTERPRET_CASE_EX_PARAM3(OP_AND,And, OrXorAnd, EMEmulateAnd);
2987	INTERPRET_CASE(OP_MOV,Mov);
2988	#ifndef IN_RC
2989	INTERPRET_CASE(OP_STOSWD,StosWD);
2990	#endif
2991	INTERPRET_CASE(OP_INVLPG,InvlPg);
2992	INTERPRET_CASE(OP_CPUID,CpuId);
2993	INTERPRET_CASE(OP_MOV_CR,MovCRx);
2994	INTERPRET_CASE(OP_MOV_DR,MovDRx);
2995	INTERPRET_CASE(OP_LLDT,LLdt);
2996	#ifdef IN_RING0
2997	INTERPRET_CASE_EX_DUAL_PARAM2(OP_LIDT, LIdt, LIGdt);
2998	INTERPRET_CASE_EX_DUAL_PARAM2(OP_LGDT, LGdt, LIGdt);
2999	#endif
3000	INTERPRET_CASE(OP_LMSW,Lmsw);
3001	INTERPRET_CASE(OP_CLTS,Clts);
3002	INTERPRET_CASE(OP_MONITOR, Monitor);
3003	INTERPRET_CASE(OP_MWAIT, MWait);
3004	INTERPRET_CASE(OP_RDMSR, Rdmsr);
3005	INTERPRET_CASE(OP_WRMSR, Wrmsr);
3006	INTERPRET_CASE_EX_PARAM3(OP_ADD,Add, AddSub, EMEmulateAdd);
3007	INTERPRET_CASE_EX_PARAM3(OP_SUB,Sub, AddSub, EMEmulateSub);
3008	INTERPRET_CASE(OP_ADC,Adc);
3009	INTERPRET_CASE_EX_LOCK_PARAM2(OP_BTR,Btr, BitTest, EMEmulateBtr, EMEmulateLockBtr);
3010	INTERPRET_CASE_EX_PARAM2(OP_BTS,Bts, BitTest, EMEmulateBts);
3011	INTERPRET_CASE_EX_PARAM2(OP_BTC,Btc, BitTest, EMEmulateBtc);
3012	INTERPRET_CASE(OP_RDTSC,Rdtsc);
3013	INTERPRET_CASE(OP_CMPXCHG, CmpXchg);
3014	#ifdef IN_RC
3015	INTERPRET_CASE(OP_STI,Sti);
3016	INTERPRET_CASE(OP_XADD, XAdd);
3017	#endif
3018	INTERPRET_CASE(OP_CMPXCHG8B, CmpXchg8b);
3019	INTERPRET_CASE(OP_HLT,Hlt);
3020	INTERPRET_CASE(OP_IRET,Iret);
3021	INTERPRET_CASE(OP_WBINVD,WbInvd);
3022	#ifdef VBOX_WITH_STATISTICS
3023	#ifndef IN_RC
3024	INTERPRET_STAT_CASE(OP_XADD, XAdd);
3025	#endif
3026	INTERPRET_STAT_CASE(OP_MOVNTPS,MovNTPS);
3027	#endif
3028	default:
3029	Log3(("emInterpretInstructionCPU: opcode=%d\n", pCpu->pCurInstr->opcode));
3030	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedMisc));
3031	return VERR_EM_INTERPRETER;
3032	#undef INTERPRET_CASE_EX_PARAM2
3033	#undef INTERPRET_STAT_CASE
3034	#undef INTERPRET_CASE_EX
3035	#undef INTERPRET_CASE
3036	}
3037	AssertFailed();
3038	return VERR_INTERNAL_ERROR;
3039	}
3040
3041
3042	/**
3043	* Sets the PC for which interrupts should be inhibited.
3044	*
3045	* @param pVM The VM handle.
3046	* @param PC The PC.
3047	*/
3048	VMMDECL(void) EMSetInhibitInterruptsPC(PVM pVM, RTGCUINTPTR PC)
3049	{
3050	pVM->em.s.GCPtrInhibitInterrupts = PC;
3051	VM_FF_SET(pVM, VM_FF_INHIBIT_INTERRUPTS);
3052	}
3053
3054
3055	/**
3056	* Gets the PC for which interrupts should be inhibited.
3057	*
3058	* There are a few instructions which inhibits or delays interrupts
3059	* for the instruction following them. These instructions are:
3060	* - STI
3061	* - MOV SS, r/m16
3062	* - POP SS
3063	*
3064	* @returns The PC for which interrupts should be inhibited.
3065	* @param pVM VM handle.
3066	*
3067	*/
3068	VMMDECL(RTGCUINTPTR) EMGetInhibitInterruptsPC(PVM pVM)
3069	{
3070	return pVM->em.s.GCPtrInhibitInterrupts;
3071	}
3072

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source: vbox/trunk/src/VBox/VMM/VMMAll/EMAll.cpp@ 14740

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