EMAll.cpp@ 15184

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1	/* $Id: EMAll.cpp 15184 2008-12-09 14:56:56Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor(/Manager) - All contexts
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_EM
26	#include <VBox/em.h>
27	#include <VBox/mm.h>
28	#include <VBox/selm.h>
29	#include <VBox/patm.h>
30	#include <VBox/csam.h>
31	#include <VBox/pgm.h>
32	#include <VBox/iom.h>
33	#include <VBox/stam.h>
34	#include "EMInternal.h"
35	#include <VBox/vm.h>
36	#include <VBox/vmm.h>
37	#include <VBox/hwaccm.h>
38	#include <VBox/tm.h>
39	#include <VBox/pdmapi.h>
40
41	#include <VBox/param.h>
42	#include <VBox/err.h>
43	#include <VBox/dis.h>
44	#include <VBox/disopcode.h>
45	#include <VBox/log.h>
46	#include <iprt/assert.h>
47	#include <iprt/asm.h>
48	#include <iprt/string.h>
49
50
51	/*******************************************************************************
52	* Defined Constants And Macros *
53	*******************************************************************************/
54	/** @def EM_ASSERT_FAULT_RETURN
55	* Safety check.
56	*
57	* Could in theory it misfire on a cross page boundary access...
58	*
59	* Currently disabled because the CSAM (+ PATM) patch monitoring occationally
60	* turns up an alias page instead of the original faulting one and annoying the
61	* heck out of anyone running a debug build. See @bugref{2609} and @bugref{1931}.
62	*/
63	#if 0
64	# define EM_ASSERT_FAULT_RETURN(expr, rc) AssertReturn(expr, rc)
65	#else
66	# define EM_ASSERT_FAULT_RETURN(expr, rc) do { } while (0)
67	#endif
68
69
70	/*******************************************************************************
71	* Internal Functions *
72	*******************************************************************************/
73	DECLINLINE(int) emInterpretInstructionCPU(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize);
74
75
76
77	/**
78	* Get the current execution manager status.
79	*
80	* @returns Current status.
81	*/
82	VMMDECL(EMSTATE) EMGetState(PVM pVM)
83	{
84	return pVM->em.s.enmState;
85	}
86
87	#ifndef IN_RC
88
89	/**
90	* Read callback for disassembly function; supports reading bytes that cross a page boundary
91	*
92	* @returns VBox status code.
93	* @param pSrc GC source pointer
94	* @param pDest HC destination pointer
95	* @param cb Number of bytes to read
96	* @param dwUserdata Callback specific user data (pCpu)
97	*
98	*/
99	DECLCALLBACK(int) EMReadBytes(RTUINTPTR pSrc, uint8_t pDest, unsigned cb, void pvUserdata)
100	{
101	DISCPUSTATE pCpu = (DISCPUSTATE )pvUserdata;
102	PVM pVM = (PVM)pCpu->apvUserData[0];
103	# ifdef IN_RING0
104	int rc = PGMPhysSimpleReadGCPtr(pVM, pDest, pSrc, cb);
105	AssertMsgRC(rc, ("PGMPhysSimpleReadGCPtr failed for pSrc=%RGv cb=%x\n", pSrc, cb));
106	# else /* IN_RING3 */
107	if (!PATMIsPatchGCAddr(pVM, pSrc))
108	{
109	int rc = PGMPhysSimpleReadGCPtr(pVM, pDest, pSrc, cb);
110	AssertRC(rc);
111	}
112	else
113	{
114	for (uint32_t i = 0; i < cb; i++)
115	{
116	uint8_t opcode;
117	if (RT_SUCCESS(PATMR3QueryOpcode(pVM, (RTGCPTR)pSrc + i, &opcode)))
118	{
119	*(pDest+i) = opcode;
120	}
121	}
122	}
123	# endif /* IN_RING3 */
124	return VINF_SUCCESS;
125	}
126
127	DECLINLINE(int) emDisCoreOne(PVM pVM, DISCPUSTATE pCpu, RTGCUINTPTR InstrGC, uint32_t pOpsize)
128	{
129	return DISCoreOneEx(InstrGC, pCpu->mode, EMReadBytes, pVM, pCpu, pOpsize);
130	}
131
132	#else /* IN_RC */
133
134	DECLINLINE(int) emDisCoreOne(PVM pVM, DISCPUSTATE pCpu, RTGCUINTPTR InstrGC, uint32_t pOpsize)
135	{
136	return DISCoreOne(pCpu, InstrGC, pOpsize);
137	}
138
139	#endif /* IN_RC */
140
141
142	/**
143	* Disassembles one instruction.
144	*
145	* @param pVM The VM handle.
146	* @param pCtxCore The context core (used for both the mode and instruction).
147	* @param pCpu Where to return the parsed instruction info.
148	* @param pcbInstr Where to return the instruction size. (optional)
149	*/
150	VMMDECL(int) EMInterpretDisasOne(PVM pVM, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, unsigned *pcbInstr)
151	{
152	RTGCPTR GCPtrInstr;
153	int rc = SELMToFlatEx(pVM, DIS_SELREG_CS, pCtxCore, pCtxCore->rip, 0, &GCPtrInstr);
154	if (RT_FAILURE(rc))
155	{
156	Log(("EMInterpretDisasOne: Failed to convert %RTsel:%RGv (cpl=%d) - rc=%Rrc !!\n",
157	pCtxCore->cs, (RTGCPTR)pCtxCore->rip, pCtxCore->ss & X86_SEL_RPL, rc));
158	return rc;
159	}
160	return EMInterpretDisasOneEx(pVM, (RTGCUINTPTR)GCPtrInstr, pCtxCore, pCpu, pcbInstr);
161	}
162
163
164	/**
165	* Disassembles one instruction.
166	*
167	* This is used by internally by the interpreter and by trap/access handlers.
168	*
169	* @param pVM The VM handle.
170	* @param GCPtrInstr The flat address of the instruction.
171	* @param pCtxCore The context core (used to determin the cpu mode).
172	* @param pCpu Where to return the parsed instruction info.
173	* @param pcbInstr Where to return the instruction size. (optional)
174	*/
175	VMMDECL(int) EMInterpretDisasOneEx(PVM pVM, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, unsigned *pcbInstr)
176	{
177	int rc = DISCoreOneEx(GCPtrInstr, SELMGetCpuModeFromSelector(pVM, pCtxCore->eflags, pCtxCore->cs, (PCPUMSELREGHID)&pCtxCore->csHid),
178	#ifdef IN_RC
179	NULL, NULL,
180	#else
181	EMReadBytes, pVM,
182	#endif
183	pCpu, pcbInstr);
184	if (RT_SUCCESS(rc))
185	return VINF_SUCCESS;
186	AssertMsgFailed(("DISCoreOne failed to GCPtrInstr=%RGv rc=%Rrc\n", GCPtrInstr, rc));
187	return VERR_INTERNAL_ERROR;
188	}
189
190
191	/**
192	* Interprets the current instruction.
193	*
194	* @returns VBox status code.
195	* @retval VINF_* Scheduling instructions.
196	* @retval VERR_EM_INTERPRETER Something we can't cope with.
197	* @retval VERR_* Fatal errors.
198	*
199	* @param pVM The VM handle.
200	* @param pRegFrame The register frame.
201	* Updates the EIP if an instruction was executed successfully.
202	* @param pvFault The fault address (CR2).
203	* @param pcbSize Size of the write (if applicable).
204	*
205	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
206	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
207	* to worry about e.g. invalid modrm combinations (!)
208	*/
209	VMMDECL(int) EMInterpretInstruction(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
210	{
211	RTGCPTR pbCode;
212
213	LogFlow(("EMInterpretInstruction %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
214	int rc = SELMToFlatEx(pVM, DIS_SELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
215	if (RT_SUCCESS(rc))
216	{
217	uint32_t cbOp;
218	DISCPUSTATE Cpu;
219	Cpu.mode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
220	rc = emDisCoreOne(pVM, &Cpu, (RTGCUINTPTR)pbCode, &cbOp);
221	if (RT_SUCCESS(rc))
222	{
223	Assert(cbOp == Cpu.opsize);
224	rc = EMInterpretInstructionCPU(pVM, &Cpu, pRegFrame, pvFault, pcbSize);
225	if (RT_SUCCESS(rc))
226	{
227	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
228	}
229	return rc;
230	}
231	}
232	return VERR_EM_INTERPRETER;
233	}
234
235
236	/**
237	* Interprets the current instruction using the supplied DISCPUSTATE structure.
238	*
239	* EIP is NOT updated!
240	*
241	* @returns VBox status code.
242	* @retval VINF_* Scheduling instructions. When these are returned, it
243	* starts to get a bit tricky to know whether code was
244	* executed or not... We'll address this when it becomes a problem.
245	* @retval VERR_EM_INTERPRETER Something we can't cope with.
246	* @retval VERR_* Fatal errors.
247	*
248	* @param pVM The VM handle.
249	* @param pCpu The disassembler cpu state for the instruction to be interpreted.
250	* @param pRegFrame The register frame. EIP is NOT changed!
251	* @param pvFault The fault address (CR2).
252	* @param pcbSize Size of the write (if applicable).
253	*
254	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
255	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
256	* to worry about e.g. invalid modrm combinations (!)
257	*
258	* @todo At this time we do NOT check if the instruction overwrites vital information.
259	* Make sure this can't happen!! (will add some assertions/checks later)
260	*/
261	VMMDECL(int) EMInterpretInstructionCPU(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
262	{
263	STAM_PROFILE_START(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Emulate), a);
264	int rc = emInterpretInstructionCPU(pVM, pCpu, pRegFrame, pvFault, pcbSize);
265	STAM_PROFILE_STOP(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Emulate), a);
266	if (RT_SUCCESS(rc))
267	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InterpretSucceeded));
268	else
269	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InterpretFailed));
270	return rc;
271	}
272
273
274	/**
275	* Interpret a port I/O instruction.
276	*
277	* @returns VBox status code suitable for scheduling.
278	* @param pVM The VM handle.
279	* @param pCtxCore The context core. This will be updated on successful return.
280	* @param pCpu The instruction to interpret.
281	* @param cbOp The size of the instruction.
282	* @remark This may raise exceptions.
283	*/
284	VMMDECL(int) EMInterpretPortIO(PVM pVM, PCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, uint32_t cbOp)
285	{
286	/*
287	* Hand it on to IOM.
288	*/
289	#ifdef IN_RC
290	int rc = IOMGCIOPortHandler(pVM, pCtxCore, pCpu);
291	if (IOM_SUCCESS(rc))
292	pCtxCore->rip += cbOp;
293	return rc;
294	#else
295	AssertReleaseMsgFailed(("not implemented\n"));
296	return VERR_NOT_IMPLEMENTED;
297	#endif
298	}
299
300
301	DECLINLINE(int) emRamRead(PVM pVM, void *pDest, RTGCPTR GCSrc, uint32_t cb)
302	{
303	#ifdef IN_RC
304	int rc = MMGCRamRead(pVM, pDest, (void *)GCSrc, cb);
305	if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
306	return rc;
307	/*
308	* The page pool cache may end up here in some cases because it
309	* flushed one of the shadow mappings used by the trapping
310	* instruction and it either flushed the TLB or the CPU reused it.
311	*/
312	RTGCPHYS GCPhys;
313	rc = PGMPhysGCPtr2GCPhys(pVM, GCSrc, &GCPhys);
314	AssertRCReturn(rc, rc);
315	PGMPhysRead(pVM, GCPhys, pDest, cb);
316	return VINF_SUCCESS;
317	#else
318	return PGMPhysReadGCPtr(pVM, pDest, GCSrc, cb);
319	#endif
320	}
321
322
323	DECLINLINE(int) emRamWrite(PVM pVM, RTGCPTR GCDest, void *pSrc, uint32_t cb)
324	{
325	#ifdef IN_RC
326	int rc = MMGCRamWrite(pVM, (void *)GCDest, pSrc, cb);
327	if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
328	return rc;
329	/*
330	* The page pool cache may end up here in some cases because it
331	* flushed one of the shadow mappings used by the trapping
332	* instruction and it either flushed the TLB or the CPU reused it.
333	* We want to play safe here, verifying that we've got write
334	* access doesn't cost us much (see PGMPhysGCPtr2GCPhys()).
335	*/
336	uint64_t fFlags;
337	RTGCPHYS GCPhys;
338	rc = PGMGstGetPage(pVM, GCDest, &fFlags, &GCPhys);
339	if (RT_FAILURE(rc))
340	return rc;
341	if ( !(fFlags & X86_PTE_RW)
342	&& (CPUMGetGuestCR0(pVM) & X86_CR0_WP))
343	return VERR_ACCESS_DENIED;
344
345	PGMPhysWrite(pVM, GCPhys + ((RTGCUINTPTR)GCDest & PAGE_OFFSET_MASK), pSrc, cb);
346	return VINF_SUCCESS;
347
348	#else
349	return PGMPhysWriteGCPtr(pVM, GCDest, pSrc, cb);
350	#endif
351	}
352
353
354	/** Convert sel:addr to a flat GC address. */
355	DECLINLINE(RTGCPTR) emConvertToFlatAddr(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, POP_PARAMETER pParam, RTGCPTR pvAddr)
356	{
357	DIS_SELREG enmPrefixSeg = DISDetectSegReg(pCpu, pParam);
358	return SELMToFlat(pVM, enmPrefixSeg, pRegFrame, pvAddr);
359	}
360
361
362	#if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
363	/**
364	* Get the mnemonic for the disassembled instruction.
365	*
366	* GC/R0 doesn't include the strings in the DIS tables because
367	* of limited space.
368	*/
369	static const char *emGetMnemonic(PDISCPUSTATE pCpu)
370	{
371	switch (pCpu->pCurInstr->opcode)
372	{
373	case OP_XCHG: return "Xchg";
374	case OP_DEC: return "Dec";
375	case OP_INC: return "Inc";
376	case OP_POP: return "Pop";
377	case OP_OR: return "Or";
378	case OP_AND: return "And";
379	case OP_MOV: return "Mov";
380	case OP_INVLPG: return "InvlPg";
381	case OP_CPUID: return "CpuId";
382	case OP_MOV_CR: return "MovCRx";
383	case OP_MOV_DR: return "MovDRx";
384	case OP_LLDT: return "LLdt";
385	case OP_LGDT: return "LGdt";
386	case OP_LIDT: return "LGdt";
387	case OP_CLTS: return "Clts";
388	case OP_MONITOR: return "Monitor";
389	case OP_MWAIT: return "MWait";
390	case OP_RDMSR: return "Rdmsr";
391	case OP_WRMSR: return "Wrmsr";
392	case OP_ADD: return "Add";
393	case OP_ADC: return "Adc";
394	case OP_SUB: return "Sub";
395	case OP_SBB: return "Sbb";
396	case OP_RDTSC: return "Rdtsc";
397	case OP_STI: return "Sti";
398	case OP_XADD: return "XAdd";
399	case OP_HLT: return "Hlt";
400	case OP_IRET: return "Iret";
401	case OP_MOVNTPS: return "MovNTPS";
402	case OP_STOSWD: return "StosWD";
403	case OP_WBINVD: return "WbInvd";
404	case OP_XOR: return "Xor";
405	case OP_BTR: return "Btr";
406	case OP_BTS: return "Bts";
407	case OP_BTC: return "Btc";
408	case OP_LMSW: return "Lmsw";
409	case OP_CMPXCHG: return pCpu->prefix & PREFIX_LOCK ? "Lock CmpXchg" : "CmpXchg";
410	case OP_CMPXCHG8B: return pCpu->prefix & PREFIX_LOCK ? "Lock CmpXchg8b" : "CmpXchg8b";
411
412	default:
413	Log(("Unknown opcode %d\n", pCpu->pCurInstr->opcode));
414	return "???";
415	}
416	}
417	#endif /* VBOX_STRICT \|\| LOG_ENABLED */
418
419
420	/**
421	* XCHG instruction emulation.
422	*/
423	static int emInterpretXchg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
424	{
425	OP_PARAMVAL param1, param2;
426
427	/* Source to make DISQueryParamVal read the register value - ugly hack */
428	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
429	if(RT_FAILURE(rc))
430	return VERR_EM_INTERPRETER;
431
432	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
433	if(RT_FAILURE(rc))
434	return VERR_EM_INTERPRETER;
435
436	#ifdef IN_RC
437	if (TRPMHasTrap(pVM))
438	{
439	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
440	{
441	#endif
442	RTGCPTR pParam1 = 0, pParam2 = 0;
443	uint64_t valpar1, valpar2;
444
445	AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
446	switch(param1.type)
447	{
448	case PARMTYPE_IMMEDIATE: /* register type is translated to this one too */
449	valpar1 = param1.val.val64;
450	break;
451
452	case PARMTYPE_ADDRESS:
453	pParam1 = (RTGCPTR)param1.val.val64;
454	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
455	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
456	rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
457	if (RT_FAILURE(rc))
458	{
459	AssertMsgFailed(("MMGCRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
460	return VERR_EM_INTERPRETER;
461	}
462	break;
463
464	default:
465	AssertFailed();
466	return VERR_EM_INTERPRETER;
467	}
468
469	switch(param2.type)
470	{
471	case PARMTYPE_ADDRESS:
472	pParam2 = (RTGCPTR)param2.val.val64;
473	pParam2 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param2, pParam2);
474	EM_ASSERT_FAULT_RETURN(pParam2 == pvFault, VERR_EM_INTERPRETER);
475	rc = emRamRead(pVM, &valpar2, pParam2, param2.size);
476	if (RT_FAILURE(rc))
477	{
478	AssertMsgFailed(("MMGCRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
479	}
480	break;
481
482	case PARMTYPE_IMMEDIATE:
483	valpar2 = param2.val.val64;
484	break;
485
486	default:
487	AssertFailed();
488	return VERR_EM_INTERPRETER;
489	}
490
491	/* Write value of parameter 2 to parameter 1 (reg or memory address) */
492	if (pParam1 == 0)
493	{
494	Assert(param1.type == PARMTYPE_IMMEDIATE); /* register actually */
495	switch(param1.size)
496	{
497	case 1: //special case for AH etc
498	rc = DISWriteReg8(pRegFrame, pCpu->param1.base.reg_gen, (uint8_t )valpar2); break;
499	case 2: rc = DISWriteReg16(pRegFrame, pCpu->param1.base.reg_gen, (uint16_t)valpar2); break;
500	case 4: rc = DISWriteReg32(pRegFrame, pCpu->param1.base.reg_gen, (uint32_t)valpar2); break;
501	case 8: rc = DISWriteReg64(pRegFrame, pCpu->param1.base.reg_gen, valpar2); break;
502	default: AssertFailedReturn(VERR_EM_INTERPRETER);
503	}
504	if (RT_FAILURE(rc))
505	return VERR_EM_INTERPRETER;
506	}
507	else
508	{
509	rc = emRamWrite(pVM, pParam1, &valpar2, param1.size);
510	if (RT_FAILURE(rc))
511	{
512	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
513	return VERR_EM_INTERPRETER;
514	}
515	}
516
517	/* Write value of parameter 1 to parameter 2 (reg or memory address) */
518	if (pParam2 == 0)
519	{
520	Assert(param2.type == PARMTYPE_IMMEDIATE); /* register actually */
521	switch(param2.size)
522	{
523	case 1: //special case for AH etc
524	rc = DISWriteReg8(pRegFrame, pCpu->param2.base.reg_gen, (uint8_t )valpar1); break;
525	case 2: rc = DISWriteReg16(pRegFrame, pCpu->param2.base.reg_gen, (uint16_t)valpar1); break;
526	case 4: rc = DISWriteReg32(pRegFrame, pCpu->param2.base.reg_gen, (uint32_t)valpar1); break;
527	case 8: rc = DISWriteReg64(pRegFrame, pCpu->param2.base.reg_gen, valpar1); break;
528	default: AssertFailedReturn(VERR_EM_INTERPRETER);
529	}
530	if (RT_FAILURE(rc))
531	return VERR_EM_INTERPRETER;
532	}
533	else
534	{
535	rc = emRamWrite(pVM, pParam2, &valpar1, param2.size);
536	if (RT_FAILURE(rc))
537	{
538	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
539	return VERR_EM_INTERPRETER;
540	}
541	}
542
543	*pcbSize = param2.size;
544	return VINF_SUCCESS;
545	#ifdef IN_RC
546	}
547	}
548	#endif
549	return VERR_EM_INTERPRETER;
550	}
551
552
553	/**
554	* INC and DEC emulation.
555	*/
556	static int emInterpretIncDec(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
557	PFNEMULATEPARAM2 pfnEmulate)
558	{
559	OP_PARAMVAL param1;
560
561	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
562	if(RT_FAILURE(rc))
563	return VERR_EM_INTERPRETER;
564
565	#ifdef IN_RC
566	if (TRPMHasTrap(pVM))
567	{
568	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
569	{
570	#endif
571	RTGCPTR pParam1 = 0;
572	uint64_t valpar1;
573
574	if (param1.type == PARMTYPE_ADDRESS)
575	{
576	pParam1 = (RTGCPTR)param1.val.val64;
577	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
578	#ifdef IN_RC
579	/* Safety check (in theory it could cross a page boundary and fault there though) */
580	AssertReturn(pParam1 == pvFault, VERR_EM_INTERPRETER);
581	#endif
582	rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
583	if (RT_FAILURE(rc))
584	{
585	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
586	return VERR_EM_INTERPRETER;
587	}
588	}
589	else
590	{
591	AssertFailed();
592	return VERR_EM_INTERPRETER;
593	}
594
595	uint32_t eflags;
596
597	eflags = pfnEmulate(&valpar1, param1.size);
598
599	/* Write result back */
600	rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
601	if (RT_FAILURE(rc))
602	{
603	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
604	return VERR_EM_INTERPRETER;
605	}
606
607	/* Update guest's eflags and finish. */
608	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
609	\| (eflags & (X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
610
611	/* All done! */
612	*pcbSize = param1.size;
613	return VINF_SUCCESS;
614	#ifdef IN_RC
615	}
616	}
617	#endif
618	return VERR_EM_INTERPRETER;
619	}
620
621
622	/**
623	* POP Emulation.
624	*/
625	static int emInterpretPop(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
626	{
627	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
628	OP_PARAMVAL param1;
629	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
630	if(RT_FAILURE(rc))
631	return VERR_EM_INTERPRETER;
632
633	#ifdef IN_RC
634	if (TRPMHasTrap(pVM))
635	{
636	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
637	{
638	#endif
639	RTGCPTR pParam1 = 0;
640	uint32_t valpar1;
641	RTGCPTR pStackVal;
642
643	/* Read stack value first */
644	if (SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->ss, &pRegFrame->ssHid) == CPUMODE_16BIT)
645	return VERR_EM_INTERPRETER; /* No legacy 16 bits stuff here, please. */
646
647	/* Convert address; don't bother checking limits etc, as we only read here */
648	pStackVal = SELMToFlat(pVM, DIS_SELREG_SS, pRegFrame, (RTGCPTR)pRegFrame->esp);
649	if (pStackVal == 0)
650	return VERR_EM_INTERPRETER;
651
652	rc = emRamRead(pVM, &valpar1, pStackVal, param1.size);
653	if (RT_FAILURE(rc))
654	{
655	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
656	return VERR_EM_INTERPRETER;
657	}
658
659	if (param1.type == PARMTYPE_ADDRESS)
660	{
661	pParam1 = (RTGCPTR)param1.val.val64;
662
663	/* pop [esp+xx] uses esp after the actual pop! */
664	AssertCompile(USE_REG_ESP == USE_REG_SP);
665	if ( (pCpu->param1.flags & USE_BASE)
666	&& (pCpu->param1.flags & (USE_REG_GEN16\|USE_REG_GEN32))
667	&& pCpu->param1.base.reg_gen == USE_REG_ESP
668	)
669	pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + param1.size);
670
671	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
672	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault \|\| (RTGCPTR)pRegFrame->esp == pvFault, VERR_EM_INTERPRETER);
673	rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
674	if (RT_FAILURE(rc))
675	{
676	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
677	return VERR_EM_INTERPRETER;
678	}
679
680	/* Update ESP as the last step */
681	pRegFrame->esp += param1.size;
682	}
683	else
684	{
685	#ifndef DEBUG_bird // annoying assertion.
686	AssertFailed();
687	#endif
688	return VERR_EM_INTERPRETER;
689	}
690
691	/* All done! */
692	*pcbSize = param1.size;
693	return VINF_SUCCESS;
694	#ifdef IN_RC
695	}
696	}
697	#endif
698	return VERR_EM_INTERPRETER;
699	}
700
701
702	/**
703	* XOR/OR/AND Emulation.
704	*/
705	static int emInterpretOrXorAnd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
706	PFNEMULATEPARAM3 pfnEmulate)
707	{
708	OP_PARAMVAL param1, param2;
709
710	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
711	if(RT_FAILURE(rc))
712	return VERR_EM_INTERPRETER;
713
714	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
715	if(RT_FAILURE(rc))
716	return VERR_EM_INTERPRETER;
717
718	#ifdef IN_RC
719	if (TRPMHasTrap(pVM))
720	{
721	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
722	{
723	#endif
724	RTGCPTR pParam1;
725	uint64_t valpar1, valpar2;
726
727	if (pCpu->param1.size != pCpu->param2.size)
728	{
729	if (pCpu->param1.size < pCpu->param2.size)
730	{
731	AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pCpu), (RTGCPTR)pRegFrame->rip, pCpu->param1.size, pCpu->param2.size)); /* should never happen! */
732	return VERR_EM_INTERPRETER;
733	}
734	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
735	pCpu->param2.size = pCpu->param1.size;
736	param2.size = param1.size;
737	}
738
739	/* The destination is always a virtual address */
740	if (param1.type == PARMTYPE_ADDRESS)
741	{
742	pParam1 = (RTGCPTR)param1.val.val64;
743	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
744	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
745	rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
746	if (RT_FAILURE(rc))
747	{
748	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
749	return VERR_EM_INTERPRETER;
750	}
751	}
752	else
753	{
754	AssertFailed();
755	return VERR_EM_INTERPRETER;
756	}
757
758	/* Register or immediate data */
759	switch(param2.type)
760	{
761	case PARMTYPE_IMMEDIATE: /* both immediate data and register (ugly) */
762	valpar2 = param2.val.val64;
763	break;
764
765	default:
766	AssertFailed();
767	return VERR_EM_INTERPRETER;
768	}
769
770	LogFlow(("emInterpretOrXorAnd %s %RGv %RX64 - %RX64 size %d (%d)\n", emGetMnemonic(pCpu), pParam1, valpar1, valpar2, param2.size, param1.size));
771
772	/* Data read, emulate instruction. */
773	uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
774
775	LogFlow(("emInterpretOrXorAnd %s result %RX64\n", emGetMnemonic(pCpu), valpar1));
776
777	/* Update guest's eflags and finish. */
778	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
779	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
780
781	/* And write it back */
782	rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
783	if (RT_SUCCESS(rc))
784	{
785	/* All done! */
786	*pcbSize = param2.size;
787	return VINF_SUCCESS;
788	}
789	#ifdef IN_RC
790	}
791	}
792	#endif
793	return VERR_EM_INTERPRETER;
794	}
795
796
797	/**
798	* LOCK XOR/OR/AND Emulation.
799	*/
800	static int emInterpretLockOrXorAnd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
801	uint32_t *pcbSize, PFNEMULATELOCKPARAM3 pfnEmulate)
802	{
803	void *pvParam1;
804	OP_PARAMVAL param1, param2;
805
806	#if HC_ARCH_BITS == 32
807	Assert(pCpu->param1.size <= 4);
808	#endif
809
810	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
811	if(RT_FAILURE(rc))
812	return VERR_EM_INTERPRETER;
813
814	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
815	if(RT_FAILURE(rc))
816	return VERR_EM_INTERPRETER;
817
818	if (pCpu->param1.size != pCpu->param2.size)
819	{
820	AssertMsgReturn(pCpu->param1.size >= pCpu->param2.size, /* should never happen! */
821	("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pCpu), (RTGCPTR)pRegFrame->rip, pCpu->param1.size, pCpu->param2.size),
822	VERR_EM_INTERPRETER);
823
824	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
825	pCpu->param2.size = pCpu->param1.size;
826	param2.size = param1.size;
827	}
828
829	#ifdef IN_RC
830	/* Safety check (in theory it could cross a page boundary and fault there though) */
831	Assert( TRPMHasTrap(pVM)
832	&& (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW));
833	EM_ASSERT_FAULT_RETURN(GCPtrPar1 == pvFault, VERR_EM_INTERPRETER);
834	#endif
835
836	/* Register and immediate data == PARMTYPE_IMMEDIATE */
837	AssertReturn(param2.type == PARMTYPE_IMMEDIATE, VERR_EM_INTERPRETER);
838	RTGCUINTREG ValPar2 = param2.val.val64;
839
840	/* The destination is always a virtual address */
841	AssertReturn(param1.type == PARMTYPE_ADDRESS, VERR_EM_INTERPRETER);
842
843	RTGCPTR GCPtrPar1 = param1.val.val64;
844	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
845	#ifdef IN_RC
846	pvParam1 = (void *)GCPtrPar1;
847	#else
848	PGMPAGEMAPLOCK Lock;
849	rc = PGMPhysGCPtr2CCPtr(pVM, GCPtrPar1, &pvParam1, &Lock);
850	AssertRCReturn(rc, VERR_EM_INTERPRETER);
851	#endif
852
853	/* Try emulate it with a one-shot #PF handler in place. (RC) */
854	Log2(("%s %RGv imm%d=%RX64\n", emGetMnemonic(pCpu), GCPtrPar1, pCpu->param2.size*8, ValPar2));
855
856	RTGCUINTREG32 eflags = 0;
857	#ifdef IN_RC
858	MMGCRamRegisterTrapHandler(pVM);
859	#endif
860	rc = pfnEmulate(pvParam1, ValPar2, pCpu->param2.size, &eflags);
861	#ifdef IN_RC
862	MMGCRamDeregisterTrapHandler(pVM);
863	#else
864	PGMPhysReleasePageMappingLock(pVM, &Lock);
865	#endif
866	if (RT_FAILURE(rc))
867	{
868	Log(("%s %RGv imm%d=%RX64-> emulation failed due to page fault!\n", emGetMnemonic(pCpu), GCPtrPar1, pCpu->param2.size*8, ValPar2));
869	return VERR_EM_INTERPRETER;
870	}
871
872	/* Update guest's eflags and finish. */
873	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
874	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
875
876	*pcbSize = param2.size;
877	return VINF_SUCCESS;
878	}
879
880
881	/**
882	* ADD, ADC & SUB Emulation.
883	*/
884	static int emInterpretAddSub(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
885	PFNEMULATEPARAM3 pfnEmulate)
886	{
887	OP_PARAMVAL param1, param2;
888	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
889	if(RT_FAILURE(rc))
890	return VERR_EM_INTERPRETER;
891
892	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
893	if(RT_FAILURE(rc))
894	return VERR_EM_INTERPRETER;
895
896	#ifdef IN_RC
897	if (TRPMHasTrap(pVM))
898	{
899	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
900	{
901	#endif
902	RTGCPTR pParam1;
903	uint64_t valpar1, valpar2;
904
905	if (pCpu->param1.size != pCpu->param2.size)
906	{
907	if (pCpu->param1.size < pCpu->param2.size)
908	{
909	AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pCpu), (RTGCPTR)pRegFrame->rip, pCpu->param1.size, pCpu->param2.size)); /* should never happen! */
910	return VERR_EM_INTERPRETER;
911	}
912	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
913	pCpu->param2.size = pCpu->param1.size;
914	param2.size = param1.size;
915	}
916
917	/* The destination is always a virtual address */
918	if (param1.type == PARMTYPE_ADDRESS)
919	{
920	pParam1 = (RTGCPTR)param1.val.val64;
921	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
922	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
923	rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
924	if (RT_FAILURE(rc))
925	{
926	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
927	return VERR_EM_INTERPRETER;
928	}
929	}
930	else
931	{
932	#ifndef DEBUG_bird
933	AssertFailed();
934	#endif
935	return VERR_EM_INTERPRETER;
936	}
937
938	/* Register or immediate data */
939	switch(param2.type)
940	{
941	case PARMTYPE_IMMEDIATE: /* both immediate data and register (ugly) */
942	valpar2 = param2.val.val64;
943	break;
944
945	default:
946	AssertFailed();
947	return VERR_EM_INTERPRETER;
948	}
949
950	/* Data read, emulate instruction. */
951	uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
952
953	/* Update guest's eflags and finish. */
954	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
955	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
956
957	/* And write it back */
958	rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
959	if (RT_SUCCESS(rc))
960	{
961	/* All done! */
962	*pcbSize = param2.size;
963	return VINF_SUCCESS;
964	}
965	#ifdef IN_RC
966	}
967	}
968	#endif
969	return VERR_EM_INTERPRETER;
970	}
971
972
973	/**
974	* ADC Emulation.
975	*/
976	static int emInterpretAdc(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
977	{
978	if (pRegFrame->eflags.Bits.u1CF)
979	return emInterpretAddSub(pVM, pCpu, pRegFrame, pvFault, pcbSize, EMEmulateAdcWithCarrySet);
980	else
981	return emInterpretAddSub(pVM, pCpu, pRegFrame, pvFault, pcbSize, EMEmulateAdd);
982	}
983
984
985	/**
986	* BTR/C/S Emulation.
987	*/
988	static int emInterpretBitTest(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
989	PFNEMULATEPARAM2UINT32 pfnEmulate)
990	{
991	OP_PARAMVAL param1, param2;
992	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
993	if(RT_FAILURE(rc))
994	return VERR_EM_INTERPRETER;
995
996	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
997	if(RT_FAILURE(rc))
998	return VERR_EM_INTERPRETER;
999
1000	#ifdef IN_RC
1001	if (TRPMHasTrap(pVM))
1002	{
1003	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1004	{
1005	#endif
1006	RTGCPTR pParam1;
1007	uint64_t valpar1 = 0, valpar2;
1008	uint32_t eflags;
1009
1010	/* The destination is always a virtual address */
1011	if (param1.type != PARMTYPE_ADDRESS)
1012	return VERR_EM_INTERPRETER;
1013
1014	pParam1 = (RTGCPTR)param1.val.val64;
1015	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
1016
1017	/* Register or immediate data */
1018	switch(param2.type)
1019	{
1020	case PARMTYPE_IMMEDIATE: /* both immediate data and register (ugly) */
1021	valpar2 = param2.val.val64;
1022	break;
1023
1024	default:
1025	AssertFailed();
1026	return VERR_EM_INTERPRETER;
1027	}
1028
1029	Log2(("emInterpret%s: pvFault=%RGv pParam1=%RGv val2=%x\n", emGetMnemonic(pCpu), pvFault, pParam1, valpar2));
1030	pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + valpar2/8);
1031	EM_ASSERT_FAULT_RETURN((RTGCPTR)((RTGCUINTPTR)pParam1 & ~3) == pvFault, VERR_EM_INTERPRETER);
1032	rc = emRamRead(pVM, &valpar1, pParam1, 1);
1033	if (RT_FAILURE(rc))
1034	{
1035	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
1036	return VERR_EM_INTERPRETER;
1037	}
1038
1039	Log2(("emInterpretBtx: val=%x\n", valpar1));
1040	/* Data read, emulate bit test instruction. */
1041	eflags = pfnEmulate(&valpar1, valpar2 & 0x7);
1042
1043	Log2(("emInterpretBtx: val=%x CF=%d\n", valpar1, !!(eflags & X86_EFL_CF)));
1044
1045	/* Update guest's eflags and finish. */
1046	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1047	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1048
1049	/* And write it back */
1050	rc = emRamWrite(pVM, pParam1, &valpar1, 1);
1051	if (RT_SUCCESS(rc))
1052	{
1053	/* All done! */
1054	*pcbSize = 1;
1055	return VINF_SUCCESS;
1056	}
1057	#ifdef IN_RC
1058	}
1059	}
1060	#endif
1061	return VERR_EM_INTERPRETER;
1062	}
1063
1064
1065	/**
1066	* LOCK BTR/C/S Emulation.
1067	*/
1068	static int emInterpretLockBitTest(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
1069	uint32_t *pcbSize, PFNEMULATELOCKPARAM2 pfnEmulate)
1070	{
1071	void *pvParam1;
1072
1073	OP_PARAMVAL param1, param2;
1074	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
1075	if(RT_FAILURE(rc))
1076	return VERR_EM_INTERPRETER;
1077
1078	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1079	if(RT_FAILURE(rc))
1080	return VERR_EM_INTERPRETER;
1081
1082	/* The destination is always a virtual address */
1083	if (param1.type != PARMTYPE_ADDRESS)
1084	return VERR_EM_INTERPRETER;
1085
1086	/* Register and immediate data == PARMTYPE_IMMEDIATE */
1087	AssertReturn(param2.type == PARMTYPE_IMMEDIATE, VERR_EM_INTERPRETER);
1088	uint64_t ValPar2 = param2.val.val64;
1089
1090	/* Adjust the parameters so what we're dealing with is a bit within the byte pointed to. */
1091	RTGCPTR GCPtrPar1 = param1.val.val64;
1092	GCPtrPar1 = (GCPtrPar1 + ValPar2 / 8);
1093	ValPar2 &= 7;
1094
1095	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
1096	#ifdef IN_RC
1097	Assert(TRPMHasTrap(pVM));
1098	EM_ASSERT_FAULT_RETURN((RTGCPTR)((RTGCUINTPTR)GCPtrPar1 & ~(RTGCUINTPTR)3) == pvFault, VERR_EM_INTERPRETER);
1099	#endif
1100
1101	#ifdef IN_RC
1102	pvParam1 = (void *)GCPtrPar1;
1103	#else
1104	PGMPAGEMAPLOCK Lock;
1105	rc = PGMPhysGCPtr2CCPtr(pVM, GCPtrPar1, &pvParam1, &Lock);
1106	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1107	#endif
1108
1109	Log2(("emInterpretLockBitTest %s: pvFault=%RGv GCPtrPar1=%RGv imm=%RX64\n", emGetMnemonic(pCpu), pvFault, GCPtrPar1, ValPar2));
1110
1111	/* Try emulate it with a one-shot #PF handler in place. (RC) */
1112	RTGCUINTREG32 eflags = 0;
1113	#ifdef IN_RC
1114	MMGCRamRegisterTrapHandler(pVM);
1115	#endif
1116	rc = pfnEmulate(pvParam1, ValPar2, &eflags);
1117	#ifdef IN_RC
1118	MMGCRamDeregisterTrapHandler(pVM);
1119	#else
1120	PGMPhysReleasePageMappingLock(pVM, &Lock);
1121	#endif
1122	if (RT_FAILURE(rc))
1123	{
1124	Log(("emInterpretLockBitTest %s: %RGv imm%d=%RX64 -> emulation failed due to page fault!\n",
1125	emGetMnemonic(pCpu), GCPtrPar1, pCpu->param2.size*8, ValPar2));
1126	return VERR_EM_INTERPRETER;
1127	}
1128
1129	Log2(("emInterpretLockBitTest %s: GCPtrPar1=%RGv imm=%RX64 CF=%d\n", emGetMnemonic(pCpu), GCPtrPar1, ValPar2, !!(eflags & X86_EFL_CF)));
1130
1131	/* Update guest's eflags and finish. */
1132	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1133	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1134
1135	*pcbSize = 1;
1136	return VINF_SUCCESS;
1137	}
1138
1139
1140	/**
1141	* MOV emulation.
1142	*/
1143	static int emInterpretMov(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1144	{
1145	OP_PARAMVAL param1, param2;
1146	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
1147	if(RT_FAILURE(rc))
1148	return VERR_EM_INTERPRETER;
1149
1150	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1151	if(RT_FAILURE(rc))
1152	return VERR_EM_INTERPRETER;
1153
1154	#ifdef IN_RC
1155	if (TRPMHasTrap(pVM))
1156	{
1157	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1158	{
1159	#else
1160	/** @todo Make this the default and don't rely on TRPM information. */
1161	if (param1.type == PARMTYPE_ADDRESS)
1162	{
1163	#endif
1164	RTGCPTR pDest;
1165	uint64_t val64;
1166
1167	switch(param1.type)
1168	{
1169	case PARMTYPE_IMMEDIATE:
1170	if(!(param1.flags & (PARAM_VAL32\|PARAM_VAL64)))
1171	return VERR_EM_INTERPRETER;
1172	/* fallthru */
1173
1174	case PARMTYPE_ADDRESS:
1175	pDest = (RTGCPTR)param1.val.val64;
1176	pDest = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pDest);
1177	break;
1178
1179	default:
1180	AssertFailed();
1181	return VERR_EM_INTERPRETER;
1182	}
1183
1184	switch(param2.type)
1185	{
1186	case PARMTYPE_IMMEDIATE: /* register type is translated to this one too */
1187	val64 = param2.val.val64;
1188	break;
1189
1190	default:
1191	Log(("emInterpretMov: unexpected type=%d rip=%RGv\n", param2.type, (RTGCPTR)pRegFrame->rip));
1192	return VERR_EM_INTERPRETER;
1193	}
1194	#ifdef LOG_ENABLED
1195	if (pCpu->mode == CPUMODE_64BIT)
1196	LogFlow(("EMInterpretInstruction at %RGv: OP_MOV %RGv <- %RX64 (%d) &val64=%RHv\n", (RTGCPTR)pRegFrame->rip, pDest, val64, param2.size, &val64));
1197	else
1198	LogFlow(("EMInterpretInstruction at %08RX64: OP_MOV %RGv <- %08X (%d) &val64=%RHv\n", pRegFrame->rip, pDest, (uint32_t)val64, param2.size, &val64));
1199	#endif
1200
1201	Assert(param2.size <= 8 && param2.size > 0);
1202	EM_ASSERT_FAULT_RETURN(pDest == pvFault, VERR_EM_INTERPRETER);
1203	rc = emRamWrite(pVM, pDest, &val64, param2.size);
1204	if (RT_FAILURE(rc))
1205	return VERR_EM_INTERPRETER;
1206
1207	*pcbSize = param2.size;
1208	}
1209	else
1210	{ /* read fault */
1211	RTGCPTR pSrc;
1212	uint64_t val64;
1213
1214	/* Source */
1215	switch(param2.type)
1216	{
1217	case PARMTYPE_IMMEDIATE:
1218	if(!(param2.flags & (PARAM_VAL32\|PARAM_VAL64)))
1219	return VERR_EM_INTERPRETER;
1220	/* fallthru */
1221
1222	case PARMTYPE_ADDRESS:
1223	pSrc = (RTGCPTR)param2.val.val64;
1224	pSrc = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param2, pSrc);
1225	break;
1226
1227	default:
1228	return VERR_EM_INTERPRETER;
1229	}
1230
1231	Assert(param1.size <= 8 && param1.size > 0);
1232	EM_ASSERT_FAULT_RETURN(pSrc == pvFault, VERR_EM_INTERPRETER);
1233	rc = emRamRead(pVM, &val64, pSrc, param1.size);
1234	if (RT_FAILURE(rc))
1235	return VERR_EM_INTERPRETER;
1236
1237	/* Destination */
1238	switch(param1.type)
1239	{
1240	case PARMTYPE_REGISTER:
1241	switch(param1.size)
1242	{
1243	case 1: rc = DISWriteReg8(pRegFrame, pCpu->param1.base.reg_gen, (uint8_t) val64); break;
1244	case 2: rc = DISWriteReg16(pRegFrame, pCpu->param1.base.reg_gen, (uint16_t)val64); break;
1245	case 4: rc = DISWriteReg32(pRegFrame, pCpu->param1.base.reg_gen, (uint32_t)val64); break;
1246	case 8: rc = DISWriteReg64(pRegFrame, pCpu->param1.base.reg_gen, val64); break;
1247	default:
1248	return VERR_EM_INTERPRETER;
1249	}
1250	if (RT_FAILURE(rc))
1251	return rc;
1252	break;
1253
1254	default:
1255	return VERR_EM_INTERPRETER;
1256	}
1257	#ifdef LOG_ENABLED
1258	if (pCpu->mode == CPUMODE_64BIT)
1259	LogFlow(("EMInterpretInstruction: OP_MOV %RGv -> %RX64 (%d)\n", pSrc, val64, param1.size));
1260	else
1261	LogFlow(("EMInterpretInstruction: OP_MOV %RGv -> %08X (%d)\n", pSrc, (uint32_t)val64, param1.size));
1262	#endif
1263	}
1264	return VINF_SUCCESS;
1265	#ifdef IN_RC
1266	}
1267	#endif
1268	return VERR_EM_INTERPRETER;
1269	}
1270
1271
1272	#ifndef IN_RC
1273	/**
1274	* [REP] STOSWD emulation
1275	*/
1276	static int emInterpretStosWD(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1277	{
1278	int rc;
1279	RTGCPTR GCDest, GCOffset;
1280	uint32_t cbSize;
1281	uint64_t cTransfers;
1282	int offIncrement;
1283
1284	/* Don't support any but these three prefix bytes. */
1285	if ((pCpu->prefix & ~(PREFIX_ADDRSIZE\|PREFIX_OPSIZE\|PREFIX_REP\|PREFIX_REX)))
1286	return VERR_EM_INTERPRETER;
1287
1288	switch (pCpu->addrmode)
1289	{
1290	case CPUMODE_16BIT:
1291	GCOffset = pRegFrame->di;
1292	cTransfers = pRegFrame->cx;
1293	break;
1294	case CPUMODE_32BIT:
1295	GCOffset = pRegFrame->edi;
1296	cTransfers = pRegFrame->ecx;
1297	break;
1298	case CPUMODE_64BIT:
1299	GCOffset = pRegFrame->rdi;
1300	cTransfers = pRegFrame->rcx;
1301	break;
1302	default:
1303	AssertFailed();
1304	return VERR_EM_INTERPRETER;
1305	}
1306
1307	GCDest = SELMToFlat(pVM, DIS_SELREG_ES, pRegFrame, GCOffset);
1308	switch (pCpu->opmode)
1309	{
1310	case CPUMODE_16BIT:
1311	cbSize = 2;
1312	break;
1313	case CPUMODE_32BIT:
1314	cbSize = 4;
1315	break;
1316	case CPUMODE_64BIT:
1317	cbSize = 8;
1318	break;
1319	default:
1320	AssertFailed();
1321	return VERR_EM_INTERPRETER;
1322	}
1323
1324	offIncrement = pRegFrame->eflags.Bits.u1DF ? -(signed)cbSize : (signed)cbSize;
1325
1326	if (!(pCpu->prefix & PREFIX_REP))
1327	{
1328	LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d\n", pRegFrame->es, GCOffset, GCDest, cbSize));
1329
1330	rc = PGMPhysWriteGCPtr(pVM, GCDest, &pRegFrame->rax, cbSize);
1331	if (RT_FAILURE(rc))
1332	return VERR_EM_INTERPRETER;
1333	Assert(rc == VINF_SUCCESS);
1334
1335	/* Update (e/r)di. */
1336	switch (pCpu->addrmode)
1337	{
1338	case CPUMODE_16BIT:
1339	pRegFrame->di += offIncrement;
1340	break;
1341	case CPUMODE_32BIT:
1342	pRegFrame->edi += offIncrement;
1343	break;
1344	case CPUMODE_64BIT:
1345	pRegFrame->rdi += offIncrement;
1346	break;
1347	default:
1348	AssertFailed();
1349	return VERR_EM_INTERPRETER;
1350	}
1351
1352	}
1353	else
1354	{
1355	if (!cTransfers)
1356	return VINF_SUCCESS;
1357
1358	LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d cTransfers=%x DF=%d\n", pRegFrame->es, GCOffset, GCDest, cbSize, cTransfers, pRegFrame->eflags.Bits.u1DF));
1359	/* Access verification first; we currently can't recover properly from traps inside this instruction */
1360	rc = PGMVerifyAccess(pVM, GCDest - ((offIncrement > 0) ? 0 : ((cTransfers-1) * cbSize)), cTransfers * cbSize, X86_PTE_RW \| X86_PTE_US);
1361	if (rc != VINF_SUCCESS)
1362	{
1363	Log(("STOSWD will generate a trap -> recompiler, rc=%d\n", rc));
1364	return VERR_EM_INTERPRETER;
1365	}
1366
1367	/* REP case */
1368	while (cTransfers)
1369	{
1370	rc = PGMPhysWriteGCPtr(pVM, GCDest, &pRegFrame->rax, cbSize);
1371	if (RT_FAILURE(rc))
1372	{
1373	rc = VERR_EM_INTERPRETER;
1374	break;
1375	}
1376
1377	Assert(rc == VINF_SUCCESS);
1378	GCOffset += offIncrement;
1379	GCDest += offIncrement;
1380	cTransfers--;
1381	}
1382
1383	/* Update the registers. */
1384	switch (pCpu->addrmode)
1385	{
1386	case CPUMODE_16BIT:
1387	pRegFrame->di = GCOffset;
1388	pRegFrame->cx = cTransfers;
1389	break;
1390	case CPUMODE_32BIT:
1391	pRegFrame->edi = GCOffset;
1392	pRegFrame->ecx = cTransfers;
1393	break;
1394	case CPUMODE_64BIT:
1395	pRegFrame->rdi = GCOffset;
1396	pRegFrame->rcx = cTransfers;
1397	break;
1398	default:
1399	AssertFailed();
1400	return VERR_EM_INTERPRETER;
1401	}
1402	}
1403
1404	*pcbSize = cbSize;
1405	return rc;
1406	}
1407	#endif /* !IN_RC */
1408
1409	#ifndef IN_RC
1410
1411	/**
1412	* [LOCK] CMPXCHG emulation.
1413	*/
1414	static int emInterpretCmpXchg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1415	{
1416	OP_PARAMVAL param1, param2;
1417
1418	#if HC_ARCH_BITS == 32
1419	Assert(pCpu->param1.size <= 4);
1420	#endif
1421
1422	/* Source to make DISQueryParamVal read the register value - ugly hack */
1423	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1424	if(RT_FAILURE(rc))
1425	return VERR_EM_INTERPRETER;
1426
1427	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1428	if(RT_FAILURE(rc))
1429	return VERR_EM_INTERPRETER;
1430
1431	uint64_t valpar;
1432	switch(param2.type)
1433	{
1434	case PARMTYPE_IMMEDIATE: /* register actually */
1435	valpar = param2.val.val64;
1436	break;
1437
1438	default:
1439	return VERR_EM_INTERPRETER;
1440	}
1441
1442	PGMPAGEMAPLOCK Lock;
1443	RTGCPTR GCPtrPar1;
1444	void *pvParam1;
1445	uint64_t eflags;
1446
1447	AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
1448	switch(param1.type)
1449	{
1450	case PARMTYPE_ADDRESS:
1451	GCPtrPar1 = param1.val.val64;
1452	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
1453
1454	rc = PGMPhysGCPtr2CCPtr(pVM, GCPtrPar1, &pvParam1, &Lock);
1455	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1456	break;
1457
1458	default:
1459	return VERR_EM_INTERPRETER;
1460	}
1461
1462	LogFlow(("%s %RGv rax=%RX64 %RX64\n", emGetMnemonic(pCpu), GCPtrPar1, pRegFrame->rax, valpar));
1463
1464	if (pCpu->prefix & PREFIX_LOCK)
1465	eflags = EMEmulateLockCmpXchg(pvParam1, &pRegFrame->rax, valpar, pCpu->param2.size);
1466	else
1467	eflags = EMEmulateCmpXchg(pvParam1, &pRegFrame->rax, valpar, pCpu->param2.size);
1468
1469	LogFlow(("%s %RGv rax=%RX64 %RX64 ZF=%d\n", emGetMnemonic(pCpu), GCPtrPar1, pRegFrame->rax, valpar, !!(eflags & X86_EFL_ZF)));
1470
1471	/* Update guest's eflags and finish. */
1472	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1473	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1474
1475	*pcbSize = param2.size;
1476	PGMPhysReleasePageMappingLock(pVM, &Lock);
1477	return VINF_SUCCESS;
1478	}
1479
1480
1481	/**
1482	* [LOCK] CMPXCHG8B emulation.
1483	*/
1484	static int emInterpretCmpXchg8b(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1485	{
1486	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
1487	OP_PARAMVAL param1;
1488
1489	/* Source to make DISQueryParamVal read the register value - ugly hack */
1490	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1491	if(RT_FAILURE(rc))
1492	return VERR_EM_INTERPRETER;
1493
1494	RTGCPTR GCPtrPar1;
1495	void *pvParam1;
1496	uint64_t eflags;
1497	PGMPAGEMAPLOCK Lock;
1498
1499	AssertReturn(pCpu->param1.size == 8, VERR_EM_INTERPRETER);
1500	switch(param1.type)
1501	{
1502	case PARMTYPE_ADDRESS:
1503	GCPtrPar1 = param1.val.val64;
1504	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
1505
1506	rc = PGMPhysGCPtr2CCPtr(pVM, GCPtrPar1, &pvParam1, &Lock);
1507	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1508	break;
1509
1510	default:
1511	return VERR_EM_INTERPRETER;
1512	}
1513
1514	LogFlow(("%s %RGv=%08x eax=%08x\n", emGetMnemonic(pCpu), pvParam1, pRegFrame->eax));
1515
1516	if (pCpu->prefix & PREFIX_LOCK)
1517	eflags = EMEmulateLockCmpXchg8b(pvParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
1518	else
1519	eflags = EMEmulateCmpXchg8b(pvParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
1520
1521	LogFlow(("%s %RGv=%08x eax=%08x ZF=%d\n", emGetMnemonic(pCpu), pvParam1, pRegFrame->eax, !!(eflags & X86_EFL_ZF)));
1522
1523	/* Update guest's eflags and finish; note that only ZF is affected. */
1524	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_ZF))
1525	\| (eflags & (X86_EFL_ZF));
1526
1527	*pcbSize = 8;
1528	PGMPhysReleasePageMappingLock(pVM, &Lock);
1529	return VINF_SUCCESS;
1530	}
1531
1532	#else /* IN_RC */
1533
1534	/**
1535	* [LOCK] CMPXCHG emulation.
1536	*/
1537	static int emInterpretCmpXchg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1538	{
1539	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
1540	OP_PARAMVAL param1, param2;
1541
1542	/* Source to make DISQueryParamVal read the register value - ugly hack */
1543	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1544	if(RT_FAILURE(rc))
1545	return VERR_EM_INTERPRETER;
1546
1547	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1548	if(RT_FAILURE(rc))
1549	return VERR_EM_INTERPRETER;
1550
1551	if (TRPMHasTrap(pVM))
1552	{
1553	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1554	{
1555	RTRCPTR pParam1;
1556	uint32_t valpar, eflags;
1557
1558	AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
1559	switch(param1.type)
1560	{
1561	case PARMTYPE_ADDRESS:
1562	pParam1 = (RTRCPTR)param1.val.val64;
1563	pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);
1564	EM_ASSERT_FAULT_RETURN(pParam1 == (RTRCPTR)pvFault, VERR_EM_INTERPRETER);
1565	break;
1566
1567	default:
1568	return VERR_EM_INTERPRETER;
1569	}
1570
1571	switch(param2.type)
1572	{
1573	case PARMTYPE_IMMEDIATE: /* register actually */
1574	valpar = param2.val.val32;
1575	break;
1576
1577	default:
1578	return VERR_EM_INTERPRETER;
1579	}
1580
1581	LogFlow(("%s %RRv eax=%08x %08x\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax, valpar));
1582
1583	MMGCRamRegisterTrapHandler(pVM);
1584	if (pCpu->prefix & PREFIX_LOCK)
1585	rc = EMGCEmulateLockCmpXchg(pParam1, &pRegFrame->eax, valpar, pCpu->param2.size, &eflags);
1586	else
1587	rc = EMGCEmulateCmpXchg(pParam1, &pRegFrame->eax, valpar, pCpu->param2.size, &eflags);
1588	MMGCRamDeregisterTrapHandler(pVM);
1589
1590	if (RT_FAILURE(rc))
1591	{
1592	Log(("%s %RGv eax=%08x %08x -> emulation failed due to page fault!\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax, valpar));
1593	return VERR_EM_INTERPRETER;
1594	}
1595
1596	LogFlow(("%s %RRv eax=%08x %08x ZF=%d\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax, valpar, !!(eflags & X86_EFL_ZF)));
1597
1598	/* Update guest's eflags and finish. */
1599	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1600	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1601
1602	*pcbSize = param2.size;
1603	return VINF_SUCCESS;
1604	}
1605	}
1606	return VERR_EM_INTERPRETER;
1607	}
1608
1609
1610	/**
1611	* [LOCK] CMPXCHG8B emulation.
1612	*/
1613	static int emInterpretCmpXchg8b(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1614	{
1615	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
1616	OP_PARAMVAL param1;
1617
1618	/* Source to make DISQueryParamVal read the register value - ugly hack */
1619	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1620	if(RT_FAILURE(rc))
1621	return VERR_EM_INTERPRETER;
1622
1623	if (TRPMHasTrap(pVM))
1624	{
1625	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1626	{
1627	RTRCPTR pParam1;
1628	uint32_t eflags;
1629
1630	AssertReturn(pCpu->param1.size == 8, VERR_EM_INTERPRETER);
1631	switch(param1.type)
1632	{
1633	case PARMTYPE_ADDRESS:
1634	pParam1 = (RTRCPTR)param1.val.val64;
1635	pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);
1636	EM_ASSERT_FAULT_RETURN(pParam1 == (RTRCPTR)pvFault, VERR_EM_INTERPRETER);
1637	break;
1638
1639	default:
1640	return VERR_EM_INTERPRETER;
1641	}
1642
1643	LogFlow(("%s %RRv=%08x eax=%08x\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax));
1644
1645	MMGCRamRegisterTrapHandler(pVM);
1646	if (pCpu->prefix & PREFIX_LOCK)
1647	rc = EMGCEmulateLockCmpXchg8b(pParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx, &eflags);
1648	else
1649	rc = EMGCEmulateCmpXchg8b(pParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx, &eflags);
1650	MMGCRamDeregisterTrapHandler(pVM);
1651
1652	if (RT_FAILURE(rc))
1653	{
1654	Log(("%s %RGv=%08x eax=%08x -> emulation failed due to page fault!\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax));
1655	return VERR_EM_INTERPRETER;
1656	}
1657
1658	LogFlow(("%s %RGv=%08x eax=%08x ZF=%d\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax, !!(eflags & X86_EFL_ZF)));
1659
1660	/* Update guest's eflags and finish; note that only ZF is affected. */
1661	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_ZF))
1662	\| (eflags & (X86_EFL_ZF));
1663
1664	*pcbSize = 8;
1665	return VINF_SUCCESS;
1666	}
1667	}
1668	return VERR_EM_INTERPRETER;
1669	}
1670
1671	#endif /* IN_RC */
1672
1673	#ifdef IN_RC
1674	/**
1675	* [LOCK] XADD emulation.
1676	*/
1677	static int emInterpretXAdd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1678	{
1679	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
1680	OP_PARAMVAL param1;
1681	uint32_t *pParamReg2;
1682	size_t cbSizeParamReg2;
1683
1684	/* Source to make DISQueryParamVal read the register value - ugly hack */
1685	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1686	if(RT_FAILURE(rc))
1687	return VERR_EM_INTERPRETER;
1688
1689	rc = DISQueryParamRegPtr(pRegFrame, pCpu, &pCpu->param2, (void **)&pParamReg2, &cbSizeParamReg2);
1690	Assert(cbSizeParamReg2 <= 4);
1691	if(RT_FAILURE(rc))
1692	return VERR_EM_INTERPRETER;
1693
1694	if (TRPMHasTrap(pVM))
1695	{
1696	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1697	{
1698	RTRCPTR pParam1;
1699	uint32_t eflags;
1700
1701	AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
1702	switch(param1.type)
1703	{
1704	case PARMTYPE_ADDRESS:
1705	pParam1 = (RTRCPTR)param1.val.val64;
1706	pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);
1707	EM_ASSERT_FAULT_RETURN(pParam1 == (RTRCPTR)pvFault, VERR_EM_INTERPRETER);
1708	break;
1709
1710	default:
1711	return VERR_EM_INTERPRETER;
1712	}
1713
1714	LogFlow(("XAdd %RRv=%08x reg=%08x\n", pParam1, *pParamReg2));
1715
1716	MMGCRamRegisterTrapHandler(pVM);
1717	if (pCpu->prefix & PREFIX_LOCK)
1718	rc = EMGCEmulateLockXAdd(pParam1, pParamReg2, cbSizeParamReg2, &eflags);
1719	else
1720	rc = EMGCEmulateXAdd(pParam1, pParamReg2, cbSizeParamReg2, &eflags);
1721	MMGCRamDeregisterTrapHandler(pVM);
1722
1723	if (RT_FAILURE(rc))
1724	{
1725	Log(("XAdd %RGv reg=%08x -> emulation failed due to page fault!\n", pParam1, *pParamReg2));
1726	return VERR_EM_INTERPRETER;
1727	}
1728
1729	LogFlow(("XAdd %RGv reg=%08x ZF=%d\n", pParam1, *pParamReg2, !!(eflags & X86_EFL_ZF)));
1730
1731	/* Update guest's eflags and finish. */
1732	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1733	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1734
1735	*pcbSize = cbSizeParamReg2;
1736	return VINF_SUCCESS;
1737	}
1738	}
1739	return VERR_EM_INTERPRETER;
1740	}
1741	#endif /* IN_RC */
1742
1743
1744	#ifdef IN_RC
1745	/**
1746	* Interpret IRET (currently only to V86 code)
1747	*
1748	* @returns VBox status code.
1749	* @param pVM The VM handle.
1750	* @param pRegFrame The register frame.
1751	*
1752	*/
1753	VMMDECL(int) EMInterpretIret(PVM pVM, PCPUMCTXCORE pRegFrame)
1754	{
1755	RTGCUINTPTR pIretStack = (RTGCUINTPTR)pRegFrame->esp;
1756	RTGCUINTPTR eip, cs, esp, ss, eflags, ds, es, fs, gs, uMask;
1757	int rc;
1758
1759	Assert(!CPUMIsGuestIn64BitCode(pVM, pRegFrame));
1760
1761	rc = emRamRead(pVM, &eip, (RTGCPTR)pIretStack , 4);
1762	rc \|= emRamRead(pVM, &cs, (RTGCPTR)(pIretStack + 4), 4);
1763	rc \|= emRamRead(pVM, &eflags, (RTGCPTR)(pIretStack + 8), 4);
1764	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1765	AssertReturn(eflags & X86_EFL_VM, VERR_EM_INTERPRETER);
1766
1767	rc \|= emRamRead(pVM, &esp, (RTGCPTR)(pIretStack + 12), 4);
1768	rc \|= emRamRead(pVM, &ss, (RTGCPTR)(pIretStack + 16), 4);
1769	rc \|= emRamRead(pVM, &es, (RTGCPTR)(pIretStack + 20), 4);
1770	rc \|= emRamRead(pVM, &ds, (RTGCPTR)(pIretStack + 24), 4);
1771	rc \|= emRamRead(pVM, &fs, (RTGCPTR)(pIretStack + 28), 4);
1772	rc \|= emRamRead(pVM, &gs, (RTGCPTR)(pIretStack + 32), 4);
1773	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1774
1775	pRegFrame->eip = eip & 0xffff;
1776	pRegFrame->cs = cs;
1777
1778	/* Mask away all reserved bits */
1779	uMask = X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_RF \| X86_EFL_VM \| X86_EFL_AC \| X86_EFL_VIF \| X86_EFL_VIP \| X86_EFL_ID;
1780	eflags &= uMask;
1781
1782	#ifndef IN_RING0
1783	CPUMRawSetEFlags(pVM, pRegFrame, eflags);
1784	#endif
1785	Assert((pRegFrame->eflags.u32 & (X86_EFL_IF\|X86_EFL_IOPL)) == X86_EFL_IF);
1786
1787	pRegFrame->esp = esp;
1788	pRegFrame->ss = ss;
1789	pRegFrame->ds = ds;
1790	pRegFrame->es = es;
1791	pRegFrame->fs = fs;
1792	pRegFrame->gs = gs;
1793
1794	return VINF_SUCCESS;
1795	}
1796	#endif /* IN_RC */
1797
1798
1799	/**
1800	* IRET Emulation.
1801	*/
1802	static int emInterpretIret(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1803	{
1804	/* only allow direct calls to EMInterpretIret for now */
1805	return VERR_EM_INTERPRETER;
1806	}
1807
1808	/**
1809	* WBINVD Emulation.
1810	*/
1811	static int emInterpretWbInvd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1812	{
1813	/* Nothing to do. */
1814	return VINF_SUCCESS;
1815	}
1816
1817
1818	/**
1819	* Interpret INVLPG
1820	*
1821	* @returns VBox status code.
1822	* @param pVM The VM handle.
1823	* @param pRegFrame The register frame.
1824	* @param pAddrGC Operand address
1825	*
1826	*/
1827	VMMDECL(int) EMInterpretInvlpg(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC)
1828	{
1829	int rc;
1830
1831	/** @todo is addr always a flat linear address or ds based
1832	* (in absence of segment override prefixes)????
1833	*/
1834	#ifdef IN_RC
1835	LogFlow(("RC: EMULATE: invlpg %RGv\n", pAddrGC));
1836	#endif
1837	rc = PGMInvalidatePage(pVM, pAddrGC);
1838	if ( rc == VINF_SUCCESS
1839	\|\| rc == VINF_PGM_SYNC_CR3 /* we can rely on the FF */)
1840	return VINF_SUCCESS;
1841	AssertMsgReturn( rc == VERR_REM_FLUSHED_PAGES_OVERFLOW
1842	\|\| rc == VINF_EM_RAW_EMULATE_INSTR,
1843	("%Rrc addr=%RGv\n", rc, pAddrGC),
1844	VERR_EM_INTERPRETER);
1845	return rc;
1846	}
1847
1848
1849	/**
1850	* INVLPG Emulation.
1851	*/
1852	static int emInterpretInvlPg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1853	{
1854	OP_PARAMVAL param1;
1855	RTGCPTR addr;
1856
1857	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1858	if(RT_FAILURE(rc))
1859	return VERR_EM_INTERPRETER;
1860
1861	switch(param1.type)
1862	{
1863	case PARMTYPE_IMMEDIATE:
1864	case PARMTYPE_ADDRESS:
1865	if(!(param1.flags & (PARAM_VAL32\|PARAM_VAL64)))
1866	return VERR_EM_INTERPRETER;
1867	addr = (RTGCPTR)param1.val.val64;
1868	break;
1869
1870	default:
1871	return VERR_EM_INTERPRETER;
1872	}
1873
1874	/** @todo is addr always a flat linear address or ds based
1875	* (in absence of segment override prefixes)????
1876	*/
1877	#ifdef IN_RC
1878	LogFlow(("RC: EMULATE: invlpg %RGv\n", addr));
1879	#endif
1880	rc = PGMInvalidatePage(pVM, addr);
1881	if ( rc == VINF_SUCCESS
1882	\|\| rc == VINF_PGM_SYNC_CR3 /* we can rely on the FF */)
1883	return VINF_SUCCESS;
1884	AssertMsgReturn( rc == VERR_REM_FLUSHED_PAGES_OVERFLOW
1885	\|\| rc == VINF_EM_RAW_EMULATE_INSTR,
1886	("%Rrc addr=%RGv\n", rc, addr),
1887	VERR_EM_INTERPRETER);
1888	return rc;
1889	}
1890
1891
1892	/**
1893	* Interpret CPUID given the parameters in the CPU context
1894	*
1895	* @returns VBox status code.
1896	* @param pVM The VM handle.
1897	* @param pRegFrame The register frame.
1898	*
1899	*/
1900	VMMDECL(int) EMInterpretCpuId(PVM pVM, PCPUMCTXCORE pRegFrame)
1901	{
1902	uint32_t iLeaf = pRegFrame->eax;
1903
1904	/* cpuid clears the high dwords of the affected 64 bits registers. */
1905	pRegFrame->rax = 0;
1906	pRegFrame->rbx = 0;
1907	pRegFrame->rcx = 0;
1908	pRegFrame->rdx = 0;
1909
1910	/* Note: operates the same in 64 and non-64 bits mode. */
1911	CPUMGetGuestCpuId(pVM, iLeaf, &pRegFrame->eax, &pRegFrame->ebx, &pRegFrame->ecx, &pRegFrame->edx);
1912	Log(("Emulate: CPUID %x -> %08x %08x %08x %08x\n", iLeaf, pRegFrame->eax, pRegFrame->ebx, pRegFrame->ecx, pRegFrame->edx));
1913	return VINF_SUCCESS;
1914	}
1915
1916
1917	/**
1918	* CPUID Emulation.
1919	*/
1920	static int emInterpretCpuId(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1921	{
1922	int rc = EMInterpretCpuId(pVM, pRegFrame);
1923	return rc;
1924	}
1925
1926
1927	/**
1928	* Interpret CRx read
1929	*
1930	* @returns VBox status code.
1931	* @param pVM The VM handle.
1932	* @param pRegFrame The register frame.
1933	* @param DestRegGen General purpose register index (USE_REG_E**))
1934	* @param SrcRegCRx CRx register index (USE_REG_CR*)
1935	*
1936	*/
1937	VMMDECL(int) EMInterpretCRxRead(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx)
1938	{
1939	int rc;
1940	uint64_t val64;
1941
1942	if (SrcRegCrx == USE_REG_CR8)
1943	{
1944	val64 = 0;
1945	rc = PDMApicGetTPR(pVM, (uint8_t *)&val64, NULL);
1946	AssertMsgRCReturn(rc, ("PDMApicGetTPR failed\n"), VERR_EM_INTERPRETER);
1947	}
1948	else
1949	{
1950	rc = CPUMGetGuestCRx(pVM, SrcRegCrx, &val64);
1951	AssertMsgRCReturn(rc, ("CPUMGetGuestCRx %d failed\n", SrcRegCrx), VERR_EM_INTERPRETER);
1952	}
1953
1954	if (CPUMIsGuestIn64BitCode(pVM, pRegFrame))
1955	rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
1956	else
1957	rc = DISWriteReg32(pRegFrame, DestRegGen, val64);
1958
1959	if(RT_SUCCESS(rc))
1960	{
1961	LogFlow(("MOV_CR: gen32=%d CR=%d val=%RX64\n", DestRegGen, SrcRegCrx, val64));
1962	return VINF_SUCCESS;
1963	}
1964	return VERR_EM_INTERPRETER;
1965	}
1966
1967
1968
1969	/**
1970	* Interpret CLTS
1971	*
1972	* @returns VBox status code.
1973	* @param pVM The VM handle.
1974	*
1975	*/
1976	VMMDECL(int) EMInterpretCLTS(PVM pVM)
1977	{
1978	uint64_t cr0 = CPUMGetGuestCR0(pVM);
1979	if (!(cr0 & X86_CR0_TS))
1980	return VINF_SUCCESS;
1981	return CPUMSetGuestCR0(pVM, cr0 & ~X86_CR0_TS);
1982	}
1983
1984	/**
1985	* CLTS Emulation.
1986	*/
1987	static int emInterpretClts(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1988	{
1989	return EMInterpretCLTS(pVM);
1990	}
1991
1992
1993	/**
1994	* Update CRx
1995	*
1996	* @returns VBox status code.
1997	* @param pVM The VM handle.
1998	* @param pRegFrame The register frame.
1999	* @param DestRegCRx CRx register index (USE_REG_CR*)
2000	* @param val New CRx value
2001	*
2002	*/
2003	static int EMUpdateCRx(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint64_t val)
2004	{
2005	uint64_t oldval;
2006	uint64_t msrEFER;
2007	int rc;
2008
2009	/** @todo Clean up this mess. */
2010	LogFlow(("EMInterpretCRxWrite at %RGv CR%d <- %RX64\n", (RTGCPTR)pRegFrame->rip, DestRegCrx, val));
2011	switch (DestRegCrx)
2012	{
2013	case USE_REG_CR0:
2014	oldval = CPUMGetGuestCR0(pVM);
2015	#ifdef IN_RC
2016	/* CR0.WP and CR0.AM changes require a reschedule run in ring 3. */
2017	if ( (val & (X86_CR0_WP \| X86_CR0_AM))
2018	!= (oldval & (X86_CR0_WP \| X86_CR0_AM)))
2019	return VERR_EM_INTERPRETER;
2020	#endif
2021	CPUMSetGuestCR0(pVM, val);
2022	val = CPUMGetGuestCR0(pVM);
2023	if ( (oldval & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE))
2024	!= (val & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE)))
2025	{
2026	/* global flush */
2027	rc = PGMFlushTLB(pVM, CPUMGetGuestCR3(pVM), true /* global */);
2028	AssertRCReturn(rc, rc);
2029	}
2030
2031	/* Deal with long mode enabling/disabling. */
2032	msrEFER = CPUMGetGuestEFER(pVM);
2033	if (msrEFER & MSR_K6_EFER_LME)
2034	{
2035	if ( !(oldval & X86_CR0_PG)
2036	&& (val & X86_CR0_PG))
2037	{
2038	/* Illegal to have an active 64 bits CS selector (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
2039	if (pRegFrame->csHid.Attr.n.u1Long)
2040	{
2041	AssertMsgFailed(("Illegal enabling of paging with CS.u1Long = 1!!\n"));
2042	return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
2043	}
2044
2045	/* Illegal to switch to long mode before activating PAE first (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
2046	if (!(CPUMGetGuestCR4(pVM) & X86_CR4_PAE))
2047	{
2048	AssertMsgFailed(("Illegal enabling of paging with PAE disabled!!\n"));
2049	return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
2050	}
2051	msrEFER \|= MSR_K6_EFER_LMA;
2052	}
2053	else
2054	if ( (oldval & X86_CR0_PG)
2055	&& !(val & X86_CR0_PG))
2056	{
2057	msrEFER &= ~MSR_K6_EFER_LMA;
2058	/* @todo Do we need to cut off rip here? High dword of rip is undefined, so it shouldn't really matter. */
2059	}
2060	CPUMSetGuestEFER(pVM, msrEFER);
2061	}
2062	return PGMChangeMode(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR4(pVM), CPUMGetGuestEFER(pVM));
2063
2064	case USE_REG_CR2:
2065	rc = CPUMSetGuestCR2(pVM, val); AssertRC(rc);
2066	return VINF_SUCCESS;
2067
2068	case USE_REG_CR3:
2069	/* Reloading the current CR3 means the guest just wants to flush the TLBs */
2070	rc = CPUMSetGuestCR3(pVM, val); AssertRC(rc);
2071	if (CPUMGetGuestCR0(pVM) & X86_CR0_PG)
2072	{
2073	/* flush */
2074	rc = PGMFlushTLB(pVM, val, !(CPUMGetGuestCR4(pVM) & X86_CR4_PGE));
2075	AssertRCReturn(rc, rc);
2076	}
2077	return VINF_SUCCESS;
2078
2079	case USE_REG_CR4:
2080	oldval = CPUMGetGuestCR4(pVM);
2081	rc = CPUMSetGuestCR4(pVM, val); AssertRC(rc);
2082	val = CPUMGetGuestCR4(pVM);
2083
2084	msrEFER = CPUMGetGuestEFER(pVM);
2085	/* Illegal to disable PAE when long mode is active. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
2086	if ( (msrEFER & MSR_K6_EFER_LMA)
2087	&& (oldval & X86_CR4_PAE)
2088	&& !(val & X86_CR4_PAE))
2089	{
2090	return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
2091	}
2092
2093	if ( (oldval & (X86_CR4_PGE\|X86_CR4_PAE\|X86_CR4_PSE))
2094	!= (val & (X86_CR4_PGE\|X86_CR4_PAE\|X86_CR4_PSE)))
2095	{
2096	/* global flush */
2097	rc = PGMFlushTLB(pVM, CPUMGetGuestCR3(pVM), true /* global */);
2098	AssertRCReturn(rc, rc);
2099	}
2100	# ifdef IN_RC
2101	/* Feeling extremely lazy. */
2102	if ( (oldval & (X86_CR4_OSFSXR\|X86_CR4_OSXMMEEXCPT\|X86_CR4_PCE\|X86_CR4_MCE\|X86_CR4_PAE\|X86_CR4_DE\|X86_CR4_TSD\|X86_CR4_PVI\|X86_CR4_VME))
2103	!= (val & (X86_CR4_OSFSXR\|X86_CR4_OSXMMEEXCPT\|X86_CR4_PCE\|X86_CR4_MCE\|X86_CR4_PAE\|X86_CR4_DE\|X86_CR4_TSD\|X86_CR4_PVI\|X86_CR4_VME)))
2104	{
2105	Log(("emInterpretMovCRx: CR4: %#RX64->%#RX64 => R3\n", oldval, val));
2106	VM_FF_SET(pVM, VM_FF_TO_R3);
2107	}
2108	# endif
2109	return PGMChangeMode(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR4(pVM), CPUMGetGuestEFER(pVM));
2110
2111	case USE_REG_CR8:
2112	return PDMApicSetTPR(pVM, val);
2113
2114	default:
2115	AssertFailed();
2116	case USE_REG_CR1: /* illegal op */
2117	break;
2118	}
2119	return VERR_EM_INTERPRETER;
2120	}
2121
2122	/**
2123	* Interpret CRx write
2124	*
2125	* @returns VBox status code.
2126	* @param pVM The VM handle.
2127	* @param pRegFrame The register frame.
2128	* @param DestRegCRx CRx register index (USE_REG_CR*)
2129	* @param SrcRegGen General purpose register index (USE_REG_E**))
2130	*
2131	*/
2132	VMMDECL(int) EMInterpretCRxWrite(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint32_t SrcRegGen)
2133	{
2134	uint64_t val;
2135	int rc;
2136
2137	if (CPUMIsGuestIn64BitCode(pVM, pRegFrame))
2138	{
2139	rc = DISFetchReg64(pRegFrame, SrcRegGen, &val);
2140	}
2141	else
2142	{
2143	uint32_t val32;
2144	rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
2145	val = val32;
2146	}
2147
2148	if (RT_SUCCESS(rc))
2149	return EMUpdateCRx(pVM, pRegFrame, DestRegCrx, val);
2150
2151	return VERR_EM_INTERPRETER;
2152	}
2153
2154	/**
2155	* Interpret LMSW
2156	*
2157	* @returns VBox status code.
2158	* @param pVM The VM handle.
2159	* @param pRegFrame The register frame.
2160	* @param u16Data LMSW source data.
2161	*
2162	*/
2163	VMMDECL(int) EMInterpretLMSW(PVM pVM, PCPUMCTXCORE pRegFrame, uint16_t u16Data)
2164	{
2165	uint64_t OldCr0 = CPUMGetGuestCR0(pVM);
2166
2167	/* Only PE, MP, EM and TS can be changed; note that PE can't be cleared by this instruction. */
2168	uint64_t NewCr0 = ( OldCr0 & ~( X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
2169	\| (u16Data & (X86_CR0_PE \| X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS));
2170
2171	return EMUpdateCRx(pVM, pRegFrame, USE_REG_CR0, NewCr0);
2172	}
2173
2174	/**
2175	* LMSW Emulation.
2176	*/
2177	static int emInterpretLmsw(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2178	{
2179	OP_PARAMVAL param1;
2180	uint32_t val;
2181
2182	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
2183	if(RT_FAILURE(rc))
2184	return VERR_EM_INTERPRETER;
2185
2186	switch(param1.type)
2187	{
2188	case PARMTYPE_IMMEDIATE:
2189	case PARMTYPE_ADDRESS:
2190	if(!(param1.flags & PARAM_VAL16))
2191	return VERR_EM_INTERPRETER;
2192	val = param1.val.val32;
2193	break;
2194
2195	default:
2196	return VERR_EM_INTERPRETER;
2197	}
2198
2199	LogFlow(("emInterpretLmsw %x\n", val));
2200	return EMInterpretLMSW(pVM, pRegFrame, val);
2201	}
2202
2203	/**
2204	* MOV CRx
2205	*/
2206	static int emInterpretMovCRx(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2207	{
2208	if ((pCpu->param1.flags == USE_REG_GEN32 \|\| pCpu->param1.flags == USE_REG_GEN64) && pCpu->param2.flags == USE_REG_CR)
2209	return EMInterpretCRxRead(pVM, pRegFrame, pCpu->param1.base.reg_gen, pCpu->param2.base.reg_ctrl);
2210
2211	if (pCpu->param1.flags == USE_REG_CR && (pCpu->param2.flags == USE_REG_GEN32 \|\| pCpu->param2.flags == USE_REG_GEN64))
2212	return EMInterpretCRxWrite(pVM, pRegFrame, pCpu->param1.base.reg_ctrl, pCpu->param2.base.reg_gen);
2213
2214	AssertMsgFailedReturn(("Unexpected control register move\n"), VERR_EM_INTERPRETER);
2215	return VERR_EM_INTERPRETER;
2216	}
2217
2218
2219	/**
2220	* Interpret DRx write
2221	*
2222	* @returns VBox status code.
2223	* @param pVM The VM handle.
2224	* @param pRegFrame The register frame.
2225	* @param DestRegDRx DRx register index (USE_REG_DR*)
2226	* @param SrcRegGen General purpose register index (USE_REG_E**))
2227	*
2228	*/
2229	VMMDECL(int) EMInterpretDRxWrite(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen)
2230	{
2231	uint64_t val;
2232	int rc;
2233
2234	if (CPUMIsGuestIn64BitCode(pVM, pRegFrame))
2235	{
2236	rc = DISFetchReg64(pRegFrame, SrcRegGen, &val);
2237	}
2238	else
2239	{
2240	uint32_t val32;
2241	rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
2242	val = val32;
2243	}
2244
2245	if (RT_SUCCESS(rc))
2246	{
2247	/** @todo we don't fail if illegal bits are set/cleared for e.g. dr7 */
2248	rc = CPUMSetGuestDRx(pVM, DestRegDrx, val);
2249	if (RT_SUCCESS(rc))
2250	return rc;
2251	AssertMsgFailed(("CPUMSetGuestDRx %d failed\n", DestRegDrx));
2252	}
2253	return VERR_EM_INTERPRETER;
2254	}
2255
2256
2257	/**
2258	* Interpret DRx read
2259	*
2260	* @returns VBox status code.
2261	* @param pVM The VM handle.
2262	* @param pRegFrame The register frame.
2263	* @param DestRegGen General purpose register index (USE_REG_E**))
2264	* @param SrcRegDRx DRx register index (USE_REG_DR*)
2265	*
2266	*/
2267	VMMDECL(int) EMInterpretDRxRead(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx)
2268	{
2269	uint64_t val64;
2270
2271	int rc = CPUMGetGuestDRx(pVM, SrcRegDrx, &val64);
2272	AssertMsgRCReturn(rc, ("CPUMGetGuestDRx %d failed\n", SrcRegDrx), VERR_EM_INTERPRETER);
2273	if (CPUMIsGuestIn64BitCode(pVM, pRegFrame))
2274	{
2275	rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
2276	}
2277	else
2278	rc = DISWriteReg32(pRegFrame, DestRegGen, (uint32_t)val64);
2279
2280	if (RT_SUCCESS(rc))
2281	return VINF_SUCCESS;
2282
2283	return VERR_EM_INTERPRETER;
2284	}
2285
2286
2287	/**
2288	* MOV DRx
2289	*/
2290	static int emInterpretMovDRx(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2291	{
2292	int rc = VERR_EM_INTERPRETER;
2293
2294	if((pCpu->param1.flags == USE_REG_GEN32 \|\| pCpu->param1.flags == USE_REG_GEN64) && pCpu->param2.flags == USE_REG_DBG)
2295	{
2296	rc = EMInterpretDRxRead(pVM, pRegFrame, pCpu->param1.base.reg_gen, pCpu->param2.base.reg_dbg);
2297	}
2298	else
2299	if(pCpu->param1.flags == USE_REG_DBG && (pCpu->param2.flags == USE_REG_GEN32 \|\| pCpu->param2.flags == USE_REG_GEN64))
2300	{
2301	rc = EMInterpretDRxWrite(pVM, pRegFrame, pCpu->param1.base.reg_dbg, pCpu->param2.base.reg_gen);
2302	}
2303	else
2304	AssertMsgFailed(("Unexpected debug register move\n"));
2305
2306	return rc;
2307	}
2308
2309
2310	/**
2311	* LLDT Emulation.
2312	*/
2313	static int emInterpretLLdt(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2314	{
2315	OP_PARAMVAL param1;
2316	RTSEL sel;
2317
2318	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
2319	if(RT_FAILURE(rc))
2320	return VERR_EM_INTERPRETER;
2321
2322	switch(param1.type)
2323	{
2324	case PARMTYPE_ADDRESS:
2325	return VERR_EM_INTERPRETER; //feeling lazy right now
2326
2327	case PARMTYPE_IMMEDIATE:
2328	if(!(param1.flags & PARAM_VAL16))
2329	return VERR_EM_INTERPRETER;
2330	sel = (RTSEL)param1.val.val16;
2331	break;
2332
2333	default:
2334	return VERR_EM_INTERPRETER;
2335	}
2336
2337	if (sel == 0)
2338	{
2339	if (CPUMGetHyperLDTR(pVM) == 0)
2340	{
2341	// this simple case is most frequent in Windows 2000 (31k - boot & shutdown)
2342	return VINF_SUCCESS;
2343	}
2344	}
2345	//still feeling lazy
2346	return VERR_EM_INTERPRETER;
2347	}
2348
2349	#ifdef IN_RING0
2350	/**
2351	* LIDT/LGDT Emulation.
2352	*/
2353	static int emInterpretLIGdt(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2354	{
2355	OP_PARAMVAL param1;
2356	RTGCPTR pParam1;
2357	X86XDTR32 dtr32;
2358
2359	Log(("Emulate %s at %RGv\n", emGetMnemonic(pCpu), (RTGCPTR)pRegFrame->rip));
2360
2361	/* Only for the VT-x real-mode emulation case. */
2362	if (!CPUMIsGuestInRealMode(pVM))
2363	return VERR_EM_INTERPRETER;
2364
2365	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
2366	if(RT_FAILURE(rc))
2367	return VERR_EM_INTERPRETER;
2368
2369	switch(param1.type)
2370	{
2371	case PARMTYPE_ADDRESS:
2372	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, param1.val.val16);
2373	break;
2374
2375	default:
2376	return VERR_EM_INTERPRETER;
2377	}
2378
2379	rc = emRamRead(pVM, &dtr32, pParam1, sizeof(dtr32));
2380	AssertRCReturn(rc, VERR_EM_INTERPRETER);
2381
2382	if (!(pCpu->prefix & PREFIX_OPSIZE))
2383	dtr32.uAddr &= 0xffffff; /* 16 bits operand size */
2384
2385	if (pCpu->pCurInstr->opcode == OP_LIDT)
2386	CPUMSetGuestIDTR(pVM, dtr32.uAddr, dtr32.cb);
2387	else
2388	CPUMSetGuestGDTR(pVM, dtr32.uAddr, dtr32.cb);
2389
2390	return VINF_SUCCESS;
2391	}
2392	#endif
2393
2394
2395	#ifdef IN_RC
2396	/**
2397	* STI Emulation.
2398	*
2399	* @remark the instruction following sti is guaranteed to be executed before any interrupts are dispatched
2400	*/
2401	static int emInterpretSti(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2402	{
2403	PPATMGCSTATE pGCState = PATMQueryGCState(pVM);
2404
2405	if(!pGCState)
2406	{
2407	Assert(pGCState);
2408	return VERR_EM_INTERPRETER;
2409	}
2410	pGCState->uVMFlags \|= X86_EFL_IF;
2411
2412	Assert(pRegFrame->eflags.u32 & X86_EFL_IF);
2413	Assert(pvFault == SELMToFlat(pVM, DIS_SELREG_CS, pRegFrame, (RTGCPTR)pRegFrame->rip));
2414
2415	pVM->em.s.GCPtrInhibitInterrupts = pRegFrame->eip + pCpu->opsize;
2416	VM_FF_SET(pVM, VM_FF_INHIBIT_INTERRUPTS);
2417
2418	return VINF_SUCCESS;
2419	}
2420	#endif /* IN_RC */
2421
2422
2423	/**
2424	* HLT Emulation.
2425	*/
2426	static int emInterpretHlt(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2427	{
2428	return VINF_EM_HALT;
2429	}
2430
2431
2432	/**
2433	* Interpret RDTSC
2434	*
2435	* @returns VBox status code.
2436	* @param pVM The VM handle.
2437	* @param pRegFrame The register frame.
2438	*
2439	*/
2440	VMMDECL(int) EMInterpretRdtsc(PVM pVM, PCPUMCTXCORE pRegFrame)
2441	{
2442	unsigned uCR4 = CPUMGetGuestCR4(pVM);
2443
2444	if (uCR4 & X86_CR4_TSD)
2445	return VERR_EM_INTERPRETER; /* genuine #GP */
2446
2447	uint64_t uTicks = TMCpuTickGet(pVM);
2448
2449	/* Same behaviour in 32 & 64 bits mode */
2450	pRegFrame->rax = (uint32_t)uTicks;
2451	pRegFrame->rdx = (uTicks >> 32ULL);
2452
2453	return VINF_SUCCESS;
2454	}
2455
2456	VMMDECL(int) EMInterpretRdtscp(PVM pVM, PCPUMCTX pCtx)
2457	{
2458	unsigned uCR4 = CPUMGetGuestCR4(pVM);
2459
2460	if (!CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
2461	{
2462	AssertFailed();
2463	return VERR_EM_INTERPRETER; /* genuine #UD */
2464	}
2465
2466	if (uCR4 & X86_CR4_TSD)
2467	return VERR_EM_INTERPRETER; /* genuine #GP */
2468
2469	uint64_t uTicks = TMCpuTickGet(pVM);
2470
2471	/* Same behaviour in 32 & 64 bits mode */
2472	pCtx->rax = (uint32_t)uTicks;
2473	pCtx->rdx = (uTicks >> 32ULL);
2474	/* Low dword of the TSC_AUX msr only. */
2475	pCtx->rcx = (uint32_t)CPUMGetGuestMsr(pVM, MSR_K8_TSC_AUX);
2476
2477	return VINF_SUCCESS;
2478	}
2479
2480	/**
2481	* RDTSC Emulation.
2482	*/
2483	static int emInterpretRdtsc(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2484	{
2485	return EMInterpretRdtsc(pVM, pRegFrame);
2486	}
2487
2488
2489	/**
2490	* MONITOR Emulation.
2491	*/
2492	static int emInterpretMonitor(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2493	{
2494	uint32_t u32Dummy, u32ExtFeatures, cpl;
2495
2496	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
2497	if (pRegFrame->ecx != 0)
2498	return VERR_EM_INTERPRETER; /* illegal value. */
2499
2500	/* Get the current privilege level. */
2501	cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2502	if (cpl != 0)
2503	return VERR_EM_INTERPRETER; /* supervisor only */
2504
2505	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
2506	if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
2507	return VERR_EM_INTERPRETER; /* not supported */
2508
2509	return VINF_SUCCESS;
2510	}
2511
2512
2513	/**
2514	* MWAIT Emulation.
2515	*/
2516	static int emInterpretMWait(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2517	{
2518	uint32_t u32Dummy, u32ExtFeatures, cpl;
2519
2520	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
2521	if (pRegFrame->ecx != 0)
2522	return VERR_EM_INTERPRETER; /* illegal value. */
2523
2524	/* Get the current privilege level. */
2525	cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2526	if (cpl != 0)
2527	return VERR_EM_INTERPRETER; /* supervisor only */
2528
2529	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
2530	if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
2531	return VERR_EM_INTERPRETER; /* not supported */
2532
2533	/** @todo not completely correct */
2534	return VINF_EM_HALT;
2535	}
2536
2537
2538	#ifdef LOG_ENABLED
2539	static const char *emMSRtoString(uint32_t uMsr)
2540	{
2541	switch (uMsr)
2542	{
2543	case MSR_IA32_APICBASE:
2544	return "MSR_IA32_APICBASE";
2545	case MSR_IA32_CR_PAT:
2546	return "MSR_IA32_CR_PAT";
2547	case MSR_IA32_SYSENTER_CS:
2548	return "MSR_IA32_SYSENTER_CS";
2549	case MSR_IA32_SYSENTER_EIP:
2550	return "MSR_IA32_SYSENTER_EIP";
2551	case MSR_IA32_SYSENTER_ESP:
2552	return "MSR_IA32_SYSENTER_ESP";
2553	case MSR_K6_EFER:
2554	return "MSR_K6_EFER";
2555	case MSR_K8_SF_MASK:
2556	return "MSR_K8_SF_MASK";
2557	case MSR_K6_STAR:
2558	return "MSR_K6_STAR";
2559	case MSR_K8_LSTAR:
2560	return "MSR_K8_LSTAR";
2561	case MSR_K8_CSTAR:
2562	return "MSR_K8_CSTAR";
2563	case MSR_K8_FS_BASE:
2564	return "MSR_K8_FS_BASE";
2565	case MSR_K8_GS_BASE:
2566	return "MSR_K8_GS_BASE";
2567	case MSR_K8_KERNEL_GS_BASE:
2568	return "MSR_K8_KERNEL_GS_BASE";
2569	case MSR_K8_TSC_AUX:
2570	return "MSR_K8_TSC_AUX";
2571	case MSR_IA32_BIOS_SIGN_ID:
2572	return "Unsupported MSR_IA32_BIOS_SIGN_ID";
2573	case MSR_IA32_PLATFORM_ID:
2574	return "Unsupported MSR_IA32_PLATFORM_ID";
2575	case MSR_IA32_BIOS_UPDT_TRIG:
2576	return "Unsupported MSR_IA32_BIOS_UPDT_TRIG";
2577	case MSR_IA32_TSC:
2578	return "Unsupported MSR_IA32_TSC";
2579	case MSR_IA32_MTRR_CAP:
2580	return "Unsupported MSR_IA32_MTRR_CAP";
2581	case MSR_IA32_MCP_CAP:
2582	return "Unsupported MSR_IA32_MCP_CAP";
2583	case MSR_IA32_MCP_STATUS:
2584	return "Unsupported MSR_IA32_MCP_STATUS";
2585	case MSR_IA32_MCP_CTRL:
2586	return "Unsupported MSR_IA32_MCP_CTRL";
2587	case MSR_IA32_MTRR_DEF_TYPE:
2588	return "Unsupported MSR_IA32_MTRR_DEF_TYPE";
2589	case MSR_K7_EVNTSEL0:
2590	return "Unsupported MSR_K7_EVNTSEL0";
2591	case MSR_K7_EVNTSEL1:
2592	return "Unsupported MSR_K7_EVNTSEL1";
2593	case MSR_K7_EVNTSEL2:
2594	return "Unsupported MSR_K7_EVNTSEL2";
2595	case MSR_K7_EVNTSEL3:
2596	return "Unsupported MSR_K7_EVNTSEL3";
2597	case MSR_IA32_MC0_CTL:
2598	return "Unsupported MSR_IA32_MC0_CTL";
2599	case MSR_IA32_MC0_STATUS:
2600	return "Unsupported MSR_IA32_MC0_STATUS";
2601	}
2602	return "Unknown MSR";
2603	}
2604	#endif /* LOG_ENABLED */
2605
2606
2607	/**
2608	* Interpret RDMSR
2609	*
2610	* @returns VBox status code.
2611	* @param pVM The VM handle.
2612	* @param pRegFrame The register frame.
2613	*
2614	*/
2615	VMMDECL(int) EMInterpretRdmsr(PVM pVM, PCPUMCTXCORE pRegFrame)
2616	{
2617	uint32_t u32Dummy, u32Features, cpl;
2618	uint64_t val;
2619	CPUMCTX *pCtx;
2620	int rc = VINF_SUCCESS;
2621
2622	/** @todo According to the Intel manuals, there's a REX version of RDMSR that is slightly different.
2623	* That version clears the high dwords of both RDX & RAX */
2624	pCtx = CPUMQueryGuestCtxPtr(pVM);
2625
2626	/* Get the current privilege level. */
2627	cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2628	if (cpl != 0)
2629	return VERR_EM_INTERPRETER; /* supervisor only */
2630
2631	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2632	if (!(u32Features & X86_CPUID_FEATURE_EDX_MSR))
2633	return VERR_EM_INTERPRETER; /* not supported */
2634
2635	switch (pRegFrame->ecx)
2636	{
2637	case MSR_IA32_APICBASE:
2638	rc = PDMApicGetBase(pVM, &val);
2639	AssertRC(rc);
2640	break;
2641
2642	case MSR_IA32_CR_PAT:
2643	val = pCtx->msrPAT;
2644	break;
2645
2646	case MSR_IA32_SYSENTER_CS:
2647	val = pCtx->SysEnter.cs;
2648	break;
2649
2650	case MSR_IA32_SYSENTER_EIP:
2651	val = pCtx->SysEnter.eip;
2652	break;
2653
2654	case MSR_IA32_SYSENTER_ESP:
2655	val = pCtx->SysEnter.esp;
2656	break;
2657
2658	case MSR_K6_EFER:
2659	val = pCtx->msrEFER;
2660	break;
2661
2662	case MSR_K8_SF_MASK:
2663	val = pCtx->msrSFMASK;
2664	break;
2665
2666	case MSR_K6_STAR:
2667	val = pCtx->msrSTAR;
2668	break;
2669
2670	case MSR_K8_LSTAR:
2671	val = pCtx->msrLSTAR;
2672	break;
2673
2674	case MSR_K8_CSTAR:
2675	val = pCtx->msrCSTAR;
2676	break;
2677
2678	case MSR_K8_FS_BASE:
2679	val = pCtx->fsHid.u64Base;
2680	break;
2681
2682	case MSR_K8_GS_BASE:
2683	val = pCtx->gsHid.u64Base;
2684	break;
2685
2686	case MSR_K8_KERNEL_GS_BASE:
2687	val = pCtx->msrKERNELGSBASE;
2688	break;
2689
2690	case MSR_K8_TSC_AUX:
2691	val = CPUMGetGuestMsr(pVM, MSR_K8_TSC_AUX);
2692	break;
2693
2694	#if 0 /def IN_RING0 /
2695	case MSR_IA32_PLATFORM_ID:
2696	case MSR_IA32_BIOS_SIGN_ID:
2697	if (CPUMGetCPUVendor(pVM) == CPUMCPUVENDOR_INTEL)
2698	{
2699	/* Available since the P6 family. VT-x implies that this feature is present. */
2700	if (pRegFrame->ecx == MSR_IA32_PLATFORM_ID)
2701	val = ASMRdMsr(MSR_IA32_PLATFORM_ID);
2702	else
2703	if (pRegFrame->ecx == MSR_IA32_BIOS_SIGN_ID)
2704	val = ASMRdMsr(MSR_IA32_BIOS_SIGN_ID);
2705	break;
2706	}
2707	/* no break */
2708	#endif
2709	default:
2710	/* In X2APIC specification this range is reserved for APIC control. */
2711	if ((pRegFrame->ecx >= MSR_IA32_APIC_START) && (pRegFrame->ecx < MSR_IA32_APIC_END))
2712	rc = PDMApicReadMSR(pVM, VMMGetCpuId(pVM), pRegFrame->ecx, &val);
2713	else
2714	/* We should actually trigger a #GP here, but don't as that might cause more trouble. */
2715	val = 0;
2716	break;
2717	}
2718	LogFlow(("EMInterpretRdmsr %s (%x) -> val=%RX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx, val));
2719	if (rc == VINF_SUCCESS)
2720	{
2721	pRegFrame->rax = (uint32_t) val;
2722	pRegFrame->rdx = (uint32_t) (val >> 32ULL);
2723	}
2724	return rc;
2725	}
2726
2727
2728	/**
2729	* RDMSR Emulation.
2730	*/
2731	static int emInterpretRdmsr(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2732	{
2733	/* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
2734	Assert(!(pCpu->prefix & PREFIX_REX));
2735	return EMInterpretRdmsr(pVM, pRegFrame);
2736	}
2737
2738
2739	/**
2740	* Interpret WRMSR
2741	*
2742	* @returns VBox status code.
2743	* @param pVM The VM handle.
2744	* @param pRegFrame The register frame.
2745	*/
2746	VMMDECL(int) EMInterpretWrmsr(PVM pVM, PCPUMCTXCORE pRegFrame)
2747	{
2748	uint32_t u32Dummy, u32Features, cpl;
2749	uint64_t val;
2750	CPUMCTX *pCtx;
2751
2752	/* Note: works the same in 32 and 64 bits modes. */
2753	pCtx = CPUMQueryGuestCtxPtr(pVM);
2754
2755	/* Get the current privilege level. */
2756	cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2757	if (cpl != 0)
2758	return VERR_EM_INTERPRETER; /* supervisor only */
2759
2760	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2761	if (!(u32Features & X86_CPUID_FEATURE_EDX_MSR))
2762	return VERR_EM_INTERPRETER; /* not supported */
2763
2764	val = RT_MAKE_U64(pRegFrame->eax, pRegFrame->edx);
2765	LogFlow(("EMInterpretWrmsr %s (%x) val=%RX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx, val));
2766	switch (pRegFrame->ecx)
2767	{
2768	case MSR_IA32_APICBASE:
2769	{
2770	int rc = PDMApicSetBase(pVM, val);
2771	AssertRC(rc);
2772	break;
2773	}
2774
2775	case MSR_IA32_CR_PAT:
2776	pCtx->msrPAT = val;
2777	break;
2778
2779	case MSR_IA32_SYSENTER_CS:
2780	pCtx->SysEnter.cs = val & 0xffff; /* 16 bits selector */
2781	break;
2782
2783	case MSR_IA32_SYSENTER_EIP:
2784	pCtx->SysEnter.eip = val;
2785	break;
2786
2787	case MSR_IA32_SYSENTER_ESP:
2788	pCtx->SysEnter.esp = val;
2789	break;
2790
2791	case MSR_K6_EFER:
2792	{
2793	uint64_t uMask = 0;
2794	uint64_t oldval = pCtx->msrEFER;
2795
2796	/* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
2797	CPUMGetGuestCpuId(pVM, 0x80000001, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2798	if (u32Features & X86_CPUID_AMD_FEATURE_EDX_NX)
2799	uMask \|= MSR_K6_EFER_NXE;
2800	if (u32Features & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE)
2801	uMask \|= MSR_K6_EFER_LME;
2802	if (u32Features & X86_CPUID_AMD_FEATURE_EDX_SEP)
2803	uMask \|= MSR_K6_EFER_SCE;
2804	if (u32Features & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
2805	uMask \|= MSR_K6_EFER_FFXSR;
2806
2807	/* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
2808	if ( ((pCtx->msrEFER & MSR_K6_EFER_LME) != (val & uMask & MSR_K6_EFER_LME))
2809	&& (pCtx->cr0 & X86_CR0_PG))
2810	{
2811	AssertMsgFailed(("Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
2812	return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
2813	}
2814
2815	/* There are a few more: e.g. MSR_K6_EFER_LMSLE */
2816	AssertMsg(!(val & ~(MSR_K6_EFER_NXE\|MSR_K6_EFER_LME\|MSR_K6_EFER_LMA /* ignored anyway */ \|MSR_K6_EFER_SCE\|MSR_K6_EFER_FFXSR)), ("Unexpected value %RX64\n", val));
2817	pCtx->msrEFER = (pCtx->msrEFER & ~uMask) \| (val & uMask);
2818
2819	/* AMD64 Achitecture Programmer's Manual: 15.15 TLB Control; flush the TLB if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
2820	if ((oldval & (MSR_K6_EFER_NXE\|MSR_K6_EFER_LME\|MSR_K6_EFER_LMA)) != (pCtx->msrEFER & (MSR_K6_EFER_NXE\|MSR_K6_EFER_LME\|MSR_K6_EFER_LMA)))
2821	HWACCMFlushTLB(pVM);
2822
2823	break;
2824	}
2825
2826	case MSR_K8_SF_MASK:
2827	pCtx->msrSFMASK = val;
2828	break;
2829
2830	case MSR_K6_STAR:
2831	pCtx->msrSTAR = val;
2832	break;
2833
2834	case MSR_K8_LSTAR:
2835	pCtx->msrLSTAR = val;
2836	break;
2837
2838	case MSR_K8_CSTAR:
2839	pCtx->msrCSTAR = val;
2840	break;
2841
2842	case MSR_K8_FS_BASE:
2843	pCtx->fsHid.u64Base = val;
2844	break;
2845
2846	case MSR_K8_GS_BASE:
2847	pCtx->gsHid.u64Base = val;
2848	break;
2849
2850	case MSR_K8_KERNEL_GS_BASE:
2851	pCtx->msrKERNELGSBASE = val;
2852	break;
2853
2854	case MSR_K8_TSC_AUX:
2855	CPUMSetGuestMsr(pVM, MSR_K8_TSC_AUX, val);
2856	break;
2857
2858	default:
2859	/* In X2APIC specification this range is reserved for APIC control. */
2860	if ((pRegFrame->ecx >= MSR_IA32_APIC_START) && (pRegFrame->ecx < MSR_IA32_APIC_END))
2861	return PDMApicWriteMSR(pVM, VMMGetCpuId(pVM), pRegFrame->ecx, val);
2862
2863	/* We should actually trigger a #GP here, but don't as that might cause more trouble. */
2864	break;
2865	}
2866	return VINF_SUCCESS;
2867	}
2868
2869
2870	/**
2871	* WRMSR Emulation.
2872	*/
2873	static int emInterpretWrmsr(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2874	{
2875	return EMInterpretWrmsr(pVM, pRegFrame);
2876	}
2877
2878
2879	/**
2880	* Internal worker.
2881	* @copydoc EMInterpretInstructionCPU
2882	*/
2883	DECLINLINE(int) emInterpretInstructionCPU(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2884	{
2885	Assert(pcbSize);
2886	*pcbSize = 0;
2887
2888	/*
2889	* Only supervisor guest code!!
2890	* And no complicated prefixes.
2891	*/
2892	/* Get the current privilege level. */
2893	uint32_t cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2894	if ( cpl != 0
2895	&& pCpu->pCurInstr->opcode != OP_RDTSC) /* rdtsc requires emulation in ring 3 as well */
2896	{
2897	Log(("WARNING: refusing instruction emulation for user-mode code!!\n"));
2898	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedUserMode));
2899	return VERR_EM_INTERPRETER;
2900	}
2901
2902	#ifdef IN_RC
2903	if ( (pCpu->prefix & (PREFIX_REPNE \| PREFIX_REP))
2904	\|\| ( (pCpu->prefix & PREFIX_LOCK)
2905	&& pCpu->pCurInstr->opcode != OP_CMPXCHG
2906	&& pCpu->pCurInstr->opcode != OP_CMPXCHG8B
2907	&& pCpu->pCurInstr->opcode != OP_XADD
2908	&& pCpu->pCurInstr->opcode != OP_OR
2909	&& pCpu->pCurInstr->opcode != OP_BTR
2910	)
2911	)
2912	#else
2913	if ( (pCpu->prefix & PREFIX_REPNE)
2914	\|\| ( (pCpu->prefix & PREFIX_REP)
2915	&& pCpu->pCurInstr->opcode != OP_STOSWD
2916	)
2917	\|\| ( (pCpu->prefix & PREFIX_LOCK)
2918	&& pCpu->pCurInstr->opcode != OP_OR
2919	&& pCpu->pCurInstr->opcode != OP_BTR
2920	&& pCpu->pCurInstr->opcode != OP_CMPXCHG
2921	&& pCpu->pCurInstr->opcode != OP_CMPXCHG8B
2922	)
2923	)
2924	#endif
2925	{
2926	//Log(("EMInterpretInstruction: wrong prefix!!\n"));
2927	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedPrefix));
2928	return VERR_EM_INTERPRETER;
2929	}
2930
2931	#if HC_ARCH_BITS == 32
2932	if (CPUMIsGuestIn64BitCode(pVM, pRegFrame))
2933	{
2934	/* Unable to emulate in 32 bits mode.
2935	* Whitelisted instructions are safe.
2936	*/
2937	if ( pCpu->param1.size > 4
2938	&& pCpu->pCurInstr->opcode != OP_STOSWD
2939	&& pCpu->pCurInstr->opcode != OP_MOV
2940	&& pCpu->pCurInstr->opcode != OP_CMPXCHG8B)
2941	return VERR_EM_INTERPRETER;
2942	}
2943	#endif
2944
2945	int rc;
2946	#if (defined(VBOX_STRICT) \|\| defined(LOG_ENABLED))
2947	LogFlow(("emInterpretInstructionCPU %s\n", emGetMnemonic(pCpu)));
2948	#endif
2949	switch (pCpu->pCurInstr->opcode)
2950	{
2951	# define INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
2952	case opcode:\
2953	if (pCpu->prefix & PREFIX_LOCK) \
2954	rc = emInterpretLock##InstrFn(pVM, pCpu, pRegFrame, pvFault, pcbSize, pfnEmulateLock); \
2955	else \
2956	rc = emInterpret##InstrFn(pVM, pCpu, pRegFrame, pvFault, pcbSize, pfnEmulate); \
2957	if (RT_SUCCESS(rc)) \
2958	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
2959	else \
2960	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
2961	return rc
2962	#define INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate) \
2963	case opcode:\
2964	rc = emInterpret##InstrFn(pVM, pCpu, pRegFrame, pvFault, pcbSize, pfnEmulate); \
2965	if (RT_SUCCESS(rc)) \
2966	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
2967	else \
2968	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
2969	return rc
2970
2971	#define INTERPRET_CASE_EX_PARAM2(opcode, Instr, InstrFn, pfnEmulate) \
2972	INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate)
2973	#define INTERPRET_CASE_EX_LOCK_PARAM2(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
2974	INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock)
2975
2976	#define INTERPRET_CASE(opcode, Instr) \
2977	case opcode:\
2978	rc = emInterpret##Instr(pVM, pCpu, pRegFrame, pvFault, pcbSize); \
2979	if (RT_SUCCESS(rc)) \
2980	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
2981	else \
2982	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
2983	return rc
2984
2985	#define INTERPRET_CASE_EX_DUAL_PARAM2(opcode, Instr, InstrFn) \
2986	case opcode:\
2987	rc = emInterpret##InstrFn(pVM, pCpu, pRegFrame, pvFault, pcbSize); \
2988	if (RT_SUCCESS(rc)) \
2989	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
2990	else \
2991	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
2992	return rc
2993
2994	#define INTERPRET_STAT_CASE(opcode, Instr) \
2995	case opcode: STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); return VERR_EM_INTERPRETER;
2996
2997	INTERPRET_CASE(OP_XCHG,Xchg);
2998	INTERPRET_CASE_EX_PARAM2(OP_DEC,Dec, IncDec, EMEmulateDec);
2999	INTERPRET_CASE_EX_PARAM2(OP_INC,Inc, IncDec, EMEmulateInc);
3000	INTERPRET_CASE(OP_POP,Pop);
3001	INTERPRET_CASE_EX_LOCK_PARAM3(OP_OR, Or, OrXorAnd, EMEmulateOr, EMEmulateLockOr);
3002	INTERPRET_CASE_EX_PARAM3(OP_XOR,Xor, OrXorAnd, EMEmulateXor);
3003	INTERPRET_CASE_EX_PARAM3(OP_AND,And, OrXorAnd, EMEmulateAnd);
3004	INTERPRET_CASE(OP_MOV,Mov);
3005	#ifndef IN_RC
3006	INTERPRET_CASE(OP_STOSWD,StosWD);
3007	#endif
3008	INTERPRET_CASE(OP_INVLPG,InvlPg);
3009	INTERPRET_CASE(OP_CPUID,CpuId);
3010	INTERPRET_CASE(OP_MOV_CR,MovCRx);
3011	INTERPRET_CASE(OP_MOV_DR,MovDRx);
3012	INTERPRET_CASE(OP_LLDT,LLdt);
3013	#ifdef IN_RING0
3014	INTERPRET_CASE_EX_DUAL_PARAM2(OP_LIDT, LIdt, LIGdt);
3015	INTERPRET_CASE_EX_DUAL_PARAM2(OP_LGDT, LGdt, LIGdt);
3016	#endif
3017	INTERPRET_CASE(OP_LMSW,Lmsw);
3018	INTERPRET_CASE(OP_CLTS,Clts);
3019	INTERPRET_CASE(OP_MONITOR, Monitor);
3020	INTERPRET_CASE(OP_MWAIT, MWait);
3021	INTERPRET_CASE(OP_RDMSR, Rdmsr);
3022	INTERPRET_CASE(OP_WRMSR, Wrmsr);
3023	INTERPRET_CASE_EX_PARAM3(OP_ADD,Add, AddSub, EMEmulateAdd);
3024	INTERPRET_CASE_EX_PARAM3(OP_SUB,Sub, AddSub, EMEmulateSub);
3025	INTERPRET_CASE(OP_ADC,Adc);
3026	INTERPRET_CASE_EX_LOCK_PARAM2(OP_BTR,Btr, BitTest, EMEmulateBtr, EMEmulateLockBtr);
3027	INTERPRET_CASE_EX_PARAM2(OP_BTS,Bts, BitTest, EMEmulateBts);
3028	INTERPRET_CASE_EX_PARAM2(OP_BTC,Btc, BitTest, EMEmulateBtc);
3029	INTERPRET_CASE(OP_RDTSC,Rdtsc);
3030	INTERPRET_CASE(OP_CMPXCHG, CmpXchg);
3031	#ifdef IN_RC
3032	INTERPRET_CASE(OP_STI,Sti);
3033	INTERPRET_CASE(OP_XADD, XAdd);
3034	#endif
3035	INTERPRET_CASE(OP_CMPXCHG8B, CmpXchg8b);
3036	INTERPRET_CASE(OP_HLT,Hlt);
3037	INTERPRET_CASE(OP_IRET,Iret);
3038	INTERPRET_CASE(OP_WBINVD,WbInvd);
3039	#ifdef VBOX_WITH_STATISTICS
3040	#ifndef IN_RC
3041	INTERPRET_STAT_CASE(OP_XADD, XAdd);
3042	#endif
3043	INTERPRET_STAT_CASE(OP_MOVNTPS,MovNTPS);
3044	#endif
3045	default:
3046	Log3(("emInterpretInstructionCPU: opcode=%d\n", pCpu->pCurInstr->opcode));
3047	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedMisc));
3048	return VERR_EM_INTERPRETER;
3049	#undef INTERPRET_CASE_EX_PARAM2
3050	#undef INTERPRET_STAT_CASE
3051	#undef INTERPRET_CASE_EX
3052	#undef INTERPRET_CASE
3053	}
3054	AssertFailed();
3055	return VERR_INTERNAL_ERROR;
3056	}
3057
3058
3059	/**
3060	* Sets the PC for which interrupts should be inhibited.
3061	*
3062	* @param pVM The VM handle.
3063	* @param PC The PC.
3064	*/
3065	VMMDECL(void) EMSetInhibitInterruptsPC(PVM pVM, RTGCUINTPTR PC)
3066	{
3067	pVM->em.s.GCPtrInhibitInterrupts = PC;
3068	VM_FF_SET(pVM, VM_FF_INHIBIT_INTERRUPTS);
3069	}
3070
3071
3072	/**
3073	* Gets the PC for which interrupts should be inhibited.
3074	*
3075	* There are a few instructions which inhibits or delays interrupts
3076	* for the instruction following them. These instructions are:
3077	* - STI
3078	* - MOV SS, r/m16
3079	* - POP SS
3080	*
3081	* @returns The PC for which interrupts should be inhibited.
3082	* @param pVM VM handle.
3083	*
3084	*/
3085	VMMDECL(RTGCUINTPTR) EMGetInhibitInterruptsPC(PVM pVM)
3086	{
3087	return pVM->em.s.GCPtrInhibitInterrupts;
3088	}
3089

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source: vbox/trunk/src/VBox/VMM/VMMAll/EMAll.cpp@ 15184

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