EMAll.cpp@ 15420

Last change on this file since 15420 was 15420, checked in by vboxsync, 16 years ago
EMAll: ADD, ADC and SUB - the first is used a bit by windows.
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1	/* $Id: EMAll.cpp 15420 2008-12-13 07:21:55Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor(/Manager) - All contexts
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_EM
26	#include <VBox/em.h>
27	#include <VBox/mm.h>
28	#include <VBox/selm.h>
29	#include <VBox/patm.h>
30	#include <VBox/csam.h>
31	#include <VBox/pgm.h>
32	#include <VBox/iom.h>
33	#include <VBox/stam.h>
34	#include "EMInternal.h"
35	#include <VBox/vm.h>
36	#include <VBox/vmm.h>
37	#include <VBox/hwaccm.h>
38	#include <VBox/tm.h>
39	#include <VBox/pdmapi.h>
40
41	#include <VBox/param.h>
42	#include <VBox/err.h>
43	#include <VBox/dis.h>
44	#include <VBox/disopcode.h>
45	#include <VBox/log.h>
46	#include <iprt/assert.h>
47	#include <iprt/asm.h>
48	#include <iprt/string.h>
49
50
51	/*******************************************************************************
52	* Defined Constants And Macros *
53	*******************************************************************************/
54	/** @def EM_ASSERT_FAULT_RETURN
55	* Safety check.
56	*
57	* Could in theory misfire on a cross page boundary access...
58	*
59	* Currently disabled because the CSAM (+ PATM) patch monitoring occasionally
60	* turns up an alias page instead of the original faulting one and annoying the
61	* heck out of anyone running a debug build. See @bugref{2609} and @bugref{1931}.
62	*/
63	#if 0
64	# define EM_ASSERT_FAULT_RETURN(expr, rc) AssertReturn(expr, rc)
65	#else
66	# define EM_ASSERT_FAULT_RETURN(expr, rc) do { } while (0)
67	#endif
68
69
70	/*******************************************************************************
71	* Internal Functions *
72	*******************************************************************************/
73	DECLINLINE(int) emInterpretInstructionCPU(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize);
74
75
76
77	/**
78	* Get the current execution manager status.
79	*
80	* @returns Current status.
81	*/
82	VMMDECL(EMSTATE) EMGetState(PVM pVM)
83	{
84	return pVM->em.s.enmState;
85	}
86
87	#ifndef IN_RC
88
89	/**
90	* Read callback for disassembly function; supports reading bytes that cross a page boundary
91	*
92	* @returns VBox status code.
93	* @param pSrc GC source pointer
94	* @param pDest HC destination pointer
95	* @param cb Number of bytes to read
96	* @param dwUserdata Callback specific user data (pCpu)
97	*
98	*/
99	DECLCALLBACK(int) EMReadBytes(RTUINTPTR pSrc, uint8_t pDest, unsigned cb, void pvUserdata)
100	{
101	DISCPUSTATE pCpu = (DISCPUSTATE )pvUserdata;
102	PVM pVM = (PVM)pCpu->apvUserData[0];
103	# ifdef IN_RING0
104	int rc = PGMPhysSimpleReadGCPtr(pVM, pDest, pSrc, cb);
105	AssertMsgRC(rc, ("PGMPhysSimpleReadGCPtr failed for pSrc=%RGv cb=%x\n", pSrc, cb));
106	# else /* IN_RING3 */
107	if (!PATMIsPatchGCAddr(pVM, pSrc))
108	{
109	int rc = PGMPhysSimpleReadGCPtr(pVM, pDest, pSrc, cb);
110	AssertRC(rc);
111	}
112	else
113	{
114	for (uint32_t i = 0; i < cb; i++)
115	{
116	uint8_t opcode;
117	if (RT_SUCCESS(PATMR3QueryOpcode(pVM, (RTGCPTR)pSrc + i, &opcode)))
118	{
119	*(pDest+i) = opcode;
120	}
121	}
122	}
123	# endif /* IN_RING3 */
124	return VINF_SUCCESS;
125	}
126
127	DECLINLINE(int) emDisCoreOne(PVM pVM, DISCPUSTATE pCpu, RTGCUINTPTR InstrGC, uint32_t pOpsize)
128	{
129	return DISCoreOneEx(InstrGC, pCpu->mode, EMReadBytes, pVM, pCpu, pOpsize);
130	}
131
132	#else /* IN_RC */
133
134	DECLINLINE(int) emDisCoreOne(PVM pVM, DISCPUSTATE pCpu, RTGCUINTPTR InstrGC, uint32_t pOpsize)
135	{
136	return DISCoreOne(pCpu, InstrGC, pOpsize);
137	}
138
139	#endif /* IN_RC */
140
141
142	/**
143	* Disassembles one instruction.
144	*
145	* @param pVM The VM handle.
146	* @param pCtxCore The context core (used for both the mode and instruction).
147	* @param pCpu Where to return the parsed instruction info.
148	* @param pcbInstr Where to return the instruction size. (optional)
149	*/
150	VMMDECL(int) EMInterpretDisasOne(PVM pVM, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, unsigned *pcbInstr)
151	{
152	RTGCPTR GCPtrInstr;
153	int rc = SELMToFlatEx(pVM, DIS_SELREG_CS, pCtxCore, pCtxCore->rip, 0, &GCPtrInstr);
154	if (RT_FAILURE(rc))
155	{
156	Log(("EMInterpretDisasOne: Failed to convert %RTsel:%RGv (cpl=%d) - rc=%Rrc !!\n",
157	pCtxCore->cs, (RTGCPTR)pCtxCore->rip, pCtxCore->ss & X86_SEL_RPL, rc));
158	return rc;
159	}
160	return EMInterpretDisasOneEx(pVM, (RTGCUINTPTR)GCPtrInstr, pCtxCore, pCpu, pcbInstr);
161	}
162
163
164	/**
165	* Disassembles one instruction.
166	*
167	* This is used by internally by the interpreter and by trap/access handlers.
168	*
169	* @param pVM The VM handle.
170	* @param GCPtrInstr The flat address of the instruction.
171	* @param pCtxCore The context core (used to determine the cpu mode).
172	* @param pCpu Where to return the parsed instruction info.
173	* @param pcbInstr Where to return the instruction size. (optional)
174	*/
175	VMMDECL(int) EMInterpretDisasOneEx(PVM pVM, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, unsigned *pcbInstr)
176	{
177	int rc = DISCoreOneEx(GCPtrInstr, SELMGetCpuModeFromSelector(pVM, pCtxCore->eflags, pCtxCore->cs, (PCPUMSELREGHID)&pCtxCore->csHid),
178	#ifdef IN_RC
179	NULL, NULL,
180	#else
181	EMReadBytes, pVM,
182	#endif
183	pCpu, pcbInstr);
184	if (RT_SUCCESS(rc))
185	return VINF_SUCCESS;
186	AssertMsgFailed(("DISCoreOne failed to GCPtrInstr=%RGv rc=%Rrc\n", GCPtrInstr, rc));
187	return VERR_INTERNAL_ERROR;
188	}
189
190
191	/**
192	* Interprets the current instruction.
193	*
194	* @returns VBox status code.
195	* @retval VINF_* Scheduling instructions.
196	* @retval VERR_EM_INTERPRETER Something we can't cope with.
197	* @retval VERR_* Fatal errors.
198	*
199	* @param pVM The VM handle.
200	* @param pRegFrame The register frame.
201	* Updates the EIP if an instruction was executed successfully.
202	* @param pvFault The fault address (CR2).
203	* @param pcbSize Size of the write (if applicable).
204	*
205	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
206	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
207	* to worry about e.g. invalid modrm combinations (!)
208	*/
209	VMMDECL(int) EMInterpretInstruction(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
210	{
211	RTGCPTR pbCode;
212
213	LogFlow(("EMInterpretInstruction %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
214	int rc = SELMToFlatEx(pVM, DIS_SELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
215	if (RT_SUCCESS(rc))
216	{
217	uint32_t cbOp;
218	DISCPUSTATE Cpu;
219	Cpu.mode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
220	rc = emDisCoreOne(pVM, &Cpu, (RTGCUINTPTR)pbCode, &cbOp);
221	if (RT_SUCCESS(rc))
222	{
223	Assert(cbOp == Cpu.opsize);
224	rc = EMInterpretInstructionCPU(pVM, &Cpu, pRegFrame, pvFault, pcbSize);
225	if (RT_SUCCESS(rc))
226	{
227	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
228	}
229	return rc;
230	}
231	}
232	return VERR_EM_INTERPRETER;
233	}
234
235
236	/**
237	* Interprets the current instruction using the supplied DISCPUSTATE structure.
238	*
239	* EIP is NOT updated!
240	*
241	* @returns VBox status code.
242	* @retval VINF_* Scheduling instructions. When these are returned, it
243	* starts to get a bit tricky to know whether code was
244	* executed or not... We'll address this when it becomes a problem.
245	* @retval VERR_EM_INTERPRETER Something we can't cope with.
246	* @retval VERR_* Fatal errors.
247	*
248	* @param pVM The VM handle.
249	* @param pCpu The disassembler cpu state for the instruction to be interpreted.
250	* @param pRegFrame The register frame. EIP is NOT changed!
251	* @param pvFault The fault address (CR2).
252	* @param pcbSize Size of the write (if applicable).
253	*
254	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
255	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
256	* to worry about e.g. invalid modrm combinations (!)
257	*
258	* @todo At this time we do NOT check if the instruction overwrites vital information.
259	* Make sure this can't happen!! (will add some assertions/checks later)
260	*/
261	VMMDECL(int) EMInterpretInstructionCPU(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
262	{
263	STAM_PROFILE_START(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Emulate), a);
264	int rc = emInterpretInstructionCPU(pVM, pCpu, pRegFrame, pvFault, pcbSize);
265	STAM_PROFILE_STOP(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Emulate), a);
266	if (RT_SUCCESS(rc))
267	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InterpretSucceeded));
268	else
269	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InterpretFailed));
270	return rc;
271	}
272
273
274	/**
275	* Interpret a port I/O instruction.
276	*
277	* @returns VBox status code suitable for scheduling.
278	* @param pVM The VM handle.
279	* @param pCtxCore The context core. This will be updated on successful return.
280	* @param pCpu The instruction to interpret.
281	* @param cbOp The size of the instruction.
282	* @remark This may raise exceptions.
283	*/
284	VMMDECL(int) EMInterpretPortIO(PVM pVM, PCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, uint32_t cbOp)
285	{
286	/*
287	* Hand it on to IOM.
288	*/
289	#ifdef IN_RC
290	int rc = IOMGCIOPortHandler(pVM, pCtxCore, pCpu);
291	if (IOM_SUCCESS(rc))
292	pCtxCore->rip += cbOp;
293	return rc;
294	#else
295	AssertReleaseMsgFailed(("not implemented\n"));
296	return VERR_NOT_IMPLEMENTED;
297	#endif
298	}
299
300
301	DECLINLINE(int) emRamRead(PVM pVM, void *pDest, RTGCPTR GCSrc, uint32_t cb)
302	{
303	#ifdef IN_RC
304	int rc = MMGCRamRead(pVM, pDest, (void *)GCSrc, cb);
305	if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
306	return rc;
307	/*
308	* The page pool cache may end up here in some cases because it
309	* flushed one of the shadow mappings used by the trapping
310	* instruction and it either flushed the TLB or the CPU reused it.
311	*/
312	RTGCPHYS GCPhys;
313	rc = PGMPhysGCPtr2GCPhys(pVM, GCSrc, &GCPhys);
314	AssertRCReturn(rc, rc);
315	PGMPhysRead(pVM, GCPhys, pDest, cb);
316	return VINF_SUCCESS;
317	#else
318	return PGMPhysReadGCPtr(pVM, pDest, GCSrc, cb);
319	#endif
320	}
321
322
323	DECLINLINE(int) emRamWrite(PVM pVM, RTGCPTR GCDest, void *pSrc, uint32_t cb)
324	{
325	#ifdef IN_RC
326	int rc = MMGCRamWrite(pVM, (void *)GCDest, pSrc, cb);
327	if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
328	return rc;
329	/*
330	* The page pool cache may end up here in some cases because it
331	* flushed one of the shadow mappings used by the trapping
332	* instruction and it either flushed the TLB or the CPU reused it.
333	* We want to play safe here, verifying that we've got write
334	* access doesn't cost us much (see PGMPhysGCPtr2GCPhys()).
335	*/
336	uint64_t fFlags;
337	RTGCPHYS GCPhys;
338	rc = PGMGstGetPage(pVM, GCDest, &fFlags, &GCPhys);
339	if (RT_FAILURE(rc))
340	return rc;
341	if ( !(fFlags & X86_PTE_RW)
342	&& (CPUMGetGuestCR0(pVM) & X86_CR0_WP))
343	return VERR_ACCESS_DENIED;
344
345	PGMPhysWrite(pVM, GCPhys + ((RTGCUINTPTR)GCDest & PAGE_OFFSET_MASK), pSrc, cb);
346	return VINF_SUCCESS;
347
348	#else
349	return PGMPhysWriteGCPtr(pVM, GCDest, pSrc, cb);
350	#endif
351	}
352
353
354	/** Convert sel:addr to a flat GC address. */
355	DECLINLINE(RTGCPTR) emConvertToFlatAddr(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, POP_PARAMETER pParam, RTGCPTR pvAddr)
356	{
357	DIS_SELREG enmPrefixSeg = DISDetectSegReg(pCpu, pParam);
358	return SELMToFlat(pVM, enmPrefixSeg, pRegFrame, pvAddr);
359	}
360
361
362	#if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
363	/**
364	* Get the mnemonic for the disassembled instruction.
365	*
366	* GC/R0 doesn't include the strings in the DIS tables because
367	* of limited space.
368	*/
369	static const char *emGetMnemonic(PDISCPUSTATE pCpu)
370	{
371	switch (pCpu->pCurInstr->opcode)
372	{
373	case OP_XCHG: return "Xchg";
374	case OP_DEC: return "Dec";
375	case OP_INC: return "Inc";
376	case OP_POP: return "Pop";
377	case OP_OR: return "Or";
378	case OP_AND: return "And";
379	case OP_MOV: return "Mov";
380	case OP_INVLPG: return "InvlPg";
381	case OP_CPUID: return "CpuId";
382	case OP_MOV_CR: return "MovCRx";
383	case OP_MOV_DR: return "MovDRx";
384	case OP_LLDT: return "LLdt";
385	case OP_LGDT: return "LGdt";
386	case OP_LIDT: return "LGdt";
387	case OP_CLTS: return "Clts";
388	case OP_MONITOR: return "Monitor";
389	case OP_MWAIT: return "MWait";
390	case OP_RDMSR: return "Rdmsr";
391	case OP_WRMSR: return "Wrmsr";
392	case OP_ADD: return "Add";
393	case OP_ADC: return "Adc";
394	case OP_SUB: return "Sub";
395	case OP_SBB: return "Sbb";
396	case OP_RDTSC: return "Rdtsc";
397	case OP_STI: return "Sti";
398	case OP_XADD: return "XAdd";
399	case OP_HLT: return "Hlt";
400	case OP_IRET: return "Iret";
401	case OP_MOVNTPS: return "MovNTPS";
402	case OP_STOSWD: return "StosWD";
403	case OP_WBINVD: return "WbInvd";
404	case OP_XOR: return "Xor";
405	case OP_BTR: return "Btr";
406	case OP_BTS: return "Bts";
407	case OP_BTC: return "Btc";
408	case OP_LMSW: return "Lmsw";
409	case OP_CMPXCHG: return pCpu->prefix & PREFIX_LOCK ? "Lock CmpXchg" : "CmpXchg";
410	case OP_CMPXCHG8B: return pCpu->prefix & PREFIX_LOCK ? "Lock CmpXchg8b" : "CmpXchg8b";
411
412	default:
413	Log(("Unknown opcode %d\n", pCpu->pCurInstr->opcode));
414	return "???";
415	}
416	}
417	#endif /* VBOX_STRICT \|\| LOG_ENABLED */
418
419
420	/**
421	* XCHG instruction emulation.
422	*/
423	static int emInterpretXchg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
424	{
425	OP_PARAMVAL param1, param2;
426
427	/* Source to make DISQueryParamVal read the register value - ugly hack */
428	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
429	if(RT_FAILURE(rc))
430	return VERR_EM_INTERPRETER;
431
432	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
433	if(RT_FAILURE(rc))
434	return VERR_EM_INTERPRETER;
435
436	#ifdef IN_RC
437	if (TRPMHasTrap(pVM))
438	{
439	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
440	{
441	#endif
442	RTGCPTR pParam1 = 0, pParam2 = 0;
443	uint64_t valpar1, valpar2;
444
445	AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
446	switch(param1.type)
447	{
448	case PARMTYPE_IMMEDIATE: /* register type is translated to this one too */
449	valpar1 = param1.val.val64;
450	break;
451
452	case PARMTYPE_ADDRESS:
453	pParam1 = (RTGCPTR)param1.val.val64;
454	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
455	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
456	rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
457	if (RT_FAILURE(rc))
458	{
459	AssertMsgFailed(("MMGCRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
460	return VERR_EM_INTERPRETER;
461	}
462	break;
463
464	default:
465	AssertFailed();
466	return VERR_EM_INTERPRETER;
467	}
468
469	switch(param2.type)
470	{
471	case PARMTYPE_ADDRESS:
472	pParam2 = (RTGCPTR)param2.val.val64;
473	pParam2 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param2, pParam2);
474	EM_ASSERT_FAULT_RETURN(pParam2 == pvFault, VERR_EM_INTERPRETER);
475	rc = emRamRead(pVM, &valpar2, pParam2, param2.size);
476	if (RT_FAILURE(rc))
477	{
478	AssertMsgFailed(("MMGCRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
479	}
480	break;
481
482	case PARMTYPE_IMMEDIATE:
483	valpar2 = param2.val.val64;
484	break;
485
486	default:
487	AssertFailed();
488	return VERR_EM_INTERPRETER;
489	}
490
491	/* Write value of parameter 2 to parameter 1 (reg or memory address) */
492	if (pParam1 == 0)
493	{
494	Assert(param1.type == PARMTYPE_IMMEDIATE); /* register actually */
495	switch(param1.size)
496	{
497	case 1: //special case for AH etc
498	rc = DISWriteReg8(pRegFrame, pCpu->param1.base.reg_gen, (uint8_t )valpar2); break;
499	case 2: rc = DISWriteReg16(pRegFrame, pCpu->param1.base.reg_gen, (uint16_t)valpar2); break;
500	case 4: rc = DISWriteReg32(pRegFrame, pCpu->param1.base.reg_gen, (uint32_t)valpar2); break;
501	case 8: rc = DISWriteReg64(pRegFrame, pCpu->param1.base.reg_gen, valpar2); break;
502	default: AssertFailedReturn(VERR_EM_INTERPRETER);
503	}
504	if (RT_FAILURE(rc))
505	return VERR_EM_INTERPRETER;
506	}
507	else
508	{
509	rc = emRamWrite(pVM, pParam1, &valpar2, param1.size);
510	if (RT_FAILURE(rc))
511	{
512	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
513	return VERR_EM_INTERPRETER;
514	}
515	}
516
517	/* Write value of parameter 1 to parameter 2 (reg or memory address) */
518	if (pParam2 == 0)
519	{
520	Assert(param2.type == PARMTYPE_IMMEDIATE); /* register actually */
521	switch(param2.size)
522	{
523	case 1: //special case for AH etc
524	rc = DISWriteReg8(pRegFrame, pCpu->param2.base.reg_gen, (uint8_t )valpar1); break;
525	case 2: rc = DISWriteReg16(pRegFrame, pCpu->param2.base.reg_gen, (uint16_t)valpar1); break;
526	case 4: rc = DISWriteReg32(pRegFrame, pCpu->param2.base.reg_gen, (uint32_t)valpar1); break;
527	case 8: rc = DISWriteReg64(pRegFrame, pCpu->param2.base.reg_gen, valpar1); break;
528	default: AssertFailedReturn(VERR_EM_INTERPRETER);
529	}
530	if (RT_FAILURE(rc))
531	return VERR_EM_INTERPRETER;
532	}
533	else
534	{
535	rc = emRamWrite(pVM, pParam2, &valpar1, param2.size);
536	if (RT_FAILURE(rc))
537	{
538	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
539	return VERR_EM_INTERPRETER;
540	}
541	}
542
543	*pcbSize = param2.size;
544	return VINF_SUCCESS;
545	#ifdef IN_RC
546	}
547	}
548	#endif
549	return VERR_EM_INTERPRETER;
550	}
551
552
553	/**
554	* INC and DEC emulation.
555	*/
556	static int emInterpretIncDec(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
557	PFNEMULATEPARAM2 pfnEmulate)
558	{
559	OP_PARAMVAL param1;
560
561	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
562	if(RT_FAILURE(rc))
563	return VERR_EM_INTERPRETER;
564
565	#ifdef IN_RC
566	if (TRPMHasTrap(pVM))
567	{
568	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
569	{
570	#endif
571	RTGCPTR pParam1 = 0;
572	uint64_t valpar1;
573
574	if (param1.type == PARMTYPE_ADDRESS)
575	{
576	pParam1 = (RTGCPTR)param1.val.val64;
577	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
578	#ifdef IN_RC
579	/* Safety check (in theory it could cross a page boundary and fault there though) */
580	AssertReturn(pParam1 == pvFault, VERR_EM_INTERPRETER);
581	#endif
582	rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
583	if (RT_FAILURE(rc))
584	{
585	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
586	return VERR_EM_INTERPRETER;
587	}
588	}
589	else
590	{
591	AssertFailed();
592	return VERR_EM_INTERPRETER;
593	}
594
595	uint32_t eflags;
596
597	eflags = pfnEmulate(&valpar1, param1.size);
598
599	/* Write result back */
600	rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
601	if (RT_FAILURE(rc))
602	{
603	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
604	return VERR_EM_INTERPRETER;
605	}
606
607	/* Update guest's eflags and finish. */
608	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
609	\| (eflags & (X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
610
611	/* All done! */
612	*pcbSize = param1.size;
613	return VINF_SUCCESS;
614	#ifdef IN_RC
615	}
616	}
617	#endif
618	return VERR_EM_INTERPRETER;
619	}
620
621
622	/**
623	* POP Emulation.
624	*/
625	static int emInterpretPop(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
626	{
627	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
628	OP_PARAMVAL param1;
629	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
630	if(RT_FAILURE(rc))
631	return VERR_EM_INTERPRETER;
632
633	#ifdef IN_RC
634	if (TRPMHasTrap(pVM))
635	{
636	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
637	{
638	#endif
639	RTGCPTR pParam1 = 0;
640	uint32_t valpar1;
641	RTGCPTR pStackVal;
642
643	/* Read stack value first */
644	if (SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->ss, &pRegFrame->ssHid) == CPUMODE_16BIT)
645	return VERR_EM_INTERPRETER; /* No legacy 16 bits stuff here, please. */
646
647	/* Convert address; don't bother checking limits etc, as we only read here */
648	pStackVal = SELMToFlat(pVM, DIS_SELREG_SS, pRegFrame, (RTGCPTR)pRegFrame->esp);
649	if (pStackVal == 0)
650	return VERR_EM_INTERPRETER;
651
652	rc = emRamRead(pVM, &valpar1, pStackVal, param1.size);
653	if (RT_FAILURE(rc))
654	{
655	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
656	return VERR_EM_INTERPRETER;
657	}
658
659	if (param1.type == PARMTYPE_ADDRESS)
660	{
661	pParam1 = (RTGCPTR)param1.val.val64;
662
663	/* pop [esp+xx] uses esp after the actual pop! */
664	AssertCompile(USE_REG_ESP == USE_REG_SP);
665	if ( (pCpu->param1.flags & USE_BASE)
666	&& (pCpu->param1.flags & (USE_REG_GEN16\|USE_REG_GEN32))
667	&& pCpu->param1.base.reg_gen == USE_REG_ESP
668	)
669	pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + param1.size);
670
671	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
672	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault \|\| (RTGCPTR)pRegFrame->esp == pvFault, VERR_EM_INTERPRETER);
673	rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
674	if (RT_FAILURE(rc))
675	{
676	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
677	return VERR_EM_INTERPRETER;
678	}
679
680	/* Update ESP as the last step */
681	pRegFrame->esp += param1.size;
682	}
683	else
684	{
685	#ifndef DEBUG_bird // annoying assertion.
686	AssertFailed();
687	#endif
688	return VERR_EM_INTERPRETER;
689	}
690
691	/* All done! */
692	*pcbSize = param1.size;
693	return VINF_SUCCESS;
694	#ifdef IN_RC
695	}
696	}
697	#endif
698	return VERR_EM_INTERPRETER;
699	}
700
701
702	/**
703	* XOR/OR/AND Emulation.
704	*/
705	static int emInterpretOrXorAnd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
706	PFNEMULATEPARAM3 pfnEmulate)
707	{
708	OP_PARAMVAL param1, param2;
709
710	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
711	if(RT_FAILURE(rc))
712	return VERR_EM_INTERPRETER;
713
714	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
715	if(RT_FAILURE(rc))
716	return VERR_EM_INTERPRETER;
717
718	#ifdef IN_RC
719	if (TRPMHasTrap(pVM))
720	{
721	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
722	{
723	#endif
724	RTGCPTR pParam1;
725	uint64_t valpar1, valpar2;
726
727	if (pCpu->param1.size != pCpu->param2.size)
728	{
729	if (pCpu->param1.size < pCpu->param2.size)
730	{
731	AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pCpu), (RTGCPTR)pRegFrame->rip, pCpu->param1.size, pCpu->param2.size)); /* should never happen! */
732	return VERR_EM_INTERPRETER;
733	}
734	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
735	pCpu->param2.size = pCpu->param1.size;
736	param2.size = param1.size;
737	}
738
739	/* The destination is always a virtual address */
740	if (param1.type == PARMTYPE_ADDRESS)
741	{
742	pParam1 = (RTGCPTR)param1.val.val64;
743	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
744	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
745	rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
746	if (RT_FAILURE(rc))
747	{
748	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
749	return VERR_EM_INTERPRETER;
750	}
751	}
752	else
753	{
754	AssertFailed();
755	return VERR_EM_INTERPRETER;
756	}
757
758	/* Register or immediate data */
759	switch(param2.type)
760	{
761	case PARMTYPE_IMMEDIATE: /* both immediate data and register (ugly) */
762	valpar2 = param2.val.val64;
763	break;
764
765	default:
766	AssertFailed();
767	return VERR_EM_INTERPRETER;
768	}
769
770	LogFlow(("emInterpretOrXorAnd %s %RGv %RX64 - %RX64 size %d (%d)\n", emGetMnemonic(pCpu), pParam1, valpar1, valpar2, param2.size, param1.size));
771
772	/* Data read, emulate instruction. */
773	uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
774
775	LogFlow(("emInterpretOrXorAnd %s result %RX64\n", emGetMnemonic(pCpu), valpar1));
776
777	/* Update guest's eflags and finish. */
778	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
779	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
780
781	/* And write it back */
782	rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
783	if (RT_SUCCESS(rc))
784	{
785	/* All done! */
786	*pcbSize = param2.size;
787	return VINF_SUCCESS;
788	}
789	#ifdef IN_RC
790	}
791	}
792	#endif
793	return VERR_EM_INTERPRETER;
794	}
795
796
797	/**
798	* LOCK XOR/OR/AND Emulation.
799	*/
800	static int emInterpretLockOrXorAnd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
801	uint32_t *pcbSize, PFNEMULATELOCKPARAM3 pfnEmulate)
802	{
803	void *pvParam1;
804	OP_PARAMVAL param1, param2;
805
806	#if HC_ARCH_BITS == 32
807	Assert(pCpu->param1.size <= 4);
808	#endif
809
810	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
811	if(RT_FAILURE(rc))
812	return VERR_EM_INTERPRETER;
813
814	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
815	if(RT_FAILURE(rc))
816	return VERR_EM_INTERPRETER;
817
818	if (pCpu->param1.size != pCpu->param2.size)
819	{
820	AssertMsgReturn(pCpu->param1.size >= pCpu->param2.size, /* should never happen! */
821	("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pCpu), (RTGCPTR)pRegFrame->rip, pCpu->param1.size, pCpu->param2.size),
822	VERR_EM_INTERPRETER);
823
824	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
825	pCpu->param2.size = pCpu->param1.size;
826	param2.size = param1.size;
827	}
828
829	#ifdef IN_RC
830	/* Safety check (in theory it could cross a page boundary and fault there though) */
831	Assert( TRPMHasTrap(pVM)
832	&& (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW));
833	EM_ASSERT_FAULT_RETURN(GCPtrPar1 == pvFault, VERR_EM_INTERPRETER);
834	#endif
835
836	/* Register and immediate data == PARMTYPE_IMMEDIATE */
837	AssertReturn(param2.type == PARMTYPE_IMMEDIATE, VERR_EM_INTERPRETER);
838	RTGCUINTREG ValPar2 = param2.val.val64;
839
840	/* The destination is always a virtual address */
841	AssertReturn(param1.type == PARMTYPE_ADDRESS, VERR_EM_INTERPRETER);
842
843	RTGCPTR GCPtrPar1 = param1.val.val64;
844	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
845	#ifdef IN_RC
846	pvParam1 = (void *)GCPtrPar1;
847	#else
848	PGMPAGEMAPLOCK Lock;
849	rc = PGMPhysGCPtr2CCPtr(pVM, GCPtrPar1, &pvParam1, &Lock);
850	AssertRCReturn(rc, VERR_EM_INTERPRETER);
851	#endif
852
853	/* Try emulate it with a one-shot #PF handler in place. (RC) */
854	Log2(("%s %RGv imm%d=%RX64\n", emGetMnemonic(pCpu), GCPtrPar1, pCpu->param2.size*8, ValPar2));
855
856	RTGCUINTREG32 eflags = 0;
857	#ifdef IN_RC
858	MMGCRamRegisterTrapHandler(pVM);
859	#endif
860	rc = pfnEmulate(pvParam1, ValPar2, pCpu->param2.size, &eflags);
861	#ifdef IN_RC
862	MMGCRamDeregisterTrapHandler(pVM);
863	#else
864	PGMPhysReleasePageMappingLock(pVM, &Lock);
865	#endif
866	if (RT_FAILURE(rc))
867	{
868	Log(("%s %RGv imm%d=%RX64-> emulation failed due to page fault!\n", emGetMnemonic(pCpu), GCPtrPar1, pCpu->param2.size*8, ValPar2));
869	return VERR_EM_INTERPRETER;
870	}
871
872	/* Update guest's eflags and finish. */
873	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
874	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
875
876	*pcbSize = param2.size;
877	return VINF_SUCCESS;
878	}
879
880
881	/**
882	* ADD, ADC & SUB Emulation.
883	*/
884	static int emInterpretAddSub(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
885	PFNEMULATEPARAM3 pfnEmulate)
886	{
887	OP_PARAMVAL param1, param2;
888	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
889	if(RT_FAILURE(rc))
890	return VERR_EM_INTERPRETER;
891
892	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
893	if(RT_FAILURE(rc))
894	return VERR_EM_INTERPRETER;
895
896	#ifdef IN_RC
897	if (TRPMHasTrap(pVM))
898	{
899	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
900	{
901	#endif
902	RTGCPTR pParam1;
903	uint64_t valpar1, valpar2;
904
905	if (pCpu->param1.size != pCpu->param2.size)
906	{
907	if (pCpu->param1.size < pCpu->param2.size)
908	{
909	AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pCpu), (RTGCPTR)pRegFrame->rip, pCpu->param1.size, pCpu->param2.size)); /* should never happen! */
910	return VERR_EM_INTERPRETER;
911	}
912	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
913	pCpu->param2.size = pCpu->param1.size;
914	param2.size = param1.size;
915	}
916
917	/* The destination is always a virtual address */
918	if (param1.type == PARMTYPE_ADDRESS)
919	{
920	pParam1 = (RTGCPTR)param1.val.val64;
921	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
922	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
923	rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
924	if (RT_FAILURE(rc))
925	{
926	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
927	return VERR_EM_INTERPRETER;
928	}
929	}
930	else
931	{
932	#ifndef DEBUG_bird
933	AssertFailed();
934	#endif
935	return VERR_EM_INTERPRETER;
936	}
937
938	/* Register or immediate data */
939	switch(param2.type)
940	{
941	case PARMTYPE_IMMEDIATE: /* both immediate data and register (ugly) */
942	valpar2 = param2.val.val64;
943	break;
944
945	default:
946	AssertFailed();
947	return VERR_EM_INTERPRETER;
948	}
949
950	/* Data read, emulate instruction. */
951	uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
952
953	/* Update guest's eflags and finish. */
954	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
955	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
956
957	/* And write it back */
958	rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
959	if (RT_SUCCESS(rc))
960	{
961	/* All done! */
962	*pcbSize = param2.size;
963	return VINF_SUCCESS;
964	}
965	#ifdef IN_RC
966	}
967	}
968	#endif
969	return VERR_EM_INTERPRETER;
970	}
971
972
973	/**
974	* ADC Emulation.
975	*/
976	static int emInterpretAdc(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
977	{
978	if (pRegFrame->eflags.Bits.u1CF)
979	return emInterpretAddSub(pVM, pCpu, pRegFrame, pvFault, pcbSize, EMEmulateAdcWithCarrySet);
980	else
981	return emInterpretAddSub(pVM, pCpu, pRegFrame, pvFault, pcbSize, EMEmulateAdd);
982	}
983
984
985	/**
986	* BTR/C/S Emulation.
987	*/
988	static int emInterpretBitTest(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
989	PFNEMULATEPARAM2UINT32 pfnEmulate)
990	{
991	OP_PARAMVAL param1, param2;
992	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
993	if(RT_FAILURE(rc))
994	return VERR_EM_INTERPRETER;
995
996	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
997	if(RT_FAILURE(rc))
998	return VERR_EM_INTERPRETER;
999
1000	#ifdef IN_RC
1001	if (TRPMHasTrap(pVM))
1002	{
1003	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1004	{
1005	#endif
1006	RTGCPTR pParam1;
1007	uint64_t valpar1 = 0, valpar2;
1008	uint32_t eflags;
1009
1010	/* The destination is always a virtual address */
1011	if (param1.type != PARMTYPE_ADDRESS)
1012	return VERR_EM_INTERPRETER;
1013
1014	pParam1 = (RTGCPTR)param1.val.val64;
1015	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
1016
1017	/* Register or immediate data */
1018	switch(param2.type)
1019	{
1020	case PARMTYPE_IMMEDIATE: /* both immediate data and register (ugly) */
1021	valpar2 = param2.val.val64;
1022	break;
1023
1024	default:
1025	AssertFailed();
1026	return VERR_EM_INTERPRETER;
1027	}
1028
1029	Log2(("emInterpret%s: pvFault=%RGv pParam1=%RGv val2=%x\n", emGetMnemonic(pCpu), pvFault, pParam1, valpar2));
1030	pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + valpar2/8);
1031	EM_ASSERT_FAULT_RETURN((RTGCPTR)((RTGCUINTPTR)pParam1 & ~3) == pvFault, VERR_EM_INTERPRETER);
1032	rc = emRamRead(pVM, &valpar1, pParam1, 1);
1033	if (RT_FAILURE(rc))
1034	{
1035	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
1036	return VERR_EM_INTERPRETER;
1037	}
1038
1039	Log2(("emInterpretBtx: val=%x\n", valpar1));
1040	/* Data read, emulate bit test instruction. */
1041	eflags = pfnEmulate(&valpar1, valpar2 & 0x7);
1042
1043	Log2(("emInterpretBtx: val=%x CF=%d\n", valpar1, !!(eflags & X86_EFL_CF)));
1044
1045	/* Update guest's eflags and finish. */
1046	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1047	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1048
1049	/* And write it back */
1050	rc = emRamWrite(pVM, pParam1, &valpar1, 1);
1051	if (RT_SUCCESS(rc))
1052	{
1053	/* All done! */
1054	*pcbSize = 1;
1055	return VINF_SUCCESS;
1056	}
1057	#ifdef IN_RC
1058	}
1059	}
1060	#endif
1061	return VERR_EM_INTERPRETER;
1062	}
1063
1064
1065	/**
1066	* LOCK BTR/C/S Emulation.
1067	*/
1068	static int emInterpretLockBitTest(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
1069	uint32_t *pcbSize, PFNEMULATELOCKPARAM2 pfnEmulate)
1070	{
1071	void *pvParam1;
1072
1073	OP_PARAMVAL param1, param2;
1074	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
1075	if(RT_FAILURE(rc))
1076	return VERR_EM_INTERPRETER;
1077
1078	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1079	if(RT_FAILURE(rc))
1080	return VERR_EM_INTERPRETER;
1081
1082	/* The destination is always a virtual address */
1083	if (param1.type != PARMTYPE_ADDRESS)
1084	return VERR_EM_INTERPRETER;
1085
1086	/* Register and immediate data == PARMTYPE_IMMEDIATE */
1087	AssertReturn(param2.type == PARMTYPE_IMMEDIATE, VERR_EM_INTERPRETER);
1088	uint64_t ValPar2 = param2.val.val64;
1089
1090	/* Adjust the parameters so what we're dealing with is a bit within the byte pointed to. */
1091	RTGCPTR GCPtrPar1 = param1.val.val64;
1092	GCPtrPar1 = (GCPtrPar1 + ValPar2 / 8);
1093	ValPar2 &= 7;
1094
1095	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
1096	#ifdef IN_RC
1097	Assert(TRPMHasTrap(pVM));
1098	EM_ASSERT_FAULT_RETURN((RTGCPTR)((RTGCUINTPTR)GCPtrPar1 & ~(RTGCUINTPTR)3) == pvFault, VERR_EM_INTERPRETER);
1099	#endif
1100
1101	#ifdef IN_RC
1102	pvParam1 = (void *)GCPtrPar1;
1103	#else
1104	PGMPAGEMAPLOCK Lock;
1105	rc = PGMPhysGCPtr2CCPtr(pVM, GCPtrPar1, &pvParam1, &Lock);
1106	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1107	#endif
1108
1109	Log2(("emInterpretLockBitTest %s: pvFault=%RGv GCPtrPar1=%RGv imm=%RX64\n", emGetMnemonic(pCpu), pvFault, GCPtrPar1, ValPar2));
1110
1111	/* Try emulate it with a one-shot #PF handler in place. (RC) */
1112	RTGCUINTREG32 eflags = 0;
1113	#ifdef IN_RC
1114	MMGCRamRegisterTrapHandler(pVM);
1115	#endif
1116	rc = pfnEmulate(pvParam1, ValPar2, &eflags);
1117	#ifdef IN_RC
1118	MMGCRamDeregisterTrapHandler(pVM);
1119	#else
1120	PGMPhysReleasePageMappingLock(pVM, &Lock);
1121	#endif
1122	if (RT_FAILURE(rc))
1123	{
1124	Log(("emInterpretLockBitTest %s: %RGv imm%d=%RX64 -> emulation failed due to page fault!\n",
1125	emGetMnemonic(pCpu), GCPtrPar1, pCpu->param2.size*8, ValPar2));
1126	return VERR_EM_INTERPRETER;
1127	}
1128
1129	Log2(("emInterpretLockBitTest %s: GCPtrPar1=%RGv imm=%RX64 CF=%d\n", emGetMnemonic(pCpu), GCPtrPar1, ValPar2, !!(eflags & X86_EFL_CF)));
1130
1131	/* Update guest's eflags and finish. */
1132	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1133	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1134
1135	*pcbSize = 1;
1136	return VINF_SUCCESS;
1137	}
1138
1139
1140	/**
1141	* MOV emulation.
1142	*/
1143	static int emInterpretMov(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1144	{
1145	OP_PARAMVAL param1, param2;
1146	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
1147	if(RT_FAILURE(rc))
1148	return VERR_EM_INTERPRETER;
1149
1150	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1151	if(RT_FAILURE(rc))
1152	return VERR_EM_INTERPRETER;
1153
1154	#ifdef IN_RC
1155	if (TRPMHasTrap(pVM))
1156	{
1157	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1158	{
1159	#else
1160	/** @todo Make this the default and don't rely on TRPM information. */
1161	if (param1.type == PARMTYPE_ADDRESS)
1162	{
1163	#endif
1164	RTGCPTR pDest;
1165	uint64_t val64;
1166
1167	switch(param1.type)
1168	{
1169	case PARMTYPE_IMMEDIATE:
1170	if(!(param1.flags & (PARAM_VAL32\|PARAM_VAL64)))
1171	return VERR_EM_INTERPRETER;
1172	/* fallthru */
1173
1174	case PARMTYPE_ADDRESS:
1175	pDest = (RTGCPTR)param1.val.val64;
1176	pDest = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pDest);
1177	break;
1178
1179	default:
1180	AssertFailed();
1181	return VERR_EM_INTERPRETER;
1182	}
1183
1184	switch(param2.type)
1185	{
1186	case PARMTYPE_IMMEDIATE: /* register type is translated to this one too */
1187	val64 = param2.val.val64;
1188	break;
1189
1190	default:
1191	Log(("emInterpretMov: unexpected type=%d rip=%RGv\n", param2.type, (RTGCPTR)pRegFrame->rip));
1192	return VERR_EM_INTERPRETER;
1193	}
1194	#ifdef LOG_ENABLED
1195	if (pCpu->mode == CPUMODE_64BIT)
1196	LogFlow(("EMInterpretInstruction at %RGv: OP_MOV %RGv <- %RX64 (%d) &val64=%RHv\n", (RTGCPTR)pRegFrame->rip, pDest, val64, param2.size, &val64));
1197	else
1198	LogFlow(("EMInterpretInstruction at %08RX64: OP_MOV %RGv <- %08X (%d) &val64=%RHv\n", pRegFrame->rip, pDest, (uint32_t)val64, param2.size, &val64));
1199	#endif
1200
1201	Assert(param2.size <= 8 && param2.size > 0);
1202	EM_ASSERT_FAULT_RETURN(pDest == pvFault, VERR_EM_INTERPRETER);
1203	rc = emRamWrite(pVM, pDest, &val64, param2.size);
1204	if (RT_FAILURE(rc))
1205	return VERR_EM_INTERPRETER;
1206
1207	*pcbSize = param2.size;
1208	}
1209	else
1210	{ /* read fault */
1211	RTGCPTR pSrc;
1212	uint64_t val64;
1213
1214	/* Source */
1215	switch(param2.type)
1216	{
1217	case PARMTYPE_IMMEDIATE:
1218	if(!(param2.flags & (PARAM_VAL32\|PARAM_VAL64)))
1219	return VERR_EM_INTERPRETER;
1220	/* fallthru */
1221
1222	case PARMTYPE_ADDRESS:
1223	pSrc = (RTGCPTR)param2.val.val64;
1224	pSrc = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param2, pSrc);
1225	break;
1226
1227	default:
1228	return VERR_EM_INTERPRETER;
1229	}
1230
1231	Assert(param1.size <= 8 && param1.size > 0);
1232	EM_ASSERT_FAULT_RETURN(pSrc == pvFault, VERR_EM_INTERPRETER);
1233	rc = emRamRead(pVM, &val64, pSrc, param1.size);
1234	if (RT_FAILURE(rc))
1235	return VERR_EM_INTERPRETER;
1236
1237	/* Destination */
1238	switch(param1.type)
1239	{
1240	case PARMTYPE_REGISTER:
1241	switch(param1.size)
1242	{
1243	case 1: rc = DISWriteReg8(pRegFrame, pCpu->param1.base.reg_gen, (uint8_t) val64); break;
1244	case 2: rc = DISWriteReg16(pRegFrame, pCpu->param1.base.reg_gen, (uint16_t)val64); break;
1245	case 4: rc = DISWriteReg32(pRegFrame, pCpu->param1.base.reg_gen, (uint32_t)val64); break;
1246	case 8: rc = DISWriteReg64(pRegFrame, pCpu->param1.base.reg_gen, val64); break;
1247	default:
1248	return VERR_EM_INTERPRETER;
1249	}
1250	if (RT_FAILURE(rc))
1251	return rc;
1252	break;
1253
1254	default:
1255	return VERR_EM_INTERPRETER;
1256	}
1257	#ifdef LOG_ENABLED
1258	if (pCpu->mode == CPUMODE_64BIT)
1259	LogFlow(("EMInterpretInstruction: OP_MOV %RGv -> %RX64 (%d)\n", pSrc, val64, param1.size));
1260	else
1261	LogFlow(("EMInterpretInstruction: OP_MOV %RGv -> %08X (%d)\n", pSrc, (uint32_t)val64, param1.size));
1262	#endif
1263	}
1264	return VINF_SUCCESS;
1265	#ifdef IN_RC
1266	}
1267	#endif
1268	return VERR_EM_INTERPRETER;
1269	}
1270
1271
1272	#ifndef IN_RC
1273	/**
1274	* [REP] STOSWD emulation
1275	*/
1276	static int emInterpretStosWD(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1277	{
1278	int rc;
1279	RTGCPTR GCDest, GCOffset;
1280	uint32_t cbSize;
1281	uint64_t cTransfers;
1282	int offIncrement;
1283
1284	/* Don't support any but these three prefix bytes. */
1285	if ((pCpu->prefix & ~(PREFIX_ADDRSIZE\|PREFIX_OPSIZE\|PREFIX_REP\|PREFIX_REX)))
1286	return VERR_EM_INTERPRETER;
1287
1288	switch (pCpu->addrmode)
1289	{
1290	case CPUMODE_16BIT:
1291	GCOffset = pRegFrame->di;
1292	cTransfers = pRegFrame->cx;
1293	break;
1294	case CPUMODE_32BIT:
1295	GCOffset = pRegFrame->edi;
1296	cTransfers = pRegFrame->ecx;
1297	break;
1298	case CPUMODE_64BIT:
1299	GCOffset = pRegFrame->rdi;
1300	cTransfers = pRegFrame->rcx;
1301	break;
1302	default:
1303	AssertFailed();
1304	return VERR_EM_INTERPRETER;
1305	}
1306
1307	GCDest = SELMToFlat(pVM, DIS_SELREG_ES, pRegFrame, GCOffset);
1308	switch (pCpu->opmode)
1309	{
1310	case CPUMODE_16BIT:
1311	cbSize = 2;
1312	break;
1313	case CPUMODE_32BIT:
1314	cbSize = 4;
1315	break;
1316	case CPUMODE_64BIT:
1317	cbSize = 8;
1318	break;
1319	default:
1320	AssertFailed();
1321	return VERR_EM_INTERPRETER;
1322	}
1323
1324	offIncrement = pRegFrame->eflags.Bits.u1DF ? -(signed)cbSize : (signed)cbSize;
1325
1326	if (!(pCpu->prefix & PREFIX_REP))
1327	{
1328	LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d\n", pRegFrame->es, GCOffset, GCDest, cbSize));
1329
1330	rc = PGMPhysWriteGCPtr(pVM, GCDest, &pRegFrame->rax, cbSize);
1331	if (RT_FAILURE(rc))
1332	return VERR_EM_INTERPRETER;
1333	Assert(rc == VINF_SUCCESS);
1334
1335	/* Update (e/r)di. */
1336	switch (pCpu->addrmode)
1337	{
1338	case CPUMODE_16BIT:
1339	pRegFrame->di += offIncrement;
1340	break;
1341	case CPUMODE_32BIT:
1342	pRegFrame->edi += offIncrement;
1343	break;
1344	case CPUMODE_64BIT:
1345	pRegFrame->rdi += offIncrement;
1346	break;
1347	default:
1348	AssertFailed();
1349	return VERR_EM_INTERPRETER;
1350	}
1351
1352	}
1353	else
1354	{
1355	if (!cTransfers)
1356	return VINF_SUCCESS;
1357
1358	LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d cTransfers=%x DF=%d\n", pRegFrame->es, GCOffset, GCDest, cbSize, cTransfers, pRegFrame->eflags.Bits.u1DF));
1359	/* Access verification first; we currently can't recover properly from traps inside this instruction */
1360	rc = PGMVerifyAccess(pVM, GCDest - ((offIncrement > 0) ? 0 : ((cTransfers-1) * cbSize)),
1361	cTransfers * cbSize,
1362	X86_PTE_RW \| (CPUMGetGuestCPL(pVM, pRegFrame) == 3 ? X86_PTE_US : 0));
1363	if (rc != VINF_SUCCESS)
1364	{
1365	Log(("STOSWD will generate a trap -> recompiler, rc=%d\n", rc));
1366	return VERR_EM_INTERPRETER;
1367	}
1368
1369	/* REP case */
1370	while (cTransfers)
1371	{
1372	rc = PGMPhysWriteGCPtr(pVM, GCDest, &pRegFrame->rax, cbSize);
1373	if (RT_FAILURE(rc))
1374	{
1375	rc = VERR_EM_INTERPRETER;
1376	break;
1377	}
1378
1379	Assert(rc == VINF_SUCCESS);
1380	GCOffset += offIncrement;
1381	GCDest += offIncrement;
1382	cTransfers--;
1383	}
1384
1385	/* Update the registers. */
1386	switch (pCpu->addrmode)
1387	{
1388	case CPUMODE_16BIT:
1389	pRegFrame->di = GCOffset;
1390	pRegFrame->cx = cTransfers;
1391	break;
1392	case CPUMODE_32BIT:
1393	pRegFrame->edi = GCOffset;
1394	pRegFrame->ecx = cTransfers;
1395	break;
1396	case CPUMODE_64BIT:
1397	pRegFrame->rdi = GCOffset;
1398	pRegFrame->rcx = cTransfers;
1399	break;
1400	default:
1401	AssertFailed();
1402	return VERR_EM_INTERPRETER;
1403	}
1404	}
1405
1406	*pcbSize = cbSize;
1407	return rc;
1408	}
1409	#endif /* !IN_RC */
1410
1411	#ifndef IN_RC
1412
1413	/**
1414	* [LOCK] CMPXCHG emulation.
1415	*/
1416	static int emInterpretCmpXchg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1417	{
1418	OP_PARAMVAL param1, param2;
1419
1420	#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL_IN_R0)
1421	Assert(pCpu->param1.size <= 4);
1422	#endif
1423
1424	/* Source to make DISQueryParamVal read the register value - ugly hack */
1425	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1426	if(RT_FAILURE(rc))
1427	return VERR_EM_INTERPRETER;
1428
1429	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1430	if(RT_FAILURE(rc))
1431	return VERR_EM_INTERPRETER;
1432
1433	uint64_t valpar;
1434	switch(param2.type)
1435	{
1436	case PARMTYPE_IMMEDIATE: /* register actually */
1437	valpar = param2.val.val64;
1438	break;
1439
1440	default:
1441	return VERR_EM_INTERPRETER;
1442	}
1443
1444	PGMPAGEMAPLOCK Lock;
1445	RTGCPTR GCPtrPar1;
1446	void *pvParam1;
1447	uint64_t eflags;
1448
1449	AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
1450	switch(param1.type)
1451	{
1452	case PARMTYPE_ADDRESS:
1453	GCPtrPar1 = param1.val.val64;
1454	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
1455
1456	rc = PGMPhysGCPtr2CCPtr(pVM, GCPtrPar1, &pvParam1, &Lock);
1457	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1458	break;
1459
1460	default:
1461	return VERR_EM_INTERPRETER;
1462	}
1463
1464	LogFlow(("%s %RGv rax=%RX64 %RX64\n", emGetMnemonic(pCpu), GCPtrPar1, pRegFrame->rax, valpar));
1465
1466	if (pCpu->prefix & PREFIX_LOCK)
1467	eflags = EMEmulateLockCmpXchg(pvParam1, &pRegFrame->rax, valpar, pCpu->param2.size);
1468	else
1469	eflags = EMEmulateCmpXchg(pvParam1, &pRegFrame->rax, valpar, pCpu->param2.size);
1470
1471	LogFlow(("%s %RGv rax=%RX64 %RX64 ZF=%d\n", emGetMnemonic(pCpu), GCPtrPar1, pRegFrame->rax, valpar, !!(eflags & X86_EFL_ZF)));
1472
1473	/* Update guest's eflags and finish. */
1474	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1475	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1476
1477	*pcbSize = param2.size;
1478	PGMPhysReleasePageMappingLock(pVM, &Lock);
1479	return VINF_SUCCESS;
1480	}
1481
1482
1483	/**
1484	* [LOCK] CMPXCHG8B emulation.
1485	*/
1486	static int emInterpretCmpXchg8b(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1487	{
1488	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
1489	OP_PARAMVAL param1;
1490
1491	/* Source to make DISQueryParamVal read the register value - ugly hack */
1492	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1493	if(RT_FAILURE(rc))
1494	return VERR_EM_INTERPRETER;
1495
1496	RTGCPTR GCPtrPar1;
1497	void *pvParam1;
1498	uint64_t eflags;
1499	PGMPAGEMAPLOCK Lock;
1500
1501	AssertReturn(pCpu->param1.size == 8, VERR_EM_INTERPRETER);
1502	switch(param1.type)
1503	{
1504	case PARMTYPE_ADDRESS:
1505	GCPtrPar1 = param1.val.val64;
1506	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
1507
1508	rc = PGMPhysGCPtr2CCPtr(pVM, GCPtrPar1, &pvParam1, &Lock);
1509	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1510	break;
1511
1512	default:
1513	return VERR_EM_INTERPRETER;
1514	}
1515
1516	LogFlow(("%s %RGv=%08x eax=%08x\n", emGetMnemonic(pCpu), pvParam1, pRegFrame->eax));
1517
1518	if (pCpu->prefix & PREFIX_LOCK)
1519	eflags = EMEmulateLockCmpXchg8b(pvParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
1520	else
1521	eflags = EMEmulateCmpXchg8b(pvParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
1522
1523	LogFlow(("%s %RGv=%08x eax=%08x ZF=%d\n", emGetMnemonic(pCpu), pvParam1, pRegFrame->eax, !!(eflags & X86_EFL_ZF)));
1524
1525	/* Update guest's eflags and finish; note that only ZF is affected. */
1526	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_ZF))
1527	\| (eflags & (X86_EFL_ZF));
1528
1529	*pcbSize = 8;
1530	PGMPhysReleasePageMappingLock(pVM, &Lock);
1531	return VINF_SUCCESS;
1532	}
1533
1534	#else /* IN_RC */
1535
1536	/**
1537	* [LOCK] CMPXCHG emulation.
1538	*/
1539	static int emInterpretCmpXchg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1540	{
1541	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
1542	OP_PARAMVAL param1, param2;
1543
1544	/* Source to make DISQueryParamVal read the register value - ugly hack */
1545	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1546	if(RT_FAILURE(rc))
1547	return VERR_EM_INTERPRETER;
1548
1549	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1550	if(RT_FAILURE(rc))
1551	return VERR_EM_INTERPRETER;
1552
1553	if (TRPMHasTrap(pVM))
1554	{
1555	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1556	{
1557	RTRCPTR pParam1;
1558	uint32_t valpar, eflags;
1559
1560	AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
1561	switch(param1.type)
1562	{
1563	case PARMTYPE_ADDRESS:
1564	pParam1 = (RTRCPTR)param1.val.val64;
1565	pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);
1566	EM_ASSERT_FAULT_RETURN(pParam1 == (RTRCPTR)pvFault, VERR_EM_INTERPRETER);
1567	break;
1568
1569	default:
1570	return VERR_EM_INTERPRETER;
1571	}
1572
1573	switch(param2.type)
1574	{
1575	case PARMTYPE_IMMEDIATE: /* register actually */
1576	valpar = param2.val.val32;
1577	break;
1578
1579	default:
1580	return VERR_EM_INTERPRETER;
1581	}
1582
1583	LogFlow(("%s %RRv eax=%08x %08x\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax, valpar));
1584
1585	MMGCRamRegisterTrapHandler(pVM);
1586	if (pCpu->prefix & PREFIX_LOCK)
1587	rc = EMGCEmulateLockCmpXchg(pParam1, &pRegFrame->eax, valpar, pCpu->param2.size, &eflags);
1588	else
1589	rc = EMGCEmulateCmpXchg(pParam1, &pRegFrame->eax, valpar, pCpu->param2.size, &eflags);
1590	MMGCRamDeregisterTrapHandler(pVM);
1591
1592	if (RT_FAILURE(rc))
1593	{
1594	Log(("%s %RGv eax=%08x %08x -> emulation failed due to page fault!\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax, valpar));
1595	return VERR_EM_INTERPRETER;
1596	}
1597
1598	LogFlow(("%s %RRv eax=%08x %08x ZF=%d\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax, valpar, !!(eflags & X86_EFL_ZF)));
1599
1600	/* Update guest's eflags and finish. */
1601	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1602	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1603
1604	*pcbSize = param2.size;
1605	return VINF_SUCCESS;
1606	}
1607	}
1608	return VERR_EM_INTERPRETER;
1609	}
1610
1611
1612	/**
1613	* [LOCK] CMPXCHG8B emulation.
1614	*/
1615	static int emInterpretCmpXchg8b(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1616	{
1617	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
1618	OP_PARAMVAL param1;
1619
1620	/* Source to make DISQueryParamVal read the register value - ugly hack */
1621	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1622	if(RT_FAILURE(rc))
1623	return VERR_EM_INTERPRETER;
1624
1625	if (TRPMHasTrap(pVM))
1626	{
1627	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1628	{
1629	RTRCPTR pParam1;
1630	uint32_t eflags;
1631
1632	AssertReturn(pCpu->param1.size == 8, VERR_EM_INTERPRETER);
1633	switch(param1.type)
1634	{
1635	case PARMTYPE_ADDRESS:
1636	pParam1 = (RTRCPTR)param1.val.val64;
1637	pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);
1638	EM_ASSERT_FAULT_RETURN(pParam1 == (RTRCPTR)pvFault, VERR_EM_INTERPRETER);
1639	break;
1640
1641	default:
1642	return VERR_EM_INTERPRETER;
1643	}
1644
1645	LogFlow(("%s %RRv=%08x eax=%08x\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax));
1646
1647	MMGCRamRegisterTrapHandler(pVM);
1648	if (pCpu->prefix & PREFIX_LOCK)
1649	rc = EMGCEmulateLockCmpXchg8b(pParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx, &eflags);
1650	else
1651	rc = EMGCEmulateCmpXchg8b(pParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx, &eflags);
1652	MMGCRamDeregisterTrapHandler(pVM);
1653
1654	if (RT_FAILURE(rc))
1655	{
1656	Log(("%s %RGv=%08x eax=%08x -> emulation failed due to page fault!\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax));
1657	return VERR_EM_INTERPRETER;
1658	}
1659
1660	LogFlow(("%s %RGv=%08x eax=%08x ZF=%d\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax, !!(eflags & X86_EFL_ZF)));
1661
1662	/* Update guest's eflags and finish; note that only ZF is affected. */
1663	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_ZF))
1664	\| (eflags & (X86_EFL_ZF));
1665
1666	*pcbSize = 8;
1667	return VINF_SUCCESS;
1668	}
1669	}
1670	return VERR_EM_INTERPRETER;
1671	}
1672
1673	#endif /* IN_RC */
1674
1675	#ifdef IN_RC
1676	/**
1677	* [LOCK] XADD emulation.
1678	*/
1679	static int emInterpretXAdd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1680	{
1681	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
1682	OP_PARAMVAL param1;
1683	uint32_t *pParamReg2;
1684	size_t cbSizeParamReg2;
1685
1686	/* Source to make DISQueryParamVal read the register value - ugly hack */
1687	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1688	if(RT_FAILURE(rc))
1689	return VERR_EM_INTERPRETER;
1690
1691	rc = DISQueryParamRegPtr(pRegFrame, pCpu, &pCpu->param2, (void **)&pParamReg2, &cbSizeParamReg2);
1692	Assert(cbSizeParamReg2 <= 4);
1693	if(RT_FAILURE(rc))
1694	return VERR_EM_INTERPRETER;
1695
1696	if (TRPMHasTrap(pVM))
1697	{
1698	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1699	{
1700	RTRCPTR pParam1;
1701	uint32_t eflags;
1702
1703	AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
1704	switch(param1.type)
1705	{
1706	case PARMTYPE_ADDRESS:
1707	pParam1 = (RTRCPTR)param1.val.val64;
1708	pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);
1709	EM_ASSERT_FAULT_RETURN(pParam1 == (RTRCPTR)pvFault, VERR_EM_INTERPRETER);
1710	break;
1711
1712	default:
1713	return VERR_EM_INTERPRETER;
1714	}
1715
1716	LogFlow(("XAdd %RRv=%08x reg=%08x\n", pParam1, *pParamReg2));
1717
1718	MMGCRamRegisterTrapHandler(pVM);
1719	if (pCpu->prefix & PREFIX_LOCK)
1720	rc = EMGCEmulateLockXAdd(pParam1, pParamReg2, cbSizeParamReg2, &eflags);
1721	else
1722	rc = EMGCEmulateXAdd(pParam1, pParamReg2, cbSizeParamReg2, &eflags);
1723	MMGCRamDeregisterTrapHandler(pVM);
1724
1725	if (RT_FAILURE(rc))
1726	{
1727	Log(("XAdd %RGv reg=%08x -> emulation failed due to page fault!\n", pParam1, *pParamReg2));
1728	return VERR_EM_INTERPRETER;
1729	}
1730
1731	LogFlow(("XAdd %RGv reg=%08x ZF=%d\n", pParam1, *pParamReg2, !!(eflags & X86_EFL_ZF)));
1732
1733	/* Update guest's eflags and finish. */
1734	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1735	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1736
1737	*pcbSize = cbSizeParamReg2;
1738	return VINF_SUCCESS;
1739	}
1740	}
1741	return VERR_EM_INTERPRETER;
1742	}
1743	#endif /* IN_RC */
1744
1745
1746	#ifdef IN_RC
1747	/**
1748	* Interpret IRET (currently only to V86 code)
1749	*
1750	* @returns VBox status code.
1751	* @param pVM The VM handle.
1752	* @param pRegFrame The register frame.
1753	*
1754	*/
1755	VMMDECL(int) EMInterpretIret(PVM pVM, PCPUMCTXCORE pRegFrame)
1756	{
1757	RTGCUINTPTR pIretStack = (RTGCUINTPTR)pRegFrame->esp;
1758	RTGCUINTPTR eip, cs, esp, ss, eflags, ds, es, fs, gs, uMask;
1759	int rc;
1760
1761	Assert(!CPUMIsGuestIn64BitCode(pVM, pRegFrame));
1762
1763	rc = emRamRead(pVM, &eip, (RTGCPTR)pIretStack , 4);
1764	rc \|= emRamRead(pVM, &cs, (RTGCPTR)(pIretStack + 4), 4);
1765	rc \|= emRamRead(pVM, &eflags, (RTGCPTR)(pIretStack + 8), 4);
1766	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1767	AssertReturn(eflags & X86_EFL_VM, VERR_EM_INTERPRETER);
1768
1769	rc \|= emRamRead(pVM, &esp, (RTGCPTR)(pIretStack + 12), 4);
1770	rc \|= emRamRead(pVM, &ss, (RTGCPTR)(pIretStack + 16), 4);
1771	rc \|= emRamRead(pVM, &es, (RTGCPTR)(pIretStack + 20), 4);
1772	rc \|= emRamRead(pVM, &ds, (RTGCPTR)(pIretStack + 24), 4);
1773	rc \|= emRamRead(pVM, &fs, (RTGCPTR)(pIretStack + 28), 4);
1774	rc \|= emRamRead(pVM, &gs, (RTGCPTR)(pIretStack + 32), 4);
1775	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1776
1777	pRegFrame->eip = eip & 0xffff;
1778	pRegFrame->cs = cs;
1779
1780	/* Mask away all reserved bits */
1781	uMask = X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_RF \| X86_EFL_VM \| X86_EFL_AC \| X86_EFL_VIF \| X86_EFL_VIP \| X86_EFL_ID;
1782	eflags &= uMask;
1783
1784	#ifndef IN_RING0
1785	CPUMRawSetEFlags(pVM, pRegFrame, eflags);
1786	#endif
1787	Assert((pRegFrame->eflags.u32 & (X86_EFL_IF\|X86_EFL_IOPL)) == X86_EFL_IF);
1788
1789	pRegFrame->esp = esp;
1790	pRegFrame->ss = ss;
1791	pRegFrame->ds = ds;
1792	pRegFrame->es = es;
1793	pRegFrame->fs = fs;
1794	pRegFrame->gs = gs;
1795
1796	return VINF_SUCCESS;
1797	}
1798	#endif /* IN_RC */
1799
1800
1801	/**
1802	* IRET Emulation.
1803	*/
1804	static int emInterpretIret(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1805	{
1806	/* only allow direct calls to EMInterpretIret for now */
1807	return VERR_EM_INTERPRETER;
1808	}
1809
1810	/**
1811	* WBINVD Emulation.
1812	*/
1813	static int emInterpretWbInvd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1814	{
1815	/* Nothing to do. */
1816	return VINF_SUCCESS;
1817	}
1818
1819
1820	/**
1821	* Interpret INVLPG
1822	*
1823	* @returns VBox status code.
1824	* @param pVM The VM handle.
1825	* @param pRegFrame The register frame.
1826	* @param pAddrGC Operand address
1827	*
1828	*/
1829	VMMDECL(int) EMInterpretInvlpg(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC)
1830	{
1831	int rc;
1832
1833	/** @todo is addr always a flat linear address or ds based
1834	* (in absence of segment override prefixes)????
1835	*/
1836	#ifdef IN_RC
1837	LogFlow(("RC: EMULATE: invlpg %RGv\n", pAddrGC));
1838	#endif
1839	rc = PGMInvalidatePage(pVM, pAddrGC);
1840	if ( rc == VINF_SUCCESS
1841	\|\| rc == VINF_PGM_SYNC_CR3 /* we can rely on the FF */)
1842	return VINF_SUCCESS;
1843	AssertMsgReturn( rc == VERR_REM_FLUSHED_PAGES_OVERFLOW
1844	\|\| rc == VINF_EM_RAW_EMULATE_INSTR,
1845	("%Rrc addr=%RGv\n", rc, pAddrGC),
1846	VERR_EM_INTERPRETER);
1847	return rc;
1848	}
1849
1850
1851	/**
1852	* INVLPG Emulation.
1853	*/
1854	static int emInterpretInvlPg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1855	{
1856	OP_PARAMVAL param1;
1857	RTGCPTR addr;
1858
1859	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1860	if(RT_FAILURE(rc))
1861	return VERR_EM_INTERPRETER;
1862
1863	switch(param1.type)
1864	{
1865	case PARMTYPE_IMMEDIATE:
1866	case PARMTYPE_ADDRESS:
1867	if(!(param1.flags & (PARAM_VAL32\|PARAM_VAL64)))
1868	return VERR_EM_INTERPRETER;
1869	addr = (RTGCPTR)param1.val.val64;
1870	break;
1871
1872	default:
1873	return VERR_EM_INTERPRETER;
1874	}
1875
1876	/** @todo is addr always a flat linear address or ds based
1877	* (in absence of segment override prefixes)????
1878	*/
1879	#ifdef IN_RC
1880	LogFlow(("RC: EMULATE: invlpg %RGv\n", addr));
1881	#endif
1882	rc = PGMInvalidatePage(pVM, addr);
1883	if ( rc == VINF_SUCCESS
1884	\|\| rc == VINF_PGM_SYNC_CR3 /* we can rely on the FF */)
1885	return VINF_SUCCESS;
1886	AssertMsgReturn( rc == VERR_REM_FLUSHED_PAGES_OVERFLOW
1887	\|\| rc == VINF_EM_RAW_EMULATE_INSTR,
1888	("%Rrc addr=%RGv\n", rc, addr),
1889	VERR_EM_INTERPRETER);
1890	return rc;
1891	}
1892
1893
1894	/**
1895	* Interpret CPUID given the parameters in the CPU context
1896	*
1897	* @returns VBox status code.
1898	* @param pVM The VM handle.
1899	* @param pRegFrame The register frame.
1900	*
1901	*/
1902	VMMDECL(int) EMInterpretCpuId(PVM pVM, PCPUMCTXCORE pRegFrame)
1903	{
1904	uint32_t iLeaf = pRegFrame->eax;
1905
1906	/* cpuid clears the high dwords of the affected 64 bits registers. */
1907	pRegFrame->rax = 0;
1908	pRegFrame->rbx = 0;
1909	pRegFrame->rcx = 0;
1910	pRegFrame->rdx = 0;
1911
1912	/* Note: operates the same in 64 and non-64 bits mode. */
1913	CPUMGetGuestCpuId(pVM, iLeaf, &pRegFrame->eax, &pRegFrame->ebx, &pRegFrame->ecx, &pRegFrame->edx);
1914	Log(("Emulate: CPUID %x -> %08x %08x %08x %08x\n", iLeaf, pRegFrame->eax, pRegFrame->ebx, pRegFrame->ecx, pRegFrame->edx));
1915	return VINF_SUCCESS;
1916	}
1917
1918
1919	/**
1920	* CPUID Emulation.
1921	*/
1922	static int emInterpretCpuId(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1923	{
1924	int rc = EMInterpretCpuId(pVM, pRegFrame);
1925	return rc;
1926	}
1927
1928
1929	/**
1930	* Interpret CRx read
1931	*
1932	* @returns VBox status code.
1933	* @param pVM The VM handle.
1934	* @param pRegFrame The register frame.
1935	* @param DestRegGen General purpose register index (USE_REG_E**))
1936	* @param SrcRegCRx CRx register index (USE_REG_CR*)
1937	*
1938	*/
1939	VMMDECL(int) EMInterpretCRxRead(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx)
1940	{
1941	int rc;
1942	uint64_t val64;
1943
1944	if (SrcRegCrx == USE_REG_CR8)
1945	{
1946	val64 = 0;
1947	rc = PDMApicGetTPR(pVM, (uint8_t *)&val64, NULL);
1948	AssertMsgRCReturn(rc, ("PDMApicGetTPR failed\n"), VERR_EM_INTERPRETER);
1949	}
1950	else
1951	{
1952	rc = CPUMGetGuestCRx(pVM, SrcRegCrx, &val64);
1953	AssertMsgRCReturn(rc, ("CPUMGetGuestCRx %d failed\n", SrcRegCrx), VERR_EM_INTERPRETER);
1954	}
1955
1956	if (CPUMIsGuestIn64BitCode(pVM, pRegFrame))
1957	rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
1958	else
1959	rc = DISWriteReg32(pRegFrame, DestRegGen, val64);
1960
1961	if(RT_SUCCESS(rc))
1962	{
1963	LogFlow(("MOV_CR: gen32=%d CR=%d val=%RX64\n", DestRegGen, SrcRegCrx, val64));
1964	return VINF_SUCCESS;
1965	}
1966	return VERR_EM_INTERPRETER;
1967	}
1968
1969
1970
1971	/**
1972	* Interpret CLTS
1973	*
1974	* @returns VBox status code.
1975	* @param pVM The VM handle.
1976	*
1977	*/
1978	VMMDECL(int) EMInterpretCLTS(PVM pVM)
1979	{
1980	uint64_t cr0 = CPUMGetGuestCR0(pVM);
1981	if (!(cr0 & X86_CR0_TS))
1982	return VINF_SUCCESS;
1983	return CPUMSetGuestCR0(pVM, cr0 & ~X86_CR0_TS);
1984	}
1985
1986	/**
1987	* CLTS Emulation.
1988	*/
1989	static int emInterpretClts(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1990	{
1991	return EMInterpretCLTS(pVM);
1992	}
1993
1994
1995	/**
1996	* Update CRx
1997	*
1998	* @returns VBox status code.
1999	* @param pVM The VM handle.
2000	* @param pRegFrame The register frame.
2001	* @param DestRegCRx CRx register index (USE_REG_CR*)
2002	* @param val New CRx value
2003	*
2004	*/
2005	static int EMUpdateCRx(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint64_t val)
2006	{
2007	uint64_t oldval;
2008	uint64_t msrEFER;
2009	int rc;
2010
2011	/** @todo Clean up this mess. */
2012	LogFlow(("EMInterpretCRxWrite at %RGv CR%d <- %RX64\n", (RTGCPTR)pRegFrame->rip, DestRegCrx, val));
2013	switch (DestRegCrx)
2014	{
2015	case USE_REG_CR0:
2016	oldval = CPUMGetGuestCR0(pVM);
2017	#ifdef IN_RC
2018	/* CR0.WP and CR0.AM changes require a reschedule run in ring 3. */
2019	if ( (val & (X86_CR0_WP \| X86_CR0_AM))
2020	!= (oldval & (X86_CR0_WP \| X86_CR0_AM)))
2021	return VERR_EM_INTERPRETER;
2022	#endif
2023	CPUMSetGuestCR0(pVM, val);
2024	val = CPUMGetGuestCR0(pVM);
2025	if ( (oldval & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE))
2026	!= (val & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE)))
2027	{
2028	/* global flush */
2029	rc = PGMFlushTLB(pVM, CPUMGetGuestCR3(pVM), true /* global */);
2030	AssertRCReturn(rc, rc);
2031	}
2032
2033	/* Deal with long mode enabling/disabling. */
2034	msrEFER = CPUMGetGuestEFER(pVM);
2035	if (msrEFER & MSR_K6_EFER_LME)
2036	{
2037	if ( !(oldval & X86_CR0_PG)
2038	&& (val & X86_CR0_PG))
2039	{
2040	/* Illegal to have an active 64 bits CS selector (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
2041	if (pRegFrame->csHid.Attr.n.u1Long)
2042	{
2043	AssertMsgFailed(("Illegal enabling of paging with CS.u1Long = 1!!\n"));
2044	return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
2045	}
2046
2047	/* Illegal to switch to long mode before activating PAE first (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
2048	if (!(CPUMGetGuestCR4(pVM) & X86_CR4_PAE))
2049	{
2050	AssertMsgFailed(("Illegal enabling of paging with PAE disabled!!\n"));
2051	return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
2052	}
2053	msrEFER \|= MSR_K6_EFER_LMA;
2054	}
2055	else
2056	if ( (oldval & X86_CR0_PG)
2057	&& !(val & X86_CR0_PG))
2058	{
2059	msrEFER &= ~MSR_K6_EFER_LMA;
2060	/* @todo Do we need to cut off rip here? High dword of rip is undefined, so it shouldn't really matter. */
2061	}
2062	CPUMSetGuestEFER(pVM, msrEFER);
2063	}
2064	return PGMChangeMode(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR4(pVM), CPUMGetGuestEFER(pVM));
2065
2066	case USE_REG_CR2:
2067	rc = CPUMSetGuestCR2(pVM, val); AssertRC(rc);
2068	return VINF_SUCCESS;
2069
2070	case USE_REG_CR3:
2071	/* Reloading the current CR3 means the guest just wants to flush the TLBs */
2072	rc = CPUMSetGuestCR3(pVM, val); AssertRC(rc);
2073	if (CPUMGetGuestCR0(pVM) & X86_CR0_PG)
2074	{
2075	/* flush */
2076	rc = PGMFlushTLB(pVM, val, !(CPUMGetGuestCR4(pVM) & X86_CR4_PGE));
2077	AssertRCReturn(rc, rc);
2078	}
2079	return VINF_SUCCESS;
2080
2081	case USE_REG_CR4:
2082	oldval = CPUMGetGuestCR4(pVM);
2083	rc = CPUMSetGuestCR4(pVM, val); AssertRC(rc);
2084	val = CPUMGetGuestCR4(pVM);
2085
2086	msrEFER = CPUMGetGuestEFER(pVM);
2087	/* Illegal to disable PAE when long mode is active. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
2088	if ( (msrEFER & MSR_K6_EFER_LMA)
2089	&& (oldval & X86_CR4_PAE)
2090	&& !(val & X86_CR4_PAE))
2091	{
2092	return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
2093	}
2094
2095	if ( (oldval & (X86_CR4_PGE\|X86_CR4_PAE\|X86_CR4_PSE))
2096	!= (val & (X86_CR4_PGE\|X86_CR4_PAE\|X86_CR4_PSE)))
2097	{
2098	/* global flush */
2099	rc = PGMFlushTLB(pVM, CPUMGetGuestCR3(pVM), true /* global */);
2100	AssertRCReturn(rc, rc);
2101	}
2102	# ifdef IN_RC
2103	/* Feeling extremely lazy. */
2104	if ( (oldval & (X86_CR4_OSFSXR\|X86_CR4_OSXMMEEXCPT\|X86_CR4_PCE\|X86_CR4_MCE\|X86_CR4_PAE\|X86_CR4_DE\|X86_CR4_TSD\|X86_CR4_PVI\|X86_CR4_VME))
2105	!= (val & (X86_CR4_OSFSXR\|X86_CR4_OSXMMEEXCPT\|X86_CR4_PCE\|X86_CR4_MCE\|X86_CR4_PAE\|X86_CR4_DE\|X86_CR4_TSD\|X86_CR4_PVI\|X86_CR4_VME)))
2106	{
2107	Log(("emInterpretMovCRx: CR4: %#RX64->%#RX64 => R3\n", oldval, val));
2108	VM_FF_SET(pVM, VM_FF_TO_R3);
2109	}
2110	# endif
2111	return PGMChangeMode(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR4(pVM), CPUMGetGuestEFER(pVM));
2112
2113	case USE_REG_CR8:
2114	return PDMApicSetTPR(pVM, val);
2115
2116	default:
2117	AssertFailed();
2118	case USE_REG_CR1: /* illegal op */
2119	break;
2120	}
2121	return VERR_EM_INTERPRETER;
2122	}
2123
2124	/**
2125	* Interpret CRx write
2126	*
2127	* @returns VBox status code.
2128	* @param pVM The VM handle.
2129	* @param pRegFrame The register frame.
2130	* @param DestRegCRx CRx register index (USE_REG_CR*)
2131	* @param SrcRegGen General purpose register index (USE_REG_E**))
2132	*
2133	*/
2134	VMMDECL(int) EMInterpretCRxWrite(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint32_t SrcRegGen)
2135	{
2136	uint64_t val;
2137	int rc;
2138
2139	if (CPUMIsGuestIn64BitCode(pVM, pRegFrame))
2140	{
2141	rc = DISFetchReg64(pRegFrame, SrcRegGen, &val);
2142	}
2143	else
2144	{
2145	uint32_t val32;
2146	rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
2147	val = val32;
2148	}
2149
2150	if (RT_SUCCESS(rc))
2151	return EMUpdateCRx(pVM, pRegFrame, DestRegCrx, val);
2152
2153	return VERR_EM_INTERPRETER;
2154	}
2155
2156	/**
2157	* Interpret LMSW
2158	*
2159	* @returns VBox status code.
2160	* @param pVM The VM handle.
2161	* @param pRegFrame The register frame.
2162	* @param u16Data LMSW source data.
2163	*
2164	*/
2165	VMMDECL(int) EMInterpretLMSW(PVM pVM, PCPUMCTXCORE pRegFrame, uint16_t u16Data)
2166	{
2167	uint64_t OldCr0 = CPUMGetGuestCR0(pVM);
2168
2169	/* Only PE, MP, EM and TS can be changed; note that PE can't be cleared by this instruction. */
2170	uint64_t NewCr0 = ( OldCr0 & ~( X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
2171	\| (u16Data & (X86_CR0_PE \| X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS));
2172
2173	return EMUpdateCRx(pVM, pRegFrame, USE_REG_CR0, NewCr0);
2174	}
2175
2176	/**
2177	* LMSW Emulation.
2178	*/
2179	static int emInterpretLmsw(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2180	{
2181	OP_PARAMVAL param1;
2182	uint32_t val;
2183
2184	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
2185	if(RT_FAILURE(rc))
2186	return VERR_EM_INTERPRETER;
2187
2188	switch(param1.type)
2189	{
2190	case PARMTYPE_IMMEDIATE:
2191	case PARMTYPE_ADDRESS:
2192	if(!(param1.flags & PARAM_VAL16))
2193	return VERR_EM_INTERPRETER;
2194	val = param1.val.val32;
2195	break;
2196
2197	default:
2198	return VERR_EM_INTERPRETER;
2199	}
2200
2201	LogFlow(("emInterpretLmsw %x\n", val));
2202	return EMInterpretLMSW(pVM, pRegFrame, val);
2203	}
2204
2205	/**
2206	* MOV CRx
2207	*/
2208	static int emInterpretMovCRx(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2209	{
2210	if ((pCpu->param1.flags == USE_REG_GEN32 \|\| pCpu->param1.flags == USE_REG_GEN64) && pCpu->param2.flags == USE_REG_CR)
2211	return EMInterpretCRxRead(pVM, pRegFrame, pCpu->param1.base.reg_gen, pCpu->param2.base.reg_ctrl);
2212
2213	if (pCpu->param1.flags == USE_REG_CR && (pCpu->param2.flags == USE_REG_GEN32 \|\| pCpu->param2.flags == USE_REG_GEN64))
2214	return EMInterpretCRxWrite(pVM, pRegFrame, pCpu->param1.base.reg_ctrl, pCpu->param2.base.reg_gen);
2215
2216	AssertMsgFailedReturn(("Unexpected control register move\n"), VERR_EM_INTERPRETER);
2217	return VERR_EM_INTERPRETER;
2218	}
2219
2220
2221	/**
2222	* Interpret DRx write
2223	*
2224	* @returns VBox status code.
2225	* @param pVM The VM handle.
2226	* @param pRegFrame The register frame.
2227	* @param DestRegDRx DRx register index (USE_REG_DR*)
2228	* @param SrcRegGen General purpose register index (USE_REG_E**))
2229	*
2230	*/
2231	VMMDECL(int) EMInterpretDRxWrite(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen)
2232	{
2233	uint64_t val;
2234	int rc;
2235
2236	if (CPUMIsGuestIn64BitCode(pVM, pRegFrame))
2237	{
2238	rc = DISFetchReg64(pRegFrame, SrcRegGen, &val);
2239	}
2240	else
2241	{
2242	uint32_t val32;
2243	rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
2244	val = val32;
2245	}
2246
2247	if (RT_SUCCESS(rc))
2248	{
2249	/** @todo we don't fail if illegal bits are set/cleared for e.g. dr7 */
2250	rc = CPUMSetGuestDRx(pVM, DestRegDrx, val);
2251	if (RT_SUCCESS(rc))
2252	return rc;
2253	AssertMsgFailed(("CPUMSetGuestDRx %d failed\n", DestRegDrx));
2254	}
2255	return VERR_EM_INTERPRETER;
2256	}
2257
2258
2259	/**
2260	* Interpret DRx read
2261	*
2262	* @returns VBox status code.
2263	* @param pVM The VM handle.
2264	* @param pRegFrame The register frame.
2265	* @param DestRegGen General purpose register index (USE_REG_E**))
2266	* @param SrcRegDRx DRx register index (USE_REG_DR*)
2267	*
2268	*/
2269	VMMDECL(int) EMInterpretDRxRead(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx)
2270	{
2271	uint64_t val64;
2272
2273	int rc = CPUMGetGuestDRx(pVM, SrcRegDrx, &val64);
2274	AssertMsgRCReturn(rc, ("CPUMGetGuestDRx %d failed\n", SrcRegDrx), VERR_EM_INTERPRETER);
2275	if (CPUMIsGuestIn64BitCode(pVM, pRegFrame))
2276	{
2277	rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
2278	}
2279	else
2280	rc = DISWriteReg32(pRegFrame, DestRegGen, (uint32_t)val64);
2281
2282	if (RT_SUCCESS(rc))
2283	return VINF_SUCCESS;
2284
2285	return VERR_EM_INTERPRETER;
2286	}
2287
2288
2289	/**
2290	* MOV DRx
2291	*/
2292	static int emInterpretMovDRx(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2293	{
2294	int rc = VERR_EM_INTERPRETER;
2295
2296	if((pCpu->param1.flags == USE_REG_GEN32 \|\| pCpu->param1.flags == USE_REG_GEN64) && pCpu->param2.flags == USE_REG_DBG)
2297	{
2298	rc = EMInterpretDRxRead(pVM, pRegFrame, pCpu->param1.base.reg_gen, pCpu->param2.base.reg_dbg);
2299	}
2300	else
2301	if(pCpu->param1.flags == USE_REG_DBG && (pCpu->param2.flags == USE_REG_GEN32 \|\| pCpu->param2.flags == USE_REG_GEN64))
2302	{
2303	rc = EMInterpretDRxWrite(pVM, pRegFrame, pCpu->param1.base.reg_dbg, pCpu->param2.base.reg_gen);
2304	}
2305	else
2306	AssertMsgFailed(("Unexpected debug register move\n"));
2307
2308	return rc;
2309	}
2310
2311
2312	/**
2313	* LLDT Emulation.
2314	*/
2315	static int emInterpretLLdt(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2316	{
2317	OP_PARAMVAL param1;
2318	RTSEL sel;
2319
2320	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
2321	if(RT_FAILURE(rc))
2322	return VERR_EM_INTERPRETER;
2323
2324	switch(param1.type)
2325	{
2326	case PARMTYPE_ADDRESS:
2327	return VERR_EM_INTERPRETER; //feeling lazy right now
2328
2329	case PARMTYPE_IMMEDIATE:
2330	if(!(param1.flags & PARAM_VAL16))
2331	return VERR_EM_INTERPRETER;
2332	sel = (RTSEL)param1.val.val16;
2333	break;
2334
2335	default:
2336	return VERR_EM_INTERPRETER;
2337	}
2338
2339	if (sel == 0)
2340	{
2341	if (CPUMGetHyperLDTR(pVM) == 0)
2342	{
2343	// this simple case is most frequent in Windows 2000 (31k - boot & shutdown)
2344	return VINF_SUCCESS;
2345	}
2346	}
2347	//still feeling lazy
2348	return VERR_EM_INTERPRETER;
2349	}
2350
2351	#ifdef IN_RING0
2352	/**
2353	* LIDT/LGDT Emulation.
2354	*/
2355	static int emInterpretLIGdt(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2356	{
2357	OP_PARAMVAL param1;
2358	RTGCPTR pParam1;
2359	X86XDTR32 dtr32;
2360
2361	Log(("Emulate %s at %RGv\n", emGetMnemonic(pCpu), (RTGCPTR)pRegFrame->rip));
2362
2363	/* Only for the VT-x real-mode emulation case. */
2364	if (!CPUMIsGuestInRealMode(pVM))
2365	return VERR_EM_INTERPRETER;
2366
2367	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
2368	if(RT_FAILURE(rc))
2369	return VERR_EM_INTERPRETER;
2370
2371	switch(param1.type)
2372	{
2373	case PARMTYPE_ADDRESS:
2374	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, param1.val.val16);
2375	break;
2376
2377	default:
2378	return VERR_EM_INTERPRETER;
2379	}
2380
2381	rc = emRamRead(pVM, &dtr32, pParam1, sizeof(dtr32));
2382	AssertRCReturn(rc, VERR_EM_INTERPRETER);
2383
2384	if (!(pCpu->prefix & PREFIX_OPSIZE))
2385	dtr32.uAddr &= 0xffffff; /* 16 bits operand size */
2386
2387	if (pCpu->pCurInstr->opcode == OP_LIDT)
2388	CPUMSetGuestIDTR(pVM, dtr32.uAddr, dtr32.cb);
2389	else
2390	CPUMSetGuestGDTR(pVM, dtr32.uAddr, dtr32.cb);
2391
2392	return VINF_SUCCESS;
2393	}
2394	#endif
2395
2396
2397	#ifdef IN_RC
2398	/**
2399	* STI Emulation.
2400	*
2401	* @remark the instruction following sti is guaranteed to be executed before any interrupts are dispatched
2402	*/
2403	static int emInterpretSti(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2404	{
2405	PPATMGCSTATE pGCState = PATMQueryGCState(pVM);
2406
2407	if(!pGCState)
2408	{
2409	Assert(pGCState);
2410	return VERR_EM_INTERPRETER;
2411	}
2412	pGCState->uVMFlags \|= X86_EFL_IF;
2413
2414	Assert(pRegFrame->eflags.u32 & X86_EFL_IF);
2415	Assert(pvFault == SELMToFlat(pVM, DIS_SELREG_CS, pRegFrame, (RTGCPTR)pRegFrame->rip));
2416
2417	pVM->em.s.GCPtrInhibitInterrupts = pRegFrame->eip + pCpu->opsize;
2418	VM_FF_SET(pVM, VM_FF_INHIBIT_INTERRUPTS);
2419
2420	return VINF_SUCCESS;
2421	}
2422	#endif /* IN_RC */
2423
2424
2425	/**
2426	* HLT Emulation.
2427	*/
2428	static int emInterpretHlt(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2429	{
2430	return VINF_EM_HALT;
2431	}
2432
2433
2434	/**
2435	* Interpret RDTSC
2436	*
2437	* @returns VBox status code.
2438	* @param pVM The VM handle.
2439	* @param pRegFrame The register frame.
2440	*
2441	*/
2442	VMMDECL(int) EMInterpretRdtsc(PVM pVM, PCPUMCTXCORE pRegFrame)
2443	{
2444	unsigned uCR4 = CPUMGetGuestCR4(pVM);
2445
2446	if (uCR4 & X86_CR4_TSD)
2447	return VERR_EM_INTERPRETER; /* genuine #GP */
2448
2449	uint64_t uTicks = TMCpuTickGet(pVM);
2450
2451	/* Same behaviour in 32 & 64 bits mode */
2452	pRegFrame->rax = (uint32_t)uTicks;
2453	pRegFrame->rdx = (uTicks >> 32ULL);
2454
2455	return VINF_SUCCESS;
2456	}
2457
2458	VMMDECL(int) EMInterpretRdtscp(PVM pVM, PCPUMCTX pCtx)
2459	{
2460	unsigned uCR4 = CPUMGetGuestCR4(pVM);
2461
2462	if (!CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
2463	{
2464	AssertFailed();
2465	return VERR_EM_INTERPRETER; /* genuine #UD */
2466	}
2467
2468	if (uCR4 & X86_CR4_TSD)
2469	return VERR_EM_INTERPRETER; /* genuine #GP */
2470
2471	uint64_t uTicks = TMCpuTickGet(pVM);
2472
2473	/* Same behaviour in 32 & 64 bits mode */
2474	pCtx->rax = (uint32_t)uTicks;
2475	pCtx->rdx = (uTicks >> 32ULL);
2476	/* Low dword of the TSC_AUX msr only. */
2477	pCtx->rcx = (uint32_t)CPUMGetGuestMsr(pVM, MSR_K8_TSC_AUX);
2478
2479	return VINF_SUCCESS;
2480	}
2481
2482	/**
2483	* RDTSC Emulation.
2484	*/
2485	static int emInterpretRdtsc(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2486	{
2487	return EMInterpretRdtsc(pVM, pRegFrame);
2488	}
2489
2490
2491	/**
2492	* MONITOR Emulation.
2493	*/
2494	static int emInterpretMonitor(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2495	{
2496	uint32_t u32Dummy, u32ExtFeatures, cpl;
2497
2498	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
2499	if (pRegFrame->ecx != 0)
2500	return VERR_EM_INTERPRETER; /* illegal value. */
2501
2502	/* Get the current privilege level. */
2503	cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2504	if (cpl != 0)
2505	return VERR_EM_INTERPRETER; /* supervisor only */
2506
2507	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
2508	if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
2509	return VERR_EM_INTERPRETER; /* not supported */
2510
2511	return VINF_SUCCESS;
2512	}
2513
2514
2515	/**
2516	* MWAIT Emulation.
2517	*/
2518	static int emInterpretMWait(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2519	{
2520	uint32_t u32Dummy, u32ExtFeatures, cpl;
2521
2522	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
2523	if (pRegFrame->ecx != 0)
2524	return VERR_EM_INTERPRETER; /* illegal value. */
2525
2526	/* Get the current privilege level. */
2527	cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2528	if (cpl != 0)
2529	return VERR_EM_INTERPRETER; /* supervisor only */
2530
2531	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
2532	if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
2533	return VERR_EM_INTERPRETER; /* not supported */
2534
2535	/** @todo not completely correct */
2536	return VINF_EM_HALT;
2537	}
2538
2539
2540	#ifdef LOG_ENABLED
2541	static const char *emMSRtoString(uint32_t uMsr)
2542	{
2543	switch (uMsr)
2544	{
2545	case MSR_IA32_APICBASE:
2546	return "MSR_IA32_APICBASE";
2547	case MSR_IA32_CR_PAT:
2548	return "MSR_IA32_CR_PAT";
2549	case MSR_IA32_SYSENTER_CS:
2550	return "MSR_IA32_SYSENTER_CS";
2551	case MSR_IA32_SYSENTER_EIP:
2552	return "MSR_IA32_SYSENTER_EIP";
2553	case MSR_IA32_SYSENTER_ESP:
2554	return "MSR_IA32_SYSENTER_ESP";
2555	case MSR_K6_EFER:
2556	return "MSR_K6_EFER";
2557	case MSR_K8_SF_MASK:
2558	return "MSR_K8_SF_MASK";
2559	case MSR_K6_STAR:
2560	return "MSR_K6_STAR";
2561	case MSR_K8_LSTAR:
2562	return "MSR_K8_LSTAR";
2563	case MSR_K8_CSTAR:
2564	return "MSR_K8_CSTAR";
2565	case MSR_K8_FS_BASE:
2566	return "MSR_K8_FS_BASE";
2567	case MSR_K8_GS_BASE:
2568	return "MSR_K8_GS_BASE";
2569	case MSR_K8_KERNEL_GS_BASE:
2570	return "MSR_K8_KERNEL_GS_BASE";
2571	case MSR_K8_TSC_AUX:
2572	return "MSR_K8_TSC_AUX";
2573	case MSR_IA32_BIOS_SIGN_ID:
2574	return "Unsupported MSR_IA32_BIOS_SIGN_ID";
2575	case MSR_IA32_PLATFORM_ID:
2576	return "Unsupported MSR_IA32_PLATFORM_ID";
2577	case MSR_IA32_BIOS_UPDT_TRIG:
2578	return "Unsupported MSR_IA32_BIOS_UPDT_TRIG";
2579	case MSR_IA32_TSC:
2580	return "Unsupported MSR_IA32_TSC";
2581	case MSR_IA32_MTRR_CAP:
2582	return "Unsupported MSR_IA32_MTRR_CAP";
2583	case MSR_IA32_MCP_CAP:
2584	return "Unsupported MSR_IA32_MCP_CAP";
2585	case MSR_IA32_MCP_STATUS:
2586	return "Unsupported MSR_IA32_MCP_STATUS";
2587	case MSR_IA32_MCP_CTRL:
2588	return "Unsupported MSR_IA32_MCP_CTRL";
2589	case MSR_IA32_MTRR_DEF_TYPE:
2590	return "Unsupported MSR_IA32_MTRR_DEF_TYPE";
2591	case MSR_K7_EVNTSEL0:
2592	return "Unsupported MSR_K7_EVNTSEL0";
2593	case MSR_K7_EVNTSEL1:
2594	return "Unsupported MSR_K7_EVNTSEL1";
2595	case MSR_K7_EVNTSEL2:
2596	return "Unsupported MSR_K7_EVNTSEL2";
2597	case MSR_K7_EVNTSEL3:
2598	return "Unsupported MSR_K7_EVNTSEL3";
2599	case MSR_IA32_MC0_CTL:
2600	return "Unsupported MSR_IA32_MC0_CTL";
2601	case MSR_IA32_MC0_STATUS:
2602	return "Unsupported MSR_IA32_MC0_STATUS";
2603	}
2604	return "Unknown MSR";
2605	}
2606	#endif /* LOG_ENABLED */
2607
2608
2609	/**
2610	* Interpret RDMSR
2611	*
2612	* @returns VBox status code.
2613	* @param pVM The VM handle.
2614	* @param pRegFrame The register frame.
2615	*
2616	*/
2617	VMMDECL(int) EMInterpretRdmsr(PVM pVM, PCPUMCTXCORE pRegFrame)
2618	{
2619	uint32_t u32Dummy, u32Features, cpl;
2620	uint64_t val;
2621	CPUMCTX *pCtx;
2622	int rc = VINF_SUCCESS;
2623
2624	/** @todo According to the Intel manuals, there's a REX version of RDMSR that is slightly different.
2625	* That version clears the high dwords of both RDX & RAX */
2626	pCtx = CPUMQueryGuestCtxPtr(pVM);
2627
2628	/* Get the current privilege level. */
2629	cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2630	if (cpl != 0)
2631	return VERR_EM_INTERPRETER; /* supervisor only */
2632
2633	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2634	if (!(u32Features & X86_CPUID_FEATURE_EDX_MSR))
2635	return VERR_EM_INTERPRETER; /* not supported */
2636
2637	switch (pRegFrame->ecx)
2638	{
2639	case MSR_IA32_APICBASE:
2640	rc = PDMApicGetBase(pVM, &val);
2641	AssertRC(rc);
2642	break;
2643
2644	case MSR_IA32_CR_PAT:
2645	val = pCtx->msrPAT;
2646	break;
2647
2648	case MSR_IA32_SYSENTER_CS:
2649	val = pCtx->SysEnter.cs;
2650	break;
2651
2652	case MSR_IA32_SYSENTER_EIP:
2653	val = pCtx->SysEnter.eip;
2654	break;
2655
2656	case MSR_IA32_SYSENTER_ESP:
2657	val = pCtx->SysEnter.esp;
2658	break;
2659
2660	case MSR_K6_EFER:
2661	val = pCtx->msrEFER;
2662	break;
2663
2664	case MSR_K8_SF_MASK:
2665	val = pCtx->msrSFMASK;
2666	break;
2667
2668	case MSR_K6_STAR:
2669	val = pCtx->msrSTAR;
2670	break;
2671
2672	case MSR_K8_LSTAR:
2673	val = pCtx->msrLSTAR;
2674	break;
2675
2676	case MSR_K8_CSTAR:
2677	val = pCtx->msrCSTAR;
2678	break;
2679
2680	case MSR_K8_FS_BASE:
2681	val = pCtx->fsHid.u64Base;
2682	break;
2683
2684	case MSR_K8_GS_BASE:
2685	val = pCtx->gsHid.u64Base;
2686	break;
2687
2688	case MSR_K8_KERNEL_GS_BASE:
2689	val = pCtx->msrKERNELGSBASE;
2690	break;
2691
2692	case MSR_K8_TSC_AUX:
2693	val = CPUMGetGuestMsr(pVM, MSR_K8_TSC_AUX);
2694	break;
2695
2696	#if 0 /def IN_RING0 /
2697	case MSR_IA32_PLATFORM_ID:
2698	case MSR_IA32_BIOS_SIGN_ID:
2699	if (CPUMGetCPUVendor(pVM) == CPUMCPUVENDOR_INTEL)
2700	{
2701	/* Available since the P6 family. VT-x implies that this feature is present. */
2702	if (pRegFrame->ecx == MSR_IA32_PLATFORM_ID)
2703	val = ASMRdMsr(MSR_IA32_PLATFORM_ID);
2704	else
2705	if (pRegFrame->ecx == MSR_IA32_BIOS_SIGN_ID)
2706	val = ASMRdMsr(MSR_IA32_BIOS_SIGN_ID);
2707	break;
2708	}
2709	/* no break */
2710	#endif
2711	default:
2712	/* In X2APIC specification this range is reserved for APIC control. */
2713	if ((pRegFrame->ecx >= MSR_IA32_APIC_START) && (pRegFrame->ecx < MSR_IA32_APIC_END))
2714	rc = PDMApicReadMSR(pVM, VMMGetCpuId(pVM), pRegFrame->ecx, &val);
2715	else
2716	/* We should actually trigger a #GP here, but don't as that might cause more trouble. */
2717	val = 0;
2718	break;
2719	}
2720	LogFlow(("EMInterpretRdmsr %s (%x) -> val=%RX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx, val));
2721	if (rc == VINF_SUCCESS)
2722	{
2723	pRegFrame->rax = (uint32_t) val;
2724	pRegFrame->rdx = (uint32_t) (val >> 32ULL);
2725	}
2726	return rc;
2727	}
2728
2729
2730	/**
2731	* RDMSR Emulation.
2732	*/
2733	static int emInterpretRdmsr(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2734	{
2735	/* Note: the Intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
2736	Assert(!(pCpu->prefix & PREFIX_REX));
2737	return EMInterpretRdmsr(pVM, pRegFrame);
2738	}
2739
2740
2741	/**
2742	* Interpret WRMSR
2743	*
2744	* @returns VBox status code.
2745	* @param pVM The VM handle.
2746	* @param pRegFrame The register frame.
2747	*/
2748	VMMDECL(int) EMInterpretWrmsr(PVM pVM, PCPUMCTXCORE pRegFrame)
2749	{
2750	uint32_t u32Dummy, u32Features, cpl;
2751	uint64_t val;
2752	CPUMCTX *pCtx;
2753
2754	/* Note: works the same in 32 and 64 bits modes. */
2755	pCtx = CPUMQueryGuestCtxPtr(pVM);
2756
2757	/* Get the current privilege level. */
2758	cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2759	if (cpl != 0)
2760	return VERR_EM_INTERPRETER; /* supervisor only */
2761
2762	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2763	if (!(u32Features & X86_CPUID_FEATURE_EDX_MSR))
2764	return VERR_EM_INTERPRETER; /* not supported */
2765
2766	val = RT_MAKE_U64(pRegFrame->eax, pRegFrame->edx);
2767	LogFlow(("EMInterpretWrmsr %s (%x) val=%RX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx, val));
2768	switch (pRegFrame->ecx)
2769	{
2770	case MSR_IA32_APICBASE:
2771	{
2772	int rc = PDMApicSetBase(pVM, val);
2773	AssertRC(rc);
2774	break;
2775	}
2776
2777	case MSR_IA32_CR_PAT:
2778	pCtx->msrPAT = val;
2779	break;
2780
2781	case MSR_IA32_SYSENTER_CS:
2782	pCtx->SysEnter.cs = val & 0xffff; /* 16 bits selector */
2783	break;
2784
2785	case MSR_IA32_SYSENTER_EIP:
2786	pCtx->SysEnter.eip = val;
2787	break;
2788
2789	case MSR_IA32_SYSENTER_ESP:
2790	pCtx->SysEnter.esp = val;
2791	break;
2792
2793	case MSR_K6_EFER:
2794	{
2795	uint64_t uMask = 0;
2796	uint64_t oldval = pCtx->msrEFER;
2797
2798	/* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
2799	CPUMGetGuestCpuId(pVM, 0x80000001, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2800	if (u32Features & X86_CPUID_AMD_FEATURE_EDX_NX)
2801	uMask \|= MSR_K6_EFER_NXE;
2802	if (u32Features & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE)
2803	uMask \|= MSR_K6_EFER_LME;
2804	if (u32Features & X86_CPUID_AMD_FEATURE_EDX_SEP)
2805	uMask \|= MSR_K6_EFER_SCE;
2806	if (u32Features & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
2807	uMask \|= MSR_K6_EFER_FFXSR;
2808
2809	/* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
2810	if ( ((pCtx->msrEFER & MSR_K6_EFER_LME) != (val & uMask & MSR_K6_EFER_LME))
2811	&& (pCtx->cr0 & X86_CR0_PG))
2812	{
2813	AssertMsgFailed(("Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
2814	return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
2815	}
2816
2817	/* There are a few more: e.g. MSR_K6_EFER_LMSLE */
2818	AssertMsg(!(val & ~(MSR_K6_EFER_NXE\|MSR_K6_EFER_LME\|MSR_K6_EFER_LMA /* ignored anyway */ \|MSR_K6_EFER_SCE\|MSR_K6_EFER_FFXSR)), ("Unexpected value %RX64\n", val));
2819	pCtx->msrEFER = (pCtx->msrEFER & ~uMask) \| (val & uMask);
2820
2821	/* AMD64 Architecture Programmer's Manual: 15.15 TLB Control; flush the TLB if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
2822	if ((oldval & (MSR_K6_EFER_NXE\|MSR_K6_EFER_LME\|MSR_K6_EFER_LMA)) != (pCtx->msrEFER & (MSR_K6_EFER_NXE\|MSR_K6_EFER_LME\|MSR_K6_EFER_LMA)))
2823	HWACCMFlushTLB(pVM);
2824
2825	break;
2826	}
2827
2828	case MSR_K8_SF_MASK:
2829	pCtx->msrSFMASK = val;
2830	break;
2831
2832	case MSR_K6_STAR:
2833	pCtx->msrSTAR = val;
2834	break;
2835
2836	case MSR_K8_LSTAR:
2837	pCtx->msrLSTAR = val;
2838	break;
2839
2840	case MSR_K8_CSTAR:
2841	pCtx->msrCSTAR = val;
2842	break;
2843
2844	case MSR_K8_FS_BASE:
2845	pCtx->fsHid.u64Base = val;
2846	break;
2847
2848	case MSR_K8_GS_BASE:
2849	pCtx->gsHid.u64Base = val;
2850	break;
2851
2852	case MSR_K8_KERNEL_GS_BASE:
2853	pCtx->msrKERNELGSBASE = val;
2854	break;
2855
2856	case MSR_K8_TSC_AUX:
2857	CPUMSetGuestMsr(pVM, MSR_K8_TSC_AUX, val);
2858	break;
2859
2860	default:
2861	/* In X2APIC specification this range is reserved for APIC control. */
2862	if ((pRegFrame->ecx >= MSR_IA32_APIC_START) && (pRegFrame->ecx < MSR_IA32_APIC_END))
2863	return PDMApicWriteMSR(pVM, VMMGetCpuId(pVM), pRegFrame->ecx, val);
2864
2865	/* We should actually trigger a #GP here, but don't as that might cause more trouble. */
2866	break;
2867	}
2868	return VINF_SUCCESS;
2869	}
2870
2871
2872	/**
2873	* WRMSR Emulation.
2874	*/
2875	static int emInterpretWrmsr(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2876	{
2877	return EMInterpretWrmsr(pVM, pRegFrame);
2878	}
2879
2880
2881	/**
2882	* Internal worker.
2883	* @copydoc EMInterpretInstructionCPU
2884	*/
2885	DECLINLINE(int) emInterpretInstructionCPU(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2886	{
2887	Assert(pcbSize);
2888	*pcbSize = 0;
2889
2890	/*
2891	* Only supervisor guest code!!
2892	* And no complicated prefixes.
2893	*/
2894	/* Get the current privilege level. */
2895	uint32_t cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2896	if ( cpl != 0
2897	&& pCpu->pCurInstr->opcode != OP_RDTSC) /* rdtsc requires emulation in ring 3 as well */
2898	{
2899	Log(("WARNING: refusing instruction emulation for user-mode code!!\n"));
2900	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedUserMode));
2901	return VERR_EM_INTERPRETER;
2902	}
2903
2904	#ifdef IN_RC
2905	if ( (pCpu->prefix & (PREFIX_REPNE \| PREFIX_REP))
2906	\|\| ( (pCpu->prefix & PREFIX_LOCK)
2907	&& pCpu->pCurInstr->opcode != OP_CMPXCHG
2908	&& pCpu->pCurInstr->opcode != OP_CMPXCHG8B
2909	&& pCpu->pCurInstr->opcode != OP_XADD
2910	&& pCpu->pCurInstr->opcode != OP_OR
2911	&& pCpu->pCurInstr->opcode != OP_BTR
2912	)
2913	)
2914	#else
2915	if ( (pCpu->prefix & PREFIX_REPNE)
2916	\|\| ( (pCpu->prefix & PREFIX_REP)
2917	&& pCpu->pCurInstr->opcode != OP_STOSWD
2918	)
2919	\|\| ( (pCpu->prefix & PREFIX_LOCK)
2920	&& pCpu->pCurInstr->opcode != OP_OR
2921	&& pCpu->pCurInstr->opcode != OP_BTR
2922	&& pCpu->pCurInstr->opcode != OP_CMPXCHG
2923	&& pCpu->pCurInstr->opcode != OP_CMPXCHG8B
2924	)
2925	)
2926	#endif
2927	{
2928	//Log(("EMInterpretInstruction: wrong prefix!!\n"));
2929	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedPrefix));
2930	return VERR_EM_INTERPRETER;
2931	}
2932
2933	#if HC_ARCH_BITS == 32
2934	/*
2935	* Unable to emulate most >4 bytes accesses in 32 bits mode.
2936	* Whitelisted instructions are safe.
2937	*/
2938	if ( pCpu->param1.size > 4
2939	&& CPUMIsGuestIn64BitCode(pVM, pRegFrame))
2940	{
2941	uint32_t uOpCode = pCpu->pCurInstr->opcode;
2942	if ( uOpCode != OP_STOSWD
2943	&& uOpCode != OP_MOV
2944	&& uOpCode != OP_CMPXCHG8B
2945	&& uOpCode != OP_XCHG
2946	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL_IN_R0
2947	&& uOpCode != OP_CMPXCHG /* solaris */
2948	&& uOpCode != OP_AND /* windows */
2949	&& uOpCode != OP_OR /* windows */
2950	&& uOpCode != OP_XOR /* because we can */
2951	&& uOpCode != OP_ADD /* windows (dripple) */
2952	&& uOpCode != OP_ADC /* because we can */
2953	&& uOpCode != OP_SUB /* because we can */
2954	/** @todo OP_BTS or is that a different kind of failure? */
2955	# endif
2956	)
2957	{
2958	# ifdef VBOX_WITH_STATISTICS
2959	switch (pCpu->pCurInstr->opcode)
2960	{
2961	# define INTERPRET_FAILED_CASE(opcode, Instr) \
2962	case opcode: STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); break;
2963	INTERPRET_FAILED_CASE(OP_XCHG,Xchg);
2964	INTERPRET_FAILED_CASE(OP_DEC,Dec);
2965	INTERPRET_FAILED_CASE(OP_INC,Inc);
2966	INTERPRET_FAILED_CASE(OP_POP,Pop);
2967	INTERPRET_FAILED_CASE(OP_OR, Or);
2968	INTERPRET_FAILED_CASE(OP_XOR,Xor);
2969	INTERPRET_FAILED_CASE(OP_AND,And);
2970	INTERPRET_FAILED_CASE(OP_MOV,Mov);
2971	INTERPRET_FAILED_CASE(OP_STOSWD,StosWD);
2972	INTERPRET_FAILED_CASE(OP_INVLPG,InvlPg);
2973	INTERPRET_FAILED_CASE(OP_CPUID,CpuId);
2974	INTERPRET_FAILED_CASE(OP_MOV_CR,MovCRx);
2975	INTERPRET_FAILED_CASE(OP_MOV_DR,MovDRx);
2976	INTERPRET_FAILED_CASE(OP_LLDT,LLdt);
2977	INTERPRET_FAILED_CASE(OP_LIDT,LIdt);
2978	INTERPRET_FAILED_CASE(OP_LGDT,LGdt);
2979	INTERPRET_FAILED_CASE(OP_LMSW,Lmsw);
2980	INTERPRET_FAILED_CASE(OP_CLTS,Clts);
2981	INTERPRET_FAILED_CASE(OP_MONITOR,Monitor);
2982	INTERPRET_FAILED_CASE(OP_MWAIT,MWait);
2983	INTERPRET_FAILED_CASE(OP_RDMSR,Rdmsr);
2984	INTERPRET_FAILED_CASE(OP_WRMSR,Wrmsr);
2985	INTERPRET_FAILED_CASE(OP_ADD,Add);
2986	INTERPRET_FAILED_CASE(OP_SUB,Sub);
2987	INTERPRET_FAILED_CASE(OP_ADC,Adc);
2988	INTERPRET_FAILED_CASE(OP_BTR,Btr);
2989	INTERPRET_FAILED_CASE(OP_BTS,Bts);
2990	INTERPRET_FAILED_CASE(OP_BTC,Btc);
2991	INTERPRET_FAILED_CASE(OP_RDTSC,Rdtsc);
2992	INTERPRET_FAILED_CASE(OP_CMPXCHG, CmpXchg);
2993	INTERPRET_FAILED_CASE(OP_STI, Sti);
2994	INTERPRET_FAILED_CASE(OP_XADD,XAdd);
2995	INTERPRET_FAILED_CASE(OP_CMPXCHG8B,CmpXchg8b);
2996	INTERPRET_FAILED_CASE(OP_HLT, Hlt);
2997	INTERPRET_FAILED_CASE(OP_IRET,Iret);
2998	INTERPRET_FAILED_CASE(OP_WBINVD,WbInvd);
2999	INTERPRET_FAILED_CASE(OP_MOVNTPS,MovNTPS);
3000	# undef INTERPRET_FAILED_CASE
3001	default:
3002	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedMisc));
3003	break;
3004	}
3005	# endif /* VBOX_WITH_STATISTICS */
3006	return VERR_EM_INTERPRETER;
3007	}
3008	}
3009	#endif
3010
3011	int rc;
3012	#if (defined(VBOX_STRICT) \|\| defined(LOG_ENABLED))
3013	LogFlow(("emInterpretInstructionCPU %s\n", emGetMnemonic(pCpu)));
3014	#endif
3015	switch (pCpu->pCurInstr->opcode)
3016	{
3017	# define INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
3018	case opcode:\
3019	if (pCpu->prefix & PREFIX_LOCK) \
3020	rc = emInterpretLock##InstrFn(pVM, pCpu, pRegFrame, pvFault, pcbSize, pfnEmulateLock); \
3021	else \
3022	rc = emInterpret##InstrFn(pVM, pCpu, pRegFrame, pvFault, pcbSize, pfnEmulate); \
3023	if (RT_SUCCESS(rc)) \
3024	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3025	else \
3026	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3027	return rc
3028	#define INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate) \
3029	case opcode:\
3030	rc = emInterpret##InstrFn(pVM, pCpu, pRegFrame, pvFault, pcbSize, pfnEmulate); \
3031	if (RT_SUCCESS(rc)) \
3032	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3033	else \
3034	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3035	return rc
3036
3037	#define INTERPRET_CASE_EX_PARAM2(opcode, Instr, InstrFn, pfnEmulate) \
3038	INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate)
3039	#define INTERPRET_CASE_EX_LOCK_PARAM2(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
3040	INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock)
3041
3042	#define INTERPRET_CASE(opcode, Instr) \
3043	case opcode:\
3044	rc = emInterpret##Instr(pVM, pCpu, pRegFrame, pvFault, pcbSize); \
3045	if (RT_SUCCESS(rc)) \
3046	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3047	else \
3048	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3049	return rc
3050
3051	#define INTERPRET_CASE_EX_DUAL_PARAM2(opcode, Instr, InstrFn) \
3052	case opcode:\
3053	rc = emInterpret##InstrFn(pVM, pCpu, pRegFrame, pvFault, pcbSize); \
3054	if (RT_SUCCESS(rc)) \
3055	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3056	else \
3057	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3058	return rc
3059
3060	#define INTERPRET_STAT_CASE(opcode, Instr) \
3061	case opcode: STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); return VERR_EM_INTERPRETER;
3062
3063	INTERPRET_CASE(OP_XCHG,Xchg);
3064	INTERPRET_CASE_EX_PARAM2(OP_DEC,Dec, IncDec, EMEmulateDec);
3065	INTERPRET_CASE_EX_PARAM2(OP_INC,Inc, IncDec, EMEmulateInc);
3066	INTERPRET_CASE(OP_POP,Pop);
3067	INTERPRET_CASE_EX_LOCK_PARAM3(OP_OR, Or, OrXorAnd, EMEmulateOr, EMEmulateLockOr);
3068	INTERPRET_CASE_EX_PARAM3(OP_XOR,Xor, OrXorAnd, EMEmulateXor);
3069	INTERPRET_CASE_EX_PARAM3(OP_AND,And, OrXorAnd, EMEmulateAnd);
3070	INTERPRET_CASE(OP_MOV,Mov);
3071	#ifndef IN_RC
3072	INTERPRET_CASE(OP_STOSWD,StosWD);
3073	#endif
3074	INTERPRET_CASE(OP_INVLPG,InvlPg);
3075	INTERPRET_CASE(OP_CPUID,CpuId);
3076	INTERPRET_CASE(OP_MOV_CR,MovCRx);
3077	INTERPRET_CASE(OP_MOV_DR,MovDRx);
3078	INTERPRET_CASE(OP_LLDT,LLdt);
3079	#ifdef IN_RING0
3080	INTERPRET_CASE_EX_DUAL_PARAM2(OP_LIDT, LIdt, LIGdt);
3081	INTERPRET_CASE_EX_DUAL_PARAM2(OP_LGDT, LGdt, LIGdt);
3082	#endif
3083	INTERPRET_CASE(OP_LMSW,Lmsw);
3084	INTERPRET_CASE(OP_CLTS,Clts);
3085	INTERPRET_CASE(OP_MONITOR, Monitor);
3086	INTERPRET_CASE(OP_MWAIT, MWait);
3087	INTERPRET_CASE(OP_RDMSR, Rdmsr);
3088	INTERPRET_CASE(OP_WRMSR, Wrmsr);
3089	INTERPRET_CASE_EX_PARAM3(OP_ADD,Add, AddSub, EMEmulateAdd);
3090	INTERPRET_CASE_EX_PARAM3(OP_SUB,Sub, AddSub, EMEmulateSub);
3091	INTERPRET_CASE(OP_ADC,Adc);
3092	INTERPRET_CASE_EX_LOCK_PARAM2(OP_BTR,Btr, BitTest, EMEmulateBtr, EMEmulateLockBtr);
3093	INTERPRET_CASE_EX_PARAM2(OP_BTS,Bts, BitTest, EMEmulateBts);
3094	INTERPRET_CASE_EX_PARAM2(OP_BTC,Btc, BitTest, EMEmulateBtc);
3095	INTERPRET_CASE(OP_RDTSC,Rdtsc);
3096	INTERPRET_CASE(OP_CMPXCHG, CmpXchg);
3097	#ifdef IN_RC
3098	INTERPRET_CASE(OP_STI,Sti);
3099	INTERPRET_CASE(OP_XADD, XAdd);
3100	#endif
3101	INTERPRET_CASE(OP_CMPXCHG8B, CmpXchg8b);
3102	INTERPRET_CASE(OP_HLT,Hlt);
3103	INTERPRET_CASE(OP_IRET,Iret);
3104	INTERPRET_CASE(OP_WBINVD,WbInvd);
3105	#ifdef VBOX_WITH_STATISTICS
3106	#ifndef IN_RC
3107	INTERPRET_STAT_CASE(OP_XADD, XAdd);
3108	#endif
3109	INTERPRET_STAT_CASE(OP_MOVNTPS,MovNTPS);
3110	#endif
3111	default:
3112	Log3(("emInterpretInstructionCPU: opcode=%d\n", pCpu->pCurInstr->opcode));
3113	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedMisc));
3114	return VERR_EM_INTERPRETER;
3115	#undef INTERPRET_CASE_EX_PARAM2
3116	#undef INTERPRET_STAT_CASE
3117	#undef INTERPRET_CASE_EX
3118	#undef INTERPRET_CASE
3119	}
3120	AssertFailed();
3121	return VERR_INTERNAL_ERROR;
3122	}
3123
3124
3125	/**
3126	* Sets the PC for which interrupts should be inhibited.
3127	*
3128	* @param pVM The VM handle.
3129	* @param PC The PC.
3130	*/
3131	VMMDECL(void) EMSetInhibitInterruptsPC(PVM pVM, RTGCUINTPTR PC)
3132	{
3133	pVM->em.s.GCPtrInhibitInterrupts = PC;
3134	VM_FF_SET(pVM, VM_FF_INHIBIT_INTERRUPTS);
3135	}
3136
3137
3138	/**
3139	* Gets the PC for which interrupts should be inhibited.
3140	*
3141	* There are a few instructions which inhibits or delays interrupts
3142	* for the instruction following them. These instructions are:
3143	* - STI
3144	* - MOV SS, r/m16
3145	* - POP SS
3146	*
3147	* @returns The PC for which interrupts should be inhibited.
3148	* @param pVM VM handle.
3149	*
3150	*/
3151	VMMDECL(RTGCUINTPTR) EMGetInhibitInterruptsPC(PVM pVM)
3152	{
3153	return pVM->em.s.GCPtrInhibitInterrupts;
3154	}
3155

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source: vbox/trunk/src/VBox/VMM/VMMAll/EMAll.cpp@ 15420

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