EMAll.cpp@ 17212

Last change on this file since 17212 was 17106, checked in by vboxsync, 16 years ago
VMM,REM: Removed the single page limitation on the TSS monitoring and going over the interrupt redirection bitmap monitoring.
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File size: 106.3 KB

Line
1	/* $Id: EMAll.cpp 17106 2009-02-25 00:35:15Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor(/Manager) - All contexts
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_EM
26	#include <VBox/em.h>
27	#include <VBox/mm.h>
28	#include <VBox/selm.h>
29	#include <VBox/patm.h>
30	#include <VBox/csam.h>
31	#include <VBox/pgm.h>
32	#include <VBox/iom.h>
33	#include <VBox/stam.h>
34	#include "EMInternal.h"
35	#include <VBox/vm.h>
36	#include <VBox/vmm.h>
37	#include <VBox/hwaccm.h>
38	#include <VBox/tm.h>
39	#include <VBox/pdmapi.h>
40
41	#include <VBox/param.h>
42	#include <VBox/err.h>
43	#include <VBox/dis.h>
44	#include <VBox/disopcode.h>
45	#include <VBox/log.h>
46	#include <iprt/assert.h>
47	#include <iprt/asm.h>
48	#include <iprt/string.h>
49
50
51	/*******************************************************************************
52	* Defined Constants And Macros *
53	*******************************************************************************/
54	/** @def EM_ASSERT_FAULT_RETURN
55	* Safety check.
56	*
57	* Could in theory misfire on a cross page boundary access...
58	*
59	* Currently disabled because the CSAM (+ PATM) patch monitoring occasionally
60	* turns up an alias page instead of the original faulting one and annoying the
61	* heck out of anyone running a debug build. See @bugref{2609} and @bugref{1931}.
62	*/
63	#if 0
64	# define EM_ASSERT_FAULT_RETURN(expr, rc) AssertReturn(expr, rc)
65	#else
66	# define EM_ASSERT_FAULT_RETURN(expr, rc) do { } while (0)
67	#endif
68
69
70	/*******************************************************************************
71	* Internal Functions *
72	*******************************************************************************/
73	DECLINLINE(int) emInterpretInstructionCPU(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize);
74
75
76
77	/**
78	* Get the current execution manager status.
79	*
80	* @returns Current status.
81	*/
82	VMMDECL(EMSTATE) EMGetState(PVM pVM)
83	{
84	return pVM->em.s.enmState;
85	}
86
87	#ifndef IN_RC
88
89	/**
90	* Read callback for disassembly function; supports reading bytes that cross a page boundary
91	*
92	* @returns VBox status code.
93	* @param pSrc GC source pointer
94	* @param pDest HC destination pointer
95	* @param cb Number of bytes to read
96	* @param dwUserdata Callback specific user data (pCpu)
97	*
98	*/
99	DECLCALLBACK(int) EMReadBytes(RTUINTPTR pSrc, uint8_t pDest, unsigned cb, void pvUserdata)
100	{
101	DISCPUSTATE pCpu = (DISCPUSTATE )pvUserdata;
102	PVM pVM = (PVM)pCpu->apvUserData[0];
103	# ifdef IN_RING0
104	int rc = PGMPhysSimpleReadGCPtr(pVM, pDest, pSrc, cb);
105	AssertMsgRC(rc, ("PGMPhysSimpleReadGCPtr failed for pSrc=%RGv cb=%x\n", pSrc, cb));
106	# else /* IN_RING3 */
107	if (!PATMIsPatchGCAddr(pVM, pSrc))
108	{
109	int rc = PGMPhysSimpleReadGCPtr(pVM, pDest, pSrc, cb);
110	AssertRC(rc);
111	}
112	else
113	{
114	for (uint32_t i = 0; i < cb; i++)
115	{
116	uint8_t opcode;
117	if (RT_SUCCESS(PATMR3QueryOpcode(pVM, (RTGCPTR)pSrc + i, &opcode)))
118	{
119	*(pDest+i) = opcode;
120	}
121	}
122	}
123	# endif /* IN_RING3 */
124	return VINF_SUCCESS;
125	}
126
127	DECLINLINE(int) emDisCoreOne(PVM pVM, DISCPUSTATE pCpu, RTGCUINTPTR InstrGC, uint32_t pOpsize)
128	{
129	return DISCoreOneEx(InstrGC, pCpu->mode, EMReadBytes, pVM, pCpu, pOpsize);
130	}
131
132	#else /* IN_RC */
133
134	DECLINLINE(int) emDisCoreOne(PVM pVM, DISCPUSTATE pCpu, RTGCUINTPTR InstrGC, uint32_t pOpsize)
135	{
136	return DISCoreOne(pCpu, InstrGC, pOpsize);
137	}
138
139	#endif /* IN_RC */
140
141
142	/**
143	* Disassembles one instruction.
144	*
145	* @param pVM The VM handle.
146	* @param pCtxCore The context core (used for both the mode and instruction).
147	* @param pCpu Where to return the parsed instruction info.
148	* @param pcbInstr Where to return the instruction size. (optional)
149	*/
150	VMMDECL(int) EMInterpretDisasOne(PVM pVM, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, unsigned *pcbInstr)
151	{
152	RTGCPTR GCPtrInstr;
153	int rc = SELMToFlatEx(pVM, DIS_SELREG_CS, pCtxCore, pCtxCore->rip, 0, &GCPtrInstr);
154	if (RT_FAILURE(rc))
155	{
156	Log(("EMInterpretDisasOne: Failed to convert %RTsel:%RGv (cpl=%d) - rc=%Rrc !!\n",
157	pCtxCore->cs, (RTGCPTR)pCtxCore->rip, pCtxCore->ss & X86_SEL_RPL, rc));
158	return rc;
159	}
160	return EMInterpretDisasOneEx(pVM, (RTGCUINTPTR)GCPtrInstr, pCtxCore, pCpu, pcbInstr);
161	}
162
163
164	/**
165	* Disassembles one instruction.
166	*
167	* This is used by internally by the interpreter and by trap/access handlers.
168	*
169	* @param pVM The VM handle.
170	* @param GCPtrInstr The flat address of the instruction.
171	* @param pCtxCore The context core (used to determine the cpu mode).
172	* @param pCpu Where to return the parsed instruction info.
173	* @param pcbInstr Where to return the instruction size. (optional)
174	*/
175	VMMDECL(int) EMInterpretDisasOneEx(PVM pVM, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, unsigned *pcbInstr)
176	{
177	int rc = DISCoreOneEx(GCPtrInstr, SELMGetCpuModeFromSelector(pVM, pCtxCore->eflags, pCtxCore->cs, (PCPUMSELREGHID)&pCtxCore->csHid),
178	#ifdef IN_RC
179	NULL, NULL,
180	#else
181	EMReadBytes, pVM,
182	#endif
183	pCpu, pcbInstr);
184	if (RT_SUCCESS(rc))
185	return VINF_SUCCESS;
186	AssertMsgFailed(("DISCoreOne failed to GCPtrInstr=%RGv rc=%Rrc\n", GCPtrInstr, rc));
187	return VERR_INTERNAL_ERROR;
188	}
189
190
191	/**
192	* Interprets the current instruction.
193	*
194	* @returns VBox status code.
195	* @retval VINF_* Scheduling instructions.
196	* @retval VERR_EM_INTERPRETER Something we can't cope with.
197	* @retval VERR_* Fatal errors.
198	*
199	* @param pVM The VM handle.
200	* @param pRegFrame The register frame.
201	* Updates the EIP if an instruction was executed successfully.
202	* @param pvFault The fault address (CR2).
203	* @param pcbSize Size of the write (if applicable).
204	*
205	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
206	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
207	* to worry about e.g. invalid modrm combinations (!)
208	*/
209	VMMDECL(int) EMInterpretInstruction(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
210	{
211	RTGCPTR pbCode;
212
213	LogFlow(("EMInterpretInstruction %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
214	int rc = SELMToFlatEx(pVM, DIS_SELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
215	if (RT_SUCCESS(rc))
216	{
217	uint32_t cbOp;
218	DISCPUSTATE Cpu;
219	Cpu.mode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
220	rc = emDisCoreOne(pVM, &Cpu, (RTGCUINTPTR)pbCode, &cbOp);
221	if (RT_SUCCESS(rc))
222	{
223	Assert(cbOp == Cpu.opsize);
224	rc = EMInterpretInstructionCPU(pVM, &Cpu, pRegFrame, pvFault, pcbSize);
225	if (RT_SUCCESS(rc))
226	{
227	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
228	}
229	return rc;
230	}
231	}
232	return VERR_EM_INTERPRETER;
233	}
234
235
236	/**
237	* Interprets the current instruction using the supplied DISCPUSTATE structure.
238	*
239	* EIP is NOT updated!
240	*
241	* @returns VBox status code.
242	* @retval VINF_* Scheduling instructions. When these are returned, it
243	* starts to get a bit tricky to know whether code was
244	* executed or not... We'll address this when it becomes a problem.
245	* @retval VERR_EM_INTERPRETER Something we can't cope with.
246	* @retval VERR_* Fatal errors.
247	*
248	* @param pVM The VM handle.
249	* @param pCpu The disassembler cpu state for the instruction to be interpreted.
250	* @param pRegFrame The register frame. EIP is NOT changed!
251	* @param pvFault The fault address (CR2).
252	* @param pcbSize Size of the write (if applicable).
253	*
254	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
255	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
256	* to worry about e.g. invalid modrm combinations (!)
257	*
258	* @todo At this time we do NOT check if the instruction overwrites vital information.
259	* Make sure this can't happen!! (will add some assertions/checks later)
260	*/
261	VMMDECL(int) EMInterpretInstructionCPU(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
262	{
263	STAM_PROFILE_START(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Emulate), a);
264	int rc = emInterpretInstructionCPU(pVM, pCpu, pRegFrame, pvFault, pcbSize);
265	STAM_PROFILE_STOP(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Emulate), a);
266	if (RT_SUCCESS(rc))
267	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InterpretSucceeded));
268	else
269	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InterpretFailed));
270	return rc;
271	}
272
273
274	/**
275	* Interpret a port I/O instruction.
276	*
277	* @returns VBox status code suitable for scheduling.
278	* @param pVM The VM handle.
279	* @param pCtxCore The context core. This will be updated on successful return.
280	* @param pCpu The instruction to interpret.
281	* @param cbOp The size of the instruction.
282	* @remark This may raise exceptions.
283	*/
284	VMMDECL(int) EMInterpretPortIO(PVM pVM, PCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, uint32_t cbOp)
285	{
286	/*
287	* Hand it on to IOM.
288	*/
289	#ifdef IN_RC
290	int rc = IOMGCIOPortHandler(pVM, pCtxCore, pCpu);
291	if (IOM_SUCCESS(rc))
292	pCtxCore->rip += cbOp;
293	return rc;
294	#else
295	AssertReleaseMsgFailed(("not implemented\n"));
296	return VERR_NOT_IMPLEMENTED;
297	#endif
298	}
299
300
301	DECLINLINE(int) emRamRead(PVM pVM, void *pDest, RTGCPTR GCSrc, uint32_t cb)
302	{
303	#ifdef IN_RC
304	int rc = MMGCRamRead(pVM, pDest, (void *)GCSrc, cb);
305	if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
306	return rc;
307	/*
308	* The page pool cache may end up here in some cases because it
309	* flushed one of the shadow mappings used by the trapping
310	* instruction and it either flushed the TLB or the CPU reused it.
311	*/
312	RTGCPHYS GCPhys;
313	rc = PGMPhysGCPtr2GCPhys(pVM, GCSrc, &GCPhys);
314	AssertRCReturn(rc, rc);
315	PGMPhysRead(pVM, GCPhys, pDest, cb);
316	return VINF_SUCCESS;
317	#else
318	return PGMPhysReadGCPtr(pVM, pDest, GCSrc, cb);
319	#endif
320	}
321
322
323	DECLINLINE(int) emRamWrite(PVM pVM, RTGCPTR GCDest, void *pSrc, uint32_t cb)
324	{
325	#ifdef IN_RC
326	int rc = MMGCRamWrite(pVM, (void *)GCDest, pSrc, cb);
327	if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
328	return rc;
329	/*
330	* The page pool cache may end up here in some cases because it
331	* flushed one of the shadow mappings used by the trapping
332	* instruction and it either flushed the TLB or the CPU reused it.
333	* We want to play safe here, verifying that we've got write
334	* access doesn't cost us much (see PGMPhysGCPtr2GCPhys()).
335	*/
336	uint64_t fFlags;
337	RTGCPHYS GCPhys;
338	rc = PGMGstGetPage(pVM, GCDest, &fFlags, &GCPhys);
339	if (RT_FAILURE(rc))
340	return rc;
341	if ( !(fFlags & X86_PTE_RW)
342	&& (CPUMGetGuestCR0(pVM) & X86_CR0_WP))
343	return VERR_ACCESS_DENIED;
344
345	PGMPhysWrite(pVM, GCPhys + ((RTGCUINTPTR)GCDest & PAGE_OFFSET_MASK), pSrc, cb);
346	return VINF_SUCCESS;
347
348	#else
349	return PGMPhysWriteGCPtr(pVM, GCDest, pSrc, cb);
350	#endif
351	}
352
353
354	/** Convert sel:addr to a flat GC address. */
355	DECLINLINE(RTGCPTR) emConvertToFlatAddr(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, POP_PARAMETER pParam, RTGCPTR pvAddr)
356	{
357	DIS_SELREG enmPrefixSeg = DISDetectSegReg(pCpu, pParam);
358	return SELMToFlat(pVM, enmPrefixSeg, pRegFrame, pvAddr);
359	}
360
361
362	#if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
363	/**
364	* Get the mnemonic for the disassembled instruction.
365	*
366	* GC/R0 doesn't include the strings in the DIS tables because
367	* of limited space.
368	*/
369	static const char *emGetMnemonic(PDISCPUSTATE pCpu)
370	{
371	switch (pCpu->pCurInstr->opcode)
372	{
373	case OP_XCHG: return "Xchg";
374	case OP_DEC: return "Dec";
375	case OP_INC: return "Inc";
376	case OP_POP: return "Pop";
377	case OP_OR: return "Or";
378	case OP_AND: return "And";
379	case OP_MOV: return "Mov";
380	case OP_INVLPG: return "InvlPg";
381	case OP_CPUID: return "CpuId";
382	case OP_MOV_CR: return "MovCRx";
383	case OP_MOV_DR: return "MovDRx";
384	case OP_LLDT: return "LLdt";
385	case OP_LGDT: return "LGdt";
386	case OP_LIDT: return "LGdt";
387	case OP_CLTS: return "Clts";
388	case OP_MONITOR: return "Monitor";
389	case OP_MWAIT: return "MWait";
390	case OP_RDMSR: return "Rdmsr";
391	case OP_WRMSR: return "Wrmsr";
392	case OP_ADD: return "Add";
393	case OP_ADC: return "Adc";
394	case OP_SUB: return "Sub";
395	case OP_SBB: return "Sbb";
396	case OP_RDTSC: return "Rdtsc";
397	case OP_STI: return "Sti";
398	case OP_XADD: return "XAdd";
399	case OP_HLT: return "Hlt";
400	case OP_IRET: return "Iret";
401	case OP_MOVNTPS: return "MovNTPS";
402	case OP_STOSWD: return "StosWD";
403	case OP_WBINVD: return "WbInvd";
404	case OP_XOR: return "Xor";
405	case OP_BTR: return "Btr";
406	case OP_BTS: return "Bts";
407	case OP_BTC: return "Btc";
408	case OP_LMSW: return "Lmsw";
409	case OP_SMSW: return "Smsw";
410	case OP_CMPXCHG: return pCpu->prefix & PREFIX_LOCK ? "Lock CmpXchg" : "CmpXchg";
411	case OP_CMPXCHG8B: return pCpu->prefix & PREFIX_LOCK ? "Lock CmpXchg8b" : "CmpXchg8b";
412
413	default:
414	Log(("Unknown opcode %d\n", pCpu->pCurInstr->opcode));
415	return "???";
416	}
417	}
418	#endif /* VBOX_STRICT \|\| LOG_ENABLED */
419
420
421	/**
422	* XCHG instruction emulation.
423	*/
424	static int emInterpretXchg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
425	{
426	OP_PARAMVAL param1, param2;
427
428	/* Source to make DISQueryParamVal read the register value - ugly hack */
429	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
430	if(RT_FAILURE(rc))
431	return VERR_EM_INTERPRETER;
432
433	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
434	if(RT_FAILURE(rc))
435	return VERR_EM_INTERPRETER;
436
437	#ifdef IN_RC
438	if (TRPMHasTrap(pVM))
439	{
440	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
441	{
442	#endif
443	RTGCPTR pParam1 = 0, pParam2 = 0;
444	uint64_t valpar1, valpar2;
445
446	AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
447	switch(param1.type)
448	{
449	case PARMTYPE_IMMEDIATE: /* register type is translated to this one too */
450	valpar1 = param1.val.val64;
451	break;
452
453	case PARMTYPE_ADDRESS:
454	pParam1 = (RTGCPTR)param1.val.val64;
455	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
456	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
457	rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
458	if (RT_FAILURE(rc))
459	{
460	AssertMsgFailed(("MMGCRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
461	return VERR_EM_INTERPRETER;
462	}
463	break;
464
465	default:
466	AssertFailed();
467	return VERR_EM_INTERPRETER;
468	}
469
470	switch(param2.type)
471	{
472	case PARMTYPE_ADDRESS:
473	pParam2 = (RTGCPTR)param2.val.val64;
474	pParam2 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param2, pParam2);
475	EM_ASSERT_FAULT_RETURN(pParam2 == pvFault, VERR_EM_INTERPRETER);
476	rc = emRamRead(pVM, &valpar2, pParam2, param2.size);
477	if (RT_FAILURE(rc))
478	{
479	AssertMsgFailed(("MMGCRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
480	}
481	break;
482
483	case PARMTYPE_IMMEDIATE:
484	valpar2 = param2.val.val64;
485	break;
486
487	default:
488	AssertFailed();
489	return VERR_EM_INTERPRETER;
490	}
491
492	/* Write value of parameter 2 to parameter 1 (reg or memory address) */
493	if (pParam1 == 0)
494	{
495	Assert(param1.type == PARMTYPE_IMMEDIATE); /* register actually */
496	switch(param1.size)
497	{
498	case 1: //special case for AH etc
499	rc = DISWriteReg8(pRegFrame, pCpu->param1.base.reg_gen, (uint8_t )valpar2); break;
500	case 2: rc = DISWriteReg16(pRegFrame, pCpu->param1.base.reg_gen, (uint16_t)valpar2); break;
501	case 4: rc = DISWriteReg32(pRegFrame, pCpu->param1.base.reg_gen, (uint32_t)valpar2); break;
502	case 8: rc = DISWriteReg64(pRegFrame, pCpu->param1.base.reg_gen, valpar2); break;
503	default: AssertFailedReturn(VERR_EM_INTERPRETER);
504	}
505	if (RT_FAILURE(rc))
506	return VERR_EM_INTERPRETER;
507	}
508	else
509	{
510	rc = emRamWrite(pVM, pParam1, &valpar2, param1.size);
511	if (RT_FAILURE(rc))
512	{
513	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
514	return VERR_EM_INTERPRETER;
515	}
516	}
517
518	/* Write value of parameter 1 to parameter 2 (reg or memory address) */
519	if (pParam2 == 0)
520	{
521	Assert(param2.type == PARMTYPE_IMMEDIATE); /* register actually */
522	switch(param2.size)
523	{
524	case 1: //special case for AH etc
525	rc = DISWriteReg8(pRegFrame, pCpu->param2.base.reg_gen, (uint8_t )valpar1); break;
526	case 2: rc = DISWriteReg16(pRegFrame, pCpu->param2.base.reg_gen, (uint16_t)valpar1); break;
527	case 4: rc = DISWriteReg32(pRegFrame, pCpu->param2.base.reg_gen, (uint32_t)valpar1); break;
528	case 8: rc = DISWriteReg64(pRegFrame, pCpu->param2.base.reg_gen, valpar1); break;
529	default: AssertFailedReturn(VERR_EM_INTERPRETER);
530	}
531	if (RT_FAILURE(rc))
532	return VERR_EM_INTERPRETER;
533	}
534	else
535	{
536	rc = emRamWrite(pVM, pParam2, &valpar1, param2.size);
537	if (RT_FAILURE(rc))
538	{
539	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
540	return VERR_EM_INTERPRETER;
541	}
542	}
543
544	*pcbSize = param2.size;
545	return VINF_SUCCESS;
546	#ifdef IN_RC
547	}
548	}
549	#endif
550	return VERR_EM_INTERPRETER;
551	}
552
553
554	/**
555	* INC and DEC emulation.
556	*/
557	static int emInterpretIncDec(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
558	PFNEMULATEPARAM2 pfnEmulate)
559	{
560	OP_PARAMVAL param1;
561
562	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
563	if(RT_FAILURE(rc))
564	return VERR_EM_INTERPRETER;
565
566	#ifdef IN_RC
567	if (TRPMHasTrap(pVM))
568	{
569	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
570	{
571	#endif
572	RTGCPTR pParam1 = 0;
573	uint64_t valpar1;
574
575	if (param1.type == PARMTYPE_ADDRESS)
576	{
577	pParam1 = (RTGCPTR)param1.val.val64;
578	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
579	#ifdef IN_RC
580	/* Safety check (in theory it could cross a page boundary and fault there though) */
581	AssertReturn(pParam1 == pvFault, VERR_EM_INTERPRETER);
582	#endif
583	rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
584	if (RT_FAILURE(rc))
585	{
586	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
587	return VERR_EM_INTERPRETER;
588	}
589	}
590	else
591	{
592	AssertFailed();
593	return VERR_EM_INTERPRETER;
594	}
595
596	uint32_t eflags;
597
598	eflags = pfnEmulate(&valpar1, param1.size);
599
600	/* Write result back */
601	rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
602	if (RT_FAILURE(rc))
603	{
604	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
605	return VERR_EM_INTERPRETER;
606	}
607
608	/* Update guest's eflags and finish. */
609	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
610	\| (eflags & (X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
611
612	/* All done! */
613	*pcbSize = param1.size;
614	return VINF_SUCCESS;
615	#ifdef IN_RC
616	}
617	}
618	#endif
619	return VERR_EM_INTERPRETER;
620	}
621
622
623	/**
624	* POP Emulation.
625	*/
626	static int emInterpretPop(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
627	{
628	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
629	OP_PARAMVAL param1;
630	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
631	if(RT_FAILURE(rc))
632	return VERR_EM_INTERPRETER;
633
634	#ifdef IN_RC
635	if (TRPMHasTrap(pVM))
636	{
637	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
638	{
639	#endif
640	RTGCPTR pParam1 = 0;
641	uint32_t valpar1;
642	RTGCPTR pStackVal;
643
644	/* Read stack value first */
645	if (SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->ss, &pRegFrame->ssHid) == CPUMODE_16BIT)
646	return VERR_EM_INTERPRETER; /* No legacy 16 bits stuff here, please. */
647
648	/* Convert address; don't bother checking limits etc, as we only read here */
649	pStackVal = SELMToFlat(pVM, DIS_SELREG_SS, pRegFrame, (RTGCPTR)pRegFrame->esp);
650	if (pStackVal == 0)
651	return VERR_EM_INTERPRETER;
652
653	rc = emRamRead(pVM, &valpar1, pStackVal, param1.size);
654	if (RT_FAILURE(rc))
655	{
656	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
657	return VERR_EM_INTERPRETER;
658	}
659
660	if (param1.type == PARMTYPE_ADDRESS)
661	{
662	pParam1 = (RTGCPTR)param1.val.val64;
663
664	/* pop [esp+xx] uses esp after the actual pop! */
665	AssertCompile(USE_REG_ESP == USE_REG_SP);
666	if ( (pCpu->param1.flags & USE_BASE)
667	&& (pCpu->param1.flags & (USE_REG_GEN16\|USE_REG_GEN32))
668	&& pCpu->param1.base.reg_gen == USE_REG_ESP
669	)
670	pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + param1.size);
671
672	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
673	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault \|\| (RTGCPTR)pRegFrame->esp == pvFault, VERR_EM_INTERPRETER);
674	rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
675	if (RT_FAILURE(rc))
676	{
677	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
678	return VERR_EM_INTERPRETER;
679	}
680
681	/* Update ESP as the last step */
682	pRegFrame->esp += param1.size;
683	}
684	else
685	{
686	#ifndef DEBUG_bird // annoying assertion.
687	AssertFailed();
688	#endif
689	return VERR_EM_INTERPRETER;
690	}
691
692	/* All done! */
693	*pcbSize = param1.size;
694	return VINF_SUCCESS;
695	#ifdef IN_RC
696	}
697	}
698	#endif
699	return VERR_EM_INTERPRETER;
700	}
701
702
703	/**
704	* XOR/OR/AND Emulation.
705	*/
706	static int emInterpretOrXorAnd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
707	PFNEMULATEPARAM3 pfnEmulate)
708	{
709	OP_PARAMVAL param1, param2;
710
711	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
712	if(RT_FAILURE(rc))
713	return VERR_EM_INTERPRETER;
714
715	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
716	if(RT_FAILURE(rc))
717	return VERR_EM_INTERPRETER;
718
719	#ifdef IN_RC
720	if (TRPMHasTrap(pVM))
721	{
722	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
723	{
724	#endif
725	RTGCPTR pParam1;
726	uint64_t valpar1, valpar2;
727
728	if (pCpu->param1.size != pCpu->param2.size)
729	{
730	if (pCpu->param1.size < pCpu->param2.size)
731	{
732	AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pCpu), (RTGCPTR)pRegFrame->rip, pCpu->param1.size, pCpu->param2.size)); /* should never happen! */
733	return VERR_EM_INTERPRETER;
734	}
735	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
736	pCpu->param2.size = pCpu->param1.size;
737	param2.size = param1.size;
738	}
739
740	/* The destination is always a virtual address */
741	if (param1.type == PARMTYPE_ADDRESS)
742	{
743	pParam1 = (RTGCPTR)param1.val.val64;
744	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
745	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
746	rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
747	if (RT_FAILURE(rc))
748	{
749	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
750	return VERR_EM_INTERPRETER;
751	}
752	}
753	else
754	{
755	AssertFailed();
756	return VERR_EM_INTERPRETER;
757	}
758
759	/* Register or immediate data */
760	switch(param2.type)
761	{
762	case PARMTYPE_IMMEDIATE: /* both immediate data and register (ugly) */
763	valpar2 = param2.val.val64;
764	break;
765
766	default:
767	AssertFailed();
768	return VERR_EM_INTERPRETER;
769	}
770
771	LogFlow(("emInterpretOrXorAnd %s %RGv %RX64 - %RX64 size %d (%d)\n", emGetMnemonic(pCpu), pParam1, valpar1, valpar2, param2.size, param1.size));
772
773	/* Data read, emulate instruction. */
774	uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
775
776	LogFlow(("emInterpretOrXorAnd %s result %RX64\n", emGetMnemonic(pCpu), valpar1));
777
778	/* Update guest's eflags and finish. */
779	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
780	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
781
782	/* And write it back */
783	rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
784	if (RT_SUCCESS(rc))
785	{
786	/* All done! */
787	*pcbSize = param2.size;
788	return VINF_SUCCESS;
789	}
790	#ifdef IN_RC
791	}
792	}
793	#endif
794	return VERR_EM_INTERPRETER;
795	}
796
797
798	/**
799	* LOCK XOR/OR/AND Emulation.
800	*/
801	static int emInterpretLockOrXorAnd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
802	uint32_t *pcbSize, PFNEMULATELOCKPARAM3 pfnEmulate)
803	{
804	void *pvParam1;
805	OP_PARAMVAL param1, param2;
806
807	#if HC_ARCH_BITS == 32
808	Assert(pCpu->param1.size <= 4);
809	#endif
810
811	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
812	if(RT_FAILURE(rc))
813	return VERR_EM_INTERPRETER;
814
815	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
816	if(RT_FAILURE(rc))
817	return VERR_EM_INTERPRETER;
818
819	if (pCpu->param1.size != pCpu->param2.size)
820	{
821	AssertMsgReturn(pCpu->param1.size >= pCpu->param2.size, /* should never happen! */
822	("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pCpu), (RTGCPTR)pRegFrame->rip, pCpu->param1.size, pCpu->param2.size),
823	VERR_EM_INTERPRETER);
824
825	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
826	pCpu->param2.size = pCpu->param1.size;
827	param2.size = param1.size;
828	}
829
830	#ifdef IN_RC
831	/* Safety check (in theory it could cross a page boundary and fault there though) */
832	Assert( TRPMHasTrap(pVM)
833	&& (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW));
834	EM_ASSERT_FAULT_RETURN(GCPtrPar1 == pvFault, VERR_EM_INTERPRETER);
835	#endif
836
837	/* Register and immediate data == PARMTYPE_IMMEDIATE */
838	AssertReturn(param2.type == PARMTYPE_IMMEDIATE, VERR_EM_INTERPRETER);
839	RTGCUINTREG ValPar2 = param2.val.val64;
840
841	/* The destination is always a virtual address */
842	AssertReturn(param1.type == PARMTYPE_ADDRESS, VERR_EM_INTERPRETER);
843
844	RTGCPTR GCPtrPar1 = param1.val.val64;
845	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
846	#ifdef IN_RC
847	pvParam1 = (void *)GCPtrPar1;
848	#else
849	PGMPAGEMAPLOCK Lock;
850	rc = PGMPhysGCPtr2CCPtr(pVM, GCPtrPar1, &pvParam1, &Lock);
851	AssertRCReturn(rc, VERR_EM_INTERPRETER);
852	#endif
853
854	/* Try emulate it with a one-shot #PF handler in place. (RC) */
855	Log2(("%s %RGv imm%d=%RX64\n", emGetMnemonic(pCpu), GCPtrPar1, pCpu->param2.size*8, ValPar2));
856
857	RTGCUINTREG32 eflags = 0;
858	#ifdef IN_RC
859	MMGCRamRegisterTrapHandler(pVM);
860	#endif
861	rc = pfnEmulate(pvParam1, ValPar2, pCpu->param2.size, &eflags);
862	#ifdef IN_RC
863	MMGCRamDeregisterTrapHandler(pVM);
864	#else
865	PGMPhysReleasePageMappingLock(pVM, &Lock);
866	#endif
867	if (RT_FAILURE(rc))
868	{
869	Log(("%s %RGv imm%d=%RX64-> emulation failed due to page fault!\n", emGetMnemonic(pCpu), GCPtrPar1, pCpu->param2.size*8, ValPar2));
870	return VERR_EM_INTERPRETER;
871	}
872
873	/* Update guest's eflags and finish. */
874	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
875	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
876
877	*pcbSize = param2.size;
878	return VINF_SUCCESS;
879	}
880
881
882	/**
883	* ADD, ADC & SUB Emulation.
884	*/
885	static int emInterpretAddSub(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
886	PFNEMULATEPARAM3 pfnEmulate)
887	{
888	OP_PARAMVAL param1, param2;
889	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
890	if(RT_FAILURE(rc))
891	return VERR_EM_INTERPRETER;
892
893	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
894	if(RT_FAILURE(rc))
895	return VERR_EM_INTERPRETER;
896
897	#ifdef IN_RC
898	if (TRPMHasTrap(pVM))
899	{
900	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
901	{
902	#endif
903	RTGCPTR pParam1;
904	uint64_t valpar1, valpar2;
905
906	if (pCpu->param1.size != pCpu->param2.size)
907	{
908	if (pCpu->param1.size < pCpu->param2.size)
909	{
910	AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pCpu), (RTGCPTR)pRegFrame->rip, pCpu->param1.size, pCpu->param2.size)); /* should never happen! */
911	return VERR_EM_INTERPRETER;
912	}
913	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
914	pCpu->param2.size = pCpu->param1.size;
915	param2.size = param1.size;
916	}
917
918	/* The destination is always a virtual address */
919	if (param1.type == PARMTYPE_ADDRESS)
920	{
921	pParam1 = (RTGCPTR)param1.val.val64;
922	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
923	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
924	rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
925	if (RT_FAILURE(rc))
926	{
927	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
928	return VERR_EM_INTERPRETER;
929	}
930	}
931	else
932	{
933	#ifndef DEBUG_bird
934	AssertFailed();
935	#endif
936	return VERR_EM_INTERPRETER;
937	}
938
939	/* Register or immediate data */
940	switch(param2.type)
941	{
942	case PARMTYPE_IMMEDIATE: /* both immediate data and register (ugly) */
943	valpar2 = param2.val.val64;
944	break;
945
946	default:
947	AssertFailed();
948	return VERR_EM_INTERPRETER;
949	}
950
951	/* Data read, emulate instruction. */
952	uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
953
954	/* Update guest's eflags and finish. */
955	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
956	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
957
958	/* And write it back */
959	rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
960	if (RT_SUCCESS(rc))
961	{
962	/* All done! */
963	*pcbSize = param2.size;
964	return VINF_SUCCESS;
965	}
966	#ifdef IN_RC
967	}
968	}
969	#endif
970	return VERR_EM_INTERPRETER;
971	}
972
973
974	/**
975	* ADC Emulation.
976	*/
977	static int emInterpretAdc(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
978	{
979	if (pRegFrame->eflags.Bits.u1CF)
980	return emInterpretAddSub(pVM, pCpu, pRegFrame, pvFault, pcbSize, EMEmulateAdcWithCarrySet);
981	else
982	return emInterpretAddSub(pVM, pCpu, pRegFrame, pvFault, pcbSize, EMEmulateAdd);
983	}
984
985
986	/**
987	* BTR/C/S Emulation.
988	*/
989	static int emInterpretBitTest(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
990	PFNEMULATEPARAM2UINT32 pfnEmulate)
991	{
992	OP_PARAMVAL param1, param2;
993	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
994	if(RT_FAILURE(rc))
995	return VERR_EM_INTERPRETER;
996
997	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
998	if(RT_FAILURE(rc))
999	return VERR_EM_INTERPRETER;
1000
1001	#ifdef IN_RC
1002	if (TRPMHasTrap(pVM))
1003	{
1004	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1005	{
1006	#endif
1007	RTGCPTR pParam1;
1008	uint64_t valpar1 = 0, valpar2;
1009	uint32_t eflags;
1010
1011	/* The destination is always a virtual address */
1012	if (param1.type != PARMTYPE_ADDRESS)
1013	return VERR_EM_INTERPRETER;
1014
1015	pParam1 = (RTGCPTR)param1.val.val64;
1016	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
1017
1018	/* Register or immediate data */
1019	switch(param2.type)
1020	{
1021	case PARMTYPE_IMMEDIATE: /* both immediate data and register (ugly) */
1022	valpar2 = param2.val.val64;
1023	break;
1024
1025	default:
1026	AssertFailed();
1027	return VERR_EM_INTERPRETER;
1028	}
1029
1030	Log2(("emInterpret%s: pvFault=%RGv pParam1=%RGv val2=%x\n", emGetMnemonic(pCpu), pvFault, pParam1, valpar2));
1031	pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + valpar2/8);
1032	EM_ASSERT_FAULT_RETURN((RTGCPTR)((RTGCUINTPTR)pParam1 & ~3) == pvFault, VERR_EM_INTERPRETER);
1033	rc = emRamRead(pVM, &valpar1, pParam1, 1);
1034	if (RT_FAILURE(rc))
1035	{
1036	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
1037	return VERR_EM_INTERPRETER;
1038	}
1039
1040	Log2(("emInterpretBtx: val=%x\n", valpar1));
1041	/* Data read, emulate bit test instruction. */
1042	eflags = pfnEmulate(&valpar1, valpar2 & 0x7);
1043
1044	Log2(("emInterpretBtx: val=%x CF=%d\n", valpar1, !!(eflags & X86_EFL_CF)));
1045
1046	/* Update guest's eflags and finish. */
1047	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1048	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1049
1050	/* And write it back */
1051	rc = emRamWrite(pVM, pParam1, &valpar1, 1);
1052	if (RT_SUCCESS(rc))
1053	{
1054	/* All done! */
1055	*pcbSize = 1;
1056	return VINF_SUCCESS;
1057	}
1058	#ifdef IN_RC
1059	}
1060	}
1061	#endif
1062	return VERR_EM_INTERPRETER;
1063	}
1064
1065
1066	/**
1067	* LOCK BTR/C/S Emulation.
1068	*/
1069	static int emInterpretLockBitTest(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
1070	uint32_t *pcbSize, PFNEMULATELOCKPARAM2 pfnEmulate)
1071	{
1072	void *pvParam1;
1073
1074	OP_PARAMVAL param1, param2;
1075	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
1076	if(RT_FAILURE(rc))
1077	return VERR_EM_INTERPRETER;
1078
1079	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1080	if(RT_FAILURE(rc))
1081	return VERR_EM_INTERPRETER;
1082
1083	/* The destination is always a virtual address */
1084	if (param1.type != PARMTYPE_ADDRESS)
1085	return VERR_EM_INTERPRETER;
1086
1087	/* Register and immediate data == PARMTYPE_IMMEDIATE */
1088	AssertReturn(param2.type == PARMTYPE_IMMEDIATE, VERR_EM_INTERPRETER);
1089	uint64_t ValPar2 = param2.val.val64;
1090
1091	/* Adjust the parameters so what we're dealing with is a bit within the byte pointed to. */
1092	RTGCPTR GCPtrPar1 = param1.val.val64;
1093	GCPtrPar1 = (GCPtrPar1 + ValPar2 / 8);
1094	ValPar2 &= 7;
1095
1096	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
1097	#ifdef IN_RC
1098	Assert(TRPMHasTrap(pVM));
1099	EM_ASSERT_FAULT_RETURN((RTGCPTR)((RTGCUINTPTR)GCPtrPar1 & ~(RTGCUINTPTR)3) == pvFault, VERR_EM_INTERPRETER);
1100	#endif
1101
1102	#ifdef IN_RC
1103	pvParam1 = (void *)GCPtrPar1;
1104	#else
1105	PGMPAGEMAPLOCK Lock;
1106	rc = PGMPhysGCPtr2CCPtr(pVM, GCPtrPar1, &pvParam1, &Lock);
1107	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1108	#endif
1109
1110	Log2(("emInterpretLockBitTest %s: pvFault=%RGv GCPtrPar1=%RGv imm=%RX64\n", emGetMnemonic(pCpu), pvFault, GCPtrPar1, ValPar2));
1111
1112	/* Try emulate it with a one-shot #PF handler in place. (RC) */
1113	RTGCUINTREG32 eflags = 0;
1114	#ifdef IN_RC
1115	MMGCRamRegisterTrapHandler(pVM);
1116	#endif
1117	rc = pfnEmulate(pvParam1, ValPar2, &eflags);
1118	#ifdef IN_RC
1119	MMGCRamDeregisterTrapHandler(pVM);
1120	#else
1121	PGMPhysReleasePageMappingLock(pVM, &Lock);
1122	#endif
1123	if (RT_FAILURE(rc))
1124	{
1125	Log(("emInterpretLockBitTest %s: %RGv imm%d=%RX64 -> emulation failed due to page fault!\n",
1126	emGetMnemonic(pCpu), GCPtrPar1, pCpu->param2.size*8, ValPar2));
1127	return VERR_EM_INTERPRETER;
1128	}
1129
1130	Log2(("emInterpretLockBitTest %s: GCPtrPar1=%RGv imm=%RX64 CF=%d\n", emGetMnemonic(pCpu), GCPtrPar1, ValPar2, !!(eflags & X86_EFL_CF)));
1131
1132	/* Update guest's eflags and finish. */
1133	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1134	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1135
1136	*pcbSize = 1;
1137	return VINF_SUCCESS;
1138	}
1139
1140
1141	/**
1142	* MOV emulation.
1143	*/
1144	static int emInterpretMov(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1145	{
1146	OP_PARAMVAL param1, param2;
1147	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
1148	if(RT_FAILURE(rc))
1149	return VERR_EM_INTERPRETER;
1150
1151	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1152	if(RT_FAILURE(rc))
1153	return VERR_EM_INTERPRETER;
1154
1155	#ifdef IN_RC
1156	if (TRPMHasTrap(pVM))
1157	{
1158	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1159	{
1160	#else
1161	/** @todo Make this the default and don't rely on TRPM information. */
1162	if (param1.type == PARMTYPE_ADDRESS)
1163	{
1164	#endif
1165	RTGCPTR pDest;
1166	uint64_t val64;
1167
1168	switch(param1.type)
1169	{
1170	case PARMTYPE_IMMEDIATE:
1171	if(!(param1.flags & (PARAM_VAL32\|PARAM_VAL64)))
1172	return VERR_EM_INTERPRETER;
1173	/* fallthru */
1174
1175	case PARMTYPE_ADDRESS:
1176	pDest = (RTGCPTR)param1.val.val64;
1177	pDest = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pDest);
1178	break;
1179
1180	default:
1181	AssertFailed();
1182	return VERR_EM_INTERPRETER;
1183	}
1184
1185	switch(param2.type)
1186	{
1187	case PARMTYPE_IMMEDIATE: /* register type is translated to this one too */
1188	val64 = param2.val.val64;
1189	break;
1190
1191	default:
1192	Log(("emInterpretMov: unexpected type=%d rip=%RGv\n", param2.type, (RTGCPTR)pRegFrame->rip));
1193	return VERR_EM_INTERPRETER;
1194	}
1195	#ifdef LOG_ENABLED
1196	if (pCpu->mode == CPUMODE_64BIT)
1197	LogFlow(("EMInterpretInstruction at %RGv: OP_MOV %RGv <- %RX64 (%d) &val64=%RHv\n", (RTGCPTR)pRegFrame->rip, pDest, val64, param2.size, &val64));
1198	else
1199	LogFlow(("EMInterpretInstruction at %08RX64: OP_MOV %RGv <- %08X (%d) &val64=%RHv\n", pRegFrame->rip, pDest, (uint32_t)val64, param2.size, &val64));
1200	#endif
1201
1202	Assert(param2.size <= 8 && param2.size > 0);
1203	EM_ASSERT_FAULT_RETURN(pDest == pvFault, VERR_EM_INTERPRETER);
1204	rc = emRamWrite(pVM, pDest, &val64, param2.size);
1205	if (RT_FAILURE(rc))
1206	return VERR_EM_INTERPRETER;
1207
1208	*pcbSize = param2.size;
1209	}
1210	else
1211	{ /* read fault */
1212	RTGCPTR pSrc;
1213	uint64_t val64;
1214
1215	/* Source */
1216	switch(param2.type)
1217	{
1218	case PARMTYPE_IMMEDIATE:
1219	if(!(param2.flags & (PARAM_VAL32\|PARAM_VAL64)))
1220	return VERR_EM_INTERPRETER;
1221	/* fallthru */
1222
1223	case PARMTYPE_ADDRESS:
1224	pSrc = (RTGCPTR)param2.val.val64;
1225	pSrc = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param2, pSrc);
1226	break;
1227
1228	default:
1229	return VERR_EM_INTERPRETER;
1230	}
1231
1232	Assert(param1.size <= 8 && param1.size > 0);
1233	EM_ASSERT_FAULT_RETURN(pSrc == pvFault, VERR_EM_INTERPRETER);
1234	rc = emRamRead(pVM, &val64, pSrc, param1.size);
1235	if (RT_FAILURE(rc))
1236	return VERR_EM_INTERPRETER;
1237
1238	/* Destination */
1239	switch(param1.type)
1240	{
1241	case PARMTYPE_REGISTER:
1242	switch(param1.size)
1243	{
1244	case 1: rc = DISWriteReg8(pRegFrame, pCpu->param1.base.reg_gen, (uint8_t) val64); break;
1245	case 2: rc = DISWriteReg16(pRegFrame, pCpu->param1.base.reg_gen, (uint16_t)val64); break;
1246	case 4: rc = DISWriteReg32(pRegFrame, pCpu->param1.base.reg_gen, (uint32_t)val64); break;
1247	case 8: rc = DISWriteReg64(pRegFrame, pCpu->param1.base.reg_gen, val64); break;
1248	default:
1249	return VERR_EM_INTERPRETER;
1250	}
1251	if (RT_FAILURE(rc))
1252	return rc;
1253	break;
1254
1255	default:
1256	return VERR_EM_INTERPRETER;
1257	}
1258	#ifdef LOG_ENABLED
1259	if (pCpu->mode == CPUMODE_64BIT)
1260	LogFlow(("EMInterpretInstruction: OP_MOV %RGv -> %RX64 (%d)\n", pSrc, val64, param1.size));
1261	else
1262	LogFlow(("EMInterpretInstruction: OP_MOV %RGv -> %08X (%d)\n", pSrc, (uint32_t)val64, param1.size));
1263	#endif
1264	}
1265	return VINF_SUCCESS;
1266	#ifdef IN_RC
1267	}
1268	#endif
1269	return VERR_EM_INTERPRETER;
1270	}
1271
1272
1273	#ifndef IN_RC
1274	/**
1275	* [REP] STOSWD emulation
1276	*/
1277	static int emInterpretStosWD(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1278	{
1279	int rc;
1280	RTGCPTR GCDest, GCOffset;
1281	uint32_t cbSize;
1282	uint64_t cTransfers;
1283	int offIncrement;
1284
1285	/* Don't support any but these three prefix bytes. */
1286	if ((pCpu->prefix & ~(PREFIX_ADDRSIZE\|PREFIX_OPSIZE\|PREFIX_REP\|PREFIX_REX)))
1287	return VERR_EM_INTERPRETER;
1288
1289	switch (pCpu->addrmode)
1290	{
1291	case CPUMODE_16BIT:
1292	GCOffset = pRegFrame->di;
1293	cTransfers = pRegFrame->cx;
1294	break;
1295	case CPUMODE_32BIT:
1296	GCOffset = pRegFrame->edi;
1297	cTransfers = pRegFrame->ecx;
1298	break;
1299	case CPUMODE_64BIT:
1300	GCOffset = pRegFrame->rdi;
1301	cTransfers = pRegFrame->rcx;
1302	break;
1303	default:
1304	AssertFailed();
1305	return VERR_EM_INTERPRETER;
1306	}
1307
1308	GCDest = SELMToFlat(pVM, DIS_SELREG_ES, pRegFrame, GCOffset);
1309	switch (pCpu->opmode)
1310	{
1311	case CPUMODE_16BIT:
1312	cbSize = 2;
1313	break;
1314	case CPUMODE_32BIT:
1315	cbSize = 4;
1316	break;
1317	case CPUMODE_64BIT:
1318	cbSize = 8;
1319	break;
1320	default:
1321	AssertFailed();
1322	return VERR_EM_INTERPRETER;
1323	}
1324
1325	offIncrement = pRegFrame->eflags.Bits.u1DF ? -(signed)cbSize : (signed)cbSize;
1326
1327	if (!(pCpu->prefix & PREFIX_REP))
1328	{
1329	LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d\n", pRegFrame->es, GCOffset, GCDest, cbSize));
1330
1331	rc = PGMPhysWriteGCPtr(pVM, GCDest, &pRegFrame->rax, cbSize);
1332	if (RT_FAILURE(rc))
1333	return VERR_EM_INTERPRETER;
1334	Assert(rc == VINF_SUCCESS);
1335
1336	/* Update (e/r)di. */
1337	switch (pCpu->addrmode)
1338	{
1339	case CPUMODE_16BIT:
1340	pRegFrame->di += offIncrement;
1341	break;
1342	case CPUMODE_32BIT:
1343	pRegFrame->edi += offIncrement;
1344	break;
1345	case CPUMODE_64BIT:
1346	pRegFrame->rdi += offIncrement;
1347	break;
1348	default:
1349	AssertFailed();
1350	return VERR_EM_INTERPRETER;
1351	}
1352
1353	}
1354	else
1355	{
1356	if (!cTransfers)
1357	return VINF_SUCCESS;
1358
1359	/* Do not try emulate cross page stuff here, this also fends off big copies which
1360	would kill PGMR0DynMap. */
1361	if ( cbSize > PAGE_SIZE
1362	\|\| cTransfers > PAGE_SIZE
1363	\|\| (GCDest >> PAGE_SHIFT) != ((GCDest + offIncrement * cTransfers) >> PAGE_SHIFT))
1364	{
1365	Log(("STOSWD is crosses pages, chicken out to the recompiler; GCDest=%RGv cbSize=%#x offIncrement=%d cTransfers=%#x\n",
1366	GCDest, cbSize, offIncrement, cTransfers));
1367	return VERR_EM_INTERPRETER;
1368	}
1369
1370	LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d cTransfers=%x DF=%d\n", pRegFrame->es, GCOffset, GCDest, cbSize, cTransfers, pRegFrame->eflags.Bits.u1DF));
1371	/* Access verification first; we currently can't recover properly from traps inside this instruction */
1372	rc = PGMVerifyAccess(pVM, GCDest - ((offIncrement > 0) ? 0 : ((cTransfers-1) * cbSize)),
1373	cTransfers * cbSize,
1374	X86_PTE_RW \| (CPUMGetGuestCPL(pVM, pRegFrame) == 3 ? X86_PTE_US : 0));
1375	if (rc != VINF_SUCCESS)
1376	{
1377	Log(("STOSWD will generate a trap -> recompiler, rc=%d\n", rc));
1378	return VERR_EM_INTERPRETER;
1379	}
1380
1381	/* REP case */
1382	while (cTransfers)
1383	{
1384	rc = PGMPhysWriteGCPtr(pVM, GCDest, &pRegFrame->rax, cbSize);
1385	if (RT_FAILURE(rc))
1386	{
1387	rc = VERR_EM_INTERPRETER;
1388	break;
1389	}
1390
1391	Assert(rc == VINF_SUCCESS);
1392	GCOffset += offIncrement;
1393	GCDest += offIncrement;
1394	cTransfers--;
1395	}
1396
1397	/* Update the registers. */
1398	switch (pCpu->addrmode)
1399	{
1400	case CPUMODE_16BIT:
1401	pRegFrame->di = GCOffset;
1402	pRegFrame->cx = cTransfers;
1403	break;
1404	case CPUMODE_32BIT:
1405	pRegFrame->edi = GCOffset;
1406	pRegFrame->ecx = cTransfers;
1407	break;
1408	case CPUMODE_64BIT:
1409	pRegFrame->rdi = GCOffset;
1410	pRegFrame->rcx = cTransfers;
1411	break;
1412	default:
1413	AssertFailed();
1414	return VERR_EM_INTERPRETER;
1415	}
1416	}
1417
1418	*pcbSize = cbSize;
1419	return rc;
1420	}
1421	#endif /* !IN_RC */
1422
1423	#ifndef IN_RC
1424
1425	/**
1426	* [LOCK] CMPXCHG emulation.
1427	*/
1428	static int emInterpretCmpXchg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1429	{
1430	OP_PARAMVAL param1, param2;
1431
1432	#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL_IN_R0)
1433	Assert(pCpu->param1.size <= 4);
1434	#endif
1435
1436	/* Source to make DISQueryParamVal read the register value - ugly hack */
1437	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1438	if(RT_FAILURE(rc))
1439	return VERR_EM_INTERPRETER;
1440
1441	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1442	if(RT_FAILURE(rc))
1443	return VERR_EM_INTERPRETER;
1444
1445	uint64_t valpar;
1446	switch(param2.type)
1447	{
1448	case PARMTYPE_IMMEDIATE: /* register actually */
1449	valpar = param2.val.val64;
1450	break;
1451
1452	default:
1453	return VERR_EM_INTERPRETER;
1454	}
1455
1456	PGMPAGEMAPLOCK Lock;
1457	RTGCPTR GCPtrPar1;
1458	void *pvParam1;
1459	uint64_t eflags;
1460
1461	AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
1462	switch(param1.type)
1463	{
1464	case PARMTYPE_ADDRESS:
1465	GCPtrPar1 = param1.val.val64;
1466	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
1467
1468	rc = PGMPhysGCPtr2CCPtr(pVM, GCPtrPar1, &pvParam1, &Lock);
1469	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1470	break;
1471
1472	default:
1473	return VERR_EM_INTERPRETER;
1474	}
1475
1476	LogFlow(("%s %RGv rax=%RX64 %RX64\n", emGetMnemonic(pCpu), GCPtrPar1, pRegFrame->rax, valpar));
1477
1478	if (pCpu->prefix & PREFIX_LOCK)
1479	eflags = EMEmulateLockCmpXchg(pvParam1, &pRegFrame->rax, valpar, pCpu->param2.size);
1480	else
1481	eflags = EMEmulateCmpXchg(pvParam1, &pRegFrame->rax, valpar, pCpu->param2.size);
1482
1483	LogFlow(("%s %RGv rax=%RX64 %RX64 ZF=%d\n", emGetMnemonic(pCpu), GCPtrPar1, pRegFrame->rax, valpar, !!(eflags & X86_EFL_ZF)));
1484
1485	/* Update guest's eflags and finish. */
1486	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1487	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1488
1489	*pcbSize = param2.size;
1490	PGMPhysReleasePageMappingLock(pVM, &Lock);
1491	return VINF_SUCCESS;
1492	}
1493
1494
1495	/**
1496	* [LOCK] CMPXCHG8B emulation.
1497	*/
1498	static int emInterpretCmpXchg8b(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1499	{
1500	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
1501	OP_PARAMVAL param1;
1502
1503	/* Source to make DISQueryParamVal read the register value - ugly hack */
1504	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1505	if(RT_FAILURE(rc))
1506	return VERR_EM_INTERPRETER;
1507
1508	RTGCPTR GCPtrPar1;
1509	void *pvParam1;
1510	uint64_t eflags;
1511	PGMPAGEMAPLOCK Lock;
1512
1513	AssertReturn(pCpu->param1.size == 8, VERR_EM_INTERPRETER);
1514	switch(param1.type)
1515	{
1516	case PARMTYPE_ADDRESS:
1517	GCPtrPar1 = param1.val.val64;
1518	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
1519
1520	rc = PGMPhysGCPtr2CCPtr(pVM, GCPtrPar1, &pvParam1, &Lock);
1521	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1522	break;
1523
1524	default:
1525	return VERR_EM_INTERPRETER;
1526	}
1527
1528	LogFlow(("%s %RGv=%08x eax=%08x\n", emGetMnemonic(pCpu), pvParam1, pRegFrame->eax));
1529
1530	if (pCpu->prefix & PREFIX_LOCK)
1531	eflags = EMEmulateLockCmpXchg8b(pvParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
1532	else
1533	eflags = EMEmulateCmpXchg8b(pvParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
1534
1535	LogFlow(("%s %RGv=%08x eax=%08x ZF=%d\n", emGetMnemonic(pCpu), pvParam1, pRegFrame->eax, !!(eflags & X86_EFL_ZF)));
1536
1537	/* Update guest's eflags and finish; note that only ZF is affected. */
1538	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_ZF))
1539	\| (eflags & (X86_EFL_ZF));
1540
1541	*pcbSize = 8;
1542	PGMPhysReleasePageMappingLock(pVM, &Lock);
1543	return VINF_SUCCESS;
1544	}
1545
1546	#else /* IN_RC */
1547
1548	/**
1549	* [LOCK] CMPXCHG emulation.
1550	*/
1551	static int emInterpretCmpXchg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1552	{
1553	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
1554	OP_PARAMVAL param1, param2;
1555
1556	/* Source to make DISQueryParamVal read the register value - ugly hack */
1557	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1558	if(RT_FAILURE(rc))
1559	return VERR_EM_INTERPRETER;
1560
1561	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1562	if(RT_FAILURE(rc))
1563	return VERR_EM_INTERPRETER;
1564
1565	if (TRPMHasTrap(pVM))
1566	{
1567	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1568	{
1569	RTRCPTR pParam1;
1570	uint32_t valpar, eflags;
1571
1572	AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
1573	switch(param1.type)
1574	{
1575	case PARMTYPE_ADDRESS:
1576	pParam1 = (RTRCPTR)param1.val.val64;
1577	pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);
1578	EM_ASSERT_FAULT_RETURN(pParam1 == (RTRCPTR)pvFault, VERR_EM_INTERPRETER);
1579	break;
1580
1581	default:
1582	return VERR_EM_INTERPRETER;
1583	}
1584
1585	switch(param2.type)
1586	{
1587	case PARMTYPE_IMMEDIATE: /* register actually */
1588	valpar = param2.val.val32;
1589	break;
1590
1591	default:
1592	return VERR_EM_INTERPRETER;
1593	}
1594
1595	LogFlow(("%s %RRv eax=%08x %08x\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax, valpar));
1596
1597	MMGCRamRegisterTrapHandler(pVM);
1598	if (pCpu->prefix & PREFIX_LOCK)
1599	rc = EMGCEmulateLockCmpXchg(pParam1, &pRegFrame->eax, valpar, pCpu->param2.size, &eflags);
1600	else
1601	rc = EMGCEmulateCmpXchg(pParam1, &pRegFrame->eax, valpar, pCpu->param2.size, &eflags);
1602	MMGCRamDeregisterTrapHandler(pVM);
1603
1604	if (RT_FAILURE(rc))
1605	{
1606	Log(("%s %RGv eax=%08x %08x -> emulation failed due to page fault!\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax, valpar));
1607	return VERR_EM_INTERPRETER;
1608	}
1609
1610	LogFlow(("%s %RRv eax=%08x %08x ZF=%d\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax, valpar, !!(eflags & X86_EFL_ZF)));
1611
1612	/* Update guest's eflags and finish. */
1613	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1614	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1615
1616	*pcbSize = param2.size;
1617	return VINF_SUCCESS;
1618	}
1619	}
1620	return VERR_EM_INTERPRETER;
1621	}
1622
1623
1624	/**
1625	* [LOCK] CMPXCHG8B emulation.
1626	*/
1627	static int emInterpretCmpXchg8b(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1628	{
1629	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
1630	OP_PARAMVAL param1;
1631
1632	/* Source to make DISQueryParamVal read the register value - ugly hack */
1633	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1634	if(RT_FAILURE(rc))
1635	return VERR_EM_INTERPRETER;
1636
1637	if (TRPMHasTrap(pVM))
1638	{
1639	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1640	{
1641	RTRCPTR pParam1;
1642	uint32_t eflags;
1643
1644	AssertReturn(pCpu->param1.size == 8, VERR_EM_INTERPRETER);
1645	switch(param1.type)
1646	{
1647	case PARMTYPE_ADDRESS:
1648	pParam1 = (RTRCPTR)param1.val.val64;
1649	pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);
1650	EM_ASSERT_FAULT_RETURN(pParam1 == (RTRCPTR)pvFault, VERR_EM_INTERPRETER);
1651	break;
1652
1653	default:
1654	return VERR_EM_INTERPRETER;
1655	}
1656
1657	LogFlow(("%s %RRv=%08x eax=%08x\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax));
1658
1659	MMGCRamRegisterTrapHandler(pVM);
1660	if (pCpu->prefix & PREFIX_LOCK)
1661	rc = EMGCEmulateLockCmpXchg8b(pParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx, &eflags);
1662	else
1663	rc = EMGCEmulateCmpXchg8b(pParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx, &eflags);
1664	MMGCRamDeregisterTrapHandler(pVM);
1665
1666	if (RT_FAILURE(rc))
1667	{
1668	Log(("%s %RGv=%08x eax=%08x -> emulation failed due to page fault!\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax));
1669	return VERR_EM_INTERPRETER;
1670	}
1671
1672	LogFlow(("%s %RGv=%08x eax=%08x ZF=%d\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax, !!(eflags & X86_EFL_ZF)));
1673
1674	/* Update guest's eflags and finish; note that only ZF is affected. */
1675	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_ZF))
1676	\| (eflags & (X86_EFL_ZF));
1677
1678	*pcbSize = 8;
1679	return VINF_SUCCESS;
1680	}
1681	}
1682	return VERR_EM_INTERPRETER;
1683	}
1684
1685	#endif /* IN_RC */
1686
1687	#ifdef IN_RC
1688	/**
1689	* [LOCK] XADD emulation.
1690	*/
1691	static int emInterpretXAdd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1692	{
1693	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
1694	OP_PARAMVAL param1;
1695	uint32_t *pParamReg2;
1696	size_t cbSizeParamReg2;
1697
1698	/* Source to make DISQueryParamVal read the register value - ugly hack */
1699	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1700	if(RT_FAILURE(rc))
1701	return VERR_EM_INTERPRETER;
1702
1703	rc = DISQueryParamRegPtr(pRegFrame, pCpu, &pCpu->param2, (void **)&pParamReg2, &cbSizeParamReg2);
1704	Assert(cbSizeParamReg2 <= 4);
1705	if(RT_FAILURE(rc))
1706	return VERR_EM_INTERPRETER;
1707
1708	if (TRPMHasTrap(pVM))
1709	{
1710	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1711	{
1712	RTRCPTR pParam1;
1713	uint32_t eflags;
1714
1715	AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
1716	switch(param1.type)
1717	{
1718	case PARMTYPE_ADDRESS:
1719	pParam1 = (RTRCPTR)param1.val.val64;
1720	pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);
1721	EM_ASSERT_FAULT_RETURN(pParam1 == (RTRCPTR)pvFault, VERR_EM_INTERPRETER);
1722	break;
1723
1724	default:
1725	return VERR_EM_INTERPRETER;
1726	}
1727
1728	LogFlow(("XAdd %RRv=%08x reg=%08x\n", pParam1, *pParamReg2));
1729
1730	MMGCRamRegisterTrapHandler(pVM);
1731	if (pCpu->prefix & PREFIX_LOCK)
1732	rc = EMGCEmulateLockXAdd(pParam1, pParamReg2, cbSizeParamReg2, &eflags);
1733	else
1734	rc = EMGCEmulateXAdd(pParam1, pParamReg2, cbSizeParamReg2, &eflags);
1735	MMGCRamDeregisterTrapHandler(pVM);
1736
1737	if (RT_FAILURE(rc))
1738	{
1739	Log(("XAdd %RGv reg=%08x -> emulation failed due to page fault!\n", pParam1, *pParamReg2));
1740	return VERR_EM_INTERPRETER;
1741	}
1742
1743	LogFlow(("XAdd %RGv reg=%08x ZF=%d\n", pParam1, *pParamReg2, !!(eflags & X86_EFL_ZF)));
1744
1745	/* Update guest's eflags and finish. */
1746	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1747	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1748
1749	*pcbSize = cbSizeParamReg2;
1750	return VINF_SUCCESS;
1751	}
1752	}
1753	return VERR_EM_INTERPRETER;
1754	}
1755	#endif /* IN_RC */
1756
1757
1758	#ifdef IN_RC
1759	/**
1760	* Interpret IRET (currently only to V86 code)
1761	*
1762	* @returns VBox status code.
1763	* @param pVM The VM handle.
1764	* @param pRegFrame The register frame.
1765	*
1766	*/
1767	VMMDECL(int) EMInterpretIret(PVM pVM, PCPUMCTXCORE pRegFrame)
1768	{
1769	RTGCUINTPTR pIretStack = (RTGCUINTPTR)pRegFrame->esp;
1770	RTGCUINTPTR eip, cs, esp, ss, eflags, ds, es, fs, gs, uMask;
1771	int rc;
1772
1773	Assert(!CPUMIsGuestIn64BitCode(pVM, pRegFrame));
1774
1775	rc = emRamRead(pVM, &eip, (RTGCPTR)pIretStack , 4);
1776	rc \|= emRamRead(pVM, &cs, (RTGCPTR)(pIretStack + 4), 4);
1777	rc \|= emRamRead(pVM, &eflags, (RTGCPTR)(pIretStack + 8), 4);
1778	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1779	AssertReturn(eflags & X86_EFL_VM, VERR_EM_INTERPRETER);
1780
1781	rc \|= emRamRead(pVM, &esp, (RTGCPTR)(pIretStack + 12), 4);
1782	rc \|= emRamRead(pVM, &ss, (RTGCPTR)(pIretStack + 16), 4);
1783	rc \|= emRamRead(pVM, &es, (RTGCPTR)(pIretStack + 20), 4);
1784	rc \|= emRamRead(pVM, &ds, (RTGCPTR)(pIretStack + 24), 4);
1785	rc \|= emRamRead(pVM, &fs, (RTGCPTR)(pIretStack + 28), 4);
1786	rc \|= emRamRead(pVM, &gs, (RTGCPTR)(pIretStack + 32), 4);
1787	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1788
1789	pRegFrame->eip = eip & 0xffff;
1790	pRegFrame->cs = cs;
1791
1792	/* Mask away all reserved bits */
1793	uMask = X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_RF \| X86_EFL_VM \| X86_EFL_AC \| X86_EFL_VIF \| X86_EFL_VIP \| X86_EFL_ID;
1794	eflags &= uMask;
1795
1796	#ifndef IN_RING0
1797	CPUMRawSetEFlags(pVM, pRegFrame, eflags);
1798	#endif
1799	Assert((pRegFrame->eflags.u32 & (X86_EFL_IF\|X86_EFL_IOPL)) == X86_EFL_IF);
1800
1801	pRegFrame->esp = esp;
1802	pRegFrame->ss = ss;
1803	pRegFrame->ds = ds;
1804	pRegFrame->es = es;
1805	pRegFrame->fs = fs;
1806	pRegFrame->gs = gs;
1807
1808	return VINF_SUCCESS;
1809	}
1810	#endif /* IN_RC */
1811
1812
1813	/**
1814	* IRET Emulation.
1815	*/
1816	static int emInterpretIret(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1817	{
1818	/* only allow direct calls to EMInterpretIret for now */
1819	return VERR_EM_INTERPRETER;
1820	}
1821
1822	/**
1823	* WBINVD Emulation.
1824	*/
1825	static int emInterpretWbInvd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1826	{
1827	/* Nothing to do. */
1828	return VINF_SUCCESS;
1829	}
1830
1831
1832	/**
1833	* Interpret INVLPG
1834	*
1835	* @returns VBox status code.
1836	* @param pVM The VM handle.
1837	* @param pRegFrame The register frame.
1838	* @param pAddrGC Operand address
1839	*
1840	*/
1841	VMMDECL(int) EMInterpretInvlpg(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC)
1842	{
1843	int rc;
1844
1845	/** @todo is addr always a flat linear address or ds based
1846	* (in absence of segment override prefixes)????
1847	*/
1848	#ifdef IN_RC
1849	LogFlow(("RC: EMULATE: invlpg %RGv\n", pAddrGC));
1850	#endif
1851	rc = PGMInvalidatePage(pVM, pAddrGC);
1852	if ( rc == VINF_SUCCESS
1853	\|\| rc == VINF_PGM_SYNC_CR3 /* we can rely on the FF */)
1854	return VINF_SUCCESS;
1855	AssertMsgReturn( rc == VERR_REM_FLUSHED_PAGES_OVERFLOW
1856	\|\| rc == VINF_EM_RAW_EMULATE_INSTR,
1857	("%Rrc addr=%RGv\n", rc, pAddrGC),
1858	VERR_EM_INTERPRETER);
1859	return rc;
1860	}
1861
1862
1863	/**
1864	* INVLPG Emulation.
1865	*/
1866	static int emInterpretInvlPg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1867	{
1868	OP_PARAMVAL param1;
1869	RTGCPTR addr;
1870
1871	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1872	if(RT_FAILURE(rc))
1873	return VERR_EM_INTERPRETER;
1874
1875	switch(param1.type)
1876	{
1877	case PARMTYPE_IMMEDIATE:
1878	case PARMTYPE_ADDRESS:
1879	if(!(param1.flags & (PARAM_VAL32\|PARAM_VAL64)))
1880	return VERR_EM_INTERPRETER;
1881	addr = (RTGCPTR)param1.val.val64;
1882	break;
1883
1884	default:
1885	return VERR_EM_INTERPRETER;
1886	}
1887
1888	/** @todo is addr always a flat linear address or ds based
1889	* (in absence of segment override prefixes)????
1890	*/
1891	#ifdef IN_RC
1892	LogFlow(("RC: EMULATE: invlpg %RGv\n", addr));
1893	#endif
1894	rc = PGMInvalidatePage(pVM, addr);
1895	if ( rc == VINF_SUCCESS
1896	\|\| rc == VINF_PGM_SYNC_CR3 /* we can rely on the FF */)
1897	return VINF_SUCCESS;
1898	AssertMsgReturn( rc == VERR_REM_FLUSHED_PAGES_OVERFLOW
1899	\|\| rc == VINF_EM_RAW_EMULATE_INSTR,
1900	("%Rrc addr=%RGv\n", rc, addr),
1901	VERR_EM_INTERPRETER);
1902	return rc;
1903	}
1904
1905
1906	/**
1907	* Interpret CPUID given the parameters in the CPU context
1908	*
1909	* @returns VBox status code.
1910	* @param pVM The VM handle.
1911	* @param pRegFrame The register frame.
1912	*
1913	*/
1914	VMMDECL(int) EMInterpretCpuId(PVM pVM, PCPUMCTXCORE pRegFrame)
1915	{
1916	uint32_t iLeaf = pRegFrame->eax;
1917
1918	/* cpuid clears the high dwords of the affected 64 bits registers. */
1919	pRegFrame->rax = 0;
1920	pRegFrame->rbx = 0;
1921	pRegFrame->rcx = 0;
1922	pRegFrame->rdx = 0;
1923
1924	/* Note: operates the same in 64 and non-64 bits mode. */
1925	CPUMGetGuestCpuId(pVM, iLeaf, &pRegFrame->eax, &pRegFrame->ebx, &pRegFrame->ecx, &pRegFrame->edx);
1926	Log(("Emulate: CPUID %x -> %08x %08x %08x %08x\n", iLeaf, pRegFrame->eax, pRegFrame->ebx, pRegFrame->ecx, pRegFrame->edx));
1927	return VINF_SUCCESS;
1928	}
1929
1930
1931	/**
1932	* CPUID Emulation.
1933	*/
1934	static int emInterpretCpuId(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1935	{
1936	int rc = EMInterpretCpuId(pVM, pRegFrame);
1937	return rc;
1938	}
1939
1940
1941	/**
1942	* Interpret CRx read
1943	*
1944	* @returns VBox status code.
1945	* @param pVM The VM handle.
1946	* @param pRegFrame The register frame.
1947	* @param DestRegGen General purpose register index (USE_REG_E**))
1948	* @param SrcRegCRx CRx register index (USE_REG_CR*)
1949	*
1950	*/
1951	VMMDECL(int) EMInterpretCRxRead(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx)
1952	{
1953	int rc;
1954	uint64_t val64;
1955
1956	if (SrcRegCrx == USE_REG_CR8)
1957	{
1958	val64 = 0;
1959	rc = PDMApicGetTPR(pVM, (uint8_t *)&val64, NULL);
1960	AssertMsgRCReturn(rc, ("PDMApicGetTPR failed\n"), VERR_EM_INTERPRETER);
1961	}
1962	else
1963	{
1964	rc = CPUMGetGuestCRx(pVM, SrcRegCrx, &val64);
1965	AssertMsgRCReturn(rc, ("CPUMGetGuestCRx %d failed\n", SrcRegCrx), VERR_EM_INTERPRETER);
1966	}
1967
1968	if (CPUMIsGuestIn64BitCode(pVM, pRegFrame))
1969	rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
1970	else
1971	rc = DISWriteReg32(pRegFrame, DestRegGen, val64);
1972
1973	if(RT_SUCCESS(rc))
1974	{
1975	LogFlow(("MOV_CR: gen32=%d CR=%d val=%RX64\n", DestRegGen, SrcRegCrx, val64));
1976	return VINF_SUCCESS;
1977	}
1978	return VERR_EM_INTERPRETER;
1979	}
1980
1981
1982
1983	/**
1984	* Interpret CLTS
1985	*
1986	* @returns VBox status code.
1987	* @param pVM The VM handle.
1988	*
1989	*/
1990	VMMDECL(int) EMInterpretCLTS(PVM pVM)
1991	{
1992	uint64_t cr0 = CPUMGetGuestCR0(pVM);
1993	if (!(cr0 & X86_CR0_TS))
1994	return VINF_SUCCESS;
1995	return CPUMSetGuestCR0(pVM, cr0 & ~X86_CR0_TS);
1996	}
1997
1998	/**
1999	* CLTS Emulation.
2000	*/
2001	static int emInterpretClts(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2002	{
2003	return EMInterpretCLTS(pVM);
2004	}
2005
2006
2007	/**
2008	* Update CRx
2009	*
2010	* @returns VBox status code.
2011	* @param pVM The VM handle.
2012	* @param pRegFrame The register frame.
2013	* @param DestRegCRx CRx register index (USE_REG_CR*)
2014	* @param val New CRx value
2015	*
2016	*/
2017	static int EMUpdateCRx(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint64_t val)
2018	{
2019	uint64_t oldval;
2020	uint64_t msrEFER;
2021	int rc;
2022
2023	/** @todo Clean up this mess. */
2024	LogFlow(("EMInterpretCRxWrite at %RGv CR%d <- %RX64\n", (RTGCPTR)pRegFrame->rip, DestRegCrx, val));
2025	switch (DestRegCrx)
2026	{
2027	case USE_REG_CR0:
2028	oldval = CPUMGetGuestCR0(pVM);
2029	#ifdef IN_RC
2030	/* CR0.WP and CR0.AM changes require a reschedule run in ring 3. */
2031	if ( (val & (X86_CR0_WP \| X86_CR0_AM))
2032	!= (oldval & (X86_CR0_WP \| X86_CR0_AM)))
2033	return VERR_EM_INTERPRETER;
2034	#endif
2035	CPUMSetGuestCR0(pVM, val);
2036	val = CPUMGetGuestCR0(pVM);
2037	if ( (oldval & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE))
2038	!= (val & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE)))
2039	{
2040	/* global flush */
2041	rc = PGMFlushTLB(pVM, CPUMGetGuestCR3(pVM), true /* global */);
2042	AssertRCReturn(rc, rc);
2043	}
2044
2045	/* Deal with long mode enabling/disabling. */
2046	msrEFER = CPUMGetGuestEFER(pVM);
2047	if (msrEFER & MSR_K6_EFER_LME)
2048	{
2049	if ( !(oldval & X86_CR0_PG)
2050	&& (val & X86_CR0_PG))
2051	{
2052	/* Illegal to have an active 64 bits CS selector (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
2053	if (pRegFrame->csHid.Attr.n.u1Long)
2054	{
2055	AssertMsgFailed(("Illegal enabling of paging with CS.u1Long = 1!!\n"));
2056	return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
2057	}
2058
2059	/* Illegal to switch to long mode before activating PAE first (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
2060	if (!(CPUMGetGuestCR4(pVM) & X86_CR4_PAE))
2061	{
2062	AssertMsgFailed(("Illegal enabling of paging with PAE disabled!!\n"));
2063	return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
2064	}
2065	msrEFER \|= MSR_K6_EFER_LMA;
2066	}
2067	else
2068	if ( (oldval & X86_CR0_PG)
2069	&& !(val & X86_CR0_PG))
2070	{
2071	msrEFER &= ~MSR_K6_EFER_LMA;
2072	/* @todo Do we need to cut off rip here? High dword of rip is undefined, so it shouldn't really matter. */
2073	}
2074	CPUMSetGuestEFER(pVM, msrEFER);
2075	}
2076	return PGMChangeMode(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR4(pVM), CPUMGetGuestEFER(pVM));
2077
2078	case USE_REG_CR2:
2079	rc = CPUMSetGuestCR2(pVM, val); AssertRC(rc);
2080	return VINF_SUCCESS;
2081
2082	case USE_REG_CR3:
2083	/* Reloading the current CR3 means the guest just wants to flush the TLBs */
2084	rc = CPUMSetGuestCR3(pVM, val); AssertRC(rc);
2085	if (CPUMGetGuestCR0(pVM) & X86_CR0_PG)
2086	{
2087	/* flush */
2088	rc = PGMFlushTLB(pVM, val, !(CPUMGetGuestCR4(pVM) & X86_CR4_PGE));
2089	AssertRCReturn(rc, rc);
2090	}
2091	return VINF_SUCCESS;
2092
2093	case USE_REG_CR4:
2094	oldval = CPUMGetGuestCR4(pVM);
2095	rc = CPUMSetGuestCR4(pVM, val); AssertRC(rc);
2096	val = CPUMGetGuestCR4(pVM);
2097
2098	/* Illegal to disable PAE when long mode is active. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
2099	msrEFER = CPUMGetGuestEFER(pVM);
2100	if ( (msrEFER & MSR_K6_EFER_LMA)
2101	&& (oldval & X86_CR4_PAE)
2102	&& !(val & X86_CR4_PAE))
2103	{
2104	return VERR_EM_INTERPRETER; /** @todo generate #GP(0) */
2105	}
2106
2107	if ( (oldval & (X86_CR4_PGE\|X86_CR4_PAE\|X86_CR4_PSE))
2108	!= (val & (X86_CR4_PGE\|X86_CR4_PAE\|X86_CR4_PSE)))
2109	{
2110	/* global flush */
2111	rc = PGMFlushTLB(pVM, CPUMGetGuestCR3(pVM), true /* global */);
2112	AssertRCReturn(rc, rc);
2113	}
2114
2115	/* Feeling extremely lazy. */
2116	# ifdef IN_RC
2117	if ( (oldval & (X86_CR4_OSFSXR\|X86_CR4_OSXMMEEXCPT\|X86_CR4_PCE\|X86_CR4_MCE\|X86_CR4_PAE\|X86_CR4_DE\|X86_CR4_TSD\|X86_CR4_PVI\|X86_CR4_VME))
2118	!= (val & (X86_CR4_OSFSXR\|X86_CR4_OSXMMEEXCPT\|X86_CR4_PCE\|X86_CR4_MCE\|X86_CR4_PAE\|X86_CR4_DE\|X86_CR4_TSD\|X86_CR4_PVI\|X86_CR4_VME)))
2119	{
2120	Log(("emInterpretMovCRx: CR4: %#RX64->%#RX64 => R3\n", oldval, val));
2121	VM_FF_SET(pVM, VM_FF_TO_R3);
2122	}
2123	# endif
2124	if ((val ^ oldval) & X86_CR4_VME)
2125	VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
2126
2127	return PGMChangeMode(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR4(pVM), CPUMGetGuestEFER(pVM));
2128
2129	case USE_REG_CR8:
2130	return PDMApicSetTPR(pVM, val);
2131
2132	default:
2133	AssertFailed();
2134	case USE_REG_CR1: /* illegal op */
2135	break;
2136	}
2137	return VERR_EM_INTERPRETER;
2138	}
2139
2140	/**
2141	* Interpret CRx write
2142	*
2143	* @returns VBox status code.
2144	* @param pVM The VM handle.
2145	* @param pRegFrame The register frame.
2146	* @param DestRegCRx CRx register index (USE_REG_CR*)
2147	* @param SrcRegGen General purpose register index (USE_REG_E**))
2148	*
2149	*/
2150	VMMDECL(int) EMInterpretCRxWrite(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint32_t SrcRegGen)
2151	{
2152	uint64_t val;
2153	int rc;
2154
2155	if (CPUMIsGuestIn64BitCode(pVM, pRegFrame))
2156	{
2157	rc = DISFetchReg64(pRegFrame, SrcRegGen, &val);
2158	}
2159	else
2160	{
2161	uint32_t val32;
2162	rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
2163	val = val32;
2164	}
2165
2166	if (RT_SUCCESS(rc))
2167	return EMUpdateCRx(pVM, pRegFrame, DestRegCrx, val);
2168
2169	return VERR_EM_INTERPRETER;
2170	}
2171
2172	/**
2173	* Interpret LMSW
2174	*
2175	* @returns VBox status code.
2176	* @param pVM The VM handle.
2177	* @param pRegFrame The register frame.
2178	* @param u16Data LMSW source data.
2179	*
2180	*/
2181	VMMDECL(int) EMInterpretLMSW(PVM pVM, PCPUMCTXCORE pRegFrame, uint16_t u16Data)
2182	{
2183	uint64_t OldCr0 = CPUMGetGuestCR0(pVM);
2184
2185	/* Only PE, MP, EM and TS can be changed; note that PE can't be cleared by this instruction. */
2186	uint64_t NewCr0 = ( OldCr0 & ~( X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
2187	\| (u16Data & (X86_CR0_PE \| X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS));
2188
2189	return EMUpdateCRx(pVM, pRegFrame, USE_REG_CR0, NewCr0);
2190	}
2191
2192	/**
2193	* LMSW Emulation.
2194	*/
2195	static int emInterpretLmsw(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2196	{
2197	OP_PARAMVAL param1;
2198	uint32_t val;
2199
2200	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
2201	if(RT_FAILURE(rc))
2202	return VERR_EM_INTERPRETER;
2203
2204	switch(param1.type)
2205	{
2206	case PARMTYPE_IMMEDIATE:
2207	case PARMTYPE_ADDRESS:
2208	if(!(param1.flags & PARAM_VAL16))
2209	return VERR_EM_INTERPRETER;
2210	val = param1.val.val32;
2211	break;
2212
2213	default:
2214	return VERR_EM_INTERPRETER;
2215	}
2216
2217	LogFlow(("emInterpretLmsw %x\n", val));
2218	return EMInterpretLMSW(pVM, pRegFrame, val);
2219	}
2220
2221	#ifdef EM_EMULATE_SMSW
2222	/**
2223	* SMSW Emulation.
2224	*/
2225	static int emInterpretSmsw(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2226	{
2227	OP_PARAMVAL param1;
2228	uint64_t cr0 = CPUMGetGuestCR0(pVM);
2229
2230	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
2231	if(RT_FAILURE(rc))
2232	return VERR_EM_INTERPRETER;
2233
2234	switch(param1.type)
2235	{
2236	case PARMTYPE_IMMEDIATE:
2237	if(param1.size != sizeof(uint16_t))
2238	return VERR_EM_INTERPRETER;
2239	LogFlow(("emInterpretSmsw %d <- cr0 (%x)\n", pCpu->param1.base.reg_gen, cr0));
2240	rc = DISWriteReg16(pRegFrame, pCpu->param1.base.reg_gen, cr0);
2241	break;
2242
2243	case PARMTYPE_ADDRESS:
2244	{
2245	RTGCPTR pParam1;
2246
2247	/* Actually forced to 16 bits regardless of the operand size. */
2248	if(param1.size != sizeof(uint16_t))
2249	return VERR_EM_INTERPRETER;
2250
2251	pParam1 = (RTGCPTR)param1.val.val64;
2252	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
2253	LogFlow(("emInterpretSmsw %VGv <- cr0 (%x)\n", pParam1, cr0));
2254
2255	rc = emRamWrite(pVM, pParam1, &cr0, sizeof(uint16_t));
2256	if (RT_FAILURE(rc))
2257	{
2258	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2259	return VERR_EM_INTERPRETER;
2260	}
2261	break;
2262	}
2263
2264	default:
2265	return VERR_EM_INTERPRETER;
2266	}
2267
2268	LogFlow(("emInterpretSmsw %x\n", cr0));
2269	return rc;
2270	}
2271	#endif
2272
2273	/**
2274	* MOV CRx
2275	*/
2276	static int emInterpretMovCRx(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2277	{
2278	if ((pCpu->param1.flags == USE_REG_GEN32 \|\| pCpu->param1.flags == USE_REG_GEN64) && pCpu->param2.flags == USE_REG_CR)
2279	return EMInterpretCRxRead(pVM, pRegFrame, pCpu->param1.base.reg_gen, pCpu->param2.base.reg_ctrl);
2280
2281	if (pCpu->param1.flags == USE_REG_CR && (pCpu->param2.flags == USE_REG_GEN32 \|\| pCpu->param2.flags == USE_REG_GEN64))
2282	return EMInterpretCRxWrite(pVM, pRegFrame, pCpu->param1.base.reg_ctrl, pCpu->param2.base.reg_gen);
2283
2284	AssertMsgFailedReturn(("Unexpected control register move\n"), VERR_EM_INTERPRETER);
2285	return VERR_EM_INTERPRETER;
2286	}
2287
2288
2289	/**
2290	* Interpret DRx write
2291	*
2292	* @returns VBox status code.
2293	* @param pVM The VM handle.
2294	* @param pRegFrame The register frame.
2295	* @param DestRegDRx DRx register index (USE_REG_DR*)
2296	* @param SrcRegGen General purpose register index (USE_REG_E**))
2297	*
2298	*/
2299	VMMDECL(int) EMInterpretDRxWrite(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen)
2300	{
2301	uint64_t val;
2302	int rc;
2303
2304	if (CPUMIsGuestIn64BitCode(pVM, pRegFrame))
2305	{
2306	rc = DISFetchReg64(pRegFrame, SrcRegGen, &val);
2307	}
2308	else
2309	{
2310	uint32_t val32;
2311	rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
2312	val = val32;
2313	}
2314
2315	if (RT_SUCCESS(rc))
2316	{
2317	/** @todo we don't fail if illegal bits are set/cleared for e.g. dr7 */
2318	rc = CPUMSetGuestDRx(pVM, DestRegDrx, val);
2319	if (RT_SUCCESS(rc))
2320	return rc;
2321	AssertMsgFailed(("CPUMSetGuestDRx %d failed\n", DestRegDrx));
2322	}
2323	return VERR_EM_INTERPRETER;
2324	}
2325
2326
2327	/**
2328	* Interpret DRx read
2329	*
2330	* @returns VBox status code.
2331	* @param pVM The VM handle.
2332	* @param pRegFrame The register frame.
2333	* @param DestRegGen General purpose register index (USE_REG_E**))
2334	* @param SrcRegDRx DRx register index (USE_REG_DR*)
2335	*
2336	*/
2337	VMMDECL(int) EMInterpretDRxRead(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx)
2338	{
2339	uint64_t val64;
2340
2341	int rc = CPUMGetGuestDRx(pVM, SrcRegDrx, &val64);
2342	AssertMsgRCReturn(rc, ("CPUMGetGuestDRx %d failed\n", SrcRegDrx), VERR_EM_INTERPRETER);
2343	if (CPUMIsGuestIn64BitCode(pVM, pRegFrame))
2344	{
2345	rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
2346	}
2347	else
2348	rc = DISWriteReg32(pRegFrame, DestRegGen, (uint32_t)val64);
2349
2350	if (RT_SUCCESS(rc))
2351	return VINF_SUCCESS;
2352
2353	return VERR_EM_INTERPRETER;
2354	}
2355
2356
2357	/**
2358	* MOV DRx
2359	*/
2360	static int emInterpretMovDRx(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2361	{
2362	int rc = VERR_EM_INTERPRETER;
2363
2364	if((pCpu->param1.flags == USE_REG_GEN32 \|\| pCpu->param1.flags == USE_REG_GEN64) && pCpu->param2.flags == USE_REG_DBG)
2365	{
2366	rc = EMInterpretDRxRead(pVM, pRegFrame, pCpu->param1.base.reg_gen, pCpu->param2.base.reg_dbg);
2367	}
2368	else
2369	if(pCpu->param1.flags == USE_REG_DBG && (pCpu->param2.flags == USE_REG_GEN32 \|\| pCpu->param2.flags == USE_REG_GEN64))
2370	{
2371	rc = EMInterpretDRxWrite(pVM, pRegFrame, pCpu->param1.base.reg_dbg, pCpu->param2.base.reg_gen);
2372	}
2373	else
2374	AssertMsgFailed(("Unexpected debug register move\n"));
2375
2376	return rc;
2377	}
2378
2379
2380	/**
2381	* LLDT Emulation.
2382	*/
2383	static int emInterpretLLdt(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2384	{
2385	OP_PARAMVAL param1;
2386	RTSEL sel;
2387
2388	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
2389	if(RT_FAILURE(rc))
2390	return VERR_EM_INTERPRETER;
2391
2392	switch(param1.type)
2393	{
2394	case PARMTYPE_ADDRESS:
2395	return VERR_EM_INTERPRETER; //feeling lazy right now
2396
2397	case PARMTYPE_IMMEDIATE:
2398	if(!(param1.flags & PARAM_VAL16))
2399	return VERR_EM_INTERPRETER;
2400	sel = (RTSEL)param1.val.val16;
2401	break;
2402
2403	default:
2404	return VERR_EM_INTERPRETER;
2405	}
2406
2407	if (sel == 0)
2408	{
2409	if (CPUMGetHyperLDTR(pVM) == 0)
2410	{
2411	// this simple case is most frequent in Windows 2000 (31k - boot & shutdown)
2412	return VINF_SUCCESS;
2413	}
2414	}
2415	//still feeling lazy
2416	return VERR_EM_INTERPRETER;
2417	}
2418
2419	#ifdef IN_RING0
2420	/**
2421	* LIDT/LGDT Emulation.
2422	*/
2423	static int emInterpretLIGdt(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2424	{
2425	OP_PARAMVAL param1;
2426	RTGCPTR pParam1;
2427	X86XDTR32 dtr32;
2428
2429	Log(("Emulate %s at %RGv\n", emGetMnemonic(pCpu), (RTGCPTR)pRegFrame->rip));
2430
2431	/* Only for the VT-x real-mode emulation case. */
2432	if (!CPUMIsGuestInRealMode(pVM))
2433	return VERR_EM_INTERPRETER;
2434
2435	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
2436	if(RT_FAILURE(rc))
2437	return VERR_EM_INTERPRETER;
2438
2439	switch(param1.type)
2440	{
2441	case PARMTYPE_ADDRESS:
2442	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, param1.val.val16);
2443	break;
2444
2445	default:
2446	return VERR_EM_INTERPRETER;
2447	}
2448
2449	rc = emRamRead(pVM, &dtr32, pParam1, sizeof(dtr32));
2450	AssertRCReturn(rc, VERR_EM_INTERPRETER);
2451
2452	if (!(pCpu->prefix & PREFIX_OPSIZE))
2453	dtr32.uAddr &= 0xffffff; /* 16 bits operand size */
2454
2455	if (pCpu->pCurInstr->opcode == OP_LIDT)
2456	CPUMSetGuestIDTR(pVM, dtr32.uAddr, dtr32.cb);
2457	else
2458	CPUMSetGuestGDTR(pVM, dtr32.uAddr, dtr32.cb);
2459
2460	return VINF_SUCCESS;
2461	}
2462	#endif
2463
2464
2465	#ifdef IN_RC
2466	/**
2467	* STI Emulation.
2468	*
2469	* @remark the instruction following sti is guaranteed to be executed before any interrupts are dispatched
2470	*/
2471	static int emInterpretSti(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2472	{
2473	PPATMGCSTATE pGCState = PATMQueryGCState(pVM);
2474
2475	if(!pGCState)
2476	{
2477	Assert(pGCState);
2478	return VERR_EM_INTERPRETER;
2479	}
2480	pGCState->uVMFlags \|= X86_EFL_IF;
2481
2482	Assert(pRegFrame->eflags.u32 & X86_EFL_IF);
2483	Assert(pvFault == SELMToFlat(pVM, DIS_SELREG_CS, pRegFrame, (RTGCPTR)pRegFrame->rip));
2484
2485	pVM->em.s.GCPtrInhibitInterrupts = pRegFrame->eip + pCpu->opsize;
2486	VM_FF_SET(pVM, VM_FF_INHIBIT_INTERRUPTS);
2487
2488	return VINF_SUCCESS;
2489	}
2490	#endif /* IN_RC */
2491
2492
2493	/**
2494	* HLT Emulation.
2495	*/
2496	static int emInterpretHlt(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2497	{
2498	return VINF_EM_HALT;
2499	}
2500
2501
2502	/**
2503	* Interpret RDTSC
2504	*
2505	* @returns VBox status code.
2506	* @param pVM The VM handle.
2507	* @param pRegFrame The register frame.
2508	*
2509	*/
2510	VMMDECL(int) EMInterpretRdtsc(PVM pVM, PCPUMCTXCORE pRegFrame)
2511	{
2512	unsigned uCR4 = CPUMGetGuestCR4(pVM);
2513
2514	if (uCR4 & X86_CR4_TSD)
2515	return VERR_EM_INTERPRETER; /* genuine #GP */
2516
2517	uint64_t uTicks = TMCpuTickGet(pVM);
2518
2519	/* Same behaviour in 32 & 64 bits mode */
2520	pRegFrame->rax = (uint32_t)uTicks;
2521	pRegFrame->rdx = (uTicks >> 32ULL);
2522
2523	return VINF_SUCCESS;
2524	}
2525
2526	VMMDECL(int) EMInterpretRdtscp(PVM pVM, PCPUMCTX pCtx)
2527	{
2528	unsigned uCR4 = CPUMGetGuestCR4(pVM);
2529
2530	if (!CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
2531	{
2532	AssertFailed();
2533	return VERR_EM_INTERPRETER; /* genuine #UD */
2534	}
2535
2536	if (uCR4 & X86_CR4_TSD)
2537	return VERR_EM_INTERPRETER; /* genuine #GP */
2538
2539	uint64_t uTicks = TMCpuTickGet(pVM);
2540
2541	/* Same behaviour in 32 & 64 bits mode */
2542	pCtx->rax = (uint32_t)uTicks;
2543	pCtx->rdx = (uTicks >> 32ULL);
2544	/* Low dword of the TSC_AUX msr only. */
2545	pCtx->rcx = (uint32_t)CPUMGetGuestMsr(pVM, MSR_K8_TSC_AUX);
2546
2547	return VINF_SUCCESS;
2548	}
2549
2550	/**
2551	* RDTSC Emulation.
2552	*/
2553	static int emInterpretRdtsc(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2554	{
2555	return EMInterpretRdtsc(pVM, pRegFrame);
2556	}
2557
2558
2559	/**
2560	* MONITOR Emulation.
2561	*/
2562	static int emInterpretMonitor(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2563	{
2564	uint32_t u32Dummy, u32ExtFeatures, cpl;
2565
2566	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
2567	if (pRegFrame->ecx != 0)
2568	return VERR_EM_INTERPRETER; /* illegal value. */
2569
2570	/* Get the current privilege level. */
2571	cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2572	if (cpl != 0)
2573	return VERR_EM_INTERPRETER; /* supervisor only */
2574
2575	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
2576	if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
2577	return VERR_EM_INTERPRETER; /* not supported */
2578
2579	return VINF_SUCCESS;
2580	}
2581
2582
2583	/**
2584	* MWAIT Emulation.
2585	*/
2586	static int emInterpretMWait(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2587	{
2588	uint32_t u32Dummy, u32ExtFeatures, cpl;
2589
2590	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
2591	if (pRegFrame->ecx != 0)
2592	return VERR_EM_INTERPRETER; /* illegal value. */
2593
2594	/* Get the current privilege level. */
2595	cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2596	if (cpl != 0)
2597	return VERR_EM_INTERPRETER; /* supervisor only */
2598
2599	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
2600	if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
2601	return VERR_EM_INTERPRETER; /* not supported */
2602
2603	/** @todo not completely correct */
2604	return VINF_EM_HALT;
2605	}
2606
2607
2608	#ifdef LOG_ENABLED
2609	static const char *emMSRtoString(uint32_t uMsr)
2610	{
2611	switch (uMsr)
2612	{
2613	case MSR_IA32_APICBASE:
2614	return "MSR_IA32_APICBASE";
2615	case MSR_IA32_CR_PAT:
2616	return "MSR_IA32_CR_PAT";
2617	case MSR_IA32_SYSENTER_CS:
2618	return "MSR_IA32_SYSENTER_CS";
2619	case MSR_IA32_SYSENTER_EIP:
2620	return "MSR_IA32_SYSENTER_EIP";
2621	case MSR_IA32_SYSENTER_ESP:
2622	return "MSR_IA32_SYSENTER_ESP";
2623	case MSR_K6_EFER:
2624	return "MSR_K6_EFER";
2625	case MSR_K8_SF_MASK:
2626	return "MSR_K8_SF_MASK";
2627	case MSR_K6_STAR:
2628	return "MSR_K6_STAR";
2629	case MSR_K8_LSTAR:
2630	return "MSR_K8_LSTAR";
2631	case MSR_K8_CSTAR:
2632	return "MSR_K8_CSTAR";
2633	case MSR_K8_FS_BASE:
2634	return "MSR_K8_FS_BASE";
2635	case MSR_K8_GS_BASE:
2636	return "MSR_K8_GS_BASE";
2637	case MSR_K8_KERNEL_GS_BASE:
2638	return "MSR_K8_KERNEL_GS_BASE";
2639	case MSR_K8_TSC_AUX:
2640	return "MSR_K8_TSC_AUX";
2641	case MSR_IA32_BIOS_SIGN_ID:
2642	return "Unsupported MSR_IA32_BIOS_SIGN_ID";
2643	case MSR_IA32_PLATFORM_ID:
2644	return "Unsupported MSR_IA32_PLATFORM_ID";
2645	case MSR_IA32_BIOS_UPDT_TRIG:
2646	return "Unsupported MSR_IA32_BIOS_UPDT_TRIG";
2647	case MSR_IA32_TSC:
2648	return "Unsupported MSR_IA32_TSC";
2649	case MSR_IA32_MTRR_CAP:
2650	return "Unsupported MSR_IA32_MTRR_CAP";
2651	case MSR_IA32_MCP_CAP:
2652	return "Unsupported MSR_IA32_MCP_CAP";
2653	case MSR_IA32_MCP_STATUS:
2654	return "Unsupported MSR_IA32_MCP_STATUS";
2655	case MSR_IA32_MCP_CTRL:
2656	return "Unsupported MSR_IA32_MCP_CTRL";
2657	case MSR_IA32_MTRR_DEF_TYPE:
2658	return "Unsupported MSR_IA32_MTRR_DEF_TYPE";
2659	case MSR_K7_EVNTSEL0:
2660	return "Unsupported MSR_K7_EVNTSEL0";
2661	case MSR_K7_EVNTSEL1:
2662	return "Unsupported MSR_K7_EVNTSEL1";
2663	case MSR_K7_EVNTSEL2:
2664	return "Unsupported MSR_K7_EVNTSEL2";
2665	case MSR_K7_EVNTSEL3:
2666	return "Unsupported MSR_K7_EVNTSEL3";
2667	case MSR_IA32_MC0_CTL:
2668	return "Unsupported MSR_IA32_MC0_CTL";
2669	case MSR_IA32_MC0_STATUS:
2670	return "Unsupported MSR_IA32_MC0_STATUS";
2671	}
2672	return "Unknown MSR";
2673	}
2674	#endif /* LOG_ENABLED */
2675
2676
2677	/**
2678	* Interpret RDMSR
2679	*
2680	* @returns VBox status code.
2681	* @param pVM The VM handle.
2682	* @param pRegFrame The register frame.
2683	*
2684	*/
2685	VMMDECL(int) EMInterpretRdmsr(PVM pVM, PCPUMCTXCORE pRegFrame)
2686	{
2687	uint32_t u32Dummy, u32Features, cpl;
2688	uint64_t val;
2689	CPUMCTX *pCtx;
2690	int rc = VINF_SUCCESS;
2691
2692	/** @todo According to the Intel manuals, there's a REX version of RDMSR that is slightly different.
2693	* That version clears the high dwords of both RDX & RAX */
2694	pCtx = CPUMQueryGuestCtxPtr(pVM);
2695
2696	/* Get the current privilege level. */
2697	cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2698	if (cpl != 0)
2699	return VERR_EM_INTERPRETER; /* supervisor only */
2700
2701	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2702	if (!(u32Features & X86_CPUID_FEATURE_EDX_MSR))
2703	return VERR_EM_INTERPRETER; /* not supported */
2704
2705	switch (pRegFrame->ecx)
2706	{
2707	case MSR_IA32_APICBASE:
2708	rc = PDMApicGetBase(pVM, &val);
2709	AssertRC(rc);
2710	break;
2711
2712	case MSR_IA32_CR_PAT:
2713	val = pCtx->msrPAT;
2714	break;
2715
2716	case MSR_IA32_SYSENTER_CS:
2717	val = pCtx->SysEnter.cs;
2718	break;
2719
2720	case MSR_IA32_SYSENTER_EIP:
2721	val = pCtx->SysEnter.eip;
2722	break;
2723
2724	case MSR_IA32_SYSENTER_ESP:
2725	val = pCtx->SysEnter.esp;
2726	break;
2727
2728	case MSR_K6_EFER:
2729	val = pCtx->msrEFER;
2730	break;
2731
2732	case MSR_K8_SF_MASK:
2733	val = pCtx->msrSFMASK;
2734	break;
2735
2736	case MSR_K6_STAR:
2737	val = pCtx->msrSTAR;
2738	break;
2739
2740	case MSR_K8_LSTAR:
2741	val = pCtx->msrLSTAR;
2742	break;
2743
2744	case MSR_K8_CSTAR:
2745	val = pCtx->msrCSTAR;
2746	break;
2747
2748	case MSR_K8_FS_BASE:
2749	val = pCtx->fsHid.u64Base;
2750	break;
2751
2752	case MSR_K8_GS_BASE:
2753	val = pCtx->gsHid.u64Base;
2754	break;
2755
2756	case MSR_K8_KERNEL_GS_BASE:
2757	val = pCtx->msrKERNELGSBASE;
2758	break;
2759
2760	case MSR_K8_TSC_AUX:
2761	val = CPUMGetGuestMsr(pVM, MSR_K8_TSC_AUX);
2762	break;
2763
2764	#if 0 /def IN_RING0 /
2765	case MSR_IA32_PLATFORM_ID:
2766	case MSR_IA32_BIOS_SIGN_ID:
2767	if (CPUMGetCPUVendor(pVM) == CPUMCPUVENDOR_INTEL)
2768	{
2769	/* Available since the P6 family. VT-x implies that this feature is present. */
2770	if (pRegFrame->ecx == MSR_IA32_PLATFORM_ID)
2771	val = ASMRdMsr(MSR_IA32_PLATFORM_ID);
2772	else
2773	if (pRegFrame->ecx == MSR_IA32_BIOS_SIGN_ID)
2774	val = ASMRdMsr(MSR_IA32_BIOS_SIGN_ID);
2775	break;
2776	}
2777	/* no break */
2778	#endif
2779	default:
2780	/* In X2APIC specification this range is reserved for APIC control. */
2781	if ((pRegFrame->ecx >= MSR_IA32_APIC_START) && (pRegFrame->ecx < MSR_IA32_APIC_END))
2782	rc = PDMApicReadMSR(pVM, VMMGetCpuId(pVM), pRegFrame->ecx, &val);
2783	else
2784	/* We should actually trigger a #GP here, but don't as that might cause more trouble. */
2785	val = 0;
2786	break;
2787	}
2788	LogFlow(("EMInterpretRdmsr %s (%x) -> val=%RX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx, val));
2789	if (rc == VINF_SUCCESS)
2790	{
2791	pRegFrame->rax = (uint32_t) val;
2792	pRegFrame->rdx = (uint32_t) (val >> 32ULL);
2793	}
2794	return rc;
2795	}
2796
2797
2798	/**
2799	* RDMSR Emulation.
2800	*/
2801	static int emInterpretRdmsr(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2802	{
2803	/* Note: the Intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
2804	Assert(!(pCpu->prefix & PREFIX_REX));
2805	return EMInterpretRdmsr(pVM, pRegFrame);
2806	}
2807
2808
2809	/**
2810	* Interpret WRMSR
2811	*
2812	* @returns VBox status code.
2813	* @param pVM The VM handle.
2814	* @param pRegFrame The register frame.
2815	*/
2816	VMMDECL(int) EMInterpretWrmsr(PVM pVM, PCPUMCTXCORE pRegFrame)
2817	{
2818	uint32_t u32Dummy, u32Features, cpl;
2819	uint64_t val;
2820	CPUMCTX *pCtx;
2821
2822	/* Note: works the same in 32 and 64 bits modes. */
2823	pCtx = CPUMQueryGuestCtxPtr(pVM);
2824
2825	/* Get the current privilege level. */
2826	cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2827	if (cpl != 0)
2828	return VERR_EM_INTERPRETER; /* supervisor only */
2829
2830	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2831	if (!(u32Features & X86_CPUID_FEATURE_EDX_MSR))
2832	return VERR_EM_INTERPRETER; /* not supported */
2833
2834	val = RT_MAKE_U64(pRegFrame->eax, pRegFrame->edx);
2835	LogFlow(("EMInterpretWrmsr %s (%x) val=%RX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx, val));
2836	switch (pRegFrame->ecx)
2837	{
2838	case MSR_IA32_APICBASE:
2839	{
2840	int rc = PDMApicSetBase(pVM, val);
2841	AssertRC(rc);
2842	break;
2843	}
2844
2845	case MSR_IA32_CR_PAT:
2846	pCtx->msrPAT = val;
2847	break;
2848
2849	case MSR_IA32_SYSENTER_CS:
2850	pCtx->SysEnter.cs = val & 0xffff; /* 16 bits selector */
2851	break;
2852
2853	case MSR_IA32_SYSENTER_EIP:
2854	pCtx->SysEnter.eip = val;
2855	break;
2856
2857	case MSR_IA32_SYSENTER_ESP:
2858	pCtx->SysEnter.esp = val;
2859	break;
2860
2861	case MSR_K6_EFER:
2862	{
2863	uint64_t uMask = 0;
2864	uint64_t oldval = pCtx->msrEFER;
2865
2866	/* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
2867	CPUMGetGuestCpuId(pVM, 0x80000001, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2868	if (u32Features & X86_CPUID_AMD_FEATURE_EDX_NX)
2869	uMask \|= MSR_K6_EFER_NXE;
2870	if (u32Features & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE)
2871	uMask \|= MSR_K6_EFER_LME;
2872	if (u32Features & X86_CPUID_AMD_FEATURE_EDX_SEP)
2873	uMask \|= MSR_K6_EFER_SCE;
2874	if (u32Features & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
2875	uMask \|= MSR_K6_EFER_FFXSR;
2876
2877	/* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
2878	if ( ((pCtx->msrEFER & MSR_K6_EFER_LME) != (val & uMask & MSR_K6_EFER_LME))
2879	&& (pCtx->cr0 & X86_CR0_PG))
2880	{
2881	AssertMsgFailed(("Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
2882	return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
2883	}
2884
2885	/* There are a few more: e.g. MSR_K6_EFER_LMSLE */
2886	AssertMsg(!(val & ~(MSR_K6_EFER_NXE\|MSR_K6_EFER_LME\|MSR_K6_EFER_LMA /* ignored anyway */ \|MSR_K6_EFER_SCE\|MSR_K6_EFER_FFXSR)), ("Unexpected value %RX64\n", val));
2887	pCtx->msrEFER = (pCtx->msrEFER & ~uMask) \| (val & uMask);
2888
2889	/* AMD64 Architecture Programmer's Manual: 15.15 TLB Control; flush the TLB if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
2890	if ((oldval & (MSR_K6_EFER_NXE\|MSR_K6_EFER_LME\|MSR_K6_EFER_LMA)) != (pCtx->msrEFER & (MSR_K6_EFER_NXE\|MSR_K6_EFER_LME\|MSR_K6_EFER_LMA)))
2891	HWACCMFlushTLB(pVM);
2892
2893	break;
2894	}
2895
2896	case MSR_K8_SF_MASK:
2897	pCtx->msrSFMASK = val;
2898	break;
2899
2900	case MSR_K6_STAR:
2901	pCtx->msrSTAR = val;
2902	break;
2903
2904	case MSR_K8_LSTAR:
2905	pCtx->msrLSTAR = val;
2906	break;
2907
2908	case MSR_K8_CSTAR:
2909	pCtx->msrCSTAR = val;
2910	break;
2911
2912	case MSR_K8_FS_BASE:
2913	pCtx->fsHid.u64Base = val;
2914	break;
2915
2916	case MSR_K8_GS_BASE:
2917	pCtx->gsHid.u64Base = val;
2918	break;
2919
2920	case MSR_K8_KERNEL_GS_BASE:
2921	pCtx->msrKERNELGSBASE = val;
2922	break;
2923
2924	case MSR_K8_TSC_AUX:
2925	CPUMSetGuestMsr(pVM, MSR_K8_TSC_AUX, val);
2926	break;
2927
2928	default:
2929	/* In X2APIC specification this range is reserved for APIC control. */
2930	if ((pRegFrame->ecx >= MSR_IA32_APIC_START) && (pRegFrame->ecx < MSR_IA32_APIC_END))
2931	return PDMApicWriteMSR(pVM, VMMGetCpuId(pVM), pRegFrame->ecx, val);
2932
2933	/* We should actually trigger a #GP here, but don't as that might cause more trouble. */
2934	break;
2935	}
2936	return VINF_SUCCESS;
2937	}
2938
2939
2940	/**
2941	* WRMSR Emulation.
2942	*/
2943	static int emInterpretWrmsr(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2944	{
2945	return EMInterpretWrmsr(pVM, pRegFrame);
2946	}
2947
2948
2949	/**
2950	* Internal worker.
2951	* @copydoc EMInterpretInstructionCPU
2952	*/
2953	DECLINLINE(int) emInterpretInstructionCPU(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2954	{
2955	Assert(pcbSize);
2956	*pcbSize = 0;
2957
2958	/*
2959	* Only supervisor guest code!!
2960	* And no complicated prefixes.
2961	*/
2962	/* Get the current privilege level. */
2963	uint32_t cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2964	if ( cpl != 0
2965	&& pCpu->pCurInstr->opcode != OP_RDTSC) /* rdtsc requires emulation in ring 3 as well */
2966	{
2967	Log(("WARNING: refusing instruction emulation for user-mode code!!\n"));
2968	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedUserMode));
2969	return VERR_EM_INTERPRETER;
2970	}
2971
2972	#ifdef IN_RC
2973	if ( (pCpu->prefix & (PREFIX_REPNE \| PREFIX_REP))
2974	\|\| ( (pCpu->prefix & PREFIX_LOCK)
2975	&& pCpu->pCurInstr->opcode != OP_CMPXCHG
2976	&& pCpu->pCurInstr->opcode != OP_CMPXCHG8B
2977	&& pCpu->pCurInstr->opcode != OP_XADD
2978	&& pCpu->pCurInstr->opcode != OP_OR
2979	&& pCpu->pCurInstr->opcode != OP_BTR
2980	)
2981	)
2982	#else
2983	if ( (pCpu->prefix & PREFIX_REPNE)
2984	\|\| ( (pCpu->prefix & PREFIX_REP)
2985	&& pCpu->pCurInstr->opcode != OP_STOSWD
2986	)
2987	\|\| ( (pCpu->prefix & PREFIX_LOCK)
2988	&& pCpu->pCurInstr->opcode != OP_OR
2989	&& pCpu->pCurInstr->opcode != OP_BTR
2990	&& pCpu->pCurInstr->opcode != OP_CMPXCHG
2991	&& pCpu->pCurInstr->opcode != OP_CMPXCHG8B
2992	)
2993	)
2994	#endif
2995	{
2996	//Log(("EMInterpretInstruction: wrong prefix!!\n"));
2997	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedPrefix));
2998	return VERR_EM_INTERPRETER;
2999	}
3000
3001	#if HC_ARCH_BITS == 32
3002	/*
3003	* Unable to emulate most >4 bytes accesses in 32 bits mode.
3004	* Whitelisted instructions are safe.
3005	*/
3006	if ( pCpu->param1.size > 4
3007	&& CPUMIsGuestIn64BitCode(pVM, pRegFrame))
3008	{
3009	uint32_t uOpCode = pCpu->pCurInstr->opcode;
3010	if ( uOpCode != OP_STOSWD
3011	&& uOpCode != OP_MOV
3012	&& uOpCode != OP_CMPXCHG8B
3013	&& uOpCode != OP_XCHG
3014	&& uOpCode != OP_BTS
3015	&& uOpCode != OP_BTR
3016	&& uOpCode != OP_BTC
3017	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL_IN_R0
3018	&& uOpCode != OP_CMPXCHG /* solaris */
3019	&& uOpCode != OP_AND /* windows */
3020	&& uOpCode != OP_OR /* windows */
3021	&& uOpCode != OP_XOR /* because we can */
3022	&& uOpCode != OP_ADD /* windows (dripple) */
3023	&& uOpCode != OP_ADC /* because we can */
3024	&& uOpCode != OP_SUB /* because we can */
3025	/** @todo OP_BTS or is that a different kind of failure? */
3026	# endif
3027	)
3028	{
3029	# ifdef VBOX_WITH_STATISTICS
3030	switch (pCpu->pCurInstr->opcode)
3031	{
3032	# define INTERPRET_FAILED_CASE(opcode, Instr) \
3033	case opcode: STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); break;
3034	INTERPRET_FAILED_CASE(OP_XCHG,Xchg);
3035	INTERPRET_FAILED_CASE(OP_DEC,Dec);
3036	INTERPRET_FAILED_CASE(OP_INC,Inc);
3037	INTERPRET_FAILED_CASE(OP_POP,Pop);
3038	INTERPRET_FAILED_CASE(OP_OR, Or);
3039	INTERPRET_FAILED_CASE(OP_XOR,Xor);
3040	INTERPRET_FAILED_CASE(OP_AND,And);
3041	INTERPRET_FAILED_CASE(OP_MOV,Mov);
3042	INTERPRET_FAILED_CASE(OP_STOSWD,StosWD);
3043	INTERPRET_FAILED_CASE(OP_INVLPG,InvlPg);
3044	INTERPRET_FAILED_CASE(OP_CPUID,CpuId);
3045	INTERPRET_FAILED_CASE(OP_MOV_CR,MovCRx);
3046	INTERPRET_FAILED_CASE(OP_MOV_DR,MovDRx);
3047	INTERPRET_FAILED_CASE(OP_LLDT,LLdt);
3048	INTERPRET_FAILED_CASE(OP_LIDT,LIdt);
3049	INTERPRET_FAILED_CASE(OP_LGDT,LGdt);
3050	INTERPRET_FAILED_CASE(OP_LMSW,Lmsw);
3051	INTERPRET_FAILED_CASE(OP_CLTS,Clts);
3052	INTERPRET_FAILED_CASE(OP_MONITOR,Monitor);
3053	INTERPRET_FAILED_CASE(OP_MWAIT,MWait);
3054	INTERPRET_FAILED_CASE(OP_RDMSR,Rdmsr);
3055	INTERPRET_FAILED_CASE(OP_WRMSR,Wrmsr);
3056	INTERPRET_FAILED_CASE(OP_ADD,Add);
3057	INTERPRET_FAILED_CASE(OP_SUB,Sub);
3058	INTERPRET_FAILED_CASE(OP_ADC,Adc);
3059	INTERPRET_FAILED_CASE(OP_BTR,Btr);
3060	INTERPRET_FAILED_CASE(OP_BTS,Bts);
3061	INTERPRET_FAILED_CASE(OP_BTC,Btc);
3062	INTERPRET_FAILED_CASE(OP_RDTSC,Rdtsc);
3063	INTERPRET_FAILED_CASE(OP_CMPXCHG, CmpXchg);
3064	INTERPRET_FAILED_CASE(OP_STI, Sti);
3065	INTERPRET_FAILED_CASE(OP_XADD,XAdd);
3066	INTERPRET_FAILED_CASE(OP_CMPXCHG8B,CmpXchg8b);
3067	INTERPRET_FAILED_CASE(OP_HLT, Hlt);
3068	INTERPRET_FAILED_CASE(OP_IRET,Iret);
3069	INTERPRET_FAILED_CASE(OP_WBINVD,WbInvd);
3070	INTERPRET_FAILED_CASE(OP_MOVNTPS,MovNTPS);
3071	# undef INTERPRET_FAILED_CASE
3072	default:
3073	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedMisc));
3074	break;
3075	}
3076	# endif /* VBOX_WITH_STATISTICS */
3077	return VERR_EM_INTERPRETER;
3078	}
3079	}
3080	#endif
3081
3082	int rc;
3083	#if (defined(VBOX_STRICT) \|\| defined(LOG_ENABLED))
3084	LogFlow(("emInterpretInstructionCPU %s\n", emGetMnemonic(pCpu)));
3085	#endif
3086	switch (pCpu->pCurInstr->opcode)
3087	{
3088	# define INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
3089	case opcode:\
3090	if (pCpu->prefix & PREFIX_LOCK) \
3091	rc = emInterpretLock##InstrFn(pVM, pCpu, pRegFrame, pvFault, pcbSize, pfnEmulateLock); \
3092	else \
3093	rc = emInterpret##InstrFn(pVM, pCpu, pRegFrame, pvFault, pcbSize, pfnEmulate); \
3094	if (RT_SUCCESS(rc)) \
3095	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3096	else \
3097	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3098	return rc
3099	#define INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate) \
3100	case opcode:\
3101	rc = emInterpret##InstrFn(pVM, pCpu, pRegFrame, pvFault, pcbSize, pfnEmulate); \
3102	if (RT_SUCCESS(rc)) \
3103	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3104	else \
3105	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3106	return rc
3107
3108	#define INTERPRET_CASE_EX_PARAM2(opcode, Instr, InstrFn, pfnEmulate) \
3109	INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate)
3110	#define INTERPRET_CASE_EX_LOCK_PARAM2(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
3111	INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock)
3112
3113	#define INTERPRET_CASE(opcode, Instr) \
3114	case opcode:\
3115	rc = emInterpret##Instr(pVM, pCpu, pRegFrame, pvFault, pcbSize); \
3116	if (RT_SUCCESS(rc)) \
3117	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3118	else \
3119	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3120	return rc
3121
3122	#define INTERPRET_CASE_EX_DUAL_PARAM2(opcode, Instr, InstrFn) \
3123	case opcode:\
3124	rc = emInterpret##InstrFn(pVM, pCpu, pRegFrame, pvFault, pcbSize); \
3125	if (RT_SUCCESS(rc)) \
3126	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3127	else \
3128	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3129	return rc
3130
3131	#define INTERPRET_STAT_CASE(opcode, Instr) \
3132	case opcode: STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); return VERR_EM_INTERPRETER;
3133
3134	INTERPRET_CASE(OP_XCHG,Xchg);
3135	INTERPRET_CASE_EX_PARAM2(OP_DEC,Dec, IncDec, EMEmulateDec);
3136	INTERPRET_CASE_EX_PARAM2(OP_INC,Inc, IncDec, EMEmulateInc);
3137	INTERPRET_CASE(OP_POP,Pop);
3138	INTERPRET_CASE_EX_LOCK_PARAM3(OP_OR, Or, OrXorAnd, EMEmulateOr, EMEmulateLockOr);
3139	INTERPRET_CASE_EX_PARAM3(OP_XOR,Xor, OrXorAnd, EMEmulateXor);
3140	INTERPRET_CASE_EX_PARAM3(OP_AND,And, OrXorAnd, EMEmulateAnd);
3141	INTERPRET_CASE(OP_MOV,Mov);
3142	#ifndef IN_RC
3143	INTERPRET_CASE(OP_STOSWD,StosWD);
3144	#endif
3145	INTERPRET_CASE(OP_INVLPG,InvlPg);
3146	INTERPRET_CASE(OP_CPUID,CpuId);
3147	INTERPRET_CASE(OP_MOV_CR,MovCRx);
3148	INTERPRET_CASE(OP_MOV_DR,MovDRx);
3149	INTERPRET_CASE(OP_LLDT,LLdt);
3150	#ifdef IN_RING0
3151	INTERPRET_CASE_EX_DUAL_PARAM2(OP_LIDT, LIdt, LIGdt);
3152	INTERPRET_CASE_EX_DUAL_PARAM2(OP_LGDT, LGdt, LIGdt);
3153	#endif
3154	INTERPRET_CASE(OP_LMSW,Lmsw);
3155	#ifdef EM_EMULATE_SMSW
3156	INTERPRET_CASE(OP_SMSW,Smsw);
3157	#endif
3158	INTERPRET_CASE(OP_CLTS,Clts);
3159	INTERPRET_CASE(OP_MONITOR, Monitor);
3160	INTERPRET_CASE(OP_MWAIT, MWait);
3161	INTERPRET_CASE(OP_RDMSR, Rdmsr);
3162	INTERPRET_CASE(OP_WRMSR, Wrmsr);
3163	INTERPRET_CASE_EX_PARAM3(OP_ADD,Add, AddSub, EMEmulateAdd);
3164	INTERPRET_CASE_EX_PARAM3(OP_SUB,Sub, AddSub, EMEmulateSub);
3165	INTERPRET_CASE(OP_ADC,Adc);
3166	INTERPRET_CASE_EX_LOCK_PARAM2(OP_BTR,Btr, BitTest, EMEmulateBtr, EMEmulateLockBtr);
3167	INTERPRET_CASE_EX_PARAM2(OP_BTS,Bts, BitTest, EMEmulateBts);
3168	INTERPRET_CASE_EX_PARAM2(OP_BTC,Btc, BitTest, EMEmulateBtc);
3169	INTERPRET_CASE(OP_RDTSC,Rdtsc);
3170	INTERPRET_CASE(OP_CMPXCHG, CmpXchg);
3171	#ifdef IN_RC
3172	INTERPRET_CASE(OP_STI,Sti);
3173	INTERPRET_CASE(OP_XADD, XAdd);
3174	#endif
3175	INTERPRET_CASE(OP_CMPXCHG8B, CmpXchg8b);
3176	INTERPRET_CASE(OP_HLT,Hlt);
3177	INTERPRET_CASE(OP_IRET,Iret);
3178	INTERPRET_CASE(OP_WBINVD,WbInvd);
3179	#ifdef VBOX_WITH_STATISTICS
3180	#ifndef IN_RC
3181	INTERPRET_STAT_CASE(OP_XADD, XAdd);
3182	#endif
3183	INTERPRET_STAT_CASE(OP_MOVNTPS,MovNTPS);
3184	#endif
3185	default:
3186	Log3(("emInterpretInstructionCPU: opcode=%d\n", pCpu->pCurInstr->opcode));
3187	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedMisc));
3188	return VERR_EM_INTERPRETER;
3189	#undef INTERPRET_CASE_EX_PARAM2
3190	#undef INTERPRET_STAT_CASE
3191	#undef INTERPRET_CASE_EX
3192	#undef INTERPRET_CASE
3193	}
3194	AssertFailed();
3195	return VERR_INTERNAL_ERROR;
3196	}
3197
3198
3199	/**
3200	* Sets the PC for which interrupts should be inhibited.
3201	*
3202	* @param pVM The VM handle.
3203	* @param PC The PC.
3204	*/
3205	VMMDECL(void) EMSetInhibitInterruptsPC(PVM pVM, RTGCUINTPTR PC)
3206	{
3207	pVM->em.s.GCPtrInhibitInterrupts = PC;
3208	VM_FF_SET(pVM, VM_FF_INHIBIT_INTERRUPTS);
3209	}
3210
3211
3212	/**
3213	* Gets the PC for which interrupts should be inhibited.
3214	*
3215	* There are a few instructions which inhibits or delays interrupts
3216	* for the instruction following them. These instructions are:
3217	* - STI
3218	* - MOV SS, r/m16
3219	* - POP SS
3220	*
3221	* @returns The PC for which interrupts should be inhibited.
3222	* @param pVM VM handle.
3223	*
3224	*/
3225	VMMDECL(RTGCUINTPTR) EMGetInhibitInterruptsPC(PVM pVM)
3226	{
3227	return pVM->em.s.GCPtrInhibitInterrupts;
3228	}
3229

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source: vbox/trunk/src/VBox/VMM/VMMAll/EMAll.cpp@ 17212

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