EMAll.cpp@ 20406

Last change on this file since 20406 was 20406, checked in by vboxsync, 15 years ago
Removed obsolete REMR3ReplayInvalidatedPages
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1	/* $Id: EMAll.cpp 20406 2009-06-08 13:39:32Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor(/Manager) - All contexts
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_EM
26	#include <VBox/em.h>
27	#include <VBox/mm.h>
28	#include <VBox/selm.h>
29	#include <VBox/patm.h>
30	#include <VBox/csam.h>
31	#include <VBox/pgm.h>
32	#include <VBox/iom.h>
33	#include <VBox/stam.h>
34	#include "EMInternal.h"
35	#include <VBox/vm.h>
36	#include <VBox/vmm.h>
37	#include <VBox/hwaccm.h>
38	#include <VBox/tm.h>
39	#include <VBox/pdmapi.h>
40
41	#include <VBox/param.h>
42	#include <VBox/err.h>
43	#include <VBox/dis.h>
44	#include <VBox/disopcode.h>
45	#include <VBox/log.h>
46	#include <iprt/assert.h>
47	#include <iprt/asm.h>
48	#include <iprt/string.h>
49
50
51	/*******************************************************************************
52	* Defined Constants And Macros *
53	*******************************************************************************/
54	/** @def EM_ASSERT_FAULT_RETURN
55	* Safety check.
56	*
57	* Could in theory misfire on a cross page boundary access...
58	*
59	* Currently disabled because the CSAM (+ PATM) patch monitoring occasionally
60	* turns up an alias page instead of the original faulting one and annoying the
61	* heck out of anyone running a debug build. See @bugref{2609} and @bugref{1931}.
62	*/
63	#if 0
64	# define EM_ASSERT_FAULT_RETURN(expr, rc) AssertReturn(expr, rc)
65	#else
66	# define EM_ASSERT_FAULT_RETURN(expr, rc) do { } while (0)
67	#endif
68
69	/* Used to pass information during instruction disassembly. */
70	typedef struct
71	{
72	PVM pVM;
73	PVMCPU pVCpu;
74	} EMDISSTATE, *PEMDISSTATE;
75
76	/*******************************************************************************
77	* Internal Functions *
78	*******************************************************************************/
79	DECLINLINE(int) emInterpretInstructionCPU(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize);
80
81
82
83	/**
84	* Get the current execution manager status.
85	*
86	* @returns Current status.
87	* @param pVCpu The VMCPU to operate on.
88	*/
89	VMMDECL(EMSTATE) EMGetState(PVMCPU pVCpu)
90	{
91	return pVCpu->em.s.enmState;
92	}
93
94	/**
95	* Sets the current execution manager status. (use only when you know what you're doing!)
96	*
97	* @param pVCpu The VMCPU to operate on.
98	*/
99	VMMDECL(void) EMSetState(PVMCPU pVCpu, EMSTATE enmNewState)
100	{
101	/* Only allowed combination: */
102	Assert(pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI && enmNewState == EMSTATE_HALTED);
103	pVCpu->em.s.enmState = enmNewState;
104	}
105
106
107	#ifndef IN_RC
108
109	/**
110	* Read callback for disassembly function; supports reading bytes that cross a page boundary
111	*
112	* @returns VBox status code.
113	* @param pSrc GC source pointer
114	* @param pDest HC destination pointer
115	* @param cb Number of bytes to read
116	* @param dwUserdata Callback specific user data (pDISState)
117	*
118	*/
119	DECLCALLBACK(int) EMReadBytes(RTUINTPTR pSrc, uint8_t pDest, unsigned cb, void pvUserdata)
120	{
121	DISCPUSTATE pDISState = (DISCPUSTATE )pvUserdata;
122	PEMDISSTATE pState = (PEMDISSTATE)pDISState->apvUserData[0];
123	PVM pVM = pState->pVM;
124	PVMCPU pVCpu = pState->pVCpu;
125
126	# ifdef IN_RING0
127	int rc = PGMPhysSimpleReadGCPtr(pVCpu, pDest, pSrc, cb);
128	AssertMsgRC(rc, ("PGMPhysSimpleReadGCPtr failed for pSrc=%RGv cb=%x rc=%d\n", pSrc, cb, rc));
129	# else /* IN_RING3 */
130	if (!PATMIsPatchGCAddr(pVM, pSrc))
131	{
132	int rc = PGMPhysSimpleReadGCPtr(pVCpu, pDest, pSrc, cb);
133	AssertRC(rc);
134	}
135	else
136	{
137	for (uint32_t i = 0; i < cb; i++)
138	{
139	uint8_t opcode;
140	if (RT_SUCCESS(PATMR3QueryOpcode(pVM, (RTGCPTR)pSrc + i, &opcode)))
141	*(pDest+i) = opcode;
142
143	}
144	}
145	# endif /* IN_RING3 */
146	return VINF_SUCCESS;
147	}
148
149	DECLINLINE(int) emDisCoreOne(PVM pVM, PVMCPU pVCpu, DISCPUSTATE pDISState, RTGCUINTPTR InstrGC, uint32_t pOpsize)
150	{
151	EMDISSTATE State;
152
153	State.pVM = pVM;
154	State.pVCpu = pVCpu;
155
156	return DISCoreOneEx(InstrGC, pDISState->mode, EMReadBytes, &State, pDISState, pOpsize);
157	}
158
159	#else /* IN_RC */
160
161	DECLINLINE(int) emDisCoreOne(PVM pVM, PVMCPU pVCpu, DISCPUSTATE pDISState, RTGCUINTPTR InstrGC, uint32_t pOpsize)
162	{
163	NOREF(pVCpu);
164	NOREF(pVM);
165	return DISCoreOne(pDISState, InstrGC, pOpsize);
166	}
167
168	#endif /* IN_RC */
169
170
171	/**
172	* Disassembles one instruction.
173	*
174	* @returns VBox status code, see SELMToFlatEx and EMInterpretDisasOneEx for
175	* details.
176	* @retval VERR_INTERNAL_ERROR on DISCoreOneEx failure.
177	*
178	* @param pVM The VM handle.
179	* @param pVCpu The VMCPU handle.
180	* @param pCtxCore The context core (used for both the mode and instruction).
181	* @param pDISState Where to return the parsed instruction info.
182	* @param pcbInstr Where to return the instruction size. (optional)
183	*/
184	VMMDECL(int) EMInterpretDisasOne(PVM pVM, PVMCPU pVCpu, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pDISState, unsigned *pcbInstr)
185	{
186	RTGCPTR GCPtrInstr;
187	int rc = SELMToFlatEx(pVM, DIS_SELREG_CS, pCtxCore, pCtxCore->rip, 0, &GCPtrInstr);
188	if (RT_FAILURE(rc))
189	{
190	Log(("EMInterpretDisasOne: Failed to convert %RTsel:%RGv (cpl=%d) - rc=%Rrc !!\n",
191	pCtxCore->cs, (RTGCPTR)pCtxCore->rip, pCtxCore->ss & X86_SEL_RPL, rc));
192	return rc;
193	}
194	return EMInterpretDisasOneEx(pVM, pVCpu, (RTGCUINTPTR)GCPtrInstr, pCtxCore, pDISState, pcbInstr);
195	}
196
197
198	/**
199	* Disassembles one instruction.
200	*
201	* This is used by internally by the interpreter and by trap/access handlers.
202	*
203	* @returns VBox status code.
204	* @retval VERR_INTERNAL_ERROR on DISCoreOneEx failure.
205	*
206	* @param pVM The VM handle.
207	* @param pVCpu The VMCPU handle.
208	* @param GCPtrInstr The flat address of the instruction.
209	* @param pCtxCore The context core (used to determine the cpu mode).
210	* @param pDISState Where to return the parsed instruction info.
211	* @param pcbInstr Where to return the instruction size. (optional)
212	*/
213	VMMDECL(int) EMInterpretDisasOneEx(PVM pVM, PVMCPU pVCpu, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pDISState, unsigned *pcbInstr)
214	{
215	#ifndef IN_RC
216	EMDISSTATE State;
217
218	State.pVM = pVM;
219	State.pVCpu = pVCpu;
220	#endif
221
222	int rc = DISCoreOneEx(GCPtrInstr, SELMGetCpuModeFromSelector(pVM, pCtxCore->eflags, pCtxCore->cs, (PCPUMSELREGHID)&pCtxCore->csHid),
223	#ifdef IN_RC
224	NULL, NULL,
225	#else
226	EMReadBytes, &State,
227	#endif
228	pDISState, pcbInstr);
229	if (RT_SUCCESS(rc))
230	return VINF_SUCCESS;
231	AssertMsgFailed(("DISCoreOne failed to GCPtrInstr=%RGv rc=%Rrc\n", GCPtrInstr, rc));
232	return VERR_INTERNAL_ERROR;
233	}
234
235
236	/**
237	* Interprets the current instruction.
238	*
239	* @returns VBox status code.
240	* @retval VINF_* Scheduling instructions.
241	* @retval VERR_EM_INTERPRETER Something we can't cope with.
242	* @retval VERR_* Fatal errors.
243	*
244	* @param pVM The VM handle.
245	* @param pVCpu The VMCPU handle.
246	* @param pRegFrame The register frame.
247	* Updates the EIP if an instruction was executed successfully.
248	* @param pvFault The fault address (CR2).
249	* @param pcbSize Size of the write (if applicable).
250	*
251	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
252	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
253	* to worry about e.g. invalid modrm combinations (!)
254	*/
255	VMMDECL(int) EMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
256	{
257	RTGCPTR pbCode;
258
259	LogFlow(("EMInterpretInstruction %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
260	int rc = SELMToFlatEx(pVM, DIS_SELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
261	if (RT_SUCCESS(rc))
262	{
263	uint32_t cbOp;
264	DISCPUSTATE Cpu;
265	Cpu.mode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
266	rc = emDisCoreOne(pVM, pVCpu, &Cpu, (RTGCUINTPTR)pbCode, &cbOp);
267	if (RT_SUCCESS(rc))
268	{
269	Assert(cbOp == Cpu.opsize);
270	rc = EMInterpretInstructionCPU(pVM, pVCpu, &Cpu, pRegFrame, pvFault, pcbSize);
271	if (RT_SUCCESS(rc))
272	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
273
274	return rc;
275	}
276	}
277	return VERR_EM_INTERPRETER;
278	}
279
280
281	/**
282	* Interprets the current instruction using the supplied DISCPUSTATE structure.
283	*
284	* EIP is NOT updated!
285	*
286	* @returns VBox status code.
287	* @retval VINF_* Scheduling instructions. When these are returned, it
288	* starts to get a bit tricky to know whether code was
289	* executed or not... We'll address this when it becomes a problem.
290	* @retval VERR_EM_INTERPRETER Something we can't cope with.
291	* @retval VERR_* Fatal errors.
292	*
293	* @param pVM The VM handle.
294	* @param pVCpu The VMCPU handle.
295	* @param pDISState The disassembler cpu state for the instruction to be interpreted.
296	* @param pRegFrame The register frame. EIP is NOT changed!
297	* @param pvFault The fault address (CR2).
298	* @param pcbSize Size of the write (if applicable).
299	*
300	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
301	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
302	* to worry about e.g. invalid modrm combinations (!)
303	*
304	* @todo At this time we do NOT check if the instruction overwrites vital information.
305	* Make sure this can't happen!! (will add some assertions/checks later)
306	*/
307	VMMDECL(int) EMInterpretInstructionCPU(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
308	{
309	STAM_PROFILE_START(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Emulate), a);
310	int rc = emInterpretInstructionCPU(pVM, pVCpu, pDISState, pRegFrame, pvFault, pcbSize);
311	STAM_PROFILE_STOP(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Emulate), a);
312	if (RT_SUCCESS(rc))
313	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InterpretSucceeded));
314	else
315	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InterpretFailed));
316	return rc;
317	}
318
319
320	/**
321	* Interpret a port I/O instruction.
322	*
323	* @returns VBox status code suitable for scheduling.
324	* @param pVM The VM handle.
325	* @param pVCpu The VMCPU handle.
326	* @param pCtxCore The context core. This will be updated on successful return.
327	* @param pDISState The instruction to interpret.
328	* @param cbOp The size of the instruction.
329	* @remark This may raise exceptions.
330	*/
331	VMMDECL(int) EMInterpretPortIO(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, PDISCPUSTATE pDISState, uint32_t cbOp)
332	{
333	/*
334	* Hand it on to IOM.
335	*/
336	#ifdef IN_RC
337	int rc = IOMGCIOPortHandler(pVM, pCtxCore, pDISState);
338	if (IOM_SUCCESS(rc))
339	pCtxCore->rip += cbOp;
340	return rc;
341	#else
342	AssertReleaseMsgFailed(("not implemented\n"));
343	return VERR_NOT_IMPLEMENTED;
344	#endif
345	}
346
347
348	DECLINLINE(int) emRamRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCPTR GCPtrSrc, uint32_t cb)
349	{
350	#ifdef IN_RC
351	int rc = MMGCRamRead(pVM, pvDst, (void *)GCPtrSrc, cb);
352	if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
353	return rc;
354	/*
355	* The page pool cache may end up here in some cases because it
356	* flushed one of the shadow mappings used by the trapping
357	* instruction and it either flushed the TLB or the CPU reused it.
358	*/
359	#endif
360	return PGMPhysInterpretedReadNoHandlers(pVCpu, pCtxCore, pvDst, GCPtrSrc, cb, /fMayTrap/ false);
361	}
362
363
364	DECLINLINE(int) emRamWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, RTGCPTR GCPtrDst, const void *pvSrc, uint32_t cb)
365	{
366	#ifdef IN_RC
367	int rc = MMGCRamWrite(pVM, (void )(uintptr_t)GCPtrDst, (void )pvSrc, cb);
368	if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
369	return rc;
370	/*
371	* The page pool cache may end up here in some cases because it
372	* flushed one of the shadow mappings used by the trapping
373	* instruction and it either flushed the TLB or the CPU reused it.
374	* We want to play safe here, verifying that we've got write
375	* access doesn't cost us much (see PGMPhysGCPtr2GCPhys()).
376	*/
377	#endif
378	return PGMPhysInterpretedWriteNoHandlers(pVCpu, pCtxCore, GCPtrDst, pvSrc, cb, /fMayTrap/ false);
379	}
380
381
382	/** Convert sel:addr to a flat GC address. */
383	DECLINLINE(RTGCPTR) emConvertToFlatAddr(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pDISState, POP_PARAMETER pParam, RTGCPTR pvAddr)
384	{
385	DIS_SELREG enmPrefixSeg = DISDetectSegReg(pDISState, pParam);
386	return SELMToFlat(pVM, enmPrefixSeg, pRegFrame, pvAddr);
387	}
388
389
390	#if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
391	/**
392	* Get the mnemonic for the disassembled instruction.
393	*
394	* GC/R0 doesn't include the strings in the DIS tables because
395	* of limited space.
396	*/
397	static const char *emGetMnemonic(PDISCPUSTATE pDISState)
398	{
399	switch (pDISState->pCurInstr->opcode)
400	{
401	case OP_XCHG: return "Xchg";
402	case OP_DEC: return "Dec";
403	case OP_INC: return "Inc";
404	case OP_POP: return "Pop";
405	case OP_OR: return "Or";
406	case OP_AND: return "And";
407	case OP_MOV: return "Mov";
408	case OP_INVLPG: return "InvlPg";
409	case OP_CPUID: return "CpuId";
410	case OP_MOV_CR: return "MovCRx";
411	case OP_MOV_DR: return "MovDRx";
412	case OP_LLDT: return "LLdt";
413	case OP_LGDT: return "LGdt";
414	case OP_LIDT: return "LGdt";
415	case OP_CLTS: return "Clts";
416	case OP_MONITOR: return "Monitor";
417	case OP_MWAIT: return "MWait";
418	case OP_RDMSR: return "Rdmsr";
419	case OP_WRMSR: return "Wrmsr";
420	case OP_ADD: return "Add";
421	case OP_ADC: return "Adc";
422	case OP_SUB: return "Sub";
423	case OP_SBB: return "Sbb";
424	case OP_RDTSC: return "Rdtsc";
425	case OP_STI: return "Sti";
426	case OP_CLI: return "Cli";
427	case OP_XADD: return "XAdd";
428	case OP_HLT: return "Hlt";
429	case OP_IRET: return "Iret";
430	case OP_MOVNTPS: return "MovNTPS";
431	case OP_STOSWD: return "StosWD";
432	case OP_WBINVD: return "WbInvd";
433	case OP_XOR: return "Xor";
434	case OP_BTR: return "Btr";
435	case OP_BTS: return "Bts";
436	case OP_BTC: return "Btc";
437	case OP_LMSW: return "Lmsw";
438	case OP_SMSW: return "Smsw";
439	case OP_CMPXCHG: return pDISState->prefix & PREFIX_LOCK ? "Lock CmpXchg" : "CmpXchg";
440	case OP_CMPXCHG8B: return pDISState->prefix & PREFIX_LOCK ? "Lock CmpXchg8b" : "CmpXchg8b";
441
442	default:
443	Log(("Unknown opcode %d\n", pDISState->pCurInstr->opcode));
444	return "???";
445	}
446	}
447	#endif /* VBOX_STRICT \|\| LOG_ENABLED */
448
449
450	/**
451	* XCHG instruction emulation.
452	*/
453	static int emInterpretXchg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
454	{
455	OP_PARAMVAL param1, param2;
456
457	/* Source to make DISQueryParamVal read the register value - ugly hack */
458	int rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param1, &param1, PARAM_SOURCE);
459	if(RT_FAILURE(rc))
460	return VERR_EM_INTERPRETER;
461
462	rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param2, &param2, PARAM_SOURCE);
463	if(RT_FAILURE(rc))
464	return VERR_EM_INTERPRETER;
465
466	#ifdef IN_RC
467	if (TRPMHasTrap(pVCpu))
468	{
469	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
470	{
471	#endif
472	RTGCPTR pParam1 = 0, pParam2 = 0;
473	uint64_t valpar1, valpar2;
474
475	AssertReturn(pDISState->param1.size == pDISState->param2.size, VERR_EM_INTERPRETER);
476	switch(param1.type)
477	{
478	case PARMTYPE_IMMEDIATE: /* register type is translated to this one too */
479	valpar1 = param1.val.val64;
480	break;
481
482	case PARMTYPE_ADDRESS:
483	pParam1 = (RTGCPTR)param1.val.val64;
484	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDISState, &pDISState->param1, pParam1);
485	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
486	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
487	if (RT_FAILURE(rc))
488	{
489	AssertMsgFailed(("MMGCRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
490	return VERR_EM_INTERPRETER;
491	}
492	break;
493
494	default:
495	AssertFailed();
496	return VERR_EM_INTERPRETER;
497	}
498
499	switch(param2.type)
500	{
501	case PARMTYPE_ADDRESS:
502	pParam2 = (RTGCPTR)param2.val.val64;
503	pParam2 = emConvertToFlatAddr(pVM, pRegFrame, pDISState, &pDISState->param2, pParam2);
504	EM_ASSERT_FAULT_RETURN(pParam2 == pvFault, VERR_EM_INTERPRETER);
505	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar2, pParam2, param2.size);
506	if (RT_FAILURE(rc))
507	{
508	AssertMsgFailed(("MMGCRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
509	}
510	break;
511
512	case PARMTYPE_IMMEDIATE:
513	valpar2 = param2.val.val64;
514	break;
515
516	default:
517	AssertFailed();
518	return VERR_EM_INTERPRETER;
519	}
520
521	/* Write value of parameter 2 to parameter 1 (reg or memory address) */
522	if (pParam1 == 0)
523	{
524	Assert(param1.type == PARMTYPE_IMMEDIATE); /* register actually */
525	switch(param1.size)
526	{
527	case 1: //special case for AH etc
528	rc = DISWriteReg8(pRegFrame, pDISState->param1.base.reg_gen, (uint8_t )valpar2); break;
529	case 2: rc = DISWriteReg16(pRegFrame, pDISState->param1.base.reg_gen, (uint16_t)valpar2); break;
530	case 4: rc = DISWriteReg32(pRegFrame, pDISState->param1.base.reg_gen, (uint32_t)valpar2); break;
531	case 8: rc = DISWriteReg64(pRegFrame, pDISState->param1.base.reg_gen, valpar2); break;
532	default: AssertFailedReturn(VERR_EM_INTERPRETER);
533	}
534	if (RT_FAILURE(rc))
535	return VERR_EM_INTERPRETER;
536	}
537	else
538	{
539	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar2, param1.size);
540	if (RT_FAILURE(rc))
541	{
542	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
543	return VERR_EM_INTERPRETER;
544	}
545	}
546
547	/* Write value of parameter 1 to parameter 2 (reg or memory address) */
548	if (pParam2 == 0)
549	{
550	Assert(param2.type == PARMTYPE_IMMEDIATE); /* register actually */
551	switch(param2.size)
552	{
553	case 1: //special case for AH etc
554	rc = DISWriteReg8(pRegFrame, pDISState->param2.base.reg_gen, (uint8_t )valpar1); break;
555	case 2: rc = DISWriteReg16(pRegFrame, pDISState->param2.base.reg_gen, (uint16_t)valpar1); break;
556	case 4: rc = DISWriteReg32(pRegFrame, pDISState->param2.base.reg_gen, (uint32_t)valpar1); break;
557	case 8: rc = DISWriteReg64(pRegFrame, pDISState->param2.base.reg_gen, valpar1); break;
558	default: AssertFailedReturn(VERR_EM_INTERPRETER);
559	}
560	if (RT_FAILURE(rc))
561	return VERR_EM_INTERPRETER;
562	}
563	else
564	{
565	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam2, &valpar1, param2.size);
566	if (RT_FAILURE(rc))
567	{
568	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
569	return VERR_EM_INTERPRETER;
570	}
571	}
572
573	*pcbSize = param2.size;
574	return VINF_SUCCESS;
575	#ifdef IN_RC
576	}
577	}
578	#endif
579	return VERR_EM_INTERPRETER;
580	}
581
582
583	/**
584	* INC and DEC emulation.
585	*/
586	static int emInterpretIncDec(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
587	PFNEMULATEPARAM2 pfnEmulate)
588	{
589	OP_PARAMVAL param1;
590
591	int rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param1, &param1, PARAM_DEST);
592	if(RT_FAILURE(rc))
593	return VERR_EM_INTERPRETER;
594
595	#ifdef IN_RC
596	if (TRPMHasTrap(pVCpu))
597	{
598	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
599	{
600	#endif
601	RTGCPTR pParam1 = 0;
602	uint64_t valpar1;
603
604	if (param1.type == PARMTYPE_ADDRESS)
605	{
606	pParam1 = (RTGCPTR)param1.val.val64;
607	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDISState, &pDISState->param1, pParam1);
608	#ifdef IN_RC
609	/* Safety check (in theory it could cross a page boundary and fault there though) */
610	AssertReturn(pParam1 == pvFault, VERR_EM_INTERPRETER);
611	#endif
612	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
613	if (RT_FAILURE(rc))
614	{
615	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
616	return VERR_EM_INTERPRETER;
617	}
618	}
619	else
620	{
621	AssertFailed();
622	return VERR_EM_INTERPRETER;
623	}
624
625	uint32_t eflags;
626
627	eflags = pfnEmulate(&valpar1, param1.size);
628
629	/* Write result back */
630	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, param1.size);
631	if (RT_FAILURE(rc))
632	{
633	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
634	return VERR_EM_INTERPRETER;
635	}
636
637	/* Update guest's eflags and finish. */
638	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
639	\| (eflags & (X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
640
641	/* All done! */
642	*pcbSize = param1.size;
643	return VINF_SUCCESS;
644	#ifdef IN_RC
645	}
646	}
647	#endif
648	return VERR_EM_INTERPRETER;
649	}
650
651
652	/**
653	* POP Emulation.
654	*/
655	static int emInterpretPop(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
656	{
657	Assert(pDISState->mode != CPUMODE_64BIT); /** @todo check */
658	OP_PARAMVAL param1;
659	int rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param1, &param1, PARAM_DEST);
660	if(RT_FAILURE(rc))
661	return VERR_EM_INTERPRETER;
662
663	#ifdef IN_RC
664	if (TRPMHasTrap(pVCpu))
665	{
666	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
667	{
668	#endif
669	RTGCPTR pParam1 = 0;
670	uint32_t valpar1;
671	RTGCPTR pStackVal;
672
673	/* Read stack value first */
674	if (SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->ss, &pRegFrame->ssHid) == CPUMODE_16BIT)
675	return VERR_EM_INTERPRETER; /* No legacy 16 bits stuff here, please. */
676
677	/* Convert address; don't bother checking limits etc, as we only read here */
678	pStackVal = SELMToFlat(pVM, DIS_SELREG_SS, pRegFrame, (RTGCPTR)pRegFrame->esp);
679	if (pStackVal == 0)
680	return VERR_EM_INTERPRETER;
681
682	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pStackVal, param1.size);
683	if (RT_FAILURE(rc))
684	{
685	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
686	return VERR_EM_INTERPRETER;
687	}
688
689	if (param1.type == PARMTYPE_ADDRESS)
690	{
691	pParam1 = (RTGCPTR)param1.val.val64;
692
693	/* pop [esp+xx] uses esp after the actual pop! */
694	AssertCompile(USE_REG_ESP == USE_REG_SP);
695	if ( (pDISState->param1.flags & USE_BASE)
696	&& (pDISState->param1.flags & (USE_REG_GEN16\|USE_REG_GEN32))
697	&& pDISState->param1.base.reg_gen == USE_REG_ESP
698	)
699	pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + param1.size);
700
701	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDISState, &pDISState->param1, pParam1);
702	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault \|\| (RTGCPTR)pRegFrame->esp == pvFault, VERR_EM_INTERPRETER);
703	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, param1.size);
704	if (RT_FAILURE(rc))
705	{
706	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
707	return VERR_EM_INTERPRETER;
708	}
709
710	/* Update ESP as the last step */
711	pRegFrame->esp += param1.size;
712	}
713	else
714	{
715	#ifndef DEBUG_bird // annoying assertion.
716	AssertFailed();
717	#endif
718	return VERR_EM_INTERPRETER;
719	}
720
721	/* All done! */
722	*pcbSize = param1.size;
723	return VINF_SUCCESS;
724	#ifdef IN_RC
725	}
726	}
727	#endif
728	return VERR_EM_INTERPRETER;
729	}
730
731
732	/**
733	* XOR/OR/AND Emulation.
734	*/
735	static int emInterpretOrXorAnd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
736	PFNEMULATEPARAM3 pfnEmulate)
737	{
738	OP_PARAMVAL param1, param2;
739
740	int rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param1, &param1, PARAM_DEST);
741	if(RT_FAILURE(rc))
742	return VERR_EM_INTERPRETER;
743
744	rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param2, &param2, PARAM_SOURCE);
745	if(RT_FAILURE(rc))
746	return VERR_EM_INTERPRETER;
747
748	#ifdef IN_RC
749	if (TRPMHasTrap(pVCpu))
750	{
751	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
752	{
753	#endif
754	RTGCPTR pParam1;
755	uint64_t valpar1, valpar2;
756
757	if (pDISState->param1.size != pDISState->param2.size)
758	{
759	if (pDISState->param1.size < pDISState->param2.size)
760	{
761	AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDISState), (RTGCPTR)pRegFrame->rip, pDISState->param1.size, pDISState->param2.size)); /* should never happen! */
762	return VERR_EM_INTERPRETER;
763	}
764	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
765	pDISState->param2.size = pDISState->param1.size;
766	param2.size = param1.size;
767	}
768
769	/* The destination is always a virtual address */
770	if (param1.type == PARMTYPE_ADDRESS)
771	{
772	pParam1 = (RTGCPTR)param1.val.val64;
773	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDISState, &pDISState->param1, pParam1);
774	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
775	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
776	if (RT_FAILURE(rc))
777	{
778	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
779	return VERR_EM_INTERPRETER;
780	}
781	}
782	else
783	{
784	AssertFailed();
785	return VERR_EM_INTERPRETER;
786	}
787
788	/* Register or immediate data */
789	switch(param2.type)
790	{
791	case PARMTYPE_IMMEDIATE: /* both immediate data and register (ugly) */
792	valpar2 = param2.val.val64;
793	break;
794
795	default:
796	AssertFailed();
797	return VERR_EM_INTERPRETER;
798	}
799
800	LogFlow(("emInterpretOrXorAnd %s %RGv %RX64 - %RX64 size %d (%d)\n", emGetMnemonic(pDISState), pParam1, valpar1, valpar2, param2.size, param1.size));
801
802	/* Data read, emulate instruction. */
803	uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
804
805	LogFlow(("emInterpretOrXorAnd %s result %RX64\n", emGetMnemonic(pDISState), valpar1));
806
807	/* Update guest's eflags and finish. */
808	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
809	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
810
811	/* And write it back */
812	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, param1.size);
813	if (RT_SUCCESS(rc))
814	{
815	/* All done! */
816	*pcbSize = param2.size;
817	return VINF_SUCCESS;
818	}
819	#ifdef IN_RC
820	}
821	}
822	#endif
823	return VERR_EM_INTERPRETER;
824	}
825
826
827	/**
828	* LOCK XOR/OR/AND Emulation.
829	*/
830	static int emInterpretLockOrXorAnd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
831	uint32_t *pcbSize, PFNEMULATELOCKPARAM3 pfnEmulate)
832	{
833	void *pvParam1;
834	OP_PARAMVAL param1, param2;
835
836	#if HC_ARCH_BITS == 32
837	Assert(pDISState->param1.size <= 4);
838	#endif
839
840	int rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param1, &param1, PARAM_DEST);
841	if(RT_FAILURE(rc))
842	return VERR_EM_INTERPRETER;
843
844	rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param2, &param2, PARAM_SOURCE);
845	if(RT_FAILURE(rc))
846	return VERR_EM_INTERPRETER;
847
848	if (pDISState->param1.size != pDISState->param2.size)
849	{
850	AssertMsgReturn(pDISState->param1.size >= pDISState->param2.size, /* should never happen! */
851	("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDISState), (RTGCPTR)pRegFrame->rip, pDISState->param1.size, pDISState->param2.size),
852	VERR_EM_INTERPRETER);
853
854	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
855	pDISState->param2.size = pDISState->param1.size;
856	param2.size = param1.size;
857	}
858
859	#ifdef IN_RC
860	/* Safety check (in theory it could cross a page boundary and fault there though) */
861	Assert( TRPMHasTrap(pVCpu)
862	&& (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW));
863	EM_ASSERT_FAULT_RETURN(GCPtrPar1 == pvFault, VERR_EM_INTERPRETER);
864	#endif
865
866	/* Register and immediate data == PARMTYPE_IMMEDIATE */
867	AssertReturn(param2.type == PARMTYPE_IMMEDIATE, VERR_EM_INTERPRETER);
868	RTGCUINTREG ValPar2 = param2.val.val64;
869
870	/* The destination is always a virtual address */
871	AssertReturn(param1.type == PARMTYPE_ADDRESS, VERR_EM_INTERPRETER);
872
873	RTGCPTR GCPtrPar1 = param1.val.val64;
874	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDISState, &pDISState->param1, GCPtrPar1);
875	#ifdef IN_RC
876	pvParam1 = (void *)GCPtrPar1;
877	#else
878	PGMPAGEMAPLOCK Lock;
879	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
880	AssertRCReturn(rc, VERR_EM_INTERPRETER);
881	#endif
882
883	/* Try emulate it with a one-shot #PF handler in place. (RC) */
884	Log2(("%s %RGv imm%d=%RX64\n", emGetMnemonic(pDISState), GCPtrPar1, pDISState->param2.size*8, ValPar2));
885
886	RTGCUINTREG32 eflags = 0;
887	#ifdef IN_RC
888	MMGCRamRegisterTrapHandler(pVM);
889	#endif
890	rc = pfnEmulate(pvParam1, ValPar2, pDISState->param2.size, &eflags);
891	#ifdef IN_RC
892	MMGCRamDeregisterTrapHandler(pVM);
893	#else
894	PGMPhysReleasePageMappingLock(pVM, &Lock);
895	#endif
896	if (RT_FAILURE(rc))
897	{
898	Log(("%s %RGv imm%d=%RX64-> emulation failed due to page fault!\n", emGetMnemonic(pDISState), GCPtrPar1, pDISState->param2.size*8, ValPar2));
899	return VERR_EM_INTERPRETER;
900	}
901
902	/* Update guest's eflags and finish. */
903	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
904	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
905
906	*pcbSize = param2.size;
907	return VINF_SUCCESS;
908	}
909
910
911	/**
912	* ADD, ADC & SUB Emulation.
913	*/
914	static int emInterpretAddSub(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
915	PFNEMULATEPARAM3 pfnEmulate)
916	{
917	OP_PARAMVAL param1, param2;
918	int rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param1, &param1, PARAM_DEST);
919	if(RT_FAILURE(rc))
920	return VERR_EM_INTERPRETER;
921
922	rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param2, &param2, PARAM_SOURCE);
923	if(RT_FAILURE(rc))
924	return VERR_EM_INTERPRETER;
925
926	#ifdef IN_RC
927	if (TRPMHasTrap(pVCpu))
928	{
929	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
930	{
931	#endif
932	RTGCPTR pParam1;
933	uint64_t valpar1, valpar2;
934
935	if (pDISState->param1.size != pDISState->param2.size)
936	{
937	if (pDISState->param1.size < pDISState->param2.size)
938	{
939	AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDISState), (RTGCPTR)pRegFrame->rip, pDISState->param1.size, pDISState->param2.size)); /* should never happen! */
940	return VERR_EM_INTERPRETER;
941	}
942	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
943	pDISState->param2.size = pDISState->param1.size;
944	param2.size = param1.size;
945	}
946
947	/* The destination is always a virtual address */
948	if (param1.type == PARMTYPE_ADDRESS)
949	{
950	pParam1 = (RTGCPTR)param1.val.val64;
951	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDISState, &pDISState->param1, pParam1);
952	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
953	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
954	if (RT_FAILURE(rc))
955	{
956	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
957	return VERR_EM_INTERPRETER;
958	}
959	}
960	else
961	{
962	#ifndef DEBUG_bird
963	AssertFailed();
964	#endif
965	return VERR_EM_INTERPRETER;
966	}
967
968	/* Register or immediate data */
969	switch(param2.type)
970	{
971	case PARMTYPE_IMMEDIATE: /* both immediate data and register (ugly) */
972	valpar2 = param2.val.val64;
973	break;
974
975	default:
976	AssertFailed();
977	return VERR_EM_INTERPRETER;
978	}
979
980	/* Data read, emulate instruction. */
981	uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
982
983	/* Update guest's eflags and finish. */
984	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
985	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
986
987	/* And write it back */
988	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, param1.size);
989	if (RT_SUCCESS(rc))
990	{
991	/* All done! */
992	*pcbSize = param2.size;
993	return VINF_SUCCESS;
994	}
995	#ifdef IN_RC
996	}
997	}
998	#endif
999	return VERR_EM_INTERPRETER;
1000	}
1001
1002
1003	/**
1004	* ADC Emulation.
1005	*/
1006	static int emInterpretAdc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1007	{
1008	if (pRegFrame->eflags.Bits.u1CF)
1009	return emInterpretAddSub(pVM, pVCpu, pDISState, pRegFrame, pvFault, pcbSize, EMEmulateAdcWithCarrySet);
1010	else
1011	return emInterpretAddSub(pVM, pVCpu, pDISState, pRegFrame, pvFault, pcbSize, EMEmulateAdd);
1012	}
1013
1014
1015	/**
1016	* BTR/C/S Emulation.
1017	*/
1018	static int emInterpretBitTest(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
1019	PFNEMULATEPARAM2UINT32 pfnEmulate)
1020	{
1021	OP_PARAMVAL param1, param2;
1022	int rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param1, &param1, PARAM_DEST);
1023	if(RT_FAILURE(rc))
1024	return VERR_EM_INTERPRETER;
1025
1026	rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param2, &param2, PARAM_SOURCE);
1027	if(RT_FAILURE(rc))
1028	return VERR_EM_INTERPRETER;
1029
1030	#ifdef IN_RC
1031	if (TRPMHasTrap(pVCpu))
1032	{
1033	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
1034	{
1035	#endif
1036	RTGCPTR pParam1;
1037	uint64_t valpar1 = 0, valpar2;
1038	uint32_t eflags;
1039
1040	/* The destination is always a virtual address */
1041	if (param1.type != PARMTYPE_ADDRESS)
1042	return VERR_EM_INTERPRETER;
1043
1044	pParam1 = (RTGCPTR)param1.val.val64;
1045	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDISState, &pDISState->param1, pParam1);
1046
1047	/* Register or immediate data */
1048	switch(param2.type)
1049	{
1050	case PARMTYPE_IMMEDIATE: /* both immediate data and register (ugly) */
1051	valpar2 = param2.val.val64;
1052	break;
1053
1054	default:
1055	AssertFailed();
1056	return VERR_EM_INTERPRETER;
1057	}
1058
1059	Log2(("emInterpret%s: pvFault=%RGv pParam1=%RGv val2=%x\n", emGetMnemonic(pDISState), pvFault, pParam1, valpar2));
1060	pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + valpar2/8);
1061	EM_ASSERT_FAULT_RETURN((RTGCPTR)((RTGCUINTPTR)pParam1 & ~3) == pvFault, VERR_EM_INTERPRETER);
1062	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, 1);
1063	if (RT_FAILURE(rc))
1064	{
1065	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
1066	return VERR_EM_INTERPRETER;
1067	}
1068
1069	Log2(("emInterpretBtx: val=%x\n", valpar1));
1070	/* Data read, emulate bit test instruction. */
1071	eflags = pfnEmulate(&valpar1, valpar2 & 0x7);
1072
1073	Log2(("emInterpretBtx: val=%x CF=%d\n", valpar1, !!(eflags & X86_EFL_CF)));
1074
1075	/* Update guest's eflags and finish. */
1076	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1077	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1078
1079	/* And write it back */
1080	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, 1);
1081	if (RT_SUCCESS(rc))
1082	{
1083	/* All done! */
1084	*pcbSize = 1;
1085	return VINF_SUCCESS;
1086	}
1087	#ifdef IN_RC
1088	}
1089	}
1090	#endif
1091	return VERR_EM_INTERPRETER;
1092	}
1093
1094
1095	/**
1096	* LOCK BTR/C/S Emulation.
1097	*/
1098	static int emInterpretLockBitTest(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
1099	uint32_t *pcbSize, PFNEMULATELOCKPARAM2 pfnEmulate)
1100	{
1101	void *pvParam1;
1102
1103	OP_PARAMVAL param1, param2;
1104	int rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param1, &param1, PARAM_DEST);
1105	if(RT_FAILURE(rc))
1106	return VERR_EM_INTERPRETER;
1107
1108	rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param2, &param2, PARAM_SOURCE);
1109	if(RT_FAILURE(rc))
1110	return VERR_EM_INTERPRETER;
1111
1112	/* The destination is always a virtual address */
1113	if (param1.type != PARMTYPE_ADDRESS)
1114	return VERR_EM_INTERPRETER;
1115
1116	/* Register and immediate data == PARMTYPE_IMMEDIATE */
1117	AssertReturn(param2.type == PARMTYPE_IMMEDIATE, VERR_EM_INTERPRETER);
1118	uint64_t ValPar2 = param2.val.val64;
1119
1120	/* Adjust the parameters so what we're dealing with is a bit within the byte pointed to. */
1121	RTGCPTR GCPtrPar1 = param1.val.val64;
1122	GCPtrPar1 = (GCPtrPar1 + ValPar2 / 8);
1123	ValPar2 &= 7;
1124
1125	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDISState, &pDISState->param1, GCPtrPar1);
1126	#ifdef IN_RC
1127	Assert(TRPMHasTrap(pVCpu));
1128	EM_ASSERT_FAULT_RETURN((RTGCPTR)((RTGCUINTPTR)GCPtrPar1 & ~(RTGCUINTPTR)3) == pvFault, VERR_EM_INTERPRETER);
1129	#endif
1130
1131	#ifdef IN_RC
1132	pvParam1 = (void *)GCPtrPar1;
1133	#else
1134	PGMPAGEMAPLOCK Lock;
1135	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
1136	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1137	#endif
1138
1139	Log2(("emInterpretLockBitTest %s: pvFault=%RGv GCPtrPar1=%RGv imm=%RX64\n", emGetMnemonic(pDISState), pvFault, GCPtrPar1, ValPar2));
1140
1141	/* Try emulate it with a one-shot #PF handler in place. (RC) */
1142	RTGCUINTREG32 eflags = 0;
1143	#ifdef IN_RC
1144	MMGCRamRegisterTrapHandler(pVM);
1145	#endif
1146	rc = pfnEmulate(pvParam1, ValPar2, &eflags);
1147	#ifdef IN_RC
1148	MMGCRamDeregisterTrapHandler(pVM);
1149	#else
1150	PGMPhysReleasePageMappingLock(pVM, &Lock);
1151	#endif
1152	if (RT_FAILURE(rc))
1153	{
1154	Log(("emInterpretLockBitTest %s: %RGv imm%d=%RX64 -> emulation failed due to page fault!\n",
1155	emGetMnemonic(pDISState), GCPtrPar1, pDISState->param2.size*8, ValPar2));
1156	return VERR_EM_INTERPRETER;
1157	}
1158
1159	Log2(("emInterpretLockBitTest %s: GCPtrPar1=%RGv imm=%RX64 CF=%d\n", emGetMnemonic(pDISState), GCPtrPar1, ValPar2, !!(eflags & X86_EFL_CF)));
1160
1161	/* Update guest's eflags and finish. */
1162	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1163	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1164
1165	*pcbSize = 1;
1166	return VINF_SUCCESS;
1167	}
1168
1169
1170	/**
1171	* MOV emulation.
1172	*/
1173	static int emInterpretMov(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1174	{
1175	OP_PARAMVAL param1, param2;
1176	int rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param1, &param1, PARAM_DEST);
1177	if(RT_FAILURE(rc))
1178	return VERR_EM_INTERPRETER;
1179
1180	rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param2, &param2, PARAM_SOURCE);
1181	if(RT_FAILURE(rc))
1182	return VERR_EM_INTERPRETER;
1183
1184	#ifdef IN_RC
1185	if (TRPMHasTrap(pVCpu))
1186	{
1187	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
1188	{
1189	#else
1190	/** @todo Make this the default and don't rely on TRPM information. */
1191	if (param1.type == PARMTYPE_ADDRESS)
1192	{
1193	#endif
1194	RTGCPTR pDest;
1195	uint64_t val64;
1196
1197	switch(param1.type)
1198	{
1199	case PARMTYPE_IMMEDIATE:
1200	if(!(param1.flags & (PARAM_VAL32\|PARAM_VAL64)))
1201	return VERR_EM_INTERPRETER;
1202	/* fallthru */
1203
1204	case PARMTYPE_ADDRESS:
1205	pDest = (RTGCPTR)param1.val.val64;
1206	pDest = emConvertToFlatAddr(pVM, pRegFrame, pDISState, &pDISState->param1, pDest);
1207	break;
1208
1209	default:
1210	AssertFailed();
1211	return VERR_EM_INTERPRETER;
1212	}
1213
1214	switch(param2.type)
1215	{
1216	case PARMTYPE_IMMEDIATE: /* register type is translated to this one too */
1217	val64 = param2.val.val64;
1218	break;
1219
1220	default:
1221	Log(("emInterpretMov: unexpected type=%d rip=%RGv\n", param2.type, (RTGCPTR)pRegFrame->rip));
1222	return VERR_EM_INTERPRETER;
1223	}
1224	#ifdef LOG_ENABLED
1225	if (pDISState->mode == CPUMODE_64BIT)
1226	LogFlow(("EMInterpretInstruction at %RGv: OP_MOV %RGv <- %RX64 (%d) &val64=%RHv\n", (RTGCPTR)pRegFrame->rip, pDest, val64, param2.size, &val64));
1227	else
1228	LogFlow(("EMInterpretInstruction at %08RX64: OP_MOV %RGv <- %08X (%d) &val64=%RHv\n", pRegFrame->rip, pDest, (uint32_t)val64, param2.size, &val64));
1229	#endif
1230
1231	Assert(param2.size <= 8 && param2.size > 0);
1232	EM_ASSERT_FAULT_RETURN(pDest == pvFault, VERR_EM_INTERPRETER);
1233	rc = emRamWrite(pVM, pVCpu, pRegFrame, pDest, &val64, param2.size);
1234	if (RT_FAILURE(rc))
1235	return VERR_EM_INTERPRETER;
1236
1237	*pcbSize = param2.size;
1238	}
1239	else
1240	{ /* read fault */
1241	RTGCPTR pSrc;
1242	uint64_t val64;
1243
1244	/* Source */
1245	switch(param2.type)
1246	{
1247	case PARMTYPE_IMMEDIATE:
1248	if(!(param2.flags & (PARAM_VAL32\|PARAM_VAL64)))
1249	return VERR_EM_INTERPRETER;
1250	/* fallthru */
1251
1252	case PARMTYPE_ADDRESS:
1253	pSrc = (RTGCPTR)param2.val.val64;
1254	pSrc = emConvertToFlatAddr(pVM, pRegFrame, pDISState, &pDISState->param2, pSrc);
1255	break;
1256
1257	default:
1258	return VERR_EM_INTERPRETER;
1259	}
1260
1261	Assert(param1.size <= 8 && param1.size > 0);
1262	EM_ASSERT_FAULT_RETURN(pSrc == pvFault, VERR_EM_INTERPRETER);
1263	rc = emRamRead(pVM, pVCpu, pRegFrame, &val64, pSrc, param1.size);
1264	if (RT_FAILURE(rc))
1265	return VERR_EM_INTERPRETER;
1266
1267	/* Destination */
1268	switch(param1.type)
1269	{
1270	case PARMTYPE_REGISTER:
1271	switch(param1.size)
1272	{
1273	case 1: rc = DISWriteReg8(pRegFrame, pDISState->param1.base.reg_gen, (uint8_t) val64); break;
1274	case 2: rc = DISWriteReg16(pRegFrame, pDISState->param1.base.reg_gen, (uint16_t)val64); break;
1275	case 4: rc = DISWriteReg32(pRegFrame, pDISState->param1.base.reg_gen, (uint32_t)val64); break;
1276	case 8: rc = DISWriteReg64(pRegFrame, pDISState->param1.base.reg_gen, val64); break;
1277	default:
1278	return VERR_EM_INTERPRETER;
1279	}
1280	if (RT_FAILURE(rc))
1281	return rc;
1282	break;
1283
1284	default:
1285	return VERR_EM_INTERPRETER;
1286	}
1287	#ifdef LOG_ENABLED
1288	if (pDISState->mode == CPUMODE_64BIT)
1289	LogFlow(("EMInterpretInstruction: OP_MOV %RGv -> %RX64 (%d)\n", pSrc, val64, param1.size));
1290	else
1291	LogFlow(("EMInterpretInstruction: OP_MOV %RGv -> %08X (%d)\n", pSrc, (uint32_t)val64, param1.size));
1292	#endif
1293	}
1294	return VINF_SUCCESS;
1295	#ifdef IN_RC
1296	}
1297	#endif
1298	return VERR_EM_INTERPRETER;
1299	}
1300
1301
1302	#ifndef IN_RC
1303	/**
1304	* [REP] STOSWD emulation
1305	*/
1306	static int emInterpretStosWD(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1307	{
1308	int rc;
1309	RTGCPTR GCDest, GCOffset;
1310	uint32_t cbSize;
1311	uint64_t cTransfers;
1312	int offIncrement;
1313
1314	/* Don't support any but these three prefix bytes. */
1315	if ((pDISState->prefix & ~(PREFIX_ADDRSIZE\|PREFIX_OPSIZE\|PREFIX_REP\|PREFIX_REX)))
1316	return VERR_EM_INTERPRETER;
1317
1318	switch (pDISState->addrmode)
1319	{
1320	case CPUMODE_16BIT:
1321	GCOffset = pRegFrame->di;
1322	cTransfers = pRegFrame->cx;
1323	break;
1324	case CPUMODE_32BIT:
1325	GCOffset = pRegFrame->edi;
1326	cTransfers = pRegFrame->ecx;
1327	break;
1328	case CPUMODE_64BIT:
1329	GCOffset = pRegFrame->rdi;
1330	cTransfers = pRegFrame->rcx;
1331	break;
1332	default:
1333	AssertFailed();
1334	return VERR_EM_INTERPRETER;
1335	}
1336
1337	GCDest = SELMToFlat(pVM, DIS_SELREG_ES, pRegFrame, GCOffset);
1338	switch (pDISState->opmode)
1339	{
1340	case CPUMODE_16BIT:
1341	cbSize = 2;
1342	break;
1343	case CPUMODE_32BIT:
1344	cbSize = 4;
1345	break;
1346	case CPUMODE_64BIT:
1347	cbSize = 8;
1348	break;
1349	default:
1350	AssertFailed();
1351	return VERR_EM_INTERPRETER;
1352	}
1353
1354	offIncrement = pRegFrame->eflags.Bits.u1DF ? -(signed)cbSize : (signed)cbSize;
1355
1356	if (!(pDISState->prefix & PREFIX_REP))
1357	{
1358	LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d\n", pRegFrame->es, GCOffset, GCDest, cbSize));
1359
1360	rc = emRamWrite(pVM, pVCpu, pRegFrame, GCDest, &pRegFrame->rax, cbSize);
1361	if (RT_FAILURE(rc))
1362	return VERR_EM_INTERPRETER;
1363	Assert(rc == VINF_SUCCESS);
1364
1365	/* Update (e/r)di. */
1366	switch (pDISState->addrmode)
1367	{
1368	case CPUMODE_16BIT:
1369	pRegFrame->di += offIncrement;
1370	break;
1371	case CPUMODE_32BIT:
1372	pRegFrame->edi += offIncrement;
1373	break;
1374	case CPUMODE_64BIT:
1375	pRegFrame->rdi += offIncrement;
1376	break;
1377	default:
1378	AssertFailed();
1379	return VERR_EM_INTERPRETER;
1380	}
1381
1382	}
1383	else
1384	{
1385	if (!cTransfers)
1386	return VINF_SUCCESS;
1387
1388	/*
1389	* Do not try emulate cross page stuff here because we don't know what might
1390	* be waiting for us on the subsequent pages. The caller has only asked us to
1391	* ignore access handlers fro the current page.
1392	* This also fends off big stores which would quickly kill PGMR0DynMap.
1393	*/
1394	if ( cbSize > PAGE_SIZE
1395	\|\| cTransfers > PAGE_SIZE
1396	\|\| (GCDest >> PAGE_SHIFT) != ((GCDest + offIncrement * cTransfers) >> PAGE_SHIFT))
1397	{
1398	Log(("STOSWD is crosses pages, chicken out to the recompiler; GCDest=%RGv cbSize=%#x offIncrement=%d cTransfers=%#x\n",
1399	GCDest, cbSize, offIncrement, cTransfers));
1400	return VERR_EM_INTERPRETER;
1401	}
1402
1403	LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d cTransfers=%x DF=%d\n", pRegFrame->es, GCOffset, GCDest, cbSize, cTransfers, pRegFrame->eflags.Bits.u1DF));
1404	/* Access verification first; we currently can't recover properly from traps inside this instruction */
1405	rc = PGMVerifyAccess(pVCpu, GCDest - ((offIncrement > 0) ? 0 : ((cTransfers-1) * cbSize)),
1406	cTransfers * cbSize,
1407	X86_PTE_RW \| (CPUMGetGuestCPL(pVCpu, pRegFrame) == 3 ? X86_PTE_US : 0));
1408	if (rc != VINF_SUCCESS)
1409	{
1410	Log(("STOSWD will generate a trap -> recompiler, rc=%d\n", rc));
1411	return VERR_EM_INTERPRETER;
1412	}
1413
1414	/* REP case */
1415	while (cTransfers)
1416	{
1417	rc = emRamWrite(pVM, pVCpu, pRegFrame, GCDest, &pRegFrame->rax, cbSize);
1418	if (RT_FAILURE(rc))
1419	{
1420	rc = VERR_EM_INTERPRETER;
1421	break;
1422	}
1423
1424	Assert(rc == VINF_SUCCESS);
1425	GCOffset += offIncrement;
1426	GCDest += offIncrement;
1427	cTransfers--;
1428	}
1429
1430	/* Update the registers. */
1431	switch (pDISState->addrmode)
1432	{
1433	case CPUMODE_16BIT:
1434	pRegFrame->di = GCOffset;
1435	pRegFrame->cx = cTransfers;
1436	break;
1437	case CPUMODE_32BIT:
1438	pRegFrame->edi = GCOffset;
1439	pRegFrame->ecx = cTransfers;
1440	break;
1441	case CPUMODE_64BIT:
1442	pRegFrame->rdi = GCOffset;
1443	pRegFrame->rcx = cTransfers;
1444	break;
1445	default:
1446	AssertFailed();
1447	return VERR_EM_INTERPRETER;
1448	}
1449	}
1450
1451	*pcbSize = cbSize;
1452	return rc;
1453	}
1454	#endif /* !IN_RC */
1455
1456	#ifndef IN_RC
1457
1458	/**
1459	* [LOCK] CMPXCHG emulation.
1460	*/
1461	static int emInterpretCmpXchg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1462	{
1463	OP_PARAMVAL param1, param2;
1464
1465	#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL_IN_R0)
1466	Assert(pDISState->param1.size <= 4);
1467	#endif
1468
1469	/* Source to make DISQueryParamVal read the register value - ugly hack */
1470	int rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param1, &param1, PARAM_SOURCE);
1471	if(RT_FAILURE(rc))
1472	return VERR_EM_INTERPRETER;
1473
1474	rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param2, &param2, PARAM_SOURCE);
1475	if(RT_FAILURE(rc))
1476	return VERR_EM_INTERPRETER;
1477
1478	uint64_t valpar;
1479	switch(param2.type)
1480	{
1481	case PARMTYPE_IMMEDIATE: /* register actually */
1482	valpar = param2.val.val64;
1483	break;
1484
1485	default:
1486	return VERR_EM_INTERPRETER;
1487	}
1488
1489	PGMPAGEMAPLOCK Lock;
1490	RTGCPTR GCPtrPar1;
1491	void *pvParam1;
1492	uint64_t eflags;
1493
1494	AssertReturn(pDISState->param1.size == pDISState->param2.size, VERR_EM_INTERPRETER);
1495	switch(param1.type)
1496	{
1497	case PARMTYPE_ADDRESS:
1498	GCPtrPar1 = param1.val.val64;
1499	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDISState, &pDISState->param1, GCPtrPar1);
1500
1501	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
1502	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1503	break;
1504
1505	default:
1506	return VERR_EM_INTERPRETER;
1507	}
1508
1509	LogFlow(("%s %RGv rax=%RX64 %RX64\n", emGetMnemonic(pDISState), GCPtrPar1, pRegFrame->rax, valpar));
1510
1511	if (pDISState->prefix & PREFIX_LOCK)
1512	eflags = EMEmulateLockCmpXchg(pvParam1, &pRegFrame->rax, valpar, pDISState->param2.size);
1513	else
1514	eflags = EMEmulateCmpXchg(pvParam1, &pRegFrame->rax, valpar, pDISState->param2.size);
1515
1516	LogFlow(("%s %RGv rax=%RX64 %RX64 ZF=%d\n", emGetMnemonic(pDISState), GCPtrPar1, pRegFrame->rax, valpar, !!(eflags & X86_EFL_ZF)));
1517
1518	/* Update guest's eflags and finish. */
1519	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1520	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1521
1522	*pcbSize = param2.size;
1523	PGMPhysReleasePageMappingLock(pVM, &Lock);
1524	return VINF_SUCCESS;
1525	}
1526
1527
1528	/**
1529	* [LOCK] CMPXCHG8B emulation.
1530	*/
1531	static int emInterpretCmpXchg8b(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1532	{
1533	Assert(pDISState->mode != CPUMODE_64BIT); /** @todo check */
1534	OP_PARAMVAL param1;
1535
1536	/* Source to make DISQueryParamVal read the register value - ugly hack */
1537	int rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param1, &param1, PARAM_SOURCE);
1538	if(RT_FAILURE(rc))
1539	return VERR_EM_INTERPRETER;
1540
1541	RTGCPTR GCPtrPar1;
1542	void *pvParam1;
1543	uint64_t eflags;
1544	PGMPAGEMAPLOCK Lock;
1545
1546	AssertReturn(pDISState->param1.size == 8, VERR_EM_INTERPRETER);
1547	switch(param1.type)
1548	{
1549	case PARMTYPE_ADDRESS:
1550	GCPtrPar1 = param1.val.val64;
1551	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDISState, &pDISState->param1, GCPtrPar1);
1552
1553	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
1554	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1555	break;
1556
1557	default:
1558	return VERR_EM_INTERPRETER;
1559	}
1560
1561	LogFlow(("%s %RGv=%08x eax=%08x\n", emGetMnemonic(pDISState), pvParam1, pRegFrame->eax));
1562
1563	if (pDISState->prefix & PREFIX_LOCK)
1564	eflags = EMEmulateLockCmpXchg8b(pvParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
1565	else
1566	eflags = EMEmulateCmpXchg8b(pvParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
1567
1568	LogFlow(("%s %RGv=%08x eax=%08x ZF=%d\n", emGetMnemonic(pDISState), pvParam1, pRegFrame->eax, !!(eflags & X86_EFL_ZF)));
1569
1570	/* Update guest's eflags and finish; note that only ZF is affected. */
1571	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_ZF))
1572	\| (eflags & (X86_EFL_ZF));
1573
1574	*pcbSize = 8;
1575	PGMPhysReleasePageMappingLock(pVM, &Lock);
1576	return VINF_SUCCESS;
1577	}
1578
1579	#else /* IN_RC */
1580
1581	/**
1582	* [LOCK] CMPXCHG emulation.
1583	*/
1584	static int emInterpretCmpXchg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1585	{
1586	Assert(pDISState->mode != CPUMODE_64BIT); /** @todo check */
1587	OP_PARAMVAL param1, param2;
1588
1589	/* Source to make DISQueryParamVal read the register value - ugly hack */
1590	int rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param1, &param1, PARAM_SOURCE);
1591	if(RT_FAILURE(rc))
1592	return VERR_EM_INTERPRETER;
1593
1594	rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param2, &param2, PARAM_SOURCE);
1595	if(RT_FAILURE(rc))
1596	return VERR_EM_INTERPRETER;
1597
1598	if (TRPMHasTrap(pVCpu))
1599	{
1600	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
1601	{
1602	RTRCPTR pParam1;
1603	uint32_t valpar, eflags;
1604
1605	AssertReturn(pDISState->param1.size == pDISState->param2.size, VERR_EM_INTERPRETER);
1606	switch(param1.type)
1607	{
1608	case PARMTYPE_ADDRESS:
1609	pParam1 = (RTRCPTR)param1.val.val64;
1610	pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pDISState, &pDISState->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);
1611	EM_ASSERT_FAULT_RETURN(pParam1 == (RTRCPTR)pvFault, VERR_EM_INTERPRETER);
1612	break;
1613
1614	default:
1615	return VERR_EM_INTERPRETER;
1616	}
1617
1618	switch(param2.type)
1619	{
1620	case PARMTYPE_IMMEDIATE: /* register actually */
1621	valpar = param2.val.val32;
1622	break;
1623
1624	default:
1625	return VERR_EM_INTERPRETER;
1626	}
1627
1628	LogFlow(("%s %RRv eax=%08x %08x\n", emGetMnemonic(pDISState), pParam1, pRegFrame->eax, valpar));
1629
1630	MMGCRamRegisterTrapHandler(pVM);
1631	if (pDISState->prefix & PREFIX_LOCK)
1632	rc = EMGCEmulateLockCmpXchg(pParam1, &pRegFrame->eax, valpar, pDISState->param2.size, &eflags);
1633	else
1634	rc = EMGCEmulateCmpXchg(pParam1, &pRegFrame->eax, valpar, pDISState->param2.size, &eflags);
1635	MMGCRamDeregisterTrapHandler(pVM);
1636
1637	if (RT_FAILURE(rc))
1638	{
1639	Log(("%s %RGv eax=%08x %08x -> emulation failed due to page fault!\n", emGetMnemonic(pDISState), pParam1, pRegFrame->eax, valpar));
1640	return VERR_EM_INTERPRETER;
1641	}
1642
1643	LogFlow(("%s %RRv eax=%08x %08x ZF=%d\n", emGetMnemonic(pDISState), pParam1, pRegFrame->eax, valpar, !!(eflags & X86_EFL_ZF)));
1644
1645	/* Update guest's eflags and finish. */
1646	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1647	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1648
1649	*pcbSize = param2.size;
1650	return VINF_SUCCESS;
1651	}
1652	}
1653	return VERR_EM_INTERPRETER;
1654	}
1655
1656
1657	/**
1658	* [LOCK] CMPXCHG8B emulation.
1659	*/
1660	static int emInterpretCmpXchg8b(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1661	{
1662	Assert(pDISState->mode != CPUMODE_64BIT); /** @todo check */
1663	OP_PARAMVAL param1;
1664
1665	/* Source to make DISQueryParamVal read the register value - ugly hack */
1666	int rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param1, &param1, PARAM_SOURCE);
1667	if(RT_FAILURE(rc))
1668	return VERR_EM_INTERPRETER;
1669
1670	if (TRPMHasTrap(pVCpu))
1671	{
1672	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
1673	{
1674	RTRCPTR pParam1;
1675	uint32_t eflags;
1676
1677	AssertReturn(pDISState->param1.size == 8, VERR_EM_INTERPRETER);
1678	switch(param1.type)
1679	{
1680	case PARMTYPE_ADDRESS:
1681	pParam1 = (RTRCPTR)param1.val.val64;
1682	pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pDISState, &pDISState->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);
1683	EM_ASSERT_FAULT_RETURN(pParam1 == (RTRCPTR)pvFault, VERR_EM_INTERPRETER);
1684	break;
1685
1686	default:
1687	return VERR_EM_INTERPRETER;
1688	}
1689
1690	LogFlow(("%s %RRv=%08x eax=%08x\n", emGetMnemonic(pDISState), pParam1, pRegFrame->eax));
1691
1692	MMGCRamRegisterTrapHandler(pVM);
1693	if (pDISState->prefix & PREFIX_LOCK)
1694	rc = EMGCEmulateLockCmpXchg8b(pParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx, &eflags);
1695	else
1696	rc = EMGCEmulateCmpXchg8b(pParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx, &eflags);
1697	MMGCRamDeregisterTrapHandler(pVM);
1698
1699	if (RT_FAILURE(rc))
1700	{
1701	Log(("%s %RGv=%08x eax=%08x -> emulation failed due to page fault!\n", emGetMnemonic(pDISState), pParam1, pRegFrame->eax));
1702	return VERR_EM_INTERPRETER;
1703	}
1704
1705	LogFlow(("%s %RGv=%08x eax=%08x ZF=%d\n", emGetMnemonic(pDISState), pParam1, pRegFrame->eax, !!(eflags & X86_EFL_ZF)));
1706
1707	/* Update guest's eflags and finish; note that only ZF is affected. */
1708	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_ZF))
1709	\| (eflags & (X86_EFL_ZF));
1710
1711	*pcbSize = 8;
1712	return VINF_SUCCESS;
1713	}
1714	}
1715	return VERR_EM_INTERPRETER;
1716	}
1717
1718	#endif /* IN_RC */
1719
1720	#ifdef IN_RC
1721	/**
1722	* [LOCK] XADD emulation.
1723	*/
1724	static int emInterpretXAdd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1725	{
1726	Assert(pDISState->mode != CPUMODE_64BIT); /** @todo check */
1727	OP_PARAMVAL param1;
1728	uint32_t *pParamReg2;
1729	size_t cbSizeParamReg2;
1730
1731	/* Source to make DISQueryParamVal read the register value - ugly hack */
1732	int rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param1, &param1, PARAM_SOURCE);
1733	if(RT_FAILURE(rc))
1734	return VERR_EM_INTERPRETER;
1735
1736	rc = DISQueryParamRegPtr(pRegFrame, pDISState, &pDISState->param2, (void **)&pParamReg2, &cbSizeParamReg2);
1737	Assert(cbSizeParamReg2 <= 4);
1738	if(RT_FAILURE(rc))
1739	return VERR_EM_INTERPRETER;
1740
1741	if (TRPMHasTrap(pVCpu))
1742	{
1743	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
1744	{
1745	RTRCPTR pParam1;
1746	uint32_t eflags;
1747
1748	AssertReturn(pDISState->param1.size == pDISState->param2.size, VERR_EM_INTERPRETER);
1749	switch(param1.type)
1750	{
1751	case PARMTYPE_ADDRESS:
1752	pParam1 = (RTRCPTR)param1.val.val64;
1753	pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pDISState, &pDISState->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);
1754	EM_ASSERT_FAULT_RETURN(pParam1 == (RTRCPTR)pvFault, VERR_EM_INTERPRETER);
1755	break;
1756
1757	default:
1758	return VERR_EM_INTERPRETER;
1759	}
1760
1761	LogFlow(("XAdd %RRv=%08x reg=%08x\n", pParam1, *pParamReg2));
1762
1763	MMGCRamRegisterTrapHandler(pVM);
1764	if (pDISState->prefix & PREFIX_LOCK)
1765	rc = EMGCEmulateLockXAdd(pParam1, pParamReg2, cbSizeParamReg2, &eflags);
1766	else
1767	rc = EMGCEmulateXAdd(pParam1, pParamReg2, cbSizeParamReg2, &eflags);
1768	MMGCRamDeregisterTrapHandler(pVM);
1769
1770	if (RT_FAILURE(rc))
1771	{
1772	Log(("XAdd %RGv reg=%08x -> emulation failed due to page fault!\n", pParam1, *pParamReg2));
1773	return VERR_EM_INTERPRETER;
1774	}
1775
1776	LogFlow(("XAdd %RGv reg=%08x ZF=%d\n", pParam1, *pParamReg2, !!(eflags & X86_EFL_ZF)));
1777
1778	/* Update guest's eflags and finish. */
1779	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1780	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1781
1782	*pcbSize = cbSizeParamReg2;
1783	return VINF_SUCCESS;
1784	}
1785	}
1786	return VERR_EM_INTERPRETER;
1787	}
1788	#endif /* IN_RC */
1789
1790
1791	#ifdef IN_RC
1792	/**
1793	* Interpret IRET (currently only to V86 code)
1794	*
1795	* @returns VBox status code.
1796	* @param pVM The VM handle.
1797	* @param pVCpu The VMCPU handle.
1798	* @param pRegFrame The register frame.
1799	*
1800	*/
1801	VMMDECL(int) EMInterpretIret(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1802	{
1803	RTGCUINTPTR pIretStack = (RTGCUINTPTR)pRegFrame->esp;
1804	RTGCUINTPTR eip, cs, esp, ss, eflags, ds, es, fs, gs, uMask;
1805	int rc;
1806
1807	Assert(!CPUMIsGuestIn64BitCode(pVCpu, pRegFrame));
1808
1809	rc = emRamRead(pVM, pVCpu, pRegFrame, &eip, (RTGCPTR)pIretStack , 4);
1810	rc \|= emRamRead(pVM, pVCpu, pRegFrame, &cs, (RTGCPTR)(pIretStack + 4), 4);
1811	rc \|= emRamRead(pVM, pVCpu, pRegFrame, &eflags, (RTGCPTR)(pIretStack + 8), 4);
1812	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1813	AssertReturn(eflags & X86_EFL_VM, VERR_EM_INTERPRETER);
1814
1815	rc \|= emRamRead(pVM, pVCpu, pRegFrame, &esp, (RTGCPTR)(pIretStack + 12), 4);
1816	rc \|= emRamRead(pVM, pVCpu, pRegFrame, &ss, (RTGCPTR)(pIretStack + 16), 4);
1817	rc \|= emRamRead(pVM, pVCpu, pRegFrame, &es, (RTGCPTR)(pIretStack + 20), 4);
1818	rc \|= emRamRead(pVM, pVCpu, pRegFrame, &ds, (RTGCPTR)(pIretStack + 24), 4);
1819	rc \|= emRamRead(pVM, pVCpu, pRegFrame, &fs, (RTGCPTR)(pIretStack + 28), 4);
1820	rc \|= emRamRead(pVM, pVCpu, pRegFrame, &gs, (RTGCPTR)(pIretStack + 32), 4);
1821	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1822
1823	pRegFrame->eip = eip & 0xffff;
1824	pRegFrame->cs = cs;
1825
1826	/* Mask away all reserved bits */
1827	uMask = X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_RF \| X86_EFL_VM \| X86_EFL_AC \| X86_EFL_VIF \| X86_EFL_VIP \| X86_EFL_ID;
1828	eflags &= uMask;
1829
1830	#ifndef IN_RING0
1831	CPUMRawSetEFlags(pVCpu, pRegFrame, eflags);
1832	#endif
1833	Assert((pRegFrame->eflags.u32 & (X86_EFL_IF\|X86_EFL_IOPL)) == X86_EFL_IF);
1834
1835	pRegFrame->esp = esp;
1836	pRegFrame->ss = ss;
1837	pRegFrame->ds = ds;
1838	pRegFrame->es = es;
1839	pRegFrame->fs = fs;
1840	pRegFrame->gs = gs;
1841
1842	return VINF_SUCCESS;
1843	}
1844	#endif /* IN_RC */
1845
1846
1847	/**
1848	* IRET Emulation.
1849	*/
1850	static int emInterpretIret(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1851	{
1852	/* only allow direct calls to EMInterpretIret for now */
1853	return VERR_EM_INTERPRETER;
1854	}
1855
1856	/**
1857	* WBINVD Emulation.
1858	*/
1859	static int emInterpretWbInvd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1860	{
1861	/* Nothing to do. */
1862	return VINF_SUCCESS;
1863	}
1864
1865
1866	/**
1867	* Interpret INVLPG
1868	*
1869	* @returns VBox status code.
1870	* @param pVM The VM handle.
1871	* @param pVCpu The VMCPU handle.
1872	* @param pRegFrame The register frame.
1873	* @param pAddrGC Operand address
1874	*
1875	*/
1876	VMMDECL(int) EMInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC)
1877	{
1878	int rc;
1879
1880	/** @todo is addr always a flat linear address or ds based
1881	* (in absence of segment override prefixes)????
1882	*/
1883	#ifdef IN_RC
1884	LogFlow(("RC: EMULATE: invlpg %RGv\n", pAddrGC));
1885	#endif
1886	rc = PGMInvalidatePage(pVCpu, pAddrGC);
1887	if ( rc == VINF_SUCCESS
1888	\|\| rc == VINF_PGM_SYNC_CR3 /* we can rely on the FF */)
1889	return VINF_SUCCESS;
1890	AssertMsgReturn(rc == VINF_EM_RAW_EMULATE_INSTR,
1891	("%Rrc addr=%RGv\n", rc, pAddrGC),
1892	VERR_EM_INTERPRETER);
1893	return rc;
1894	}
1895
1896
1897	/**
1898	* INVLPG Emulation.
1899	*/
1900	static int emInterpretInvlPg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1901	{
1902	OP_PARAMVAL param1;
1903	RTGCPTR addr;
1904
1905	int rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param1, &param1, PARAM_SOURCE);
1906	if(RT_FAILURE(rc))
1907	return VERR_EM_INTERPRETER;
1908
1909	switch(param1.type)
1910	{
1911	case PARMTYPE_IMMEDIATE:
1912	case PARMTYPE_ADDRESS:
1913	if(!(param1.flags & (PARAM_VAL32\|PARAM_VAL64)))
1914	return VERR_EM_INTERPRETER;
1915	addr = (RTGCPTR)param1.val.val64;
1916	break;
1917
1918	default:
1919	return VERR_EM_INTERPRETER;
1920	}
1921
1922	/** @todo is addr always a flat linear address or ds based
1923	* (in absence of segment override prefixes)????
1924	*/
1925	#ifdef IN_RC
1926	LogFlow(("RC: EMULATE: invlpg %RGv\n", addr));
1927	#endif
1928	rc = PGMInvalidatePage(pVCpu, addr);
1929	if ( rc == VINF_SUCCESS
1930	\|\| rc == VINF_PGM_SYNC_CR3 /* we can rely on the FF */)
1931	return VINF_SUCCESS;
1932	AssertMsgReturn(rc == VINF_EM_RAW_EMULATE_INSTR,
1933	("%Rrc addr=%RGv\n", rc, addr),
1934	VERR_EM_INTERPRETER);
1935	return rc;
1936	}
1937
1938
1939	/**
1940	* Interpret CPUID given the parameters in the CPU context
1941	*
1942	* @returns VBox status code.
1943	* @param pVM The VM handle.
1944	* @param pVCpu The VMCPU handle.
1945	* @param pRegFrame The register frame.
1946	*
1947	*/
1948	VMMDECL(int) EMInterpretCpuId(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1949	{
1950	uint32_t iLeaf = pRegFrame->eax;
1951
1952	/* cpuid clears the high dwords of the affected 64 bits registers. */
1953	pRegFrame->rax = 0;
1954	pRegFrame->rbx = 0;
1955	pRegFrame->rcx = 0;
1956	pRegFrame->rdx = 0;
1957
1958	/* Note: operates the same in 64 and non-64 bits mode. */
1959	CPUMGetGuestCpuId(pVCpu, iLeaf, &pRegFrame->eax, &pRegFrame->ebx, &pRegFrame->ecx, &pRegFrame->edx);
1960	Log(("Emulate: CPUID %x -> %08x %08x %08x %08x\n", iLeaf, pRegFrame->eax, pRegFrame->ebx, pRegFrame->ecx, pRegFrame->edx));
1961	return VINF_SUCCESS;
1962	}
1963
1964
1965	/**
1966	* CPUID Emulation.
1967	*/
1968	static int emInterpretCpuId(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1969	{
1970	int rc = EMInterpretCpuId(pVM, pVCpu, pRegFrame);
1971	return rc;
1972	}
1973
1974
1975	/**
1976	* Interpret CRx read
1977	*
1978	* @returns VBox status code.
1979	* @param pVM The VM handle.
1980	* @param pVCpu The VMCPU handle.
1981	* @param pRegFrame The register frame.
1982	* @param DestRegGen General purpose register index (USE_REG_E**))
1983	* @param SrcRegCRx CRx register index (USE_REG_CR*)
1984	*
1985	*/
1986	VMMDECL(int) EMInterpretCRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx)
1987	{
1988	int rc;
1989	uint64_t val64;
1990
1991	if (SrcRegCrx == USE_REG_CR8)
1992	{
1993	val64 = 0;
1994	rc = PDMApicGetTPR(pVCpu, (uint8_t *)&val64, NULL);
1995	AssertMsgRCReturn(rc, ("PDMApicGetTPR failed\n"), VERR_EM_INTERPRETER);
1996	}
1997	else
1998	{
1999	rc = CPUMGetGuestCRx(pVCpu, SrcRegCrx, &val64);
2000	AssertMsgRCReturn(rc, ("CPUMGetGuestCRx %d failed\n", SrcRegCrx), VERR_EM_INTERPRETER);
2001	}
2002
2003	if (CPUMIsGuestIn64BitCode(pVCpu, pRegFrame))
2004	rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
2005	else
2006	rc = DISWriteReg32(pRegFrame, DestRegGen, val64);
2007
2008	if(RT_SUCCESS(rc))
2009	{
2010	LogFlow(("MOV_CR: gen32=%d CR=%d val=%RX64\n", DestRegGen, SrcRegCrx, val64));
2011	return VINF_SUCCESS;
2012	}
2013	return VERR_EM_INTERPRETER;
2014	}
2015
2016
2017
2018	/**
2019	* Interpret CLTS
2020	*
2021	* @returns VBox status code.
2022	* @param pVM The VM handle.
2023	* @param pVCpu The VMCPU handle.
2024	*
2025	*/
2026	VMMDECL(int) EMInterpretCLTS(PVM pVM, PVMCPU pVCpu)
2027	{
2028	uint64_t cr0 = CPUMGetGuestCR0(pVCpu);
2029	if (!(cr0 & X86_CR0_TS))
2030	return VINF_SUCCESS;
2031	return CPUMSetGuestCR0(pVCpu, cr0 & ~X86_CR0_TS);
2032	}
2033
2034	/**
2035	* CLTS Emulation.
2036	*/
2037	static int emInterpretClts(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2038	{
2039	return EMInterpretCLTS(pVM, pVCpu);
2040	}
2041
2042
2043	/**
2044	* Update CRx
2045	*
2046	* @returns VBox status code.
2047	* @param pVM The VM handle.
2048	* @param pVCpu The VMCPU handle.
2049	* @param pRegFrame The register frame.
2050	* @param DestRegCRx CRx register index (USE_REG_CR*)
2051	* @param val New CRx value
2052	*
2053	*/
2054	static int emUpdateCRx(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint64_t val)
2055	{
2056	uint64_t oldval;
2057	uint64_t msrEFER;
2058	int rc, rc2;
2059
2060	/** @todo Clean up this mess. */
2061	LogFlow(("EMInterpretCRxWrite at %RGv CR%d <- %RX64\n", (RTGCPTR)pRegFrame->rip, DestRegCrx, val));
2062	switch (DestRegCrx)
2063	{
2064	case USE_REG_CR0:
2065	oldval = CPUMGetGuestCR0(pVCpu);
2066	#ifdef IN_RC
2067	/* CR0.WP and CR0.AM changes require a reschedule run in ring 3. */
2068	if ( (val & (X86_CR0_WP \| X86_CR0_AM))
2069	!= (oldval & (X86_CR0_WP \| X86_CR0_AM)))
2070	return VERR_EM_INTERPRETER;
2071	#endif
2072	rc = VINF_SUCCESS;
2073	CPUMSetGuestCR0(pVCpu, val);
2074	val = CPUMGetGuestCR0(pVCpu);
2075	if ( (oldval & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE))
2076	!= (val & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE)))
2077	{
2078	/* global flush */
2079	rc = PGMFlushTLB(pVCpu, CPUMGetGuestCR3(pVCpu), true /* global */);
2080	AssertRCReturn(rc, rc);
2081	}
2082
2083	/* Deal with long mode enabling/disabling. */
2084	msrEFER = CPUMGetGuestEFER(pVCpu);
2085	if (msrEFER & MSR_K6_EFER_LME)
2086	{
2087	if ( !(oldval & X86_CR0_PG)
2088	&& (val & X86_CR0_PG))
2089	{
2090	/* Illegal to have an active 64 bits CS selector (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
2091	if (pRegFrame->csHid.Attr.n.u1Long)
2092	{
2093	AssertMsgFailed(("Illegal enabling of paging with CS.u1Long = 1!!\n"));
2094	return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
2095	}
2096
2097	/* Illegal to switch to long mode before activating PAE first (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
2098	if (!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PAE))
2099	{
2100	AssertMsgFailed(("Illegal enabling of paging with PAE disabled!!\n"));
2101	return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
2102	}
2103	msrEFER \|= MSR_K6_EFER_LMA;
2104	}
2105	else
2106	if ( (oldval & X86_CR0_PG)
2107	&& !(val & X86_CR0_PG))
2108	{
2109	msrEFER &= ~MSR_K6_EFER_LMA;
2110	/* @todo Do we need to cut off rip here? High dword of rip is undefined, so it shouldn't really matter. */
2111	}
2112	CPUMSetGuestEFER(pVCpu, msrEFER);
2113	}
2114	rc2 = PGMChangeMode(pVCpu, CPUMGetGuestCR0(pVCpu), CPUMGetGuestCR4(pVCpu), CPUMGetGuestEFER(pVCpu));
2115	return rc2 == VINF_SUCCESS ? rc : rc2;
2116
2117	case USE_REG_CR2:
2118	rc = CPUMSetGuestCR2(pVCpu, val); AssertRC(rc);
2119	return VINF_SUCCESS;
2120
2121	case USE_REG_CR3:
2122	/* Reloading the current CR3 means the guest just wants to flush the TLBs */
2123	rc = CPUMSetGuestCR3(pVCpu, val); AssertRC(rc);
2124	if (CPUMGetGuestCR0(pVCpu) & X86_CR0_PG)
2125	{
2126	/* flush */
2127	rc = PGMFlushTLB(pVCpu, val, !(CPUMGetGuestCR4(pVCpu) & X86_CR4_PGE));
2128	AssertRCReturn(rc, rc);
2129	}
2130	return rc;
2131
2132	case USE_REG_CR4:
2133	oldval = CPUMGetGuestCR4(pVCpu);
2134	rc = CPUMSetGuestCR4(pVCpu, val); AssertRC(rc);
2135	val = CPUMGetGuestCR4(pVCpu);
2136
2137	/* Illegal to disable PAE when long mode is active. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
2138	msrEFER = CPUMGetGuestEFER(pVCpu);
2139	if ( (msrEFER & MSR_K6_EFER_LMA)
2140	&& (oldval & X86_CR4_PAE)
2141	&& !(val & X86_CR4_PAE))
2142	{
2143	return VERR_EM_INTERPRETER; /** @todo generate #GP(0) */
2144	}
2145
2146	rc = VINF_SUCCESS;
2147	if ( (oldval & (X86_CR4_PGE\|X86_CR4_PAE\|X86_CR4_PSE))
2148	!= (val & (X86_CR4_PGE\|X86_CR4_PAE\|X86_CR4_PSE)))
2149	{
2150	/* global flush */
2151	rc = PGMFlushTLB(pVCpu, CPUMGetGuestCR3(pVCpu), true /* global */);
2152	AssertRCReturn(rc, rc);
2153	}
2154
2155	/* Feeling extremely lazy. */
2156	# ifdef IN_RC
2157	if ( (oldval & (X86_CR4_OSFSXR\|X86_CR4_OSXMMEEXCPT\|X86_CR4_PCE\|X86_CR4_MCE\|X86_CR4_PAE\|X86_CR4_DE\|X86_CR4_TSD\|X86_CR4_PVI\|X86_CR4_VME))
2158	!= (val & (X86_CR4_OSFSXR\|X86_CR4_OSXMMEEXCPT\|X86_CR4_PCE\|X86_CR4_MCE\|X86_CR4_PAE\|X86_CR4_DE\|X86_CR4_TSD\|X86_CR4_PVI\|X86_CR4_VME)))
2159	{
2160	Log(("emInterpretMovCRx: CR4: %#RX64->%#RX64 => R3\n", oldval, val));
2161	VMCPU_FF_SET(pVCpu, VMCPU_FF_TO_R3);
2162	}
2163	# endif
2164	if ((val ^ oldval) & X86_CR4_VME)
2165	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
2166
2167	rc2 = PGMChangeMode(pVCpu, CPUMGetGuestCR0(pVCpu), CPUMGetGuestCR4(pVCpu), CPUMGetGuestEFER(pVCpu));
2168	return rc2 == VINF_SUCCESS ? rc : rc2;
2169
2170	case USE_REG_CR8:
2171	return PDMApicSetTPR(pVCpu, val);
2172
2173	default:
2174	AssertFailed();
2175	case USE_REG_CR1: /* illegal op */
2176	break;
2177	}
2178	return VERR_EM_INTERPRETER;
2179	}
2180
2181	/**
2182	* Interpret CRx write
2183	*
2184	* @returns VBox status code.
2185	* @param pVM The VM handle.
2186	* @param pVCpu The VMCPU handle.
2187	* @param pRegFrame The register frame.
2188	* @param DestRegCRx CRx register index (USE_REG_CR*)
2189	* @param SrcRegGen General purpose register index (USE_REG_E**))
2190	*
2191	*/
2192	VMMDECL(int) EMInterpretCRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint32_t SrcRegGen)
2193	{
2194	uint64_t val;
2195	int rc;
2196
2197	if (CPUMIsGuestIn64BitCode(pVCpu, pRegFrame))
2198	{
2199	rc = DISFetchReg64(pRegFrame, SrcRegGen, &val);
2200	}
2201	else
2202	{
2203	uint32_t val32;
2204	rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
2205	val = val32;
2206	}
2207
2208	if (RT_SUCCESS(rc))
2209	return emUpdateCRx(pVM, pVCpu, pRegFrame, DestRegCrx, val);
2210
2211	return VERR_EM_INTERPRETER;
2212	}
2213
2214	/**
2215	* Interpret LMSW
2216	*
2217	* @returns VBox status code.
2218	* @param pVM The VM handle.
2219	* @param pVCpu The VMCPU handle.
2220	* @param pRegFrame The register frame.
2221	* @param u16Data LMSW source data.
2222	*
2223	*/
2224	VMMDECL(int) EMInterpretLMSW(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint16_t u16Data)
2225	{
2226	uint64_t OldCr0 = CPUMGetGuestCR0(pVCpu);
2227
2228	/* Only PE, MP, EM and TS can be changed; note that PE can't be cleared by this instruction. */
2229	uint64_t NewCr0 = ( OldCr0 & ~( X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
2230	\| (u16Data & (X86_CR0_PE \| X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS));
2231
2232	return emUpdateCRx(pVM, pVCpu, pRegFrame, USE_REG_CR0, NewCr0);
2233	}
2234
2235	/**
2236	* LMSW Emulation.
2237	*/
2238	static int emInterpretLmsw(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2239	{
2240	OP_PARAMVAL param1;
2241	uint32_t val;
2242
2243	int rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param1, &param1, PARAM_SOURCE);
2244	if(RT_FAILURE(rc))
2245	return VERR_EM_INTERPRETER;
2246
2247	switch(param1.type)
2248	{
2249	case PARMTYPE_IMMEDIATE:
2250	case PARMTYPE_ADDRESS:
2251	if(!(param1.flags & PARAM_VAL16))
2252	return VERR_EM_INTERPRETER;
2253	val = param1.val.val32;
2254	break;
2255
2256	default:
2257	return VERR_EM_INTERPRETER;
2258	}
2259
2260	LogFlow(("emInterpretLmsw %x\n", val));
2261	return EMInterpretLMSW(pVM, pVCpu, pRegFrame, val);
2262	}
2263
2264	#ifdef EM_EMULATE_SMSW
2265	/**
2266	* SMSW Emulation.
2267	*/
2268	static int emInterpretSmsw(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2269	{
2270	OP_PARAMVAL param1;
2271	uint64_t cr0 = CPUMGetGuestCR0(pVCpu);
2272
2273	int rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param1, &param1, PARAM_SOURCE);
2274	if(RT_FAILURE(rc))
2275	return VERR_EM_INTERPRETER;
2276
2277	switch(param1.type)
2278	{
2279	case PARMTYPE_IMMEDIATE:
2280	if(param1.size != sizeof(uint16_t))
2281	return VERR_EM_INTERPRETER;
2282	LogFlow(("emInterpretSmsw %d <- cr0 (%x)\n", pDISState->param1.base.reg_gen, cr0));
2283	rc = DISWriteReg16(pRegFrame, pDISState->param1.base.reg_gen, cr0);
2284	break;
2285
2286	case PARMTYPE_ADDRESS:
2287	{
2288	RTGCPTR pParam1;
2289
2290	/* Actually forced to 16 bits regardless of the operand size. */
2291	if(param1.size != sizeof(uint16_t))
2292	return VERR_EM_INTERPRETER;
2293
2294	pParam1 = (RTGCPTR)param1.val.val64;
2295	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDISState, &pDISState->param1, pParam1);
2296	LogFlow(("emInterpretSmsw %VGv <- cr0 (%x)\n", pParam1, cr0));
2297
2298	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &cr0, sizeof(uint16_t));
2299	if (RT_FAILURE(rc))
2300	{
2301	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2302	return VERR_EM_INTERPRETER;
2303	}
2304	break;
2305	}
2306
2307	default:
2308	return VERR_EM_INTERPRETER;
2309	}
2310
2311	LogFlow(("emInterpretSmsw %x\n", cr0));
2312	return rc;
2313	}
2314	#endif
2315
2316	/**
2317	* MOV CRx
2318	*/
2319	static int emInterpretMovCRx(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2320	{
2321	if ((pDISState->param1.flags == USE_REG_GEN32 \|\| pDISState->param1.flags == USE_REG_GEN64) && pDISState->param2.flags == USE_REG_CR)
2322	return EMInterpretCRxRead(pVM, pVCpu, pRegFrame, pDISState->param1.base.reg_gen, pDISState->param2.base.reg_ctrl);
2323
2324	if (pDISState->param1.flags == USE_REG_CR && (pDISState->param2.flags == USE_REG_GEN32 \|\| pDISState->param2.flags == USE_REG_GEN64))
2325	return EMInterpretCRxWrite(pVM, pVCpu, pRegFrame, pDISState->param1.base.reg_ctrl, pDISState->param2.base.reg_gen);
2326
2327	AssertMsgFailedReturn(("Unexpected control register move\n"), VERR_EM_INTERPRETER);
2328	return VERR_EM_INTERPRETER;
2329	}
2330
2331
2332	/**
2333	* Interpret DRx write
2334	*
2335	* @returns VBox status code.
2336	* @param pVM The VM handle.
2337	* @param pVCpu The VMCPU handle.
2338	* @param pRegFrame The register frame.
2339	* @param DestRegDRx DRx register index (USE_REG_DR*)
2340	* @param SrcRegGen General purpose register index (USE_REG_E**))
2341	*
2342	*/
2343	VMMDECL(int) EMInterpretDRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen)
2344	{
2345	uint64_t val;
2346	int rc;
2347
2348	if (CPUMIsGuestIn64BitCode(pVCpu, pRegFrame))
2349	{
2350	rc = DISFetchReg64(pRegFrame, SrcRegGen, &val);
2351	}
2352	else
2353	{
2354	uint32_t val32;
2355	rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
2356	val = val32;
2357	}
2358
2359	if (RT_SUCCESS(rc))
2360	{
2361	/** @todo we don't fail if illegal bits are set/cleared for e.g. dr7 */
2362	rc = CPUMSetGuestDRx(pVCpu, DestRegDrx, val);
2363	if (RT_SUCCESS(rc))
2364	return rc;
2365	AssertMsgFailed(("CPUMSetGuestDRx %d failed\n", DestRegDrx));
2366	}
2367	return VERR_EM_INTERPRETER;
2368	}
2369
2370
2371	/**
2372	* Interpret DRx read
2373	*
2374	* @returns VBox status code.
2375	* @param pVM The VM handle.
2376	* @param pVCpu The VMCPU handle.
2377	* @param pRegFrame The register frame.
2378	* @param DestRegGen General purpose register index (USE_REG_E**))
2379	* @param SrcRegDRx DRx register index (USE_REG_DR*)
2380	*
2381	*/
2382	VMMDECL(int) EMInterpretDRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx)
2383	{
2384	uint64_t val64;
2385
2386	int rc = CPUMGetGuestDRx(pVCpu, SrcRegDrx, &val64);
2387	AssertMsgRCReturn(rc, ("CPUMGetGuestDRx %d failed\n", SrcRegDrx), VERR_EM_INTERPRETER);
2388	if (CPUMIsGuestIn64BitCode(pVCpu, pRegFrame))
2389	{
2390	rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
2391	}
2392	else
2393	rc = DISWriteReg32(pRegFrame, DestRegGen, (uint32_t)val64);
2394
2395	if (RT_SUCCESS(rc))
2396	return VINF_SUCCESS;
2397
2398	return VERR_EM_INTERPRETER;
2399	}
2400
2401
2402	/**
2403	* MOV DRx
2404	*/
2405	static int emInterpretMovDRx(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2406	{
2407	int rc = VERR_EM_INTERPRETER;
2408
2409	if((pDISState->param1.flags == USE_REG_GEN32 \|\| pDISState->param1.flags == USE_REG_GEN64) && pDISState->param2.flags == USE_REG_DBG)
2410	{
2411	rc = EMInterpretDRxRead(pVM, pVCpu, pRegFrame, pDISState->param1.base.reg_gen, pDISState->param2.base.reg_dbg);
2412	}
2413	else
2414	if(pDISState->param1.flags == USE_REG_DBG && (pDISState->param2.flags == USE_REG_GEN32 \|\| pDISState->param2.flags == USE_REG_GEN64))
2415	{
2416	rc = EMInterpretDRxWrite(pVM, pVCpu, pRegFrame, pDISState->param1.base.reg_dbg, pDISState->param2.base.reg_gen);
2417	}
2418	else
2419	AssertMsgFailed(("Unexpected debug register move\n"));
2420
2421	return rc;
2422	}
2423
2424
2425	/**
2426	* LLDT Emulation.
2427	*/
2428	static int emInterpretLLdt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2429	{
2430	OP_PARAMVAL param1;
2431	RTSEL sel;
2432
2433	int rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param1, &param1, PARAM_SOURCE);
2434	if(RT_FAILURE(rc))
2435	return VERR_EM_INTERPRETER;
2436
2437	switch(param1.type)
2438	{
2439	case PARMTYPE_ADDRESS:
2440	return VERR_EM_INTERPRETER; //feeling lazy right now
2441
2442	case PARMTYPE_IMMEDIATE:
2443	if(!(param1.flags & PARAM_VAL16))
2444	return VERR_EM_INTERPRETER;
2445	sel = (RTSEL)param1.val.val16;
2446	break;
2447
2448	default:
2449	return VERR_EM_INTERPRETER;
2450	}
2451
2452	#ifdef IN_RING0
2453	/* Only for the VT-x real-mode emulation case. */
2454	AssertReturn(CPUMIsGuestInRealMode(pVCpu), VERR_EM_INTERPRETER);
2455	CPUMSetGuestLDTR(pVCpu, sel);
2456	return VINF_SUCCESS;
2457	#else
2458	if (sel == 0)
2459	{
2460	if (CPUMGetHyperLDTR(pVCpu) == 0)
2461	{
2462	// this simple case is most frequent in Windows 2000 (31k - boot & shutdown)
2463	return VINF_SUCCESS;
2464	}
2465	}
2466	//still feeling lazy
2467	return VERR_EM_INTERPRETER;
2468	#endif
2469	}
2470
2471	#ifdef IN_RING0
2472	/**
2473	* LIDT/LGDT Emulation.
2474	*/
2475	static int emInterpretLIGdt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2476	{
2477	OP_PARAMVAL param1;
2478	RTGCPTR pParam1;
2479	X86XDTR32 dtr32;
2480
2481	Log(("Emulate %s at %RGv\n", emGetMnemonic(pDISState), (RTGCPTR)pRegFrame->rip));
2482
2483	/* Only for the VT-x real-mode emulation case. */
2484	AssertReturn(CPUMIsGuestInRealMode(pVCpu), VERR_EM_INTERPRETER);
2485
2486	int rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param1, &param1, PARAM_SOURCE);
2487	if(RT_FAILURE(rc))
2488	return VERR_EM_INTERPRETER;
2489
2490	switch(param1.type)
2491	{
2492	case PARMTYPE_ADDRESS:
2493	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDISState, &pDISState->param1, param1.val.val16);
2494	break;
2495
2496	default:
2497	return VERR_EM_INTERPRETER;
2498	}
2499
2500	rc = emRamRead(pVM, pVCpu, pRegFrame, &dtr32, pParam1, sizeof(dtr32));
2501	AssertRCReturn(rc, VERR_EM_INTERPRETER);
2502
2503	if (!(pDISState->prefix & PREFIX_OPSIZE))
2504	dtr32.uAddr &= 0xffffff; /* 16 bits operand size */
2505
2506	if (pDISState->pCurInstr->opcode == OP_LIDT)
2507	CPUMSetGuestIDTR(pVCpu, dtr32.uAddr, dtr32.cb);
2508	else
2509	CPUMSetGuestGDTR(pVCpu, dtr32.uAddr, dtr32.cb);
2510
2511	return VINF_SUCCESS;
2512	}
2513	#endif
2514
2515
2516	#ifdef IN_RC
2517	/**
2518	* STI Emulation.
2519	*
2520	* @remark the instruction following sti is guaranteed to be executed before any interrupts are dispatched
2521	*/
2522	static int emInterpretSti(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2523	{
2524	PPATMGCSTATE pGCState = PATMQueryGCState(pVM);
2525
2526	if(!pGCState)
2527	{
2528	Assert(pGCState);
2529	return VERR_EM_INTERPRETER;
2530	}
2531	pGCState->uVMFlags \|= X86_EFL_IF;
2532
2533	Assert(pRegFrame->eflags.u32 & X86_EFL_IF);
2534	Assert(pvFault == SELMToFlat(pVM, DIS_SELREG_CS, pRegFrame, (RTGCPTR)pRegFrame->rip));
2535
2536	pVCpu->em.s.GCPtrInhibitInterrupts = pRegFrame->eip + pDISState->opsize;
2537	VMCPU_FF_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2538
2539	return VINF_SUCCESS;
2540	}
2541	#endif /* IN_RC */
2542
2543
2544	/**
2545	* HLT Emulation.
2546	*/
2547	static int emInterpretHlt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2548	{
2549	return VINF_EM_HALT;
2550	}
2551
2552
2553	/**
2554	* Interpret RDTSC
2555	*
2556	* @returns VBox status code.
2557	* @param pVM The VM handle.
2558	* @param pVCpu The VMCPU handle.
2559	* @param pRegFrame The register frame.
2560	*
2561	*/
2562	VMMDECL(int) EMInterpretRdtsc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
2563	{
2564	unsigned uCR4 = CPUMGetGuestCR4(pVCpu);
2565
2566	if (uCR4 & X86_CR4_TSD)
2567	return VERR_EM_INTERPRETER; /* genuine #GP */
2568
2569	uint64_t uTicks = TMCpuTickGet(pVCpu);
2570
2571	/* Same behaviour in 32 & 64 bits mode */
2572	pRegFrame->rax = (uint32_t)uTicks;
2573	pRegFrame->rdx = (uTicks >> 32ULL);
2574
2575	return VINF_SUCCESS;
2576	}
2577
2578	/**
2579	* Interpret RDTSCP
2580	*
2581	* @returns VBox status code.
2582	* @param pVM The VM handle.
2583	* @param pVCpu The VMCPU handle.
2584	* @param pCtx The CPU context.
2585	*
2586	*/
2587	VMMDECL(int) EMInterpretRdtscp(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2588	{
2589	unsigned uCR4 = CPUMGetGuestCR4(pVCpu);
2590
2591	if (!CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
2592	{
2593	AssertFailed();
2594	return VERR_EM_INTERPRETER; /* genuine #UD */
2595	}
2596
2597	if (uCR4 & X86_CR4_TSD)
2598	return VERR_EM_INTERPRETER; /* genuine #GP */
2599
2600	uint64_t uTicks = TMCpuTickGet(pVCpu);
2601
2602	/* Same behaviour in 32 & 64 bits mode */
2603	pCtx->rax = (uint32_t)uTicks;
2604	pCtx->rdx = (uTicks >> 32ULL);
2605	/* Low dword of the TSC_AUX msr only. */
2606	pCtx->rcx = (uint32_t)CPUMGetGuestMsr(pVCpu, MSR_K8_TSC_AUX);
2607
2608	return VINF_SUCCESS;
2609	}
2610
2611	/**
2612	* RDTSC Emulation.
2613	*/
2614	static int emInterpretRdtsc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2615	{
2616	return EMInterpretRdtsc(pVM, pVCpu, pRegFrame);
2617	}
2618
2619	/**
2620	* Interpret RDPMC
2621	*
2622	* @returns VBox status code.
2623	* @param pVM The VM handle.
2624	* @param pVCpu The VMCPU handle.
2625	* @param pRegFrame The register frame.
2626	*
2627	*/
2628	VMMDECL(int) EMInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
2629	{
2630	unsigned uCR4 = CPUMGetGuestCR4(pVCpu);
2631
2632	/* If X86_CR4_PCE is not set, then CPL must be zero. */
2633	if ( !(uCR4 & X86_CR4_PCE)
2634	&& CPUMGetGuestCPL(pVCpu, pRegFrame) != 0)
2635	{
2636	Assert(CPUMGetGuestCR0(pVCpu) & X86_CR0_PE);
2637	return VERR_EM_INTERPRETER; /* genuine #GP */
2638	}
2639
2640	/* Just return zero here; rather tricky to properly emulate this, especially as the specs are a mess. */
2641	pRegFrame->rax = 0;
2642	pRegFrame->rdx = 0;
2643	/* @todo We should trigger a #GP here if the cpu doesn't support the index in ecx. */
2644	return VINF_SUCCESS;
2645	}
2646
2647	/**
2648	* RDPMC Emulation
2649	*/
2650	static int emInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2651	{
2652	return EMInterpretRdpmc(pVM, pVCpu, pRegFrame);
2653	}
2654
2655	/**
2656	* MONITOR Emulation.
2657	*/
2658	static int emInterpretMonitor(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2659	{
2660	uint32_t u32Dummy, u32ExtFeatures, cpl;
2661
2662	Assert(pDISState->mode != CPUMODE_64BIT); /** @todo check */
2663	if (pRegFrame->ecx != 0)
2664	return VERR_EM_INTERPRETER; /* illegal value. */
2665
2666	/* Get the current privilege level. */
2667	cpl = CPUMGetGuestCPL(pVCpu, pRegFrame);
2668	if (cpl != 0)
2669	return VERR_EM_INTERPRETER; /* supervisor only */
2670
2671	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
2672	if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
2673	return VERR_EM_INTERPRETER; /* not supported */
2674
2675	return VINF_SUCCESS;
2676	}
2677
2678
2679	/**
2680	* MWAIT Emulation.
2681	*/
2682	VMMDECL(int) EMInterpretMWait(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
2683	{
2684	uint32_t u32Dummy, u32ExtFeatures, cpl;
2685
2686	/* @todo bit 1 is supposed to tell the cpu to wake us up on interrupts even if IF is cleared.
2687	* Not sure which models. Intel docs say ecx and eax must be zero for Pentium 4 CPUs
2688	* CPUID.05H.ECX[0] defines support for power management extensions (eax)
2689	*/
2690	if (pRegFrame->ecx != 0)
2691	return VERR_EM_INTERPRETER; /* illegal value. */
2692
2693	/* Get the current privilege level. */
2694	cpl = CPUMGetGuestCPL(pVCpu, pRegFrame);
2695	if (cpl != 0)
2696	return VERR_EM_INTERPRETER; /* supervisor only */
2697
2698	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
2699	if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
2700	return VERR_EM_INTERPRETER; /* not supported */
2701
2702	/** @todo not completely correct */
2703	return VINF_EM_HALT;
2704	}
2705
2706	static int emInterpretMWait(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2707	{
2708	Assert(pDISState->mode != CPUMODE_64BIT); /** @todo check */
2709
2710	return EMInterpretMWait(pVM, pVCpu, pRegFrame);
2711	}
2712
2713
2714	#ifdef LOG_ENABLED
2715	static const char *emMSRtoString(uint32_t uMsr)
2716	{
2717	switch (uMsr)
2718	{
2719	case MSR_IA32_APICBASE:
2720	return "MSR_IA32_APICBASE";
2721	case MSR_IA32_CR_PAT:
2722	return "MSR_IA32_CR_PAT";
2723	case MSR_IA32_SYSENTER_CS:
2724	return "MSR_IA32_SYSENTER_CS";
2725	case MSR_IA32_SYSENTER_EIP:
2726	return "MSR_IA32_SYSENTER_EIP";
2727	case MSR_IA32_SYSENTER_ESP:
2728	return "MSR_IA32_SYSENTER_ESP";
2729	case MSR_K6_EFER:
2730	return "MSR_K6_EFER";
2731	case MSR_K8_SF_MASK:
2732	return "MSR_K8_SF_MASK";
2733	case MSR_K6_STAR:
2734	return "MSR_K6_STAR";
2735	case MSR_K8_LSTAR:
2736	return "MSR_K8_LSTAR";
2737	case MSR_K8_CSTAR:
2738	return "MSR_K8_CSTAR";
2739	case MSR_K8_FS_BASE:
2740	return "MSR_K8_FS_BASE";
2741	case MSR_K8_GS_BASE:
2742	return "MSR_K8_GS_BASE";
2743	case MSR_K8_KERNEL_GS_BASE:
2744	return "MSR_K8_KERNEL_GS_BASE";
2745	case MSR_K8_TSC_AUX:
2746	return "MSR_K8_TSC_AUX";
2747	case MSR_IA32_BIOS_SIGN_ID:
2748	return "Unsupported MSR_IA32_BIOS_SIGN_ID";
2749	case MSR_IA32_PLATFORM_ID:
2750	return "Unsupported MSR_IA32_PLATFORM_ID";
2751	case MSR_IA32_BIOS_UPDT_TRIG:
2752	return "Unsupported MSR_IA32_BIOS_UPDT_TRIG";
2753	case MSR_IA32_TSC:
2754	return "MSR_IA32_TSC";
2755	case MSR_IA32_MTRR_CAP:
2756	return "Unsupported MSR_IA32_MTRR_CAP";
2757	case MSR_IA32_MCP_CAP:
2758	return "Unsupported MSR_IA32_MCP_CAP";
2759	case MSR_IA32_MCP_STATUS:
2760	return "Unsupported MSR_IA32_MCP_STATUS";
2761	case MSR_IA32_MCP_CTRL:
2762	return "Unsupported MSR_IA32_MCP_CTRL";
2763	case MSR_IA32_MTRR_DEF_TYPE:
2764	return "Unsupported MSR_IA32_MTRR_DEF_TYPE";
2765	case MSR_K7_EVNTSEL0:
2766	return "Unsupported MSR_K7_EVNTSEL0";
2767	case MSR_K7_EVNTSEL1:
2768	return "Unsupported MSR_K7_EVNTSEL1";
2769	case MSR_K7_EVNTSEL2:
2770	return "Unsupported MSR_K7_EVNTSEL2";
2771	case MSR_K7_EVNTSEL3:
2772	return "Unsupported MSR_K7_EVNTSEL3";
2773	case MSR_IA32_MC0_CTL:
2774	return "Unsupported MSR_IA32_MC0_CTL";
2775	case MSR_IA32_MC0_STATUS:
2776	return "Unsupported MSR_IA32_MC0_STATUS";
2777	case MSR_IA32_PERFEVTSEL0:
2778	return "Unsupported MSR_IA32_PERFEVTSEL0";
2779	case MSR_IA32_PERFEVTSEL1:
2780	return "Unsupported MSR_IA32_PERFEVTSEL1";
2781	case MSR_IA32_PERF_STATUS:
2782	return "Unsupported MSR_IA32_PERF_STATUS";
2783	case MSR_IA32_PERF_CTL:
2784	return "Unsupported MSR_IA32_PERF_CTL";
2785	}
2786	return "Unknown MSR";
2787	}
2788	#endif /* LOG_ENABLED */
2789
2790
2791	/**
2792	* Interpret RDMSR
2793	*
2794	* @returns VBox status code.
2795	* @param pVM The VM handle.
2796	* @param pVCpu The VMCPU handle.
2797	* @param pRegFrame The register frame.
2798	*
2799	*/
2800	VMMDECL(int) EMInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
2801	{
2802	uint32_t u32Dummy, u32Features, cpl;
2803	uint64_t val;
2804	CPUMCTX *pCtx;
2805	int rc = VINF_SUCCESS;
2806
2807	/** @todo According to the Intel manuals, there's a REX version of RDMSR that is slightly different.
2808	* That version clears the high dwords of both RDX & RAX */
2809	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2810
2811	/* Get the current privilege level. */
2812	cpl = CPUMGetGuestCPL(pVCpu, pRegFrame);
2813	if (cpl != 0)
2814	return VERR_EM_INTERPRETER; /* supervisor only */
2815
2816	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2817	if (!(u32Features & X86_CPUID_FEATURE_EDX_MSR))
2818	return VERR_EM_INTERPRETER; /* not supported */
2819
2820	switch (pRegFrame->ecx)
2821	{
2822	case MSR_IA32_TSC:
2823	val = TMCpuTickGet(pVCpu);
2824	break;
2825
2826	case MSR_IA32_APICBASE:
2827	rc = PDMApicGetBase(pVM, &val);
2828	AssertRC(rc);
2829	break;
2830
2831	case MSR_IA32_CR_PAT:
2832	val = pCtx->msrPAT;
2833	break;
2834
2835	case MSR_IA32_SYSENTER_CS:
2836	val = pCtx->SysEnter.cs;
2837	break;
2838
2839	case MSR_IA32_SYSENTER_EIP:
2840	val = pCtx->SysEnter.eip;
2841	break;
2842
2843	case MSR_IA32_SYSENTER_ESP:
2844	val = pCtx->SysEnter.esp;
2845	break;
2846
2847	case MSR_K6_EFER:
2848	val = pCtx->msrEFER;
2849	break;
2850
2851	case MSR_K8_SF_MASK:
2852	val = pCtx->msrSFMASK;
2853	break;
2854
2855	case MSR_K6_STAR:
2856	val = pCtx->msrSTAR;
2857	break;
2858
2859	case MSR_K8_LSTAR:
2860	val = pCtx->msrLSTAR;
2861	break;
2862
2863	case MSR_K8_CSTAR:
2864	val = pCtx->msrCSTAR;
2865	break;
2866
2867	case MSR_K8_FS_BASE:
2868	val = pCtx->fsHid.u64Base;
2869	break;
2870
2871	case MSR_K8_GS_BASE:
2872	val = pCtx->gsHid.u64Base;
2873	break;
2874
2875	case MSR_K8_KERNEL_GS_BASE:
2876	val = pCtx->msrKERNELGSBASE;
2877	break;
2878
2879	case MSR_K8_TSC_AUX:
2880	val = CPUMGetGuestMsr(pVCpu, MSR_K8_TSC_AUX);
2881	break;
2882
2883	#if 0 /def IN_RING0 /
2884	case MSR_IA32_PLATFORM_ID:
2885	case MSR_IA32_BIOS_SIGN_ID:
2886	if (CPUMGetCPUVendor(pVM) == CPUMCPUVENDOR_INTEL)
2887	{
2888	/* Available since the P6 family. VT-x implies that this feature is present. */
2889	if (pRegFrame->ecx == MSR_IA32_PLATFORM_ID)
2890	val = ASMRdMsr(MSR_IA32_PLATFORM_ID);
2891	else
2892	if (pRegFrame->ecx == MSR_IA32_BIOS_SIGN_ID)
2893	val = ASMRdMsr(MSR_IA32_BIOS_SIGN_ID);
2894	break;
2895	}
2896	/* no break */
2897	#endif
2898	default:
2899	/* In X2APIC specification this range is reserved for APIC control. */
2900	if ((pRegFrame->ecx >= MSR_IA32_APIC_START) && (pRegFrame->ecx < MSR_IA32_APIC_END))
2901	rc = PDMApicReadMSR(pVM, pVCpu->idCpu, pRegFrame->ecx, &val);
2902	else
2903	/* We should actually trigger a #GP here, but don't as that will cause more trouble. */
2904	val = 0;
2905	break;
2906	}
2907	LogFlow(("EMInterpretRdmsr %s (%x) -> val=%RX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx, val));
2908	if (rc == VINF_SUCCESS)
2909	{
2910	pRegFrame->rax = (uint32_t) val;
2911	pRegFrame->rdx = (uint32_t) (val >> 32ULL);
2912	}
2913	return rc;
2914	}
2915
2916
2917	/**
2918	* RDMSR Emulation.
2919	*/
2920	static int emInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2921	{
2922	/* Note: the Intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
2923	Assert(!(pDISState->prefix & PREFIX_REX));
2924	return EMInterpretRdmsr(pVM, pVCpu, pRegFrame);
2925	}
2926
2927
2928	/**
2929	* Interpret WRMSR
2930	*
2931	* @returns VBox status code.
2932	* @param pVM The VM handle.
2933	* @param pVCpu The VMCPU handle.
2934	* @param pRegFrame The register frame.
2935	*/
2936	VMMDECL(int) EMInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
2937	{
2938	uint32_t u32Dummy, u32Features, cpl;
2939	uint64_t val;
2940	CPUMCTX *pCtx;
2941
2942	/* Note: works the same in 32 and 64 bits modes. */
2943	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2944
2945	/* Get the current privilege level. */
2946	cpl = CPUMGetGuestCPL(pVCpu, pRegFrame);
2947	if (cpl != 0)
2948	return VERR_EM_INTERPRETER; /* supervisor only */
2949
2950	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2951	if (!(u32Features & X86_CPUID_FEATURE_EDX_MSR))
2952	return VERR_EM_INTERPRETER; /* not supported */
2953
2954	val = RT_MAKE_U64(pRegFrame->eax, pRegFrame->edx);
2955	LogFlow(("EMInterpretWrmsr %s (%x) val=%RX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx, val));
2956	switch (pRegFrame->ecx)
2957	{
2958	case MSR_IA32_APICBASE:
2959	{
2960	int rc = PDMApicSetBase(pVM, val);
2961	AssertRC(rc);
2962	break;
2963	}
2964
2965	case MSR_IA32_CR_PAT:
2966	pCtx->msrPAT = val;
2967	break;
2968
2969	case MSR_IA32_SYSENTER_CS:
2970	pCtx->SysEnter.cs = val & 0xffff; /* 16 bits selector */
2971	break;
2972
2973	case MSR_IA32_SYSENTER_EIP:
2974	pCtx->SysEnter.eip = val;
2975	break;
2976
2977	case MSR_IA32_SYSENTER_ESP:
2978	pCtx->SysEnter.esp = val;
2979	break;
2980
2981	case MSR_K6_EFER:
2982	{
2983	uint64_t uMask = 0;
2984	uint64_t oldval = pCtx->msrEFER;
2985
2986	/* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
2987	CPUMGetGuestCpuId(pVCpu, 0x80000001, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2988	if (u32Features & X86_CPUID_AMD_FEATURE_EDX_NX)
2989	uMask \|= MSR_K6_EFER_NXE;
2990	if (u32Features & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE)
2991	uMask \|= MSR_K6_EFER_LME;
2992	if (u32Features & X86_CPUID_AMD_FEATURE_EDX_SEP)
2993	uMask \|= MSR_K6_EFER_SCE;
2994	if (u32Features & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
2995	uMask \|= MSR_K6_EFER_FFXSR;
2996
2997	/* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
2998	if ( ((pCtx->msrEFER & MSR_K6_EFER_LME) != (val & uMask & MSR_K6_EFER_LME))
2999	&& (pCtx->cr0 & X86_CR0_PG))
3000	{
3001	AssertMsgFailed(("Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
3002	return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
3003	}
3004
3005	/* There are a few more: e.g. MSR_K6_EFER_LMSLE */
3006	AssertMsg(!(val & ~(MSR_K6_EFER_NXE\|MSR_K6_EFER_LME\|MSR_K6_EFER_LMA /* ignored anyway */ \|MSR_K6_EFER_SCE\|MSR_K6_EFER_FFXSR)), ("Unexpected value %RX64\n", val));
3007	pCtx->msrEFER = (pCtx->msrEFER & ~uMask) \| (val & uMask);
3008
3009	/* AMD64 Architecture Programmer's Manual: 15.15 TLB Control; flush the TLB if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
3010	if ((oldval & (MSR_K6_EFER_NXE\|MSR_K6_EFER_LME\|MSR_K6_EFER_LMA)) != (pCtx->msrEFER & (MSR_K6_EFER_NXE\|MSR_K6_EFER_LME\|MSR_K6_EFER_LMA)))
3011	HWACCMFlushTLB(pVCpu);
3012
3013	break;
3014	}
3015
3016	case MSR_K8_SF_MASK:
3017	pCtx->msrSFMASK = val;
3018	break;
3019
3020	case MSR_K6_STAR:
3021	pCtx->msrSTAR = val;
3022	break;
3023
3024	case MSR_K8_LSTAR:
3025	pCtx->msrLSTAR = val;
3026	break;
3027
3028	case MSR_K8_CSTAR:
3029	pCtx->msrCSTAR = val;
3030	break;
3031
3032	case MSR_K8_FS_BASE:
3033	pCtx->fsHid.u64Base = val;
3034	break;
3035
3036	case MSR_K8_GS_BASE:
3037	pCtx->gsHid.u64Base = val;
3038	break;
3039
3040	case MSR_K8_KERNEL_GS_BASE:
3041	pCtx->msrKERNELGSBASE = val;
3042	break;
3043
3044	case MSR_K8_TSC_AUX:
3045	CPUMSetGuestMsr(pVCpu, MSR_K8_TSC_AUX, val);
3046	break;
3047
3048	default:
3049	/* In X2APIC specification this range is reserved for APIC control. */
3050	if ((pRegFrame->ecx >= MSR_IA32_APIC_START) && (pRegFrame->ecx < MSR_IA32_APIC_END))
3051	return PDMApicWriteMSR(pVM, pVCpu->idCpu, pRegFrame->ecx, val);
3052
3053	/* We should actually trigger a #GP here, but don't as that might cause more trouble. */
3054	break;
3055	}
3056	return VINF_SUCCESS;
3057	}
3058
3059
3060	/**
3061	* WRMSR Emulation.
3062	*/
3063	static int emInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3064	{
3065	return EMInterpretWrmsr(pVM, pVCpu, pRegFrame);
3066	}
3067
3068
3069	/**
3070	* Internal worker.
3071	* @copydoc EMInterpretInstructionCPU
3072	*/
3073	DECLINLINE(int) emInterpretInstructionCPU(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3074	{
3075	Assert(pcbSize);
3076	*pcbSize = 0;
3077
3078	/*
3079	* Only supervisor guest code!!
3080	* And no complicated prefixes.
3081	*/
3082	/* Get the current privilege level. */
3083	uint32_t cpl = CPUMGetGuestCPL(pVCpu, pRegFrame);
3084	if ( cpl != 0
3085	&& pDISState->pCurInstr->opcode != OP_RDTSC) /* rdtsc requires emulation in ring 3 as well */
3086	{
3087	Log(("WARNING: refusing instruction emulation for user-mode code!!\n"));
3088	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedUserMode));
3089	return VERR_EM_INTERPRETER;
3090	}
3091
3092	#ifdef IN_RC
3093	if ( (pDISState->prefix & (PREFIX_REPNE \| PREFIX_REP))
3094	\|\| ( (pDISState->prefix & PREFIX_LOCK)
3095	&& pDISState->pCurInstr->opcode != OP_CMPXCHG
3096	&& pDISState->pCurInstr->opcode != OP_CMPXCHG8B
3097	&& pDISState->pCurInstr->opcode != OP_XADD
3098	&& pDISState->pCurInstr->opcode != OP_OR
3099	&& pDISState->pCurInstr->opcode != OP_BTR
3100	)
3101	)
3102	#else
3103	if ( (pDISState->prefix & PREFIX_REPNE)
3104	\|\| ( (pDISState->prefix & PREFIX_REP)
3105	&& pDISState->pCurInstr->opcode != OP_STOSWD
3106	)
3107	\|\| ( (pDISState->prefix & PREFIX_LOCK)
3108	&& pDISState->pCurInstr->opcode != OP_OR
3109	&& pDISState->pCurInstr->opcode != OP_BTR
3110	&& pDISState->pCurInstr->opcode != OP_CMPXCHG
3111	&& pDISState->pCurInstr->opcode != OP_CMPXCHG8B
3112	)
3113	)
3114	#endif
3115	{
3116	//Log(("EMInterpretInstruction: wrong prefix!!\n"));
3117	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedPrefix));
3118	return VERR_EM_INTERPRETER;
3119	}
3120
3121	#if HC_ARCH_BITS == 32
3122	/*
3123	* Unable to emulate most >4 bytes accesses in 32 bits mode.
3124	* Whitelisted instructions are safe.
3125	*/
3126	if ( pDISState->param1.size > 4
3127	&& CPUMIsGuestIn64BitCode(pVCpu, pRegFrame))
3128	{
3129	uint32_t uOpCode = pDISState->pCurInstr->opcode;
3130	if ( uOpCode != OP_STOSWD
3131	&& uOpCode != OP_MOV
3132	&& uOpCode != OP_CMPXCHG8B
3133	&& uOpCode != OP_XCHG
3134	&& uOpCode != OP_BTS
3135	&& uOpCode != OP_BTR
3136	&& uOpCode != OP_BTC
3137	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL_IN_R0
3138	&& uOpCode != OP_CMPXCHG /* solaris */
3139	&& uOpCode != OP_AND /* windows */
3140	&& uOpCode != OP_OR /* windows */
3141	&& uOpCode != OP_XOR /* because we can */
3142	&& uOpCode != OP_ADD /* windows (dripple) */
3143	&& uOpCode != OP_ADC /* because we can */
3144	&& uOpCode != OP_SUB /* because we can */
3145	/** @todo OP_BTS or is that a different kind of failure? */
3146	# endif
3147	)
3148	{
3149	# ifdef VBOX_WITH_STATISTICS
3150	switch (pDISState->pCurInstr->opcode)
3151	{
3152	# define INTERPRET_FAILED_CASE(opcode, Instr) \
3153	case opcode: STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); break;
3154	INTERPRET_FAILED_CASE(OP_XCHG,Xchg);
3155	INTERPRET_FAILED_CASE(OP_DEC,Dec);
3156	INTERPRET_FAILED_CASE(OP_INC,Inc);
3157	INTERPRET_FAILED_CASE(OP_POP,Pop);
3158	INTERPRET_FAILED_CASE(OP_OR, Or);
3159	INTERPRET_FAILED_CASE(OP_XOR,Xor);
3160	INTERPRET_FAILED_CASE(OP_AND,And);
3161	INTERPRET_FAILED_CASE(OP_MOV,Mov);
3162	INTERPRET_FAILED_CASE(OP_STOSWD,StosWD);
3163	INTERPRET_FAILED_CASE(OP_INVLPG,InvlPg);
3164	INTERPRET_FAILED_CASE(OP_CPUID,CpuId);
3165	INTERPRET_FAILED_CASE(OP_MOV_CR,MovCRx);
3166	INTERPRET_FAILED_CASE(OP_MOV_DR,MovDRx);
3167	INTERPRET_FAILED_CASE(OP_LLDT,LLdt);
3168	INTERPRET_FAILED_CASE(OP_LIDT,LIdt);
3169	INTERPRET_FAILED_CASE(OP_LGDT,LGdt);
3170	INTERPRET_FAILED_CASE(OP_LMSW,Lmsw);
3171	INTERPRET_FAILED_CASE(OP_CLTS,Clts);
3172	INTERPRET_FAILED_CASE(OP_MONITOR,Monitor);
3173	INTERPRET_FAILED_CASE(OP_MWAIT,MWait);
3174	INTERPRET_FAILED_CASE(OP_RDMSR,Rdmsr);
3175	INTERPRET_FAILED_CASE(OP_WRMSR,Wrmsr);
3176	INTERPRET_FAILED_CASE(OP_ADD,Add);
3177	INTERPRET_FAILED_CASE(OP_SUB,Sub);
3178	INTERPRET_FAILED_CASE(OP_ADC,Adc);
3179	INTERPRET_FAILED_CASE(OP_BTR,Btr);
3180	INTERPRET_FAILED_CASE(OP_BTS,Bts);
3181	INTERPRET_FAILED_CASE(OP_BTC,Btc);
3182	INTERPRET_FAILED_CASE(OP_RDTSC,Rdtsc);
3183	INTERPRET_FAILED_CASE(OP_CMPXCHG, CmpXchg);
3184	INTERPRET_FAILED_CASE(OP_STI, Sti);
3185	INTERPRET_FAILED_CASE(OP_XADD,XAdd);
3186	INTERPRET_FAILED_CASE(OP_CMPXCHG8B,CmpXchg8b);
3187	INTERPRET_FAILED_CASE(OP_HLT, Hlt);
3188	INTERPRET_FAILED_CASE(OP_IRET,Iret);
3189	INTERPRET_FAILED_CASE(OP_WBINVD,WbInvd);
3190	INTERPRET_FAILED_CASE(OP_MOVNTPS,MovNTPS);
3191	# undef INTERPRET_FAILED_CASE
3192	default:
3193	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedMisc));
3194	break;
3195	}
3196	# endif /* VBOX_WITH_STATISTICS */
3197	return VERR_EM_INTERPRETER;
3198	}
3199	}
3200	#endif
3201
3202	int rc;
3203	#if (defined(VBOX_STRICT) \|\| defined(LOG_ENABLED))
3204	LogFlow(("emInterpretInstructionCPU %s\n", emGetMnemonic(pDISState)));
3205	#endif
3206	switch (pDISState->pCurInstr->opcode)
3207	{
3208	/*
3209	* Macros for generating the right case statements.
3210	*/
3211	# define INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
3212	case opcode:\
3213	if (pDISState->prefix & PREFIX_LOCK) \
3214	rc = emInterpretLock##InstrFn(pVM, pVCpu, pDISState, pRegFrame, pvFault, pcbSize, pfnEmulateLock); \
3215	else \
3216	rc = emInterpret##InstrFn(pVM, pVCpu, pDISState, pRegFrame, pvFault, pcbSize, pfnEmulate); \
3217	if (RT_SUCCESS(rc)) \
3218	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3219	else \
3220	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3221	return rc
3222	#define INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate) \
3223	case opcode:\
3224	rc = emInterpret##InstrFn(pVM, pVCpu, pDISState, pRegFrame, pvFault, pcbSize, pfnEmulate); \
3225	if (RT_SUCCESS(rc)) \
3226	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3227	else \
3228	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3229	return rc
3230
3231	#define INTERPRET_CASE_EX_PARAM2(opcode, Instr, InstrFn, pfnEmulate) \
3232	INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate)
3233	#define INTERPRET_CASE_EX_LOCK_PARAM2(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
3234	INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock)
3235
3236	#define INTERPRET_CASE(opcode, Instr) \
3237	case opcode:\
3238	rc = emInterpret##Instr(pVM, pVCpu, pDISState, pRegFrame, pvFault, pcbSize); \
3239	if (RT_SUCCESS(rc)) \
3240	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3241	else \
3242	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3243	return rc
3244
3245	#define INTERPRET_CASE_EX_DUAL_PARAM2(opcode, Instr, InstrFn) \
3246	case opcode:\
3247	rc = emInterpret##InstrFn(pVM, pVCpu, pDISState, pRegFrame, pvFault, pcbSize); \
3248	if (RT_SUCCESS(rc)) \
3249	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3250	else \
3251	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3252	return rc
3253
3254	#define INTERPRET_STAT_CASE(opcode, Instr) \
3255	case opcode: STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); return VERR_EM_INTERPRETER;
3256
3257	/*
3258	* The actual case statements.
3259	*/
3260	INTERPRET_CASE(OP_XCHG,Xchg);
3261	INTERPRET_CASE_EX_PARAM2(OP_DEC,Dec, IncDec, EMEmulateDec);
3262	INTERPRET_CASE_EX_PARAM2(OP_INC,Inc, IncDec, EMEmulateInc);
3263	INTERPRET_CASE(OP_POP,Pop);
3264	INTERPRET_CASE_EX_LOCK_PARAM3(OP_OR, Or, OrXorAnd, EMEmulateOr, EMEmulateLockOr);
3265	INTERPRET_CASE_EX_PARAM3(OP_XOR,Xor, OrXorAnd, EMEmulateXor);
3266	INTERPRET_CASE_EX_PARAM3(OP_AND,And, OrXorAnd, EMEmulateAnd);
3267	INTERPRET_CASE(OP_MOV,Mov);
3268	#ifndef IN_RC
3269	INTERPRET_CASE(OP_STOSWD,StosWD);
3270	#endif
3271	INTERPRET_CASE(OP_INVLPG,InvlPg);
3272	INTERPRET_CASE(OP_CPUID,CpuId);
3273	INTERPRET_CASE(OP_MOV_CR,MovCRx);
3274	INTERPRET_CASE(OP_MOV_DR,MovDRx);
3275	#ifdef IN_RING0
3276	INTERPRET_CASE_EX_DUAL_PARAM2(OP_LIDT, LIdt, LIGdt);
3277	INTERPRET_CASE_EX_DUAL_PARAM2(OP_LGDT, LGdt, LIGdt);
3278	#endif
3279	INTERPRET_CASE(OP_LLDT,LLdt);
3280	INTERPRET_CASE(OP_LMSW,Lmsw);
3281	#ifdef EM_EMULATE_SMSW
3282	INTERPRET_CASE(OP_SMSW,Smsw);
3283	#endif
3284	INTERPRET_CASE(OP_CLTS,Clts);
3285	INTERPRET_CASE(OP_MONITOR, Monitor);
3286	INTERPRET_CASE(OP_MWAIT, MWait);
3287	INTERPRET_CASE(OP_RDMSR, Rdmsr);
3288	INTERPRET_CASE(OP_WRMSR, Wrmsr);
3289	INTERPRET_CASE_EX_PARAM3(OP_ADD,Add, AddSub, EMEmulateAdd);
3290	INTERPRET_CASE_EX_PARAM3(OP_SUB,Sub, AddSub, EMEmulateSub);
3291	INTERPRET_CASE(OP_ADC,Adc);
3292	INTERPRET_CASE_EX_LOCK_PARAM2(OP_BTR,Btr, BitTest, EMEmulateBtr, EMEmulateLockBtr);
3293	INTERPRET_CASE_EX_PARAM2(OP_BTS,Bts, BitTest, EMEmulateBts);
3294	INTERPRET_CASE_EX_PARAM2(OP_BTC,Btc, BitTest, EMEmulateBtc);
3295	INTERPRET_CASE(OP_RDPMC,Rdpmc);
3296	INTERPRET_CASE(OP_RDTSC,Rdtsc);
3297	INTERPRET_CASE(OP_CMPXCHG, CmpXchg);
3298	#ifdef IN_RC
3299	INTERPRET_CASE(OP_STI,Sti);
3300	INTERPRET_CASE(OP_XADD, XAdd);
3301	#endif
3302	INTERPRET_CASE(OP_CMPXCHG8B, CmpXchg8b);
3303	INTERPRET_CASE(OP_HLT,Hlt);
3304	INTERPRET_CASE(OP_IRET,Iret);
3305	INTERPRET_CASE(OP_WBINVD,WbInvd);
3306	#ifdef VBOX_WITH_STATISTICS
3307	# ifndef IN_RC
3308	INTERPRET_STAT_CASE(OP_XADD, XAdd);
3309	# endif
3310	INTERPRET_STAT_CASE(OP_MOVNTPS,MovNTPS);
3311	#endif
3312
3313	default:
3314	Log3(("emInterpretInstructionCPU: opcode=%d\n", pDISState->pCurInstr->opcode));
3315	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedMisc));
3316	return VERR_EM_INTERPRETER;
3317
3318	#undef INTERPRET_CASE_EX_PARAM2
3319	#undef INTERPRET_STAT_CASE
3320	#undef INTERPRET_CASE_EX
3321	#undef INTERPRET_CASE
3322	} /* switch (opcode) */
3323	AssertFailed();
3324	return VERR_INTERNAL_ERROR;
3325	}
3326
3327
3328	/**
3329	* Sets the PC for which interrupts should be inhibited.
3330	*
3331	* @param pVCpu The VMCPU handle.
3332	* @param PC The PC.
3333	*/
3334	VMMDECL(void) EMSetInhibitInterruptsPC(PVMCPU pVCpu, RTGCUINTPTR PC)
3335	{
3336	pVCpu->em.s.GCPtrInhibitInterrupts = PC;
3337	VMCPU_FF_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
3338	}
3339
3340
3341	/**
3342	* Gets the PC for which interrupts should be inhibited.
3343	*
3344	* There are a few instructions which inhibits or delays interrupts
3345	* for the instruction following them. These instructions are:
3346	* - STI
3347	* - MOV SS, r/m16
3348	* - POP SS
3349	*
3350	* @returns The PC for which interrupts should be inhibited.
3351	* @param pVCpu The VMCPU handle.
3352	*
3353	*/
3354	VMMDECL(RTGCUINTPTR) EMGetInhibitInterruptsPC(PVMCPU pVCpu)
3355	{
3356	return pVCpu->em.s.GCPtrInhibitInterrupts;
3357	}
3358

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source: vbox/trunk/src/VBox/VMM/VMMAll/EMAll.cpp@ 20406

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